[PATCH 0/5] *** phyCORE-AM62x: DDR detection / Inject DDR timing deltas ***
PHYTEC stores details about the hardware in an EEPROM on the SoM. We can utilize this information and chose the proper DDR timings accordingly.
Due to the limited SRAM memory on the AM62x, the concept was to store only the DDR timings deltas and not their full set, see Patch 4 & 5.
The last patch adds support for a 1 GB and 4 GB RAM variant of the phyCORE-AM62x.
Patch 4 & 5 are based on https://patchwork.ozlabs.org/project/uboot/list/?series=404273
Wadim Egorov (5): board: phytec: Make AM6 SoM detection depend on I2C board: phytec: Fix function definitions in AM6x SOM detection arm: mach-k3: am625: Call do_board_detect() before DDR probing board: phytec: common: Introduce a method to inject DDR timings deltas board: phytec: am62x: Add support for 1 & 4 GB RAM variants
arch/arm/mach-k3/am625_init.c | 2 + board/phytec/common/Kconfig | 2 + board/phytec/common/am6_som_detection.c | 18 +- board/phytec/common/am6_som_detection.h | 8 + board/phytec/common/k3/Makefile | 1 + board/phytec/common/k3/k3_ddrss_patch.c | 68 ++++++ board/phytec/common/k3/k3_ddrss_patch.h | 28 +++ board/phytec/phycore_am62x/MAINTAINERS | 1 + board/phytec/phycore_am62x/phycore-am62x.c | 152 ++++++++++++- board/phytec/phycore_am62x/phycore-ddr-data.h | 206 ++++++++++++++++++ configs/phycore_am62x_a53_defconfig | 4 + configs/phycore_am62x_r5_defconfig | 4 + 12 files changed, 483 insertions(+), 11 deletions(-) create mode 100644 board/phytec/common/k3/k3_ddrss_patch.c create mode 100644 board/phytec/common/k3/k3_ddrss_patch.h create mode 100644 board/phytec/phycore_am62x/phycore-ddr-data.h
SoM detection is using I2C driver model functions. Let's depend on I2C.
Signed-off-by: Wadim Egorov w.egorov@phytec.de --- board/phytec/common/Kconfig | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/board/phytec/common/Kconfig b/board/phytec/common/Kconfig index 1077f0f4b61..56c8290f641 100644 --- a/board/phytec/common/Kconfig +++ b/board/phytec/common/Kconfig @@ -16,6 +16,7 @@ config PHYTEC_AM62_SOM_DETECTION bool "Support SoM detection for AM62x PHYTEC platforms" depends on (TARGET_PHYCORE_AM62X_A53 || TARGET_PHYCORE_AM62X_R5) && \ PHYTEC_SOM_DETECTION + depends on SPL_I2C && DM_I2C default y help Support of I2C EEPROM based SoM detection. Supported @@ -25,6 +26,7 @@ config PHYTEC_AM64_SOM_DETECTION bool "Support SoM detection for AM64x PHYTEC platforms" depends on (TARGET_PHYCORE_AM64X_A53 || TARGET_PHYCORE_AM64X_R5) && \ PHYTEC_SOM_DETECTION + depends on SPL_I2C && DM_I2C default y help Support of I2C EEPROM based SoM detection. Supported
Functions are declared as phytec_am6* and not phytec_am62*. Update the definitions to match the declarations.
Fixes: 9d152c23279c ("board: phytec: Add SOM detection for AM6x")
Signed-off-by: Wadim Egorov w.egorov@phytec.de --- board/phytec/common/am6_som_detection.c | 18 +++++++++--------- 1 file changed, 9 insertions(+), 9 deletions(-)
diff --git a/board/phytec/common/am6_som_detection.c b/board/phytec/common/am6_som_detection.c index 2e9884dab44..7930ab42d1c 100644 --- a/board/phytec/common/am6_som_detection.c +++ b/board/phytec/common/am6_som_detection.c @@ -73,7 +73,7 @@ static u8 phytec_check_opt(struct phytec_eeprom_data *data, u8 option) * - The size * - PHYTEC_EEPROM_INVAL when the data is invalid. */ -u8 __maybe_unused phytec_get_am62_ddr_size(struct phytec_eeprom_data *data) +u8 __maybe_unused phytec_get_am6_ddr_size(struct phytec_eeprom_data *data) { u8 ddr_id = phytec_check_opt(data, 3);
@@ -89,7 +89,7 @@ u8 __maybe_unused phytec_get_am62_ddr_size(struct phytec_eeprom_data *data) * - Otherwise a board depended code for the size. * - PHYTEC_EEPROM_INVAL when the data is invalid. */ -u8 __maybe_unused phytec_get_am62_spi(struct phytec_eeprom_data *data) +u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data) { u8 spi = phytec_check_opt(data, 5);
@@ -105,7 +105,7 @@ u8 __maybe_unused phytec_get_am62_spi(struct phytec_eeprom_data *data) * - 0x1 if 10/100/1000 MBit Phy is populated. * - PHYTEC_EEPROM_INVAL when the data is invalid. */ -u8 __maybe_unused phytec_get_am62_eth(struct phytec_eeprom_data *data) +u8 __maybe_unused phytec_get_am6_eth(struct phytec_eeprom_data *data) { u8 eth = phytec_check_opt(data, 6);
@@ -121,7 +121,7 @@ u8 __maybe_unused phytec_get_am62_eth(struct phytec_eeprom_data *data) * - 1 if it is populated. * - PHYTEC_EEPROM_INVAL when the data is invalid. */ -u8 __maybe_unused phytec_get_am62_rtc(struct phytec_eeprom_data *data) +u8 __maybe_unused phytec_get_am6_rtc(struct phytec_eeprom_data *data) { u8 rtc = phytec_check_opt(data, 7);
@@ -131,28 +131,28 @@ u8 __maybe_unused phytec_get_am62_rtc(struct phytec_eeprom_data *data)
#else
-inline int __maybe_unused phytec_am62_detect(struct phytec_eeprom_data *data) +inline int __maybe_unused phytec_am6_detect(struct phytec_eeprom_data *data) { return -1; }
inline u8 __maybe_unused -phytec_get_am62_ddr_size(struct phytec_eeprom_data *data) +phytec_get_am6_ddr_size(struct phytec_eeprom_data *data) { return PHYTEC_EEPROM_INVAL; }
-inline u8 __maybe_unused phytec_get_am62_spi(struct phytec_eeprom_data *data) +inline u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data) { return PHYTEC_EEPROM_INVAL; }
-inline u8 __maybe_unused phytec_get_am62_eth(struct phytec_eeprom_data *data) +inline u8 __maybe_unused phytec_get_am6_eth(struct phytec_eeprom_data *data) { return PHYTEC_EEPROM_INVAL; }
-inline u8 __maybe_unused phytec_get_am62_rtc(struct phytec_eeprom_data *data) +inline u8 __maybe_unused phytec_get_am6_rtc(struct phytec_eeprom_data *data) { return PHYTEC_EEPROM_INVAL; }
Call do_board_detect() hook before the K3 DDRSS driver gets probed. It will allow boards to adjust DDR timings in do_board_detect().
Signed-off-by: Wadim Egorov w.egorov@phytec.de --- arch/arm/mach-k3/am625_init.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/mach-k3/am625_init.c b/arch/arm/mach-k3/am625_init.c index 668f9a51ef4..672de1c03de 100644 --- a/arch/arm/mach-k3/am625_init.c +++ b/arch/arm/mach-k3/am625_init.c @@ -212,6 +212,8 @@ void board_init_f(ulong dummy)
preloader_console_init();
+ do_board_detect(); + /* * Allow establishing an early console as required for example when * doing a UART-based boot. Note that this console may not "survive"
Introduce fdt_apply_ddrss_timings_patch() to allow board code to override DDR settings in the device tree prior to DDRSS driver probing.
Signed-off-by: Wadim Egorov w.egorov@phytec.de --- board/phytec/common/k3/Makefile | 1 + board/phytec/common/k3/k3_ddrss_patch.c | 68 +++++++++++++++++++++++++ board/phytec/common/k3/k3_ddrss_patch.h | 28 ++++++++++ board/phytec/phycore_am62x/MAINTAINERS | 1 + 4 files changed, 98 insertions(+) create mode 100644 board/phytec/common/k3/k3_ddrss_patch.c create mode 100644 board/phytec/common/k3/k3_ddrss_patch.h
diff --git a/board/phytec/common/k3/Makefile b/board/phytec/common/k3/Makefile index bcca1a9f846..40e91a43e99 100644 --- a/board/phytec/common/k3/Makefile +++ b/board/phytec/common/k3/Makefile @@ -1,2 +1,3 @@ # SPDX-License-Identifier: GPL-2.0+ obj-y += board.o +obj-$(CONFIG_K3_DDRSS) += k3_ddrss_patch.o diff --git a/board/phytec/common/k3/k3_ddrss_patch.c b/board/phytec/common/k3/k3_ddrss_patch.c new file mode 100644 index 00000000000..39f7be8dc92 --- /dev/null +++ b/board/phytec/common/k3/k3_ddrss_patch.c @@ -0,0 +1,68 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov w.egorov@phytec.de + */ + +#include "k3_ddrss_patch.h" + +#include <fdt_support.h> +#include <linux/errno.h> + +#ifdef CONFIG_K3_AM64_DDRSS +#define LPDDR4_INTR_CTL_REG_COUNT (423U) +#define LPDDR4_INTR_PHY_INDEP_REG_COUNT (345U) +#endif + +static int fdt_setprop_inplace_idx_u32(void *fdt, int nodeoffset, + const char *name, uint32_t idx, u32 val) +{ + val = cpu_to_be32(val); + return fdt_setprop_inplace_namelen_partial(fdt, nodeoffset, name, + strlen(name), + idx * sizeof(val), &val, + sizeof(val)); +} + +int fdt_apply_ddrss_timings_patch(void *fdt, struct ddrss *ddrss) +{ + int i, j; + int ret; + int mem_offset; + + mem_offset = fdt_path_offset(fdt, "/memorycontroller@f300000"); + if (mem_offset < 0) + return -ENODEV; + + for (i = 0; i < LPDDR4_INTR_CTL_REG_COUNT; i++) + for (j = 0; j < ddrss->ctl_regs_num; j++) + if (i == ddrss->ctl_regs[j].off) { + ret = fdt_setprop_inplace_idx_u32(fdt, + mem_offset, "ti,ctl-data", i, + ddrss->ctl_regs[j].val); + if (ret) + return ret; + } + + for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++) + for (j = 0; j < ddrss->pi_regs_num; j++) + if (i == ddrss->pi_regs[j].off) { + ret = fdt_setprop_inplace_idx_u32(fdt, + mem_offset, "ti,pi-data", i, + ddrss->pi_regs[j].val); + if (ret) + return ret; + } + + for (i = 0; i < LPDDR4_INTR_PHY_INDEP_REG_COUNT; i++) + for (j = 0; j < ddrss->phy_regs_num; j++) + if (i == ddrss->phy_regs[j].off) { + ret = fdt_setprop_inplace_idx_u32(fdt, + mem_offset, "ti,phy-data", i, + ddrss->phy_regs[j].val); + if (ret) + return ret; + } + + return 0; +} diff --git a/board/phytec/common/k3/k3_ddrss_patch.h b/board/phytec/common/k3/k3_ddrss_patch.h new file mode 100644 index 00000000000..0a47c85116a --- /dev/null +++ b/board/phytec/common/k3/k3_ddrss_patch.h @@ -0,0 +1,28 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov w.egorov@phytec.de + */ + +#ifndef K3_DDRSS_PATCH +#define K3_DDRSS_PATCH + +#include <linux/types.h> + +struct ddr_reg { + u32 off; + u32 val; +}; + +struct ddrss { + struct ddr_reg *ctl_regs; + u32 ctl_regs_num; + struct ddr_reg *pi_regs; + u32 pi_regs_num; + struct ddr_reg *phy_regs; + u32 phy_regs_num; +}; + +int fdt_apply_ddrss_timings_patch(void *fdt, struct ddrss *ddrss); + +#endif /* K3_DDRSS_PATCH */ diff --git a/board/phytec/phycore_am62x/MAINTAINERS b/board/phytec/phycore_am62x/MAINTAINERS index 02ac88e58a4..42463ad054e 100644 --- a/board/phytec/phycore_am62x/MAINTAINERS +++ b/board/phytec/phycore_am62x/MAINTAINERS @@ -11,3 +11,4 @@ F: configs/phycore_am62x_a53_defconfig F: configs/phycore_am62x_r5_defconfig F: include/configs/phycore_am62x.h F: doc/board/phytec/phycore-am62x.rst +F: board/phytec/common/k3
Use content of EEPROM to detect the actual RAM size and adjust DDR timings, size and banks accordingly. Also enable the SoM detection per default in the defconfigs.
Signed-off-by: Wadim Egorov w.egorov@phytec.de --- board/phytec/common/am6_som_detection.h | 8 + board/phytec/phycore_am62x/phycore-am62x.c | 152 ++++++++++++- board/phytec/phycore_am62x/phycore-ddr-data.h | 206 ++++++++++++++++++ configs/phycore_am62x_a53_defconfig | 4 + configs/phycore_am62x_r5_defconfig | 4 + 5 files changed, 372 insertions(+), 2 deletions(-) create mode 100644 board/phytec/phycore_am62x/phycore-ddr-data.h
diff --git a/board/phytec/common/am6_som_detection.h b/board/phytec/common/am6_som_detection.h index 032f9da3aab..c5c6e179da6 100644 --- a/board/phytec/common/am6_som_detection.h +++ b/board/phytec/common/am6_som_detection.h @@ -9,11 +9,19 @@
#include "phytec_som_detection.h"
+#define EEPROM_ADDR 0x50 #define PHYTEC_AM62X_SOM 71 #define PHYTEC_AM64X_SOM 72 #define PHYTEC_EEPROM_VALUE_X 0x21 #define PHYTEC_EEPROM_NOR_FLASH_64MB_QSPI 0xC
+enum { + EEPROM_RAM_SIZE_512MB = 0, + EEPROM_RAM_SIZE_1GB = 1, + EEPROM_RAM_SIZE_2GB = 2, + EEPROM_RAM_SIZE_4GB = 4 +}; + int __maybe_unused phytec_am6_detect(struct phytec_eeprom_data *data); u8 __maybe_unused phytec_get_am6_ddr_size(struct phytec_eeprom_data *data); u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data); diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c index a082b886bda..4a76f1343d7 100644 --- a/board/phytec/phycore_am62x/phycore-am62x.c +++ b/board/phytec/phycore_am62x/phycore-am62x.c @@ -8,6 +8,13 @@ #include <spl.h> #include <fdt_support.h>
+#include "phycore-ddr-data.h" +#include "../common/k3/k3_ddrss_patch.h" +#include "../common/am6_som_detection.h" + +#define AM64_DDRSS_SS_BASE 0x0F300000 +#define DDRSS_V2A_CTL_REG 0x0020 + DECLARE_GLOBAL_DATA_PTR;
int board_init(void) @@ -15,16 +22,157 @@ int board_init(void) return 0; }
+static u8 phytec_get_am62_ddr_size_default(void) +{ + int ret; + struct phytec_eeprom_data data; + + if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_FIX)) { + if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_1GB)) + return EEPROM_RAM_SIZE_1GB; + else if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_2GB)) + return EEPROM_RAM_SIZE_2GB; + else if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_4GB)) + return EEPROM_RAM_SIZE_4GB; + } + + ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR); + if (!ret && data.valid) + return phytec_get_am6_ddr_size(&data); + + /* Default DDR size is 2GB */ + return EEPROM_RAM_SIZE_2GB; +} + int dram_init(void) { - return fdtdec_setup_mem_size_base(); + u8 ram_size = phytec_get_am62_ddr_size_default(); + + /* + * HACK: ddrss driver support 2GB RAM by default + * V2A_CTL_REG should be updated to support other RAM size + */ + if (IS_ENABLED(CONFIG_K3_AM64_DDRSS)) + if (ram_size == EEPROM_RAM_SIZE_4GB) + writel(0x00000210, AM64_DDRSS_SS_BASE + DDRSS_V2A_CTL_REG); + + switch (ram_size) { + case EEPROM_RAM_SIZE_1GB: + gd->ram_size = 0x40000000; + break; + case EEPROM_RAM_SIZE_2GB: + gd->ram_size = 0x80000000; + break; + case EEPROM_RAM_SIZE_4GB: +#ifdef CONFIG_PHYS_64BIT + gd->ram_size = 0x100000000; +#else + gd->ram_size = 0x80000000; +#endif + break; + default: + gd->ram_size = 0x80000000; + } + + return 0; +} + +phys_size_t board_get_usable_ram_top(phys_size_t total_size) +{ +#ifdef CONFIG_PHYS_64BIT + /* Limit RAM used by U-Boot to the DDR low region */ + if (gd->ram_top > 0x100000000) + return 0x100000000; +#endif + return gd->ram_top; }
int dram_init_banksize(void) { - return fdtdec_setup_memory_banksize(); + u8 ram_size; + + ram_size = phytec_get_am62_ddr_size_default(); + switch (ram_size) { + case EEPROM_RAM_SIZE_1GB: + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x40000000; + gd->ram_size = 0x40000000; + break; + + case EEPROM_RAM_SIZE_2GB: + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x80000000; + gd->ram_size = 0x80000000; + break; + + case EEPROM_RAM_SIZE_4GB: + /* Bank 0 declares the memory available in the DDR low region */ + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x80000000; + gd->ram_size = 0x80000000; + +#ifdef CONFIG_PHYS_64BIT + /* Bank 1 declares the memory available in the DDR upper region */ + gd->bd->bi_dram[1].start = 0x880000000; + gd->bd->bi_dram[1].size = 0x80000000; + gd->ram_size = 0x100000000; +#endif + break; + default: + /* Continue with default 2GB setup */ + gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE; + gd->bd->bi_dram[0].size = 0x80000000; + gd->ram_size = 0x80000000; + printf("DDR size %d is not supported\n", ram_size); + } + + return 0; +} + +#if defined(CONFIG_K3_DDRSS) +int update_ddrss_timings(void) +{ + int ret; + u8 ram_size; + struct ddrss *ddr_patch = NULL; + void *fdt = (void *)gd->fdt_blob; + + ram_size = phytec_get_am62_ddr_size_default(); + switch (ram_size) { + case EEPROM_RAM_SIZE_1GB: + ddr_patch = &phycore_ddrss_data[PHYCORE_1GB]; + break; + case EEPROM_RAM_SIZE_2GB: + ddr_patch = NULL; + break; + case EEPROM_RAM_SIZE_4GB: + ddr_patch = &phycore_ddrss_data[PHYCORE_4GB]; + break; + default: + break; + } + + /* Nothing to patch */ + if (!ddr_patch) + return 0; + + debug("Applying DDRSS timings patch for ram_size %d\n", ram_size); + + ret = fdt_apply_ddrss_timings_patch(fdt, ddr_patch); + if (ret < 0) { + printf("Failed to apply ddrs timings patch %d\n", ret); + return ret; + } + + return 0; }
+int do_board_detect(void) +{ + return update_ddrss_timings(); +} +#endif + #define CTRLMMR_USB0_PHY_CTRL 0x43004008 #define CTRLMMR_USB1_PHY_CTRL 0x43004018 #define CORE_VOLTAGE 0x80000000 diff --git a/board/phytec/phycore_am62x/phycore-ddr-data.h b/board/phytec/phycore_am62x/phycore-ddr-data.h new file mode 100644 index 00000000000..fe6eccd959e --- /dev/null +++ b/board/phytec/phycore_am62x/phycore-ddr-data.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/* + * Copyright (C) 2024 PHYTEC Messtechnik GmbH + * Author: Wadim Egorov w.egorov@phytec.de + */ + +#ifndef PHYCORE_DDR_DATA +#define PHYCORE_DDR_DATA + +#include "../common/k3/k3_ddrss_patch.h" + +/* 1 GB variant delta */ +struct ddr_reg ddr_1gb_ctl_regs[] = { + { 55, 0x0400DB60 }, + { 58, 0x0400DB60 }, + { 61, 0x0400DB60 }, + { 73, 0x00001860 }, + { 75, 0x00001860 }, + { 77, 0x00001860 }, + { 119, 0x00061800 }, + { 120, 0x00061800 }, + { 121, 0x00061800 }, + { 122, 0x00061800 }, + { 123, 0x00061800 }, + { 125, 0x0000AAA0 }, + { 126, 0x00061800 }, + { 127, 0x00061800 }, + { 128, 0x00061800 }, + { 129, 0x00061800 }, + { 130, 0x00061800 }, + { 132, 0x0000AAA0 }, + { 133, 0x00061800 }, + { 134, 0x00061800 }, + { 135, 0x00061800 }, + { 136, 0x00061800 }, + { 137, 0x00061800 }, + { 139, 0x0000AAA0 }, + { 206, 0x00000000 }, + { 209, 0x00000000 }, + { 212, 0x00000000 }, + { 215, 0x00000000 }, + { 218, 0x00000000 }, + { 221, 0x00000000 }, + { 230, 0x00000000 }, + { 231, 0x00000000 }, + { 232, 0x00000000 }, + { 233, 0x00000000 }, + { 234, 0x00000000 }, + { 235, 0x00000000 }, + { 316, 0x01010000 }, + { 318, 0x3FFF0000 }, + { 327, 0x00000C01 }, + { 328, 0x00000000 }, + { 385, 0x000030C0 }, + { 390, 0x0000DB60 }, + { 391, 0x0001E780 }, + { 394, 0x000030C0 }, + { 399, 0x0000DB60 }, + { 400, 0x0001E780 }, + { 403, 0x000030C0 }, + { 408, 0x0000DB60 }, + { 409, 0x0001E780 } +}; + +struct ddr_reg ddr_1gb_pi_regs[] = { + { 77, 0x04000100 }, + { 176, 0x00001860 }, + { 178, 0x00001860 }, + { 180, 0x04001860 }, + { 233, 0x0000C570 }, + { 238, 0x0000C570 }, + { 243, 0x0000C570 }, + { 247, 0x000030C0 }, + { 248, 0x0001E780 }, + { 249, 0x000030C0 }, + { 250, 0x0001E780 }, + { 251, 0x000030C0 }, + { 252, 0x0001E780 }, + { 299, 0x00000000 }, + { 301, 0x00000000 }, + { 307, 0x00000000 }, + { 309, 0x00000000 }, + { 315, 0x00000000 }, + { 317, 0x00000000 }, + { 323, 0x00000000 }, + { 325, 0x00000000 }, + { 331, 0x00000000 }, + { 333, 0x00000000 }, + { 339, 0x00000000 }, + { 341, 0x00000000 } +}; + +struct ddr_reg ddr_1gb_phy_regs[] = { + { 1371, 0x0001F7C2 }, +}; + +/* 4 GB variant delta */ +struct ddr_reg ddr_4gb_ctl_regs[] = { + { 55, 0x0400DB60 }, + { 58, 0x0400DB60 }, + { 61, 0x0400DB60 }, + { 73, 0x00001860 }, + { 75, 0x00001860 }, + { 77, 0x00001860 }, + { 119, 0x00061800 }, + { 120, 0x00061800 }, + { 121, 0x00061800 }, + { 122, 0x00061800 }, + { 123, 0x00061800 }, + { 125, 0x0000AAA0 }, + { 126, 0x00061800 }, + { 127, 0x00061800 }, + { 128, 0x00061800 }, + { 129, 0x00061800 }, + { 130, 0x00061800 }, + { 132, 0x0000AAA0 }, + { 133, 0x00061800 }, + { 134, 0x00061800 }, + { 135, 0x00061800 }, + { 136, 0x00061800 }, + { 137, 0x00061800 }, + { 139, 0x0000AAA0 }, + { 206, 0x00000000 }, + { 209, 0x00000000 }, + { 212, 0x00000000 }, + { 215, 0x00000000 }, + { 218, 0x00000000 }, + { 221, 0x00000000 }, + { 230, 0x00000000 }, + { 231, 0x00000000 }, + { 232, 0x00000000 }, + { 233, 0x00000000 }, + { 234, 0x00000000 }, + { 235, 0x00000000 }, + { 316, 0x00000000 }, + { 318, 0x7FFF0000 }, + { 327, 0x01000C01 }, + { 328, 0x00000001 }, + { 385, 0x000030C0 }, + { 390, 0x0000DB60 }, + { 391, 0x0001E780 }, + { 394, 0x000030C0 }, + { 399, 0x0000DB60 }, + { 400, 0x0001E780 }, + { 403, 0x000030C0 }, + { 408, 0x0000DB60 }, + { 409, 0x0001E780 } +}; + +struct ddr_reg ddr_4gb_pi_regs[] = { + { 77, 0x04000000 }, + { 176, 0x00001860 }, + { 178, 0x00001860 }, + { 180, 0x04001860 }, + { 233, 0x0000C570 }, + { 238, 0x0000C570 }, + { 243, 0x0000C570 }, + { 247, 0x000030C0 }, + { 248, 0x0001E780 }, + { 249, 0x000030C0 }, + { 250, 0x0001E780 }, + { 251, 0x000030C0 }, + { 252, 0x0001E780 }, + { 299, 0x00000000 }, + { 301, 0x00000000 }, + { 307, 0x00000000 }, + { 309, 0x00000000 }, + { 315, 0x00000000 }, + { 317, 0x00000000 }, + { 323, 0x00000000 }, + { 325, 0x00000000 }, + { 331, 0x00000000 }, + { 333, 0x00000000 }, + { 339, 0x00000000 }, + { 341, 0x00000000 } +}; + +struct ddr_reg ddr_4gb_phy_regs[] = { + { 1371, 0x0001F7C2 }, +}; + +enum { + PHYCORE_1GB, + PHYCORE_4GB, +}; + +struct ddrss phycore_ddrss_data[] = { + [PHYCORE_1GB] = { + .ctl_regs = &ddr_1gb_ctl_regs[0], + .ctl_regs_num = ARRAY_SIZE(ddr_1gb_ctl_regs), + .pi_regs = &ddr_1gb_pi_regs[0], + .pi_regs_num = ARRAY_SIZE(ddr_1gb_pi_regs), + .phy_regs = &ddr_1gb_phy_regs[0], + .phy_regs_num = ARRAY_SIZE(ddr_1gb_phy_regs), + }, + [PHYCORE_4GB] = { + .ctl_regs = &ddr_4gb_ctl_regs[0], + .ctl_regs_num = ARRAY_SIZE(ddr_4gb_ctl_regs), + .pi_regs = &ddr_4gb_pi_regs[0], + .pi_regs_num = ARRAY_SIZE(ddr_4gb_pi_regs), + .phy_regs = &ddr_4gb_phy_regs[0], + .phy_regs_num = ARRAY_SIZE(ddr_4gb_phy_regs), + }, +}; + +#endif /* PHYCORE_DDR_DATA */ diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index fd36edc29dd..145887c0286 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_SOC_K3_AM625=y +CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_TARGET_PHYCORE_AM62X_A53=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000 @@ -45,6 +46,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" +CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER_DOMAIN=y @@ -73,6 +75,8 @@ CONFIG_CLK_TI_SCI=y CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/phycore_am62x_r5_defconfig b/configs/phycore_am62x_r5_defconfig index 389672d5227..0062a4e3569 100644 --- a/configs/phycore_am62x_r5_defconfig +++ b/configs/phycore_am62x_r5_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_SOC_K3_AM625=y +CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_TARGET_PHYCORE_AM62X_R5=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c3a7f0 @@ -50,6 +51,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y @@ -88,6 +90,7 @@ CONFIG_SPL_CLK_K3_PLL=y CONFIG_SPL_CLK_K3=y CONFIG_TI_SCI_PROTOCOL=y CONFIG_DA8XX_GPIO=y +CONFIG_DM_I2C=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_SPL_MISC=y @@ -129,3 +132,4 @@ CONFIG_SPL_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_LIB_RATIONAL=y CONFIG_SPL_LIB_RATIONAL=y +CONFIG_SYS_I2C_OMAP24XX=y
Hey Wadim,
On 07.05.24 17:17, Wadim Egorov wrote:
Use content of EEPROM to detect the actual RAM size and adjust DDR timings, size and banks accordingly. Also enable the SoM detection per default in the defconfigs.
Signed-off-by: Wadim Egorov w.egorov@phytec.de
board/phytec/common/am6_som_detection.h | 8 + board/phytec/phycore_am62x/phycore-am62x.c | 152 ++++++++++++- board/phytec/phycore_am62x/phycore-ddr-data.h | 206 ++++++++++++++++++ configs/phycore_am62x_a53_defconfig | 4 + configs/phycore_am62x_r5_defconfig | 4 + 5 files changed, 372 insertions(+), 2 deletions(-) create mode 100644 board/phytec/phycore_am62x/phycore-ddr-data.h
diff --git a/board/phytec/common/am6_som_detection.h b/board/phytec/common/am6_som_detection.h index 032f9da3aab..c5c6e179da6 100644 --- a/board/phytec/common/am6_som_detection.h +++ b/board/phytec/common/am6_som_detection.h @@ -9,11 +9,19 @@
#include "phytec_som_detection.h"
+#define EEPROM_ADDR 0x50 #define PHYTEC_AM62X_SOM 71 #define PHYTEC_AM64X_SOM 72 #define PHYTEC_EEPROM_VALUE_X 0x21 #define PHYTEC_EEPROM_NOR_FLASH_64MB_QSPI 0xC
+enum {
- EEPROM_RAM_SIZE_512MB = 0,
- EEPROM_RAM_SIZE_1GB = 1,
- EEPROM_RAM_SIZE_2GB = 2,
- EEPROM_RAM_SIZE_4GB = 4
+};
- int __maybe_unused phytec_am6_detect(struct phytec_eeprom_data *data); u8 __maybe_unused phytec_get_am6_ddr_size(struct phytec_eeprom_data *data); u8 __maybe_unused phytec_get_am6_spi(struct phytec_eeprom_data *data);
diff --git a/board/phytec/phycore_am62x/phycore-am62x.c b/board/phytec/phycore_am62x/phycore-am62x.c index a082b886bda..4a76f1343d7 100644 --- a/board/phytec/phycore_am62x/phycore-am62x.c +++ b/board/phytec/phycore_am62x/phycore-am62x.c @@ -8,6 +8,13 @@ #include <spl.h> #include <fdt_support.h>
+#include "phycore-ddr-data.h" +#include "../common/k3/k3_ddrss_patch.h" +#include "../common/am6_som_detection.h"
+#define AM64_DDRSS_SS_BASE 0x0F300000 +#define DDRSS_V2A_CTL_REG 0x0020
DECLARE_GLOBAL_DATA_PTR;
int board_init(void)
@@ -15,16 +22,157 @@ int board_init(void) return 0; }
+static u8 phytec_get_am62_ddr_size_default(void) +{
- int ret;
- struct phytec_eeprom_data data;
- if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_FIX)) {
if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_1GB))return EEPROM_RAM_SIZE_1GB;else if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_2GB))return EEPROM_RAM_SIZE_2GB;else if (IS_ENABLED(CONFIG_PHYCORE_AM62X_RAM_SIZE_4GB))return EEPROM_RAM_SIZE_4GB;- }
Please define these configs in board/phytec/phycore_am62x/Kconfig.
- Daniel
- ret = phytec_eeprom_data_setup(&data, 0, EEPROM_ADDR);
- if (!ret && data.valid)
return phytec_get_am6_ddr_size(&data);- /* Default DDR size is 2GB */
- return EEPROM_RAM_SIZE_2GB;
+}
- int dram_init(void) {
- return fdtdec_setup_mem_size_base();
- u8 ram_size = phytec_get_am62_ddr_size_default();
- /*
* HACK: ddrss driver support 2GB RAM by default* V2A_CTL_REG should be updated to support other RAM size*/- if (IS_ENABLED(CONFIG_K3_AM64_DDRSS))
if (ram_size == EEPROM_RAM_SIZE_4GB)writel(0x00000210, AM64_DDRSS_SS_BASE + DDRSS_V2A_CTL_REG);- switch (ram_size) {
- case EEPROM_RAM_SIZE_1GB:
gd->ram_size = 0x40000000;break;- case EEPROM_RAM_SIZE_2GB:
gd->ram_size = 0x80000000;break;- case EEPROM_RAM_SIZE_4GB:
+#ifdef CONFIG_PHYS_64BIT
gd->ram_size = 0x100000000;+#else
gd->ram_size = 0x80000000;+#endif
break;- default:
gd->ram_size = 0x80000000;- }
- return 0;
+}
+phys_size_t board_get_usable_ram_top(phys_size_t total_size) +{ +#ifdef CONFIG_PHYS_64BIT
- /* Limit RAM used by U-Boot to the DDR low region */
- if (gd->ram_top > 0x100000000)
return 0x100000000;+#endif
return gd->ram_top; }
int dram_init_banksize(void) {
- return fdtdec_setup_memory_banksize();
- u8 ram_size;
- ram_size = phytec_get_am62_ddr_size_default();
- switch (ram_size) {
- case EEPROM_RAM_SIZE_1GB:
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;gd->bd->bi_dram[0].size = 0x40000000;gd->ram_size = 0x40000000;break;- case EEPROM_RAM_SIZE_2GB:
gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;gd->bd->bi_dram[0].size = 0x80000000;gd->ram_size = 0x80000000;break;- case EEPROM_RAM_SIZE_4GB:
/* Bank 0 declares the memory available in the DDR low region */gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;gd->bd->bi_dram[0].size = 0x80000000;gd->ram_size = 0x80000000;+#ifdef CONFIG_PHYS_64BIT
/* Bank 1 declares the memory available in the DDR upper region */gd->bd->bi_dram[1].start = 0x880000000;gd->bd->bi_dram[1].size = 0x80000000;gd->ram_size = 0x100000000;+#endif
break;- default:
/* Continue with default 2GB setup */gd->bd->bi_dram[0].start = CFG_SYS_SDRAM_BASE;gd->bd->bi_dram[0].size = 0x80000000;gd->ram_size = 0x80000000;printf("DDR size %d is not supported\n", ram_size);- }
- return 0;
+}
+#if defined(CONFIG_K3_DDRSS) +int update_ddrss_timings(void) +{
- int ret;
- u8 ram_size;
- struct ddrss *ddr_patch = NULL;
- void *fdt = (void *)gd->fdt_blob;
- ram_size = phytec_get_am62_ddr_size_default();
- switch (ram_size) {
- case EEPROM_RAM_SIZE_1GB:
ddr_patch = &phycore_ddrss_data[PHYCORE_1GB];break;- case EEPROM_RAM_SIZE_2GB:
ddr_patch = NULL;break;- case EEPROM_RAM_SIZE_4GB:
ddr_patch = &phycore_ddrss_data[PHYCORE_4GB];break;- default:
break;- }
- /* Nothing to patch */
- if (!ddr_patch)
return 0;- debug("Applying DDRSS timings patch for ram_size %d\n", ram_size);
- ret = fdt_apply_ddrss_timings_patch(fdt, ddr_patch);
- if (ret < 0) {
printf("Failed to apply ddrs timings patch %d\n", ret);return ret;- }
- return 0; }
+int do_board_detect(void) +{
- return update_ddrss_timings();
+} +#endif
- #define CTRLMMR_USB0_PHY_CTRL 0x43004008 #define CTRLMMR_USB1_PHY_CTRL 0x43004018 #define CORE_VOLTAGE 0x80000000
diff --git a/board/phytec/phycore_am62x/phycore-ddr-data.h b/board/phytec/phycore_am62x/phycore-ddr-data.h new file mode 100644 index 00000000000..fe6eccd959e --- /dev/null +++ b/board/phytec/phycore_am62x/phycore-ddr-data.h @@ -0,0 +1,206 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later */ +/*
- Copyright (C) 2024 PHYTEC Messtechnik GmbH
- Author: Wadim Egorov w.egorov@phytec.de
- */
+#ifndef PHYCORE_DDR_DATA +#define PHYCORE_DDR_DATA
+#include "../common/k3/k3_ddrss_patch.h"
+/* 1 GB variant delta */ +struct ddr_reg ddr_1gb_ctl_regs[] = {
- { 55, 0x0400DB60 },
- { 58, 0x0400DB60 },
- { 61, 0x0400DB60 },
- { 73, 0x00001860 },
- { 75, 0x00001860 },
- { 77, 0x00001860 },
- { 119, 0x00061800 },
- { 120, 0x00061800 },
- { 121, 0x00061800 },
- { 122, 0x00061800 },
- { 123, 0x00061800 },
- { 125, 0x0000AAA0 },
- { 126, 0x00061800 },
- { 127, 0x00061800 },
- { 128, 0x00061800 },
- { 129, 0x00061800 },
- { 130, 0x00061800 },
- { 132, 0x0000AAA0 },
- { 133, 0x00061800 },
- { 134, 0x00061800 },
- { 135, 0x00061800 },
- { 136, 0x00061800 },
- { 137, 0x00061800 },
- { 139, 0x0000AAA0 },
- { 206, 0x00000000 },
- { 209, 0x00000000 },
- { 212, 0x00000000 },
- { 215, 0x00000000 },
- { 218, 0x00000000 },
- { 221, 0x00000000 },
- { 230, 0x00000000 },
- { 231, 0x00000000 },
- { 232, 0x00000000 },
- { 233, 0x00000000 },
- { 234, 0x00000000 },
- { 235, 0x00000000 },
- { 316, 0x01010000 },
- { 318, 0x3FFF0000 },
- { 327, 0x00000C01 },
- { 328, 0x00000000 },
- { 385, 0x000030C0 },
- { 390, 0x0000DB60 },
- { 391, 0x0001E780 },
- { 394, 0x000030C0 },
- { 399, 0x0000DB60 },
- { 400, 0x0001E780 },
- { 403, 0x000030C0 },
- { 408, 0x0000DB60 },
- { 409, 0x0001E780 }
+};
+struct ddr_reg ddr_1gb_pi_regs[] = {
- { 77, 0x04000100 },
- { 176, 0x00001860 },
- { 178, 0x00001860 },
- { 180, 0x04001860 },
- { 233, 0x0000C570 },
- { 238, 0x0000C570 },
- { 243, 0x0000C570 },
- { 247, 0x000030C0 },
- { 248, 0x0001E780 },
- { 249, 0x000030C0 },
- { 250, 0x0001E780 },
- { 251, 0x000030C0 },
- { 252, 0x0001E780 },
- { 299, 0x00000000 },
- { 301, 0x00000000 },
- { 307, 0x00000000 },
- { 309, 0x00000000 },
- { 315, 0x00000000 },
- { 317, 0x00000000 },
- { 323, 0x00000000 },
- { 325, 0x00000000 },
- { 331, 0x00000000 },
- { 333, 0x00000000 },
- { 339, 0x00000000 },
- { 341, 0x00000000 }
+};
+struct ddr_reg ddr_1gb_phy_regs[] = {
- { 1371, 0x0001F7C2 },
+};
+/* 4 GB variant delta */ +struct ddr_reg ddr_4gb_ctl_regs[] = {
- { 55, 0x0400DB60 },
- { 58, 0x0400DB60 },
- { 61, 0x0400DB60 },
- { 73, 0x00001860 },
- { 75, 0x00001860 },
- { 77, 0x00001860 },
- { 119, 0x00061800 },
- { 120, 0x00061800 },
- { 121, 0x00061800 },
- { 122, 0x00061800 },
- { 123, 0x00061800 },
- { 125, 0x0000AAA0 },
- { 126, 0x00061800 },
- { 127, 0x00061800 },
- { 128, 0x00061800 },
- { 129, 0x00061800 },
- { 130, 0x00061800 },
- { 132, 0x0000AAA0 },
- { 133, 0x00061800 },
- { 134, 0x00061800 },
- { 135, 0x00061800 },
- { 136, 0x00061800 },
- { 137, 0x00061800 },
- { 139, 0x0000AAA0 },
- { 206, 0x00000000 },
- { 209, 0x00000000 },
- { 212, 0x00000000 },
- { 215, 0x00000000 },
- { 218, 0x00000000 },
- { 221, 0x00000000 },
- { 230, 0x00000000 },
- { 231, 0x00000000 },
- { 232, 0x00000000 },
- { 233, 0x00000000 },
- { 234, 0x00000000 },
- { 235, 0x00000000 },
- { 316, 0x00000000 },
- { 318, 0x7FFF0000 },
- { 327, 0x01000C01 },
- { 328, 0x00000001 },
- { 385, 0x000030C0 },
- { 390, 0x0000DB60 },
- { 391, 0x0001E780 },
- { 394, 0x000030C0 },
- { 399, 0x0000DB60 },
- { 400, 0x0001E780 },
- { 403, 0x000030C0 },
- { 408, 0x0000DB60 },
- { 409, 0x0001E780 }
+};
+struct ddr_reg ddr_4gb_pi_regs[] = {
- { 77, 0x04000000 },
- { 176, 0x00001860 },
- { 178, 0x00001860 },
- { 180, 0x04001860 },
- { 233, 0x0000C570 },
- { 238, 0x0000C570 },
- { 243, 0x0000C570 },
- { 247, 0x000030C0 },
- { 248, 0x0001E780 },
- { 249, 0x000030C0 },
- { 250, 0x0001E780 },
- { 251, 0x000030C0 },
- { 252, 0x0001E780 },
- { 299, 0x00000000 },
- { 301, 0x00000000 },
- { 307, 0x00000000 },
- { 309, 0x00000000 },
- { 315, 0x00000000 },
- { 317, 0x00000000 },
- { 323, 0x00000000 },
- { 325, 0x00000000 },
- { 331, 0x00000000 },
- { 333, 0x00000000 },
- { 339, 0x00000000 },
- { 341, 0x00000000 }
+};
+struct ddr_reg ddr_4gb_phy_regs[] = {
- { 1371, 0x0001F7C2 },
+};
+enum {
- PHYCORE_1GB,
- PHYCORE_4GB,
+};
+struct ddrss phycore_ddrss_data[] = {
- [PHYCORE_1GB] = {
.ctl_regs = &ddr_1gb_ctl_regs[0],.ctl_regs_num = ARRAY_SIZE(ddr_1gb_ctl_regs),.pi_regs = &ddr_1gb_pi_regs[0],.pi_regs_num = ARRAY_SIZE(ddr_1gb_pi_regs),.phy_regs = &ddr_1gb_phy_regs[0],.phy_regs_num = ARRAY_SIZE(ddr_1gb_phy_regs),- },
- [PHYCORE_4GB] = {
.ctl_regs = &ddr_4gb_ctl_regs[0],.ctl_regs_num = ARRAY_SIZE(ddr_4gb_ctl_regs),.pi_regs = &ddr_4gb_pi_regs[0],.pi_regs_num = ARRAY_SIZE(ddr_4gb_pi_regs),.phy_regs = &ddr_4gb_phy_regs[0],.phy_regs_num = ARRAY_SIZE(ddr_4gb_phy_regs),- },
+};
+#endif /* PHYCORE_DDR_DATA */ diff --git a/configs/phycore_am62x_a53_defconfig b/configs/phycore_am62x_a53_defconfig index fd36edc29dd..145887c0286 100644 --- a/configs/phycore_am62x_a53_defconfig +++ b/configs/phycore_am62x_a53_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_SOC_K3_AM625=y +CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_TARGET_PHYCORE_AM62X_A53=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80b80000 @@ -45,6 +46,7 @@ CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x1400 CONFIG_SPL_ENV_SUPPORT=y CONFIG_SPL_FS_LOAD_PAYLOAD_NAME="u-boot.img" +CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_POWER_DOMAIN=y @@ -73,6 +75,8 @@ CONFIG_CLK_TI_SCI=y CONFIG_DMA_CHANNELS=y CONFIG_TI_K3_NAVSS_UDMA=y CONFIG_TI_SCI_PROTOCOL=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_OMAP24XX=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/phycore_am62x_r5_defconfig b/configs/phycore_am62x_r5_defconfig index 389672d5227..0062a4e3569 100644 --- a/configs/phycore_am62x_r5_defconfig +++ b/configs/phycore_am62x_r5_defconfig @@ -6,6 +6,7 @@ CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 CONFIG_SOC_K3_AM625=y +CONFIG_PHYTEC_SOM_DETECTION=y CONFIG_TARGET_PHYCORE_AM62X_R5=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43c3a7f0 @@ -50,6 +51,7 @@ CONFIG_SPL_SYS_MALLOC_SIZE=0x1000000 CONFIG_SPL_EARLY_BSS=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x400 +CONFIG_SPL_I2C=y CONFIG_SPL_DM_MAILBOX=y CONFIG_SPL_DM_SPI_FLASH=y CONFIG_SPL_DM_RESET=y @@ -88,6 +90,7 @@ CONFIG_SPL_CLK_K3_PLL=y CONFIG_SPL_CLK_K3=y CONFIG_TI_SCI_PROTOCOL=y CONFIG_DA8XX_GPIO=y +CONFIG_DM_I2C=y CONFIG_DM_MAILBOX=y CONFIG_K3_SEC_PROXY=y CONFIG_SPL_MISC=y @@ -129,3 +132,4 @@ CONFIG_SPL_TIMER=y CONFIG_OMAP_TIMER=y CONFIG_LIB_RATIONAL=y CONFIG_SPL_LIB_RATIONAL=y +CONFIG_SYS_I2C_OMAP24XX=y
Tested-by: John Ma jma@phytec.com
On 5/7/24 08:17, Wadim Egorov wrote:
PHYTEC stores details about the hardware in an EEPROM on the SoM. We can utilize this information and chose the proper DDR timings accordingly.
Due to the limited SRAM memory on the AM62x, the concept was to store only the DDR timings deltas and not their full set, see Patch 4 & 5.
The last patch adds support for a 1 GB and 4 GB RAM variant of the phyCORE-AM62x.
Patch 4 & 5 are based on https://patchwork.ozlabs.org/project/uboot/list/?series=404273
Wadim Egorov (5): board: phytec: Make AM6 SoM detection depend on I2C board: phytec: Fix function definitions in AM6x SOM detection arm: mach-k3: am625: Call do_board_detect() before DDR probing board: phytec: common: Introduce a method to inject DDR timings deltas board: phytec: am62x: Add support for 1 & 4 GB RAM variants
arch/arm/mach-k3/am625_init.c | 2 + board/phytec/common/Kconfig | 2 + board/phytec/common/am6_som_detection.c | 18 +- board/phytec/common/am6_som_detection.h | 8 + board/phytec/common/k3/Makefile | 1 + board/phytec/common/k3/k3_ddrss_patch.c | 68 ++++++ board/phytec/common/k3/k3_ddrss_patch.h | 28 +++ board/phytec/phycore_am62x/MAINTAINERS | 1 + board/phytec/phycore_am62x/phycore-am62x.c | 152 ++++++++++++- board/phytec/phycore_am62x/phycore-ddr-data.h | 206 ++++++++++++++++++ configs/phycore_am62x_a53_defconfig | 4 + configs/phycore_am62x_r5_defconfig | 4 + 12 files changed, 483 insertions(+), 11 deletions(-) create mode 100644 board/phytec/common/k3/k3_ddrss_patch.c create mode 100644 board/phytec/common/k3/k3_ddrss_patch.h create mode 100644 board/phytec/phycore_am62x/phycore-ddr-data.h
participants (3)
-
Daniel Schultz -
John Ma -
Wadim Egorov