[U-Boot] [PATCH 0/4] Add Beelink GS1
This serie introduce the Beelink GS1 board with a patch for the reset on Allwinner H6.
Thanks to Jagan Teki most of the Beelink GS1 device-tree is taken from the Orange Pi boards.
Clément Péron (4): arm: dts: h6: move MMC pinctrl to soc arm: dts: h6: Add Beelink GS1 initial support arm: sunxi: h6: fix reset using r_wdog arm: dts: h6: minor sync with linux
arch/arm/dts/Makefile | 1 + arch/arm/dts/sun50i-h6-beelink-gs1.dts | 183 ++++++++++++++++++ arch/arm/dts/sun50i-h6-orangepi.dtsi | 2 - arch/arm/dts/sun50i-h6-pine-h64.dts | 4 - arch/arm/dts/sun50i-h6.dtsi | 16 +- .../include/asm/arch-sunxi/cpu_sun50i_h6.h | 1 + arch/arm/mach-sunxi/board.c | 9 +- configs/beelink_gs1_defconfig | 15 ++ 8 files changed, 217 insertions(+), 14 deletions(-) create mode 100644 arch/arm/dts/sun50i-h6-beelink-gs1.dts create mode 100644 configs/beelink_gs1_defconfig
There is only one muxing avalaible for each MMC controller.
Move this pinmux to the SOC dtsi.
Signed-off-by: Clément Péron peron.clem@gmail.com --- arch/arm/dts/sun50i-h6-orangepi.dtsi | 2 -- arch/arm/dts/sun50i-h6-pine-h64.dts | 4 ---- arch/arm/dts/sun50i-h6.dtsi | 4 ++++ 3 files changed, 4 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/sun50i-h6-orangepi.dtsi b/arch/arm/dts/sun50i-h6-orangepi.dtsi index 0612c19cd9..3748dcaa70 100644 --- a/arch/arm/dts/sun50i-h6-orangepi.dtsi +++ b/arch/arm/dts/sun50i-h6-orangepi.dtsi @@ -24,8 +24,6 @@ };
&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_cldo1>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; bus-width = <4>; diff --git a/arch/arm/dts/sun50i-h6-pine-h64.dts b/arch/arm/dts/sun50i-h6-pine-h64.dts index ceffc40810..a26314c084 100644 --- a/arch/arm/dts/sun50i-h6-pine-h64.dts +++ b/arch/arm/dts/sun50i-h6-pine-h64.dts @@ -42,16 +42,12 @@ };
&mmc0 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc0_pins>; vmmc-supply = <®_cldo1>; cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; status = "okay"; };
&mmc2 { - pinctrl-names = "default"; - pinctrl-0 = <&mmc2_pins>; vmmc-supply = <®_cldo1>; vqmmc-supply = <®_bldo2>; non-removable; diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi index cfa5fffcf6..617cea35d1 100644 --- a/arch/arm/dts/sun50i-h6.dtsi +++ b/arch/arm/dts/sun50i-h6.dtsi @@ -158,6 +158,8 @@ resets = <&ccu RST_BUS_MMC0>; reset-names = "ahb"; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc0_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>; @@ -186,6 +188,8 @@ resets = <&ccu RST_BUS_MMC2>; reset-names = "ahb"; interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&mmc2_pins>; status = "disabled"; #address-cells = <1>; #size-cells = <0>;
On Mon, Apr 8, 2019 at 10:11 PM Clément Péron peron.clem@gmail.com wrote:
There is only one muxing avalaible for each MMC controller.
Move this pinmux to the SOC dtsi.
Sync all dts(i) changes in one patch with head commit id details on patch commit message instead of few minor updates. sync with some rc tag would be beneficial if needed changes been part of that.
Hi,
On Fri, 12 Apr 2019 at 15:36, Jagan Teki jagan@amarulasolutions.com wrote:
On Mon, Apr 8, 2019 at 10:11 PM Clément Péron peron.clem@gmail.com wrote:
There is only one muxing avalaible for each MMC controller.
Move this pinmux to the SOC dtsi.
Sync all dts(i) changes in one patch with head commit id details on patch commit message instead of few minor updates. sync with some rc tag would be beneficial if needed changes been part of that.
eMMC pins move patch are planned for 5.2 no rc tag for now... I can postpone the sync dts(i) patch later If you prefer ?
Clement
Beelink GS1 is an Allwinner H6 based TV box, which support: - Allwinner H6 Quad-core 64-bit ARM Cortex-A53 - GPU Mali-T720 - 2GB LPDDR3 RAM - 16GB eMMC - AXP805 PMIC - 1Gbps GMAC via RTL8211E - USB 2.0 and 3.0 Host - HDMI port - S/PDIF port - 5V/2A DC power supply - Wi-Fi/BT via Fn-Link 6222B-SRB (RTL8222BS)
Signed-off-by: Clément Péron peron.clem@gmail.com --- arch/arm/dts/Makefile | 1 + arch/arm/dts/sun50i-h6-beelink-gs1.dts | 183 +++++++++++++++++++++++++ configs/beelink_gs1_defconfig | 15 ++ 3 files changed, 199 insertions(+) create mode 100644 arch/arm/dts/sun50i-h6-beelink-gs1.dts create mode 100644 configs/beelink_gs1_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0e2ffdb87f..4931b7d3cc 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -467,6 +467,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \ sun50i-h5-orangepi-prime.dtb \ sun50i-h5-orangepi-zero-plus2.dtb dtb-$(CONFIG_MACH_SUN50I_H6) += \ + sun50i-h6-beelink-gs1.dtb \ sun50i-h6-orangepi-lite2.dtb \ sun50i-h6-orangepi-one-plus.dtb \ sun50i-h6-pine-h64.dtb diff --git a/arch/arm/dts/sun50i-h6-beelink-gs1.dts b/arch/arm/dts/sun50i-h6-beelink-gs1.dts new file mode 100644 index 0000000000..c80862375f --- /dev/null +++ b/arch/arm/dts/sun50i-h6-beelink-gs1.dts @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/* + * Copyright (C) 2019 Clément Péron peron.clem@gmail.com + */ + +/dts-v1/; + +#include "sun50i-h6.dtsi" + +#include <dt-bindings/gpio/gpio.h> + +/ { + model = "Beelink GS1"; + compatible = "azw,beelink-gs1", "allwinner,sun50i-h6"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + + power { + label = "beelink:white:power"; + gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */ + default-state = "on"; + }; + }; + + reg_vcc5v: vcc5v { + /* board wide 5V supply directly from the DC jack */ + compatible = "regulator-fixed"; + regulator-name = "vcc-5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + regulator-always-on; + }; +}; + +&mmc0 { + vmmc-supply = <®_cldo1>; + cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>; + bus-width = <4>; + status = "okay"; +}; + +&mmc2 { + vmmc-supply = <®_cldo1>; + vqmmc-supply = <®_bldo2>; + non-removable; + cap-mmc-hw-reset; + status = "okay"; +}; + +&r_i2c { + status = "okay"; + + axp805: pmic@36 { + compatible = "x-powers,axp805", "x-powers,axp806"; + reg = <0x36>; + interrupt-parent = <&r_intc>; + interrupts = <0 IRQ_TYPE_LEVEL_LOW>; + interrupt-controller; + #interrupt-cells = <1>; + x-powers,self-working-mode; + vina-supply = <®_vcc5v>; + vinb-supply = <®_vcc5v>; + vinc-supply = <®_vcc5v>; + vind-supply = <®_vcc5v>; + vine-supply = <®_vcc5v>; + aldoin-supply = <®_vcc5v>; + bldoin-supply = <®_vcc5v>; + cldoin-supply = <®_vcc5v>; + + regulators { + reg_aldo1: aldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-pl"; + }; + + reg_aldo2: aldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-ac200"; + regulator-enable-ramp-delay = <100000>; + }; + + reg_aldo3: aldo3 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc25-dram"; + }; + + reg_bldo1: bldo1 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-bias-pll"; + }; + + reg_bldo2: bldo2 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-efuse-pcie-hdmi-io"; + }; + + reg_bldo3: bldo3 { + regulator-always-on; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-name = "vcc-dcxoio"; + }; + + bldo4 { + /* unused */ + }; + + reg_cldo1: cldo1 { + regulator-always-on; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-3v3"; + }; + + reg_cldo2: cldo2 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-1"; + }; + + reg_cldo3: cldo3 { + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-name = "vcc-wifi-2"; + }; + + reg_dcdca: dcdca { + regulator-always-on; + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; + regulator-name = "vdd-cpu"; + }; + + reg_dcdcc: dcdcc { + regulator-min-microvolt = <810000>; + regulator-max-microvolt = <1080000>; + regulator-name = "vdd-gpu"; + }; + + reg_dcdcd: dcdcd { + regulator-always-on; + regulator-min-microvolt = <960000>; + regulator-max-microvolt = <960000>; + regulator-name = "vdd-sys"; + }; + + reg_dcdce: dcdce { + regulator-always-on; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-name = "vcc-dram"; + }; + + sw { + /* unused */ + }; + }; + }; +}; + +&uart0 { + pinctrl-names = "default"; + pinctrl-0 = <&uart0_ph_pins>; + status = "okay"; +}; diff --git a/configs/beelink_gs1_defconfig b/configs/beelink_gs1_defconfig new file mode 100644 index 0000000000..ef4dd29549 --- /dev/null +++ b/configs/beelink_gs1_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN50I_H6=y +CONFIG_MMC0_CD_PIN="PF6" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +# CONFIG_PSCI_RESET is not set +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-beelink-gs1" +CONFIG_LED=y +CONFIG_LED_GPIO=y
Hi,
On Mon, 8 Apr 2019 at 18:41, Clément Péron peron.clem@gmail.com wrote:
Beelink GS1 is an Allwinner H6 based TV box, which support:
- Allwinner H6 Quad-core 64-bit ARM Cortex-A53
- GPU Mali-T720
- 2GB LPDDR3 RAM
- 16GB eMMC
- AXP805 PMIC
- 1Gbps GMAC via RTL8211E
- USB 2.0 and 3.0 Host
- HDMI port
- S/PDIF port
- 5V/2A DC power supply
- Wi-Fi/BT via Fn-Link 6222B-SRB (RTL8222BS)
Signed-off-by: Clément Péron peron.clem@gmail.com
arch/arm/dts/Makefile | 1 + arch/arm/dts/sun50i-h6-beelink-gs1.dts | 183 +++++++++++++++++++++++++ configs/beelink_gs1_defconfig | 15 ++ 3 files changed, 199 insertions(+) create mode 100644 arch/arm/dts/sun50i-h6-beelink-gs1.dts create mode 100644 configs/beelink_gs1_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 0e2ffdb87f..4931b7d3cc 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -467,6 +467,7 @@ dtb-$(CONFIG_MACH_SUN50I_H5) += \ sun50i-h5-orangepi-prime.dtb \ sun50i-h5-orangepi-zero-plus2.dtb dtb-$(CONFIG_MACH_SUN50I_H6) += \
sun50i-h6-beelink-gs1.dtb \ sun50i-h6-orangepi-lite2.dtb \ sun50i-h6-orangepi-one-plus.dtb \ sun50i-h6-pine-h64.dtbdiff --git a/arch/arm/dts/sun50i-h6-beelink-gs1.dts b/arch/arm/dts/sun50i-h6-beelink-gs1.dts new file mode 100644 index 0000000000..c80862375f --- /dev/null +++ b/arch/arm/dts/sun50i-h6-beelink-gs1.dts @@ -0,0 +1,183 @@ +// SPDX-License-Identifier: (GPL-2.0+ or MIT) +/*
- Copyright (C) 2019 Clément Péron peron.clem@gmail.com
- */
+/dts-v1/;
+#include "sun50i-h6.dtsi"
+#include <dt-bindings/gpio/gpio.h>
+/ {
model = "Beelink GS1";compatible = "azw,beelink-gs1", "allwinner,sun50i-h6";aliases {serial0 = &uart0;};chosen {stdout-path = "serial0:115200n8";};leds {compatible = "gpio-leds";power {label = "beelink:white:power";gpios = <&r_pio 0 4 GPIO_ACTIVE_HIGH>; /* PL4 */default-state = "on";};};reg_vcc5v: vcc5v {/* board wide 5V supply directly from the DC jack */compatible = "regulator-fixed";regulator-name = "vcc-5v";regulator-min-microvolt = <5000000>;regulator-max-microvolt = <5000000>;regulator-always-on;};+};
+&mmc0 {
vmmc-supply = <®_cldo1>;cd-gpios = <&pio 5 6 GPIO_ACTIVE_LOW>;bus-width = <4>;status = "okay";+};
+&mmc2 {
vmmc-supply = <®_cldo1>;vqmmc-supply = <®_bldo2>;non-removable;cap-mmc-hw-reset;
bus-width = <8>; I missed the bus-width.
The is the same issue on Pine H64
Clement
status = "okay";+};
+&r_i2c {
status = "okay";axp805: pmic@36 {compatible = "x-powers,axp805", "x-powers,axp806";reg = <0x36>;interrupt-parent = <&r_intc>;interrupts = <0 IRQ_TYPE_LEVEL_LOW>;interrupt-controller;#interrupt-cells = <1>;x-powers,self-working-mode;vina-supply = <®_vcc5v>;vinb-supply = <®_vcc5v>;vinc-supply = <®_vcc5v>;vind-supply = <®_vcc5v>;vine-supply = <®_vcc5v>;aldoin-supply = <®_vcc5v>;bldoin-supply = <®_vcc5v>;cldoin-supply = <®_vcc5v>;regulators {reg_aldo1: aldo1 {regulator-always-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc-pl";};reg_aldo2: aldo2 {regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc-ac200";regulator-enable-ramp-delay = <100000>;};reg_aldo3: aldo3 {regulator-always-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc25-dram";};reg_bldo1: bldo1 {regulator-always-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc-bias-pll";};reg_bldo2: bldo2 {regulator-always-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc-efuse-pcie-hdmi-io";};reg_bldo3: bldo3 {regulator-always-on;regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-name = "vcc-dcxoio";};bldo4 {/* unused */};reg_cldo1: cldo1 {regulator-always-on;regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc-3v3";};reg_cldo2: cldo2 {regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc-wifi-1";};reg_cldo3: cldo3 {regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-name = "vcc-wifi-2";};reg_dcdca: dcdca {regulator-always-on;regulator-min-microvolt = <810000>;regulator-max-microvolt = <1080000>;regulator-name = "vdd-cpu";};reg_dcdcc: dcdcc {regulator-min-microvolt = <810000>;regulator-max-microvolt = <1080000>;regulator-name = "vdd-gpu";};reg_dcdcd: dcdcd {regulator-always-on;regulator-min-microvolt = <960000>;regulator-max-microvolt = <960000>;regulator-name = "vdd-sys";};reg_dcdce: dcdce {regulator-always-on;regulator-min-microvolt = <1200000>;regulator-max-microvolt = <1200000>;regulator-name = "vcc-dram";};sw {/* unused */};};};+};
+&uart0 {
pinctrl-names = "default";pinctrl-0 = <&uart0_ph_pins>;status = "okay";+}; diff --git a/configs/beelink_gs1_defconfig b/configs/beelink_gs1_defconfig new file mode 100644 index 0000000000..ef4dd29549 --- /dev/null +++ b/configs/beelink_gs1_defconfig @@ -0,0 +1,15 @@ +CONFIG_ARM=y +CONFIG_ARCH_SUNXI=y +CONFIG_SPL=y +CONFIG_MACH_SUN50I_H6=y +CONFIG_MMC0_CD_PIN="PF6" +CONFIG_MMC_SUNXI_SLOT_EXTRA=2 +# CONFIG_PSCI_RESET is not set +CONFIG_NR_DRAM_BANKS=1 +# CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +# CONFIG_CMD_FLASH is not set +# CONFIG_SPL_DOS_PARTITION is not set +# CONFIG_SPL_EFI_PARTITION is not set +CONFIG_DEFAULT_DEVICE_TREE="sun50i-h6-beelink-gs1" +CONFIG_LED=y
+CONFIG_LED_GPIO=y
2.17.1
WDOG in H6 is broken so the reset is actually not working.
Use the R_WDOG instead.
Signed-off-by: Clément Péron peron.clem@gmail.com --- arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h | 1 + arch/arm/mach-sunxi/board.c | 9 +++++++-- 2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h index 41a9b0fc47..6392cb07b4 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h @@ -60,6 +60,7 @@ #define SUNXI_RTC_BASE 0x07000000 #define SUNXI_R_CPUCFG_BASE 0x07000400 #define SUNXI_PRCM_BASE 0x07010000 +#define SUNXI_R_WDOG_BASE 0x07020400 #define SUNXI_R_PIO_BASE 0x07022000 #define SUNXI_R_UART_BASE 0x07080000 #define SUNXI_R_TWI_BASE 0x07081400 diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index b74eaf2a0e..3f8128fbf4 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -287,9 +287,14 @@ void reset_cpu(ulong addr) writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); } #elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6) +#if defined(CONFIG_MACH_SUN50I_H6) + /* WDOG is broken for H6 use the R_WDOG instead */ static const struct sunxi_wdog *wdog = - ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; - + (struct sunxi_wdog *)SUNXI_R_WDOG_BASE; +#else + static const struct sunxi_wdog *wdog = + ((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog; +#endif /* Set the watchdog for its shortest interval (.5s) and wait */ writel(WDT_CFG_RESET, &wdog->cfg); writel(WDT_MODE_EN, &wdog->mode);
+Chen-Yu.
I would like to fix the reset using the R_WDOG instead of WDOG.
What do you think?
If it's acceptable I will propose a similar patch on ATF.
Regards, Clement
On Mon, 8 Apr 2019 at 18:41, Clément Péron peron.clem@gmail.com wrote:
WDOG in H6 is broken so the reset is actually not working.
Use the R_WDOG instead.
Signed-off-by: Clément Péron peron.clem@gmail.com
arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h | 1 + arch/arm/mach-sunxi/board.c | 9 +++++++-- 2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h index 41a9b0fc47..6392cb07b4 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h @@ -60,6 +60,7 @@ #define SUNXI_RTC_BASE 0x07000000 #define SUNXI_R_CPUCFG_BASE 0x07000400 #define SUNXI_PRCM_BASE 0x07010000 +#define SUNXI_R_WDOG_BASE 0x07020400 #define SUNXI_R_PIO_BASE 0x07022000 #define SUNXI_R_UART_BASE 0x07080000 #define SUNXI_R_TWI_BASE 0x07081400 diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index b74eaf2a0e..3f8128fbf4 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -287,9 +287,14 @@ void reset_cpu(ulong addr) writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); } #elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6) +#if defined(CONFIG_MACH_SUN50I_H6)
/* WDOG is broken for H6 use the R_WDOG instead */ static const struct sunxi_wdog *wdog =
((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
(struct sunxi_wdog *)SUNXI_R_WDOG_BASE;+#else
static const struct sunxi_wdog *wdog =((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;+#endif /* Set the watchdog for its shortest interval (.5s) and wait */ writel(WDT_CFG_RESET, &wdog->cfg); writel(WDT_MODE_EN, &wdog->mode); -- 2.17.1
Hi,
On Mon, 8 Apr 2019 at 18:47, Clément Péron peron.clem@gmail.com wrote:
+Chen-Yu.
I would like to fix the reset using the R_WDOG instead of WDOG.
What do you think?
Adding information about the issue as explained on ATF:
" There seems to have a HW errata in the new revision of the SoC. Only SoC used in Pine H64 and Rongpin RP-H6B seems to be NOT affected. Lot of users on OrangePi boards (Lite2 / One Plus and 3) are complaining about this issue. I personnaly own a Beelink GS1 which has the issue. My SoC is a H6 V200-AWIN H7309BA 6842 and Chen-Yu Tsai has these two boards : - Pine h64 with a SoC H6 V200-AWIN H6448BA 7782 - OrangePi Lite 2 with a SoC H6 V200-AWIN H8068BA 61C2 The Pine H64 is working fine but not OPi Lite 2.
I'm not sure if it's an HW errata or not but the result is here WDOG doesn't make these boards reboot properly which should never happen ! " https://review.trustedfirmware.org/c/TF-A/trusted-firmware-a/+/830
Clement
Regards, Clement
On Mon, 8 Apr 2019 at 18:41, Clément Péron peron.clem@gmail.com wrote:
WDOG in H6 is broken so the reset is actually not working.
Use the R_WDOG instead.
Signed-off-by: Clément Péron peron.clem@gmail.com
arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h | 1 + arch/arm/mach-sunxi/board.c | 9 +++++++-- 2 files changed, 8 insertions(+), 2 deletions(-)
diff --git a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h index 41a9b0fc47..6392cb07b4 100644 --- a/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h +++ b/arch/arm/include/asm/arch-sunxi/cpu_sun50i_h6.h @@ -60,6 +60,7 @@ #define SUNXI_RTC_BASE 0x07000000 #define SUNXI_R_CPUCFG_BASE 0x07000400 #define SUNXI_PRCM_BASE 0x07010000 +#define SUNXI_R_WDOG_BASE 0x07020400 #define SUNXI_R_PIO_BASE 0x07022000 #define SUNXI_R_UART_BASE 0x07080000 #define SUNXI_R_TWI_BASE 0x07081400 diff --git a/arch/arm/mach-sunxi/board.c b/arch/arm/mach-sunxi/board.c index b74eaf2a0e..3f8128fbf4 100644 --- a/arch/arm/mach-sunxi/board.c +++ b/arch/arm/mach-sunxi/board.c @@ -287,9 +287,14 @@ void reset_cpu(ulong addr) writel(WDT_MODE_RESET_EN | WDT_MODE_EN, &wdog->mode); } #elif defined(CONFIG_SUNXI_GEN_SUN6I) || defined(CONFIG_MACH_SUN50I_H6) +#if defined(CONFIG_MACH_SUN50I_H6)
/* WDOG is broken for H6 use the R_WDOG instead */ static const struct sunxi_wdog *wdog =
((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;
(struct sunxi_wdog *)SUNXI_R_WDOG_BASE;+#else
static const struct sunxi_wdog *wdog =((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->wdog;+#endif /* Set the watchdog for its shortest interval (.5s) and wait */ writel(WDT_CFG_RESET, &wdog->cfg); writel(WDT_MODE_EN, &wdog->mode); -- 2.17.1
There are some minor differences between U-Boot and Linux.
Sync only the minor changes.
Signed-off-by: Clément Péron peron.clem@gmail.com --- arch/arm/dts/sun50i-h6.dtsi | 12 ++++++------ 1 file changed, 6 insertions(+), 6 deletions(-)
diff --git a/arch/arm/dts/sun50i-h6.dtsi b/arch/arm/dts/sun50i-h6.dtsi index 617cea35d1..5f01314703 100644 --- a/arch/arm/dts/sun50i-h6.dtsi +++ b/arch/arm/dts/sun50i-h6.dtsi @@ -19,28 +19,28 @@ #size-cells = <0>;
cpu0: cpu@0 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <0>; enable-method = "psci"; };
cpu1: cpu@1 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <1>; enable-method = "psci"; };
cpu2: cpu@2 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <2>; enable-method = "psci"; };
cpu3: cpu@3 { - compatible = "arm,cortex-a53", "arm,armv8"; + compatible = "arm,cortex-a53"; device_type = "cpu"; reg = <3>; enable-method = "psci"; @@ -143,7 +143,7 @@ bias-pull-up; };
- uart0_ph_pins: uart0-ph { + uart0_ph_pins: uart0-ph-pins { pins = "PH0", "PH1"; function = "uart0"; }; @@ -270,7 +270,7 @@ interrupt-controller; #interrupt-cells = <3>;
- r_i2c_pins: r-i2c { + r_i2c_pins: r-i2c-pins { pins = "PL0", "PL1"; function = "s_i2c"; };
participants (2)
-
Clément Péron -
Jagan Teki