[U-Boot] [PATCH 0/7] OMAP5: Add support for OMAP5432 SOC
This patch series support OMAP5432 in Mainline U-boot. The major difference from OMAP5430 is that it supports DDR3 memory. Things to be done for supporting DDR3: 1) ioconfig for ddr3 2) Initialization sequence and ddr3 leveling 3) Change in DPLL_CORE locking sequence 4) Voltage changes
This series has been tested on OMAP4430 sdp OMAP5430sevm OMAP5432uevm
MAKEALL has been tested for all armv7 boards to ensure no build breakage.
Lokesh Vutla (7): OMAP5: Adding correct Control id code for OMAP5430 OMAP5: ADD chip detection for OMAP5432 SOC OMAP5: Configure the io settings for omap5432 uevm board OMAP5: ADD precalculated timings for ddr3 OMAP5: EMIF: Add support for DDR3 device OMAP5: DPLL core lock for OMAP5432 OMAP5: Change voltages for omap5432
arch/arm/cpu/armv7/omap-common/clocks-common.c | 8 +- arch/arm/cpu/armv7/omap-common/emif-common.c | 118 +++++++++++++++++++++-- arch/arm/cpu/armv7/omap4/hwinit.c | 5 + arch/arm/cpu/armv7/omap4/sdram_elpida.c | 1 + arch/arm/cpu/armv7/omap5/clocks.c | 31 ++++-- arch/arm/cpu/armv7/omap5/hwinit.c | 123 ++++++++++++++++++++---- arch/arm/cpu/armv7/omap5/sdram.c | 50 ++++++++++- arch/arm/include/asm/arch-omap4/clocks.h | 5 + arch/arm/include/asm/arch-omap5/clocks.h | 15 +++ arch/arm/include/asm/arch-omap5/omap.h | 18 +++- arch/arm/include/asm/emif.h | 50 ++++++++++- arch/arm/include/asm/omap_common.h | 1 + 12 files changed, 382 insertions(+), 43 deletions(-)
Control id code for omap5430 ES1.0 is hard coded with a wrong value. This patch corrects the value
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/include/asm/arch-omap5/omap.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index e3f55d2..70a38be 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -56,7 +56,7 @@ #define CONTROL_ID_CODE (CTRL_BASE + 0x204)
/* To be verified */ -#define OMAP5_CONTROL_ID_CODE_ES1_0 0x0B85202F +#define OMAP5_CONTROL_ID_CODE_ES1_0 0x0B94202F
/* STD_FUSE_PROD_ID_1 */ #define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218)
Hi Lokesh,
@@ -56,7 +56,7 @@ #define CONTROL_ID_CODE (CTRL_BASE + 0x204)
/* To be verified */ -#define OMAP5_CONTROL_ID_CODE_ES1_0 0x0B85202F +#define OMAP5_CONTROL_ID_CODE_ES1_0 0x0B94202F
ok, then the above comment /* To be verified */ can be removed as well
Thanks, Sricharan
This patch adds chip detection for OMAP5432
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/omap5/hwinit.c | 10 +++++++++- arch/arm/include/asm/arch-omap5/omap.h | 3 ++- arch/arm/include/asm/omap_common.h | 1 + 3 files changed, 12 insertions(+), 2 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index d01cc81..e2f76a1 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -154,7 +154,15 @@ void init_omap_revision(void)
switch (rev) { case MIDR_CORTEX_A15_R0P0: - *omap_si_rev = OMAP5430_ES1_0; + switch (readl(CONTROL_ID_CODE)) { + case OMAP5430_CONTROL_ID_CODE_ES1_0: + *omap_si_rev = OMAP5430_ES1_0; + break; + case OMAP5432_CONTROL_ID_CODE_ES1_0: + default: + *omap_si_rev = OMAP5432_ES1_0; + break; + } break; default: *omap_si_rev = OMAP5430_SILICON_ID_INVALID; diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 70a38be..0a4c8ec 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -56,7 +56,8 @@ #define CONTROL_ID_CODE (CTRL_BASE + 0x204)
/* To be verified */ -#define OMAP5_CONTROL_ID_CODE_ES1_0 0x0B94202F +#define OMAP5430_CONTROL_ID_CODE_ES1_0 0x0B94202F +#define OMAP5432_CONTROL_ID_CODE_ES1_0 0x0B99802F
/* STD_FUSE_PROD_ID_1 */ #define STD_FUSE_PROD_ID_1 (CTRL_BASE + 0x218) diff --git a/arch/arm/include/asm/omap_common.h b/arch/arm/include/asm/omap_common.h index 459b6b1..4e95eee 100644 --- a/arch/arm/include/asm/omap_common.h +++ b/arch/arm/include/asm/omap_common.h @@ -136,4 +136,5 @@ static inline u32 omap_revision(void) /* omap5 */ #define OMAP5430_SILICON_ID_INVALID 0 #define OMAP5430_ES1_0 0x54300100 +#define OMAP5432_ES1_0 0x54320100 #endif /* _OMAP_COMMON_H_ */
This patch adds the IO settings required for OMAP5432 uevm's DDR3 pads
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/omap5/hwinit.c | 98 +++++++++++++++++++++++++------ arch/arm/include/asm/arch-omap5/omap.h | 15 +++++- 2 files changed, 93 insertions(+), 20 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index e2f76a1..df0b760 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -52,6 +52,81 @@ static struct gpio_bank gpio_bank_54xx[6] = { const struct gpio_bank *const omap_gpio_bank = gpio_bank_54xx;
#ifdef CONFIG_SPL_BUILD +/* LPDDR2 specific IO settings */ +static void io_settings_lpddr2(void) +{ + struct omap_sys_ctrl_regs *ioregs_base = + (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; + + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, + &(ioregs_base->control_ddrch1_0)); + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, + &(ioregs_base->control_ddrch1_1)); + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, + &(ioregs_base->control_ddrch2_0)); + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, + &(ioregs_base->control_ddrch2_1)); + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, + &(ioregs_base->control_lpddr2ch1_0)); + writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, + &(ioregs_base->control_lpddr2ch1_1)); + writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL, + &(ioregs_base->control_ddrio_0)); + writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL, + &(ioregs_base->control_ddrio_1)); + writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL, + &(ioregs_base->control_ddrio_2)); +} + +/* DDR3 specific IO settings */ +static void io_settings_ddr3(void) +{ + u32 io_settings = 0; + struct omap_sys_ctrl_regs *ioregs_base = + (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; + + writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, + &(ioregs_base->control_ddr3ch1_0)); + writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, + &(ioregs_base->control_ddrch1_0)); + writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, + &(ioregs_base->control_ddrch1_1)); + + writel(DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL, + &(ioregs_base->control_ddr3ch2_0)); + writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, + &(ioregs_base->control_ddrch2_0)); + writel(DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL, + &(ioregs_base->control_ddrch2_1)); + + writel(DDR_IO_0_VREF_CELLS_DDR3_VALUE, + &(ioregs_base->control_ddrio_0)); + writel(DDR_IO_1_VREF_CELLS_DDR3_VALUE, + &(ioregs_base->control_ddrio_1)); + writel(DDR_IO_2_VREF_CELLS_DDR3_VALUE, + &(ioregs_base->control_ddrio_2)); + + /* omap5432 does not use lpddr2 */ + writel(0x0, &(ioregs_base->control_lpddr2ch1_0)); + writel(0x0, &(ioregs_base->control_lpddr2ch1_1)); + + writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, + &(ioregs_base->control_emif1_sdram_config_ext)); + writel(SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES, + &(ioregs_base->control_emif2_sdram_config_ext)); + + /* Disable DLL select */ + io_settings = (readl(&(ioregs_base->control_port_emif1_sdram_config)) + & 0xFFEFFFFF); + writel(io_settings, + &(ioregs_base->control_port_emif1_sdram_config)); + + io_settings = (readl(&(ioregs_base->control_port_emif2_sdram_config)) + & 0xFFEFFFFF); + writel(io_settings, + &(ioregs_base->control_port_emif2_sdram_config)); +} + /* * Some tuning of IOs for optimal power and performance */ @@ -115,25 +190,10 @@ void do_io_settings(void) (sc_fast << 17) | (sc_fast << 14); writel(io_settings, &(ioregs_base->control_smart3io_padconf_1));
- /* LPDDR2 io settings */ - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch1_0)); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch1_1)); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch2_0)); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_DQ_NO_PULL_DQS_PULL_DOWN, - &(ioregs_base->control_ddrch2_1)); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, - &(ioregs_base->control_lpddr2ch1_0)); - writel(DDR_IO_I_34OHM_SR_FASTEST_WD_CK_CKE_NCS_CA_PULL_DOWN, - &(ioregs_base->control_lpddr2ch1_1)); - writel(DDR_IO_0_DDR2_DQ_INT_EN_ALL_DDR3_CA_DIS_ALL, - &(ioregs_base->control_ddrio_0)); - writel(DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL, - &(ioregs_base->control_ddrio_1)); - writel(DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL, - &(ioregs_base->control_ddrio_2)); + if (omap_revision() <= OMAP5430_ES1_0) + io_settings_lpddr2(); + else + io_settings_ddr3();
/* Efuse settings */ writel(EFUSE_1, &(ioregs_base->control_efuse_1)); diff --git a/arch/arm/include/asm/arch-omap5/omap.h b/arch/arm/include/asm/arch-omap5/omap.h index 0a4c8ec..f0658d0 100644 --- a/arch/arm/include/asm/arch-omap5/omap.h +++ b/arch/arm/include/asm/arch-omap5/omap.h @@ -179,7 +179,14 @@ struct omap_sys_ctrl_regs { u32 control_srcomp_east_side; /*0x4A002E7C*/ u32 control_srcomp_west_side; /*0x4A002E80*/ u32 control_srcomp_code_latch; /*0x4A002E84*/ - u32 pad4[3680198]; + u32 pad4[3679394]; + u32 control_port_emif1_sdram_config; /*0x4AE0C110*/ + u32 control_port_emif1_lpddr2_nvm_config; /*0x4AE0C114*/ + u32 control_port_emif2_sdram_config; /*0x4AE0C118*/ + u32 pad5[10]; + u32 control_emif1_sdram_config_ext; /* 0x4AE0C144 */ + u32 control_emif2_sdram_config_ext; /* 0x4AE0C148 */ + u32 pad6[789]; u32 control_smart1nopmio_padconf_0; /* 0x4AE0CDA0 */ u32 control_smart1nopmio_padconf_1; /* 0x4AE0CDA4 */ u32 control_padconf_mode; /* 0x4AE0CDA8 */ @@ -234,6 +241,12 @@ struct omap_sys_ctrl_regs { #define DDR_IO_1_DQ_OUT_EN_ALL_DQ_INT_EN_ALL 0x8421084 #define DDR_IO_2_CA_OUT_EN_ALL_CA_INT_EN_ALL 0x8421000
+#define DDR_IO_I_40OHM_SR_SLOWEST_WD_DQ_NO_PULL_DQS_NO_PULL 0x7C7C7C6C +#define DDR_IO_I_40OHM_SR_FAST_WD_DQ_NO_PULL_DQS_NO_PULL 0x64646464 +#define DDR_IO_0_VREF_CELLS_DDR3_VALUE 0xBAE8C631 +#define DDR_IO_1_VREF_CELLS_DDR3_VALUE 0xBC6318DC +#define DDR_IO_2_VREF_CELLS_DDR3_VALUE 0x0 + #define EFUSE_1 0x45145100 #define EFUSE_2 0x45145100 #define EFUSE_3 0x45145100
Adding precalculated timings for ddr3 with 1cs adding required registers for ddr3
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/omap4/sdram_elpida.c | 1 + arch/arm/cpu/armv7/omap5/sdram.c | 50 ++++++++++++++++++++++++++++++- arch/arm/include/asm/emif.h | 5 +++ 3 files changed, 55 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap4/sdram_elpida.c b/arch/arm/cpu/armv7/omap4/sdram_elpida.c index b538960..239ad2b 100644 --- a/arch/arm/cpu/armv7/omap4/sdram_elpida.c +++ b/arch/arm/cpu/armv7/omap4/sdram_elpida.c @@ -92,6 +92,7 @@ const struct emif_regs emif_regs_elpida_400_mhz_2cs = {
/* Dummy registers for OMAP44xx */ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; +const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { .dmm_lisa_map_0 = 0xFF020100, diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index b2b5753..bf7a42e 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -86,6 +86,29 @@ const struct emif_regs emif_regs_266_mhz_2cs = { .emif_ddr_ext_phy_ctrl_5 = 0x04010040 };
+const struct emif_regs emif_regs_ddr3_532_mhz_1cs = { + .sdram_config_init = 0x61851B32, + .sdram_config = 0x61851B32, + .ref_ctrl = 0x00001035, + .sdram_tim1 = 0xCCCF36B3, + .sdram_tim2 = 0x308F7FDA, + .sdram_tim3 = 0x027F88A8, + .read_idle_ctrl = 0x00050000, + .zq_config = 0x0007190B, + .temp_alert_config = 0x00000000, + .emif_ddr_phy_ctlr_1_init = 0x0020420A, + .emif_ddr_phy_ctlr_1 = 0x0024420A, + .emif_ddr_ext_phy_ctrl_1 = 0x04040100, + .emif_ddr_ext_phy_ctrl_2 = 0x00000000, + .emif_ddr_ext_phy_ctrl_3 = 0x00000000, + .emif_ddr_ext_phy_ctrl_4 = 0x00000000, + .emif_ddr_ext_phy_ctrl_5 = 0x04010040, + .emif_rd_wr_lvl_rmp_win = 0x00000000, + .emif_rd_wr_lvl_rmp_ctl = 0x80000000, + .emif_rd_wr_lvl_ctl = 0x00000000, + .emif_rd_wr_exec_thresh = 0x00000305 +}; + const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .dmm_lisa_map_0 = 0x0, .dmm_lisa_map_1 = 0, @@ -115,9 +138,34 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x00000077 };
+const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { + 0x01004010, + 0x00001004, + 0x04010040, + 0x01004010, + 0x00001004, + 0x00000000, + 0x00000000, + 0x00000000, + 0x80080080, + 0x00800800, + 0x08102040, + 0x00000002, + 0x0, + 0x0, + 0x0, + 0x00000000, + 0x00000000, + 0x00000000, + 0x00000057 +}; + static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) { - *regs = &emif_regs_532_mhz_2cs; + if (omap_revision() == OMAP5432_ES1_0) + *regs = &emif_regs_ddr3_532_mhz_1cs; + else + *regs = &emif_regs_532_mhz_2cs; } void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) __attribute__((weak, alias("emif_get_reg_dump_sdp"))); diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index f1e3ad2..5d2649e 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -650,6 +650,7 @@ struct dmm_lisa_map_regs { };
extern const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; +extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
#define CS0 0 #define CS1 1 @@ -1073,6 +1074,10 @@ struct emif_regs { u32 emif_ddr_ext_phy_ctrl_3; u32 emif_ddr_ext_phy_ctrl_4; u32 emif_ddr_ext_phy_ctrl_5; + u32 emif_rd_wr_lvl_rmp_win; + u32 emif_rd_wr_lvl_rmp_ctl; + u32 emif_rd_wr_lvl_ctl; + u32 emif_rd_wr_exec_thresh; };
/* assert macros */
Hi Lokesh,
Adding precalculated timings for ddr3 with 1cs adding required registers for ddr3
You want to mention the part name as well ?
nit in subject : and defining the additional registers required for DDR3.
[snip..]
/* Dummy registers for OMAP44xx */ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; +const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
const struct dmm_lisa_map_regs lisa_map_2G_x_1_x_2 = { .dmm_lisa_map_0 = 0xFF020100, diff --git a/arch/arm/cpu/armv7/omap5/sdram.c b/arch/arm/cpu/armv7/omap5/sdram.c index b2b5753..bf7a42e 100644 --- a/arch/arm/cpu/armv7/omap5/sdram.c +++ b/arch/arm/cpu/armv7/omap5/sdram.c @@ -86,6 +86,29 @@ const struct emif_regs emif_regs_266_mhz_2cs = { .emif_ddr_ext_phy_ctrl_5 = 0x04010040 };
+const struct emif_regs emif_regs_ddr3_532_mhz_1cs = {
- .sdram_config_init = 0x61851B32,
- .sdram_config = 0x61851B32,
- .ref_ctrl = 0x00001035,
- .sdram_tim1 = 0xCCCF36B3,
- .sdram_tim2 = 0x308F7FDA,
- .sdram_tim3 = 0x027F88A8,
- .read_idle_ctrl = 0x00050000,
- .zq_config = 0x0007190B,
- .temp_alert_config = 0x00000000,
- .emif_ddr_phy_ctlr_1_init = 0x0020420A,
- .emif_ddr_phy_ctlr_1 = 0x0024420A,
- .emif_ddr_ext_phy_ctrl_1 = 0x04040100,
- .emif_ddr_ext_phy_ctrl_2 = 0x00000000,
- .emif_ddr_ext_phy_ctrl_3 = 0x00000000,
- .emif_ddr_ext_phy_ctrl_4 = 0x00000000,
- .emif_ddr_ext_phy_ctrl_5 = 0x04010040,
- .emif_rd_wr_lvl_rmp_win = 0x00000000,
- .emif_rd_wr_lvl_rmp_ctl = 0x80000000,
- .emif_rd_wr_lvl_ctl = 0x00000000,
- .emif_rd_wr_exec_thresh = 0x00000305
+};
const struct dmm_lisa_map_regs lisa_map_4G_x_2_x_2 = { .dmm_lisa_map_0 = 0x0, .dmm_lisa_map_1 = 0, @@ -115,9 +138,34 @@ const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = { 0x00000077 };
+const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG] = {
- 0x01004010,
- 0x00001004,
- 0x04010040,
- 0x01004010,
- 0x00001004,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x80080080,
- 0x00800800,
- 0x08102040,
- 0x00000002,
- 0x0,
- 0x0,
- 0x0,
- 0x00000000,
- 0x00000000,
- 0x00000000,
- 0x00000057
+};
static void emif_get_reg_dump_sdp(u32 emif_nr, const struct emif_regs **regs) {
- *regs = &emif_regs_532_mhz_2cs;
- if (omap_revision() == OMAP5432_ES1_0)
- *regs = &emif_regs_ddr3_532_mhz_1cs;
- else
- *regs = &emif_regs_532_mhz_2cs;
} void emif_get_reg_dump(u32 emif_nr, const struct emif_regs **regs) __attribute__((weak, alias("emif_get_reg_dump_sdp"))); diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index f1e3ad2..5d2649e 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -650,6 +650,7 @@ struct dmm_lisa_map_regs { };
extern const u32 ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG]; +extern const u32 ddr3_ext_phy_ctrl_const_base[EMIF_EXT_PHY_CTRL_CONST_REG];
#define CS0 0 #define CS1 1 @@ -1073,6 +1074,10 @@ struct emif_regs { u32 emif_ddr_ext_phy_ctrl_3; u32 emif_ddr_ext_phy_ctrl_4; u32 emif_ddr_ext_phy_ctrl_5;
- u32 emif_rd_wr_lvl_rmp_win;
- u32 emif_rd_wr_lvl_rmp_ctl;
- u32 emif_rd_wr_lvl_ctl;
- u32 emif_rd_wr_exec_thresh;
};
/* assert macros */
Thanks, Sricharan
In OMAP5432 EMIF controlller supports DDR3 device. This patch adds support for ddr3 device intialization and configuration. Initialization sequence is done as specified in JEDEC specs. This also adds support for ddr3 leveling.
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/omap-common/emif-common.c | 105 +++++++++++++++++++++++++- arch/arm/cpu/armv7/omap4/hwinit.c | 5 + arch/arm/cpu/armv7/omap5/hwinit.c | 15 ++++ arch/arm/include/asm/emif.h | 45 +++++++++++- 4 files changed, 166 insertions(+), 4 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index db509c9..0668fe4 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -190,7 +190,7 @@ void emif_update_timings(u32 base, const struct emif_regs *regs) writel(regs->temp_alert_config, &emif->emif_temp_alert_config); writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw);
- if (omap_revision() == OMAP5430_ES1_0) { + if (omap_revision() >= OMAP5430_ES1_0) { writel(EMIF_L3_CONFIG_VAL_SYS_10_MPU_5_LL_0, &emif->emif_l3_config); } else if (omap_revision() >= OMAP4460_ES1_0) { @@ -202,6 +202,101 @@ void emif_update_timings(u32 base, const struct emif_regs *regs) } }
+static void ddr3_leveling(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + + /* keep sdram in self-refresh */ + writel(((LP_MODE_SELF_REFRESH << EMIF_REG_LP_MODE_SHIFT) + & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); + __udelay(130); + + /* + * Set invert_clkout (if activated)--DDR_PHYCTRL_1 + * Invert clock adds an additional half cycle delay on the command + * interface. The additional half cycle, is usually meant to enable + * leveling in the situation that DQS is later than CK on the board.It + * also helps provide some additional margin for leveling. + */ + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1); + writel(regs->emif_ddr_phy_ctlr_1, &emif->emif_ddr_phy_ctrl_1_shdw); + __udelay(130); + + writel(((LP_MODE_DISABLE << EMIF_REG_LP_MODE_SHIFT) + & EMIF_REG_LP_MODE_MASK), &emif->emif_pwr_mgmt_ctrl); + + /* Launch Full leveling */ + writel(DDR3_FULL_LVL, &emif->emif_rd_wr_lvl_ctl); + + /* Wait till full leveling is complete */ + readl(&emif->emif_rd_wr_lvl_ctl); + __udelay(130); + + /* Read data eye leveling no of samples */ + config_data_eye_leveling_samples(base); + + /* Launch 8 incremental WR_LVL- to compensate for PHY limitation */ + writel(0x2 << EMIF_REG_WRLVLINC_INT_SHIFT, &emif->emif_rd_wr_lvl_ctl); + __udelay(130); + + /* Launch Incremental leveling */ + writel(DDR3_INC_LVL, &emif->emif_rd_wr_lvl_ctl); + __udelay(130); +} + +static void ddr3_init(u32 base, const struct emif_regs *regs) +{ + struct emif_reg_struct *emif = (struct emif_reg_struct *)base; + u32 *ext_phy_ctrl_base = 0; + u32 *emif_ext_phy_ctrl_base = 0; + u32 i = 0; + + /* + * Set SDRAM_CONFIG and PHY control registers to locked frequency + * and RL =7. As the default values of the Mode Registers are not + * defined, contents of mode Registers must be fully initialized. + * H/W takes care of this initialization + */ + writel(regs->sdram_config_init, &emif->emif_sdram_config); + + writel(regs->emif_ddr_phy_ctlr_1_init, &emif->emif_ddr_phy_ctrl_1); + + /* Update timing registers */ + writel(regs->sdram_tim1, &emif->emif_sdram_tim_1); + writel(regs->sdram_tim2, &emif->emif_sdram_tim_2); + writel(regs->sdram_tim3, &emif->emif_sdram_tim_3); + + writel(regs->ref_ctrl, &emif->emif_sdram_ref_ctrl); + writel(regs->read_idle_ctrl, &emif->emif_read_idlectrl); + + ext_phy_ctrl_base = (u32 *) &(regs->emif_ddr_ext_phy_ctrl_1); + emif_ext_phy_ctrl_base = (u32 *) &(emif->emif_ddr_ext_phy_ctrl_1); + + /* Configure external phy control timing registers */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_TIMING_REG; i++) { + writel(*ext_phy_ctrl_base, emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(*ext_phy_ctrl_base++, emif_ext_phy_ctrl_base++); + } + + /* + * external phy 6-24 registers do not change with + * ddr frequency + */ + for (i = 0; i < EMIF_EXT_PHY_CTRL_CONST_REG; i++) { + writel(ddr3_ext_phy_ctrl_const_base[i], + emif_ext_phy_ctrl_base++); + /* Update shadow registers */ + writel(ddr3_ext_phy_ctrl_const_base[i], + emif_ext_phy_ctrl_base++); + } + + /* enable leveling */ + writel(regs->emif_rd_wr_lvl_rmp_ctl, &emif->emif_rd_wr_lvl_rmp_ctl); + + ddr3_leveling(base, regs); +} + #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS #define print_timing_reg(reg) debug(#reg" - 0x%08x\n", (reg))
@@ -975,8 +1070,12 @@ static void do_sdram_init(u32 base) * Changing the timing registers in EMIF can happen(going from one * OPP to another) */ - if (!in_sdram) - lpddr2_init(base, regs); + if (!in_sdram) { + if (omap_revision() != OMAP5432_ES1_0) + lpddr2_init(base, regs); + else + ddr3_init(base, regs); + }
/* Write to the shadow registers */ emif_update_timings(base, regs); diff --git a/arch/arm/cpu/armv7/omap4/hwinit.c b/arch/arm/cpu/armv7/omap4/hwinit.c index 187e938..2c34e48 100644 --- a/arch/arm/cpu/armv7/omap4/hwinit.c +++ b/arch/arm/cpu/armv7/omap4/hwinit.c @@ -118,6 +118,11 @@ void do_io_settings(void) } #endif
+/* dummy fuction for omap4 */ +void config_data_eye_leveling_samples(u32 emif_base) +{ +} + void init_omap_revision(void) { /* diff --git a/arch/arm/cpu/armv7/omap5/hwinit.c b/arch/arm/cpu/armv7/omap5/hwinit.c index df0b760..d0c3ff7 100644 --- a/arch/arm/cpu/armv7/omap5/hwinit.c +++ b/arch/arm/cpu/armv7/omap5/hwinit.c @@ -35,6 +35,7 @@ #include <asm/sizes.h> #include <asm/utils.h> #include <asm/arch/gpio.h> +#include <asm/emif.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -203,6 +204,20 @@ void do_io_settings(void) } #endif
+void config_data_eye_leveling_samples(u32 emif_base) +{ + struct omap_sys_ctrl_regs *ioregs_base = + (struct omap_sys_ctrl_regs *) SYSCTRL_GENERAL_CORE_BASE; + + /*EMIF_SDRAM_CONFIG_EXT-Read data eye leveling no of samples =4*/ + if (emif_base == EMIF1_BASE) + writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, + &(ioregs_base->control_emif1_sdram_config_ext)); + else if (emif_base == EMIF2_BASE) + writel(SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES, + &(ioregs_base->control_emif2_sdram_config_ext)); +} + void init_omap_revision(void) { /* diff --git a/arch/arm/include/asm/emif.h b/arch/arm/include/asm/emif.h index 5d2649e..c2ad877 100644 --- a/arch/arm/include/asm/emif.h +++ b/arch/arm/include/asm/emif.h @@ -471,6 +471,49 @@ #define EMIF_REG_DDR_PHY_CTRL_2_SHIFT 0 #define EMIF_REG_DDR_PHY_CTRL_2_MASK (0xffffffff << 0)
+/*EMIF_READ_WRITE_LEVELING_CONTROL*/ +#define EMIF_REG_RDWRLVLFULL_START_SHIFT 31 +#define EMIF_REG_RDWRLVLFULL_START_MASK (1 << 31) +#define EMIF_REG_RDWRLVLINC_PRE_SHIFT 24 +#define EMIF_REG_RDWRLVLINC_PRE_MASK (0x7F << 24) +#define EMIF_REG_RDLVLINC_INT_SHIFT 16 +#define EMIF_REG_RDLVLINC_INT_MASK (0xFF << 16) +#define EMIF_REG_RDLVLGATEINC_INT_SHIFT 8 +#define EMIF_REG_RDLVLGATEINC_INT_MASK (0xFF << 8) +#define EMIF_REG_WRLVLINC_INT_SHIFT 0 +#define EMIF_REG_WRLVLINC_INT_MASK (0xFF << 0) + +/*EMIF_READ_WRITE_LEVELING_RAMP_CONTROL*/ +#define EMIF_REG_RDWRLVL_EN_SHIFT 31 +#define EMIF_REG_RDWRLVL_EN_MASK (1 << 31) +#define EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT 24 +#define EMIF_REG_RDWRLVLINC_RMP_PRE_MASK (0x7F << 24) +#define EMIF_REG_RDLVLINC_RMP_INT_SHIFT 16 +#define EMIF_REG_RDLVLINC_RMP_INT_MASK (0xFF << 16) +#define EMIF_REG_RDLVLGATEINC_RMP_INT_SHIFT 8 +#define EMIF_REG_RDLVLGATEINC_RMP_INT_MASK (0xFF << 8) +#define EMIF_REG_WRLVLINC_RMP_INT_SHIFT 0 +#define EMIF_REG_WRLVLINC_RMP_INT_MASK (0xFF << 0) + +/*EMIF_READ_WRITE_LEVELING_RAMP_WINDOW*/ +#define EMIF_REG_RDWRLVLINC_RMP_WIN_SHIFT 0 +#define EMIF_REG_RDWRLVLINC_RMP_WIN_MASK (0x1FFF << 0) + +/*Leveling Fields */ +#define DDR3_WR_LVL_INT 0x73 +#define DDR3_RD_LVL_INT 0x33 +#define DDR3_RD_LVL_GATE_INT 0x59 +#define RD_RW_LVL_INC_PRE 0x0 +#define DDR3_FULL_LVL (1 << EMIF_REG_RDWRLVL_EN_SHIFT) + +#define DDR3_INC_LVL ((DDR3_WR_LVL_INT << EMIF_REG_WRLVLINC_INT_SHIFT) \ + | (DDR3_RD_LVL_GATE_INT << EMIF_REG_RDLVLGATEINC_INT_SHIFT) \ + | (DDR3_RD_LVL_INT << EMIF_REG_RDLVLINC_RMP_INT_SHIFT) \ + | (RD_RW_LVL_INC_PRE << EMIF_REG_RDWRLVLINC_RMP_PRE_SHIFT)) + +#define SDRAM_CONFIG_EXT_RD_LVL_11_SAMPLES 0x0000C1A7 +#define SDRAM_CONFIG_EXT_RD_LVL_4_SAMPLES 0x000001A7 + /* DMM */ #define DMM_BASE 0x4E000040
@@ -1104,5 +1147,5 @@ extern u32 *const T_den; extern u32 *const emif_sizes; #endif
- +void config_data_eye_leveling_samples(u32 emif_base); #endif
On Tue, May 22, 2012 at 03:33:25PM +0530, Lokesh Vutla wrote:
In OMAP5432 EMIF controlller supports DDR3 device. This patch adds support for ddr3 device intialization and configuration. Initialization sequence is done as specified in JEDEC specs. This also adds support for ddr3 leveling.
[snip]
@@ -975,8 +1070,12 @@ static void do_sdram_init(u32 base) * Changing the timing registers in EMIF can happen(going from one * OPP to another) */
- if (!in_sdram)
lpddr2_init(base, regs);
- if (!in_sdram) {
if (omap_revision() != OMAP5432_ES1_0)lpddr2_init(base, regs);elseddr3_init(base, regs);- }
In omap4+ land do we have any other way of telling which family we're on? I ask since I'm preparing to add DDR3 support to am33xx and I'd like to switch it over to the common emif framework as well.
Hi Tom,
In OMAP5432 EMIF controlller supports DDR3 device. This patch adds support for ddr3 device intialization and configuration. Initialization sequence is done as specified in JEDEC specs. This also adds support for ddr3 leveling.
[snip]
@@ -975,8 +1070,12 @@ static void do_sdram_init(u32 base) * Changing the timing registers in EMIF can happen(going from one * OPP to another) */
- if (!in_sdram)
- lpddr2_init(base, regs);
- if (!in_sdram) {
- if (omap_revision() != OMAP5432_ES1_0)
- lpddr2_init(base, regs);
- else
- ddr3_init(base, regs);
- }
In omap4+ land do we have any other way of telling which family we're on? I ask since I'm preparing to add DDR3 support to am33xx and I'd like to switch it over to the common emif framework as well.
I think the SDRAM_TYPE[31:29] EMIF_SDRAM_CONFIG register should tell the connected device at reset. I will cross confirm this on the board and tell.
That being true, we can get rid of these OMAP based checks and have generic code.
Thanks, Sricharan
On Tue, May 22, 2012 at 08:28:55PM +0530, R, Sricharan wrote:
Hi Tom,
In OMAP5432 EMIF controlller supports DDR3 device. This patch adds support for ddr3 device intialization and configuration. Initialization sequence is done as specified in JEDEC specs. This also adds support for ddr3 leveling.
[snip]
@@ -975,8 +1070,12 @@ static void do_sdram_init(u32 base) ? ? ? ?* Changing the timing registers in EMIF can happen(going from one ? ? ? ?* OPP to another) ? ? ? ?*/
- ? ? if (!in_sdram)
- ? ? ? ? ? ? lpddr2_init(base, regs);
- ? ? if (!in_sdram) {
- ? ? ? ? ? ? if (omap_revision() != OMAP5432_ES1_0)
- ? ? ? ? ? ? ? ? ? ? lpddr2_init(base, regs);
- ? ? ? ? ? ? else
- ? ? ? ? ? ? ? ? ? ? ddr3_init(base, regs);
- ? ? }
In omap4+ land do we have any other way of telling which family we're on? ?I ask since I'm preparing to add DDR3 support to am33xx and I'd like to switch it over to the common emif framework as well.
I think the SDRAM_TYPE[31:29] EMIF_SDRAM_CONFIG register should tell the connected device at reset. I will cross confirm this on the board and tell.
OK. I can't find the omap5430 TRM quickly but on the am335x one, SDRAM_TYPE is 3 for DDR3, 2 for DDR2 and 1 for LPDDR1 and 0 for DDR1.
- ? ? if (!in_sdram)
- ? ? ? ? ? ? lpddr2_init(base, regs);
- ? ? if (!in_sdram) {
- ? ? ? ? ? ? if (omap_revision() != OMAP5432_ES1_0)
- ? ? ? ? ? ? ? ? ? ? lpddr2_init(base, regs);
- ? ? ? ? ? ? else
- ? ? ? ? ? ? ? ? ? ? ddr3_init(base, regs);
- ? ? }
In omap4+ land do we have any other way of telling which family we're on? ?I ask since I'm preparing to add DDR3 support to am33xx and I'd like to switch it over to the common emif framework as well.
I think the SDRAM_TYPE[31:29] EMIF_SDRAM_CONFIG register should tell the connected device at reset. I will cross confirm this on the board and tell.
OK. I can't find the omap5430 TRM quickly but on the am335x one, SDRAM_TYPE is 3 for DDR3, 2 for DDR2 and 1 for LPDDR1 and 0 for DDR1.
ah, this is what is there on OMAP5. 3 for DDR3 4 for LPDDR2-S4, 5 for LPDDR2-S2
Atleast DDR3 encoding is same. So we can differentiate bw DDR3 and 2 in same way. Is the reset value set correctly on am335x according to the device connected?
Thanks, Sricharan
On 05/22/2012 08:27 AM, R, Sricharan wrote:
- ? ? if (!in_sdram)
- ? ? ? ? ? ? lpddr2_init(base, regs);
- ? ? if (!in_sdram) {
- ? ? ? ? ? ? if (omap_revision() != OMAP5432_ES1_0)
- ? ? ? ? ? ? ? ? ? ? lpddr2_init(base, regs);
- ? ? ? ? ? ? else
- ? ? ? ? ? ? ? ? ? ? ddr3_init(base, regs);
- ? ? }
In omap4+ land do we have any other way of telling which family we're on? ?I ask since I'm preparing to add DDR3 support to am33xx and I'd like to switch it over to the common emif framework as well.
I think the SDRAM_TYPE[31:29] EMIF_SDRAM_CONFIG register should tell the connected device at reset. I will cross confirm this on the board and tell.
OK. I can't find the omap5430 TRM quickly but on the am335x one, SDRAM_TYPE is 3 for DDR3, 2 for DDR2 and 1 for LPDDR1 and 0 for DDR1.
ah, this is what is there on OMAP5. 3 for DDR3 4 for LPDDR2-S4, 5 for LPDDR2-S2
4/5 are listed as reserved here :( http://www.ti.com/lit/pdf/spruh73
Atleast DDR3 encoding is same. So we can differentiate bw DDR3 and 2 in same way. Is the reset value set correctly on am335x according to the device connected?
I'll have to do some checking as the code doesn't check that today.
Hi Tom,
ah, this is what is there on OMAP5. 3 for DDR3 4 for LPDDR2-S4, 5 for LPDDR2-S2
4/5 are listed as reserved here :( http://www.ti.com/lit/pdf/spruh73
Atleast DDR3 encoding is same. So we can differentiate bw DDR3 and 2 in same way. Is the reset value set correctly on am335x according to the device connected?
I'll have to do some checking as the code doesn't check that today.
The reset value reflects the connected device correctly for lpddr2 and ddr3. Is that the same case in am33xx platforms ?
Thanks, Sricharan
On 05/23/2012 05:22 AM, R, Sricharan wrote:
Hi Tom,
ah, this is what is there on OMAP5. 3 for DDR3 4 for LPDDR2-S4, 5 for LPDDR2-S2
4/5 are listed as reserved here :( http://www.ti.com/lit/pdf/spruh73
Atleast DDR3 encoding is same. So we can differentiate bw DDR3 and 2 in same way. Is the reset value set correctly on am335x according to the device connected?
I'll have to do some checking as the code doesn't check that today.
The reset value reflects the connected device correctly for lpddr2 and ddr3. Is that the same case in am33xx platforms ?
Yes, it's 3 on DDR3 and 2 on (non-LP) DDR2. I spent some time yesterday starting on splitting up emif-common (am33xx does not have DMM) and making am33xx link at least with the common code. My idea is to add a few more defines and make that part of do_sdram_init be: if (!in_sdram) { switch(reg_sdram_type) { #ifdef CONFIG_EMIF4_DDR2 case 2: ddr2_init(); break; #ifdef CONFIG_EMFI4_DDR3 case 3: ddr3_init(); break; #endif #ifdef CONFIG_EMIF4_LPDDR2 case 4: case 5: lpddr2_init(); break; #endif default: panic("Unsupported DDR type connected to EMIF4"); } }
And move lpddr2_init to emif4-lpddr2.c, and so forth. My experimenting yesterday lead me to conclude that EMIF_MOD_ID_REGISTER behaves as is documented for am33xx on omap4/5 so what we're doing should be feasible. I'm going to try and locally make the ddr3 patches work on the am33xx DDR3 board as a way to prove that out and if it works, and we're fine with what I've laid out above, start working towards that layout.
Hi Tom,
ah, this is what is there on OMAP5. 3 for DDR3 4 for LPDDR2-S4, 5 for LPDDR2-S2
4/5 are listed as reserved here :( http://www.ti.com/lit/pdf/spruh73
Atleast DDR3 encoding is same. So we can differentiate bw DDR3 and 2 in same way. Is the reset value set correctly on am335x according to the device connected?
I'll have to do some checking as the code doesn't check that today.
The reset value reflects the connected device correctly for lpddr2 and ddr3. Is that the same case in am33xx platforms ?
Yes, it's 3 on DDR3 and 2 on (non-LP) DDR2. I spent some time yesterday starting on splitting up emif-common (am33xx does not have DMM) and making am33xx link at least with the common code. My idea is to add a few more defines and make that part of do_sdram_init be: if (!in_sdram) { switch(reg_sdram_type) { #ifdef CONFIG_EMIF4_DDR2 case 2: ddr2_init(); break; #ifdef CONFIG_EMFI4_DDR3 case 3: ddr3_init(); break; #endif #ifdef CONFIG_EMIF4_LPDDR2 case 4: case 5: lpddr2_init(); break; #endif default: panic("Unsupported DDR type connected to EMIF4"); } }
And move lpddr2_init to emif4-lpddr2.c, and so forth. My experimenting yesterday lead me to conclude that EMIF_MOD_ID_REGISTER behaves as is documented for am33xx on omap4/5 so what we're doing should be feasible.
ok, and there are only few omap checks that are in the common lpddr2 and ddr3 init paths, that we should be able to get rid of, so we can have generic lpddr2_init and ddr3_init. But anyways as you said we can do all these only after the current code works for DDR3 on your am33xx.
I'm going to try and locally make the ddr3 patches work on the am33xx DDR3 board as a way to prove that out and if it works, and we're fine with what I've laid out above, start working towards that layout.
yeah, sounds correct. How about something like this, similar to the above #define DDR2 1 #define LPDDR2 2 #define DDR3 3 #define LPDDR3 4
and soc specific code returns the correct ddr type. For OMAP get_ddr_type() { switch(EMIF_SDRAM_CONFIG & SDRAM_TYPE) { case 3: return DDR3; case 4: case 5: default: return LPDDR2; } We can avoid the #ifdef s in the emif code and use the type returned by SOC to do the required initialisations. ?
Thanks, Sricharan
On Thu, May 24, 2012 at 12:15:23PM +0530, R, Sricharan wrote:
Hi Tom,
[snip]
?I'm going to try and locally make the ddr3 patches work on the am33xx DDR3 board as a way to prove that out and if it works, and we're fine with what I've laid out above, start working towards that layout.
yeah, sounds correct. How about something like this, similar to the above #define DDR2 1 #define LPDDR2 2 #define DDR3 3 #define LPDDR3 4
and soc specific code returns the correct ddr type. For OMAP get_ddr_type() { switch(EMIF_SDRAM_CONFIG & SDRAM_TYPE) { case 3: return DDR3; case 4: case 5: default: return LPDDR2; } We can avoid the #ifdef s in the emif code and use the type returned by SOC to do the required initialisations. ?
One thing I want to avoid is bloating each of the boards with DDR config code it won't ever use. OMAP4/5 won't have DDR2 and AM33xx won't have LPDDR2. But maybe there's some linker magic we can do to avoid #ifdefs.
No need to Unlock DPLL initially. DDR3 can work at normal OPP from initialozation
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/omap-common/clocks-common.c | 8 ++++++-- arch/arm/cpu/armv7/omap-common/emif-common.c | 13 +++++++++---- arch/arm/include/asm/arch-omap4/clocks.h | 5 +++++ arch/arm/include/asm/arch-omap5/clocks.h | 5 +++++ 4 files changed, 25 insertions(+), 6 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap-common/clocks-common.c b/arch/arm/cpu/armv7/omap-common/clocks-common.c index 10d286a..b1fd277 100644 --- a/arch/arm/cpu/armv7/omap-common/clocks-common.c +++ b/arch/arm/cpu/armv7/omap-common/clocks-common.c @@ -299,8 +299,12 @@ static void setup_dplls(void) * Core DPLL will be locked after setting up EMIF * using the FREQ_UPDATE method(freq_update_core()) */ - do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, DPLL_NO_LOCK, - "core"); + if (omap_revision() != OMAP5432_ES1_0) + do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, + DPLL_NO_LOCK, "core"); + else + do_setup_dpll(&prcm->cm_clkmode_dpll_core, params, + DPLL_LOCK, "core"); /* Set the ratios for CORE_CLK, L3_CLK, L4_CLK */ temp = (CLKSEL_CORE_X2_DIV_1 << CLKSEL_CORE_SHIFT) | (CLKSEL_L3_CORE_DIV_2 << CLKSEL_L3_SHIFT) | diff --git a/arch/arm/cpu/armv7/omap-common/emif-common.c b/arch/arm/cpu/armv7/omap-common/emif-common.c index 0668fe4..5cb4cee 100644 --- a/arch/arm/cpu/armv7/omap-common/emif-common.c +++ b/arch/arm/cpu/armv7/omap-common/emif-common.c @@ -1232,6 +1232,7 @@ void dmm_init(u32 base) void sdram_init(void) { u32 in_sdram, size_prog, size_detect; + u32 omap_rev = omap_revision();
debug(">>sdram_init()\n");
@@ -1241,9 +1242,12 @@ void sdram_init(void) in_sdram = running_from_sdram(); debug("in_sdram = %d\n", in_sdram);
- if (!in_sdram) - bypass_dpll(&prcm->cm_clkmode_dpll_core); - + if (!in_sdram) { + if (omap_rev != OMAP5432_ES1_0) + bypass_dpll(&prcm->cm_clkmode_dpll_core); + else + writel(CM_DLL_CTRL_NO_OVERRIDE, &prcm->cm_dll_ctrl); + }
do_sdram_init(EMIF1_BASE); do_sdram_init(EMIF2_BASE); @@ -1255,7 +1259,8 @@ void sdram_init(void) }
/* for the shadow registers to take effect */ - freq_update_core(); + if (omap_rev != OMAP5432_ES1_0) + freq_update_core();
/* Do some testing after the init */ if (!in_sdram) { diff --git a/arch/arm/include/asm/arch-omap4/clocks.h b/arch/arm/include/asm/arch-omap4/clocks.h index 617729c..be20fc0 100644 --- a/arch/arm/include/asm/arch-omap4/clocks.h +++ b/arch/arm/include/asm/arch-omap4/clocks.h @@ -525,6 +525,11 @@ struct omap4_scrm_regs {
#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */
+/* CM_DLL_CTRL */ +#define CM_DLL_CTRL_OVERRIDE_SHIFT 0 +#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) +#define CM_DLL_CTRL_NO_OVERRIDE 0 + /* CM_CLKMODE_DPLL */ #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11) diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index f32cf3e..409e0e3 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -490,6 +490,11 @@ struct omap5_prcm_regs {
#define DPLL_CLKOUT_DIV_MASK 0x1F /* post-divider mask */
+/* CM_DLL_CTRL */ +#define CM_DLL_CTRL_OVERRIDE_SHIFT 0 +#define CM_DLL_CTRL_OVERRIDE_MASK (1 << 0) +#define CM_DLL_CTRL_NO_OVERRIDE 0 + /* CM_CLKMODE_DPLL */ #define CM_CLKMODE_DPLL_REGM4XEN_SHIFT 11 #define CM_CLKMODE_DPLL_REGM4XEN_MASK (1 << 11)
Hi Lokesh,
No need to Unlock DPLL initially. DDR3 can work at normal OPP from initialozation
Why is it so ? The commit log should make it clear why is it nessecary to do the initialisations at higher frequency and that becomes the reason for this patch.
Thanks, Sricharan
Change voltages for OMAP5432
Signed-off-by: Lokesh Vutla lokeshvutla@ti.com --- arch/arm/cpu/armv7/omap5/clocks.c | 31 ++++++++++++++++++++--------- arch/arm/include/asm/arch-omap5/clocks.h | 10 +++++++++ 2 files changed, 31 insertions(+), 10 deletions(-)
diff --git a/arch/arm/cpu/armv7/omap5/clocks.c b/arch/arm/cpu/armv7/omap5/clocks.c index 1a59f26..65dc5c7 100644 --- a/arch/arm/cpu/armv7/omap5/clocks.c +++ b/arch/arm/cpu/armv7/omap5/clocks.c @@ -260,20 +260,31 @@ const struct dpll_params *get_abe_dpll_params(void) */ void scale_vcores(void) { - u32 volt; + u32 volt_core, volt_mpu, volt_mm;
omap_vc_init(PRM_VC_I2C_CHANNEL_FREQ_KHZ);
/* Palmas settings */ - volt = VDD_CORE; - do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt); - - volt = VDD_MPU; - do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt); - - volt = VDD_MM; - do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt); - + if (omap_revision() != OMAP5432_ES1_0) { + volt_core = VDD_CORE; + volt_mpu = VDD_MPU; + volt_mm = VDD_MM; + } else { + volt_core = VDD_CORE_5432; + volt_mpu = VDD_MPU_5432; + volt_mm = VDD_MM_5432; + } + + do_scale_vcore(SMPS_REG_ADDR_8_CORE, volt_core); + do_scale_vcore(SMPS_REG_ADDR_12_MPU, volt_mpu); + do_scale_vcore(SMPS_REG_ADDR_45_IVA, volt_mm); + + if (omap_revision() == OMAP5432_ES1_0) { + /* Configure LDO SRAM "magic" bits */ + writel(2, &prcm->prm_sldo_core_setup); + writel(2, &prcm->prm_sldo_mpu_setup); + writel(2, &prcm->prm_sldo_mm_setup); + } }
u32 get_offset_code(u32 volt_offset) diff --git a/arch/arm/include/asm/arch-omap5/clocks.h b/arch/arm/include/asm/arch-omap5/clocks.h index 409e0e3..5f1a7aa 100644 --- a/arch/arm/include/asm/arch-omap5/clocks.h +++ b/arch/arm/include/asm/arch-omap5/clocks.h @@ -480,6 +480,13 @@ struct omap5_prcm_regs { u32 pad217[4]; u32 prm_vc_cfg_i2c_mode; /* 4ae07bb4 */ u32 prm_vc_cfg_i2c_clk; /* 4ae07bb8 */ + u32 pad218[2]; + u32 prm_sldo_core_setup; /* 4ae07bc4 */ + u32 prm_sldo_core_ctrl; /* 4ae07bc8 */ + u32 prm_sldo_mpu_setup; /* 4ae07bcc */ + u32 prm_sldo_mpu_ctrl; /* 4ae07bd0 */ + u32 prm_sldo_mm_setup; /* 4ae07bd4 */ + u32 prm_sldo_mm_ctrl; /* 4ae07bd8 */ };
/* DPLL register offsets */ @@ -646,6 +653,9 @@ struct omap5_prcm_regs { #define VDD_MPU 1000 #define VDD_MM 1000 #define VDD_CORE 1040 +#define VDD_MPU_5432 1150 +#define VDD_MM_5432 1150 +#define VDD_CORE_5432 1150
/* Standard offset is 0.5v expressed in uv */ #define PALMAS_SMPS_BASE_VOLT_UV 500000
On Tue, May 22, 2012 at 03:33:20PM +0530, Lokesh Vutla wrote:
This patch series support OMAP5432 in Mainline U-boot. The major difference from OMAP5430 is that it supports DDR3 memory. Things to be done for supporting DDR3:
- ioconfig for ddr3
- Initialization sequence and ddr3 leveling
- Change in DPLL_CORE locking sequence
- Voltage changes
This series has been tested on OMAP4430 sdp OMAP5430sevm OMAP5432uevm
MAKEALL has been tested for all armv7 boards to ensure no build breakage.
Applied to u-boot-ti/master, thanks (and we'll deal with integration of am33xx into emif-common for the next release).
participants (4)
-
Lokesh Vutla -
R, Sricharan -
Tom Rini -
Tom Rini