From: Moritz Fischer moritz.fischer@ettus.com

Signed-off-by: Moritz Fischer moritz.fischer@ettus.com Signed-off-by: Olof Johansson olof@lixom.net Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynq-7000.dtsi | 7 +++++++ 1 file changed, 7 insertions(+)

diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index a352bc87114e..55eae614630a 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -272,6 +272,13 @@ reg = <0x100 0x100>; };

+ rstc: rstc@200 { + compatible = "xlnx,zynq-reset"; + reg = <0x200 0x48>; + #reset-cells = <1>; + syscon = <&slcr>; + }; + pinctrl0: pinctrl@700 { compatible = "xlnx,pinctrl-zynq"; reg = <0x700 0x200>;

- Have compatible string as the first property - Sync with Linux kernel dtsi - Add missing interrupt properties

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynq-7000.dtsi | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/arch/arm/dts/zynq-7000.dtsi b/arch/arm/dts/zynq-7000.dtsi index aff65f2decb3..a327557c19cc 100644 --- a/arch/arm/dts/zynq-7000.dtsi +++ b/arch/arm/dts/zynq-7000.dtsi @@ -306,7 +306,11 @@

devcfg: devcfg@f8007000 { compatible = "xlnx,zynq-devcfg-1.0"; + interrupt-parent = <&intc>; + interrupts = <0 8 4>; reg = <0xf8007000 0x100>; + clocks = <&clkc 12>, <&clkc 15>, <&clkc 16>, <&clkc 17>, <&clkc 18>; + clock-names = "ref_clk", "fclk0", "fclk1", "fclk2", "fclk3"; syscon = <&slcr>; };

From: Punnaiah Choudary Kalluri punnaiah.choudary.kalluri@xilinx.com

Added phy reset gpio information for gem0.

Signed-off-by: Punnaiah Choudary Kalluri punnaia@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynq-zc702.dts | 2 ++ 1 file changed, 2 insertions(+)

diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index eba7037daba1..ee050aa12faf 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -91,6 +91,8 @@ phy-handle = <&ethernet_phy>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gem0_default>; + phy-reset-gpio = <&gpio0 11 0>; + phy-reset-active-low;

ethernet_phy: ethernet-phy@7 { reg = <7>;

From: Christian Kohn christian.kohn@xilinx.com

Add missing adv7511 and configure to match Base TRD.

Signed-off-by: Christian Kohn christian.kohn@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynq-zc706.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+)

diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index bf996ad4d8af..cefee253fb06 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -84,6 +84,21 @@ }; };

+ i2c@1 { + #address-cells = <1>; + #size-cells = <0>; + reg = <1>; + adv7511: hdmi-tx@39 { + compatible = "adi,adv7511"; + reg = <0x39>; + adi,input-depth = <8>; + adi,input-colorspace = "yuv422"; + adi,input-clock = "1x"; + adi,input-style = <3>; + adi,input-justification = "evenly"; + }; + }; + i2c@2 { #address-cells = <1>; #size-cells = <0>;

Keep nodes alphabelitally sorted.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynq-zc702.dts | 10 +++++----- arch/arm/dts/zynq-zc706.dts | 10 +++++----- arch/arm/dts/zynq-zc770-xm010.dts | 42 +++++++++++++++++++-------------------- arch/arm/dts/zynq-zed.dts | 6 +++--- arch/arm/dts/zynq-zybo.dts | 6 +++--- 5 files changed, 37 insertions(+), 37 deletions(-)

diff --git a/arch/arm/dts/zynq-zc702.dts b/arch/arm/dts/zynq-zc702.dts index 8ad1db281de8..6585010f4bc8 100644 --- a/arch/arm/dts/zynq-zc702.dts +++ b/arch/arm/dts/zynq-zc702.dts @@ -387,6 +387,11 @@ }; };

+&qspi { + u-boot,dm-pre-reloc; + status = "okay"; +}; + &sdhci0 { u-boot,dm-pre-reloc; status = "okay"; @@ -401,11 +406,6 @@ pinctrl-0 = <&pinctrl_uart1_default>; };

-&qspi { - u-boot,dm-pre-reloc; - status = "okay"; -}; - &usb0 { status = "okay"; dr_mode = "host"; diff --git a/arch/arm/dts/zynq-zc706.dts b/arch/arm/dts/zynq-zc706.dts index cefee253fb06..d04880a2cdd3 100644 --- a/arch/arm/dts/zynq-zc706.dts +++ b/arch/arm/dts/zynq-zc706.dts @@ -306,6 +306,11 @@ }; };

+&qspi { + u-boot,dm-pre-reloc; + status = "okay"; +}; + &sdhci0 { u-boot,dm-pre-reloc; status = "okay"; @@ -320,11 +325,6 @@ pinctrl-0 = <&pinctrl_uart1_default>; };

-&qspi { - u-boot,dm-pre-reloc; - status = "okay"; -}; - &usb0 { status = "okay"; dr_mode = "host"; diff --git a/arch/arm/dts/zynq-zc770-xm010.dts b/arch/arm/dts/zynq-zc770-xm010.dts index 6dc7c89ddb2b..33524cb6def5 100644 --- a/arch/arm/dts/zynq-zc770-xm010.dts +++ b/arch/arm/dts/zynq-zc770-xm010.dts @@ -36,27 +36,6 @@ }; };

-&spi1 { - status = "okay"; - num-cs = <4>; - is-decoded-cs = <0>; - flash@0 { - compatible = "sst25wf080"; - reg = <1>; - spi-max-frequency = <1000000>; - #address-cells = <1>; - #size-cells = <1>; - partition@test { - label = "spi-flash"; - reg = <0x0 0x100000>; - }; - }; -}; - -&qspi { - status = "okay"; -}; - &can0 { status = "okay"; }; @@ -82,10 +61,31 @@

};

+&qspi { + status = "okay"; +}; + &sdhci0 { status = "okay"; };

+&spi1 { + status = "okay"; + num-cs = <4>; + is-decoded-cs = <0>; + flash@0 { + compatible = "sst25wf080"; + reg = <1>; + spi-max-frequency = <1000000>; + #address-cells = <1>; + #size-cells = <1>; + partition@test { + label = "spi-flash"; + reg = <0x0 0x100000>; + }; + }; +}; + &uart1 { u-boot,dm-pre-reloc; status = "okay"; diff --git a/arch/arm/dts/zynq-zed.dts b/arch/arm/dts/zynq-zed.dts index b262d83ee672..4363a4fcaccb 100644 --- a/arch/arm/dts/zynq-zed.dts +++ b/arch/arm/dts/zynq-zed.dts @@ -50,17 +50,17 @@ }; };

-&sdhci0 { +&qspi { u-boot,dm-pre-reloc; status = "okay"; };

-&uart1 { +&sdhci0 { u-boot,dm-pre-reloc; status = "okay"; };

-&qspi { +&uart1 { u-boot,dm-pre-reloc; status = "okay"; }; diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts index acc6e42b46fc..f32923f5d25d 100644 --- a/arch/arm/dts/zynq-zybo.dts +++ b/arch/arm/dts/zynq-zybo.dts @@ -51,17 +51,17 @@ }; };

-&sdhci0 { +&qspi { u-boot,dm-pre-reloc; status = "okay"; };

-&uart1 { +&sdhci0 { u-boot,dm-pre-reloc; status = "okay"; };

-&qspi { +&uart1 { u-boot,dm-pre-reloc; status = "okay"; };

Sync with others zynq DTS files.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynq-zc770-xm011.dts | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/zynq-zc770-xm011.dts b/arch/arm/dts/zynq-zc770-xm011.dts index 858d0e2bc25e..463b14b5ea15 100644 --- a/arch/arm/dts/zynq-zc770-xm011.dts +++ b/arch/arm/dts/zynq-zc770-xm011.dts @@ -7,6 +7,7 @@ */ /dts-v1/; #include "zynq-7000.dtsi" + / { compatible = "xlnx,zynq-zc770-xm011", "xlnx,zynq-7000"; model = "Xilinx Zynq";

Add missing DT nodes and enable USB.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynq-microzed.dts | 38 +++++++++++++++++++++++++++++++++++++- configs/zynq_microzed_defconfig | 4 ++++ include/configs/zynq_microzed.h | 2 ++ 3 files changed, 43 insertions(+), 1 deletion(-)

diff --git a/arch/arm/dts/zynq-microzed.dts b/arch/arm/dts/zynq-microzed.dts index 793ab44eae24..cb238cd5e7bb 100644 --- a/arch/arm/dts/zynq-microzed.dts +++ b/arch/arm/dts/zynq-microzed.dts @@ -1,7 +1,7 @@ /* * Xilinx MicroZED board DTS * - * Copyright (C) 2013 Xilinx, Inc. + * Copyright (C) 2013 - 2016 Xilinx, Inc. * * SPDX-License-Identifier: GPL-2.0+ */ @@ -15,12 +15,27 @@ aliases { serial0 = &uart1; spi0 = &qspi; + mmc0 = &sdhci0; };

memory { device_type = "memory"; reg = <0 0x40000000>; }; + + chosen { + bootargs = "earlyprintk"; + stdout-path = "serial0:115200n8"; + }; + + usb_phy0: phy0 { + compatible = "usb-nop-xceiv"; + #phy-cells = <0>; + }; +}; + +&clkc { + ps-clk-frequency = <33333333>; };

&qspi { @@ -32,3 +47,24 @@ u-boot,dm-pre-reloc; status = "okay"; }; + +&gem0 { + status = "okay"; + phy-mode = "rgmii-id"; + phy-handle = <&ethernet_phy>; + + ethernet_phy: ethernet-phy@0 { + reg = <0>; + }; +}; + +&sdhci0 { + u-boot,dm-pre-reloc; + status = "okay"; +}; + +&usb0 { + status = "okay"; + dr_mode = "host"; + usb-phy = <&usb_phy0>; +}; diff --git a/configs/zynq_microzed_defconfig b/configs/zynq_microzed_defconfig index 1d70e43df0c8..bd261c16ebb0 100644 --- a/configs/zynq_microzed_defconfig +++ b/configs/zynq_microzed_defconfig @@ -21,3 +21,7 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_ZYNQ_GEM=y CONFIG_ZYNQ_QSPI=y +CONFIG_USB=y +CONFIG_USB_ULPI_VIEWPORT=y +CONFIG_USB_ULPI=y +CONFIG_USB_GADGET=y diff --git a/include/configs/zynq_microzed.h b/include/configs/zynq_microzed.h index e66088da4f79..ec7bb1cef553 100644 --- a/include/configs/zynq_microzed.h +++ b/include/configs/zynq_microzed.h @@ -12,6 +12,8 @@

#define CONFIG_SYS_NO_FLASH

+#define CONFIG_ZYNQ_USB + #include <configs/zynq-common.h>

#endif /* __CONFIG_ZYNQ_MICROZED_H */

Compatible property should be the first.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

arch/arm/dts/zynq-zybo.dts | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/arm/dts/zynq-zybo.dts b/arch/arm/dts/zynq-zybo.dts index f32923f5d25d..f8dcf1d6995c 100644 --- a/arch/arm/dts/zynq-zybo.dts +++ b/arch/arm/dts/zynq-zybo.dts @@ -31,8 +31,8 @@ };

usb_phy0: phy0 { - #phy-cells = <0>; compatible = "usb-nop-xceiv"; + #phy-cells = <0>; reset-gpios = <&gpio0 46 1>; }; };

This is example how to change u-boot to support more memory banks read from DT.

Signed-off-by: Michal Simek michal.simek@xilinx.com ---

board/xilinx/zynq/board.c | 132 ++++++++++++++++++++++++++++++++++++++---- include/configs/zynq-common.h | 4 +- 2 files changed, 123 insertions(+), 13 deletions(-)

diff --git a/board/xilinx/zynq/board.c b/board/xilinx/zynq/board.c index 4c20450b6359..183f64275349 100644 --- a/board/xilinx/zynq/board.c +++ b/board/xilinx/zynq/board.c @@ -111,26 +111,134 @@ int zynq_board_read_rom_ethaddr(unsigned char *ethaddr) return 0; }

+#if !defined(CONFIG_SYS_SDRAM_BASE) && !defined(CONFIG_SYS_SDRAM_SIZE) +/* + * fdt_get_reg - Fill buffer by information from DT + */ +static phys_size_t fdt_get_reg(const void *fdt, int nodeoffset, void *buf, + const u32 *cell, int n) +{ + int i = 0, b, banks; + int parent_offset = fdt_parent_offset(fdt, nodeoffset); + int address_cells = fdt_address_cells(fdt, parent_offset); + int size_cells = fdt_size_cells(fdt, parent_offset); + char *p = buf; + u64 val; + u64 vals; + + debug("%s: addr_cells=%x, size_cell=%x, buf=%p, cell=%p\n", + __func__, address_cells, size_cells, buf, cell); + + /* Check memory bank setup */ + banks = n % (address_cells + size_cells); + if (banks) + panic("Incorrect memory setup cells=%d, ac=%d, sc=%d\n", + n, address_cells, size_cells); + + banks = n / (address_cells + size_cells); + + for (b = 0; b < banks; b++) { + debug("%s: Bank #%d:\n", __func__, b); + if (address_cells == 2) { + val = cell[i + 1]; + val <<= 32; + val |= cell[i]; + val = fdt64_to_cpu(val); + debug("%s: addr64=%llx, ptr=%p, cell=%p\n", + __func__, val, p, &cell[i]); + *(phys_addr_t *)p = val; + } else { + debug("%s: addr32=%x, ptr=%p\n", + __func__, fdt32_to_cpu(cell[i]), p); + *(phys_addr_t *)p = fdt32_to_cpu(cell[i]); + } + p += sizeof(phys_addr_t); + i += address_cells; + + debug("%s: pa=%p, i=%x, size=%zu\n", __func__, p, i, + sizeof(phys_addr_t)); + + if (size_cells == 2) { + vals = cell[i + 1]; + vals <<= 32; + vals |= cell[i]; + vals = fdt64_to_cpu(vals); + + debug("%s: size64=%llx, ptr=%p, cell=%p\n", + __func__, vals, p, &cell[i]); + *(phys_size_t *)p = vals; + } else { + debug("%s: size32=%x, ptr=%p\n", + __func__, fdt32_to_cpu(cell[i]), p); + *(phys_size_t *)p = fdt32_to_cpu(cell[i]); + } + p += sizeof(phys_size_t); + i += size_cells; + + debug("%s: ps=%p, i=%x, size=%zu\n", + __func__, p, i, sizeof(phys_size_t)); + } + + /* Return the first address size */ + return *(phys_size_t *)((char *)buf + sizeof(phys_addr_t)); +} + +#define FDT_REG_SIZE sizeof(u32) +/* Temp location for sharing data for storing */ +/* Up to 64-bit address + 64-bit size */ +static u8 tmp[CONFIG_NR_DRAM_BANKS * 16]; + +void dram_init_banksize(void) +{ + int bank; + + memcpy(&gd->bd->bi_dram[0], &tmp, sizeof(tmp)); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + debug("Bank #%d: start %llx\n", bank, + (unsigned long long)gd->bd->bi_dram[bank].start); + debug("Bank #%d: size %llx\n", bank, + (unsigned long long)gd->bd->bi_dram[bank].size); + } +} + int dram_init(void) { - int node; - fdt_addr_t addr; - fdt_size_t size; + int node, len; const void *blob = gd->fdt_blob; + const u32 *cell;

- node = fdt_node_offset_by_prop_value(blob, -1, "device_type", - "memory", 7); - if (node == -FDT_ERR_NOTFOUND) { - debug("ZYNQ DRAM: Can't get memory node\n"); - return -1; + memset(&tmp, 0, sizeof(tmp)); + + /* find or create "/memory" node. */ + node = fdt_subnode_offset(blob, 0, "memory"); + if (node < 0) { + printf("%s: Can't get memory node\n", __func__); + return node; } - addr = fdtdec_get_addr_size(blob, node, "reg", &size); - if (addr == FDT_ADDR_T_NONE || size == 0) { - debug("ZYNQ DRAM: Can't get base address or size\n"); + + /* Get pointer to cells and lenght of it */ + cell = fdt_getprop(blob, node, "reg", &len); + if (!cell) { + printf("%s: Can't get reg property\n", __func__); return -1; } - gd->ram_size = size; + + gd->ram_size = fdt_get_reg(blob, node, &tmp, cell, len / FDT_REG_SIZE); + + debug("%s: Initial DRAM size %llx\n", __func__, (u64)gd->ram_size); + + zynq_ddrc_init(); + + return 0; +} +#else +int dram_init(void) +{ + gd->ram_size = CONFIG_SYS_SDRAM_SIZE; + zynq_ddrc_init();

return 0; } +#endif diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index aac1e2badd04..2d941a7192c5 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -277,7 +277,9 @@ /* Physical Memory map */ #define CONFIG_SYS_TEXT_BASE 0x4000000

-#define CONFIG_NR_DRAM_BANKS 1 +#ifndef CONFIG_NR_DRAM_BANKS +# define CONFIG_NR_DRAM_BANKS 1 +#endif

#define CONFIG_SYS_MEMTEST_START 0 #define CONFIG_SYS_MEMTEST_END 0x1000