On Fri, 16 Feb 2024 at 02:22, Caleb Connolly caleb.connolly@linaro.org wrote:

When booting U-Boot on board with a locked down first-stage bootloader, we emulate the Linux boot header. By passing the U-Boot FDT through this first-stage bootloader and retrieving it afterwards we can pre-populate the memory nodes and other info like the KASLR address.

Add a function to export the FDT addr so that boards can use it over the built-in FDT.

Don't check is_addr_accessible() here because we might not yet have a valid mem_map if it's going to be populated from the FDT, let the board do their own validation instead.

Reviewed-by: Tom Rini trini@konsulko.com Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

---

arch/arm/lib/save_prev_bl_data.c | 5 +++++ include/init.h | 11 +++++++++++ 2 files changed, 16 insertions(+)

Reviewed-by: Sumit Garg sumit.garg@linaro.org

-Sumit

diff --git a/arch/arm/lib/save_prev_bl_data.c b/arch/arm/lib/save_prev_bl_data.c index f7b23faf0d66..b286bac9bf00 100644 --- a/arch/arm/lib/save_prev_bl_data.c +++ b/arch/arm/lib/save_prev_bl_data.c @@ -45,6 +45,11 @@ bool is_addr_accessible(phys_addr_t addr) return false; }

+phys_addr_t get_prev_bl_fdt_addr(void) +{

•   return reg0;
  

+}

int save_prev_bl_data(void) { struct fdt_header *fdt_blob; diff --git a/include/init.h b/include/init.h index 9a1951d10a01..630d86729c4e 100644 --- a/include/init.h +++ b/include/init.h @@ -168,6 +168,17 @@ defined(CONFIG_SAVE_PREV_BL_FDT_ADDR)

• Return: 0 if ok; -ENODATA on error

*/ int save_prev_bl_data(void);

+/**

• • get_prev_bl_fdt_addr - When u-boot is chainloaded, get the address
• • of the FDT passed by the previous bootloader.
• • Return: the address of the FDT passed by the previous bootloader
• • or 0 if not found.
• */

+phys_addr_t get_prev_bl_fdt_addr(void); +#else +#define get_prev_bl_fdt_addr() 0LLU #endif

/**

-- 2.43.1

On 2024-02-15 21:52, Caleb Connolly wrote:

Add support for a vbus-supply regulator specified in devicetree. This provides generic support to avoid hardcoded GPIO configuration in board init code.

Reviewed-by: Neil Armstrong neil.armstrong@linaro.org Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

---

This patch has no dependencies

Cc: Marek Vasut marex@denx.de

drivers/usb/dwc3/dwc3-generic.c | 12 ++++++++++++ 1 file changed, 12 insertions(+)

diff --git a/drivers/usb/dwc3/dwc3-generic.c b/drivers/usb/dwc3/dwc3-generic.c index 6fb2de8a5ace..48da621ba966 100644 --- a/drivers/usb/dwc3/dwc3-generic.c +++ b/drivers/usb/dwc3/dwc3-generic.c @@ -21,6 +21,7 @@ #include <linux/usb/ch9.h> #include <linux/usb/gadget.h> #include <malloc.h> +#include <power/regulator.h> #include <usb.h> #include "core.h" #include "gadget.h" @@ -47,6 +48,7 @@ struct dwc3_generic_priv { struct dwc3_generic_host_priv { struct xhci_ctrl xhci_ctrl; struct dwc3_generic_priv gen_priv;

• struct udevice *vbus_dev;

vbus_supply may be a better name, it is a name used by other drivers.

};

static int dwc3_generic_probe(struct udevice *dev, @@ -240,6 +242,13 @@ static int dwc3_generic_host_probe(struct udevice *dev) if (rc) return rc;

• rc = device_get_supply_regulator(dev, "vbus-supply", &priv->vbus_dev);
• if (rc)

• debug("%s: No vbus regulator found: %d\n", dev->name, rc);
  

• if (priv->vbus_dev)

• regulator_set_enable(priv->vbus_dev, true);
  

This should use the following form:

rc = regulator_set_enable_if_allowed(priv->vbus_supply, true); if (rc && rc != -ENOSYS) return rc;

That should only report an error if there is an error enabling the regulator, or -ENOSYS if regulator support has been disabled.

Because fixed and gpio regulators now are referenced counted you will need to clean up and disable the supply if the call to xhci_register() fails, something like following should probably work:

rc = xhci_register(dev, hccr, hcor); if (rc) regulator_set_enable_if_allowed(priv->vbus_supply, false);

return rc;

• hccr = (struct xhci_hccr *)priv->gen_priv.base; hcor = (struct xhci_hcor *)(priv->gen_priv.base + HC_LENGTH(xhci_readl(&(hccr)->cr_capbase)));

@@ -256,6 +265,9 @@ static int dwc3_generic_host_remove(struct udevice *dev) if (rc) return rc;

• if (priv->vbus_dev)

• regulator_set_enable(priv->vbus_dev, false);
  

This can safely use the following without any if check:

regulator_set_enable_if_allowed(priv->vbus_supply, false);

Regards, Jonas

• return dwc3_generic_remove(dev, &priv->gen_priv);

}

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly caleb.connolly@linaro.org wrote:

Use the clk_* helper functions and the correct property name for clocks.

Reviewed-by: Neil Armstrong neil.armstrong@linaro.org Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

---

drivers/mmc/msm_sdhci.c | 69 +++++++++++++++++++++++++++++++++---------------- 1 file changed, 47 insertions(+), 22 deletions(-)

Reviewed-by: Sumit Garg sumit.garg@linaro.org

-Sumit

diff --git a/drivers/mmc/msm_sdhci.c b/drivers/mmc/msm_sdhci.c index fe1e754bfde0..b63538fce20c 100644 --- a/drivers/mmc/msm_sdhci.c +++ b/drivers/mmc/msm_sdhci.c @@ -44,6 +44,7 @@ struct msm_sdhc_plat { struct msm_sdhc { struct sdhci_host host; void *base;

•   struct clk_bulk clks;
  

};

struct msm_sdhc_variant_info { @@ -54,35 +55,57 @@ DECLARE_GLOBAL_DATA_PTR;

static int msm_sdc_clk_init(struct udevice *dev) {

•   int node = dev_of_offset(dev);
  

•   uint clk_rate = fdtdec_get_uint(gd->fdt_blob, node, "clock-frequency",
  

•                                   400000);
  

•   uint clkd[2]; /* clk_id and clk_no */
  

•   int clk_offset;
  

•   struct udevice *clk_dev;
  

•   struct clk clk;
  

•   int ret;
  

•   struct msm_sdhc *prv = dev_get_priv(dev);
  

•   ofnode node = dev_ofnode(dev);
  

•   uint clk_rate;
  

•   int ret, i = 0, n_clks;
  

•   const char *clk_name;
  
  

•   ret = fdtdec_get_int_array(gd->fdt_blob, node, "clock", clkd, 2);
  

•   ret = ofnode_read_u32(node, "clock-frequency", &clk_rate);
    if (ret)
  

•           return ret;
  

•           clk_rate = 400000;
  
  

•   clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
  

•   if (clk_offset < 0)
  

•           return clk_offset;
  

•   ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
  

•   if (ret)
  

•   ret = clk_get_bulk(dev, &prv->clks);
  

•   if (ret) {
  

•           log_warning("Couldn't get mmc clocks: %d\n", ret);
            return ret;
  

•   }
  
  

•   clk.id = clkd[1];
  

•   ret = clk_request(clk_dev, &clk);
  

•   if (ret < 0)
  

•   ret = clk_enable_bulk(&prv->clks);
  

•   if (ret) {
  

•           log_warning("Couldn't enable mmc clocks: %d\n", ret);
            return ret;
  

•   }
  
  

•   ret = clk_set_rate(&clk, clk_rate);
  

•   if (ret < 0)
  

•           return ret;
  

•   /* If clock-names is unspecified, then the first clock is the core clock */
  

•   if (!ofnode_get_property(node, "clock-names", &n_clks)) {
  

•           if (!clk_set_rate(&prv->clks.clks[0], clk_rate)) {
  

•                   log_warning("Couldn't set core clock rate: %d\n", ret);
  

•                   return -EINVAL;
  

•           }
  

•   }
  

•   /* Find the index of the "core" clock */
  

•   while (i < n_clks) {
  

•           ofnode_read_string_index(node, "clock-names", i, &clk_name);
  

•           if (!strcmp(clk_name, "core"))
  

•                   break;
  

•           i++;
  

•   }
  

•   if (i >= prv->clks.count) {
  

•           log_warning("Couldn't find core clock (index %d but only have %d clocks)\n", i,
  

•                  prv->clks.count);
  

•           return -EINVAL;
  

•   }
  

•   /* The clock is already enabled by the clk_bulk above */
  

•   ret = clk_set_rate(&prv->clks.clks[i], clk_rate);
  

•   /* If we get a rate of 0 then something has probably gone wrong. */
  

•   if (ret == 0) {
  

•           log_warning("Couldn't set core clock rate to %u! Driver returned rate of 0\n", clk_rate);
  

•           return -EINVAL;
  

•   }
  
    return 0;
  

} @@ -187,6 +210,8 @@ static int msm_sdc_remove(struct udevice *dev) if (!var_info->mci_removed) writel(0, priv->base + SDCC_MCI_HC_MODE);

•   clk_release_bulk(&priv->clks);
  

•   return 0;
  

}

-- 2.43.1

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly caleb.connolly@linaro.org wrote:

We should be returning the rate that we set the clock to, drivers like MMC rely on this. So fix it.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

drivers/clk/qcom/clock-qcs404.c | 25 +++++++++++++------------ 1 file changed, 13 insertions(+), 12 deletions(-)

Reviewed-by: Sumit Garg sumit.garg@linaro.org

-Sumit

diff --git a/drivers/clk/qcom/clock-qcs404.c b/drivers/clk/qcom/clock-qcs404.c index f5b352803927..958312b88842 100644 --- a/drivers/clk/qcom/clock-qcs404.c +++ b/drivers/clk/qcom/clock-qcs404.c @@ -193,24 +193,18 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate)

    switch (clk->id) {
    case GCC_BLSP1_UART2_APPS_CLK:

•           /* UART: 115200 */
  

•           /* UART: 1843200Hz for a fixed 115200 baudrate (19200000 * (12/125)) */
            clk_rcg_set_rate_mnd(priv->base, &uart2_regs, 0, 12, 125,
                                 CFG_CLK_SRC_CXO, 16);
            clk_enable_cbc(priv->base + BLSP1_UART2_APPS_CBCR);
  

•           break;
  

•   case GCC_BLSP1_AHB_CLK:
  

•           clk_enable_vote_clk(priv->base, &gcc_blsp1_ahb_clk);
  

•           break;
  

•           return 1843200;
    case GCC_SDCC1_APPS_CLK:
            /* SDCC1: 200MHz */
            clk_rcg_set_rate_mnd(priv->base, &sdc_regs, 7, 0, 0,
                                 CFG_CLK_SRC_GPLL0, 8);
            clk_enable_gpll0(priv->base, &gpll0_vote_clk);
            clk_enable_cbc(priv->base + SDCC_APPS_CBCR(1));
  

•           break;
  

•   case GCC_SDCC1_AHB_CLK:
  

•           clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
  

•           break;
  

•           return rate;
    case GCC_ETH_RGMII_CLK:
            if (rate == 250000000)
                    clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 0, 0,
  

@@ -224,11 +218,15 @@ static ulong qcs404_clk_set_rate(struct clk *clk, ulong rate) else if (rate == 5000000) clk_rcg_set_rate_mnd(priv->base, &emac_regs, 3, 1, 50, CFG_CLK_SRC_GPLL1, 8);

•           break;
  

•   default:
  

•           return 0;
  

•           return rate;
    }
  
  

•   /* There is a bug only seeming to affect this board where the MMC driver somehow calls
  

•    * clk_set_rate() on a clock with id 0 which is associated with the qcom_clk device.
  

•    * The only clock with ID 0 is the xo_board clock which should not be associated with
  

•    * this device...
  

•    */
  

•   log_debug("Unknown clock id %ld\n", clk->id);
    return 0;
  

}

@@ -305,6 +303,9 @@ static int qcs404_clk_enable(struct clk *clk) clk_rcg_set_rate(priv->base, &blsp1_qup4_i2c_apps_regs, 0, CFG_CLK_SRC_CXO); break;

•   case GCC_SDCC1_AHB_CLK:
  

•           clk_enable_cbc(priv->base + SDCC_AHB_CBCR(1));
  

•           break;
    default:
            return 0;
    }
  
  

-- 2.43.1

On 15/02/2024 21:52, Caleb Connolly wrote:

Introduce support for early debugging. This relies on the previous stage bootloader to initialise the UART clocks, when running with U-Boot as the primary bootloader this feature doesn't work. It will require a way to configure the clocks before the driver model is available.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

drivers/serial/Kconfig | 8 ++++++++ drivers/serial/serial_msm.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 26460c4e0cab..fbd351a47859 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -319,6 +319,14 @@ config DEBUG_UART_S5P will need to provide parameters to make this work. The driver will be available until the real driver-model serial is running.

+config DEBUG_UART_MSM

• bool "Qualcomm QUP UART debug"
• depends on ARCH_SNAPDRAGON
• help

•  Select this to enable a debug UART using the serial_msm driver. You
  

•  will need to provide parameters to make this work. The driver will
  

•  be available until the real driver-model serial is running.
  

• config DEBUG_UART_MSM_GENI bool "Qualcomm snapdragon" depends on ARCH_SNAPDRAGON

diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index f4d96313b931..44b93bd7ff21 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -252,3 +252,40 @@ U_BOOT_DRIVER(serial_msm) = { .probe = msm_serial_probe, .ops = &msm_serial_ops, };

+#ifdef CONFIG_DEBUG_UART_MSM

+static struct msm_serial_data init_serial_data = {

• .base = CONFIG_VAL(DEBUG_UART_BASE),
• .clk_rate = 7372800,

+};

+#include <debug_uart.h>

+/* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */ +//int apq8016_clk_init_uart(phys_addr_t gcc_base);

+static inline void _debug_uart_init(void) +{

• /* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */
• //apq8016_clk_init_uart(0x1800000);
• uart_dm_init(&init_serial_data);

+}

+static inline void _debug_uart_putc(int ch) +{

• struct msm_serial_data *priv = &init_serial_data;
• while (!(readl(priv->base + UARTDM_SR) & UARTDM_SR_TX_EMPTY) &&

•       !(readl(priv->base + UARTDM_ISR) & UARTDM_ISR_TX_READY))
  

• ;
  

• writel(UARTDM_CR_CMD_RESET_TX_READY, priv->base + UARTDM_CR);
• writel(1, priv->base + UARTDM_NCF_TX);
• writel(ch, priv->base + UARTDM_TF);

+}

+DEBUG_UART_FUNCS

+#endif

Reviewed-by: Neil Armstrong neil.armstrong@linaro.org

On 20/02/2024 06:08, Sumit Garg wrote:

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly caleb.connolly@linaro.org wrote:

...

Introduce support for early debugging. This relies on the previous stage bootloader to initialise the UART clocks, when running with U-Boot as the primary bootloader this feature doesn't work. It will require a way to configure the clocks before the driver model is available.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

drivers/serial/Kconfig | 8 ++++++++ drivers/serial/serial_msm.c | 37 +++++++++++++++++++++++++++++++++++++ 2 files changed, 45 insertions(+)

diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 26460c4e0cab..fbd351a47859 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -319,6 +319,14 @@ config DEBUG_UART_S5P will need to provide parameters to make this work. The driver will be available until the real driver-model serial is running.

+config DEBUG_UART_MSM

•   bool "Qualcomm QUP UART debug"
  

•   depends on ARCH_SNAPDRAGON
  

Since this debug UART only works for chainloaded configuration, can we somehow add explicit dependency here? Something like !REMAKE_ELF?

With a small patch (which didn't make it into v4 apparently) the apq8016_clk_init_uart() function from clock-apq8016 can be adjusted to just take a base address rather than "struct msm_clk_priv". It can then be called from debug_uart_init() and allows for debug UART to be used when U-Boot is running as the first stage.

This is definitely not ideal (although fwiw if the GPLLs were configured right then this same function could maybe work on QCS404 as well - the RCGs are at the same physical addresses), but I don't think gating it behind REMAKE_ELF or something is a great solution here.

-Sumit

...

•   help
  

•     Select this to enable a debug UART using the serial_msm driver. You
  

•     will need to provide parameters to make this work. The driver will
  

•     be available until the real driver-model serial is running.
  

config DEBUG_UART_MSM_GENI bool "Qualcomm snapdragon" depends on ARCH_SNAPDRAGON diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index f4d96313b931..44b93bd7ff21 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -252,3 +252,40 @@ U_BOOT_DRIVER(serial_msm) = { .probe = msm_serial_probe, .ops = &msm_serial_ops, };

+#ifdef CONFIG_DEBUG_UART_MSM

+static struct msm_serial_data init_serial_data = {

•   .base = CONFIG_VAL(DEBUG_UART_BASE),
  

•   .clk_rate = 7372800,
  

+};

+#include <debug_uart.h>

+/* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */ +//int apq8016_clk_init_uart(phys_addr_t gcc_base);

+static inline void _debug_uart_init(void) +{

•   /* Uncomment to turn on UART clocks when debugging U-Boot as aboot on MSM8916 */
  

•   //apq8016_clk_init_uart(0x1800000);
  

•   uart_dm_init(&init_serial_data);
  

+}

+static inline void _debug_uart_putc(int ch) +{

•   struct msm_serial_data *priv = &init_serial_data;
  

•   while (!(readl(priv->base + UARTDM_SR) & UARTDM_SR_TX_EMPTY) &&
  

•          !(readl(priv->base + UARTDM_ISR) & UARTDM_ISR_TX_READY))
  

•           ;
  

•   writel(UARTDM_CR_CMD_RESET_TX_READY, priv->base + UARTDM_CR);
  

•   writel(1, priv->base + UARTDM_NCF_TX);
  

•   writel(ch, priv->base + UARTDM_TF);
  

+}

+DEBUG_UART_FUNCS

+#endif

-- 2.43.1

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly caleb.connolly@linaro.org wrote:

Use the modern helpers to fetch the clock and use the correct property ("clocks" instead of "clock"). Drop the call to pinctrl_select_state() as no boards have a "uart" pinctrl state and this prints confusing errors.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

arch/arm/dts/dragonboard410c.dts | 3 ++- arch/arm/dts/dragonboard820c.dts | 3 ++- drivers/serial/serial_msm.c | 25 +++++-------------------- 3 files changed, 9 insertions(+), 22 deletions(-)

Reviewed-by: Sumit Garg sumit.garg@linaro.org

-Sumit

diff --git a/arch/arm/dts/dragonboard410c.dts b/arch/arm/dts/dragonboard410c.dts index 02c824d0226c..c395e6cc0427 100644 --- a/arch/arm/dts/dragonboard410c.dts +++ b/arch/arm/dts/dragonboard410c.dts @@ -84,7 +84,8 @@ serial@78b0000 { compatible = "qcom,msm-uartdm-v1.4"; reg = <0x78b0000 0x200>;

•                   clock = <&clkc 4>;
  

•                   clocks = <&clkc 4>;
  

•                   clock-names = "core";
                    pinctrl-names = "uart";
                    pinctrl-0 = <&blsp1_uart>;
            };
  

diff --git a/arch/arm/dts/dragonboard820c.dts b/arch/arm/dts/dragonboard820c.dts index 146a0af8aafe..86b7f83d36d6 100644 --- a/arch/arm/dts/dragonboard820c.dts +++ b/arch/arm/dts/dragonboard820c.dts @@ -78,7 +78,8 @@ blsp2_uart2: serial@75b0000 { compatible = "qcom,msm-uartdm-v1.4", "qcom,msm-uartdm"; reg = <0x75b0000 0x1000>;

•                   clock = <&gcc 4>;
  

•                   clocks = <&gcc 4>;
  

•                   clock-names = "core";
                    pinctrl-names = "uart";
                    pinctrl-0 = <&blsp8_uart>;
            };
  

diff --git a/drivers/serial/serial_msm.c b/drivers/serial/serial_msm.c index 44b93bd7ff21..ac4280c6c4c2 100644 --- a/drivers/serial/serial_msm.c +++ b/drivers/serial/serial_msm.c @@ -160,29 +160,14 @@ static int msm_uart_clk_init(struct udevice *dev) { uint clk_rate = fdtdec_get_uint(gd->fdt_blob, dev_of_offset(dev), "clock-frequency", 115200);

•   uint clkd[2]; /* clk_id and clk_no */
  

•   int clk_offset;
  

•   struct udevice *clk_dev;
    struct clk clk;
    int ret;
  
  

•   ret = fdtdec_get_int_array(gd->fdt_blob, dev_of_offset(dev), "clock",
  

•                              clkd, 2);
  

•   if (ret)
  

•           return ret;
  

•   clk_offset = fdt_node_offset_by_phandle(gd->fdt_blob, clkd[0]);
  

•   if (clk_offset < 0)
  

•           return clk_offset;
  

•   ret = uclass_get_device_by_of_offset(UCLASS_CLK, clk_offset, &clk_dev);
  

•   if (ret)
  

•           return ret;
  

•   clk.id = clkd[1];
  

•   ret = clk_request(clk_dev, &clk);
  

•   if (ret < 0)
  

•   ret = clk_get_by_name(dev, "core", &clk);
  

•   if (ret < 0) {
  

•           pr_warn("%s: Failed to get clock: %d\n", __func__, ret);
            return ret;
  

•   }
  
    ret = clk_set_rate(&clk, clk_rate);
    if (ret < 0)
  

@@ -218,7 +203,6 @@ static int msm_serial_probe(struct udevice *dev) if (ret) return ret;

•   pinctrl_select_state(dev, "uart");
    uart_dm_init(priv);
  
    return 0;
  

@@ -251,6 +235,7 @@ U_BOOT_DRIVER(serial_msm) = { .priv_auto = sizeof(struct msm_serial_data), .probe = msm_serial_probe, .ops = &msm_serial_ops,

•   .flags = DM_FLAG_PRE_RELOC,
  

};

#ifdef CONFIG_DEBUG_UART_MSM

-- 2.43.1

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly caleb.connolly@linaro.org wrote:

Qualcomm PMICs number their GPIOs starting from 1, implement a custom .xlate method to handle this.

Reviewed-by: Neil Armstrong neil.armstrong@linaro.org Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

---

drivers/gpio/qcom_pmic_gpio.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)

Reviewed-by: Sumit Garg sumit.garg@linaro.org

-Sumit

diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c index 6167c8411678..2a4fef8d28cb 100644 --- a/drivers/gpio/qcom_pmic_gpio.c +++ b/drivers/gpio/qcom_pmic_gpio.c @@ -209,12 +209,34 @@ static int qcom_gpio_set_value(struct udevice *dev, unsigned offset, REG_CTL_OUTPUT_MASK, !!value); }

+static int qcom_gpio_xlate(struct udevice *dev, struct gpio_desc *desc,

•                      struct ofnode_phandle_args *args)
  

+{

•   struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
  

•   if (args->args_count < 1)
  

•           return -EINVAL;
  

•   /* GPIOs in DT are 1-based */
  

•   desc->offset = args->args[0] - 1;
  

•   if (desc->offset >= uc_priv->gpio_count)
  

•           return -EINVAL;
  

•   if (args->args_count < 2)
  

•           return 0;
  

•   desc->flags = gpio_flags_xlate(args->args[1]);
  

•   return 0;
  

+}

static const struct dm_gpio_ops qcom_gpio_ops = { .direction_input = qcom_gpio_direction_input, .direction_output = qcom_gpio_direction_output, .get_value = qcom_gpio_get_value, .set_value = qcom_gpio_set_value, .get_function = qcom_gpio_get_function,

•   .xlate                  = qcom_gpio_xlate,
  

};

static int qcom_gpio_probe(struct udevice *dev)

-- 2.43.1

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly caleb.connolly@linaro.org wrote:

Some platforms hard reset when attempting to configure PMIC GPIOs. Add support for quirks specified in match data with a single quirk to skip this configuration. We rely on the GPIO already be configured correctly, which is always the case for volume up (the only current user of these GPIOs).

I can't find a similar quirk in the counterpart Linux driver (drivers/pinctrl/qcom/pinctrl-spmi-gpio.c). Is there anything we are missing in the U-Boot driver?

-Sumit

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

drivers/gpio/qcom_pmic_gpio.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c index 2a4fef8d28cb..198cd84bc31e 100644 --- a/drivers/gpio/qcom_pmic_gpio.c +++ b/drivers/gpio/qcom_pmic_gpio.c @@ -64,6 +64,15 @@ #define REG_EN_CTL 0x46 #define REG_EN_CTL_ENABLE (1 << 7)

+/**

• • pmic_gpio_match_data - platform specific configuration
• • @PMIC_MATCH_READONLY: treat all GPIOs as readonly, don't attempt to configure them
• */

+enum pmic_gpio_quirks {

•   QCOM_PMIC_QUIRK_READONLY = (1 << 0),
  

+};

struct qcom_gpio_bank { uint32_t pid; /* Peripheral ID on SPMI bus */ bool lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */ @@ -75,7 +84,12 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset, struct qcom_gpio_bank *priv = dev_get_priv(dev); uint32_t gpio_base = priv->pid + REG_OFFSET(offset); uint32_t reg_ctl_val;

•   int ret;
  

•   ulong quirks = dev_get_driver_data(dev);
  

•   int ret = 0;
  

•   /* Some PMICs don't like their GPIOs being configured */
  

•   if (quirks & QCOM_PMIC_QUIRK_READONLY)
  

•           return 0;
  
    /* Disable the GPIO */
    ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL,
  

@@ -304,7 +318,7 @@ static int qcom_gpio_of_to_plat(struct udevice *dev) static const struct udevice_id qcom_gpio_ids[] = { { .compatible = "qcom,pm8916-gpio" }, { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */

•   { .compatible = "qcom,pm8998-gpio" },
  

•   { .compatible = "qcom,pm8998-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
    { .compatible = "qcom,pms405-gpio" },
    { }
  

};

-- 2.43.1

On Wed, 21 Feb 2024 at 14:19, Neil Armstrong neil.armstrong@linaro.org wrote:

On 20/02/2024 06:56, Sumit Garg wrote:

...

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly caleb.connolly@linaro.org wrote:

...

Some platforms hard reset when attempting to configure PMIC GPIOs. Add support for quirks specified in match data with a single quirk to skip this configuration. We rely on the GPIO already be configured correctly, which is always the case for volume up (the only current user of these GPIOs).

I can't find a similar quirk in the counterpart Linux driver (drivers/pinctrl/qcom/pinctrl-spmi-gpio.c). Is there anything we are missing in the U-Boot driver?

It's not ideal, it's fine to have it at first but at some point a proper solution should be found.

Then at least let's add code comments to say that it is just a workaround for the time being until a proper solution is found.

-Sumit

Neil

...

-Sumit

...

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

drivers/gpio/qcom_pmic_gpio.c | 18 ++++++++++++++++-- 1 file changed, 16 insertions(+), 2 deletions(-)

diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c index 2a4fef8d28cb..198cd84bc31e 100644 --- a/drivers/gpio/qcom_pmic_gpio.c +++ b/drivers/gpio/qcom_pmic_gpio.c @@ -64,6 +64,15 @@ #define REG_EN_CTL 0x46 #define REG_EN_CTL_ENABLE (1 << 7)

+/**

• • pmic_gpio_match_data - platform specific configuration
• • @PMIC_MATCH_READONLY: treat all GPIOs as readonly, don't attempt to configure them
• */

+enum pmic_gpio_quirks {

•   QCOM_PMIC_QUIRK_READONLY = (1 << 0),
  

+};

• struct qcom_gpio_bank { uint32_t pid; /* Peripheral ID on SPMI bus */ bool lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */

@@ -75,7 +84,12 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset, struct qcom_gpio_bank *priv = dev_get_priv(dev); uint32_t gpio_base = priv->pid + REG_OFFSET(offset); uint32_t reg_ctl_val;

•   int ret;
  

•   ulong quirks = dev_get_driver_data(dev);
  

•   int ret = 0;
  

•   /* Some PMICs don't like their GPIOs being configured */
  

•   if (quirks & QCOM_PMIC_QUIRK_READONLY)
  

•           return 0;
  
     /* Disable the GPIO */
     ret = pmic_clrsetbits(dev->parent, gpio_base + REG_EN_CTL,
  

@@ -304,7 +318,7 @@ static int qcom_gpio_of_to_plat(struct udevice *dev) static const struct udevice_id qcom_gpio_ids[] = { { .compatible = "qcom,pm8916-gpio" }, { .compatible = "qcom,pm8994-gpio" }, /* 22 GPIO's */

•   { .compatible = "qcom,pm8998-gpio" },
  

•   { .compatible = "qcom,pm8998-gpio", .data = QCOM_PMIC_QUIRK_READONLY },
     { .compatible = "qcom,pms405-gpio" },
     { }
  

  };

-- 2.43.1

On 15/02/2024 21:52, Caleb Connolly wrote:

Introduce a basic pinctrl driver for the SPMI PMIC GPIOs. This is necessary to make proper use of upstream DT bindings specifically on the dragonboard410c where they're used to switch between USB host and device modes.

Only support for driving the pins as output low or high is enabled for now.

To minimise duplicated code and allow for sharing common DT data, the pinctrl driver is initialised as a child of the existing GPIO driver.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

drivers/gpio/qcom_pmic_gpio.c | 257 +++++++++++++++++++++++++++++------------- 1 file changed, 176 insertions(+), 81 deletions(-)

diff --git a/drivers/gpio/qcom_pmic_gpio.c b/drivers/gpio/qcom_pmic_gpio.c index 198cd84bc31e..9eca1556c356 100644 --- a/drivers/gpio/qcom_pmic_gpio.c +++ b/drivers/gpio/qcom_pmic_gpio.c @@ -7,10 +7,14 @@

#include <common.h> #include <dm.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <dm/pinctrl.h> #include <log.h> #include <power/pmic.h> #include <spmi/spmi.h> #include <asm/io.h> +#include <stdlib.h> #include <asm/gpio.h> #include <linux/bitops.h>

@@ -73,17 +77,54 @@ enum pmic_gpio_quirks { QCOM_PMIC_QUIRK_READONLY = (1 << 0), };

-struct qcom_gpio_bank { +struct qcom_pmic_gpio_data { uint32_t pid; /* Peripheral ID on SPMI bus */ bool lv_mv_type; /* If subtype is GPIO_LV(0x10) or GPIO_MV(0x11) */

• u32 pin_count;
• struct udevice *pmic; /* Reference to pmic device for read/write */ };

-static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset, +/* dev can be the GPIO or pinctrl device */ +static int _qcom_gpio_set_direction(struct udevice *dev, u32 offset, bool input, int value) +{

• struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
• u32 gpio_base = plat->pid + REG_OFFSET(offset);
• u32 reg_ctl_val;
• int ret = 0;
• /* Select the mode and output */
• if (plat->lv_mv_type) {

• if (input)
  

• 	reg_ctl_val = REG_CTL_LV_MV_MODE_INPUT;
  

• else
  

• 	reg_ctl_val = REG_CTL_LV_MV_MODE_INOUT;
  

• } else {

• if (input)
  

• 	reg_ctl_val = REG_CTL_MODE_INPUT;
  

• else
  

• 	reg_ctl_val = REG_CTL_MODE_INOUT | !!value;
  

• }
• ret = pmic_reg_write(plat->pmic, gpio_base + REG_CTL, reg_ctl_val);
• if (ret < 0)

• return ret;
  

• if (plat->lv_mv_type && !input) {

• ret = pmic_reg_write(plat->pmic,
  

• 		     gpio_base + REG_LV_MV_OUTPUT_CTL,
  

• 		     !!value << REG_LV_MV_OUTPUT_CTL_SHIFT);
  

• if (ret < 0)
  

• 	return ret;
  

• }
• return 0;

+}

+static int qcom_gpio_set_direction(struct udevice *dev, unsigned int offset, bool input, int value) {

• struct qcom_gpio_bank *priv = dev_get_priv(dev);
• uint32_t gpio_base = priv->pid + REG_OFFSET(offset);
• uint32_t reg_ctl_val;

• struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
• uint32_t gpio_base = plat->pid + REG_OFFSET(offset); ulong quirks = dev_get_driver_data(dev); int ret = 0;

@@ -97,33 +138,10 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset, if (ret < 0) return ret;

• /* Select the mode and output */
• if (priv->lv_mv_type) {

• if (input)
  

• 	reg_ctl_val = REG_CTL_LV_MV_MODE_INPUT;
  

• else
  

• 	reg_ctl_val = REG_CTL_LV_MV_MODE_INOUT;
  

• } else {

• if (input)
  

• 	reg_ctl_val = REG_CTL_MODE_INPUT;
  

• else
  

• 	reg_ctl_val = REG_CTL_MODE_INOUT | !!value;
  

• }
• ret = pmic_reg_write(dev->parent, gpio_base + REG_CTL, reg_ctl_val);
• if (ret < 0)

• return ret;
  

• if (priv->lv_mv_type && !input) {

• ret = pmic_reg_write(dev->parent,
  

• 		     gpio_base + REG_LV_MV_OUTPUT_CTL,
  

• 		     !!value << REG_LV_MV_OUTPUT_CTL_SHIFT);
  

• if (ret < 0)
  

• 	return ret;
  

• }

• _qcom_gpio_set_direction(dev, offset, input, value);

  /* Set the right pull (no pull) */

• ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_PULL_CTL,

• ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_PULL_CTL, REG_DIG_PULL_NO_PU); if (ret < 0) return ret;

@@ -131,13 +149,13 @@ static int qcom_gpio_set_direction(struct udevice *dev, unsigned offset, /* Configure output pin drivers if needed */ if (!input) { /* Select the VIN - VIN0, pin is input so it doesn't matter */

• ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_VIN_CTL,
  

• ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_VIN_CTL,
  	     REG_DIG_VIN_VIN0);
  

  if (ret < 0) return ret;

  /* Set the right dig out control */

• ret = pmic_reg_write(dev->parent, gpio_base + REG_DIG_OUT_CTL,
  

• ret = pmic_reg_write(plat->pmic, gpio_base + REG_DIG_OUT_CTL,
  	     REG_DIG_OUT_CTL_CMOS |
  	     REG_DIG_OUT_CTL_DRIVE_L);
  

  if (ret < 0)

@@ -162,15 +180,15 @@ static int qcom_gpio_direction_output(struct udevice *dev, unsigned offset,

static int qcom_gpio_get_function(struct udevice *dev, unsigned offset) {

• struct qcom_gpio_bank *priv = dev_get_priv(dev);
• uint32_t gpio_base = priv->pid + REG_OFFSET(offset);

• struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
• uint32_t gpio_base = plat->pid + REG_OFFSET(offset); int reg;

• reg = pmic_reg_read(dev->parent, gpio_base + REG_CTL);

• reg = pmic_reg_read(plat->pmic, gpio_base + REG_CTL); if (reg < 0) return reg;

• if (priv->lv_mv_type) {

• if (plat->lv_mv_type) { switch (reg & REG_CTL_LV_MV_MODE_MASK) { case REG_CTL_LV_MV_MODE_INPUT: return GPIOF_INPUT;

@@ -195,11 +213,11 @@ static int qcom_gpio_get_function(struct udevice *dev, unsigned offset)

static int qcom_gpio_get_value(struct udevice *dev, unsigned offset) {

• struct qcom_gpio_bank *priv = dev_get_priv(dev);
• uint32_t gpio_base = priv->pid + REG_OFFSET(offset);

• struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
• uint32_t gpio_base = plat->pid + REG_OFFSET(offset); int reg;

• reg = pmic_reg_read(dev->parent, gpio_base + REG_STATUS);

• reg = pmic_reg_read(plat->pmic, gpio_base + REG_STATUS); if (reg < 0) return reg;

@@ -209,11 +227,11 @@ static int qcom_gpio_get_value(struct udevice *dev, unsigned offset) static int qcom_gpio_set_value(struct udevice *dev, unsigned offset, int value) {

• struct qcom_gpio_bank *priv = dev_get_priv(dev);
• uint32_t gpio_base = priv->pid + REG_OFFSET(offset);

• struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);

• uint32_t gpio_base = plat->pid + REG_OFFSET(offset);

  /* Set the output value of the gpio */

• if (priv->lv_mv_type)

• if (plat->lv_mv_type) return pmic_clrsetbits(dev->parent, gpio_base + REG_LV_MV_OUTPUT_CTL, REG_LV_MV_OUTPUT_CTL_MASK,

@@ -253,63 +271,74 @@ static const struct dm_gpio_ops qcom_gpio_ops = { .xlate = qcom_gpio_xlate, };

+static int qcom_gpio_bind(struct udevice *dev) +{

• struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
• ulong quirks = dev_get_driver_data(dev);
• struct udevice *child;
• struct driver *drv;
• int ret;
• drv = lists_driver_lookup_name("qcom_pmic_pinctrl");
• if (!drv) {

• log_warning("Cannot find driver '%s'\n", "qcom_pmic_pinctrl");
  

• return -ENOENT;
  

• }
• /* Bind the GPIO driver as a child of the PMIC. */
• ret = device_bind_with_driver_data(dev, drv,

• 			   dev->name,
  

• 			   quirks, dev_ofnode(dev), &child);
  

• if (ret)

• return log_msg_ret("bind", ret);
  

• dev_set_plat(child, plat);
• return 0;

+}

• static int qcom_gpio_probe(struct udevice *dev) {

• struct qcom_gpio_bank *priv = dev_get_priv(dev);
• int reg;

• struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);

• struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);

• struct ofnode_phandle_args args;

• int val, ret; u64 pid;

• plat->pmic = dev->parent;

• pid = dev_read_addr(dev); if (pid == FDT_ADDR_T_NONE) return log_msg_ret("bad address", -EINVAL);

• priv->pid = pid;

• plat->pid = pid;

  /* Do a sanity check */

• reg = pmic_reg_read(dev->parent, priv->pid + REG_TYPE);
• if (reg != REG_TYPE_VAL)

• val = pmic_reg_read(plat->pmic, plat->pid + REG_TYPE);
• if (val != REG_TYPE_VAL) return log_msg_ret("bad type", -ENXIO);

• reg = pmic_reg_read(dev->parent, priv->pid + REG_SUBTYPE);
• if (reg != REG_SUBTYPE_GPIO_4CH && reg != REG_SUBTYPE_GPIOC_4CH &&

•    reg != REG_SUBTYPE_GPIO_LV && reg != REG_SUBTYPE_GPIO_MV)
  

• val = pmic_reg_read(plat->pmic, plat->pid + REG_SUBTYPE);
• if (val != REG_SUBTYPE_GPIO_4CH && val != REG_SUBTYPE_GPIOC_4CH &&

•    val != REG_SUBTYPE_GPIO_LV && val != REG_SUBTYPE_GPIO_MV)
  

  return log_msg_ret("bad subtype", -ENXIO);

• priv->lv_mv_type = reg == REG_SUBTYPE_GPIO_LV ||

• 	   reg == REG_SUBTYPE_GPIO_MV;
  

• return 0;

-}

-/*

• • Parse basic GPIO count specified via the gpio-ranges property
• • as specified in Linux devicetrees
• • Returns < 0 on error, otherwise gpio count
• */

-static int qcom_gpio_of_parse_ranges(struct udevice *dev) -{

• int ret;
• struct ofnode_phandle_args args;

• plat->lv_mv_type = val == REG_SUBTYPE_GPIO_LV ||

• 	   val == REG_SUBTYPE_GPIO_MV;
  
  

• /*

• * Parse basic GPIO count specified via the gpio-ranges property
  

• * as specified in upstream devicetrees
  

• */
  

  ret = ofnode_parse_phandle_with_args(dev_ofnode(dev), "gpio-ranges", NULL, 3, 0, &args); if (ret) return log_msg_ret("gpio-ranges", ret);

• return args.args[2];

-}

-static int qcom_gpio_of_to_plat(struct udevice *dev) -{

• struct gpio_dev_priv *uc_priv = dev_get_uclass_priv(dev);
• int ret;
• ret = qcom_gpio_of_parse_ranges(dev);
• if (ret > 0)

• uc_priv->gpio_count = ret;
  

• else

• return ret;
  

• plat->pin_count = args.args[2];

• uc_priv->gpio_count = plat->pin_count; uc_priv->bank_name = "pmic";

  return 0;

@@ -327,9 +356,75 @@ U_BOOT_DRIVER(qcom_pmic_gpio) = { .name = "qcom_pmic_gpio", .id = UCLASS_GPIO, .of_match = qcom_gpio_ids,

• .of_to_plat = qcom_gpio_of_to_plat,
• .probe = qcom_gpio_probe,

• .bind = qcom_gpio_bind,
• .probe = qcom_gpio_probe, .ops = &qcom_gpio_ops,

• .priv_auto = sizeof(struct qcom_gpio_bank),

• .plat_auto = sizeof(struct qcom_pmic_gpio_data),
• .flags = DM_FLAG_ALLOC_PDATA, };

+static const struct pinconf_param qcom_pmic_pinctrl_conf_params[] = {

• { "output-high", PIN_CONFIG_OUTPUT_ENABLE, 1 },
• { "output-low", PIN_CONFIG_OUTPUT, 0 },

+};

+static int qcom_pmic_pinctrl_get_pins_count(struct udevice *dev) +{

• struct qcom_pmic_gpio_data *plat = dev_get_plat(dev);
• return plat->pin_count;

+}

+static const char *qcom_pmic_pinctrl_get_pin_name(struct udevice *dev, unsigned int selector) +{

• static char name[8];
• /* DT indexes from 1 */
• snprintf(name, sizeof(name), "gpio%u", selector + 1);
• return name;

+}

+static int qcom_pmic_pinctrl_pinconf_set(struct udevice *dev, unsigned int selector,

• 			 unsigned int param, unsigned int arg)
  

+{

• /* We only support configuring the pin as an output, either low or high */
• return _qcom_gpio_set_direction(dev, selector, false,

• 			param == PIN_CONFIG_OUTPUT_ENABLE);
  

+}

+static const char *qcom_pmic_pinctrl_get_function_name(struct udevice *dev, unsigned int selector) +{

• if (!selector)

• return "normal";
  

• return NULL;

+}

+static int qcom_pmic_pinctrl_generic_get_functions_count(struct udevice *dev) +{

• return 1;

+}

+static int qcom_pmic_pinctrl_generic_pinmux_set_mux(struct udevice *dev, unsigned int selector,

• 				    unsigned int func_selector)
  

+{

• return 0;

+}

+struct pinctrl_ops qcom_pmic_pinctrl_ops = {

• .get_pins_count = qcom_pmic_pinctrl_get_pins_count,
• .get_pin_name = qcom_pmic_pinctrl_get_pin_name,
• .set_state = pinctrl_generic_set_state,
• .pinconf_num_params = ARRAY_SIZE(qcom_pmic_pinctrl_conf_params),
• .pinconf_params = qcom_pmic_pinctrl_conf_params,
• .pinconf_set = qcom_pmic_pinctrl_pinconf_set,
• .get_function_name = qcom_pmic_pinctrl_get_function_name,
• .get_functions_count = qcom_pmic_pinctrl_generic_get_functions_count,
• .pinmux_set = qcom_pmic_pinctrl_generic_pinmux_set_mux,

+};

+U_BOOT_DRIVER(qcom_pmic_pinctrl) = {

• .name = "qcom_pmic_pinctrl",
• .id = UCLASS_PINCTRL,
• .ops = &qcom_pmic_pinctrl_ops,

+};

Reviewed-by: Neil Armstrong neil.armstrong@linaro.org

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly caleb.connolly@linaro.org wrote:

Adjust the DT to match upstream bindings.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

arch/sandbox/dts/sandbox.dtsi | 9 ++++----- 1 file changed, 4 insertions(+), 5 deletions(-)

Reviewed-by: Sumit Garg sumit.garg@linaro.org

-Sumit

diff --git a/arch/sandbox/dts/sandbox.dtsi b/arch/sandbox/dts/sandbox.dtsi index 241f397ba6e7..c93ce7128942 100644 --- a/arch/sandbox/dts/sandbox.dtsi +++ b/arch/sandbox/dts/sandbox.dtsi @@ -419,17 +419,16 @@ #size-cells = <0x1>; pm8916@0 { compatible = "qcom,spmi-pmic";

•                   reg = <0x0 0x1>;
  

•                   reg = <0x0 0x0>;
                    #address-cells = <0x1>;
  

•                   #size-cells = <0x1>;
  

•                   #size-cells = <0x0>;
  
                    spmi_gpios: gpios@c000 {
                            compatible = "qcom,pm8916-gpio";
  

•                           reg = <0xc000 0x400>;
  

•                           reg = <0xc000>;
                            gpio-controller;
  

•                           gpio-count = <4>;
  

•                           gpio-ranges = <&spmi_gpios 0 0 4>;
                            #gpio-cells = <2>;
  

•                           gpio-bank-name="spmi";
                    };
            };
    };
  
  

-- 2.43.1

On 15/02/2024 21:52, Caleb Connolly wrote:

Most platforms have a handful of "special" GPIOs, like the MMC clock/data lanes, UFS reset, etc. These don't follow the usually naming scheme of "gpioX" and also have unique capabilities and registers. We can get away without supporting them all for now, but DT compatibility is still an issue.

Add support for allowing these to be specified after the other pins, and make all pinmux/pinconf calls for them nop.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

arch/arm/mach-snapdragon/include/mach/gpio.h | 2 ++ drivers/gpio/msm_gpio.c | 20 ++++++++++++++++++++ drivers/pinctrl/qcom/pinctrl-qcom.c | 12 ++++++++++++ 3 files changed, 34 insertions(+)

diff --git a/arch/arm/mach-snapdragon/include/mach/gpio.h b/arch/arm/mach-snapdragon/include/mach/gpio.h index 8dac62f870b9..c373f5a4cf3d 100644 --- a/arch/arm/mach-snapdragon/include/mach/gpio.h +++ b/arch/arm/mach-snapdragon/include/mach/gpio.h @@ -13,6 +13,8 @@ struct msm_pin_data { int pin_count; const unsigned int *pin_offsets;

• /* Index of first special pin, these are ignored for now */

• unsigned int special_pins_start; };

  static inline u32 qcom_pin_offset(const unsigned int *offs, unsigned int selector)

diff --git a/drivers/gpio/msm_gpio.c b/drivers/gpio/msm_gpio.c index 80cd28bb231f..8a5e8730e911 100644 --- a/drivers/gpio/msm_gpio.c +++ b/drivers/gpio/msm_gpio.c @@ -39,6 +39,10 @@ static int msm_gpio_direction_input(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev);

• /* Always NOP for special pins, assume they're in the correct state */
• if (gpio >= priv->pin_data->special_pins_start)

• return 0;
  

• /* Disable OE bit */ clrsetbits_le32(priv->base + GPIO_CONFIG_REG(dev, gpio), GPIO_OE_MASK, GPIO_OE_DISABLE);

@@ -50,6 +54,10 @@ static int msm_gpio_set_value(struct udevice *dev, unsigned int gpio, int value) { struct msm_gpio_bank *priv = dev_get_priv(dev);

• /* Always NOP for special pins, assume they're in the correct state */
• if (gpio >= priv->pin_data->special_pins_start)

• return 0;
  

• value = !!value; /* set value */ writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));

@@ -62,6 +70,10 @@ static int msm_gpio_direction_output(struct udevice *dev, unsigned int gpio, { struct msm_gpio_bank *priv = dev_get_priv(dev);

• /* Always NOP for special pins, assume they're in the correct state */
• if (gpio >= priv->pin_data->special_pins_start)

• return 0;
  

• value = !!value; /* set value */ writel(value << GPIO_OUT, priv->base + GPIO_IN_OUT_REG(dev, gpio));

@@ -76,6 +88,10 @@ static int msm_gpio_get_value(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev);

• /* Always NOP for special pins, assume they're in the correct state */
• if (gpio >= priv->pin_data->special_pins_start)

• return 0;
  

• return !!(readl(priv->base + GPIO_IN_OUT_REG(dev, gpio)) >> GPIO_IN); }

@@ -83,6 +99,10 @@ static int msm_gpio_get_function(struct udevice *dev, unsigned int gpio) { struct msm_gpio_bank *priv = dev_get_priv(dev);

• /* Always NOP for special pins, assume they're in the correct state */
• if (gpio >= priv->pin_data->special_pins_start)

• return 0;
  

• if (readl(priv->base + GPIO_CONFIG_REG(dev, gpio)) & GPIO_OE_ENABLE) return GPIOF_OUTPUT;

diff --git a/drivers/pinctrl/qcom/pinctrl-qcom.c b/drivers/pinctrl/qcom/pinctrl-qcom.c index dc3d8c4d9034..1ea4d21c41fc 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcom.c +++ b/drivers/pinctrl/qcom/pinctrl-qcom.c @@ -83,6 +83,10 @@ static int msm_pinmux_set(struct udevice *dev, unsigned int pin_selector, { struct msm_pinctrl_priv *priv = dev_get_priv(dev);

• /* Always NOP for special pins, assume they're in the correct state */
• if (pin_selector >= priv->data->pin_data.special_pins_start)

• return 0;
  

• clrsetbits_le32(priv->base + GPIO_CONFIG_REG(priv, pin_selector), TLMM_FUNC_SEL_MASK | TLMM_GPIO_DISABLE, priv->data->get_function_mux(func_selector) << 2);

@@ -94,6 +98,10 @@ static int msm_pinconf_set(struct udevice *dev, unsigned int pin_selector, { struct msm_pinctrl_priv *priv = dev_get_priv(dev);

• /* Always NOP for special pins */
• if (pin_selector >= priv->data->pin_data.special_pins_start)

• return 0;
  

• switch (param) { case PIN_CONFIG_DRIVE_STRENGTH: argument = (argument / 2) - 1;

@@ -136,6 +144,10 @@ int msm_pinctrl_bind(struct udevice *dev) const char *name; int ret;

• /* Make sure we don't indadvertently treat all pins as special pins. */
• if (!data->pin_data.special_pins_start)

• data->pin_data.special_pins_start = data->pin_data.pin_count;
  

• drv = lists_driver_lookup_name("pinctrl_qcom"); if (!drv) return -ENOENT;

Reviewed-by: Neil Armstrong neil.armstrong@linaro.org

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly caleb.connolly@linaro.org wrote:

Upstream devicetrees label GPIOs with "gpioX", not "GPIO_X", fix this for SoCs where we're now using upstream DT.

Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

drivers/pinctrl/qcom/pinctrl-apq8016.c | 26 +++++++-------- drivers/pinctrl/qcom/pinctrl-apq8096.c | 16 +++++----- drivers/pinctrl/qcom/pinctrl-qcs404.c | 58 ++++++++++++++++++++++++++++------ 3 files changed, 69 insertions(+), 31 deletions(-)

Reviewed-by: Sumit Garg sumit.garg@linaro.org

-Sumit

diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c index 8149ffd83cc4..10796710ba7a 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c @@ -14,18 +14,18 @@ #define MAX_PIN_NAME_LEN 32 static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); static const char * const msm_pinctrl_pins[] = {

•   "SDC1_CLK",
  

•   "SDC1_CMD",
  

•   "SDC1_DATA",
  

•   "SDC2_CLK",
  

•   "SDC2_CMD",
  

•   "SDC2_DATA",
  

•   "QDSD_CLK",
  

•   "QDSD_CMD",
  

•   "QDSD_DATA0",
  

•   "QDSD_DATA1",
  

•   "QDSD_DATA2",
  

•   "QDSD_DATA3",
  

•   "sdc1_clk",
  

•   "sdc1_cmd",
  

•   "sdc1_data",
  

•   "sdc2_clk",
  

•   "sdc2_cmd",
  

•   "sdc2_data",
  

•   "qdsd_clk",
  

•   "qdsd_cmd",
  

•   "qdsd_data0",
  

•   "qdsd_data1",
  

•   "qdsd_data2",
  

•   "qdsd_data3",
  

};

static const struct pinctrl_function msm_pinctrl_functions[] = { @@ -42,7 +42,7 @@ static const char *apq8016_get_pin_name(struct udevice *dev, unsigned int selector) { if (selector < 122) {

•           snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
  

•           snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
            return pin_name;
    } else {
            return msm_pinctrl_pins[selector - 122];
  

diff --git a/drivers/pinctrl/qcom/pinctrl-apq8096.c b/drivers/pinctrl/qcom/pinctrl-apq8096.c index d64ab1ff7bee..f2eeb4cf469a 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8096.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8096.c @@ -14,13 +14,13 @@ #define MAX_PIN_NAME_LEN 32 static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); static const char * const msm_pinctrl_pins[] = {

•   "SDC1_CLK",
  

•   "SDC1_CMD",
  

•   "SDC1_DATA",
  

•   "SDC2_CLK",
  

•   "SDC2_CMD",
  

•   "SDC2_DATA",
  

•   "SDC1_RCLK",
  

•   "sdc1_clk",
  

•   "sdc1_cmd",
  

•   "sdc1_data",
  

•   "sdc2_clk",
  

•   "sdc2_cmd",
  

•   "sdc2_data",
  

•   "sdc1_rclk",
  

};

static const struct pinctrl_function msm_pinctrl_functions[] = { @@ -37,7 +37,7 @@ static const char *apq8096_get_pin_name(struct udevice *dev, unsigned int selector) { if (selector < 150) {

•           snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
  

•           snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
            return pin_name;
    } else {
            return msm_pinctrl_pins[selector - 150];
  

diff --git a/drivers/pinctrl/qcom/pinctrl-qcs404.c b/drivers/pinctrl/qcom/pinctrl-qcs404.c index ac00afa2a1f4..5066f2bba6b3 100644 --- a/drivers/pinctrl/qcom/pinctrl-qcs404.c +++ b/drivers/pinctrl/qcom/pinctrl-qcs404.c @@ -10,20 +10,24 @@

#include "pinctrl-qcom.h"

+#define NORTH 0x00300000 +#define SOUTH 0x00000000 +#define EAST 0x06b00000

#define MAX_PIN_NAME_LEN 32 static char pin_name[MAX_PIN_NAME_LEN] __section(".data"); static const char * const msm_pinctrl_pins[] = {

•   "SDC1_RCLK",
  

•   "SDC1_CLK",
  

•   "SDC1_CMD",
  

•   "SDC1_DATA",
  

•   "SDC2_CLK",
  

•   "SDC2_CMD",
  

•   "SDC2_DATA",
  

•   "sdc1_rclk",
  

•   "sdc1_clk",
  

•   "sdc1_cmd",
  

•   "sdc1_data",
  

•   "sdc2_clk",
  

•   "sdc2_cmd",
  

•   "sdc2_data",
  

};

static const struct pinctrl_function msm_pinctrl_functions[] = {

•   {"blsp_uart2", 1},
  

•   {"gpio", 0},
    {"rgmii_int", 1},
    {"rgmii_ck", 1},
    {"rgmii_tx", 1},
  

@@ -37,6 +41,40 @@ static const struct pinctrl_function msm_pinctrl_functions[] = { {"blsp_i2c_scl_a2", 3}, {"blsp_i2c3", 2}, {"blsp_i2c4", 1},

•   {"blsp_uart_tx_a2", 1},
  

•   {"blsp_uart_rx_a2", 1},
  

+};

+static const unsigned int qcs404_pin_offsets[] = {

•   [0] = SOUTH,    [1] = SOUTH,    [2] = SOUTH,    [3] = SOUTH,    [4] = SOUTH,
  

•   [5] = SOUTH,   [6] = SOUTH,   [7] = SOUTH,   [8] = SOUTH,    [9] = SOUTH,
  

•   [10] = SOUTH,   [11] = SOUTH,   [12] = SOUTH,  [13] = SOUTH,  [14] = SOUTH,
  

•   [15] = SOUTH,  [16] = SOUTH,  [17] = NORTH,  [18] = NORTH,  [19] = NORTH,
  

•   [20] = NORTH,  [21] = SOUTH,  [22] = NORTH,  [23] = NORTH,  [24] = NORTH,
  

•   [25] = NORTH,  [26] = EAST,  [27] = EAST,   [28] = EAST,   [29] = EAST,
  

•   [30] = NORTH,   [31] = NORTH,  [32] = NORTH,  [33] = NORTH,  [34] = SOUTH,
  

•   [35] = SOUTH,  [36] = NORTH,  [37] = NORTH,  [38] = NORTH,  [39] = EAST,
  

•   [40] = EAST,  [41] = EAST,   [42] = EAST,   [43] = EAST,   [44] = EAST,
  

•   [45] = EAST,   [46] = EAST,   [47] = EAST,   [48] = EAST,   [49] = EAST,
  

•   [50] = EAST,  [51] = EAST,  [52] = EAST,  [53] = EAST,  [54] = EAST,
  

•   [55] = EAST,  [56] = EAST,  [57] = EAST,  [58] = EAST,  [59] = EAST,
  

•   [60] = NORTH,  [61] = NORTH,  [62] = NORTH,  [63] = NORTH,  [64] = NORTH,
  

•   [65] = NORTH,  [66] = NORTH,  [67] = NORTH,  [68] = NORTH,  [69] = NORTH,
  

•   [70] = NORTH,   [71] = NORTH,   [72] = NORTH,   [73] = NORTH,   [74] = NORTH,
  

•   [75] = NORTH,   [76] = NORTH,   [77] = NORTH,   [78] = EAST,   [79] = EAST,
  

•   [80] = EAST,  [81] = EAST,  [82] = NORTH,  [83] = NORTH,  [84] = NORTH,
  

•   [85] = NORTH,   [86] = EAST,   [87] = EAST,   [88] = EAST,   [89] = EAST,
  

•   [90] = EAST,  [91] = EAST,  [92] = EAST,  [93] = EAST,  [94] = EAST,
  

•   [95] = EAST,  [96] = EAST,  [97] = EAST,  [98] = EAST,  [99] = EAST,
  

•   [100] = EAST, [101] = EAST, [102] = EAST, [103] = EAST, [104] = EAST,
  

•   [105] = EAST, [106] = EAST, [107] = EAST, [108] = EAST, [109] = EAST,
  

•   [110] = EAST, [111] = EAST, [112] = EAST, [113] = EAST, [114] = EAST,
  

•   [115] = EAST, [116] = EAST, [117] = NORTH, [118] = NORTH, [119] = EAST,
  

•   /*
  

•    * There's 126 pins but the last ones are special and have non-standard registers
  

•    * so we leave them out here. The pinctrl and GPIO drivers both currently ignore
  

•    * these pins.
  

•    */
  

};

static const char *qcs404_get_function_name(struct udevice *dev, @@ -49,7 +87,7 @@ static const char *qcs404_get_pin_name(struct udevice *dev, unsigned int selector) { if (selector < 120) {

•           snprintf(pin_name, MAX_PIN_NAME_LEN, "GPIO_%u", selector);
  

•           snprintf(pin_name, MAX_PIN_NAME_LEN, "gpio%u", selector);
            return pin_name;
    } else {
            return msm_pinctrl_pins[selector - 120];
  

@@ -62,7 +100,7 @@ static unsigned int qcs404_get_function_mux(unsigned int selector) }

static struct msm_pinctrl_data qcs404_data = {

•   .pin_data = { .pin_count = 126, },
  

•   .pin_data = { .pin_count = 126, .pin_offsets = qcs404_pin_offsets, .special_pins_start = 120, },
    .functions_count = ARRAY_SIZE(msm_pinctrl_functions),
    .get_function_name = qcs404_get_function_name,
    .get_function_mux = qcs404_get_function_mux,
  
  

-- 2.43.1

On 15/02/2024 21:52, Caleb Connolly wrote:

On the DB410c we support running as a first stage bootloader. This requires initialising the GPIOs which are muxed to UART before they can be used. Add DM_FLAG_PRE_RELOC to the apq8016 pinctrl driver to ensure that we do this early enough.

This is required to prevent the first few lines of UART log from being dropped.

Reported-by: Sumit Garg sumit.garg@linaro.org Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

---

drivers/pinctrl/qcom/pinctrl-apq8016.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/drivers/pinctrl/qcom/pinctrl-apq8016.c b/drivers/pinctrl/qcom/pinctrl-apq8016.c index 10796710ba7a..df5bd1c19f6e 100644 --- a/drivers/pinctrl/qcom/pinctrl-apq8016.c +++ b/drivers/pinctrl/qcom/pinctrl-apq8016.c @@ -73,4 +73,5 @@ U_BOOT_DRIVER(pinctrl_apq8016) = { .of_match = msm_pinctrl_ids, .ops = &msm_pinctrl_ops, .bind = msm_pinctrl_bind,

• .flags = DM_FLAG_PRE_RELOC, };

Reviewed-by: Neil Armstrong neil.armstrong@linaro.org

On Thu, 15 Feb 2024 at 21:03, Caleb Connolly caleb.connolly@linaro.org wrote:

Add a config fragment for building U-Boot such that it can be chainloaded by aboot/LK rather than being flashed directly to the aboot partition.

How does this work in practice? I think a lot of devices, one example I see is signed vs unsigned, or emmc vs other storage, have to configs, how would a user choose with LK vs the other option here?

Reviewed-by: Neil Armstrong neil.armstrong@linaro.org Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

---

board/qualcomm/dragonboard410c/configs/chainloaded.config | 7 +++++++ 1 file changed, 7 insertions(+)

diff --git a/board/qualcomm/dragonboard410c/configs/chainloaded.config b/board/qualcomm/dragonboard410c/configs/chainloaded.config new file mode 100644 index 000000000000..3fd064924a1f --- /dev/null +++ b/board/qualcomm/dragonboard410c/configs/chainloaded.config @@ -0,0 +1,7 @@ +# CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK is not set +CONFIG_TEXT_BASE=0x0 +# CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR is not set +# CONFIG_REMAKE_ELF is not set +CONFIG_POSITION_INDEPENDENT=y +CONFIG_INIT_SP_RELATIVE=y +CONFIG_SYS_INIT_SP_BSS_OFFSET=524288

-- 2.43.1

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly caleb.connolly@linaro.org wrote:

db820c predated support for prepending the kernel image header automatically, drop it's custom linker script and head.S in favour of this generic support.

Reviewed-by: Neil Armstrong neil.armstrong@linaro.org Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

---

arch/arm/mach-snapdragon/Kconfig | 1 + board/qualcomm/dragonboard820c/Makefile | 1 - board/qualcomm/dragonboard820c/head.S | 33 --------- board/qualcomm/dragonboard820c/u-boot.lds | 111 ------------------------------ 4 files changed, 1 insertion(+), 145 deletions(-)

Reviewed-by: Sumit Garg sumit.garg@linaro.org

-Sumit

diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index ad6671081910..f897c393464f 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -45,6 +45,7 @@ config TARGET_DRAGONBOARD410C

config TARGET_DRAGONBOARD820C bool "96Boards Dragonboard 820C"

•   select LINUX_KERNEL_IMAGE_HEADER
    imply CLK_QCOM_APQ8096
    imply PINCTRL_QCOM_APQ8096
    imply BUTTON_QCOM_PMIC
  

diff --git a/board/qualcomm/dragonboard820c/Makefile b/board/qualcomm/dragonboard820c/Makefile index 643311f5b3ba..2ae6d16364aa 100644 --- a/board/qualcomm/dragonboard820c/Makefile +++ b/board/qualcomm/dragonboard820c/Makefile @@ -3,4 +3,3 @@ # (C) Copyright 2017 Jorge Ramirez-Ortiz jorge.ramirez-ortiz@gmail.com

obj-y := dragonboard820c.o -extra-y += head.o diff --git a/board/qualcomm/dragonboard820c/head.S b/board/qualcomm/dragonboard820c/head.S deleted file mode 100644 index b052a858fd32..000000000000 --- a/board/qualcomm/dragonboard820c/head.S +++ /dev/null @@ -1,33 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*

• • ARM64 header for proper chain-loading with Little Kernel.
• • Little Kernel shipped with Dragonboard820C boots standard Linux images for
• • ARM64. This file adds header that is required to boot U-Boot properly.
• • For details see:
• • https://www.kernel.org/doc/Documentation/arm64/booting.txt
• • (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com
• */

-#include <config.h>

-/*

• • per document in linux/Doc/arm64/booting.text
• */

-.global _arm64_header -_arm64_header:

•   b _start
  

•   .word 0
  

•   .quad   CONFIG_TEXT_BASE-PHYS_SDRAM_1 /* Image load offset, LE */
  

•   .quad   0    /* Effective size of kernel image, little-endian */
  

•   .quad   0    /* kernel flags, little-endian */
  

•   .quad   0    /* reserved */
  

•   .quad   0    /* reserved */
  

•   .quad   0    /* reserved */
  

•   .byte   0x41 /* Magic number, "ARM\x64" */
  

•   .byte   0x52
  

•   .byte   0x4d
  

•   .byte   0x64
  

•   .word   0    /* reserved (used for PE COFF offset) */
  

diff --git a/board/qualcomm/dragonboard820c/u-boot.lds b/board/qualcomm/dragonboard820c/u-boot.lds deleted file mode 100644 index 5251b59fbe76..000000000000 --- a/board/qualcomm/dragonboard820c/u-boot.lds +++ /dev/null @@ -1,111 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*

• • Override linker script for fastboot-readable images
• • (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com
• • Based on arch/arm/cpu/armv8/u-boot.lds (Just add header)
• */

-OUTPUT_FORMAT("elf64-littleaarch64", "elf64-littleaarch64", "elf64-littleaarch64") -OUTPUT_ARCH(aarch64) -ENTRY(_arm64_header) -SECTIONS -{

•   . = 0x00000000;
  

•   . = ALIGN(8);
  

•   .text :
  

•   {
  

•           *(.__image_copy_start)
  

•           board/qualcomm/dragonboard820c/head.o (.text*)
  

•           CPUDIR/start.o (.text*)
  

•   }
  

•   /* This needs to come before *(.text*) */
  

•   .efi_runtime : {
  

•            __efi_runtime_start = .;
  

•           *(.text.efi_runtime*)
  

•           *(.rodata.efi_runtime*)
  

•           *(.data.efi_runtime*)
  

•            __efi_runtime_stop = .;
  

•   }
  

•   .text_rest :
  

•   {
  

•           *(.text*)
  

•   }
  

•   . = ALIGN(8);
  

•   .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) }
  

•   . = ALIGN(8);
  

•   .data : {
  

•           *(.data*)
  

•   }
  

•   . = ALIGN(8);
  

•   . = .;
  

•   . = ALIGN(8);
  

•   __u_boot_list : {
  

•           KEEP(*(SORT(__u_boot_list*)));
  

•   }
  

•   . = ALIGN(8);
  

•   .efi_runtime_rel : {
  

•            __efi_runtime_rel_start = .;
  

•           *(.rel*.efi_runtime)
  

•           *(.rel*.efi_runtime.*)
  

•            __efi_runtime_rel_stop = .;
  

•   }
  

•   . = ALIGN(8);
  

•   .image_copy_end :
  

•   {
  

•           *(.__image_copy_end)
  

•   }
  

•   . = ALIGN(8);
  

•   .rel_dyn_start :
  

•   {
  

•           *(.__rel_dyn_start)
  

•   }
  

•   .rela.dyn : {
  

•           *(.rela*)
  

•   }
  

•   .rel_dyn_end :
  

•   {
  

•           *(.__rel_dyn_end)
  

•   }
  

•   _end = .;
  

•   . = ALIGN(8);
  

•   .bss_start : {
  

•           KEEP(*(.__bss_start));
  

•   }
  

•   .bss : {
  

•           *(.bss*)
  

•            . = ALIGN(8);
  

•   }
  

•   .bss_end : {
  

•           KEEP(*(.__bss_end));
  

•   }
  

•   /DISCARD/ : { *(.dynsym) }
  

•   /DISCARD/ : { *(.dynstr*) }
  

•   /DISCARD/ : { *(.dynamic*) }
  

•   /DISCARD/ : { *(.plt*) }
  

•   /DISCARD/ : { *(.interp*) }
  

•   /DISCARD/ : { *(.gnu*) }
  

-}

-- 2.43.1

On Fri, 16 Feb 2024 at 02:22, Caleb Connolly caleb.connolly@linaro.org wrote:

Historically, Qualcomm boards have relied on heavy hardcoding in U-Boot, in many cases to the specific SoC but also to the board itself (e.g. memory map). This has been largely resolved by modernising the Qualcomm drivers in U-Boot, however the board code still largely follows this model.

This patch removes the board specific memory maps and duplicated board init code, replacing it with generic init code.

The memory map is now built at runtime based on data read from DT, this allows for the memory map to be provided without having to recompile U-Boot. Support is also added for booting with appended DTBs, so that the first-stage bootloader can populate the memory map for us.

The sdm845 specific init code is dropped entirely, it set an environment variable depending on if a button was pressed, but this variable wasn't used in U-Boot, and could be written to use the button command instead.

The KASLR detection is also dropped as with appended dtb, the kaslr seed can be read directly from the DTB passed to U-Boot.

A new qcom_defconfig is added, with the aim of providing a generic U-Boot configuration that will work on as many Qualcomm boards as possible. It replaces the defconfig files for the Dragonboard 845c, Galaxy S9, and QCS404 EVB. For now the db410c and 820c are excluded as they still have some board code left.

Similarly, the config headers for db845c, starqltechn, and qcs404-evb are replaced by a single qcom header.

The previously db410c-specific board_usb_init() function is made to be generic and is added to mach-snapdragon. While we lack proper modelling for USB configuration, using a well-known named pinctrl state is a reasonably generic middleground, and works using upstream DT. This function will do nothing unless the USB node has a pinctrl state named "device", in which case it will be set when entering USB peripheral mode.

Reviewed-by: Neil Armstrong neil.armstrong@linaro.org Signed-off-by: Caleb Connolly caleb.connolly@linaro.org

---

arch/arm/Kconfig | 3 + arch/arm/dts/Makefile | 9 +- arch/arm/mach-snapdragon/Kconfig | 96 ++-------- arch/arm/mach-snapdragon/Makefile | 6 +- arch/arm/mach-snapdragon/board.c | 215 +++++++++++++++++++++++ arch/arm/mach-snapdragon/init_sdm845.c | 73 -------- arch/arm/mach-snapdragon/sysmap-apq8016.c | 31 ---- arch/arm/mach-snapdragon/sysmap-apq8096.c | 31 ---- arch/arm/mach-snapdragon/sysmap-qcs404.c | 43 ----- arch/arm/mach-snapdragon/sysmap-sdm845.c | 31 ---- board/qualcomm/dragonboard410c/Kconfig | 15 -- board/qualcomm/dragonboard410c/dragonboard410c.c | 41 ----- board/qualcomm/dragonboard820c/Kconfig | 15 -- board/qualcomm/dragonboard820c/dragonboard820c.c | 39 +--- board/qualcomm/dragonboard845c/Kconfig | 12 -- board/qualcomm/qcs404-evb/Kconfig | 15 -- board/qualcomm/qcs404-evb/qcs404-evb.c | 21 +-- configs/dragonboard410c_defconfig | 6 +- configs/dragonboard820c_defconfig | 6 +- configs/dragonboard845c_defconfig | 29 --- configs/qcom_defconfig | 67 +++++++ configs/qcs404evb_defconfig | 5 +- configs/starqltechn_defconfig | 41 ----- include/configs/dragonboard845c.h | 20 --- include/configs/qcom.h | 21 +++ include/configs/qcs404-evb.h | 20 --- include/configs/sdm845.h | 26 --- 27 files changed, 345 insertions(+), 592 deletions(-)

Reviewed-by: Sumit Garg sumit.garg@linaro.org

-Sumit

diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 6b072be24634..672577d0ddcc 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1095,6 +1095,9 @@ config ARCH_SNAPDRAGON select OF_SEPARATE select SMEM select SPMI

•   select OF_BOARD
  

•   select SAVE_PREV_BL_FDT_ADDR
  

•   select LINUX_KERNEL_IMAGE_HEADER
    imply CMD_DM
  
  

config ARCH_SOCFPGA diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index ce10d3dbb07d..751035a577f6 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -631,10 +631,11 @@ dtb-$(CONFIG_TARGET_SL28) += fsl-ls1028a-kontron-sl28.dtb \

dtb-$(CONFIG_TARGET_TEN64) += fsl-ls1088a-ten64.dtb

-dtb-$(CONFIG_TARGET_DRAGONBOARD410C) += dragonboard410c.dtb -dtb-$(CONFIG_TARGET_DRAGONBOARD820C) += dragonboard820c.dtb -dtb-$(CONFIG_TARGET_STARQLTECHN) += starqltechn.dtb -dtb-$(CONFIG_TARGET_QCS404EVB) += qcs404-evb.dtb +dtb-$(CONFIG_ARCH_SNAPDRAGON) += dragonboard410c.dtb \

•   dragonboard820c.dtb \
  

•   dragonboard845c.dtb \
  

•   starqltechn.dtb \
  

•   qcs404-evb.dtb
  
  

dtb-$(CONFIG_TARGET_STEMMY) += ste-ux500-samsung-stemmy.dtb

diff --git a/arch/arm/mach-snapdragon/Kconfig b/arch/arm/mach-snapdragon/Kconfig index f897c393464f..96e44e2c5491 100644 --- a/arch/arm/mach-snapdragon/Kconfig +++ b/arch/arm/mach-snapdragon/Kconfig @@ -3,6 +3,9 @@ if ARCH_SNAPDRAGON config SYS_SOC default "snapdragon"

+config SYS_VENDOR

•   default "qualcomm"
  

config SYS_MALLOC_F_LEN default 0x2000

@@ -12,91 +15,24 @@ config SPL_SYS_MALLOC_F config SPL_SYS_MALLOC_F_LEN default 0x2000

-config SDM845

•   bool "Qualcomm Snapdragon 845 SoC"
  

•   select LINUX_KERNEL_IMAGE_HEADER
  

•   imply CLK_QCOM_SDM845
  

•   imply PINCTRL_QCOM_SDM845
  

•   imply BUTTON_QCOM_PMIC
  

config LNX_KRNL_IMG_TEXT_OFFSET_BASE default 0x80000000

-choice

•   prompt "Snapdragon board select"
  

-config TARGET_DRAGONBOARD410C

•   bool "96Boards Dragonboard 410C"
  

•   select BOARD_LATE_INIT
  

•   select ENABLE_ARM_SOC_BOOT0_HOOK
  

•   imply CLK_QCOM_APQ8016
  

•   imply PINCTRL_QCOM_APQ8016
  

•   imply BUTTON_QCOM_PMIC
  

+config SYS_BOARD

•   string "Qualcomm custom board"
    help
  

•     Support for 96Boards Dragonboard 410C. This board complies with
  

•     96Board Open Platform Specifications. Features:
  

•     - Qualcomm Snapdragon 410C SoC - APQ8016 (4xCortex A53, Adreno 306)
  

•     - 1GiB RAM
  

•     - 8GiB eMMC, uSD slot
  

•     - WiFi, Bluetooth and GPS module
  

•     - 2x Host, 1x Device USB port
  

•     - HDMI
  

•     - 20-pin low speed and 40-pin high speed expanders, 4 LED, 3 buttons
  

•     The Dragonboard 410c and 820c have additional board init
  

•     code that isn't shared with other Qualcomm boards.
  

•     Based on this option board/qualcomm/<CONFIG_SYS_BOARD> will
  

•     be used.
  
  

-config TARGET_DRAGONBOARD820C

•   bool "96Boards Dragonboard 820C"
  

•   select LINUX_KERNEL_IMAGE_HEADER
  

•   imply CLK_QCOM_APQ8096
  

•   imply PINCTRL_QCOM_APQ8096
  

•   imply BUTTON_QCOM_PMIC
  

+config SYS_CONFIG_NAME

•   string "Board configuration name"
  

•   default SYS_BOARD if SYS_BOARD != ""
  

•   default "qcom"
    help
  

•     Support for 96Boards Dragonboard 820C. This board complies with
  

•     96Board Open Platform Specifications. Features:
  

•     - Qualcomm Snapdragon 820C SoC - APQ8096 (4xKyro CPU)
  

•     - 3GiB RAM
  

•     - 32GiB UFS drive
  

-config TARGET_DRAGONBOARD845C

•   bool "96Boards Dragonboard 845C"
  

•   help
  

•     Support for 96Boards Dragonboard 845C aka Robotics RB3 Development
  

•     Platform. This board complies with 96Boards Open Platform
  

•     Specifications. Features:
  

•     - Qualcomm Snapdragon SDA845 SoC
  

•     - 4GiB RAM
  

•     - 64GiB UFS drive
  

•   select MISC_INIT_R
  

•   select SDM845
  

-config TARGET_STARQLTECHN

•   bool "Samsung S9 SM-G9600(starqltechn)"
  

•   help
  

•     Support for Samsung S9 SM-G9600(starqltechn) board.
  

•     Features:
  

•     - Qualcomm Snapdragon SDM845 SoC
  

•     - 4GiB RAM
  

•     - 64GiB UFS drive
  

•   select MISC_INIT_R
  

•   select SDM845
  

-config TARGET_QCS404EVB

•   bool "Qualcomm Technologies, Inc. QCS404 EVB"
  

•   select LINUX_KERNEL_IMAGE_HEADER
  

•   imply CLK_QCOM_QCS404
  

•   imply PINCTRL_QCOM_QCS404
  

•   help
  

•     Support for Qualcomm Technologies, Inc. QCS404 evaluation board.
  

•     Features:
  

•     - Qualcomm Snapdragon QCS404 SoC
  

•     - 1GiB RAM
  

•     - 8GiB eMMC, uSD slot
  

-endchoice

-source "board/qualcomm/dragonboard410c/Kconfig" -source "board/qualcomm/dragonboard820c/Kconfig" -source "board/qualcomm/dragonboard845c/Kconfig" -source "board/samsung/starqltechn/Kconfig" -source "board/qualcomm/qcs404-evb/Kconfig"

•     This option contains information about board configuration name.
  

•     Based on this option include/configs/<CONFIG_SYS_CONFIG_NAME>.h header
  

•     will be used for board configuration.
  
  

endif diff --git a/arch/arm/mach-snapdragon/Makefile b/arch/arm/mach-snapdragon/Makefile index d02432df8b04..857171e593da 100644 --- a/arch/arm/mach-snapdragon/Makefile +++ b/arch/arm/mach-snapdragon/Makefile @@ -2,8 +2,4 @@ # # (C) Copyright 2015 Mateusz Kulikowski mateusz.kulikowski@gmail.com

-obj-$(CONFIG_SDM845) += sysmap-sdm845.o -obj-$(CONFIG_SDM845) += init_sdm845.o -obj-$(CONFIG_TARGET_DRAGONBOARD820C) += sysmap-apq8096.o -obj-$(CONFIG_TARGET_DRAGONBOARD410C) += sysmap-apq8016.o -obj-$(CONFIG_TARGET_QCS404EVB) += sysmap-qcs404.o +obj-y += board.o diff --git a/arch/arm/mach-snapdragon/board.c b/arch/arm/mach-snapdragon/board.c new file mode 100644 index 000000000000..a1867852bcca --- /dev/null +++ b/arch/arm/mach-snapdragon/board.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*

• • Common initialisation for Qualcomm Snapdragon boards.
• • Copyright (c) 2024 Linaro Ltd.
• • Author: Caleb Connolly caleb.connolly@linaro.org
• */

+#include "time.h" +#include <asm/armv8/mmu.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/psci.h> +#include <asm/system.h> +#include <dm/device.h> +#include <dm/pinctrl.h> +#include <dm/uclass-internal.h> +#include <dm/read.h> +#include <env.h> +#include <init.h> +#include <linux/arm-smccc.h> +#include <linux/bug.h> +#include <linux/psci.h> +#include <linux/sizes.h> +#include <malloc.h> +#include <usb.h>

+DECLARE_GLOBAL_DATA_PTR;

+static struct mm_region rbx_mem_map[CONFIG_NR_DRAM_BANKS + 2] = { { 0 } };

+struct mm_region *mem_map = rbx_mem_map;

+int dram_init(void) +{

•   return fdtdec_setup_mem_size_base();
  

+}

+static int ddr_bank_cmp(const void *v1, const void *v2) +{

•   const struct {
  

•           phys_addr_t start;
  

•           phys_size_t size;
  

•   } *res1 = v1, *res2 = v2;
  

•   if (!res1->size)
  

•           return 1;
  

•   if (!res2->size)
  

•           return -1;
  

•   return (res1->start >> 24) - (res2->start >> 24);
  

+}

+int dram_init_banksize(void) +{

•   int ret;
  

•   ret = fdtdec_setup_memory_banksize();
  

•   if (ret < 0)
  

•           return ret;
  

•   if (CONFIG_NR_DRAM_BANKS < 2)
  

•           return 0;
  

•   /* Sort our RAM banks -_- */
  

•   qsort(gd->bd->bi_dram, CONFIG_NR_DRAM_BANKS, sizeof(gd->bd->bi_dram[0]), ddr_bank_cmp);
  

•   return 0;
  

+}

+static void show_psci_version(void) +{

•   struct arm_smccc_res res;
  

•   arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
  

•   debug("PSCI:  v%ld.%ld\n",
  

•         PSCI_VERSION_MAJOR(res.a0),
  

•         PSCI_VERSION_MINOR(res.a0));
  

+}

+void *board_fdt_blob_setup(int *err) +{

•   phys_addr_t fdt;
  

•   /* Return DTB pointer passed by ABL */
  

•   *err = 0;
  

•   fdt = get_prev_bl_fdt_addr();
  

•   /*
  

•    * If we bail then the board will simply not boot, instead let's
  

•    * try and use the FDT built into U-Boot if there is one...
  

•    * This avoids having a hard dependency on the previous stage bootloader
  

•    */
  

•   if (IS_ENABLED(CONFIG_OF_SEPARATE) && (!fdt || fdt != ALIGN(fdt, SZ_4K))) {
  

•           debug("%s: Using built in FDT, bootloader gave us %#llx\n", __func__, fdt);
  

•           return (void *)gd->fdt_blob;
  

•   }
  

•   return (void *)fdt;
  

+}

+void reset_cpu(void) +{

•   psci_system_reset();
  

+}

+/*

• • Some Qualcomm boards require GPIO configuration when switching USB modes.
• • Support setting this configuration via pinctrl state.
• */

+int board_usb_init(int index, enum usb_init_type init) +{

•   struct udevice *usb;
  

•   int ret = 0;
  

•   /* USB device */
  

•   ret = uclass_find_device_by_seq(UCLASS_USB, index, &usb);
  

•   if (ret) {
  

•           printf("Cannot find USB device\n");
  

•           return ret;
  

•   }
  

•   ret = dev_read_stringlist_search(usb, "pinctrl-names",
  

•                                    "device");
  

•   /* No "device" pinctrl state, so just bail */
  

•   if (ret < 0)
  

•           return 0;
  

•   /* Select "default" or "device" pinctrl */
  

•   switch (init) {
  

•   case USB_INIT_HOST:
  

•           pinctrl_select_state(usb, "default");
  

•           break;
  

•   case USB_INIT_DEVICE:
  

•           pinctrl_select_state(usb, "device");
  

•           break;
  

•   default:
  

•           debug("Unknown usb_init_type %d\n", init);
  

•           break;
  

•   }
  

•   return 0;
  

+}

+/*

• • Some boards still need board specific init code, they can implement that by
• • overriding this function.
• • FIXME: get rid of board specific init code
• */

+void __weak qcom_board_init(void) +{ +}

+int board_init(void) +{

•   show_psci_version();
  

•   qcom_board_init();
  

•   return 0;
  

+}

+static void build_mem_map(void) +{

•   int i;
  

•   /*
  

•    * Ensure the peripheral block is sized to correctly cover the address range
  

•    * up to the first memory bank.
  

•    * Don't map the first page to ensure that we actually trigger an abort on a
  

•    * null pointer access rather than just hanging.
  

•    * FIXME: we should probably split this into more precise regions
  

•    */
  

•   mem_map[0].phys = 0x1000;
  

•   mem_map[0].virt = mem_map[0].phys;
  

•   mem_map[0].size = gd->bd->bi_dram[0].start - mem_map[0].phys;
  

•   mem_map[0].attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  

•                    PTE_BLOCK_NON_SHARE |
  

•                    PTE_BLOCK_PXN | PTE_BLOCK_UXN;
  

•   debug("Configured memory map:\n");
  

•   debug("  0x%016llx - 0x%016llx: Peripheral block\n",
  

•         mem_map[0].phys, mem_map[0].phys + mem_map[0].size);
  

•   /*
  

•    * Now add memory map entries for each DRAM bank, ensuring we don't
  

•    * overwrite the list terminator
  

•    */
  

•   for (i = 0; i < ARRAY_SIZE(rbx_mem_map) - 2 && gd->bd->bi_dram[i].size; i++) {
  

•           if (i == ARRAY_SIZE(rbx_mem_map) - 1) {
  

•                   log_warning("Too many DRAM banks!\n");
  

•                   break;
  

•           }
  

•           mem_map[i + 1].phys = gd->bd->bi_dram[i].start;
  

•           mem_map[i + 1].virt = mem_map[i + 1].phys;
  

•           mem_map[i + 1].size = gd->bd->bi_dram[i].size;
  

•           mem_map[i + 1].attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  

•                                PTE_BLOCK_INNER_SHARE;
  

•           debug("  0x%016llx - 0x%016llx: DDR bank %d\n",
  

•                 mem_map[i + 1].phys, mem_map[i + 1].phys + mem_map[i + 1].size, i);
  

•   }
  

+}

+u64 get_page_table_size(void) +{

•   return SZ_64K;
  

+}

+void enable_caches(void) +{

•   build_mem_map();
  

•   icache_enable();
  

•   dcache_enable();
  

+} diff --git a/arch/arm/mach-snapdragon/init_sdm845.c b/arch/arm/mach-snapdragon/init_sdm845.c deleted file mode 100644 index 067acc9a6f44..000000000000 --- a/arch/arm/mach-snapdragon/init_sdm845.c +++ /dev/null @@ -1,73 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*

• • Common init part for boards based on SDM845
• • (C) Copyright 2021 Dzmitry Sankouski dsankouski@gmail.com
• */

-#include <button.h> -#include <init.h> -#include <env.h> -#include <common.h> -#include <asm/system.h> -#include <asm/gpio.h> -#include <dm.h>

-DECLARE_GLOBAL_DATA_PTR;

-int dram_init(void) -{

•   return fdtdec_setup_mem_size_base();
  

-}

-void reset_cpu(void) -{

•   psci_system_reset();
  

-}

-__weak int board_init(void) -{

•   return 0;
  

-}

-/* Check for vol- and power buttons */ -__weak int misc_init_r(void) -{

•   struct udevice *btn;
  

•   int ret;
  

•   enum button_state_t state;
  

•   ret = button_get_by_label("pwrkey", &btn);
  

•   if (ret < 0) {
  

•           printf("Couldn't find power button!\n");
  

•           return ret;
  

•   }
  

•   state = button_get_state(btn);
  

•   if (state == BUTTON_ON) {
  

•           env_set("key_power", "1");
  

•           printf("Power button pressed\n");
  

•   } else {
  

•           env_set("key_power", "0");
  

•   }
  

•   /*
  

•    * search for kaslr address, set by primary bootloader by searching first
  

•    * 0x100 relocated bytes at u-boot's initial load address range
  

•    */
  

•   uintptr_t start = gd->ram_base;
  

•   uintptr_t end = start + 0x800000;
  

•   u8 *addr = (u8 *)start;
  

•   phys_addr_t *relocaddr = (phys_addr_t *)gd->relocaddr;
  

•   u32 block_size = 0x1000;
  

•   while (memcmp(addr, relocaddr, 0x100) && (uintptr_t)addr < end)
  

•           addr += block_size;
  

•   if ((uintptr_t)addr >= end)
  

•           printf("KASLR not found in range 0x%lx - 0x%lx", start, end);
  

•   else
  

•           env_set_addr("KASLR", addr);
  

•   return 0;
  

-} diff --git a/arch/arm/mach-snapdragon/sysmap-apq8016.c b/arch/arm/mach-snapdragon/sysmap-apq8016.c deleted file mode 100644 index ffa3f9aa3532..000000000000 --- a/arch/arm/mach-snapdragon/sysmap-apq8016.c +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*

• • Qualcomm APQ8016 memory map
• • (C) Copyright 2016 Mateusz Kulikowski mateusz.kulikowski@gmail.com
• */

-#include <common.h> -#include <asm/armv8/mmu.h>

-static struct mm_region apq8016_mem_map[] = {

•   {
  

•           .virt = 0x0UL, /* Peripheral block */
  

•           .phys = 0x0UL, /* Peripheral block */
  

•           .size = 0x8000000UL,
  

•           .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  

•                    PTE_BLOCK_NON_SHARE |
  

•                    PTE_BLOCK_PXN | PTE_BLOCK_UXN
  

•   }, {
  

•           .virt = 0x80000000UL, /* DDR */
  

•           .phys = 0x80000000UL, /* DDR */
  

•           .size = 0x80000000UL,
  

•           .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  

•                    PTE_BLOCK_INNER_SHARE
  

•   }, {
  

•           /* List terminator */
  

•           0,
  

•   }
  

-};

-struct mm_region *mem_map = apq8016_mem_map; diff --git a/arch/arm/mach-snapdragon/sysmap-apq8096.c b/arch/arm/mach-snapdragon/sysmap-apq8096.c deleted file mode 100644 index 0614f8308d02..000000000000 --- a/arch/arm/mach-snapdragon/sysmap-apq8096.c +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*

• • Qualcomm APQ8096 memory map
• • (C) Copyright 2017 Jorge Ramirez Ortiz jorge.ramirez-ortiz@linaro.org
• */

-#include <common.h> -#include <asm/armv8/mmu.h>

-static struct mm_region apq8096_mem_map[] = {

•   {
  

•           .virt = 0x0UL, /* Peripheral block */
  

•           .phys = 0x0UL, /* Peripheral block */
  

•           .size = 0x10000000UL,
  

•           .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  

•                    PTE_BLOCK_NON_SHARE |
  

•                    PTE_BLOCK_PXN | PTE_BLOCK_UXN
  

•   }, {
  

•           .virt = 0x80000000UL, /* DDR */
  

•           .phys = 0x80000000UL, /* DDR */
  

•           .size = 0xC0000000UL,
  

•           .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  

•                    PTE_BLOCK_INNER_SHARE
  

•   }, {
  

•           /* List terminator */
  

•           0,
  

•   }
  

-};

-struct mm_region *mem_map = apq8096_mem_map; diff --git a/arch/arm/mach-snapdragon/sysmap-qcs404.c b/arch/arm/mach-snapdragon/sysmap-qcs404.c deleted file mode 100644 index 64ca4adf1bd1..000000000000 --- a/arch/arm/mach-snapdragon/sysmap-qcs404.c +++ /dev/null @@ -1,43 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*

• • Qualcomm QCS404 memory map
• • (C) Copyright 2022 Sumit Garg sumit.garg@linaro.org
• */

-#include <common.h> -#include <asm/armv8/mmu.h>

-static struct mm_region qcs404_mem_map[] = {

•   {
  

•           .virt = 0x0UL, /* Peripheral block */
  

•           .phys = 0x0UL, /* Peripheral block */
  

•           .size = 0x8000000UL,
  

•           .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  

•                    PTE_BLOCK_NON_SHARE |
  

•                    PTE_BLOCK_PXN | PTE_BLOCK_UXN
  

•   }, {
  

•           .virt = 0x80000000UL, /* DDR */
  

•           .phys = 0x80000000UL, /* DDR */
  

•           .size = 0x05900000UL,
  

•           .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  

•                    PTE_BLOCK_INNER_SHARE
  

•   }, {
  

•           .virt = 0x89600000UL, /* DDR */
  

•           .phys = 0x89600000UL, /* DDR */
  

•           .size = 0x162000000UL,
  

•           .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  

•                    PTE_BLOCK_INNER_SHARE
  

•   }, {
  

•           .virt = 0xa0000000UL, /* DDR */
  

•           .phys = 0xa0000000UL, /* DDR */
  

•           .size = 0x20000000UL,
  

•           .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  

•                    PTE_BLOCK_INNER_SHARE
  

•   }, {
  

•           /* List terminator */
  

•           0,
  

•   }
  

-};

-struct mm_region *mem_map = qcs404_mem_map; diff --git a/arch/arm/mach-snapdragon/sysmap-sdm845.c b/arch/arm/mach-snapdragon/sysmap-sdm845.c deleted file mode 100644 index 721ac411665c..000000000000 --- a/arch/arm/mach-snapdragon/sysmap-sdm845.c +++ /dev/null @@ -1,31 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/*

• • Qualcomm SDM845 memory map
• • (C) Copyright 2021 Dzmitry Sankouski dsankousk@gmail.com
• */

-#include <common.h> -#include <asm/armv8/mmu.h>

-static struct mm_region sdm845_mem_map[] = {

•   {
  

•           .virt = 0x0UL, /* Peripheral block */
  

•           .phys = 0x0UL, /* Peripheral block */
  

•           .size = 0x10000000UL,
  

•           .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |
  

•                    PTE_BLOCK_NON_SHARE |
  

•                    PTE_BLOCK_PXN | PTE_BLOCK_UXN
  

•   }, {
  

•           .virt = 0x80000000UL, /* DDR */
  

•           .phys = 0x80000000UL, /* DDR */
  

•           .size = 0x200000000UL, /* 8GiB - maximum allowed memory */
  

•           .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) |
  

•                    PTE_BLOCK_INNER_SHARE
  

•   }, {
  

•           /* List terminator */
  

•           0,
  

•   }
  

-};

-struct mm_region *mem_map = sdm845_mem_map; diff --git a/board/qualcomm/dragonboard410c/Kconfig b/board/qualcomm/dragonboard410c/Kconfig deleted file mode 100644 index 03bd7ae309cd..000000000000 --- a/board/qualcomm/dragonboard410c/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_DRAGONBOARD410C

-config SYS_BOARD

•   default "dragonboard410c"
  

-config SYS_VENDOR

•   default "qualcomm"
  

-config SYS_SOC

•   default "apq8016"
  

-config SYS_CONFIG_NAME

•   default "dragonboard410c"
  

-endif diff --git a/board/qualcomm/dragonboard410c/dragonboard410c.c b/board/qualcomm/dragonboard410c/dragonboard410c.c index 40b5448c6ef1..0136cc2237de 100644 --- a/board/qualcomm/dragonboard410c/dragonboard410c.c +++ b/board/qualcomm/dragonboard410c/dragonboard410c.c @@ -23,37 +23,6 @@

DECLARE_GLOBAL_DATA_PTR;

-#define USB_HUB_RESET_GPIO 2 -#define USB_SW_SELECT_GPIO 3

-int board_usb_init(int index, enum usb_init_type init) -{

•   struct udevice *usb;
  

•   int ret = 0;
  

•   /* USB device */
  

•   ret = device_find_global_by_ofnode(ofnode_path("/soc/usb"), &usb);
  

•   if (ret) {
  

•           printf("Cannot find USB device\n");
  

•           return ret;
  

•   }
  

•   /* Select "default" or "device" pinctrl */
  

•   switch (init) {
  

•   case USB_INIT_HOST:
  

•           pinctrl_select_state(usb, "default");
  

•           break;
  

•   case USB_INIT_DEVICE:
  

•           pinctrl_select_state(usb, "device");
  

•           break;
  

•   default:
  

•           debug("Unknown usb_init_type %d\n", init);
  

•           break;
  

•   }
  

•   return 0;
  

-}

/* UNSTUFF_BITS macro taken from Linux Kernel: drivers/mmc/core/sd.c */ #define UNSTUFF_BITS(resp, start, size) \ ({ \ @@ -119,11 +88,6 @@ int misc_init_r(void) return 0; }

-int board_init(void) -{

•   return 0;
  

-}

int board_late_init(void) { char serial[16]; @@ -166,8 +130,3 @@ int ft_board_setup(void *blob, struct bd_info *bd) "local-bd-address", mac, ARP_HLEN, 1); return 0; }

-void reset_cpu(void) -{

•   psci_system_reset();
  

-} diff --git a/board/qualcomm/dragonboard820c/Kconfig b/board/qualcomm/dragonboard820c/Kconfig deleted file mode 100644 index aff9af527128..000000000000 --- a/board/qualcomm/dragonboard820c/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_DRAGONBOARD820C

-config SYS_BOARD

•   default "dragonboard820c"
  

-config SYS_VENDOR

•   default "qualcomm"
  

-config SYS_SOC

•   default "apq8096"
  

-config SYS_CONFIG_NAME

•   default "dragonboard820c"
  

-endif diff --git a/board/qualcomm/dragonboard820c/dragonboard820c.c b/board/qualcomm/dragonboard820c/dragonboard820c.c index 2f0db628368b..ac7de711c588 100644 --- a/board/qualcomm/dragonboard820c/dragonboard820c.c +++ b/board/qualcomm/dragonboard820c/dragonboard820c.c @@ -27,24 +27,6 @@

DECLARE_GLOBAL_DATA_PTR;

-int dram_init(void) -{

•   gd->ram_size = PHYS_SDRAM_SIZE;
  

•   return 0;
  

-}

-int dram_init_banksize(void) -{

•   gd->bd->bi_dram[0].start = PHYS_SDRAM_1;
  

•   gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE;
  

•   gd->bd->bi_dram[1].start = PHYS_SDRAM_2;
  

•   gd->bd->bi_dram[1].size  = PHYS_SDRAM_2_SIZE;
  

•   return 0;
  

-}

static void sdhci_power_init(void) { const u32 TLMM_PULL_MASK = 0x3; @@ -113,28 +95,9 @@ static void sdhci_power_init(void) rclk[i].val << rclk[i].bit); }

-static void show_psci_version(void) -{

•   struct arm_smccc_res res;
  

•   arm_smccc_smc(ARM_PSCI_0_2_FN_PSCI_VERSION, 0, 0, 0, 0, 0, 0, 0, &res);
  

•   printf("PSCI:  v%ld.%ld\n",
  

•          PSCI_VERSION_MAJOR(res.a0),
  

•           PSCI_VERSION_MINOR(res.a0));
  

-}

-int board_init(void) +void qcom_board_init(void) { sdhci_power_init();

•   show_psci_version();
  

•   return 0;
  

-}

-void reset_cpu(void) -{

•   psci_system_reset();
  

}

/* Check for vol- button - if pressed - stop autoboot */ diff --git a/board/qualcomm/dragonboard845c/Kconfig b/board/qualcomm/dragonboard845c/Kconfig deleted file mode 100644 index 52fdff288d59..000000000000 --- a/board/qualcomm/dragonboard845c/Kconfig +++ /dev/null @@ -1,12 +0,0 @@ -if TARGET_DRAGONBOARD845C

-config SYS_BOARD

•   default "dragonboard845c"
  

-config SYS_CONFIG_NAME

•   default "dragonboard845c"
  

-config SYS_VENDOR

•   default "qualcomm"
  

-endif diff --git a/board/qualcomm/qcs404-evb/Kconfig b/board/qualcomm/qcs404-evb/Kconfig deleted file mode 100644 index 32657c7d5e31..000000000000 --- a/board/qualcomm/qcs404-evb/Kconfig +++ /dev/null @@ -1,15 +0,0 @@ -if TARGET_QCS404EVB

-config SYS_BOARD

•   default "qcs404-evb"
  

-config SYS_VENDOR

•   default "qualcomm"
  

-config SYS_SOC

•   default "qcs404"
  

-config SYS_CONFIG_NAME

•   default "qcs404-evb"
  

-endif diff --git a/board/qualcomm/qcs404-evb/qcs404-evb.c b/board/qualcomm/qcs404-evb/qcs404-evb.c index 249dca7e72f1..1a4b1f97a3ae 100644 --- a/board/qualcomm/qcs404-evb/qcs404-evb.c +++ b/board/qualcomm/qcs404-evb/qcs404-evb.c @@ -14,16 +14,10 @@ #include <asm/gpio.h> #include <asm/global_data.h> #include <fdt_support.h> -#include <asm/arch/dram.h>

DECLARE_GLOBAL_DATA_PTR;

-int dram_init(void) -{

•   return fdtdec_setup_mem_size_base();
  

-}

-int board_init(void) +void qcom_board_init(void) { struct udevice *pmic_gpio; struct gpio_desc usb_vbus_boost_pin; @@ -34,29 +28,22 @@ int board_init(void) &pmic_gpio); if (ret < 0) { printf("Failed to find pms405_gpios@c000 node.\n");

•           return ret;
  

•           return;
    }
  
    node = fdt_subnode_offset(gd->fdt_blob, dev_of_offset(pmic_gpio),
                              "usb_vbus_boost_pin");
    if (node < 0) {
            printf("Failed to find usb_hub_reset_pm dt node.\n");
  

•           return node;
  

•           return;
    }
    ret = gpio_request_by_name_nodev(offset_to_ofnode(node), "gpios", 0,
                                     &usb_vbus_boost_pin, 0);
    if (ret < 0) {
            printf("Failed to request usb_hub_reset_pm gpio.\n");
  

•           return ret;
  

•           return;
    }
  
    dm_gpio_set_dir_flags(&usb_vbus_boost_pin,
                          GPIOD_IS_OUT | GPIOD_IS_OUT_ACTIVE);
  

•   return 0;
  

-}

-void reset_cpu(void) -{

•   psci_system_reset();
  

} diff --git a/configs/dragonboard410c_defconfig b/configs/dragonboard410c_defconfig index 56a73893d3df..efdee8a40fa3 100644 --- a/configs/dragonboard410c_defconfig +++ b/configs/dragonboard410c_defconfig @@ -1,9 +1,10 @@ CONFIG_ARM=y +CONFIG_SYS_BOARD="dragonboard410c" CONFIG_COUNTER_FREQUENCY=19000000 +CONFIG_ENABLE_ARM_SOC_BOOT0_HOOK=y CONFIG_ARCH_SNAPDRAGON=y CONFIG_TEXT_BASE=0x8f600000 CONFIG_SYS_MALLOC_LEN=0x802000 -CONFIG_NR_DRAM_BANKS=1 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0 CONFIG_ENV_SIZE=0x2000 @@ -38,7 +39,9 @@ CONFIG_CMD_TIMER=y CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_BUTTON_QCOM_PMIC=y CONFIG_CLK=y +CONFIG_CLK_QCOM_APQ8016=y CONFIG_USB_FUNCTION_FASTBOOT=y CONFIG_FASTBOOT_BUF_ADDR=0x91000000 CONFIG_FASTBOOT_FLASH=y @@ -52,6 +55,7 @@ CONFIG_MMC_SDHCI_MSM=y CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_PINCONF=y +CONFIG_PINCTRL_QCOM_APQ8016=y CONFIG_DM_PMIC=y CONFIG_PMIC_QCOM=y CONFIG_MSM_SERIAL=y diff --git a/configs/dragonboard820c_defconfig b/configs/dragonboard820c_defconfig index 7304ff97dd8e..89847ce0b307 100644 --- a/configs/dragonboard820c_defconfig +++ b/configs/dragonboard820c_defconfig @@ -1,14 +1,13 @@ CONFIG_ARM=y +CONFIG_SYS_BOARD="dragonboard820c" CONFIG_COUNTER_FREQUENCY=19000000 CONFIG_ARCH_SNAPDRAGON=y CONFIG_TEXT_BASE=0x80080000 CONFIG_SYS_MALLOC_LEN=0x804000 -CONFIG_NR_DRAM_BANKS=2 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007fff0 CONFIG_ENV_SIZE=0x4000 CONFIG_DEFAULT_DEVICE_TREE="dragonboard820c" -CONFIG_TARGET_DRAGONBOARD820C=y CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 820C" CONFIG_SYS_LOAD_ADDR=0x80080000 CONFIG_DISTRO_DEFAULTS=y @@ -35,12 +34,15 @@ CONFIG_ENV_IS_IN_EXT4=y CONFIG_ENV_EXT4_INTERFACE="mmc" CONFIG_ENV_EXT4_DEVICE_AND_PART="0:1" CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_BUTTON_QCOM_PMIC=y CONFIG_CLK=y +CONFIG_CLK_QCOM_APQ8096=y CONFIG_QCOM_PMIC_GPIO=y CONFIG_MMC_SDHCI=y CONFIG_MMC_SDHCI_MSM=y CONFIG_PINCTRL=y CONFIG_PINCONF=y +CONFIG_PINCTRL_QCOM_APQ8096=y CONFIG_DM_PMIC=y CONFIG_PMIC_QCOM=y CONFIG_MSM_SERIAL=y diff --git a/configs/dragonboard845c_defconfig b/configs/dragonboard845c_defconfig deleted file mode 100644 index f29f11e342e7..000000000000 --- a/configs/dragonboard845c_defconfig +++ /dev/null @@ -1,29 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_COUNTER_FREQUENCY=19000000 -CONFIG_POSITION_INDEPENDENT=y -CONFIG_ARCH_SNAPDRAGON=y -CONFIG_DEFAULT_DEVICE_TREE="dragonboard845c" -CONFIG_TARGET_DRAGONBOARD845C=y -CONFIG_IDENT_STRING="\nQualcomm-DragonBoard 845C" -CONFIG_SYS_LOAD_ADDR=0x80000000 -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_BOOTDELAY=5 -CONFIG_SAVE_PREV_BL_FDT_ADDR=y -CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y -CONFIG_SYS_CBSIZE=512 -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=64 -CONFIG_CMD_GPIO=y -# CONFIG_NET is not set -CONFIG_CLK=y -CONFIG_MSM_GPIO=y -CONFIG_QCOM_PMIC_GPIO=y -CONFIG_PINCTRL=y -CONFIG_DM_PMIC=y -CONFIG_PMIC_QCOM=y -CONFIG_MSM_GENI_SERIAL=y -CONFIG_SPMI_MSM=y -CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/qcom_defconfig b/configs/qcom_defconfig new file mode 100644 index 000000000000..a84f5aee444e --- /dev/null +++ b/configs/qcom_defconfig @@ -0,0 +1,67 @@ +CONFIG_ARM=y +CONFIG_SKIP_LOWLEVEL_INIT=y +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_SNAPDRAGON=y +CONFIG_DEFAULT_DEVICE_TREE="dragonboard845c" +CONFIG_SYS_LOAD_ADDR=0x0 +CONFIG_BUTTON_CMD=y +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_BOOTSTD_FULL=y +# CONFIG_BOOTMETH_VBE is not set +CONFIG_BOOTDELAY=1 +CONFIG_USE_PREBOOT=y +CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y +CONFIG_SYS_CBSIZE=512 +CONFIG_LOG_MAX_LEVEL=9 +CONFIG_LOG_DEFAULT_LEVEL=4 +# CONFIG_DISPLAY_CPUINFO is not set +CONFIG_DISPLAY_BOARDINFO_LATE=y +CONFIG_CMD_BOOTMENU=y +CONFIG_CMD_CLK=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_MMC=y +CONFIG_CMD_UFS=y +CONFIG_CMD_USB=y +CONFIG_CMD_CAT=y +CONFIG_CMD_BMP=y +CONFIG_CMD_LOG=y +# CONFIG_NET is not set +CONFIG_BUTTON_QCOM_PMIC=y +CONFIG_CLK=y +CONFIG_CLK_QCOM_QCS404=y +CONFIG_CLK_QCOM_SDM845=y +CONFIG_MSM_GPIO=y +CONFIG_QCOM_PMIC_GPIO=y +CONFIG_DM_KEYBOARD=y +CONFIG_BUTTON_KEYBOARD=y +CONFIG_MMC_HS200_SUPPORT=y +CONFIG_MMC_SDHCI=y +CONFIG_MMC_SDHCI_ADMA=y +CONFIG_MMC_SDHCI_MSM=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_QCOM_QCS404=y +CONFIG_PINCTRL_QCOM_SDM845=y +CONFIG_DM_PMIC=y +CONFIG_PMIC_QCOM=y +CONFIG_SCSI=y +CONFIG_MSM_SERIAL=y +CONFIG_MSM_GENI_SERIAL=y +CONFIG_SPMI_MSM=y +CONFIG_SYSINFO=y +CONFIG_SYSINFO_SMBIOS=y +CONFIG_USB=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_DWC3=y +CONFIG_USB_DWC3=y +CONFIG_UFS=y +CONFIG_VIDEO=y +# CONFIG_VIDEO_FONT_8X16 is not set +CONFIG_VIDEO_FONT_16X32=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_NO_FB_CLEAR=y +CONFIG_VIDEO_SIMPLE=y +CONFIG_HEXDUMP=y +# CONFIG_GENERATE_SMBIOS_TABLE is not set +CONFIG_LMB_MAX_REGIONS=64 diff --git a/configs/qcs404evb_defconfig b/configs/qcs404evb_defconfig index 700c024e8b6a..d85d193895b0 100644 --- a/configs/qcs404evb_defconfig +++ b/configs/qcs404evb_defconfig @@ -1,11 +1,10 @@ CONFIG_ARM=y +CONFIG_SYS_BOARD="qcs404-evb" CONFIG_SKIP_LOWLEVEL_INIT=y CONFIG_COUNTER_FREQUENCY=19000000 CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_SNAPDRAGON=y CONFIG_DEFAULT_DEVICE_TREE="qcs404-evb" -CONFIG_DM_RESET=y -CONFIG_TARGET_QCS404EVB=y CONFIG_IDENT_STRING="\nQualcomm QCS404-EVB" CONFIG_SYS_LOAD_ADDR=0x80000000 CONFIG_FIT=y @@ -31,6 +30,7 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y # CONFIG_NET is not set CONFIG_CLK=y +CONFIG_CLK_QCOM_QCS404=y CONFIG_MSM_GPIO=y CONFIG_QCOM_PMIC_GPIO=y CONFIG_MISC=y @@ -42,6 +42,7 @@ CONFIG_PHY=y CONFIG_PHY_QCOM_USB_HS_28NM=y CONFIG_PHY_QCOM_USB_SS=y CONFIG_PINCTRL=y +CONFIG_PINCTRL_QCOM_QCS404=y CONFIG_DM_PMIC=y CONFIG_PMIC_QCOM=y CONFIG_MSM_SERIAL=y diff --git a/configs/starqltechn_defconfig b/configs/starqltechn_defconfig deleted file mode 100644 index 6980a8232667..000000000000 --- a/configs/starqltechn_defconfig +++ /dev/null @@ -1,41 +0,0 @@ -CONFIG_ARM=y -CONFIG_SKIP_LOWLEVEL_INIT=y -CONFIG_COUNTER_FREQUENCY=19000000 -CONFIG_POSITION_INDEPENDENT=y -CONFIG_ARCH_SNAPDRAGON=y -CONFIG_DEFAULT_DEVICE_TREE="starqltechn" -CONFIG_TARGET_STARQLTECHN=y -CONFIG_IDENT_STRING="\nSamsung S9 SM-G9600" -CONFIG_SYS_LOAD_ADDR=0x80000000 -CONFIG_FIT=y -CONFIG_FIT_VERBOSE=y -CONFIG_BOOTDELAY=0 -CONFIG_SAVE_PREV_BL_FDT_ADDR=y -CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR=y -CONFIG_SYS_CBSIZE=512 -CONFIG_SYS_PBSIZE=532 -# CONFIG_DISPLAY_CPUINFO is not set -CONFIG_HUSH_PARSER=y -CONFIG_SYS_MAXARGS=64 -CONFIG_CMD_BOOTMENU=y -CONFIG_CMD_GPIO=y -CONFIG_CMD_BMP=y -# CONFIG_NET is not set -CONFIG_BUTTON=y -CONFIG_CLK=y -CONFIG_MSM_GPIO=y -CONFIG_QCOM_PMIC_GPIO=y -CONFIG_DM_KEYBOARD=y -CONFIG_BUTTON_KEYBOARD=y -CONFIG_PINCTRL=y -CONFIG_DM_PMIC=y -CONFIG_PMIC_QCOM=y -CONFIG_MSM_GENI_SERIAL=y -CONFIG_SPMI_MSM=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_FONT_8X16 is not set -CONFIG_VIDEO_FONT_16X32=y -CONFIG_SYS_WHITE_ON_BLACK=y -CONFIG_VIDEO_SIMPLE=y -CONFIG_VIDEO_DT_SIMPLEFB=y -CONFIG_LMB_MAX_REGIONS=64 diff --git a/include/configs/dragonboard845c.h b/include/configs/dragonboard845c.h deleted file mode 100644 index 14a8a2ca049e..000000000000 --- a/include/configs/dragonboard845c.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*

• • Configuration file for Dragonboard 845c, based on Qualcomm SDA845 chip
• • (C) Copyright 2022 Sumit Garg sumit.garg@linaro.org
• */

-#ifndef __CONFIGS_SDM845_H -#define __CONFIGS_SDM845_H

-#include <linux/sizes.h>

-#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }

-#define CFG_EXTRA_ENV_SETTINGS \

•   "bootm_size=0x5000000\0"        \
  

•   "bootm_low=0x80000000\0"        \
  

•   "bootcmd=bootm $prevbl_initrd_start_addr\0"
  

-#endif diff --git a/include/configs/qcom.h b/include/configs/qcom.h new file mode 100644 index 000000000000..e50b3bce5cdd --- /dev/null +++ b/include/configs/qcom.h @@ -0,0 +1,21 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*

• • Configuration file for Qualcomm Snapdragon boards
• • (C) Copyright 2021 Dzmitry Sankouski dsankouski@gmail.com
• • (C) Copyright 2023 Linaro Ltd.
• */

+#ifndef __CONFIGS_SNAPDRAGON_H +#define __CONFIGS_SNAPDRAGON_H

+#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }

+/* Load addressed are calculated during board_late_init(). See arm/mach-snapdragon/board.c */ +#define CFG_EXTRA_ENV_SETTINGS \

•   "stdin=serial,button-kbd\0"     \
  

•   "stdout=serial,vidconsole\0"    \
  

•   "stderr=serial,vidconsole\0" \
  

•   "bootcmd=bootm $prevbl_initrd_start_addr\0"
  

+#endif diff --git a/include/configs/qcs404-evb.h b/include/configs/qcs404-evb.h deleted file mode 100644 index 9501d43665e9..000000000000 --- a/include/configs/qcs404-evb.h +++ /dev/null @@ -1,20 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*

• • Configuration file for QCS404 evaluation board
• • (C) Copyright 2022 Sumit Garg sumit.garg@linaro.org
• */

-#ifndef __CONFIGS_QCS404EVB_H -#define __CONFIGS_QCS404EVB_H

-#include <linux/sizes.h>

-#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }

-#define CFG_EXTRA_ENV_SETTINGS \

•   "bootm_size=0x5000000\0"        \
  

•   "bootm_low=0x80000000\0"        \
  

•   "bootcmd=bootm $prevbl_initrd_start_addr\0"
  

-#endif diff --git a/include/configs/sdm845.h b/include/configs/sdm845.h deleted file mode 100644 index 5ad8569b2152..000000000000 --- a/include/configs/sdm845.h +++ /dev/null @@ -1,26 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/*

• • Configuration file for boards, based on Qualcomm SDM845 chip
• • (C) Copyright 2021 Dzmitry Sankouski dsankouski@gmail.com
• */

-#ifndef __CONFIGS_SDM845_H -#define __CONFIGS_SDM845_H

-#include <linux/sizes.h>

-#define CFG_SYS_BAUDRATE_TABLE { 115200, 230400, 460800, 921600 }

-#define CFG_EXTRA_ENV_SETTINGS \

•   "bootm_size=0x4000000\0"        \
  

•   "bootm_low=0x80000000\0"        \
  

•   "stdin=serial,button-kbd\0"     \
  

•   "stdout=serial,vidconsole\0"    \
  

•   "stderr=serial,vidconsole\0"    \
  

•   "preboot=source $prevbl_initrd_start_addr:prebootscript\0" \
  

•   "bootcmd=source $prevbl_initrd_start_addr:bootscript\0"
  

-/* Size of malloc() pool */

-#endif

-- 2.43.1