[PATCH 1/2] ARM: cache: Allow SPL to build cache-pl310.c
Before this commit, the SPL could enable the PL310 L2 cache [1], but the cache maintenance functions from cache-pl310.c were only useable for non-SPL builds.
After enabling the cache one must be able to flush it, too. Thus this commit allows cache-pl310.c to be included in the SPL build.
[1] See for example arch/arm/mach-imx/cache.c: v7_outer_cache_enable()
Signed-off-by: Philip Oberfichtner pro@denx.de ---
arch/arm/lib/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index c603fe61bc..ac1d4245bb 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -33,7 +33,6 @@ obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTZ) += bootm.o zimage.o -obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o else obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o @@ -46,6 +45,7 @@ else obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o endif +obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o obj-$(CONFIG_$(SPL_TPL_)SEMIHOSTING) += semihosting.o
ifneq ($(filter y,$(CONFIG_SAVE_PREV_BL_INITRAMFS_START_ADDR) $(CONFIG_SAVE_PREV_BL_FDT_ADDR)),)
From: Marek Vasut marex@denx.de
Enable d-cache early in SPL right after DRAM is started up. This reduces U-Boot proper load time by 650ms when loaded from SPI NOR.
Signed-off-by: Marek Vasut marex@denx.de Signed-off-by: Philip Oberfichtner pro@denx.de
---
board/dhelectronics/dh_imx6/dh_imx6_spl.c | 27 +++++++++++++++++++++++ 1 file changed, 27 insertions(+)
diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index e49e97724a..2c0ddc527a 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -6,6 +6,7 @@ */
#include <common.h> +#include <cpu_func.h> #include <init.h> #include <asm/arch/clock.h> #include <asm/arch/crm_regs.h> @@ -14,11 +15,13 @@ #include <asm/arch/mx6-ddr.h> #include <asm/arch/mx6-pins.h> #include <asm/arch/sys_proto.h> +#include <asm/cache.h> #include <asm/gpio.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/mxc_i2c.h> #include <asm/io.h> +#include <asm/system.h> #include <errno.h> #include <fuse.h> #include <fsl_esdhc_imx.h> @@ -610,6 +613,20 @@ static void dhcom_spl_dram_init(void) } }
+void dram_bank_mmu_setup(int bank) +{ + int i; + + set_section_dcache(ROMCP_ARB_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION); + set_section_dcache(IRAM_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION); + + for (i = MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT; + i < ((MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT) + + (SZ_1G >> MMU_SECTION_SHIFT)); + i++) + set_section_dcache(i, DCACHE_DEFAULT_OPTION); +} + void board_init_f(ulong dummy) { /* setup AIPS and disable watchdog */ @@ -636,9 +653,19 @@ void board_init_f(ulong dummy) /* DDR3 initialization */ dhcom_spl_dram_init();
+ /* Set up early MMU tables at the beginning of DRAM and start d-cache */ + gd->arch.tlb_addr = MMDC0_ARB_BASE_ADDR + SZ_32M; + gd->arch.tlb_size = PGTABLE_SIZE; + enable_caches(); + /* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */ board_init_r(NULL, 0); } + +void spl_board_prepare_for_boot(void) +{ + dcache_disable(); +}
On 8/4/22 10:15, Philip Oberfichtner wrote:
From: Marek Vasut marex@denx.de
Enable d-cache early in SPL right after DRAM is started up. This reduces U-Boot proper load time by 650ms when loaded from SPI NOR.
Signed-off-by: Marek Vasut marex@denx.de Signed-off-by: Philip Oberfichtner pro@denx.de
board/dhelectronics/dh_imx6/dh_imx6_spl.c | 27 +++++++++++++++++++++++ 1 file changed, 27 insertions(+)
diff --git a/board/dhelectronics/dh_imx6/dh_imx6_spl.c b/board/dhelectronics/dh_imx6/dh_imx6_spl.c index e49e97724a..2c0ddc527a 100644 --- a/board/dhelectronics/dh_imx6/dh_imx6_spl.c +++ b/board/dhelectronics/dh_imx6/dh_imx6_spl.c @@ -6,6 +6,7 @@ */
#include <common.h> +#include <cpu_func.h> #include <init.h> #include <asm/arch/clock.h> #include <asm/arch/crm_regs.h> @@ -14,11 +15,13 @@ #include <asm/arch/mx6-ddr.h> #include <asm/arch/mx6-pins.h> #include <asm/arch/sys_proto.h> +#include <asm/cache.h> #include <asm/gpio.h> #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/mxc_i2c.h> #include <asm/io.h> +#include <asm/system.h> #include <errno.h> #include <fuse.h> #include <fsl_esdhc_imx.h> @@ -610,6 +613,20 @@ static void dhcom_spl_dram_init(void) } }
+void dram_bank_mmu_setup(int bank) +{
- int i;
- set_section_dcache(ROMCP_ARB_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION);
- set_section_dcache(IRAM_BASE_ADDR >> MMU_SECTION_SHIFT, DCACHE_DEFAULT_OPTION);
- for (i = MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT;
i < ((MMDC0_ARB_BASE_ADDR >> MMU_SECTION_SHIFT) +(SZ_1G >> MMU_SECTION_SHIFT));i++)set_section_dcache(i, DCACHE_DEFAULT_OPTION);+}
- void board_init_f(ulong dummy) { /* setup AIPS and disable watchdog */
@@ -636,9 +653,19 @@ void board_init_f(ulong dummy) /* DDR3 initialization */ dhcom_spl_dram_init();
/* Set up early MMU tables at the beginning of DRAM and start d-cache */
gd->arch.tlb_addr = MMDC0_ARB_BASE_ADDR + SZ_32M;
gd->arch.tlb_size = PGTABLE_SIZE;
enable_caches();
/* Clear the BSS. */ memset(__bss_start, 0, __bss_end - __bss_start);
/* load/boot image from boot device */ board_init_r(NULL, 0); }
+void spl_board_prepare_for_boot(void) +{
An explanation why this is needed in a comment would be good to have.
- dcache_disable();
+}
On 8/4/22 10:15, Philip Oberfichtner wrote:
Before this commit, the SPL could enable the PL310 L2 cache [1], but the cache maintenance functions from cache-pl310.c were only useable for non-SPL builds.
After enabling the cache one must be able to flush it, too. Thus this commit allows cache-pl310.c to be included in the SPL build.
[1] See for example arch/arm/mach-imx/cache.c: v7_outer_cache_enable()
Signed-off-by: Philip Oberfichtner pro@denx.de
arch/arm/lib/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index c603fe61bc..ac1d4245bb 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -33,7 +33,6 @@ obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTZ) += bootm.o zimage.o -obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o else obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o @@ -46,6 +45,7 @@ else obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o endif +obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
Doesn't this need SPL/TPL Kconfig symbols and
obj-$(CONFIG_$(SPL_TPL_)SYS_L2_PL310) += cache-pl310.o
?
On Thu, 2022-08-04 at 11:02 +0200, Marek Vasut wrote:
On 8/4/22 10:15, Philip Oberfichtner wrote:
Before this commit, the SPL could enable the PL310 L2 cache [1], but the cache maintenance functions from cache-pl310.c were only useable for non-SPL builds.
After enabling the cache one must be able to flush it, too. Thus this commit allows cache-pl310.c to be included in the SPL build.
[1] See for example arch/arm/mach-imx/cache.c: v7_outer_cache_enable()
Signed-off-by: Philip Oberfichtner pro@denx.de
arch/arm/lib/Makefile | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/lib/Makefile b/arch/arm/lib/Makefile index c603fe61bc..ac1d4245bb 100644 --- a/arch/arm/lib/Makefile +++ b/arch/arm/lib/Makefile @@ -33,7 +33,6 @@ obj-$(CONFIG_OF_LIBFDT) += bootm-fdt.o obj-$(CONFIG_CMD_BOOTI) += bootm.o image.o obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-$(CONFIG_CMD_BOOTZ) += bootm.o zimage.o -obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o else obj-$(CONFIG_$(SPL_TPL_)FRAMEWORK) += spl.o obj-$(CONFIG_SPL_FRAMEWORK) += zimage.o @@ -46,6 +45,7 @@ else obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o endif +obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
Doesn't this need SPL/TPL Kconfig symbols and
obj-$(CONFIG_$(SPL_TPL_)SYS_L2_PL310) += cache-pl310.o
?
CONFIG_SYS_L2_PL310 is not converted to Kconfig yet. And there is no CONFIG_SPL_ usage for it so far. So I'd say no. Please correct me if I'm wrong.
On 8/4/22 11:19, Philip Oberfichtner wrote:
[...]
@@ -46,6 +45,7 @@ else obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMSET) += memset.o obj-$(CONFIG_$(SPL_TPL_)USE_ARCH_MEMCPY) += memcpy.o endif +obj-$(CONFIG_SYS_L2_PL310) += cache-pl310.o
Doesn't this need SPL/TPL Kconfig symbols and
obj-$(CONFIG_$(SPL_TPL_)SYS_L2_PL310) += cache-pl310.o
?
CONFIG_SYS_L2_PL310 is not converted to Kconfig yet. And there is no CONFIG_SPL_ usage for it so far. So I'd say no. Please correct me if I'm wrong.
I'm concerned whether applying this patch won't enable L2CC in SPL for boards where this could break things.
There is a script to do the conversion to Kconfig easily, see doc/develop/moveconfig.rst . It might make sense to run it first, convert this symbol to Kconfig, and then add this patch second, and then enable SPL_...PL310 for this board only.
participants (2)
-
Marek Vasut -
Philip Oberfichtner