Understand.

Thanks.

Best regards, Haijun

于 2014/1/9 18:43, Pantelis Antoniou 写道:

Hi Haijun,

On Dec 11, 2013, at 7:35 AM, Haijun Zhang wrote:

...

The upper 4 data signals of esdhc are shared with spi flash. So detect if the upper 4 pins are assigned to esdhc before enable sdhc 8 bit width.

Signed-off-by: Haijun Zhang haijun.zhang@freescale.com

changs for V2:

• No changes

drivers/mmc/fsl_esdhc.c | 5 +++++ include/configs/T4240QDS.h | 1 + 2 files changed, 6 insertions(+)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index b3b5f37..a5fee3c 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -646,6 +646,11 @@ int fsl_esdhc_initialize(bd_t *bis, struct fsl_esdhc_cfg *cfg) mmc->host_caps &= ~MMC_MODE_4BIT; }

• /* Detect if the upper 4 pins are used for ESDHC */

+#if defined(CONFIG_T4240QDS)

• if (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC_WIDTH8))

• mmc->host_caps &= ~MMC_MODE_8BIT;
  

+#endif

Same comment applies as for the card detect quirk,

#define CONFIG_ESDHC_DETECT_8_BIT_QUIRK etc.

...

if (caps & ESDHC_HOSTCAPBLT_HSS) mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS;

diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index 955e6b9..4799d38 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -167,6 +167,7 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 #define QIXIS_BRDCFG5 0x55 #define QIXIS_MUX_SDHC 2 +#define QIXIS_MUX_SDHC_WIDTH8 1 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)

#define CONFIG_SYS_CSPR3_EXT (0xf)

1.8.4.1

Regards

-- Pantelis

Hi Haijun,

On Dec 11, 2013, at 7:35 AM, Haijun Zhang wrote:

On BSC9131 and BSC9132: For High Capacity SD Cards (> 2 GBytes), the 32-bit source address specifies the memory address in block address format. Block length is fixed to 512 bytes as per the SD High Capacity specification. So we need to convert the block address format to byte address format to calculate the envaddr.

If there is no enough space for environment variables or envaddr is larger than 4GiB, we relocate the envaddr to 0x400. The address relocated is in the front of the first partition that is assigned for sdboot only.

Signed-off-by: Haijun Zhang haijun.zhang@freescale.com

changes for V2:

• Use 0xffffffffu instead of UINT_MAX

board/freescale/common/sdhc_boot.c | 30 ++++++++++++++++++++++++++++++ 1 file changed, 30 insertions(+)

diff --git a/board/freescale/common/sdhc_boot.c b/board/freescale/common/sdhc_boot.c index f6e2b2b..b5ae489 100644 --- a/board/freescale/common/sdhc_boot.c +++ b/board/freescale/common/sdhc_boot.c @@ -16,6 +16,8 @@ #define ESDHC_BOOT_IMAGE_SIZE 0x48 #define ESDHC_BOOT_IMAGE_ADDR 0x50

+#define ESDHC_DEFAULT_ENVADDR 0x400

int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) { u8 *tmp_buf; @@ -39,6 +41,34 @@ int mmc_get_env_addr(struct mmc *mmc, int copy, u32 *env_addr) /* Get the code size from offset 0x48 */ code_len = *(u32 *)(tmp_buf + ESDHC_BOOT_IMAGE_SIZE);

• /*

• * On soc BSC9131, BSC9132:
  

• * In High Capacity SD Cards (> 2 GBytes), the 32-bit source address and
  

• * code length of these soc specify the memory address in block address
  

• * format. Block length is fixed to 512 bytes as per the SD High
  

• * Capacity specification.
  

• */
  

• if ((SVR_SOC_VER(get_svr()) == SVR_9131) ||

• 	(SVR_SOC_VER(get_svr()) == SVR_9132)) {
  

• u64 tmp;
  

• if (mmc->high_capacity) {
  

• 	tmp = (u64)code_offset * blklen;
  

• 	tmp += code_len * blklen;
  

• } else
  

• 	tmp = code_offset + code_len;
  

• if ((tmp + CONFIG_ENV_SIZE > mmc->capacity) ||
  

• 		(tmp > 0xFFFFFFFFU))
  

• 	*env_addr = ESDHC_DEFAULT_ENVADDR;
  

• else
  

• 	*env_addr = tmp;
  

• free(tmp_buf);
  

• return 0;
  

• }

Yet another board quirk.

#define CONFIG_ESDHC_ENVADDR_QUIRK please, and put this block of code in a board/soc specific file.

*env_addr = code_offset + code_len;

free(tmp_buf);

1.8.4.1

Regards

-- Pantelis

Thanks Pantelis.

I'll rework this patch as you suggested.

Thanks.

Regards,

Haijun

于 2014/1/9 18:42, Pantelis Antoniou 写道:

Hi Haijun,

On Dec 11, 2013, at 7:35 AM, Haijun Zhang wrote:

...

Card detection pin is ineffective on T4240QDS Rev1.0. There are two cards can be connected to board.

1. eMMC card is built-in board, can not be removed. so For eMMC card it is always there.
2. Card detecting pin is functional for SDHC card in Rev2.0.

This workaround force sdhc driver scan and initialize the card regardless of whether the card is inserted or not in case Rev1.0.

Signed-off-by: Haijun Zhang Haijun.Zhang@freescale.com

changes for V2:

• Add the judgement condition for this broken card

drivers/mmc/fsl_esdhc.c | 9 +++++++++ include/configs/T4240QDS.h | 2 ++ 2 files changed, 11 insertions(+)

diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index 134a02d..b3b5f37 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -548,6 +548,15 @@ static int esdhc_getcd(struct mmc *mmc) struct fsl_esdhc *regs = (struct fsl_esdhc *)cfg->esdhc_base; int timeout = 1000;

• /*

• * Card detecting pin is not functional on T4240QDS with rev 1.0 SoC.
  

• * Presuming card is present.
  

• */
  

+#if defined(CONFIG_T4240QDS)

• if (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) ||

• 	IS_SVR_REV(get_svr(), 1, 0))
  

• return 1;
  

+#endif

I just don't like this. It's a bunch of completely board specific code dropped in the middle of a generic driver.

Rework to something like this:

In the board file (T4240QDS)

#define CONFIG_ESDHC_DETECT_QUIRK \ (!(readb(QIXIS_BASE + QIXIS_BRDCFG5) & QIXIS_MUX_SDHC) || \ IS_SVR_REV(get_svr(), 1, 0)))

And do this in the driver:

#ifdef CONFIG_ESDHC_DETECT_QUIRK if (CONFIG_ESDHC_DETECT_QUIRK) return 1; #endif

Do the same to all other quirks please.

...

while (!(esdhc_read32(&regs->prsstat) & PRSSTAT_CINS) && --timeout) udelay(1000);

diff --git a/include/configs/T4240QDS.h b/include/configs/T4240QDS.h index c96df54..955e6b9 100644 --- a/include/configs/T4240QDS.h +++ b/include/configs/T4240QDS.h @@ -165,6 +165,8 @@ unsigned long get_board_ddr_clk(void); #define QIXIS_RCFG_CTL_RECONFIG_IDLE 0x20 #define QIXIS_RCFG_CTL_RECONFIG_START 0x21 #define QIXIS_RCFG_CTL_WATCHDOG_ENBLE 0x08 +#define QIXIS_BRDCFG5 0x55 +#define QIXIS_MUX_SDHC 2 #define QIXIS_BASE_PHYS (0xf00000000ull | QIXIS_BASE)

#define CONFIG_SYS_CSPR3_EXT (0xf)

1.8.4.1

Regards

-- Pantelis