[PATCH 1/1] add support for mws4 board
mws4 is an arm based nuclear probe hardware used from german government to monitor nuclear activity
Signed-off-by: Marian Ulbricht ulbricht@innoroute.de --- arch/arm/dts/Makefile | 3 + arch/arm/dts/omap3-mws4-u-boot.dtsi | 14 ++ arch/arm/dts/omap3-mws4.dts | 137 ++++++++++++++ arch/arm/mach-omap2/omap3/Kconfig | 10 + board/ultratronik/mws4/Kconfig | 12 ++ board/ultratronik/mws4/MAINTAINERS | 6 + board/ultratronik/mws4/Makefile | 6 + board/ultratronik/mws4/default.env | 11 ++ board/ultratronik/mws4/mws4.c | 283 ++++++++++++++++++++++++++++ board/ultratronik/mws4/mws4.h | 203 ++++++++++++++++++++ configs/omap3_mws4_defconfig | 74 ++++++++ include/configs/omap3_mws4.h | 103 ++++++++++ 12 files changed, 862 insertions(+) create mode 100644 arch/arm/dts/omap3-mws4-u-boot.dtsi create mode 100644 arch/arm/dts/omap3-mws4.dts create mode 100644 board/ultratronik/mws4/Kconfig create mode 100644 board/ultratronik/mws4/MAINTAINERS create mode 100644 board/ultratronik/mws4/Makefile create mode 100644 board/ultratronik/mws4/default.env create mode 100644 board/ultratronik/mws4/mws4.c create mode 100644 board/ultratronik/mws4/mws4.h create mode 100644 configs/omap3_mws4_defconfig create mode 100644 include/configs/omap3_mws4.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 83630af4f6..7b68a49990 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1047,6 +1047,9 @@ dtb-$(CONFIG_TARGET_OMAP3_BEAGLE) += \ omap3-beagle-xm.dtb \ omap3-beagle.dtb
+dtb-$(CONFIG_TARGET_OMAP3_MWS4) += \ + omap3-mws4.dtb + dtb-$(CONFIG_TARGET_OMAP3_IGEP00X0) += \ omap3-igep0020.dtb
diff --git a/arch/arm/dts/omap3-mws4-u-boot.dtsi b/arch/arm/dts/omap3-mws4-u-boot.dtsi new file mode 100644 index 0000000000..2c03701c89 --- /dev/null +++ b/arch/arm/dts/omap3-mws4-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * (C) Copyright 2017 Derald D. Woods woods.technical@gmail.com + */ + +#include "omap3-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart3; + }; +}; diff --git a/arch/arm/dts/omap3-mws4.dts b/arch/arm/dts/omap3-mws4.dts new file mode 100644 index 0000000000..f8a5c3d5b8 --- /dev/null +++ b/arch/arm/dts/omap3-mws4.dts @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * Modified 2015 by Bernhard Gätzschmann, Ultratronik from Beagleboard xM + * + * Modified 2022 Marian Ulbricht ulbricht@innoroute.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "omap34xx.dtsi" + +/ { + model = "Ultratronik BFS MWS4"; + compatible = "ti,omap3-mmi4", "ti,omap3"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + hwconfig { + i_enable_mmc = <1>; + i_enable_musb = <1>; + i_musb_mode = <1>;/*0-undefined, 1-HOST, 2-PERIPHERAL, 3-OTG*/ + i_musb_power=<500>; + i_enable_ehci = <0>; + i_usb_reset_gpio = <20>; /* DUMMY Entry */ + i_enable_eth = <1>; + i_eth_irq_gpio = <130>; + i_eth_fifo_gpio = <0>; + i_eth_cs = <4>; + i_gpio_leds_0 = "led0:red", "none", "false", "102", "0"; + i_gpio_leds_1 = "led1:yellow", "none", "false", "103", "0"; + i_gpio_leds_2 = "led2:green", "none", "false", "104", "0"; + i_gpio_leds_3 = "led3:orange", "none", "false", "101", "0"; + i_gpio_leds_4 = "usb:enable", "none", "false", "110", "1"; + i_gpio_leds_5 = "usbhub:reset", "none", "false", "27", "0"; + i_gpio_leds_6 = "iic:reset", "none", "false", "163", "0"; + i_gpio_leds_7 = "rs232:reset", "none", "false", "26", "0"; + i_i2c_bus_hw_2 = "2", "100"; + i_i2c_device_0 = "rtc8564", "0x51", "2"; + i_i2c_bus_hw_3 = "3", "100"; + i_enable_flash = <1>; + i_enable_audio = <0>; + i_enable_video = <0>; + i_enable_can = <0>; + }; + + ue_pinctrl { +/* GPIO: HW ID */ + pin_94 = "cam_hs.gpio_94", "IEN", "PTU", "DIS"; /* GPIO_94 */ + pin_95 = "cam_vs.gpio_95", "IEN", "PTU", "DIS"; /* GPIO_95 */ + pin_96 = "cam_xclka.gpio_96", "IEN", "PTU", "DIS"; /* GPIO_96 */ + +/* GPIO: Digital Out */ + pin_156 = "mcbsp1_clkr.gpio_156", "IEN", "PTU", "DIS"; /* GPIO_156 */ + pin_157 = "mcbsp1_fsr.gpio_157", "IEN", "PTU", "DIS"; /* GPIO_157 */ + pin_158 = "mcbsp1_dx.gpio_158", "IEN", "PTU", "DIS"; /* GPIO_158 */ + pin_159 = "mcbsp1_dr.gpio_159", "IEN", "PTU", "DIS"; /* GPIO_159 */ + pin_160 = "mcbsp_clks.gpio_160", "IEN", "PTU", "DIS"; /* GPIO_160 */ + pin_161 = "mcbsp1_fsx.gpio_161", "IEN", "PTU", "DIS"; /* GPIO_161 */ + pin_162 = "mcbsp1_clkx.gpio_162", "IEN", "PTU", "DIS"; /*GPIO_162 */ + +/* GPIO: Digital In */ + pin_99 = "cam_d0.gpio_99", "IEN", "PTU", "DIS"; /* D_IN1_I */ + pin_100 = "cam_d1.gpio_100", "IEN", "PTU", "DIS"; /* D_IN2_I */ + pin_106 = "cam_d7.gpio_106", "IEN", "PTD", "DIS"; /* D_IN3_I */ + pin_107 = "cam_d8.gpio_107", "IEN", "PTD", "DIS"; /* D_IN4_I */ + pin_108 = "cam_d9.gpio_108", "IEN", "PTD", "DIS"; /* D_IN5_I */ + +/* GPIO: Watchdog Trigger */ + pin_117 = "mcbsp2_clkx.gpio_117", "IDIS", "PTD", "DIS"; /* WD_TRIGGER */ + +/* GPIO: TestAdapter */ + pin_171 = "mcspi1_clk.gpio_171", "IEN", "PTU", "DIS"; /* TP200 */ + pin_172 = "mcspi1_simo.gpio_172", "IEN", "PTU", "DIS"; /* TP201 */ + pin_173 = "mcspi1_somi.gpio_173", "IEN", "PTU", "DIS"; /* TP202 */ + pin_174 = "mcspi1_cs0.gpio_174", "IEN", "PTU", "DIS"; /* TP203 */ + pin_177 = "mcspi1_cs3.gpio_177", "IEN", "PTU", "DIS"; /* TP204 */ + pin_178 = "mcspi2_clk.gpio_178", "IEN", "PTU", "DIS"; /* TP205 */ + pin_179 = "mcspi2_simo.gpio_179", "IEN", "PTU", "DIS"; /* TP206 */ + pin_180 = "mcspi2_somi.gpio_180", "IEN", "PTU", "DIS"; /* TP207 */ + pin_1 = "sys_clkreq.gpio_1", "IEN", "PTU", "DIS"; /* TP240 */ + + +/* USB0 */ + pin_120 = "hsusb0_clk.hsusb0_clk", "IEN", "PTD", "DIS"; /* USB0 CLK */ + pin_121 = "hsusb0_stp.hsusb0_stp", "IDIS", "PTU", "EN"; /* USB0 STP */ + pin_122 = "hsusb0_dir.hsusb0_dir", "IEN", "PTD", "DIS"; /* USB0 DIR */ + pin_124 = "hsusb0_nxt.hsusb0_nxt", "IEN", "PTD", "DIS"; /* USB0 NXT */ + pin_125 = "hsusb0_data0.hsusb0_data0", "IEN", "PTD", "DIS"; /* USB0 D0 */ + pin_0130 = "hsusb0_data1.hsusb0_data1", "IEN", "PTD", "DIS"; /* USB0 D1 */ + pin_0131 = "hsusb0_data2.hsusb0_data2", "IEN", "PTD", "DIS"; /* USB0 D2 */ + pin_169 = "hsusb0_data3.hsusb0_data3", "IEN", "PTD", "DIS"; /* USB0 D3 */ + pin_188 = "hsusb0_data4.hsusb0_data4", "IEN", "PTD", "DIS"; /* USB0 D4 */ + pin_189 = "hsusb0_data5.hsusb0_data5", "IEN", "PTD", "DIS"; /* USB0 D5 */ + pin_190 = "hsusb0_data6.hsusb0_data6", "IEN", "PTD", "DIS"; /* USB0 D6 */ + pin_191 = "hsusb0_data7.hsusb0_data7", "IEN", "PTD", "DIS"; /* USB0 D7 */ + pin_110 = "cam_d11.gpio_110", "IEN", "PTD", "DIS"; /* #USB_OTG_RESET */ + pin_27 = "etk_d13.gpio_27", "IEN", "PTD", "DIS"; /* #USB_HUB_RESET */ + +/* SERIELL */ + pin_148 = "uart1_tx.uart1_tx", "IDIS", "PTD", "DIS"; /* TXD1 */ + pin_151 = "uart1_rx.uart1_rx", "IEN", "PTU", "EN"; /* RXD1 */ + pin_149 = "uart1_rts.uart1_rts", "IDIS", "PTD", "DIS"; /* #RTS1 */ + +/* ETHERNET */ + pin_55 = "gpmc_ncs4.gpmc_ncs4", "IEN", "PTU", "EN"; /* #GPMC_CS4 ETH */ + pin_130 = "sdmmc2_clk.gpio_130", "IEN", "PTD", "DIS"; /* #ETH_IRQ */ +/* SD CARD */ + pin_126 = "sdmmc1_dat4.gpio_126", "IEN", "PTD", "DIS"; /* SD_WP */ + pin_59 = "gpmc_clk.gpio_59", "IEN", "PTD", "DIS"; /* #SD_CD */ +/* I2C #2 */ + pin_168 = "i2c2_scl.i2c2_scl", "IEN", "PTU", "EN"; /* SCL2 */ + pin_183 = "i2c2_sda.i2c2_sda", "IEN", "PTU", "EN"; /* SDA2 */ + +/* I2C #3 */ + pin_184 = "i2c3_scl.i2c3_scl", "IEN", "PTU", "EN"; /* SCL3 */ + pin_185 = "i2c3_sda.i2c3_sda", "IEN", "PTU", "EN"; /* SDA3 */ + + +/* DIVERSES */ + pin_101 = "cam_d2.gpio_101", "IDIS", "PTD", "DIS"; /* (Orange) LED */ + pin_102 = "cam_d3.gpio_102", "IDIS", "PTD", "DIS"; /* (Red) LED1 */ + pin_103 = "cam_d4.gpio_103", "IDIS", "PTD", "DIS"; /* (Yellow) LED2 */ + pin_104 = "cam_d5.gpio_104", "IDIS", "PTD", "DIS"; /* (Green) LED3 */ + pin_105 = "cam_d6.gpio_105", "IEN", "PTD", "DIS"; /* Push Button*/ + pin_163 = "uart3_cts_rctx.gpio_163", "IEN", "PTD", "DIS"; /* II2 Reset */ + pin_26 = "etk_d12.gpio_26", "IEN", "PTD", "DIS"; /* RS232 Reset */ + }; + +}; + diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig index 81c898b66e..23e971b5ba 100644 --- a/arch/arm/mach-omap2/omap3/Kconfig +++ b/arch/arm/mach-omap2/omap3/Kconfig @@ -43,6 +43,15 @@ config TARGET_OMAP3_BEAGLE select OMAP3_GPIO_6 imply CMD_DM
+config TARGET_OMAP3_MWS4 + bool "Ultratrokik OMAP3 MWS4" + select DM + select DM_GPIO + select DM_SERIAL + select OMAP3_GPIO_5 + select OMAP3_GPIO_6 + imply CMD_DM + config TARGET_CM_T35 bool "CompuLab CM-T3530 and CM-T3730 boards" select OMAP3_GPIO_2 @@ -162,5 +171,6 @@ source "board/isee/igep00x0/Kconfig" source "board/logicpd/omap3som/Kconfig" source "board/nokia/rx51/Kconfig" source "board/lg/sniper/Kconfig" +source "board/ultratronik/mws4/Kconfig"
endif diff --git a/board/ultratronik/mws4/Kconfig b/board/ultratronik/mws4/Kconfig new file mode 100644 index 0000000000..95d4c9e460 --- /dev/null +++ b/board/ultratronik/mws4/Kconfig @@ -0,0 +1,12 @@ +if TARGET_OMAP3_MWS4 + +config SYS_BOARD + default "mws4" + +config SYS_VENDOR + default "ultratronik" + +config SYS_CONFIG_NAME + default "omap3_mws4" + +endif diff --git a/board/ultratronik/mws4/MAINTAINERS b/board/ultratronik/mws4/MAINTAINERS new file mode 100644 index 0000000000..fc9022c594 --- /dev/null +++ b/board/ultratronik/mws4/MAINTAINERS @@ -0,0 +1,6 @@ +MWS4 BfS +M: M. Ulbricht ulbricht@innoroute.de +S: Maintained +F: board/ultratronik/mws4/ +F: include/configs/omap3_mws4.h +F: configs/omap3_mws4_defconfig diff --git a/board/ultratronik/mws4/Makefile b/board/ultratronik/mws4/Makefile new file mode 100644 index 0000000000..507a365aeb --- /dev/null +++ b/board/ultratronik/mws4/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y := mws4.o diff --git a/board/ultratronik/mws4/default.env b/board/ultratronik/mws4/default.env new file mode 100644 index 0000000000..b610a9622d --- /dev/null +++ b/board/ultratronik/mws4/default.env @@ -0,0 +1,11 @@ +arch=arm +baudrate=115200 +board=mws4 +board_name=mws4 +bootargs=console=ttyS2,115200 earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait +boot_sd=fatload mmc 0 0x80000000 uImage; fatload mmc 0 0x89000000 omap3-mws4.dtb; bootm 0x80000000 - 0x89000000 +boot_nand=nand read.e 0x80000000 0x140000 0xA00000;nand read.e 0x89000000 0x120000 0x20000;bootm 0x80000000 - 0x89000000 +bootmode_nand=setenv bootcmd run boot_nand;setenv bootargs 'console=ttyS2,115200 ubi.mtd=5 root=ubi0:rootfs rootfstype=ubifs rw rootwait';saveenv +bootmode_sd=setenv bootcmd run boot_sd; setenv bootargs 'console=ttyS2,115200 earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait';saveenv +flash_kernel=fatload mmc 0 0x80000000 uImage;nand erase 0x140000 0xA00000;nand write.e 0x80000000 0x140000 0xA00000;fatload mmc 0 0x89000000 omap3-mws4.dtb;nand erase 0x120000 0x20000;nand write.e 0x89000000 0x120000 0x20000 +bootcmd=run boot_sd diff --git a/board/ultratronik/mws4/mws4.c b/board/ultratronik/mws4/mws4.c new file mode 100644 index 0000000000..7ab5e2745b --- /dev/null +++ b/board/ultratronik/mws4/mws4.c @@ -0,0 +1,283 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2004-2011 + * Texas Instruments, <www.ti.com> + * + * Author : + * Sunil Kumar sunilsaini05@gmail.com + * Shashi Ranjan shashiranjanmca05@gmail.com + * + * Derived from Beagle Board and 3430 SDP code by + * Richard Woodruff r-woodruff2@ti.com + * Syed Mohammed Khasim khasim@ti.com + * + */ +// mod for BfS ulbricht@innoroute.de 2021 +#include <common.h> +#include <bootstage.h> +#include <dm.h> +#include <env.h> +#include <init.h> +#include <net.h> +#include <ns16550.h> +#include <serial.h> +#include <twl4030.h> +#include <linux/mtd/rawnand.h> +#include <asm/io.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mux.h> +#include <asm/arch/mem.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/mach-types.h> +#include <asm/omap_musb.h> +#include <linux/errno.h> +#include <linux/usb/ch9.h> +#include <linux/usb/gadget.h> +#include <linux/usb/musb.h> +#include "mws4.h" +#include <command.h> +#include <usb.h> +#include <asm/ehci-omap.h> + +#define TWL4030_I2C_BUS 0 +#define EXPANSION_EEPROM_I2C_BUS 1 +#define EXPANSION_EEPROM_I2C_ADDRESS 0x50 + +#define TINCANTOOLS_ZIPPY 0x01000100 +#define TINCANTOOLS_ZIPPY2 0x02000100 +#define TINCANTOOLS_TRAINER 0x04000100 +#define TINCANTOOLS_SHOWDOG 0x03000100 +#define KBADC_BEAGLEFPGA 0x01000600 +#define LW_BEAGLETOUCH 0x01000700 +#define BRAINMUX_LCDOG 0x01000800 +#define BRAINMUX_LCDOGTOUCH 0x02000800 +#define BBTOYS_WIFI 0x01000B00 +#define BBTOYS_VGA 0x02000B00 +#define BBTOYS_LCD 0x03000B00 +#define BCT_BRETTL3 0x01000F00 +#define BCT_BRETTL4 0x02000F00 +#define LSR_COM6L_ADPT 0x01001300 +#define BEAGLE_NO_EEPROM 0xffffffff + +DECLARE_GLOBAL_DATA_PTR; + +static struct { + unsigned int device_vendor; + unsigned char revision; + unsigned char content; + char fab_revision[8]; + char env_var[16]; + char env_setting[64]; +} expansion_config; + + +#if !defined(CONFIG_SPL_BUILD) +/* Call usb_stop() before starting the kernel */ +//void show_boot_progress(int val) +//{ +// if (val == BOOTSTAGE_ID_RUN_OS) +// usb_stop(); +//} + +static struct omap_usbhs_board_data usbhs_bdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY +}; + +int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); +} + +int ehci_hcd_stop(int index) +{ + return omap_ehci_hcd_stop(); +} +#endif +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* board id for Linux */ + gd->bd->bi_arch_number = 5109; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + +printf("Support InnoRoute.de\n"); +// init power + twl4030_power_init(); +// unprotect Power registers + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, + TWL4030_PM_MASTER_PROTECT_KEY, 0xC0); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, + TWL4030_PM_MASTER_PROTECT_KEY, 0x0C); +// enable HF 19,5MhZ CLK (need for VBUS!) + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, + TWL4030_PM_MASTER_CFG_BOOT, 0x19); +// protect power registers + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, + TWL4030_PM_MASTER_PROTECT_KEY, 0x00); + return 0; +} + +#if defined(CONFIG_SPL_OS_BOOT) +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + + return 0; +} +#endif /* CONFIG_SPL_OS_BOOT */ + +/* + * Routine: get_board_revision + * Description: Detect if we are running on a Beagle revision Ax/Bx, + * C1/2/3, C4, xM Ax/Bx or xM Cx. This can be done by reading + * the level of GPIO173, GPIO172 and GPIO171. This should + * result in + * GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx + * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3 + * GPIO173, GPIO172, GPIO171: 1 0 1 => C4 + * GPIO173, GPIO172, GPIO171: 0 1 0 => xM Cx + * GPIO173, GPIO172, GPIO171: 0 0 0 => xM Ax/Bx + */ +static int get_board_revision(void) +{ + static int revision = 7; + +/* if (revision == -1) {*/ +/* if (!gpio_request(171, "rev0") &&*/ +/* !gpio_request(172, "rev1") &&*/ +/* !gpio_request(173, "rev2")) {*/ +/* gpio_direction_input(171);*/ +/* gpio_direction_input(172);*/ +/* gpio_direction_input(173);*/ + +/* revision = gpio_get_value(173) << 2 |*/ +/* gpio_get_value(172) << 1 |*/ +/* gpio_get_value(171);*/ +/* } else {*/ +/* printf("Error: unable to acquire board revision GPIOs\n");*/ +/* }*/ +/* }*/ + + return revision; +} + +#ifdef CONFIG_SPL_BUILD +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on the first bank. This + * provides the timing values back to the function that configures + * the memory. + */ +void get_board_mem_timings(struct board_sdrc_timings *timings) +{ + int pop_mfr, pop_id; + + /* 256MB DDR */ + timings->mcfg = HYNIX_V_MCFG_200(256 << 20); + timings->ctrla = HYNIX_V_ACTIMA_200; + timings->ctrlb = HYNIX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mr = MICRON_V_MR_165; +} +#endif + + + + + +/* + * Routine: misc_init_r + * Description: Configure board specific parts + */ +int misc_init_r(void) +{ + struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE; + struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE; + struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE; + bool generate_fake_mac = false; + u32 value; + + /* Enable i2c2 pullup resisters */ + value = readl(&prog_io_base->io1); + value &= ~(PRG_I2C2_PULLUPRESX); + writel(value, &prog_io_base->io1); +env_set("beaglerev", "AxBx"); + + + +env_set("buddy", "none"); + + + + /* Set GPIO states before they are made outputs */ +/* writel(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1,*/ +/* &gpio6_base->setdataout);*/ +/* writel(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |*/ +/* GPIO15 | GPIO14 | GPIO13 | GPIO12, &gpio5_base->setdataout);*/ + +/* //Configure GPIOs to output */ +/* writel(~(GPIO23 | GPIO10 | GPIO8 | GPIO2 | GPIO1), &gpio6_base->oe);*/ +/* writel(~(GPIO31 | GPIO30 | GPIO29 | GPIO28 | GPIO22 | GPIO21 |*/ +/* GPIO15 | GPIO14 | GPIO13 | GPIO12), &gpio5_base->oe);*/ + + omap_die_id_display(); +/* Set VAUX2 to 1.8V for EHCI PHY */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, + TWL4030_PM_RECEIVER_VAUX2_VSEL_18, + TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); + + //dieid_num_r(); +/*#ifdef CONFIG_VIDEO_OMAP3*/ +/* beagle_dvi_pup();*/ +/* beagle_display_init();*/ +/* omap3_dss_enable();*/ +/*#endif*/ + +/* if (generate_fake_mac)*/ +/* omap_die_id_usbethaddr();*/ + +/*#if defined(CONFIG_MTDIDS_DEFAULT) && defined(CONFIG_MTDPARTS_DEFAULT)*/ +/* if (strlen(CONFIG_MTDIDS_DEFAULT))*/ +/* env_set("mtdids", CONFIG_MTDIDS_DEFAULT);*/ + +/* if (strlen(CONFIG_MTDPARTS_DEFAULT))*/ +/* env_set("mtdparts", CONFIG_MTDPARTS_DEFAULT);*/ +/*#endif*/ + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_MWS4(); +} + +#if defined(CONFIG_MMC) +int board_mmc_init(struct bd_info *bis) +{ + return omap_mmc_init(0, 0, 0, -1, -1); +} +#endif + +#if defined(CONFIG_MMC) +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif diff --git a/board/ultratronik/mws4/mws4.h b/board/ultratronik/mws4/mws4.h new file mode 100644 index 0000000000..9655d19be3 --- /dev/null +++ b/board/ultratronik/mws4/mws4.h @@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2008 + * Dirk Behme dirk.behme@gmail.com + */ +// mod for BfS ulbricht@innoroute.de 2021 +#ifndef _BEAGLE_H_ +#define _BEAGLE_H_ + +#include <asm/arch/dss.h> + +const omap3_sysinfo sysinfo = { + DDR_STACKED, + "BfS MWS4", +#if defined(CONFIG_ENV_IS_IN_ONENAND) + "OneNAND", +#else + "NAND", +#endif +}; + +/* BeagleBoard revisions */ +#define REVISION_AXBX 0x7 +#define REVISION_CX 0x6 +#define REVISION_C4 0x5 +#define REVISION_XM_AB 0x0 +#define REVISION_XM_C 0x2 + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_MWS4() \ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ + MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*SYS_nDMA_REQ3*/\ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\ + MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ + /*CAMERA*/\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M4)) /*CAM_HS HW0*/\ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) /*CAM_VS HW1*/\ + MUX_VAL(CP(CAM_XCLKA), (IEN | PTU | EN | M4)) /*CAM_XCLKA HW2*/\ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M4)) /*CAM_D0 DIN1*/\ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M4)) /*CAM_D1 DIN2*/\ + MUX_VAL(CP(CAM_D2), (IDIS | PTD | DIS | M4)) /*CAM_D2, led_sm*/\ + MUX_VAL(CP(CAM_D3), (IDIS | PTD | DIS | M4)) /*CAM_D3, led1*/\ + MUX_VAL(CP(CAM_D4), (IDIS | PTD | DIS | M4)) /*CAM_D4, led2*/\ + MUX_VAL(CP(CAM_D5), (IDIS | PTD | DIS | M4)) /*CAM_D5, led3*/\ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M4)) /*CAM_D6 sw_sm*/\ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M4)) /*CAM_D7 DIN3*/\ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M4)) /*CAM_D8 DIN4*/\ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M4)) /*CAM_D9 DIN5*/\ + MUX_VAL(CP(CAM_D11), (IDIS | PTD | DIS | M4)) /*CAM_D11,usb2en*/\ + /*Audio Interface */\ + MUX_VAL(CP(MCBSP2_CLKX), (IDIS | PTD | DIS | M4)) /*McBSP2_CLKX wd_trigger*/\ + /*Expansion card */\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ + /*Wireless LAN */\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | DIS | M4)) /*GPIO_130 eth_irq*/\ + /*Modem Interface */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*GPIO_149*/ \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M0)) /*SSI1_DAT_RX*/\ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /*GPIO_156*/\ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)) /*GPIO_157 GPO1*/\ + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158 GPO2*/\ + MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159 GPO3*/\ + MUX_VAL(CP(MCBSP_CLKS), (IDIS | PTD | DIS | M4)) /*McBSP_CLKS GPO4*/\ + MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161 GPO5*/\ + MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162 GPO6*/\ + /*Serial Interface*/\ +/* MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) *//*UART3_CTS_RCTX IIC_RES_18*/\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | DIS | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | DIS | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | DIS | M0)) /*I2C2_SCL*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | DIS | M0)) /*I2C2_SDA*/\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | DIS | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | DIS | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | DIS | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | DIS | M0)) /*I2C4_SDA*/\ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M0)) /*GPIO_2*/\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M0)) /*GPIO_3*/\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0)) /*GPIO_4*/\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M0)) /*GPIO_5*/\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M0)) /*GPIO_6*/\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M0)) /*GPIO_7*/\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M0)) /*GPIO_8*/ \ + MUX_VAL(CP(SYS_OFF_MODE), (IDIS | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/ + + +#endif + + + diff --git a/configs/omap3_mws4_defconfig b/configs/omap3_mws4_defconfig new file mode 100644 index 0000000000..af0bdd1823 --- /dev/null +++ b/configs/omap3_mws4_defconfig @@ -0,0 +1,74 @@ +CONFIG_SYS_NAND_PAGE_SIZE=2048 +CONFIG_SYS_NAND_OOBSIZE=64 +CONFIG_ARM=y +CONFIG_ARCH_OMAP2PLUS=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_OFFSET=0x100000 +CONFIG_TARGET_OMAP3_MWS4=y +CONFIG_DEFAULT_DEVICE_TREE="omap3-mws4" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NAND_BOOT=y +CONFIG_SD_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR="q" +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_USE_PREBOOT=y +CONFIG_DEFAULT_FDT_FILE="omap3-mws4.dtb" +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SYS_PROMPT="MWS4 # " +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_USE_DEFAULT_ENV_FILE=y +CONFIG_DEFAULT_ENV_FILE="board/ultratronik/mws4/default.env" +CONFIG_VERSION_VARIABLE=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82000000 +CONFIG_DM_MMC=y +CONFIG_MMC_OMAP_HS=y +CONFIG_CMD_PINMUX=y +CONFIG_DM_I2C=y +CONFIG_PINCTRL=y +CONFIG_MTD=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y +# CONFIG_NAND_OMAP_GPMC_PREFETCH is not set +CONFIG_SYS_NAND_BUSWIDTH_16BIT=y +CONFIG_DM_ETH=y +CONFIG_SPI=y +CONFIG_PHY=y +CONFIG_USB_MUSB_TI=y +CONFIG_DM_SPI=y +CONFIG_OMAP3_SPI=y +CONFIG_USB=y +CONFIG_USB_MUSB_TI=y +CONFIG_DM_USB=y +CONFIG_OMAP_USB_PHY=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OMAP3=y +CONFIG_USB_MUSB_HOST=y +CONFIG_USB_MUSB_GADGET=n +CONFIG_USB_MUSB_OMAP2PLUS=y +CONFIG_TWL4030_USB=y +CONFIG_USB_ETHER=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_VIDEO_OMAP3=y +CONFIG_BCH=y +CONFIG_SPL_OF_LIBFDT=y diff --git a/include/configs/omap3_mws4.h b/include/configs/omap3_mws4.h new file mode 100644 index 0000000000..862e910aab --- /dev/null +++ b/include/configs/omap3_mws4.h @@ -0,0 +1,103 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments. + * Richard Woodruff r-woodruff2@ti.com + * Syed Mohammed Khasim x0khasim@ti.com + * + * Configuration settings for the TI OMAP3530 Beagle board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/ti_omap3_common.h> + +/* + * We are only ever GP parts and will utilize all of the "downloaded image" + * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). + */ + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_CONS_INDEX 3 + +/* NAND */ +#if defined(CONFIG_MTD_RAW_NAND) +#define CONFIG_SYS_FLASH_BASE NAND_BASE +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW +//#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#define CONFIG_SYS_ENV_SECT_SIZE SZ_128K +/* NAND: SPL falcon mode configs */ +#if defined(CONFIG_SPL_OS_BOOT) +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000 +#endif /* CONFIG_SPL_OS_BOOT */ +#endif /* CONFIG_MTD_RAW_NAND */ + +/* USB EHCI */ +//#define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 147 + +/* Enable Multi Bus support for I2C */ +#define CONFIG_I2C_MULTI_BUS + +/* DSS Support */ + +/* TWL4030 LED Support */ + +#define MEM_LAYOUT_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV + +#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "setenv mmcdev " #instance "; " \ + "run mmcboot\0" +#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#if defined(CONFIG_MTD_RAW_NAND) + +#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "if test ${mtdids} = '' || test ${mtdparts} = '' ; then " \ + "echo NAND boot disabled: No mtdids and/or mtdparts; " \ + "else " \ + "run nandboot; " \ + "fi\0" +#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(LEGACY_MMC, legacy_mmc, 0) \ + func(UBIFS, ubifs, 0) \ + func(NAND, nand, 0) + +#else /* !CONFIG_MTD_RAW_NAND */ + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(LEGACY_MMC, legacy_mmc, 0) + +#endif /* CONFIG_MTD_RAW_NAND */ + +#include <config_distro_bootcmd.h> + +#define CONFIG_EXTRA_ENV_SETTINGS \ + MEM_LAYOUT_ENV_SETTINGS \ + "console=ttyO2,115200n8\0" \ + BOOTENV +#endif /* __CONFIG_H */
On Sun, May 08, 2022 at 03:46:55PM +0200, Marian Ulbricht wrote:
mws4 is an arm based nuclear probe hardware used from german government to monitor nuclear activity
Signed-off-by: Marian Ulbricht ulbricht@innoroute.de
Thanks for the submission. Have you submitted the board dts files to upstream Linux? Also, please remove all of the commented out code in the board files, etc.
Am 08.05.22 um 16:21 schrieb Tom Rini:
On Sun, May 08, 2022 at 03:46:55PM +0200, Marian Ulbricht wrote:
mws4 is an arm based nuclear probe hardware used from german government to monitor nuclear activity
Signed-off-by: Marian Ulbricht ulbricht@innoroute.de
Thanks for the submission. Have you submitted the board dts files to upstream Linux? Also, please remove all of the commented out code in the board files, etc.
Hi, not yet, i started from bottom up: u-boot -> buildroot -> kernel
[PATCH 1/1 v2] add support for mws4 board
mws4 is an arm based nuclear probe hardware used from german government to monitor nuclear activity
Signed-off-by: Marian Ulbricht ulbricht@innoroute.de --- Changes v2:
* code cleanup
arch/arm/dts/Makefile | 3 + arch/arm/dts/omap3-mws4-u-boot.dtsi | 14 ++ arch/arm/dts/omap3-mws4.dts | 137 +++++++++++++++++ arch/arm/mach-omap2/omap3/Kconfig | 10 ++ board/ultratronik/mws4/Kconfig | 12 ++ board/ultratronik/mws4/MAINTAINERS | 6 + board/ultratronik/mws4/Makefile | 6 + board/ultratronik/mws4/default.env | 11 ++ board/ultratronik/mws4/mws4.c | 226 ++++++++++++++++++++++++++++ board/ultratronik/mws4/mws4.h | 203 +++++++++++++++++++++++++ configs/omap3_mws4_defconfig | 74 +++++++++ include/configs/omap3_mws4.h | 100 ++++++++++++ 12 files changed, 802 insertions(+) create mode 100644 arch/arm/dts/omap3-mws4-u-boot.dtsi create mode 100644 arch/arm/dts/omap3-mws4.dts create mode 100644 board/ultratronik/mws4/Kconfig create mode 100644 board/ultratronik/mws4/MAINTAINERS create mode 100644 board/ultratronik/mws4/Makefile create mode 100644 board/ultratronik/mws4/default.env create mode 100644 board/ultratronik/mws4/mws4.c create mode 100644 board/ultratronik/mws4/mws4.h create mode 100644 configs/omap3_mws4_defconfig create mode 100644 include/configs/omap3_mws4.h
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 83630af4f6..7b68a49990 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1047,6 +1047,9 @@ dtb-$(CONFIG_TARGET_OMAP3_BEAGLE) += \ omap3-beagle-xm.dtb \ omap3-beagle.dtb
+dtb-$(CONFIG_TARGET_OMAP3_MWS4) += \ + omap3-mws4.dtb + dtb-$(CONFIG_TARGET_OMAP3_IGEP00X0) += \ omap3-igep0020.dtb
diff --git a/arch/arm/dts/omap3-mws4-u-boot.dtsi b/arch/arm/dts/omap3-mws4-u-boot.dtsi new file mode 100644 index 0000000000..2c03701c89 --- /dev/null +++ b/arch/arm/dts/omap3-mws4-u-boot.dtsi @@ -0,0 +1,14 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * U-Boot additions + * + * (C) Copyright 2017 Derald D. Woods woods.technical@gmail.com + */ + +#include "omap3-u-boot.dtsi" + +/ { + chosen { + stdout-path = &uart3; + }; +}; diff --git a/arch/arm/dts/omap3-mws4.dts b/arch/arm/dts/omap3-mws4.dts new file mode 100644 index 0000000000..f8a5c3d5b8 --- /dev/null +++ b/arch/arm/dts/omap3-mws4.dts @@ -0,0 +1,137 @@ +/* + * Copyright (C) 2011 Texas Instruments Incorporated - http://www.ti.com/ + * + * Modified 2015 by Bernhard Gätzschmann, Ultratronik from Beagleboard xM + * + * Modified 2022 Marian Ulbricht ulbricht@innoroute.de + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + */ +/dts-v1/; + +#include "omap34xx.dtsi" + +/ { + model = "Ultratronik BFS MWS4"; + compatible = "ti,omap3-mmi4", "ti,omap3"; + + memory { + device_type = "memory"; + reg = <0x80000000 0x10000000>; /* 256 MB */ + }; + + hwconfig { + i_enable_mmc = <1>; + i_enable_musb = <1>; + i_musb_mode = <1>;/*0-undefined, 1-HOST, 2-PERIPHERAL, 3-OTG*/ + i_musb_power=<500>; + i_enable_ehci = <0>; + i_usb_reset_gpio = <20>; /* DUMMY Entry */ + i_enable_eth = <1>; + i_eth_irq_gpio = <130>; + i_eth_fifo_gpio = <0>; + i_eth_cs = <4>; + i_gpio_leds_0 = "led0:red", "none", "false", "102", "0"; + i_gpio_leds_1 = "led1:yellow", "none", "false", "103", "0"; + i_gpio_leds_2 = "led2:green", "none", "false", "104", "0"; + i_gpio_leds_3 = "led3:orange", "none", "false", "101", "0"; + i_gpio_leds_4 = "usb:enable", "none", "false", "110", "1"; + i_gpio_leds_5 = "usbhub:reset", "none", "false", "27", "0"; + i_gpio_leds_6 = "iic:reset", "none", "false", "163", "0"; + i_gpio_leds_7 = "rs232:reset", "none", "false", "26", "0"; + i_i2c_bus_hw_2 = "2", "100"; + i_i2c_device_0 = "rtc8564", "0x51", "2"; + i_i2c_bus_hw_3 = "3", "100"; + i_enable_flash = <1>; + i_enable_audio = <0>; + i_enable_video = <0>; + i_enable_can = <0>; + }; + + ue_pinctrl { +/* GPIO: HW ID */ + pin_94 = "cam_hs.gpio_94", "IEN", "PTU", "DIS"; /* GPIO_94 */ + pin_95 = "cam_vs.gpio_95", "IEN", "PTU", "DIS"; /* GPIO_95 */ + pin_96 = "cam_xclka.gpio_96", "IEN", "PTU", "DIS"; /* GPIO_96 */ + +/* GPIO: Digital Out */ + pin_156 = "mcbsp1_clkr.gpio_156", "IEN", "PTU", "DIS"; /* GPIO_156 */ + pin_157 = "mcbsp1_fsr.gpio_157", "IEN", "PTU", "DIS"; /* GPIO_157 */ + pin_158 = "mcbsp1_dx.gpio_158", "IEN", "PTU", "DIS"; /* GPIO_158 */ + pin_159 = "mcbsp1_dr.gpio_159", "IEN", "PTU", "DIS"; /* GPIO_159 */ + pin_160 = "mcbsp_clks.gpio_160", "IEN", "PTU", "DIS"; /* GPIO_160 */ + pin_161 = "mcbsp1_fsx.gpio_161", "IEN", "PTU", "DIS"; /* GPIO_161 */ + pin_162 = "mcbsp1_clkx.gpio_162", "IEN", "PTU", "DIS"; /*GPIO_162 */ + +/* GPIO: Digital In */ + pin_99 = "cam_d0.gpio_99", "IEN", "PTU", "DIS"; /* D_IN1_I */ + pin_100 = "cam_d1.gpio_100", "IEN", "PTU", "DIS"; /* D_IN2_I */ + pin_106 = "cam_d7.gpio_106", "IEN", "PTD", "DIS"; /* D_IN3_I */ + pin_107 = "cam_d8.gpio_107", "IEN", "PTD", "DIS"; /* D_IN4_I */ + pin_108 = "cam_d9.gpio_108", "IEN", "PTD", "DIS"; /* D_IN5_I */ + +/* GPIO: Watchdog Trigger */ + pin_117 = "mcbsp2_clkx.gpio_117", "IDIS", "PTD", "DIS"; /* WD_TRIGGER */ + +/* GPIO: TestAdapter */ + pin_171 = "mcspi1_clk.gpio_171", "IEN", "PTU", "DIS"; /* TP200 */ + pin_172 = "mcspi1_simo.gpio_172", "IEN", "PTU", "DIS"; /* TP201 */ + pin_173 = "mcspi1_somi.gpio_173", "IEN", "PTU", "DIS"; /* TP202 */ + pin_174 = "mcspi1_cs0.gpio_174", "IEN", "PTU", "DIS"; /* TP203 */ + pin_177 = "mcspi1_cs3.gpio_177", "IEN", "PTU", "DIS"; /* TP204 */ + pin_178 = "mcspi2_clk.gpio_178", "IEN", "PTU", "DIS"; /* TP205 */ + pin_179 = "mcspi2_simo.gpio_179", "IEN", "PTU", "DIS"; /* TP206 */ + pin_180 = "mcspi2_somi.gpio_180", "IEN", "PTU", "DIS"; /* TP207 */ + pin_1 = "sys_clkreq.gpio_1", "IEN", "PTU", "DIS"; /* TP240 */ + + +/* USB0 */ + pin_120 = "hsusb0_clk.hsusb0_clk", "IEN", "PTD", "DIS"; /* USB0 CLK */ + pin_121 = "hsusb0_stp.hsusb0_stp", "IDIS", "PTU", "EN"; /* USB0 STP */ + pin_122 = "hsusb0_dir.hsusb0_dir", "IEN", "PTD", "DIS"; /* USB0 DIR */ + pin_124 = "hsusb0_nxt.hsusb0_nxt", "IEN", "PTD", "DIS"; /* USB0 NXT */ + pin_125 = "hsusb0_data0.hsusb0_data0", "IEN", "PTD", "DIS"; /* USB0 D0 */ + pin_0130 = "hsusb0_data1.hsusb0_data1", "IEN", "PTD", "DIS"; /* USB0 D1 */ + pin_0131 = "hsusb0_data2.hsusb0_data2", "IEN", "PTD", "DIS"; /* USB0 D2 */ + pin_169 = "hsusb0_data3.hsusb0_data3", "IEN", "PTD", "DIS"; /* USB0 D3 */ + pin_188 = "hsusb0_data4.hsusb0_data4", "IEN", "PTD", "DIS"; /* USB0 D4 */ + pin_189 = "hsusb0_data5.hsusb0_data5", "IEN", "PTD", "DIS"; /* USB0 D5 */ + pin_190 = "hsusb0_data6.hsusb0_data6", "IEN", "PTD", "DIS"; /* USB0 D6 */ + pin_191 = "hsusb0_data7.hsusb0_data7", "IEN", "PTD", "DIS"; /* USB0 D7 */ + pin_110 = "cam_d11.gpio_110", "IEN", "PTD", "DIS"; /* #USB_OTG_RESET */ + pin_27 = "etk_d13.gpio_27", "IEN", "PTD", "DIS"; /* #USB_HUB_RESET */ + +/* SERIELL */ + pin_148 = "uart1_tx.uart1_tx", "IDIS", "PTD", "DIS"; /* TXD1 */ + pin_151 = "uart1_rx.uart1_rx", "IEN", "PTU", "EN"; /* RXD1 */ + pin_149 = "uart1_rts.uart1_rts", "IDIS", "PTD", "DIS"; /* #RTS1 */ + +/* ETHERNET */ + pin_55 = "gpmc_ncs4.gpmc_ncs4", "IEN", "PTU", "EN"; /* #GPMC_CS4 ETH */ + pin_130 = "sdmmc2_clk.gpio_130", "IEN", "PTD", "DIS"; /* #ETH_IRQ */ +/* SD CARD */ + pin_126 = "sdmmc1_dat4.gpio_126", "IEN", "PTD", "DIS"; /* SD_WP */ + pin_59 = "gpmc_clk.gpio_59", "IEN", "PTD", "DIS"; /* #SD_CD */ +/* I2C #2 */ + pin_168 = "i2c2_scl.i2c2_scl", "IEN", "PTU", "EN"; /* SCL2 */ + pin_183 = "i2c2_sda.i2c2_sda", "IEN", "PTU", "EN"; /* SDA2 */ + +/* I2C #3 */ + pin_184 = "i2c3_scl.i2c3_scl", "IEN", "PTU", "EN"; /* SCL3 */ + pin_185 = "i2c3_sda.i2c3_sda", "IEN", "PTU", "EN"; /* SDA3 */ + + +/* DIVERSES */ + pin_101 = "cam_d2.gpio_101", "IDIS", "PTD", "DIS"; /* (Orange) LED */ + pin_102 = "cam_d3.gpio_102", "IDIS", "PTD", "DIS"; /* (Red) LED1 */ + pin_103 = "cam_d4.gpio_103", "IDIS", "PTD", "DIS"; /* (Yellow) LED2 */ + pin_104 = "cam_d5.gpio_104", "IDIS", "PTD", "DIS"; /* (Green) LED3 */ + pin_105 = "cam_d6.gpio_105", "IEN", "PTD", "DIS"; /* Push Button*/ + pin_163 = "uart3_cts_rctx.gpio_163", "IEN", "PTD", "DIS"; /* II2 Reset */ + pin_26 = "etk_d12.gpio_26", "IEN", "PTD", "DIS"; /* RS232 Reset */ + }; + +}; + diff --git a/arch/arm/mach-omap2/omap3/Kconfig b/arch/arm/mach-omap2/omap3/Kconfig index 81c898b66e..23e971b5ba 100644 --- a/arch/arm/mach-omap2/omap3/Kconfig +++ b/arch/arm/mach-omap2/omap3/Kconfig @@ -43,6 +43,15 @@ config TARGET_OMAP3_BEAGLE select OMAP3_GPIO_6 imply CMD_DM
+config TARGET_OMAP3_MWS4 + bool "Ultratrokik OMAP3 MWS4" + select DM + select DM_GPIO + select DM_SERIAL + select OMAP3_GPIO_5 + select OMAP3_GPIO_6 + imply CMD_DM + config TARGET_CM_T35 bool "CompuLab CM-T3530 and CM-T3730 boards" select OMAP3_GPIO_2 @@ -162,5 +171,6 @@ source "board/isee/igep00x0/Kconfig" source "board/logicpd/omap3som/Kconfig" source "board/nokia/rx51/Kconfig" source "board/lg/sniper/Kconfig" +source "board/ultratronik/mws4/Kconfig"
endif diff --git a/board/ultratronik/mws4/Kconfig b/board/ultratronik/mws4/Kconfig new file mode 100644 index 0000000000..95d4c9e460 --- /dev/null +++ b/board/ultratronik/mws4/Kconfig @@ -0,0 +1,12 @@ +if TARGET_OMAP3_MWS4 + +config SYS_BOARD + default "mws4" + +config SYS_VENDOR + default "ultratronik" + +config SYS_CONFIG_NAME + default "omap3_mws4" + +endif diff --git a/board/ultratronik/mws4/MAINTAINERS b/board/ultratronik/mws4/MAINTAINERS new file mode 100644 index 0000000000..fc9022c594 --- /dev/null +++ b/board/ultratronik/mws4/MAINTAINERS @@ -0,0 +1,6 @@ +MWS4 BfS +M: M. Ulbricht ulbricht@innoroute.de +S: Maintained +F: board/ultratronik/mws4/ +F: include/configs/omap3_mws4.h +F: configs/omap3_mws4_defconfig diff --git a/board/ultratronik/mws4/Makefile b/board/ultratronik/mws4/Makefile new file mode 100644 index 0000000000..507a365aeb --- /dev/null +++ b/board/ultratronik/mws4/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. + +obj-y := mws4.o diff --git a/board/ultratronik/mws4/default.env b/board/ultratronik/mws4/default.env new file mode 100644 index 0000000000..b610a9622d --- /dev/null +++ b/board/ultratronik/mws4/default.env @@ -0,0 +1,11 @@ +arch=arm +baudrate=115200 +board=mws4 +board_name=mws4 +bootargs=console=ttyS2,115200 earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait +boot_sd=fatload mmc 0 0x80000000 uImage; fatload mmc 0 0x89000000 omap3-mws4.dtb; bootm 0x80000000 - 0x89000000 +boot_nand=nand read.e 0x80000000 0x140000 0xA00000;nand read.e 0x89000000 0x120000 0x20000;bootm 0x80000000 - 0x89000000 +bootmode_nand=setenv bootcmd run boot_nand;setenv bootargs 'console=ttyS2,115200 ubi.mtd=5 root=ubi0:rootfs rootfstype=ubifs rw rootwait';saveenv +bootmode_sd=setenv bootcmd run boot_sd; setenv bootargs 'console=ttyS2,115200 earlyprintk root=/dev/mmcblk0p2 rootfstype=ext4 rw rootwait';saveenv +flash_kernel=fatload mmc 0 0x80000000 uImage;nand erase 0x140000 0xA00000;nand write.e 0x80000000 0x140000 0xA00000;fatload mmc 0 0x89000000 omap3-mws4.dtb;nand erase 0x120000 0x20000;nand write.e 0x89000000 0x120000 0x20000 +bootcmd=run boot_sd diff --git a/board/ultratronik/mws4/mws4.c b/board/ultratronik/mws4/mws4.c new file mode 100644 index 0000000000..463a337e74 --- /dev/null +++ b/board/ultratronik/mws4/mws4.c @@ -0,0 +1,226 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * (C) Copyright 2004-2011 + * Texas Instruments, <www.ti.com> + * + * Author : + * Sunil Kumar sunilsaini05@gmail.com + * Shashi Ranjan shashiranjanmca05@gmail.com + * + * Derived from Beagle Board and 3430 SDP code by + * Richard Woodruff r-woodruff2@ti.com + * Syed Mohammed Khasim khasim@ti.com + * + */ +// Modified 2022 for BfS Marian Ulbricht ulbricht@innoroute.de +#include <common.h> +#include <bootstage.h> +#include <dm.h> +#include <env.h> +#include <init.h> +#include <net.h> +#include <ns16550.h> +#include <serial.h> +#include <twl4030.h> +#include <linux/mtd/rawnand.h> +#include <asm/io.h> +#include <asm/arch/mmc_host_def.h> +#include <asm/arch/mux.h> +#include <asm/arch/mem.h> +#include <asm/arch/sys_proto.h> +#include <asm/gpio.h> +#include <asm/mach-types.h> +#include <asm/omap_musb.h> +#include <linux/errno.h> +#include <linux/usb/ch9.h> +#include <linux/usb/gadget.h> +#include <linux/usb/musb.h> +#include "mws4.h" +#include <command.h> +#include <usb.h> +#include <asm/ehci-omap.h> + +#define TWL4030_I2C_BUS 0 +#define EXPANSION_EEPROM_I2C_BUS 1 +#define EXPANSION_EEPROM_I2C_ADDRESS 0x50 + +#define TINCANTOOLS_ZIPPY 0x01000100 +#define TINCANTOOLS_ZIPPY2 0x02000100 +#define TINCANTOOLS_TRAINER 0x04000100 +#define TINCANTOOLS_SHOWDOG 0x03000100 +#define KBADC_BEAGLEFPGA 0x01000600 +#define LW_BEAGLETOUCH 0x01000700 +#define BRAINMUX_LCDOG 0x01000800 +#define BRAINMUX_LCDOGTOUCH 0x02000800 +#define BBTOYS_WIFI 0x01000B00 +#define BBTOYS_VGA 0x02000B00 +#define BBTOYS_LCD 0x03000B00 +#define BCT_BRETTL3 0x01000F00 +#define BCT_BRETTL4 0x02000F00 +#define LSR_COM6L_ADPT 0x01001300 +#define BEAGLE_NO_EEPROM 0xffffffff + +DECLARE_GLOBAL_DATA_PTR; + +static struct { + unsigned int device_vendor; + unsigned char revision; + unsigned char content; + char fab_revision[8]; + char env_var[16]; + char env_setting[64]; +} expansion_config; + + +#if !defined(CONFIG_SPL_BUILD) + +static struct omap_usbhs_board_data usbhs_bdata = { + .port_mode[0] = OMAP_EHCI_PORT_MODE_PHY +}; + +int ehci_hcd_init(int index, struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + return omap_ehci_hcd_init(&usbhs_bdata, hccr, hcor); +} + +int ehci_hcd_stop(int index) +{ + return omap_ehci_hcd_stop(); +} +#endif +/* + * Routine: board_init + * Description: Early hardware init. + */ +int board_init(void) +{ + gpmc_init(); /* in SRAM or SDRAM, finish GPMC */ + /* board id for Linux */ + gd->bd->bi_arch_number = 5109; + /* boot param addr */ + gd->bd->bi_boot_params = (OMAP34XX_SDRC_CS0 + 0x100); + +printf("Support InnoRoute.de\n"); +// init power + twl4030_power_init(); +// unprotect Power registers + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, + TWL4030_PM_MASTER_PROTECT_KEY, 0xC0); + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, + TWL4030_PM_MASTER_PROTECT_KEY, 0x0C); +// enable HF 19,5MhZ CLK (need for VBUS!) + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, + TWL4030_PM_MASTER_CFG_BOOT, 0x19); +// protect power registers + twl4030_i2c_write_u8(TWL4030_CHIP_PM_MASTER, + TWL4030_PM_MASTER_PROTECT_KEY, 0x00); + return 0; +} + +#if defined(CONFIG_SPL_OS_BOOT) +int spl_start_uboot(void) +{ + /* break into full u-boot on 'c' */ + if (serial_tstc() && serial_getc() == 'c') + return 1; + + return 0; +} +#endif /* CONFIG_SPL_OS_BOOT */ + +/* + * Routine: get_board_revision + * Description: Detect if we are running on a Beagle revision Ax/Bx, + * C1/2/3, C4, xM Ax/Bx or xM Cx. This can be done by reading + * the level of GPIO173, GPIO172 and GPIO171. This should + * result in + * GPIO173, GPIO172, GPIO171: 1 1 1 => Ax/Bx + * GPIO173, GPIO172, GPIO171: 1 1 0 => C1/2/3 + * GPIO173, GPIO172, GPIO171: 1 0 1 => C4 + * GPIO173, GPIO172, GPIO171: 0 1 0 => xM Cx + * GPIO173, GPIO172, GPIO171: 0 0 0 => xM Ax/Bx + */ +static int get_board_revision(void) +{ + static int revision = 7; + return revision; +} + +#ifdef CONFIG_SPL_BUILD +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on the first bank. This + * provides the timing values back to the function that configures + * the memory. + */ +void get_board_mem_timings(struct board_sdrc_timings *timings) +{ + int pop_mfr, pop_id; + + /* 256MB DDR */ + timings->mcfg = HYNIX_V_MCFG_200(256 << 20); + timings->ctrla = HYNIX_V_ACTIMA_200; + timings->ctrlb = HYNIX_V_ACTIMB_200; + timings->rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_200MHz; + timings->mr = MICRON_V_MR_165; +} +#endif + + + + + +/* + * Routine: misc_init_r + * Description: Configure board specific parts + */ +int misc_init_r(void) +{ + struct gpio *gpio5_base = (struct gpio *)OMAP34XX_GPIO5_BASE; + struct gpio *gpio6_base = (struct gpio *)OMAP34XX_GPIO6_BASE; + struct control_prog_io *prog_io_base = (struct control_prog_io *)OMAP34XX_CTRL_BASE; + bool generate_fake_mac = false; + u32 value; + + /* Enable i2c2 pullup resisters */ + value = readl(&prog_io_base->io1); + value &= ~(PRG_I2C2_PULLUPRESX); + writel(value, &prog_io_base->io1); + env_set("beaglerev", "AxBx"); + env_set("buddy", "none"); + + omap_die_id_display(); +/* Set VAUX2 to 1.8V for EHCI PHY */ + twl4030_pmrecv_vsel_cfg(TWL4030_PM_RECEIVER_VAUX2_DEDICATED, + TWL4030_PM_RECEIVER_VAUX2_VSEL_18, + TWL4030_PM_RECEIVER_VAUX2_DEV_GRP, + TWL4030_PM_RECEIVER_DEV_GRP_P1); + + return 0; +} + +/* + * Routine: set_muxconf_regs + * Description: Setting up the configuration Mux registers specific to the + * hardware. Many pins need to be moved from protect to primary + * mode. + */ +void set_muxconf_regs(void) +{ + MUX_MWS4(); +} + +#if defined(CONFIG_MMC) +int board_mmc_init(struct bd_info *bis) +{ + return omap_mmc_init(0, 0, 0, -1, -1); +} +#endif + +#if defined(CONFIG_MMC) +void board_mmc_power_init(void) +{ + twl4030_power_mmc_init(0); +} +#endif diff --git a/board/ultratronik/mws4/mws4.h b/board/ultratronik/mws4/mws4.h new file mode 100644 index 0000000000..9655d19be3 --- /dev/null +++ b/board/ultratronik/mws4/mws4.h @@ -0,0 +1,203 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2008 + * Dirk Behme dirk.behme@gmail.com + */ +// Modified 2022 for BfS Marian Ulbricht ulbricht@innoroute.de +#ifndef _BEAGLE_H_ +#define _BEAGLE_H_ + +#include <asm/arch/dss.h> + +const omap3_sysinfo sysinfo = { + DDR_STACKED, + "BfS MWS4", +#if defined(CONFIG_ENV_IS_IN_ONENAND) + "OneNAND", +#else + "NAND", +#endif +}; + +/* BeagleBoard revisions */ +#define REVISION_AXBX 0x7 +#define REVISION_CX 0x6 +#define REVISION_C4 0x5 +#define REVISION_XM_AB 0x0 +#define REVISION_XM_C 0x2 + +/* + * IEN - Input Enable + * IDIS - Input Disable + * PTD - Pull type Down + * PTU - Pull type Up + * DIS - Pull type selection is inactive + * EN - Pull type selection is active + * M0 - Mode 0 + * The commented string gives the final mux configuration for that pin + */ +#define MUX_MWS4() \ + /*SDRC*/\ + MUX_VAL(CP(SDRC_D0), (IEN | PTD | DIS | M0)) /*SDRC_D0*/\ + MUX_VAL(CP(SDRC_D1), (IEN | PTD | DIS | M0)) /*SDRC_D1*/\ + MUX_VAL(CP(SDRC_D2), (IEN | PTD | DIS | M0)) /*SDRC_D2*/\ + MUX_VAL(CP(SDRC_D3), (IEN | PTD | DIS | M0)) /*SDRC_D3*/\ + MUX_VAL(CP(SDRC_D4), (IEN | PTD | DIS | M0)) /*SDRC_D4*/\ + MUX_VAL(CP(SDRC_D5), (IEN | PTD | DIS | M0)) /*SDRC_D5*/\ + MUX_VAL(CP(SDRC_D6), (IEN | PTD | DIS | M0)) /*SDRC_D6*/\ + MUX_VAL(CP(SDRC_D7), (IEN | PTD | DIS | M0)) /*SDRC_D7*/\ + MUX_VAL(CP(SDRC_D8), (IEN | PTD | DIS | M0)) /*SDRC_D8*/\ + MUX_VAL(CP(SDRC_D9), (IEN | PTD | DIS | M0)) /*SDRC_D9*/\ + MUX_VAL(CP(SDRC_D10), (IEN | PTD | DIS | M0)) /*SDRC_D10*/\ + MUX_VAL(CP(SDRC_D11), (IEN | PTD | DIS | M0)) /*SDRC_D11*/\ + MUX_VAL(CP(SDRC_D12), (IEN | PTD | DIS | M0)) /*SDRC_D12*/\ + MUX_VAL(CP(SDRC_D13), (IEN | PTD | DIS | M0)) /*SDRC_D13*/\ + MUX_VAL(CP(SDRC_D14), (IEN | PTD | DIS | M0)) /*SDRC_D14*/\ + MUX_VAL(CP(SDRC_D15), (IEN | PTD | DIS | M0)) /*SDRC_D15*/\ + MUX_VAL(CP(SDRC_D16), (IEN | PTD | DIS | M0)) /*SDRC_D16*/\ + MUX_VAL(CP(SDRC_D17), (IEN | PTD | DIS | M0)) /*SDRC_D17*/\ + MUX_VAL(CP(SDRC_D18), (IEN | PTD | DIS | M0)) /*SDRC_D18*/\ + MUX_VAL(CP(SDRC_D19), (IEN | PTD | DIS | M0)) /*SDRC_D19*/\ + MUX_VAL(CP(SDRC_D20), (IEN | PTD | DIS | M0)) /*SDRC_D20*/\ + MUX_VAL(CP(SDRC_D21), (IEN | PTD | DIS | M0)) /*SDRC_D21*/\ + MUX_VAL(CP(SDRC_D22), (IEN | PTD | DIS | M0)) /*SDRC_D22*/\ + MUX_VAL(CP(SDRC_D23), (IEN | PTD | DIS | M0)) /*SDRC_D23*/\ + MUX_VAL(CP(SDRC_D24), (IEN | PTD | DIS | M0)) /*SDRC_D24*/\ + MUX_VAL(CP(SDRC_D25), (IEN | PTD | DIS | M0)) /*SDRC_D25*/\ + MUX_VAL(CP(SDRC_D26), (IEN | PTD | DIS | M0)) /*SDRC_D26*/\ + MUX_VAL(CP(SDRC_D27), (IEN | PTD | DIS | M0)) /*SDRC_D27*/\ + MUX_VAL(CP(SDRC_D28), (IEN | PTD | DIS | M0)) /*SDRC_D28*/\ + MUX_VAL(CP(SDRC_D29), (IEN | PTD | DIS | M0)) /*SDRC_D29*/\ + MUX_VAL(CP(SDRC_D30), (IEN | PTD | DIS | M0)) /*SDRC_D30*/\ + MUX_VAL(CP(SDRC_D31), (IEN | PTD | DIS | M0)) /*SDRC_D31*/\ + MUX_VAL(CP(SDRC_CLK), (IEN | PTD | DIS | M0)) /*SDRC_CLK*/\ + MUX_VAL(CP(SDRC_DQS0), (IEN | PTD | DIS | M0)) /*SDRC_DQS0*/\ + MUX_VAL(CP(SDRC_DQS1), (IEN | PTD | DIS | M0)) /*SDRC_DQS1*/\ + MUX_VAL(CP(SDRC_DQS2), (IEN | PTD | DIS | M0)) /*SDRC_DQS2*/\ + MUX_VAL(CP(SDRC_DQS3), (IEN | PTD | DIS | M0)) /*SDRC_DQS3*/\ + /*GPMC*/\ + MUX_VAL(CP(GPMC_A1), (IDIS | PTD | DIS | M0)) /*GPMC_A1*/\ + MUX_VAL(CP(GPMC_A2), (IDIS | PTD | DIS | M0)) /*GPMC_A2*/\ + MUX_VAL(CP(GPMC_A3), (IDIS | PTD | DIS | M0)) /*GPMC_A3*/\ + MUX_VAL(CP(GPMC_A4), (IDIS | PTD | DIS | M0)) /*GPMC_A4*/\ + MUX_VAL(CP(GPMC_A5), (IDIS | PTD | DIS | M0)) /*GPMC_A5*/\ + MUX_VAL(CP(GPMC_A6), (IDIS | PTD | DIS | M0)) /*GPMC_A6*/\ + MUX_VAL(CP(GPMC_A7), (IDIS | PTD | DIS | M0)) /*GPMC_A7*/\ + MUX_VAL(CP(GPMC_A8), (IDIS | PTD | DIS | M0)) /*GPMC_A8*/\ + MUX_VAL(CP(GPMC_A9), (IDIS | PTD | DIS | M0)) /*GPMC_A9*/\ + MUX_VAL(CP(GPMC_A10), (IDIS | PTD | DIS | M0)) /*GPMC_A10*/\ + MUX_VAL(CP(GPMC_D0), (IEN | PTD | DIS | M0)) /*GPMC_D0*/\ + MUX_VAL(CP(GPMC_D1), (IEN | PTD | DIS | M0)) /*GPMC_D1*/\ + MUX_VAL(CP(GPMC_D2), (IEN | PTD | DIS | M0)) /*GPMC_D2*/\ + MUX_VAL(CP(GPMC_D3), (IEN | PTD | DIS | M0)) /*GPMC_D3*/\ + MUX_VAL(CP(GPMC_D4), (IEN | PTD | DIS | M0)) /*GPMC_D4*/\ + MUX_VAL(CP(GPMC_D5), (IEN | PTD | DIS | M0)) /*GPMC_D5*/\ + MUX_VAL(CP(GPMC_D6), (IEN | PTD | DIS | M0)) /*GPMC_D6*/\ + MUX_VAL(CP(GPMC_D7), (IEN | PTD | DIS | M0)) /*GPMC_D7*/\ + MUX_VAL(CP(GPMC_D8), (IEN | PTD | DIS | M0)) /*GPMC_D8*/\ + MUX_VAL(CP(GPMC_D9), (IEN | PTD | DIS | M0)) /*GPMC_D9*/\ + MUX_VAL(CP(GPMC_D10), (IEN | PTD | DIS | M0)) /*GPMC_D10*/\ + MUX_VAL(CP(GPMC_D11), (IEN | PTD | DIS | M0)) /*GPMC_D11*/\ + MUX_VAL(CP(GPMC_D12), (IEN | PTD | DIS | M0)) /*GPMC_D12*/\ + MUX_VAL(CP(GPMC_D13), (IEN | PTD | DIS | M0)) /*GPMC_D13*/\ + MUX_VAL(CP(GPMC_D14), (IEN | PTD | DIS | M0)) /*GPMC_D14*/\ + MUX_VAL(CP(GPMC_D15), (IEN | PTD | DIS | M0)) /*GPMC_D15*/\ + MUX_VAL(CP(GPMC_NCS0), (IDIS | PTU | EN | M0)) /*GPMC_nCS0*/\ + MUX_VAL(CP(GPMC_NCS1), (IDIS | PTU | EN | M0)) /*GPMC_nCS1*/\ + MUX_VAL(CP(GPMC_NCS2), (IDIS | PTU | EN | M0)) /*GPMC_nCS2*/\ + MUX_VAL(CP(GPMC_NCS3), (IDIS | PTU | EN | M0)) /*GPMC_nCS3*/\ + MUX_VAL(CP(GPMC_NCS4), (IDIS | PTU | EN | M0)) /*GPMC_nCS4*/\ + MUX_VAL(CP(GPMC_NCS5), (IDIS | PTD | DIS | M0)) /*GPMC_nCS5*/\ + MUX_VAL(CP(GPMC_NCS6), (IEN | PTD | DIS | M1)) /*SYS_nDMA_REQ2*/\ + MUX_VAL(CP(GPMC_NCS7), (IEN | PTU | EN | M1)) /*SYS_nDMA_REQ3*/\ + MUX_VAL(CP(GPMC_NBE1), (IEN | PTD | DIS | M0)) /*GPMC_nBE1*/\ + MUX_VAL(CP(GPMC_WAIT2), (IEN | PTU | EN | M0)) /*GPMC_WAIT2*/\ + MUX_VAL(CP(GPMC_WAIT3), (IEN | PTU | EN | M0)) /*GPMC_WAIT3*/\ + MUX_VAL(CP(GPMC_CLK), (IEN | PTD | DIS | M4)) /*GPMC_CLK*/\ + MUX_VAL(CP(GPMC_NADV_ALE), (IDIS | PTD | DIS | M0)) /*GPMC_nADV_ALE*/\ + MUX_VAL(CP(GPMC_NOE), (IDIS | PTD | DIS | M0)) /*GPMC_nOE*/\ + MUX_VAL(CP(GPMC_NWE), (IDIS | PTD | DIS | M0)) /*GPMC_nWE*/\ + MUX_VAL(CP(GPMC_NBE0_CLE), (IDIS | PTD | DIS | M0)) /*GPMC_nBE0_CLE*/\ + MUX_VAL(CP(GPMC_NWP), (IEN | PTD | DIS | M0)) /*GPMC_nWP*/\ + MUX_VAL(CP(GPMC_WAIT0), (IEN | PTU | EN | M0)) /*GPMC_WAIT0*/\ + MUX_VAL(CP(GPMC_WAIT1), (IEN | PTU | EN | M0)) /*GPMC_WAIT1*/\ + /*CAMERA*/\ + MUX_VAL(CP(CAM_HS), (IEN | PTU | EN | M4)) /*CAM_HS HW0*/\ + MUX_VAL(CP(CAM_VS), (IEN | PTU | EN | M4)) /*CAM_VS HW1*/\ + MUX_VAL(CP(CAM_XCLKA), (IEN | PTU | EN | M4)) /*CAM_XCLKA HW2*/\ + MUX_VAL(CP(CAM_D0), (IEN | PTD | DIS | M4)) /*CAM_D0 DIN1*/\ + MUX_VAL(CP(CAM_D1), (IEN | PTD | DIS | M4)) /*CAM_D1 DIN2*/\ + MUX_VAL(CP(CAM_D2), (IDIS | PTD | DIS | M4)) /*CAM_D2, led_sm*/\ + MUX_VAL(CP(CAM_D3), (IDIS | PTD | DIS | M4)) /*CAM_D3, led1*/\ + MUX_VAL(CP(CAM_D4), (IDIS | PTD | DIS | M4)) /*CAM_D4, led2*/\ + MUX_VAL(CP(CAM_D5), (IDIS | PTD | DIS | M4)) /*CAM_D5, led3*/\ + MUX_VAL(CP(CAM_D6), (IEN | PTD | DIS | M4)) /*CAM_D6 sw_sm*/\ + MUX_VAL(CP(CAM_D7), (IEN | PTD | DIS | M4)) /*CAM_D7 DIN3*/\ + MUX_VAL(CP(CAM_D8), (IEN | PTD | DIS | M4)) /*CAM_D8 DIN4*/\ + MUX_VAL(CP(CAM_D9), (IEN | PTD | DIS | M4)) /*CAM_D9 DIN5*/\ + MUX_VAL(CP(CAM_D11), (IDIS | PTD | DIS | M4)) /*CAM_D11,usb2en*/\ + /*Audio Interface */\ + MUX_VAL(CP(MCBSP2_CLKX), (IDIS | PTD | DIS | M4)) /*McBSP2_CLKX wd_trigger*/\ + /*Expansion card */\ + MUX_VAL(CP(MMC1_CLK), (IDIS | PTU | EN | M0)) /*MMC1_CLK*/\ + MUX_VAL(CP(MMC1_CMD), (IEN | PTU | EN | M0)) /*MMC1_CMD*/\ + MUX_VAL(CP(MMC1_DAT0), (IEN | PTU | EN | M0)) /*MMC1_DAT0*/\ + MUX_VAL(CP(MMC1_DAT1), (IEN | PTU | EN | M0)) /*MMC1_DAT1*/\ + MUX_VAL(CP(MMC1_DAT2), (IEN | PTU | EN | M0)) /*MMC1_DAT2*/\ + MUX_VAL(CP(MMC1_DAT3), (IEN | PTU | EN | M0)) /*MMC1_DAT3*/\ + /*Wireless LAN */\ + MUX_VAL(CP(MMC2_CLK), (IEN | PTU | DIS | M4)) /*GPIO_130 eth_irq*/\ + /*Modem Interface */\ + MUX_VAL(CP(UART1_TX), (IDIS | PTD | DIS | M0)) /*UART1_TX*/\ + MUX_VAL(CP(UART1_RTS), (IDIS | PTD | DIS | M0)) /*GPIO_149*/ \ + MUX_VAL(CP(UART1_RX), (IEN | PTD | DIS | M0)) /*UART1_RX*/\ + MUX_VAL(CP(MCBSP4_CLKX), (IDIS | PTD | DIS | M0)) /*SSI1_DAT_RX*/\ + MUX_VAL(CP(MCBSP1_CLKR), (IEN | PTD | DIS | M0)) /*GPIO_156*/\ + MUX_VAL(CP(MCBSP1_FSR), (IDIS | PTU | DIS | M4)) /*GPIO_157 GPO1*/\ + MUX_VAL(CP(MCBSP1_DX), (IDIS | PTD | DIS | M4)) /*GPIO_158 GPO2*/\ + MUX_VAL(CP(MCBSP1_DR), (IDIS | PTD | DIS | M4)) /*GPIO_159 GPO3*/\ + MUX_VAL(CP(MCBSP_CLKS), (IDIS | PTD | DIS | M4)) /*McBSP_CLKS GPO4*/\ + MUX_VAL(CP(MCBSP1_FSX), (IDIS | PTD | DIS | M4)) /*GPIO_161 GPO5*/\ + MUX_VAL(CP(MCBSP1_CLKX), (IDIS | PTD | DIS | M4)) /*GPIO_162 GPO6*/\ + /*Serial Interface*/\ +/* MUX_VAL(CP(UART3_CTS_RCTX), (IDIS | PTD | DIS | M4)) *//*UART3_CTS_RCTX IIC_RES_18*/\ + MUX_VAL(CP(UART3_RX_IRRX), (IEN | PTD | DIS | M0)) /*UART3_RX_IRRX*/\ + MUX_VAL(CP(UART3_TX_IRTX), (IDIS | PTD | DIS | M0)) /*UART3_TX_IRTX*/\ + MUX_VAL(CP(HSUSB0_CLK), (IEN | PTD | DIS | M0)) /*HSUSB0_CLK*/\ + MUX_VAL(CP(HSUSB0_STP), (IDIS | PTU | EN | M0)) /*HSUSB0_STP*/\ + MUX_VAL(CP(HSUSB0_DIR), (IEN | PTD | DIS | M0)) /*HSUSB0_DIR*/\ + MUX_VAL(CP(HSUSB0_NXT), (IEN | PTD | DIS | M0)) /*HSUSB0_NXT*/\ + MUX_VAL(CP(HSUSB0_DATA0), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA0*/\ + MUX_VAL(CP(HSUSB0_DATA1), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA1*/\ + MUX_VAL(CP(HSUSB0_DATA2), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA2*/\ + MUX_VAL(CP(HSUSB0_DATA3), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA3*/\ + MUX_VAL(CP(HSUSB0_DATA4), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA4*/\ + MUX_VAL(CP(HSUSB0_DATA5), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA5*/\ + MUX_VAL(CP(HSUSB0_DATA6), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA6*/\ + MUX_VAL(CP(HSUSB0_DATA7), (IEN | PTD | DIS | M0)) /*HSUSB0_DATA7*/\ + MUX_VAL(CP(I2C1_SCL), (IEN | PTU | DIS | M0)) /*I2C1_SCL*/\ + MUX_VAL(CP(I2C1_SDA), (IEN | PTU | DIS | M0)) /*I2C1_SDA*/\ + MUX_VAL(CP(I2C2_SCL), (IEN | PTU | DIS | M0)) /*I2C2_SCL*/\ + MUX_VAL(CP(I2C2_SDA), (IEN | PTU | DIS | M0)) /*I2C2_SDA*/\ + MUX_VAL(CP(I2C3_SCL), (IEN | PTU | DIS | M0)) /*I2C3_SCL*/\ + MUX_VAL(CP(I2C3_SDA), (IEN | PTU | DIS | M0)) /*I2C3_SDA*/\ + MUX_VAL(CP(I2C4_SCL), (IEN | PTU | DIS | M0)) /*I2C4_SCL*/\ + MUX_VAL(CP(I2C4_SDA), (IEN | PTU | DIS | M0)) /*I2C4_SDA*/\ + /*Control and debug */\ + MUX_VAL(CP(SYS_32K), (IEN | PTD | DIS | M0)) /*SYS_32K*/\ + MUX_VAL(CP(SYS_BOOT0), (IEN | PTD | DIS | M0)) /*GPIO_2*/\ + MUX_VAL(CP(SYS_BOOT1), (IEN | PTD | DIS | M0)) /*GPIO_3*/\ + MUX_VAL(CP(SYS_BOOT2), (IEN | PTD | DIS | M0)) /*GPIO_4*/\ + MUX_VAL(CP(SYS_BOOT3), (IEN | PTD | DIS | M0)) /*GPIO_5*/\ + MUX_VAL(CP(SYS_BOOT4), (IEN | PTD | DIS | M0)) /*GPIO_6*/\ + MUX_VAL(CP(SYS_BOOT5), (IEN | PTD | DIS | M0)) /*GPIO_7*/\ + MUX_VAL(CP(SYS_BOOT6), (IDIS | PTD | DIS | M0)) /*GPIO_8*/ \ + MUX_VAL(CP(SYS_OFF_MODE), (IDIS | PTD | DIS | M0)) /*SYS_OFF_MODE*/\ + MUX_VAL(CP(SDRC_CKE0), (IDIS | PTU | EN | M0)) /*sdrc_cke0*/\ + MUX_VAL(CP(SDRC_CKE1), (IDIS | PTU | EN | M0)) /*sdrc_cke1*/ + + +#endif + + + diff --git a/configs/omap3_mws4_defconfig b/configs/omap3_mws4_defconfig new file mode 100644 index 0000000000..af0bdd1823 --- /dev/null +++ b/configs/omap3_mws4_defconfig @@ -0,0 +1,74 @@ +CONFIG_SYS_NAND_PAGE_SIZE=2048 +CONFIG_SYS_NAND_OOBSIZE=64 +CONFIG_ARM=y +CONFIG_ARCH_OMAP2PLUS=y +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_OFFSET=0x100000 +CONFIG_TARGET_OMAP3_MWS4=y +CONFIG_DEFAULT_DEVICE_TREE="omap3-mws4" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_NAND_BOOT=y +CONFIG_SD_BOOT=y +CONFIG_BOOTDELAY=3 +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_STOP_STR="q" +CONFIG_AUTOBOOT_KEYED_CTRLC=y +CONFIG_USE_PREBOOT=y +CONFIG_DEFAULT_FDT_FILE="omap3-mws4.dtb" +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SYS_PROMPT="MWS4 # " +CONFIG_CMD_ASKENV=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FS_UUID=y +CONFIG_CMD_UBI=y +# CONFIG_ISO_PARTITION is not set +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_NAND=y +CONFIG_USE_DEFAULT_ENV_FILE=y +CONFIG_DEFAULT_ENV_FILE="board/ultratronik/mws4/default.env" +CONFIG_VERSION_VARIABLE=y +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x82000000 +CONFIG_DM_MMC=y +CONFIG_MMC_OMAP_HS=y +CONFIG_CMD_PINMUX=y +CONFIG_DM_I2C=y +CONFIG_PINCTRL=y +CONFIG_MTD=y +CONFIG_SYS_NAND_USE_FLASH_BBT=y +# CONFIG_NAND_OMAP_GPMC_PREFETCH is not set +CONFIG_SYS_NAND_BUSWIDTH_16BIT=y +CONFIG_DM_ETH=y +CONFIG_SPI=y +CONFIG_PHY=y +CONFIG_USB_MUSB_TI=y +CONFIG_DM_SPI=y +CONFIG_OMAP3_SPI=y +CONFIG_USB=y +CONFIG_USB_MUSB_TI=y +CONFIG_DM_USB=y +CONFIG_OMAP_USB_PHY=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_OMAP3=y +CONFIG_USB_MUSB_HOST=y +CONFIG_USB_MUSB_GADGET=n +CONFIG_USB_MUSB_OMAP2PLUS=y +CONFIG_TWL4030_USB=y +CONFIG_USB_ETHER=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_VIDEO_OMAP3=y +CONFIG_BCH=y +CONFIG_SPL_OF_LIBFDT=y diff --git a/include/configs/omap3_mws4.h b/include/configs/omap3_mws4.h new file mode 100644 index 0000000000..1c0138a0a6 --- /dev/null +++ b/include/configs/omap3_mws4.h @@ -0,0 +1,100 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * (C) Copyright 2006-2008 + * Texas Instruments. + * Richard Woodruff r-woodruff2@ti.com + * Syed Mohammed Khasim x0khasim@ti.com + * + * Configuration settings for the TI OMAP3530 Beagle board. + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/ti_omap3_common.h> + +/* + * We are only ever GP parts and will utilize all of the "downloaded image" + * area in SRAM which starts at 0x40200000 and ends at 0x4020FFFF (64KB). + */ + +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG +#define CONFIG_REVISION_TAG + +#define CONFIG_CONS_INDEX 3 + +/* NAND */ +#if defined(CONFIG_MTD_RAW_NAND) +#define CONFIG_SYS_FLASH_BASE NAND_BASE +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW +//#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 +#define CONFIG_SYS_ENV_SECT_SIZE SZ_128K +/* NAND: SPL falcon mode configs */ +#if defined(CONFIG_SPL_OS_BOOT) +#define CONFIG_SYS_NAND_SPL_KERNEL_OFFS 0x2a0000 +#endif /* CONFIG_SPL_OS_BOOT */ +#endif /* CONFIG_MTD_RAW_NAND */ + +/* Enable Multi Bus support for I2C */ +#define CONFIG_I2C_MULTI_BUS + +/* DSS Support */ + +/* TWL4030 LED Support */ + +#define MEM_LAYOUT_ENV_SETTINGS \ + DEFAULT_LINUX_BOOT_ENV + +#define BOOTENV_DEV_LEGACY_MMC(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "setenv mmcdev " #instance "; " \ + "run mmcboot\0" +#define BOOTENV_DEV_NAME_LEGACY_MMC(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#if defined(CONFIG_MTD_RAW_NAND) + +#define BOOTENV_DEV_NAND(devtypeu, devtypel, instance) \ + "bootcmd_" #devtypel #instance "=" \ + "if test ${mtdids} = '' || test ${mtdparts} = '' ; then " \ + "echo NAND boot disabled: No mtdids and/or mtdparts; " \ + "else " \ + "run nandboot; " \ + "fi\0" +#define BOOTENV_DEV_NAME_NAND(devtypeu, devtypel, instance) \ + #devtypel #instance " " + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(LEGACY_MMC, legacy_mmc, 0) \ + func(UBIFS, ubifs, 0) \ + func(NAND, nand, 0) + +#else /* !CONFIG_MTD_RAW_NAND */ + +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 0) \ + func(LEGACY_MMC, legacy_mmc, 0) + +#endif /* CONFIG_MTD_RAW_NAND */ + +#include <config_distro_bootcmd.h> + +#define CONFIG_EXTRA_ENV_SETTINGS \ + MEM_LAYOUT_ENV_SETTINGS \ + "console=ttyO2,115200n8\0" \ + BOOTENV +#endif /* __CONFIG_H */
On Sun, May 08, 2022 at 05:47:58PM +0200, Marian Ulbricht wrote:
Am 08.05.22 um 16:21 schrieb Tom Rini:
On Sun, May 08, 2022 at 03:46:55PM +0200, Marian Ulbricht wrote:
mws4 is an arm based nuclear probe hardware used from german government to monitor nuclear activity
Signed-off-by: Marian Ulbricht ulbricht@innoroute.de
Thanks for the submission. Have you submitted the board dts files to upstream Linux? Also, please remove all of the commented out code in the board files, etc.
Hi, not yet, i started from bottom up: u-boot -> buildroot -> kernel
OK. We require the board dts itself to be submitted to the kernel first, as we keep that as an unchanged copy of the file in upstream and try and sync them down periodically.
[PATCH 1/1 v2] add support for mws4 board
mws4 is an arm based nuclear probe hardware used from german government to monitor nuclear activity
Signed-off-by: Marian Ulbricht ulbricht@innoroute.de
Changes v2:
- code cleanup
Note that there's a number of whitespace, etc, issues that checkpatch.pl reports. For the dts files, you can set that aside and follow what upstream says there, but the rest need to be addressed.
participants (2)
-
Marian Ulbricht -
Tom Rini