[U-Boot] [RESEND] [PATCH] arm: dts: Stratix10: Add QSPI node
Add QSPI device tree to Stratix 10. Sync from Linux Stratix 10 dts.
Tested on Stratix 10 SoC devkit. SOCFPGA_STRATIX10 # sf probe 0:0 SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com --- arch/arm/dts/socfpga_stratix10.dtsi | 15 +++++++++++++++ arch/arm/dts/socfpga_stratix10_socdk.dts | 21 +++++++++++++++++++++ 2 files changed, 36 insertions(+)
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index ee93725d64..9998bb1ba3 100644 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -391,5 +391,20 @@ resets = <&rst WATCHDOG3_RESET>; status = "disabled"; }; + + qspi: spi@ff8d2000 { + compatible = "cdns,qspi-nor"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0xff8d2000 0x100>, + <0xff900000 0x100000>; + interrupts = <0 3 4>; + cdns,fifo-depth = <128>; + cdns,fifo-width = <4>; + cdns,trigger-address = <0x00000000>; + bus-num = <0>; + status = "disabled"; + u-boot,dm-pre-reloc; + }; }; }; diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index c59b77d829..4c47415b51 100644 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -10,6 +10,7 @@
aliases { serial0 = &uart0; + spi0 = &qspi; };
chosen { @@ -87,6 +88,26 @@ smplsel = <0>; };
+&qspi { + status = "okay"; + + flash@0 { + u-boot,dm-pre-reloc; + #address-cells = <1>; + #size-cells = <1>; + compatible = "spi-flash"; + reg = <0>; /* chip select */ + spi-max-frequency = <50000000>; + + page-size = <256>; + block-size = <16>; /* 2^16, 64KB */ + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + }; +}; + &uart0 { status = "okay"; };
On 3/22/19 10:15 AM, Ley Foon Tan wrote:
Add QSPI device tree to Stratix 10. Sync from Linux Stratix 10 dts.
Tested on Stratix 10 SoC devkit. SOCFPGA_STRATIX10 # sf probe 0:0 SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
arch/arm/dts/socfpga_stratix10.dtsi | 15 +++++++++++++++ arch/arm/dts/socfpga_stratix10_socdk.dts | 21 +++++++++++++++++++++ 2 files changed, 36 insertions(+)
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index ee93725d64..9998bb1ba3 100644 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -391,5 +391,20 @@ resets = <&rst WATCHDOG3_RESET>; status = "disabled"; };
qspi: spi@ff8d2000 {compatible = "cdns,qspi-nor";#address-cells = <1>;#size-cells = <0>;reg = <0xff8d2000 0x100>,<0xff900000 0x100000>;interrupts = <0 3 4>;cdns,fifo-depth = <128>;cdns,fifo-width = <4>;cdns,trigger-address = <0x00000000>;bus-num = <0>;status = "disabled";u-boot,dm-pre-reloc;};}; diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index c59b77d829..4c47415b51 100644 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -10,6 +10,7 @@
aliases { serial0 = &uart0;
spi0 = &qspi;};
chosen {
@@ -87,6 +88,26 @@ smplsel = <0>; };
+&qspi {
- status = "okay";
- flash@0 {
u-boot,dm-pre-reloc;#address-cells = <1>;#size-cells = <1>;compatible = "spi-flash";reg = <0>; /* chip select */spi-max-frequency = <50000000>;
The other SoCFPGAs use 100 MHz for the CQSPI , why would S10 use 50 MHz ?
page-size = <256>;block-size = <16>; /* 2^16, 64KB */cdns,tshsl-ns = <50>;cdns,tsd2d-ns = <50>;cdns,tchsh-ns = <4>;cdns,tslch-ns = <4>;- };
+};
&uart0 { status = "okay"; };
On Fri, Mar 22, 2019 at 12:59 PM Marek Vasut marex@denx.de wrote:
On 3/22/19 10:15 AM, Ley Foon Tan wrote:
Add QSPI device tree to Stratix 10. Sync from Linux Stratix 10 dts.
Tested on Stratix 10 SoC devkit. SOCFPGA_STRATIX10 # sf probe 0:0 SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
arch/arm/dts/socfpga_stratix10.dtsi | 15 +++++++++++++++ arch/arm/dts/socfpga_stratix10_socdk.dts | 21 +++++++++++++++++++++ 2 files changed, 36 insertions(+)
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index ee93725d64..9998bb1ba3 100644 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -391,5 +391,20 @@ resets = <&rst WATCHDOG3_RESET>; status = "disabled"; };
qspi: spi@ff8d2000 {compatible = "cdns,qspi-nor";#address-cells = <1>;#size-cells = <0>;reg = <0xff8d2000 0x100>,<0xff900000 0x100000>;interrupts = <0 3 4>;cdns,fifo-depth = <128>;cdns,fifo-width = <4>;cdns,trigger-address = <0x00000000>;bus-num = <0>;status = "disabled";u-boot,dm-pre-reloc;}; };}; diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index c59b77d829..4c47415b51 100644 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -10,6 +10,7 @@
aliases { serial0 = &uart0;
spi0 = &qspi; }; chosen {@@ -87,6 +88,26 @@ smplsel = <0>; };
+&qspi {
status = "okay";flash@0 {u-boot,dm-pre-reloc;#address-cells = <1>;#size-cells = <1>;compatible = "spi-flash";reg = <0>; /* chip select */spi-max-frequency = <50000000>;The other SoCFPGAs use 100 MHz for the CQSPI , why would S10 use 50 MHz ?
I wonder who, when and why they were switched to 100 MHz, as they were at 50 MHz in the past as well, or am I wrong?
Regards, Simon
page-size = <256>;block-size = <16>; /* 2^16, 64KB */cdns,tshsl-ns = <50>;cdns,tsd2d-ns = <50>;cdns,tchsh-ns = <4>;cdns,tslch-ns = <4>;};+};
&uart0 { status = "okay"; };
-- Best regards, Marek Vasut
On 3/22/19 1:06 PM, Simon Goldschmidt wrote:
On Fri, Mar 22, 2019 at 12:59 PM Marek Vasut marex@denx.de wrote:
On 3/22/19 10:15 AM, Ley Foon Tan wrote:
Add QSPI device tree to Stratix 10. Sync from Linux Stratix 10 dts.
Tested on Stratix 10 SoC devkit. SOCFPGA_STRATIX10 # sf probe 0:0 SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
arch/arm/dts/socfpga_stratix10.dtsi | 15 +++++++++++++++ arch/arm/dts/socfpga_stratix10_socdk.dts | 21 +++++++++++++++++++++ 2 files changed, 36 insertions(+)
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index ee93725d64..9998bb1ba3 100644 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -391,5 +391,20 @@ resets = <&rst WATCHDOG3_RESET>; status = "disabled"; };
qspi: spi@ff8d2000 {compatible = "cdns,qspi-nor";#address-cells = <1>;#size-cells = <0>;reg = <0xff8d2000 0x100>,<0xff900000 0x100000>;interrupts = <0 3 4>;cdns,fifo-depth = <128>;cdns,fifo-width = <4>;cdns,trigger-address = <0x00000000>;bus-num = <0>;status = "disabled";u-boot,dm-pre-reloc;}; };}; diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index c59b77d829..4c47415b51 100644 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -10,6 +10,7 @@
aliases { serial0 = &uart0;
spi0 = &qspi; }; chosen {@@ -87,6 +88,26 @@ smplsel = <0>; };
+&qspi {
status = "okay";flash@0 {u-boot,dm-pre-reloc;#address-cells = <1>;#size-cells = <1>;compatible = "spi-flash";reg = <0>; /* chip select */spi-max-frequency = <50000000>;The other SoCFPGAs use 100 MHz for the CQSPI , why would S10 use 50 MHz ?
I wonder who, when and why they were switched to 100 MHz, as they were at 50 MHz in the past as well, or am I wrong?
I was under the impression they were 100 since the beginning of times. Where did you find 50 MHz ?
On Fri, Mar 22, 2019 at 1:10 PM Marek Vasut marex@denx.de wrote:
On 3/22/19 1:06 PM, Simon Goldschmidt wrote:
On Fri, Mar 22, 2019 at 12:59 PM Marek Vasut marex@denx.de wrote:
On 3/22/19 10:15 AM, Ley Foon Tan wrote:
Add QSPI device tree to Stratix 10. Sync from Linux Stratix 10 dts.
Tested on Stratix 10 SoC devkit. SOCFPGA_STRATIX10 # sf probe 0:0 SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
arch/arm/dts/socfpga_stratix10.dtsi | 15 +++++++++++++++ arch/arm/dts/socfpga_stratix10_socdk.dts | 21 +++++++++++++++++++++ 2 files changed, 36 insertions(+)
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index ee93725d64..9998bb1ba3 100644 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -391,5 +391,20 @@ resets = <&rst WATCHDOG3_RESET>; status = "disabled"; };
qspi: spi@ff8d2000 {compatible = "cdns,qspi-nor";#address-cells = <1>;#size-cells = <0>;reg = <0xff8d2000 0x100>,<0xff900000 0x100000>;interrupts = <0 3 4>;cdns,fifo-depth = <128>;cdns,fifo-width = <4>;cdns,trigger-address = <0x00000000>;bus-num = <0>;status = "disabled";u-boot,dm-pre-reloc;}; };}; diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index c59b77d829..4c47415b51 100644 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -10,6 +10,7 @@
aliases { serial0 = &uart0;
spi0 = &qspi; }; chosen {@@ -87,6 +88,26 @@ smplsel = <0>; };
+&qspi {
status = "okay";flash@0 {u-boot,dm-pre-reloc;#address-cells = <1>;#size-cells = <1>;compatible = "spi-flash";reg = <0>; /* chip select */spi-max-frequency = <50000000>;The other SoCFPGAs use 100 MHz for the CQSPI , why would S10 use 50 MHz ?
I wonder who, when and why they were switched to 100 MHz, as they were at 50 MHz in the past as well, or am I wrong?
I was under the impression they were 100 since the beginning of times. Where did you find 50 MHz ?
Good question, let me dig on that.
Regards, Simon
On Fri, Mar 22, 2019 at 1:18 PM Simon Goldschmidt simon.k.r.goldschmidt@gmail.com wrote:
On Fri, Mar 22, 2019 at 1:10 PM Marek Vasut marex@denx.de wrote:
On 3/22/19 1:06 PM, Simon Goldschmidt wrote:
On Fri, Mar 22, 2019 at 12:59 PM Marek Vasut marex@denx.de wrote:
On 3/22/19 10:15 AM, Ley Foon Tan wrote:
Add QSPI device tree to Stratix 10. Sync from Linux Stratix 10 dts.
Tested on Stratix 10 SoC devkit. SOCFPGA_STRATIX10 # sf probe 0:0 SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
arch/arm/dts/socfpga_stratix10.dtsi | 15 +++++++++++++++ arch/arm/dts/socfpga_stratix10_socdk.dts | 21 +++++++++++++++++++++ 2 files changed, 36 insertions(+)
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index ee93725d64..9998bb1ba3 100644 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -391,5 +391,20 @@ resets = <&rst WATCHDOG3_RESET>; status = "disabled"; };
qspi: spi@ff8d2000 {compatible = "cdns,qspi-nor";#address-cells = <1>;#size-cells = <0>;reg = <0xff8d2000 0x100>,<0xff900000 0x100000>;interrupts = <0 3 4>;cdns,fifo-depth = <128>;cdns,fifo-width = <4>;cdns,trigger-address = <0x00000000>;bus-num = <0>;status = "disabled";u-boot,dm-pre-reloc;}; };}; diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index c59b77d829..4c47415b51 100644 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -10,6 +10,7 @@
aliases { serial0 = &uart0;
spi0 = &qspi; }; chosen {@@ -87,6 +88,26 @@ smplsel = <0>; };
+&qspi {
status = "okay";flash@0 {u-boot,dm-pre-reloc;#address-cells = <1>;#size-cells = <1>;compatible = "spi-flash";reg = <0>; /* chip select */spi-max-frequency = <50000000>;The other SoCFPGAs use 100 MHz for the CQSPI , why would S10 use 50 MHz ?
I wonder who, when and why they were switched to 100 MHz, as they were at 50 MHz in the past as well, or am I wrong?
I was under the impression they were 100 since the beginning of times. Where did you find 50 MHz ?
Good question, let me dig on that.
Some boards were at 50 MHz before I merged the dt files from Linux: https://github.com/u-boot/u-boot/commit/c402e8170245a0ca2b9398185638b349eeff...
In contrast to the U-Boot dts, the Linux dts for e.g. the socrates board has been at 100 MHz from the beginning.
I don't know if that is due to a limitation of the flash chips on those boards or if it has been an error when reading those specs...
Regards, Simon
On 3/22/19 1:27 PM, Simon Goldschmidt wrote:
On Fri, Mar 22, 2019 at 1:18 PM Simon Goldschmidt simon.k.r.goldschmidt@gmail.com wrote:
On Fri, Mar 22, 2019 at 1:10 PM Marek Vasut marex@denx.de wrote:
On 3/22/19 1:06 PM, Simon Goldschmidt wrote:
On Fri, Mar 22, 2019 at 12:59 PM Marek Vasut marex@denx.de wrote:
On 3/22/19 10:15 AM, Ley Foon Tan wrote:
Add QSPI device tree to Stratix 10. Sync from Linux Stratix 10 dts.
Tested on Stratix 10 SoC devkit. SOCFPGA_STRATIX10 # sf probe 0:0 SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
arch/arm/dts/socfpga_stratix10.dtsi | 15 +++++++++++++++ arch/arm/dts/socfpga_stratix10_socdk.dts | 21 +++++++++++++++++++++ 2 files changed, 36 insertions(+)
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index ee93725d64..9998bb1ba3 100644 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -391,5 +391,20 @@ resets = <&rst WATCHDOG3_RESET>; status = "disabled"; };
qspi: spi@ff8d2000 {compatible = "cdns,qspi-nor";#address-cells = <1>;#size-cells = <0>;reg = <0xff8d2000 0x100>,<0xff900000 0x100000>;interrupts = <0 3 4>;cdns,fifo-depth = <128>;cdns,fifo-width = <4>;cdns,trigger-address = <0x00000000>;bus-num = <0>;status = "disabled";u-boot,dm-pre-reloc;}; };}; diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index c59b77d829..4c47415b51 100644 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -10,6 +10,7 @@
aliases { serial0 = &uart0;
spi0 = &qspi; }; chosen {@@ -87,6 +88,26 @@ smplsel = <0>; };
+&qspi {
status = "okay";flash@0 {u-boot,dm-pre-reloc;#address-cells = <1>;#size-cells = <1>;compatible = "spi-flash";reg = <0>; /* chip select */spi-max-frequency = <50000000>;The other SoCFPGAs use 100 MHz for the CQSPI , why would S10 use 50 MHz ?
I wonder who, when and why they were switched to 100 MHz, as they were at 50 MHz in the past as well, or am I wrong?
I was under the impression they were 100 since the beginning of times. Where did you find 50 MHz ?
Good question, let me dig on that.
Some boards were at 50 MHz before I merged the dt files from Linux: https://github.com/u-boot/u-boot/commit/c402e8170245a0ca2b9398185638b349eeff...
In contrast to the U-Boot dts, the Linux dts for e.g. the socrates board has been at 100 MHz from the beginning.
I don't know if that is due to a limitation of the flash chips on those boards or if it has been an error when reading those specs...
So it's a per-board thing then ? Let's see what Ley has to say about the S10 then .
Marek Vasut marex@denx.de schrieb am Fr., 22. März 2019, 13:35:
On 3/22/19 1:27 PM, Simon Goldschmidt wrote:
On Fri, Mar 22, 2019 at 1:18 PM Simon Goldschmidt simon.k.r.goldschmidt@gmail.com wrote:
On Fri, Mar 22, 2019 at 1:10 PM Marek Vasut marex@denx.de wrote:
On 3/22/19 1:06 PM, Simon Goldschmidt wrote:
On Fri, Mar 22, 2019 at 12:59 PM Marek Vasut marex@denx.de wrote:
On 3/22/19 10:15 AM, Ley Foon Tan wrote: > Add QSPI device tree to Stratix 10. > Sync from Linux Stratix 10 dts. > > Tested on Stratix 10 SoC devkit. > SOCFPGA_STRATIX10 # sf probe 0:0 > SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB,
total 256 MiB
> > Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com > --- > arch/arm/dts/socfpga_stratix10.dtsi | 15 +++++++++++++++ > arch/arm/dts/socfpga_stratix10_socdk.dts | 21 +++++++++++++++++++++ > 2 files changed, 36 insertions(+) > > diff --git a/arch/arm/dts/socfpga_stratix10.dtsi
b/arch/arm/dts/socfpga_stratix10.dtsi
> index ee93725d64..9998bb1ba3 100644 > --- a/arch/arm/dts/socfpga_stratix10.dtsi > +++ b/arch/arm/dts/socfpga_stratix10.dtsi > @@ -391,5 +391,20 @@ > resets = <&rst WATCHDOG3_RESET>; > status = "disabled"; > }; > + > + qspi: spi@ff8d2000 { > + compatible = "cdns,qspi-nor"; > + #address-cells = <1>; > + #size-cells = <0>; > + reg = <0xff8d2000 0x100>, > + <0xff900000 0x100000>; > + interrupts = <0 3 4>; > + cdns,fifo-depth = <128>; > + cdns,fifo-width = <4>; > + cdns,trigger-address = <0x00000000>; > + bus-num = <0>; > + status = "disabled"; > + u-boot,dm-pre-reloc; > + }; > }; > }; > diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts
b/arch/arm/dts/socfpga_stratix10_socdk.dts
> index c59b77d829..4c47415b51 100644 > --- a/arch/arm/dts/socfpga_stratix10_socdk.dts > +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts > @@ -10,6 +10,7 @@ > > aliases { > serial0 = &uart0; > + spi0 = &qspi; > }; > > chosen { > @@ -87,6 +88,26 @@ > smplsel = <0>; > }; > > +&qspi { > + status = "okay"; > + > + flash@0 { > + u-boot,dm-pre-reloc; > + #address-cells = <1>; > + #size-cells = <1>; > + compatible = "spi-flash"; > + reg = <0>; /* chip select */ > + spi-max-frequency = <50000000>;
The other SoCFPGAs use 100 MHz for the CQSPI , why would S10 use 50
MHz ?
I wonder who, when and why they were switched to 100 MHz, as they
were at 50 MHz
in the past as well, or am I wrong?
I was under the impression they were 100 since the beginning of times. Where did you find 50 MHz ?
Good question, let me dig on that.
Some boards were at 50 MHz before I merged the dt files from Linux:
https://github.com/u-boot/u-boot/commit/c402e8170245a0ca2b9398185638b349eeff...
In contrast to the U-Boot dts, the Linux dts for e.g. the socrates board has been at 100 MHz from the beginning.
I don't know if that is due to a limitation of the flash chips on those boards or if it has been an error when reading those specs...
So it's a per-board thing then ? Let's see what Ley has to say about the S10 then .
From a devicetree point of view, it's a per-board thing. And it describes
the flash chip, so yes, board specific. But it still seemed inconsistent.
Regards, Simon
On Fri, Mar 22, 2019 at 8:42 PM Simon Goldschmidt simon.k.r.goldschmidt@gmail.com wrote:
Marek Vasut marex@denx.de schrieb am Fr., 22. März 2019, 13:35:
On 3/22/19 1:27 PM, Simon Goldschmidt wrote:
On Fri, Mar 22, 2019 at 1:18 PM Simon Goldschmidt simon.k.r.goldschmidt@gmail.com wrote:
On Fri, Mar 22, 2019 at 1:10 PM Marek Vasut marex@denx.de wrote:
On 3/22/19 1:06 PM, Simon Goldschmidt wrote:
On Fri, Mar 22, 2019 at 12:59 PM Marek Vasut marex@denx.de wrote: > > On 3/22/19 10:15 AM, Ley Foon Tan wrote: >> Add QSPI device tree to Stratix 10. >> Sync from Linux Stratix 10 dts. >> >> Tested on Stratix 10 SoC devkit. >> SOCFPGA_STRATIX10 # sf probe 0:0 >> SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB,
total 256 MiB
>> >> Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com >> --- >> arch/arm/dts/socfpga_stratix10.dtsi | 15 +++++++++++++++ >> arch/arm/dts/socfpga_stratix10_socdk.dts | 21 +++++++++++++++++++++ >> 2 files changed, 36 insertions(+) >> >> diff --git a/arch/arm/dts/socfpga_stratix10.dtsi
b/arch/arm/dts/socfpga_stratix10.dtsi
>> index ee93725d64..9998bb1ba3 100644 >> --- a/arch/arm/dts/socfpga_stratix10.dtsi >> +++ b/arch/arm/dts/socfpga_stratix10.dtsi >> @@ -391,5 +391,20 @@ >> resets = <&rst WATCHDOG3_RESET>; >> status = "disabled"; >> }; >> + >> + qspi: spi@ff8d2000 { >> + compatible = "cdns,qspi-nor"; >> + #address-cells = <1>; >> + #size-cells = <0>; >> + reg = <0xff8d2000 0x100>, >> + <0xff900000 0x100000>; >> + interrupts = <0 3 4>; >> + cdns,fifo-depth = <128>; >> + cdns,fifo-width = <4>; >> + cdns,trigger-address = <0x00000000>; >> + bus-num = <0>; >> + status = "disabled"; >> + u-boot,dm-pre-reloc; >> + }; >> }; >> }; >> diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts
b/arch/arm/dts/socfpga_stratix10_socdk.dts
>> index c59b77d829..4c47415b51 100644 >> --- a/arch/arm/dts/socfpga_stratix10_socdk.dts >> +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts >> @@ -10,6 +10,7 @@ >> >> aliases { >> serial0 = &uart0; >> + spi0 = &qspi; >> }; >> >> chosen { >> @@ -87,6 +88,26 @@ >> smplsel = <0>; >> }; >> >> +&qspi { >> + status = "okay"; >> + >> + flash@0 { >> + u-boot,dm-pre-reloc; >> + #address-cells = <1>; >> + #size-cells = <1>; >> + compatible = "spi-flash"; >> + reg = <0>; /* chip select */ >> + spi-max-frequency = <50000000>; > > The other SoCFPGAs use 100 MHz for the CQSPI , why would S10 use 50
MHz ?
I wonder who, when and why they were switched to 100 MHz, as they
were at 50 MHz
in the past as well, or am I wrong?
I was under the impression they were 100 since the beginning of times. Where did you find 50 MHz ?
Good question, let me dig on that.
Some boards were at 50 MHz before I merged the dt files from Linux:
https://github.com/u-boot/u-boot/commit/c402e8170245a0ca2b9398185638b349eeff...
In contrast to the U-Boot dts, the Linux dts for e.g. the socrates board has been at 100 MHz from the beginning.
I don't know if that is due to a limitation of the flash chips on those boards or if it has been an error when reading those specs...
So it's a per-board thing then ? Let's see what Ley has to say about the S10 then .
From a devicetree point of view, it's a per-board thing. And it describes the flash chip, so yes, board specific. But it still seemed inconsistent.
It should be 100MHz. QSPI reference clock is 400MHz. SPI flash clock can up to 100MHz.
Dinh, Linux dts need to update this too. Please take note.
Regards
Ley Foon
On Fri, Mar 22, 2019 at 10:15 AM Ley Foon Tan ley.foon.tan@intel.com wrote:
Add QSPI device tree to Stratix 10. Sync from Linux Stratix 10 dts.
Tested on Stratix 10 SoC devkit. SOCFPGA_STRATIX10 # sf probe 0:0 SF: Detected mt25qu02g with page size 256 Bytes, erase size 64 KiB, total 256 MiB
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com
arch/arm/dts/socfpga_stratix10.dtsi | 15 +++++++++++++++ arch/arm/dts/socfpga_stratix10_socdk.dts | 21 +++++++++++++++++++++ 2 files changed, 36 insertions(+)
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index ee93725d64..9998bb1ba3 100644 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -391,5 +391,20 @@ resets = <&rst WATCHDOG3_RESET>; status = "disabled"; };
qspi: spi@ff8d2000 {compatible = "cdns,qspi-nor";#address-cells = <1>;#size-cells = <0>;reg = <0xff8d2000 0x100>,<0xff900000 0x100000>;interrupts = <0 3 4>;cdns,fifo-depth = <128>;cdns,fifo-width = <4>;cdns,trigger-address = <0x00000000>;bus-num = <0>;status = "disabled";u-boot,dm-pre-reloc;}; };}; diff --git a/arch/arm/dts/socfpga_stratix10_socdk.dts b/arch/arm/dts/socfpga_stratix10_socdk.dts index c59b77d829..4c47415b51 100644 --- a/arch/arm/dts/socfpga_stratix10_socdk.dts +++ b/arch/arm/dts/socfpga_stratix10_socdk.dts @@ -10,6 +10,7 @@
aliases { serial0 = &uart0;
spi0 = &qspi; }; chosen {@@ -87,6 +88,26 @@ smplsel = <0>; };
+&qspi {
status = "okay";flash@0 {u-boot,dm-pre-reloc;#address-cells = <1>;#size-cells = <1>;compatible = "spi-flash";
"jedec,spi-nor", see my comment to in the other thread.
reg = <0>; /* chip select */spi-max-frequency = <50000000>;
This has changed to the one sent 10 minutes ago, so it should be a v2, right?
page-size = <256>;block-size = <16>; /* 2^16, 64KB */cdns,tshsl-ns = <50>;cdns,tsd2d-ns = <50>;cdns,tchsh-ns = <4>;cdns,tslch-ns = <4>;};+};
&uart0 { status = "okay"; }; -- 2.19.0
participants (4)
-
Ley Foon Tan -
Ley Foon Tan -
Marek Vasut -
Simon Goldschmidt