[U-Boot] [PATCH 1/6] x86: Support machines with >4GB of RAM
Some systems have more than 4GB of RAM. U-Boot can only place things below 4GB so any memory above that should not be used. Ignore any such memory so that the memory size will not exceed the maximum.
This prevents gd->ram_size exceeding 4GB which causes problems for PCI devices which use DMA.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/x86/cpu/coreboot/sdram.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index e98a230..9c3ab81 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -90,7 +90,8 @@ int dram_init(void) struct memrange *memrange = &lib_sysinfo.memrange[i]; unsigned long long end = memrange->base + memrange->size;
- if (memrange->type == CB_MEM_RAM && end > ram_size) + if (memrange->type == CB_MEM_RAM && end > ram_size && + memrange->base < (1ULL << 32)) ram_size = end; } gd->ram_size = ram_size; @@ -108,7 +109,8 @@ void dram_init_banksize(void) for (i = 0, j = 0; i < lib_sysinfo.n_memranges; i++) { struct memrange *memrange = &lib_sysinfo.memrange[i];
- if (memrange->type == CB_MEM_RAM) { + if (memrange->type == CB_MEM_RAM && + memrange->base < (1ULL << 32)) { gd->bd->bi_dram[j].start = memrange->base; gd->bd->bi_dram[j].size = memrange->size; j++;
At present a VGA console assumes a keyboard unless a CONFIG option is set. This difference can be dealt with by a device tree option, allowing boards that are otherwise the same to use the same configuration.
Signed-off-by: Simon Glass sjg@chromium.org ---
doc/README.fdt-control | 16 ++++++++++++++++ drivers/video/cfb_console.c | 29 +++++++++++++++++++---------- 2 files changed, 35 insertions(+), 10 deletions(-)
diff --git a/doc/README.fdt-control b/doc/README.fdt-control index d8fe4a8..e6d5ed0 100644 --- a/doc/README.fdt-control +++ b/doc/README.fdt-control @@ -171,6 +171,22 @@ After board configuration is done, fdt supported u-boot can be build in two ways $ make DEVICE_TREE=<dts-file-name>
+Configuration Options +--------------------- + +A number of run-time configuration options are provided in the /config node +of the control device tree. You can access these using fdtdec_get_config_int(), +fdtdec_get_config_bool() and fdtdec_get_config_string(). + +Available options are: + +silent-console + If present and non-zero, the console is silenced by default on boot. + +no-keyboard + Tells U-Boot not to expect an attached keyboard with a VGA console + + Limitations -----------
diff --git a/drivers/video/cfb_console.c b/drivers/video/cfb_console.c index a81affa..fcaaa7f 100644 --- a/drivers/video/cfb_console.c +++ b/drivers/video/cfb_console.c @@ -87,6 +87,7 @@ */
#include <common.h> +#include <fdtdec.h> #include <version.h> #include <malloc.h> #include <linux/compiler.h> @@ -2251,6 +2252,7 @@ int drv_video_init(void) { int skip_dev_init; struct stdio_dev console_dev; + bool have_keyboard;
/* Check if video initialization should be skipped */ if (board_video_skip()) @@ -2262,11 +2264,18 @@ int drv_video_init(void) if (board_cfb_skip()) return 0;
-#if !defined(CONFIG_VGA_AS_SINGLE_DEVICE) - debug("KBD: Keyboard init ...\n"); - skip_dev_init |= (VIDEO_KBD_INIT_FCT == -1); +#if defined(CONFIG_VGA_AS_SINGLE_DEVICE) + have_keyboard = false; +#elif defined(CONFIG_OF_CONTROL) + have_keyboard = !fdtdec_get_config_bool(gd->fdt_blob, + "u-boot,no-keyboard"); +#else + have_keyboard = true; #endif - + if (have_keyboard) { + debug("KBD: Keyboard init ...\n"); + skip_dev_init |= (VIDEO_KBD_INIT_FCT == -1); + } if (skip_dev_init) return 0;
@@ -2278,12 +2287,12 @@ int drv_video_init(void) console_dev.putc = video_putc; /* 'putc' function */ console_dev.puts = video_puts; /* 'puts' function */
-#if !defined(CONFIG_VGA_AS_SINGLE_DEVICE) - /* Also init console device */ - console_dev.flags |= DEV_FLAGS_INPUT; - console_dev.tstc = VIDEO_TSTC_FCT; /* 'tstc' function */ - console_dev.getc = VIDEO_GETC_FCT; /* 'getc' function */ -#endif /* CONFIG_VGA_AS_SINGLE_DEVICE */ + if (have_keyboard) { + /* Also init console device */ + console_dev.flags |= DEV_FLAGS_INPUT; + console_dev.tstc = VIDEO_TSTC_FCT; /* 'tstc' function */ + console_dev.getc = VIDEO_GETC_FCT; /* 'getc' function */ + }
if (stdio_register(&console_dev) != 0) return 0;
Hi Simon,
On Tue, 10 Feb 2015 18:59:49 -0700 Simon Glass sjg@chromium.org wrote:
At present a VGA console assumes a keyboard unless a CONFIG option is set. This difference can be dealt with by a device tree option, allowing boards that are otherwise the same to use the same configuration.
Signed-off-by: Simon Glass sjg@chromium.org
Acked-by: Anatolij Gustschin agust@denx.de
Add Lynxpoint to the driver so that the Asus Chromebox can be supported.
Signed-off-by: Simon Glass sjg@chromium.org ---
drivers/spi/ich.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 194e882..9848e0b 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -185,7 +185,8 @@ static int get_ich_version(uint16_t device_id) device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) || - device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC) + device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC || + device_id == PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC) return 9;
return 0;
On 11 February 2015 at 07:29, Simon Glass sjg@chromium.org wrote:
Add Lynxpoint to the driver so that the Asus Chromebox can be supported.
Signed-off-by: Simon Glass sjg@chromium.org
drivers/spi/ich.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 194e882..9848e0b 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -185,7 +185,8 @@ static int get_ich_version(uint16_t device_id) device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) ||
device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)
device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC ||device_id == PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC) return 9; return 0;-- 2.2.0.rc0.207.ga3a616c
Reviewed-by: Jagannadha Sutradharudu Teki jagannadh.teki@gmail.com
thanks!
Hi Simon,
On Wed, Feb 11, 2015 at 9:59 AM, Simon Glass sjg@chromium.org wrote:
Add Lynxpoint to the driver so that the Asus Chromebox can be supported.
Signed-off-by: Simon Glass sjg@chromium.org
drivers/spi/ich.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 194e882..9848e0b 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -185,7 +185,8 @@ static int get_ich_version(uint16_t device_id) device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) ||
device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)
device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC ||device_id == PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC)
Where is PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC defined?
return 9; return 0;--
Regards, Bin
On Wed, Feb 25, 2015 at 3:11 PM, Bin Meng bmeng.cn@gmail.com wrote:
Hi Simon,
On Wed, Feb 11, 2015 at 9:59 AM, Simon Glass sjg@chromium.org wrote:
Add Lynxpoint to the driver so that the Asus Chromebox can be supported.
Signed-off-by: Simon Glass sjg@chromium.org
drivers/spi/ich.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/spi/ich.c b/drivers/spi/ich.c index 194e882..9848e0b 100644 --- a/drivers/spi/ich.c +++ b/drivers/spi/ich.c @@ -185,7 +185,8 @@ static int get_ich_version(uint16_t device_id) device_id <= PCI_DEVICE_ID_INTEL_COUGARPOINT_LPC_MAX) || (device_id >= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MIN && device_id <= PCI_DEVICE_ID_INTEL_PANTHERPOINT_LPC_MAX) ||
device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC)
device_id == PCI_DEVICE_ID_INTEL_VALLEYVIEW_LPC ||device_id == PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC)Where is PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC defined?
Ah, I see it in the patch#5 in this series!
return 9; return 0;--
Regards, Bin
Since Chromebooks mostly have similar configuration, put it in a common file.
Signed-off-by: Simon Glass sjg@chromium.org ---
include/configs/chromebook_link.h | 61 +---------------------------------- include/configs/x86-chromebook.h | 68 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+), 60 deletions(-) create mode 100644 include/configs/x86-chromebook.h
diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index 7b460e8..5265787 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -14,65 +14,6 @@ #define __CONFIG_H
#include <configs/x86-common.h> - - -#define CONFIG_SYS_MONITOR_LEN (1 << 20) - -#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_MISC_INIT_R - -#define CONFIG_NR_DRAM_BANKS 8 -#define CONFIG_X86_MRC_ADDR 0xfffa0000 -#define CONFIG_CACHE_MRC_SIZE_KB 512 - -#define CONFIG_X86_SERIAL - -#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \ - PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ - {PCI_VENDOR_ID_INTEL, \ - PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \ - {PCI_VENDOR_ID_INTEL, \ - PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \ - {PCI_VENDOR_ID_INTEL, \ - PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE} - -#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin -#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 - -#define CONFIG_PCI_MEM_BUS 0xe0000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000 - -#define CONFIG_PCI_PREF_BUS 0xd0000000 -#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS -#define CONFIG_PCI_PREF_SIZE 0x10000000 - -#define CONFIG_PCI_IO_BUS 0x1000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0xefff - -#define CONFIG_SYS_EARLY_PCI_INIT -#define CONFIG_PCI_PNP - -#define CONFIG_BIOSEMU -#define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO - -#define CONFIG_CROS_EC -#define CONFIG_CROS_EC_LPC -#define CONFIG_CMD_CROS_EC -#define CONFIG_ARCH_EARLY_INIT_R - -#undef CONFIG_ENV_IS_NOWHERE -#undef CONFIG_ENV_SIZE -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x003f8000 - -#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ - "stdout=vga,serial\0" \ - "stderr=vga,serial\0" +#include <configs/x86-chromebook.h>
#endif /* __CONFIG_H */ diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h new file mode 100644 index 0000000..b6a76fe --- /dev/null +++ b/include/configs/x86-chromebook.h @@ -0,0 +1,68 @@ +/* + * + * Copyright (c) 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _X86_CHROMEBOOK_H +#define _X86_CHROMEBOOK_H + +#define CONFIG_SYS_MONITOR_LEN (1 << 20) + +#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R + +#define CONFIG_NR_DRAM_BANKS 8 +#define CONFIG_X86_MRC_ADDR 0xfffa0000 +#define CONFIG_CACHE_MRC_SIZE_KB 512 + +#define CONFIG_X86_SERIAL + +#define CONFIG_SCSI_DEV_LIST \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI}, \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}, \ + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI} + +#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin +#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000 + +#define CONFIG_PCI_MEM_BUS 0xe0000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000 + +#define CONFIG_PCI_PREF_BUS 0xd0000000 +#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS +#define CONFIG_PCI_PREF_SIZE 0x10000000 + +#define CONFIG_PCI_IO_BUS 0x1000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0xefff + +#define CONFIG_SYS_EARLY_PCI_INIT +#define CONFIG_PCI_PNP + +#define CONFIG_BIOSEMU +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO + +#define CONFIG_CROS_EC +#define CONFIG_CROS_EC_LPC +#define CONFIG_CMD_CROS_EC +#define CONFIG_ARCH_EARLY_INIT_R + +#undef CONFIG_ENV_IS_NOWHERE +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x003f8000 + +#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \ + "stdout=vga,serial\0" \ + "stderr=vga,serial\0" + +#endif
On Wed, Feb 11, 2015 at 9:59 AM, Simon Glass sjg@chromium.org wrote:
Since Chromebooks mostly have similar configuration, put it in a common file.
Signed-off-by: Simon Glass sjg@chromium.org
include/configs/chromebook_link.h | 61 +---------------------------------- include/configs/x86-chromebook.h | 68 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 69 insertions(+), 60 deletions(-) create mode 100644 include/configs/x86-chromebook.h
diff --git a/include/configs/chromebook_link.h b/include/configs/chromebook_link.h index 7b460e8..5265787 100644 --- a/include/configs/chromebook_link.h +++ b/include/configs/chromebook_link.h @@ -14,65 +14,6 @@ #define __CONFIG_H
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (1 << 20)
-#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_MISC_INIT_R
-#define CONFIG_NR_DRAM_BANKS 8 -#define CONFIG_X86_MRC_ADDR 0xfffa0000 -#define CONFIG_CACHE_MRC_SIZE_KB 512
-#define CONFIG_X86_SERIAL
-#define CONFIG_SCSI_DEV_LIST {PCI_VENDOR_ID_INTEL, \
PCI_DEVICE_ID_INTEL_NM10_AHCI}, \{PCI_VENDOR_ID_INTEL, \PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \{PCI_VENDOR_ID_INTEL, \PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \{PCI_VENDOR_ID_INTEL, \PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}-#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin -#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000
-#define CONFIG_PCI_MEM_BUS 0xe0000000 -#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS -#define CONFIG_PCI_MEM_SIZE 0x10000000
-#define CONFIG_PCI_PREF_BUS 0xd0000000 -#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS -#define CONFIG_PCI_PREF_SIZE 0x10000000
-#define CONFIG_PCI_IO_BUS 0x1000 -#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS -#define CONFIG_PCI_IO_SIZE 0xefff
-#define CONFIG_SYS_EARLY_PCI_INIT -#define CONFIG_PCI_PNP
-#define CONFIG_BIOSEMU -#define VIDEO_IO_OFFSET 0 -#define CONFIG_X86EMU_RAW_IO
-#define CONFIG_CROS_EC -#define CONFIG_CROS_EC_LPC -#define CONFIG_CMD_CROS_EC -#define CONFIG_ARCH_EARLY_INIT_R
-#undef CONFIG_ENV_IS_NOWHERE -#undef CONFIG_ENV_SIZE -#define CONFIG_ENV_SIZE 0x1000 -#define CONFIG_ENV_SECT_SIZE 0x1000 -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_ENV_OFFSET 0x003f8000
-#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
"stdout=vga,serial\0" \"stderr=vga,serial\0"+#include <configs/x86-chromebook.h>
#endif /* __CONFIG_H */ diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h new file mode 100644 index 0000000..b6a76fe --- /dev/null +++ b/include/configs/x86-chromebook.h @@ -0,0 +1,68 @@ +/*
- Copyright (c) 2015 Google, Inc
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _X86_CHROMEBOOK_H +#define _X86_CHROMEBOOK_H
+#define CONFIG_SYS_MONITOR_LEN (1 << 20)
+#define CONFIG_DCACHE_RAM_MRC_VAR_SIZE 0x4000 +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_MISC_INIT_R
+#define CONFIG_NR_DRAM_BANKS 8 +#define CONFIG_X86_MRC_ADDR 0xfffa0000 +#define CONFIG_CACHE_MRC_SIZE_KB 512
+#define CONFIG_X86_SERIAL
+#define CONFIG_SCSI_DEV_LIST \
{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_NM10_AHCI}, \{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_MOBILE}, \{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_COUGARPOINT_AHCI_SERIES6}, \{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_PANTHERPOINT_AHCI_MOBILE}, \{PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI}+#define CONFIG_X86_OPTION_ROM_FILE pci8086,0166.bin +#define CONFIG_X86_OPTION_ROM_ADDR 0xfff90000
+#define CONFIG_PCI_MEM_BUS 0xe0000000 +#define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS +#define CONFIG_PCI_MEM_SIZE 0x10000000
+#define CONFIG_PCI_PREF_BUS 0xd0000000 +#define CONFIG_PCI_PREF_PHYS CONFIG_PCI_PREF_BUS +#define CONFIG_PCI_PREF_SIZE 0x10000000
+#define CONFIG_PCI_IO_BUS 0x1000 +#define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS +#define CONFIG_PCI_IO_SIZE 0xefff
+#define CONFIG_SYS_EARLY_PCI_INIT +#define CONFIG_PCI_PNP
+#define CONFIG_BIOSEMU +#define VIDEO_IO_OFFSET 0 +#define CONFIG_X86EMU_RAW_IO
+#define CONFIG_CROS_EC +#define CONFIG_CROS_EC_LPC +#define CONFIG_CMD_CROS_EC +#define CONFIG_ARCH_EARLY_INIT_R
+#undef CONFIG_ENV_IS_NOWHERE +#undef CONFIG_ENV_SIZE +#define CONFIG_ENV_SIZE 0x1000 +#define CONFIG_ENV_SECT_SIZE 0x1000 +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_OFFSET 0x003f8000
+#define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,vga,serial\0" \
"stdout=vga,serial\0" \"stderr=vga,serial\0"+#endif
Reviewed-by: Bin Meng bmeng.cn@gmail.com
Add some new device IDs used by this haswell-based chipset.
Signed-off-by: Simon Glass sjg@chromium.org ---
include/pci_ids.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/pci_ids.h b/include/pci_ids.h index dc2ca21..2e66851 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -3016,6 +3016,8 @@ #define PCI_DEVICE_ID_INTEL_TCF_UART_2 0x8813 #define PCI_DEVICE_ID_INTEL_TCF_UART_3 0x8814 #define PCI_DEVICE_ID_INTEL_IXP2800 0x9004 +#define PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI 0x9c03 +#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC 0x9c45 #define PCI_DEVICE_ID_INTEL_S21152BB 0xb152
#define PCI_VENDOR_ID_SCALEMP 0x8686
Hi Simon,
On Wed, Feb 11, 2015 at 9:59 AM, Simon Glass sjg@chromium.org wrote:
Add some new device IDs used by this haswell-based chipset.
Signed-off-by: Simon Glass sjg@chromium.org
Reviewed-by: Bin Meng bmeng.cn@gmail.com
But please re-arrange the patch order in this series so that this patch#5 comes before patch#3 and #4 otherwise patch#3 and patch#4 won't build.
include/pci_ids.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/include/pci_ids.h b/include/pci_ids.h index dc2ca21..2e66851 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -3016,6 +3016,8 @@ #define PCI_DEVICE_ID_INTEL_TCF_UART_2 0x8813 #define PCI_DEVICE_ID_INTEL_TCF_UART_3 0x8814 #define PCI_DEVICE_ID_INTEL_IXP2800 0x9004 +#define PCI_DEVICE_ID_INTEL_LYNXPOINT_AHCI 0x9c03 +#define PCI_DEVICE_ID_INTEL_LYNXPOINT_LPC 0x9c45 #define PCI_DEVICE_ID_INTEL_S21152BB 0xb152
#define PCI_VENDOR_ID_SCALEMP 0x8686
Regards, Bin
Support running U-Boot as a coreboot payload. Tested peripherals include:
- Video (HDMI and DisplayPort) - SATA disk - Gigabit Ethernet - SPI flash
USB3 does not work. This may be a problem with the USB3 PCI driver or something in the USB3 stack and has not been investigated So far this is disabled. The SD card slot also does not work.
For video, coreboot will need to run the OPROM to set this up.
With this board, bare support (running without coreboot) is not available as yet.
Signed-off-by: Simon Glass sjg@chromium.org ---
arch/x86/Kconfig | 16 +++++++++ arch/x86/dts/Makefile | 1 + arch/x86/dts/chromebox_panther.dts | 64 ++++++++++++++++++++++++++++++++++ board/google/chromebox_panther/Kconfig | 18 ++++++++++ configs/chromebox_panther_defconfig | 11 ++++++ include/configs/chromebox_panther.h | 17 +++++++++ 6 files changed, 127 insertions(+) create mode 100644 arch/x86/dts/chromebox_panther.dts create mode 100644 board/google/chromebox_panther/Kconfig create mode 100644 configs/chromebox_panther_defconfig create mode 100644 include/configs/chromebox_panther.h
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index fef11f3..6c667ae 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -32,6 +32,20 @@ config TARGET_CHROMEBOOK_LINK and it provides a 2560x1700 high resolution touch-enabled LCD display.
+config TARGET_CHROMEBOX_PANTHER + bool "Support Chromebox panther (not available)" + select n + help + Note: At present this must be used with Coreboot. See README.x86 + for instructions. + + This is the Asus Chromebox CN60 released in 2014. It uses an Intel + Haswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has a + Lynx Point platform controller hub, PCIe WiFi and Bluetooth. It also + includes a USB SD reader, four USB3 ports, display port and HDMI + video output and a 16GB SATA solid state drive. There is no Chrome + OS EC on this model. + config TARGET_CROWNBAY bool "Support Intel Crown Bay CRB" help @@ -420,6 +434,8 @@ source "board/coreboot/coreboot/Kconfig"
source "board/google/chromebook_link/Kconfig"
+source "board/google/chromebox_panther/Kconfig" + source "board/intel/crownbay/Kconfig"
source "board/intel/minnowmax/Kconfig" diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 7a66133..431bbd8 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -1,4 +1,5 @@ dtb-y += chromebook_link.dtb \ + chromebox_panther.dtb \ crownbay.dtb \ galileo.dtb \ minnowmax.dtb diff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts new file mode 100644 index 0000000..01d43e4 --- /dev/null +++ b/arch/x86/dts/chromebox_panther.dts @@ -0,0 +1,64 @@ +/dts-v1/; + +/include/ "skeleton.dtsi" +/include/ "serial.dtsi" + +/ { + model = "Google Panther"; + compatible = "google,panther", "intel,celeron-haswell"; + + aliases { + spi0 = "/spi"; + }; + + config { + silent-console = <0>; + no-keyboard; + }; + + gpioa { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0 0x10>; + bank-name = "A"; + }; + + gpiob { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x30 0x10>; + bank-name = "B"; + }; + + gpioc { + compatible = "intel,ich6-gpio"; + u-boot,dm-pre-reloc; + reg = <0x40 0x10>; + bank-name = "C"; + }; + + chosen { + stdout-path = "/serial"; + }; + + spi { + #address-cells = <1>; + #size-cells = <0>; + compatible = "intel,ich-spi"; + spi-flash@0 { + #size-cells = <1>; + #address-cells = <1>; + reg = <0>; + compatible = "winbond,w25q64", "spi-flash"; + memory-map = <0xff800000 0x00800000>; + rw-mrc-cache { + label = "rw-mrc-cache"; + /* Alignment: 4k (for updating) */ + reg = <0x003e0000 0x00010000>; + type = "wiped"; + wipe-value = [ff]; + }; + }; + }; + +}; diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig new file mode 100644 index 0000000..788b122 --- /dev/null +++ b/board/google/chromebox_panther/Kconfig @@ -0,0 +1,18 @@ +if TARGET_CHROMEBOX_PANTHER + +config SYS_BOARD + default "chromebox_panther" + +config SYS_VENDOR + default "google" + +config SYS_SOC + default "haswell" + +config SYS_CONFIG_NAME + default "chromebox_panther" + +config BOARD_SPECIFIC_OPTIONS # dummy + def_bool y + +endif diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig new file mode 100644 index 0000000..cbde39e --- /dev/null +++ b/configs/chromebox_panther_defconfig @@ -0,0 +1,11 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000" +CONFIG_X86=y +CONFIG_TARGET_CHROMEBOX_PANTHER=y +CONFIG_OF_CONTROL=y +CONFIG_OF_SEPARATE=y +CONFIG_DEFAULT_DEVICE_TREE="chromebox_panther" +CONFIG_HAVE_MRC=y +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_VIDEO_VESA=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_11A=y diff --git a/include/configs/chromebox_panther.h b/include/configs/chromebox_panther.h new file mode 100644 index 0000000..00fe26d --- /dev/null +++ b/include/configs/chromebox_panther.h @@ -0,0 +1,17 @@ +/* + * Copyright (c) 2011 The Chromium OS Authors. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <configs/x86-common.h> +#include <configs/x86-chromebook.h> + +#define CONFIG_RTL8169 +/* Avoid a warning in the Realtek Ethernet driver */ +#define CONFIG_SYS_CACHELINE_SIZE 16 + +#endif /* __CONFIG_H */
Hi Simon,
On Wed, Feb 11, 2015 at 9:59 AM, Simon Glass sjg@chromium.org wrote:
Support running U-Boot as a coreboot payload. Tested peripherals include:
- Video (HDMI and DisplayPort)
- SATA disk
- Gigabit Ethernet
- SPI flash
USB3 does not work. This may be a problem with the USB3 PCI driver or something in the USB3 stack and has not been investigated So far this is disabled. The SD card slot also does not work.
For video, coreboot will need to run the OPROM to set this up.
With this board, bare support (running without coreboot) is not available as yet.
Signed-off-by: Simon Glass sjg@chromium.org
arch/x86/Kconfig | 16 +++++++++ arch/x86/dts/Makefile | 1 + arch/x86/dts/chromebox_panther.dts | 64 ++++++++++++++++++++++++++++++++++ board/google/chromebox_panther/Kconfig | 18 ++++++++++ configs/chromebox_panther_defconfig | 11 ++++++ include/configs/chromebox_panther.h | 17 +++++++++ 6 files changed, 127 insertions(+) create mode 100644 arch/x86/dts/chromebox_panther.dts create mode 100644 board/google/chromebox_panther/Kconfig create mode 100644 configs/chromebox_panther_defconfig create mode 100644 include/configs/chromebox_panther.h
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index fef11f3..6c667ae 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -32,6 +32,20 @@ config TARGET_CHROMEBOOK_LINK and it provides a 2560x1700 high resolution touch-enabled LCD display.
+config TARGET_CHROMEBOX_PANTHER
bool "Support Chromebox panther (not available)"select nhelpNote: At present this must be used with Coreboot. See README.x86for instructions.This is the Asus Chromebox CN60 released in 2014. It uses an IntelHaswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has aLynx Point platform controller hub, PCIe WiFi and Bluetooth. It alsoincludes a USB SD reader, four USB3 ports, display port and HDMIvideo output and a 16GB SATA solid state drive. There is no ChromeOS EC on this model.config TARGET_CROWNBAY bool "Support Intel Crown Bay CRB" help @@ -420,6 +434,8 @@ source "board/coreboot/coreboot/Kconfig"
source "board/google/chromebook_link/Kconfig"
+source "board/google/chromebox_panther/Kconfig"
source "board/intel/crownbay/Kconfig"
source "board/intel/minnowmax/Kconfig" diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 7a66133..431bbd8 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -1,4 +1,5 @@ dtb-y += chromebook_link.dtb \
chromebox_panther.dtb \ crownbay.dtb \ galileo.dtb \ minnowmax.dtbdiff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts new file mode 100644 index 0000000..01d43e4 --- /dev/null +++ b/arch/x86/dts/chromebox_panther.dts @@ -0,0 +1,64 @@ +/dts-v1/;
+/include/ "skeleton.dtsi" +/include/ "serial.dtsi"
+/ {
model = "Google Panther";compatible = "google,panther", "intel,celeron-haswell";
"intel,celeron-haswell"? celeron is the brand name of the processor. To keep in consistent with other dts files, I think we can just describe it to be "intel,haswell".
aliases {spi0 = "/spi";};config {silent-console = <0>;no-keyboard;};gpioa {compatible = "intel,ich6-gpio";u-boot,dm-pre-reloc;reg = <0 0x10>;bank-name = "A";};gpiob {compatible = "intel,ich6-gpio";u-boot,dm-pre-reloc;reg = <0x30 0x10>;bank-name = "B";};gpioc {compatible = "intel,ich6-gpio";u-boot,dm-pre-reloc;reg = <0x40 0x10>;bank-name = "C";};chosen {stdout-path = "/serial";};spi {#address-cells = <1>;#size-cells = <0>;compatible = "intel,ich-spi";spi-flash@0 {#size-cells = <1>;#address-cells = <1>;reg = <0>;compatible = "winbond,w25q64", "spi-flash";memory-map = <0xff800000 0x00800000>;rw-mrc-cache {label = "rw-mrc-cache";/* Alignment: 4k (for updating) */reg = <0x003e0000 0x00010000>;type = "wiped";wipe-value = [ff];};};};+}; diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig new file mode 100644 index 0000000..788b122 --- /dev/null +++ b/board/google/chromebox_panther/Kconfig @@ -0,0 +1,18 @@ +if TARGET_CHROMEBOX_PANTHER
+config SYS_BOARD
default "chromebox_panther"+config SYS_VENDOR
default "google"+config SYS_SOC
default "haswell"
I don't see haswell directory created in arch/x86/cpu. Is there anything I missed?
+config SYS_CONFIG_NAME
default "chromebox_panther"+config BOARD_SPECIFIC_OPTIONS # dummy
def_bool y+endif diff --git a/configs/chromebox_panther_defconfig b/configs/chromebox_panther_defconfig new file mode 100644 index 0000000..cbde39e --- /dev/null +++ b/configs/chromebox_panther_defconfig @@ -0,0 +1,11 @@ +CONFIG_SYS_EXTRA_OPTIONS="SYS_TEXT_BASE=0xfff00000" +CONFIG_X86=y +CONFIG_TARGET_CHROMEBOX_PANTHER=y +CONFIG_OF_CONTROL=y +CONFIG_OF_SEPARATE=y +CONFIG_DEFAULT_DEVICE_TREE="chromebox_panther" +CONFIG_HAVE_MRC=y +CONFIG_SMM_TSEG_SIZE=0x800000 +CONFIG_VIDEO_VESA=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_11A=y diff --git a/include/configs/chromebox_panther.h b/include/configs/chromebox_panther.h new file mode 100644 index 0000000..00fe26d --- /dev/null +++ b/include/configs/chromebox_panther.h @@ -0,0 +1,17 @@ +/*
- Copyright (c) 2011 The Chromium OS Authors.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __CONFIG_H +#define __CONFIG_H
+#include <configs/x86-common.h> +#include <configs/x86-chromebook.h>
+#define CONFIG_RTL8169 +/* Avoid a warning in the Realtek Ethernet driver */ +#define CONFIG_SYS_CACHELINE_SIZE 16
+#endif /* __CONFIG_H */
Regards, Bin
Hi Bin,
On 25 February 2015 at 00:32, Bin Meng bmeng.cn@gmail.com wrote:
Hi Simon,
On Wed, Feb 11, 2015 at 9:59 AM, Simon Glass sjg@chromium.org wrote:
Support running U-Boot as a coreboot payload. Tested peripherals include:
- Video (HDMI and DisplayPort)
- SATA disk
- Gigabit Ethernet
- SPI flash
USB3 does not work. This may be a problem with the USB3 PCI driver or something in the USB3 stack and has not been investigated So far this is disabled. The SD card slot also does not work.
For video, coreboot will need to run the OPROM to set this up.
With this board, bare support (running without coreboot) is not available as yet.
Signed-off-by: Simon Glass sjg@chromium.org
arch/x86/Kconfig | 16 +++++++++ arch/x86/dts/Makefile | 1 + arch/x86/dts/chromebox_panther.dts | 64 ++++++++++++++++++++++++++++++++++ board/google/chromebox_panther/Kconfig | 18 ++++++++++ configs/chromebox_panther_defconfig | 11 ++++++ include/configs/chromebox_panther.h | 17 +++++++++ 6 files changed, 127 insertions(+) create mode 100644 arch/x86/dts/chromebox_panther.dts create mode 100644 board/google/chromebox_panther/Kconfig create mode 100644 configs/chromebox_panther_defconfig create mode 100644 include/configs/chromebox_panther.h
diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index fef11f3..6c667ae 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -32,6 +32,20 @@ config TARGET_CHROMEBOOK_LINK and it provides a 2560x1700 high resolution touch-enabled LCD display.
+config TARGET_CHROMEBOX_PANTHER
bool "Support Chromebox panther (not available)"select nhelpNote: At present this must be used with Coreboot. See README.x86for instructions.This is the Asus Chromebox CN60 released in 2014. It uses an IntelHaswell Celeron 2955U Dual Core CPU with 2GB of SDRAM. It has aLynx Point platform controller hub, PCIe WiFi and Bluetooth. It alsoincludes a USB SD reader, four USB3 ports, display port and HDMIvideo output and a 16GB SATA solid state drive. There is no ChromeOS EC on this model.config TARGET_CROWNBAY bool "Support Intel Crown Bay CRB" help @@ -420,6 +434,8 @@ source "board/coreboot/coreboot/Kconfig"
source "board/google/chromebook_link/Kconfig"
+source "board/google/chromebox_panther/Kconfig"
source "board/intel/crownbay/Kconfig"
source "board/intel/minnowmax/Kconfig" diff --git a/arch/x86/dts/Makefile b/arch/x86/dts/Makefile index 7a66133..431bbd8 100644 --- a/arch/x86/dts/Makefile +++ b/arch/x86/dts/Makefile @@ -1,4 +1,5 @@ dtb-y += chromebook_link.dtb \
chromebox_panther.dtb \ crownbay.dtb \ galileo.dtb \ minnowmax.dtbdiff --git a/arch/x86/dts/chromebox_panther.dts b/arch/x86/dts/chromebox_panther.dts new file mode 100644 index 0000000..01d43e4 --- /dev/null +++ b/arch/x86/dts/chromebox_panther.dts @@ -0,0 +1,64 @@ +/dts-v1/;
+/include/ "skeleton.dtsi" +/include/ "serial.dtsi"
+/ {
model = "Google Panther";compatible = "google,panther", "intel,celeron-haswell";"intel,celeron-haswell"? celeron is the brand name of the processor. To keep in consistent with other dts files, I think we can just describe it to be "intel,haswell".
OK.
aliases {spi0 = "/spi";};config {silent-console = <0>;no-keyboard;};gpioa {compatible = "intel,ich6-gpio";u-boot,dm-pre-reloc;reg = <0 0x10>;bank-name = "A";};gpiob {compatible = "intel,ich6-gpio";u-boot,dm-pre-reloc;reg = <0x30 0x10>;bank-name = "B";};gpioc {compatible = "intel,ich6-gpio";u-boot,dm-pre-reloc;reg = <0x40 0x10>;bank-name = "C";};chosen {stdout-path = "/serial";};spi {#address-cells = <1>;#size-cells = <0>;compatible = "intel,ich-spi";spi-flash@0 {#size-cells = <1>;#address-cells = <1>;reg = <0>;compatible = "winbond,w25q64", "spi-flash";memory-map = <0xff800000 0x00800000>;rw-mrc-cache {label = "rw-mrc-cache";/* Alignment: 4k (for updating) */reg = <0x003e0000 0x00010000>;type = "wiped";wipe-value = [ff];};};};+}; diff --git a/board/google/chromebox_panther/Kconfig b/board/google/chromebox_panther/Kconfig new file mode 100644 index 0000000..788b122 --- /dev/null +++ b/board/google/chromebox_panther/Kconfig @@ -0,0 +1,18 @@ +if TARGET_CHROMEBOX_PANTHER
+config SYS_BOARD
default "chromebox_panther"+config SYS_VENDOR
default "google"+config SYS_SOC
default "haswell"I don't see haswell directory created in arch/x86/cpu. Is there anything I missed?
No, at present there is no 'bare' support. When I resend this series there are a few fixes needed based on my further testing.
Regards, Simon
Hi Simon,
On Wed, Feb 11, 2015 at 9:59 AM, Simon Glass sjg@chromium.org wrote:
Some systems have more than 4GB of RAM. U-Boot can only place things below 4GB so any memory above that should not be used. Ignore any such memory so that the memory size will not exceed the maximum.
This prevents gd->ram_size exceeding 4GB which causes problems for PCI devices which use DMA.
Signed-off-by: Simon Glass sjg@chromium.org
arch/x86/cpu/coreboot/sdram.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index e98a230..9c3ab81 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -90,7 +90,8 @@ int dram_init(void) struct memrange *memrange = &lib_sysinfo.memrange[i]; unsigned long long end = memrange->base + memrange->size;
if (memrange->type == CB_MEM_RAM && end > ram_size)
if (memrange->type == CB_MEM_RAM && end > ram_size &&memrange->base < (1ULL << 32))
Can we safely assume no single entry in memrange[] lies across the 4GB boundary?
ram_size = end; } gd->ram_size = ram_size;@@ -108,7 +109,8 @@ void dram_init_banksize(void) for (i = 0, j = 0; i < lib_sysinfo.n_memranges; i++) { struct memrange *memrange = &lib_sysinfo.memrange[i];
if (memrange->type == CB_MEM_RAM) {
if (memrange->type == CB_MEM_RAM &&memrange->base < (1ULL << 32)) { gd->bd->bi_dram[j].start = memrange->base; gd->bd->bi_dram[j].size = memrange->size; j++;--
Regards, Bin
Hi Bin,
On 25 February 2015 at 00:10, Bin Meng bmeng.cn@gmail.com wrote:
Hi Simon,
On Wed, Feb 11, 2015 at 9:59 AM, Simon Glass sjg@chromium.org wrote:
Some systems have more than 4GB of RAM. U-Boot can only place things below 4GB so any memory above that should not be used. Ignore any such memory so that the memory size will not exceed the maximum.
This prevents gd->ram_size exceeding 4GB which causes problems for PCI devices which use DMA.
Signed-off-by: Simon Glass sjg@chromium.org
arch/x86/cpu/coreboot/sdram.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index e98a230..9c3ab81 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -90,7 +90,8 @@ int dram_init(void) struct memrange *memrange = &lib_sysinfo.memrange[i]; unsigned long long end = memrange->base + memrange->size;
if (memrange->type == CB_MEM_RAM && end > ram_size)
if (memrange->type == CB_MEM_RAM && end > ram_size &&memrange->base < (1ULL << 32))Can we safely assume no single entry in memrange[] lies across the 4GB boundary?
From what I have seen, yes. There always seems to be a hole in memory
from about 3.3GB to 4GB.
ram_size = end; } gd->ram_size = ram_size;@@ -108,7 +109,8 @@ void dram_init_banksize(void) for (i = 0, j = 0; i < lib_sysinfo.n_memranges; i++) { struct memrange *memrange = &lib_sysinfo.memrange[i];
if (memrange->type == CB_MEM_RAM) {
if (memrange->type == CB_MEM_RAM &&memrange->base < (1ULL << 32)) { gd->bd->bi_dram[j].start = memrange->base; gd->bd->bi_dram[j].size = memrange->size; j++;--
Regards, Bin
Regards, Simon
Hi Simon,
On Thu, Feb 26, 2015 at 8:55 AM, Simon Glass sjg@chromium.org wrote:
Hi Bin,
On 25 February 2015 at 00:10, Bin Meng bmeng.cn@gmail.com wrote:
Hi Simon,
On Wed, Feb 11, 2015 at 9:59 AM, Simon Glass sjg@chromium.org wrote:
Some systems have more than 4GB of RAM. U-Boot can only place things below 4GB so any memory above that should not be used. Ignore any such memory so that the memory size will not exceed the maximum.
This prevents gd->ram_size exceeding 4GB which causes problems for PCI devices which use DMA.
Signed-off-by: Simon Glass sjg@chromium.org
arch/x86/cpu/coreboot/sdram.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/arch/x86/cpu/coreboot/sdram.c b/arch/x86/cpu/coreboot/sdram.c index e98a230..9c3ab81 100644 --- a/arch/x86/cpu/coreboot/sdram.c +++ b/arch/x86/cpu/coreboot/sdram.c @@ -90,7 +90,8 @@ int dram_init(void) struct memrange *memrange = &lib_sysinfo.memrange[i]; unsigned long long end = memrange->base + memrange->size;
if (memrange->type == CB_MEM_RAM && end > ram_size)
if (memrange->type == CB_MEM_RAM && end > ram_size &&memrange->base < (1ULL << 32))Can we safely assume no single entry in memrange[] lies across the 4GB boundary?
From what I have seen, yes. There always seems to be a hole in memory from about 3.3GB to 4GB.
OK, then
Reviewed-by: Bin Meng bmeng.cn@gmail.com
ram_size = end; } gd->ram_size = ram_size;@@ -108,7 +109,8 @@ void dram_init_banksize(void) for (i = 0, j = 0; i < lib_sysinfo.n_memranges; i++) { struct memrange *memrange = &lib_sysinfo.memrange[i];
if (memrange->type == CB_MEM_RAM) {
if (memrange->type == CB_MEM_RAM &&memrange->base < (1ULL << 32)) { gd->bd->bi_dram[j].start = memrange->base; gd->bd->bi_dram[j].size = memrange->size; j++;--
Regards, Bin
participants (4)
-
Anatolij Gustschin -
Bin Meng -
Jagan Teki -
Simon Glass