[PATCH 1/5] dts: stm32mp157c-odyssey: set PLL4_P to 125Mhz for ETH_CLK
Odyssey board requires ETH_CLK of 125Mhz. This commit sets PLL4_P/Q/R to 125, 62.5 and 62.5Mhz in respectively.
Signed-off-by: Heesub Shin heesub@gmail.com --- arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi index b780dbd95e..d07fdcf4bc 100644 --- a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi @@ -115,11 +115,11 @@ bootph-all; };
- /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ + /* VCO = 750.0 MHz => P = 125, Q = 62.5, R = 62.5 */ pll4: st,pll@3 { compatible = "st,stm32mp1-pll"; reg = <3>; - cfg = < 3 98 5 7 7 PQR(1,1,1) >; + cfg = < 3 124 5 9 9 PQR(1,1,1) >; bootph-all; }; };
In Odyssey board, we should use the internal clock from RCC as the transmit clock, instead of the external clock from ETH_CLK125 pad. This commit adds a property, st,eth-clk-sel, so that the ETH_CLK_SEL mux selects ETH_CLK.
Signed-off-by: Heesub Shin heesub@gmail.com --- arch/arm/dts/stm32mp157c-odyssey.dts | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts index 17bcf56f74..53ba018197 100644 --- a/arch/arm/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/dts/stm32mp157c-odyssey.dts @@ -75,6 +75,7 @@ phy-mode = "rgmii-id"; max-speed = <1000>; phy-handle = <&phy0>; + st,ext-phyclk;
mdio0 { #address-cells = <1>;
On 4/28/24 16:24, Heesub Shin wrote:
In Odyssey board, we should use the internal clock from RCC as the transmit clock, instead of the external clock from ETH_CLK125 pad. This commit adds a property, st,eth-clk-sel, so that the ETH_CLK_SEL mux selects ETH_CLK.
Signed-off-by: Heesub Shin heesub@gmail.com
arch/arm/dts/stm32mp157c-odyssey.dts | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts index 17bcf56f74..53ba018197 100644 --- a/arch/arm/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/dts/stm32mp157c-odyssey.dts @@ -75,6 +75,7 @@ phy-mode = "rgmii-id"; max-speed = <1000>; phy-handle = <&phy0>;
st,ext-phyclk;
mdio0 { #address-cells = <1>;
Reviewed-by: Patrice Chotard patrice.chotard@foss.st.com
Thanks Patrice
On 6/6/24 16:37, Patrice CHOTARD wrote:
On 4/28/24 16:24, Heesub Shin wrote:
In Odyssey board, we should use the internal clock from RCC as the transmit clock, instead of the external clock from ETH_CLK125 pad. This commit adds a property, st,eth-clk-sel, so that the ETH_CLK_SEL mux selects ETH_CLK.
Signed-off-by: Heesub Shin heesub@gmail.com
arch/arm/dts/stm32mp157c-odyssey.dts | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts index 17bcf56f74..53ba018197 100644 --- a/arch/arm/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/dts/stm32mp157c-odyssey.dts @@ -75,6 +75,7 @@ phy-mode = "rgmii-id"; max-speed = <1000>; phy-handle = <&phy0>;
st,ext-phyclk;
mdio0 { #address-cells = <1>;
Reviewed-by: Patrice Chotard patrice.chotard@foss.st.com
Thanks Patrice
Applied to u-boot-stm32/next
Thanks Patrice
In Odyssey board, KSZ9031 is at the PHY address 0x7, not 0x0. This commit fixes it.
Signed-off-by: Heesub Shin heesub@gmail.com --- arch/arm/dts/stm32mp157c-odyssey.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts index 53ba018197..b6210cf8b2 100644 --- a/arch/arm/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/dts/stm32mp157c-odyssey.dts @@ -81,8 +81,8 @@ #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio"; - phy0: ethernet-phy@0 { - reg = <0>; + phy0: ethernet-phy@7 { + reg = <7>; }; }; };
On 4/28/24 16:24, Heesub Shin wrote:
In Odyssey board, KSZ9031 is at the PHY address 0x7, not 0x0. This commit fixes it.
Signed-off-by: Heesub Shin heesub@gmail.com
arch/arm/dts/stm32mp157c-odyssey.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts index 53ba018197..b6210cf8b2 100644 --- a/arch/arm/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/dts/stm32mp157c-odyssey.dts @@ -81,8 +81,8 @@ #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@0 {reg = <0>;
phy0: ethernet-phy@7 {reg = <7>;};
Reviewed-by: Patrice Chotard patrice.chotard@foss.st.com
Thanks Patrice
On 4/28/24 16:24, Heesub Shin wrote:
In Odyssey board, KSZ9031 is at the PHY address 0x7, not 0x0. This commit fixes it.
Signed-off-by: Heesub Shin heesub@gmail.com
arch/arm/dts/stm32mp157c-odyssey.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts index 53ba018197..b6210cf8b2 100644 --- a/arch/arm/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/dts/stm32mp157c-odyssey.dts @@ -81,8 +81,8 @@ #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@0 {reg = <0>;
phy0: ethernet-phy@7 {reg = <7>;};
Applied to u-boot-stm32/next
Thanks Patrice
On 4/28/24 16:24, Heesub Shin wrote:
In Odyssey board, KSZ9031 is at the PHY address 0x7, not 0x0. This commit fixes it.
Signed-off-by: Heesub Shin heesub@gmail.com
arch/arm/dts/stm32mp157c-odyssey.dts | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts index 53ba018197..b6210cf8b2 100644 --- a/arch/arm/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/dts/stm32mp157c-odyssey.dts @@ -81,8 +81,8 @@ #address-cells = <1>; #size-cells = <0>; compatible = "snps,dwmac-mdio";
phy0: ethernet-phy@0 {reg = <0>;
phy0: ethernet-phy@7 {reg = <7>;};
Applied to u-boot-stm32/next
Thanks Patrice
This commit adds support for a property 'phy-reset-gpios' to reset PHY chipset.
Signed-off-by: Heesub Shin heesub@gmail.com --- drivers/net/dwc_eth_qos_stm32.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c index fbc08bba1d..cffaa10b70 100644 --- a/drivers/net/dwc_eth_qos_stm32.c +++ b/drivers/net/dwc_eth_qos_stm32.c @@ -266,6 +266,12 @@ static int eqos_probe_resources_stm32(struct udevice *dev) if (ret) dev_warn(dev, "No phy clock provided %d\n", ret);
+ /* Get reset gpio pin (optional) */ + ret = gpio_request_by_name(dev, "phy-reset-gpios", 0, + &eqos->phy_reset_gpio, GPIOD_IS_OUT); + if (ret) + pr_warn("No phy reset gpio provided: %d\n", ret); + dev_dbg(dev, "%s: OK\n", __func__);
return 0; @@ -277,6 +283,21 @@ err_probe: return ret; }
+static int eqos_start_resets_stm32(struct udevice *dev) +{ + struct eqos_priv *eqos = dev_get_priv(dev); + + debug("%s(dev=%p):\n", __func__, dev); + + if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) { + dm_gpio_set_value(&eqos->phy_reset_gpio, 1); + udelay(2); + dm_gpio_set_value(&eqos->phy_reset_gpio, 0); + } + + return 0; +} + static int eqos_remove_resources_stm32(struct udevice *dev) { dev_dbg(dev, "%s:\n", __func__); @@ -292,7 +313,7 @@ static struct eqos_ops eqos_stm32_ops = { .eqos_probe_resources = eqos_probe_resources_stm32, .eqos_remove_resources = eqos_remove_resources_stm32, .eqos_stop_resets = eqos_null_ops, - .eqos_start_resets = eqos_null_ops, + .eqos_start_resets = eqos_start_resets_stm32, .eqos_stop_clks = eqos_stop_clks_stm32, .eqos_start_clks = eqos_start_clks_stm32, .eqos_calibrate_pads = eqos_null_ops,
On 4/28/24 16:24, Heesub Shin wrote:
This commit adds support for a property 'phy-reset-gpios' to reset PHY chipset.
Signed-off-by: Heesub Shin heesub@gmail.com
drivers/net/dwc_eth_qos_stm32.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c index fbc08bba1d..cffaa10b70 100644 --- a/drivers/net/dwc_eth_qos_stm32.c +++ b/drivers/net/dwc_eth_qos_stm32.c @@ -266,6 +266,12 @@ static int eqos_probe_resources_stm32(struct udevice *dev) if (ret) dev_warn(dev, "No phy clock provided %d\n", ret);
/* Get reset gpio pin (optional) */
ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
&eqos->phy_reset_gpio, GPIOD_IS_OUT);if (ret)
pr_warn("No phy reset gpio provided: %d\n", ret);dev_dbg(dev, "%s: OK\n", __func__);
return 0;
@@ -277,6 +283,21 @@ err_probe: return ret; }
+static int eqos_start_resets_stm32(struct udevice *dev) +{
- struct eqos_priv *eqos = dev_get_priv(dev);
- debug("%s(dev=%p):\n", __func__, dev);
- if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
dm_gpio_set_value(&eqos->phy_reset_gpio, 1);udelay(2);dm_gpio_set_value(&eqos->phy_reset_gpio, 0);- }
- return 0;
+}
static int eqos_remove_resources_stm32(struct udevice *dev) { dev_dbg(dev, "%s:\n", __func__); @@ -292,7 +313,7 @@ static struct eqos_ops eqos_stm32_ops = { .eqos_probe_resources = eqos_probe_resources_stm32, .eqos_remove_resources = eqos_remove_resources_stm32, .eqos_stop_resets = eqos_null_ops,
- .eqos_start_resets = eqos_null_ops,
- .eqos_start_resets = eqos_start_resets_stm32, .eqos_stop_clks = eqos_stop_clks_stm32, .eqos_start_clks = eqos_start_clks_stm32, .eqos_calibrate_pads = eqos_null_ops,
Reviewed-by: Patrice Chotard patrice.chotard@foss.st.com
Thanks Patrice
On 4/28/24 16:24, Heesub Shin wrote:
This commit adds support for a property 'phy-reset-gpios' to reset PHY chipset.
Signed-off-by: Heesub Shin heesub@gmail.com
drivers/net/dwc_eth_qos_stm32.c | 23 ++++++++++++++++++++++- 1 file changed, 22 insertions(+), 1 deletion(-)
diff --git a/drivers/net/dwc_eth_qos_stm32.c b/drivers/net/dwc_eth_qos_stm32.c index fbc08bba1d..cffaa10b70 100644 --- a/drivers/net/dwc_eth_qos_stm32.c +++ b/drivers/net/dwc_eth_qos_stm32.c @@ -266,6 +266,12 @@ static int eqos_probe_resources_stm32(struct udevice *dev) if (ret) dev_warn(dev, "No phy clock provided %d\n", ret);
/* Get reset gpio pin (optional) */
ret = gpio_request_by_name(dev, "phy-reset-gpios", 0,
&eqos->phy_reset_gpio, GPIOD_IS_OUT);if (ret)
pr_warn("No phy reset gpio provided: %d\n", ret);dev_dbg(dev, "%s: OK\n", __func__);
return 0;
@@ -277,6 +283,21 @@ err_probe: return ret; }
+static int eqos_start_resets_stm32(struct udevice *dev) +{
- struct eqos_priv *eqos = dev_get_priv(dev);
- debug("%s(dev=%p):\n", __func__, dev);
- if (dm_gpio_is_valid(&eqos->phy_reset_gpio)) {
dm_gpio_set_value(&eqos->phy_reset_gpio, 1);udelay(2);dm_gpio_set_value(&eqos->phy_reset_gpio, 0);- }
- return 0;
+}
static int eqos_remove_resources_stm32(struct udevice *dev) { dev_dbg(dev, "%s:\n", __func__); @@ -292,7 +313,7 @@ static struct eqos_ops eqos_stm32_ops = { .eqos_probe_resources = eqos_probe_resources_stm32, .eqos_remove_resources = eqos_remove_resources_stm32, .eqos_stop_resets = eqos_null_ops,
- .eqos_start_resets = eqos_null_ops,
- .eqos_start_resets = eqos_start_resets_stm32, .eqos_stop_clks = eqos_stop_clks_stm32, .eqos_start_clks = eqos_start_clks_stm32, .eqos_calibrate_pads = eqos_null_ops,
Applied to u-boot-stm32/next
Thanks Patrice
In Odyssey board, we should reset the PHY chipset, toggling G0 pin.
Signed-off-by: Heesub Shin heesub@gmail.com --- arch/arm/dts/stm32mp157c-odyssey.dts | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts index b6210cf8b2..4cc5e07683 100644 --- a/arch/arm/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/dts/stm32mp157c-odyssey.dts @@ -75,6 +75,7 @@ phy-mode = "rgmii-id"; max-speed = <1000>; phy-handle = <&phy0>; + phy-reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; st,ext-phyclk;
mdio0 {
On 4/28/24 16:24, Heesub Shin wrote:
In Odyssey board, we should reset the PHY chipset, toggling G0 pin.
Signed-off-by: Heesub Shin heesub@gmail.com
arch/arm/dts/stm32mp157c-odyssey.dts | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts index b6210cf8b2..4cc5e07683 100644 --- a/arch/arm/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/dts/stm32mp157c-odyssey.dts @@ -75,6 +75,7 @@ phy-mode = "rgmii-id"; max-speed = <1000>; phy-handle = <&phy0>;
phy-reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; st,ext-phyclk;
mdio0 {
Reviewed-by: Patrice Chotard patrice.chotard@foss.st.com
Thanks Patrice
On 4/28/24 16:24, Heesub Shin wrote:
In Odyssey board, we should reset the PHY chipset, toggling G0 pin.
Signed-off-by: Heesub Shin heesub@gmail.com
arch/arm/dts/stm32mp157c-odyssey.dts | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts index b6210cf8b2..4cc5e07683 100644 --- a/arch/arm/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/dts/stm32mp157c-odyssey.dts @@ -75,6 +75,7 @@ phy-mode = "rgmii-id"; max-speed = <1000>; phy-handle = <&phy0>;
phy-reset-gpios = <&gpiog 0 GPIO_ACTIVE_LOW>; st,ext-phyclk;
mdio0 {
Applied to u-boot-stm32/next
Thanks Patrice
On 4/28/24 16:24, Heesub Shin wrote:
Odyssey board requires ETH_CLK of 125Mhz. This commit sets PLL4_P/Q/R to 125, 62.5 and 62.5Mhz in respectively.
Signed-off-by: Heesub Shin heesub@gmail.com
arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi index b780dbd95e..d07fdcf4bc 100644 --- a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi @@ -115,11 +115,11 @@ bootph-all; };
- /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
- /* VCO = 750.0 MHz => P = 125, Q = 62.5, R = 62.5 */ pll4: st,pll@3 { compatible = "st,stm32mp1-pll"; reg = <3>;
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
cfg = < 3 124 5 9 9 PQR(1,1,1) >;};
Reviewed-by: Patrice Chotard patrice.chotard@foss.st.com
Thanks Patrice
On 4/28/24 16:24, Heesub Shin wrote:
Odyssey board requires ETH_CLK of 125Mhz. This commit sets PLL4_P/Q/R to 125, 62.5 and 62.5Mhz in respectively.
Signed-off-by: Heesub Shin heesub@gmail.com
arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi index b780dbd95e..d07fdcf4bc 100644 --- a/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-odyssey-som-u-boot.dtsi @@ -115,11 +115,11 @@ bootph-all; };
- /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */
- /* VCO = 750.0 MHz => P = 125, Q = 62.5, R = 62.5 */ pll4: st,pll@3 { compatible = "st,stm32mp1-pll"; reg = <3>;
cfg = < 3 98 5 7 7 PQR(1,1,1) >;
cfg = < 3 124 5 9 9 PQR(1,1,1) >;};
Applied to u-boot-stm32/next
Thanks Patrice
participants (2)
-
Heesub Shin -
Patrice CHOTARD