[U-Boot] [PATCH] armv8: fsl-layerscape: Put SATA code under SATA configs
It is not necessary for every SoC to have 2 SATA controller. So put SATA1, SATA2 code under respective defines.
Signed-off-by: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Signed-off-by: Ashish Kumar Ashish.Kumar@nxp.com --- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index ddb7d82..a704103 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -215,11 +215,14 @@ int sata_init(void) { struct ccsr_ahci __iomem *ccsr_ahci;
+#ifdef CONFIG_SYS_SATA2 ccsr_ahci = (void *)CONFIG_SYS_SATA2; out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); out_le32(&ccsr_ahci->axicc, AHCI_PORT_AXICC_CFG); +#endif
+#ifdef CONFIG_SYS_SATA1 ccsr_ahci = (void *)CONFIG_SYS_SATA1; out_le32(&ccsr_ahci->ppcfg, AHCI_PORT_PHY_1_CFG); out_le32(&ccsr_ahci->ptc, AHCI_PORT_TRANS_CFG); @@ -227,6 +230,7 @@ int sata_init(void)
ahci_init((void __iomem *)CONFIG_SYS_SATA1); scsi_scan(false); +#endif
return 0; }
LS2080 family has CCN-504 cache coherent interconnet. Other SoCs from LSCH3 may have differnt interconnect like LS1088.
Signed-off-by: Ashish Kumar Ashish.Kumar@nxp.com Signed-off-by: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com --- For clean git am this "http://patchwork.ozlabs.org/patch/800408/" should be applied first
README | 4 ++++ arch/arm/cpu/armv8/fsl-layerscape/Kconfig | 4 ++++ arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 8 +++++--- 3 files changed, 13 insertions(+), 3 deletions(-)
diff --git a/README b/README index a66a7ae..585e285 100644 --- a/README +++ b/README @@ -322,6 +322,10 @@ build a config tool - later. Defined For SoC that has cache coherent interconnect CCN-400
+ CONFIG_SYS_FSL_HAS_CCN504 + + Defined for SoC that has cache coherent interconnect CCN-504 + The following options need to be configured:
- CPU Type: Define exactly one, e.g. CONFIG_MPC85XX. diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig index 1132969..bb69ca6 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Kconfig +++ b/arch/arm/cpu/armv8/fsl-layerscape/Kconfig @@ -60,6 +60,7 @@ config ARCH_LS2080A select SYS_FSL_DDR select SYS_FSL_DDR_LE select SYS_FSL_DDR_VER_50 + select SYS_FSL_HAS_CCN504 select SYS_FSL_HAS_DP_DDR select SYS_FSL_HAS_SEC select SYS_FSL_HAS_DDR4 @@ -267,6 +268,9 @@ config SYS_FSL_IFC_BANK_COUNT config SYS_FSL_HAS_CCI400 bool
+config SYS_FSL_HAS_CCN504 + bool + config SYS_FSL_HAS_DP_DDR bool
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 3136e3f..5ff01a0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -76,7 +76,7 @@ ENTRY(lowlevel_init) switch_el x1, 1f, 100f, 100f /* skip if not in EL3 */ 1:
-#ifdef CONFIG_FSL_LSCH3 +#if defined (CONFIG_SYS_FSL_HAS_CCN504)
/* Set Wuo bit for RN-I 20 */ #ifdef CONFIG_ARCH_LS2080A @@ -171,7 +171,7 @@ ENTRY(lowlevel_init) ldr x0, =CCI_S2_QOS_CONTROL_BASE(20) ldr x1, =0x00FF000C bl ccn504_set_qos -#endif +#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
#ifdef SMMU_BASE /* Set the SMMU page size in the sACR register */ @@ -338,7 +338,9 @@ get_svr: ldr x1, =FSL_LSCH3_SVR ldr w0, [x1] ret +#endif
+#ifdef CONFIG_SYS_FSL_HAS_CCN504 hnf_pstate_poll: /* x0 has the desired status, return 0 for success, 1 for timeout * clobber x1, x2, x3, x4, x6, x7 @@ -420,7 +422,7 @@ ENTRY(__asm_flush_l3_dcache) mov lr, x29 ret ENDPROC(__asm_flush_l3_dcache) -#endif +#endif /* CONFIG_SYS_FSL_HAS_CCN504 */
#ifdef CONFIG_MP /* Keep literals not used by the secondary boot code outside it */
On 08/17/2017 10:24 PM, Ashish Kumar wrote:
LS2080 family has CCN-504 cache coherent interconnet. Other SoCs from LSCH3 may have differnt interconnect like LS1088.
Signed-off-by: Ashish Kumar Ashish.Kumar@nxp.com Signed-off-by: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com
Revised commit message. Applied to fsl-qoriq master. Thanks.
York
On 08/17/2017 10:24 PM, Ashish Kumar wrote:
It is not necessary for every SoC to have 2 SATA controller. So put SATA1, SATA2 code under respective defines.
Signed-off-by: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Signed-off-by: Ashish Kumar Ashish.Kumar@nxp.com
Applied to fsl-qoriq mater. Thanks.
York
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Ashish Kumar -
York Sun