[RESEND PATCH 0/3] clk: Fix ETH initialization on i.MX6Q boards using CCF
This short patch series fixes boards, which after the commit 673f6597321d ("net: fec_mxc: support i.MX8M with CLK_CCF") were required to support in CCF 'ipg' (i.e. IMX6QDL_CLK_ENET) and 'ptp' (i.e. IMX6QDL_CLK_ENET_REF) clocks during ETH initialization. Lack of those clocks supported in CCF resulted in non-functional ETH.
[Rebased on top of v2020.10-rc2]
Lukasz Majewski (3): clk: imx6: Add definition for IMX6QDL_CLK_ENET clock clk: imx: Add support for pllv3 enet clock clk: imx6: Add definition for IMX6QDL_CLK_ENET_REF clock
drivers/clk/imx/clk-imx6q.c | 8 ++++++++ drivers/clk/imx/clk-pllv3.c | 25 +++++++++++++++++++++++++ 2 files changed, 33 insertions(+)
After commit 673f6597321d ("net: fec_mxc: support i.MX8M with CLK_CCF") all NXP boards, which are not IMX8 and in the same time are supporting CCF need to provide IMX6QDL_CLK_ENET.
This change defines the missing clock in i.MX6Q's CCF.
Signed-off-by: Lukasz Majewski lukma@denx.de ---
drivers/clk/imx/clk-imx6q.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index 11d194363d..d954af9a07 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -183,6 +183,7 @@ static int imx6q_clk_probe(struct udevice *dev) clk_dm(IMX6QDL_CLK_I2C2, imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8));
+ clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2("enet", "ipg", base + 0x6c, 10)); return 0; }
This code has been ported from Linux kernel v5.5.5 (tag) and has been adjusted to U-Boot's DM.
It adds support for correct recognition of IMX_PLLV3_ENET flag in the clk-pllv3.c driver.
Signed-off-by: Lukasz Majewski lukma@denx.de ---
drivers/clk/imx/clk-pllv3.c | 25 +++++++++++++++++++++++++ 1 file changed, 25 insertions(+)
diff --git a/drivers/clk/imx/clk-pllv3.c b/drivers/clk/imx/clk-pllv3.c index b4a9d587e1..feacaee1c4 100644 --- a/drivers/clk/imx/clk-pllv3.c +++ b/drivers/clk/imx/clk-pllv3.c @@ -20,6 +20,7 @@ #define UBOOT_DM_CLK_IMX_PLLV3_SYS "imx_clk_pllv3_sys" #define UBOOT_DM_CLK_IMX_PLLV3_USB "imx_clk_pllv3_usb" #define UBOOT_DM_CLK_IMX_PLLV3_AV "imx_clk_pllv3_av" +#define UBOOT_DM_CLK_IMX_PLLV3_ENET "imx_clk_pllv3_enet"
#define PLL_NUM_OFFSET 0x10 #define PLL_DENOM_OFFSET 0x20 @@ -36,6 +37,7 @@ struct clk_pllv3 { u32 enable_bit; u32 div_mask; u32 div_shift; + unsigned long ref_clock; };
#define to_clk_pllv3(_clk) container_of(_clk, struct clk_pllv3, clk) @@ -232,6 +234,19 @@ static const struct clk_ops clk_pllv3_av_ops = { .set_rate = clk_pllv3_av_set_rate, };
+static ulong clk_pllv3_enet_get_rate(struct clk *clk) +{ + struct clk_pllv3 *pll = to_clk_pllv3(clk); + + return pll->ref_clock; +} + +static const struct clk_ops clk_pllv3_enet_ops = { + .enable = clk_pllv3_generic_enable, + .disable = clk_pllv3_generic_disable, + .get_rate = clk_pllv3_enet_get_rate, +}; + struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, const char *parent_name, void __iomem *base, u32 div_mask) @@ -269,6 +284,10 @@ struct clk *imx_clk_pllv3(enum imx_pllv3_type type, const char *name, pll->div_shift = 0; pll->powerup_set = false; break; + case IMX_PLLV3_ENET: + drv_name = UBOOT_DM_CLK_IMX_PLLV3_ENET; + pll->ref_clock = 500000000; + break; default: kfree(pll); return ERR_PTR(-ENOTSUPP); @@ -314,3 +333,9 @@ U_BOOT_DRIVER(clk_pllv3_av) = { .ops = &clk_pllv3_av_ops, .flags = DM_FLAG_PRE_RELOC, }; + +U_BOOT_DRIVER(clk_pllv3_enet) = { + .name = UBOOT_DM_CLK_IMX_PLLV3_ENET, + .id = UCLASS_CLK, + .ops = &clk_pllv3_enet_ops, +};
After commit 673f6597321d ("net: fec_mxc: support i.MX8M with CLK_CCF") all NXP boards, which are not IMX8 and in the same time are supporting CCF need to provide PTP clock.
On the i.MX6Q this clock is provided with IMX6QDL_CLK_ENET_REF in the Linux kernel's CCF.
Code in this change models the simplest case when enet reference clock is generated from 'osc' clock.
Signed-off-by: Lukasz Majewski lukma@denx.de ---
drivers/clk/imx/clk-imx6q.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/clk/imx/clk-imx6q.c b/drivers/clk/imx/clk-imx6q.c index d954af9a07..5343036bab 100644 --- a/drivers/clk/imx/clk-imx6q.c +++ b/drivers/clk/imx/clk-imx6q.c @@ -113,6 +113,10 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_pfd("pll2_pfd0_352m", "pll2_bus", base + 0x100, 0)); clk_dm(IMX6QDL_CLK_PLL2_PFD2_396M, imx_clk_pfd("pll2_pfd2_396m", "pll2_bus", base + 0x100, 2)); + clk_dm(IMX6QDL_CLK_PLL6, + imx_clk_pllv3(IMX_PLLV3_ENET, "pll6", "osc", base + 0xe0, 0x3)); + clk_dm(IMX6QDL_CLK_PLL6_ENET, + imx_clk_gate("pll6_enet", "pll6", base + 0xe0, 13));
/* CCM clocks */ base = dev_read_addr_ptr(dev); @@ -184,6 +188,9 @@ static int imx6q_clk_probe(struct udevice *dev) imx_clk_gate2("i2c2", "ipg_per", base + 0x70, 8));
clk_dm(IMX6QDL_CLK_ENET, imx_clk_gate2("enet", "ipg", base + 0x6c, 10)); + clk_dm(IMX6QDL_CLK_ENET_REF, + imx_clk_fixed_factor("enet_ref", "pll6_enet", 1, 1)); + return 0; }
participants (1)
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Lukasz Majewski