[U-Boot] How to support Page Mode Flash Memory Device?
Hi, I want to implement the page mode for S29GL064N90TFI020 in U-Boot. After i study the page mode, the difference between standard mode and page mode is the less access time following the first access. So, what should i do for the page mode? Is anyone kindly help me on this? Best Regards,Vincent Cheng
Hi Cheng,
On Monday 02 August 2010 09:39:46 Cheng Vincent wrote:
I want to implement the page mode for S29GL064N90TFI020 in U-Boot. After i study the page mode, the difference between standard mode and page mode is the less access time following the first access. So, what should i do for the page mode? Is anyone kindly help me on this? Best Regards,Vincent Cheng
Define CONFIG_SYS_FLASH_USE_BUFFER_WRITE in your config header. This is most likely what you're looking for.
Cheers, Stefan
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office@denx.de
Dear Stefan, Thanks for your suggestions.But i consider that the "write buffer" and the "page mode read" are quite different.BTW, i have searched the internet but got nothing about Page Mode source code. Has anyone ever implemented it? Best Regards,Vincent Cheng
From: sr@denx.de To: u-boot@lists.denx.de Subject: Re: [U-Boot] How to support Page Mode Flash Memory Device? Date: Mon, 2 Aug 2010 11:41:59 +0200 CC: whchang34@hotmail.com
Hi Cheng,
On Monday 02 August 2010 09:39:46 Cheng Vincent wrote:
I want to implement the page mode for S29GL064N90TFI020 in U-Boot. After i study the page mode, the difference between standard mode and page mode is the less access time following the first access. So, what should i do for the page mode? Is anyone kindly help me on this? Best Regards,Vincent Cheng
Define CONFIG_SYS_FLASH_USE_BUFFER_WRITE in your config header. This is most likely what you're looking for.
Cheers, Stefan
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-0 Fax: (+49)-8142-66989-80 Email: office@denx.de
Hi Cheng,
But i consider that the "write buffer" and the "page mode read" are quite different. BTW, i have searched the internet but got nothing about Page Mode source code. Has anyone ever implemented it?
There is nothing to 'implement'. Page mode flash has a timing parameter indicating the time to the first read, and then the time for subsequent reads within a page to return.
If you are interfacing to this flash using a processor local bus controller, then you generally only have one read timing parameter you can configure. In that case, you would have to configure the local bus controller read timing of the processor to the flash worst-case value, i.e., the timing for the read of the first word in a page.
If you are interfacing to the flash using an FPGA, then you can exploit this feature. For example, I use this feature to get optimal read timing from a FPGA configuration controller.
See p30, Figure 12.
http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf
That figure should clarify what page mode means. The example design uses S29GL512N11TF020 parts.
Cheers, Dave
Dear Dave, I learn much from your reply. Thank you very much!Best Regards,Vincent Cheng
Date: Mon, 2 Aug 2010 20:30:30 -0700 From: dwh@ovro.caltech.edu To: whchang34@hotmail.com CC: u-boot@lists.denx.de Subject: Re: [U-Boot] How to support Page Mode Flash Memory Device?
Hi Cheng,
But i consider that the "write buffer" and the "page mode read" are quite different. BTW, i have searched the internet but got nothing about Page Mode source code. Has anyone ever implemented it?
There is nothing to 'implement'. Page mode flash has a timing parameter indicating the time to the first read, and then the time for subsequent reads within a page to return.
If you are interfacing to this flash using a processor local bus controller, then you generally only have one read timing parameter you can configure. In that case, you would have to configure the local bus controller read timing of the processor to the flash worst-case value, i.e., the timing for the read of the first word in a page.
If you are interfacing to the flash using an FPGA, then you can exploit this feature. For example, I use this feature to get optimal read timing from a FPGA configuration controller.
See p30, Figure 12.
http://www.ovro.caltech.edu/~dwh/carma_board/fpga_configuration.pdf
That figure should clarify what page mode means. The example design uses S29GL512N11TF020 parts.
Cheers, Dave
There is nothing to 'implement'. Page mode flash has a timing parameter indicating the time to the first read, and then the time for subsequent reads within a page to return.
If you are interfacing to this flash using a processor local bus controller, then you generally only have one read timing parameter you can configure. In that case, you would have to configure the local bus controller read timing of the processor to the flash worst-case value, i.e., the timing for the read of the first word in a page.
The local bus controller of your processor have to support the page mode for NOR Flash. IIRC, The GPCM of PQx doesn't support such feature right now.
If you are interfacing to the flash using an FPGA, then you can exploit this feature. For example, I use this feature to get optimal read timing from a FPGA configuration controller.
It is easy to control the timing for FPGA.
Thanks, Dave
Dear Dave, I have checked the datasheet of the CPU. It did support the Page Read Mode. I would find the way to make it possible. BTW, i'm very appreciate of your responses.
Best Regards,
Vincent Cheng
Subject: RE: [U-Boot] How to support Page Mode Flash Memory Device? Date: Tue, 3 Aug 2010 14:35:45 +0800 From: r63238@freescale.com To: dwh@ovro.caltech.edu; whchang34@hotmail.com CC: u-boot@lists.denx.de
There is nothing to 'implement'. Page mode flash has a timing parameter indicating the time to the first read, and then the time for subsequent reads within a page to return.
If you are interfacing to this flash using a processor local bus controller, then you generally only have one read timing parameter you can configure. In that case, you would have to configure the local bus controller read timing of the processor to the flash worst-case value, i.e., the timing for the read of the first word in a page.
The local bus controller of your processor have to support the page mode for NOR Flash. IIRC, The GPCM of PQx doesn't support such feature right now.
If you are interfacing to the flash using an FPGA, then you can exploit this feature. For example, I use this feature to get optimal read timing from a FPGA configuration controller.
It is easy to control the timing for FPGA.
Thanks, Dave
participants (4)
-
Cheng Vincent -
David Hawkins -
Liu Dave-R63238 -
Stefan Roese