[U-Boot] [PATCH 0/4] EXYNOS: Add support for MSHCI driver
This patch enables the MSHCI driver support for EXYNOS5.
Rajeshwari Shinde (4): EXYNOS: MSHCI: Add clock for EXYNOS5 EXYNOS5: PINMUX: Add pinmux for SDMMC4 EXYNOS: Add base address for MSHCI EXYNOS5: Enable support for MSHCI
This patchset is based on following patches: "EXYNOS5: PINMUX: Added default pinumx settings" "EXYNOS: SMDK5250: Enable the pinmux setup" "PMIC: MAX77686: Add support for MAX77686" "PMIC: SMDK5250: Enable MAX77686 pmic chip" "EXYNOS5: Enable I2C support" arch/arm/cpu/armv7/exynos/clock.c | 94 ++++++++++++++++++++++++++++++++ arch/arm/cpu/armv7/exynos/pinmux.c | 24 ++++++--- arch/arm/include/asm/arch-exynos/clk.h | 4 ++ arch/arm/include/asm/arch-exynos/cpu.h | 3 + board/samsung/smdk5250/smdk5250.c | 3 + include/configs/smdk5250.h | 1 + 6 files changed, 122 insertions(+), 7 deletions(-)
Add apis to set and get divider clock ratio for FSYS_BLK on EXYNOS5.
Signed-off-by: Terry Lambert tlambert@chromium.org Signed-off-by: Alim Akhtar alim.akhtar@samsung.com Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com --- arch/arm/cpu/armv7/exynos/clock.c | 96 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clk.h | 4 + 2 files changed, 100 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 3b86b0c..3af1aac 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -414,6 +414,90 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) writel(val, addr); }
+static unsigned long exynos5_get_mshci_clk_div(enum periph_id peripheral) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + u32 *addr; + unsigned int div_mmc, div_mmc_pre; + unsigned int mpll_clock, sclk_mmc; + + mpll_clock = get_pll_clk(MPLL); + + /* + * CLK_DIV_FSYS1 + * MMC0_PRE_RATIO [15:8], MMC0_RATIO [3:0] + * CLK_DIV_FSYS2 + * MMC2_PRE_RATIO [15:8], MMC2_RATIO [3:0] + * CLK_DIV_FSYS3 + * MMC4_PRE_RATIO [15:8], MMC4_RATIO [3:0] + */ + switch (peripheral) { + case PERIPH_ID_SDMMC0: + addr = &clk->div_fsys1; + break; + case PERIPH_ID_SDMMC2: + addr = &clk->div_fsys2; + break; + case PERIPH_ID_SDMMC4: + addr = &clk->div_fsys3; + break; + default: + debug("invalid peripheral\n"); + return -1; + } + + div_mmc = (readl(addr) & 0xf) + 1; + div_mmc_pre = ((readl(addr) & 0xff00) >> 8) + 1; + sclk_mmc = (mpll_clock / div_mmc) / div_mmc_pre; + + return sclk_mmc; +} + +static int exynos5_set_mshci_clk_div(enum periph_id peripheral) +{ + struct exynos5_clock *clk = + (struct exynos5_clock *)samsung_get_base_clock(); + u32 *addr; + unsigned int clock; + unsigned int tmp; + unsigned int i; + + /* get mpll clock */ + clock = get_pll_clk(MPLL) / 1000000; + + /* + * CLK_DIV_FSYS1 + * MMC0_PRE_RATIO [15:8], MMC0_RATIO [3:0] + * CLK_DIV_FSYS2 + * MMC2_PRE_RATIO [15:8], MMC2_RATIO [3:0] + * CLK_DIV_FSYS3 + * MMC4_PRE_RATIO [15:8], MMC4_RATIO [3:0] + */ + switch (peripheral) { + case PERIPH_ID_SDMMC0: + addr = &clk->div_fsys1; + break; + case PERIPH_ID_SDMMC2: + addr = &clk->div_fsys2; + break; + case PERIPH_ID_SDMMC4: + addr = &clk->div_fsys3; + break; + default: + debug("invalid peripheral\n"); + return -1; + } + tmp = readl(addr) & ~0xff0f; + for (i = 0; i <= 0xf; i++) { + if ((clock / (i + 1)) <= 400) { + writel(tmp | i << 0, addr); + break; + } + } + return 0; +} + /* get_lcd_clk: return lcd clock frequency */ static unsigned long exynos4_get_lcd_clk(void) { @@ -651,6 +735,18 @@ void set_mmc_clk(int dev_index, unsigned int div) exynos4_set_mmc_clk(dev_index, div); }
+unsigned long get_mshci_clk_div(enum periph_id peripheral) +{ + if (cpu_is_exynos5()) + return exynos5_get_mshci_clk_div(peripheral); +} + +int set_mshci_clk_div(enum periph_id peripheral) +{ + if (cpu_is_exynos5()) + return exynos5_set_mshci_clk_div(peripheral); +} + unsigned long get_lcd_clk(void) { if (cpu_is_exynos4()) diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 72dc655..4a6fa90 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -22,6 +22,8 @@ #ifndef __ASM_ARM_ARCH_CLK_H_ #define __ASM_ARM_ARCH_CLK_H_
+#include <asm/arch/pinmux.h> + #define APLL 0 #define MPLL 1 #define EPLL 2 @@ -34,6 +36,8 @@ unsigned long get_i2c_clk(void); unsigned long get_pwm_clk(void); unsigned long get_uart_clk(int dev_index); void set_mmc_clk(int dev_index, unsigned int div); +unsigned long get_mshci_clk_div(enum periph_id peripheral); +int set_mshci_clk_div(enum periph_id peripheral); unsigned long get_lcd_clk(void); void set_lcd_clk(void); void set_mipi_clk(void);
Hi Rajeshwari,
On Fri, May 25, 2012 at 4:53 AM, Rajeshwari Shinde <rajeshwari.s@samsung.com
wrote:
Add apis to set and get divider clock ratio for FSYS_BLK on EXYNOS5.
Signed-off-by: Terry Lambert tlambert@chromium.org Signed-off-by: Alim Akhtar alim.akhtar@samsung.com Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com
Acked-by: Simon Glass sjg@chromium.org
I have a few suggestions but I realise that most of these are things that will change as you collect more patches. So if you like it is fine with me as is.
arch/arm/cpu/armv7/exynos/clock.c | 96 ++++++++++++++++++++++++++++++++ arch/arm/include/asm/arch-exynos/clk.h | 4 + 2 files changed, 100 insertions(+), 0 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/clock.c b/arch/arm/cpu/armv7/exynos/clock.c index 3b86b0c..3af1aac 100644 --- a/arch/arm/cpu/armv7/exynos/clock.c +++ b/arch/arm/cpu/armv7/exynos/clock.c @@ -414,6 +414,90 @@ static void exynos5_set_mmc_clk(int dev_index, unsigned int div) writel(val, addr); }
+static unsigned long exynos5_get_mshci_clk_div(enum periph_id peripheral)
Would it be better to have a consistent clock_ prefix on all the functions here. Then people can see the function in the code and know what .h and .c file to look in.
+{
struct exynos5_clock *clk =(struct exynos5_clock *)samsung_get_base_clock();u32 *addr;unsigned int div_mmc, div_mmc_pre;unsigned int mpll_clock, sclk_mmc;mpll_clock = get_pll_clk(MPLL);/** CLK_DIV_FSYS1* MMC0_PRE_RATIO [15:8], MMC0_RATIO [3:0]* CLK_DIV_FSYS2* MMC2_PRE_RATIO [15:8], MMC2_RATIO [3:0]* CLK_DIV_FSYS3* MMC4_PRE_RATIO [15:8], MMC4_RATIO [3:0]*/switch (peripheral) {case PERIPH_ID_SDMMC0:addr = &clk->div_fsys1;break;case PERIPH_ID_SDMMC2:addr = &clk->div_fsys2;break;case PERIPH_ID_SDMMC4:addr = &clk->div_fsys3;break;default:debug("invalid peripheral\n");return -1;}div_mmc = (readl(addr) & 0xf) + 1;div_mmc_pre = ((readl(addr) & 0xff00) >> 8) + 1;sclk_mmc = (mpll_clock / div_mmc) / div_mmc_pre;return sclk_mmc;+}
+static int exynos5_set_mshci_clk_div(enum periph_id peripheral) +{
struct exynos5_clock *clk =(struct exynos5_clock *)samsung_get_base_clock();u32 *addr;unsigned int clock;unsigned int tmp;unsigned int i;/* get mpll clock */clock = get_pll_clk(MPLL) / 1000000;/** CLK_DIV_FSYS1* MMC0_PRE_RATIO [15:8], MMC0_RATIO [3:0]* CLK_DIV_FSYS2* MMC2_PRE_RATIO [15:8], MMC2_RATIO [3:0]* CLK_DIV_FSYS3* MMC4_PRE_RATIO [15:8], MMC4_RATIO [3:0]*/switch (peripheral) {case PERIPH_ID_SDMMC0:addr = &clk->div_fsys1;break;case PERIPH_ID_SDMMC2:addr = &clk->div_fsys2;break;case PERIPH_ID_SDMMC4:addr = &clk->div_fsys3;break;default:debug("invalid peripheral\n");return -1;}tmp = readl(addr) & ~0xff0f;for (i = 0; i <= 0xf; i++) {if ((clock / (i + 1)) <= 400) {writel(tmp | i << 0, addr);break;}}return 0;+}
/* get_lcd_clk: return lcd clock frequency */ static unsigned long exynos4_get_lcd_clk(void) { @@ -651,6 +735,18 @@ void set_mmc_clk(int dev_index, unsigned int div) exynos4_set_mmc_clk(dev_index, div); }
+unsigned long get_mshci_clk_div(enum periph_id peripheral) +{
if (cpu_is_exynos5())return exynos5_get_mshci_clk_div(peripheral);+}
+int set_mshci_clk_div(enum periph_id peripheral) +{
if (cpu_is_exynos5())return exynos5_set_mshci_clk_div(peripheral);+}
unsigned long get_lcd_clk(void) { if (cpu_is_exynos4()) diff --git a/arch/arm/include/asm/arch-exynos/clk.h b/arch/arm/include/asm/arch-exynos/clk.h index 72dc655..4a6fa90 100644 --- a/arch/arm/include/asm/arch-exynos/clk.h +++ b/arch/arm/include/asm/arch-exynos/clk.h @@ -22,6 +22,8 @@ #ifndef __ASM_ARM_ARCH_CLK_H_ #define __ASM_ARM_ARCH_CLK_H_
+#include <asm/arch/pinmux.h>
Do you need this here? Maybe periph.h instead? Or just 'enum periph_id' somewhere?
#define APLL 0 #define MPLL 1 #define EPLL 2 @@ -34,6 +36,8 @@ unsigned long get_i2c_clk(void); unsigned long get_pwm_clk(void); unsigned long get_uart_clk(int dev_index); void set_mmc_clk(int dev_index, unsigned int div); +unsigned long get_mshci_clk_div(enum periph_id peripheral);
It would be nice to properly comment all these function.
+int set_mshci_clk_div(enum periph_id peripheral); unsigned long get_lcd_clk(void); void set_lcd_clk(void); void set_mipi_clk(void); -- 1.7.4.4
Regards,
Simon
Add pinmux support for SDMMC4 on EXYNOS5.
Signed-off-by: Terry Lambert tlambert@chromium.org Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com --- This patch is based on: "EXYNOS5: PINMUX: Added default pinumx settings" arch/arm/cpu/armv7/exynos/pinmux.c | 24 +++++++++++++++++------- 1 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 103bcbb..9319fd6 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -32,7 +32,7 @@ int exynos5_pinmux_config(int peripheral, int flags) struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); struct s5p_gpio_bank *bank, *bank_ext; - int i, start, count; + int i, start, count, pin, pin_ext, drv;
switch (peripheral) { case PERIPH_ID_UART0: @@ -66,6 +66,10 @@ int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_SDMMC1: case PERIPH_ID_SDMMC2: case PERIPH_ID_SDMMC3: + case PERIPH_ID_SDMMC4: + pin = GPIO_FUNC(0x2); + pin_ext = GPIO_FUNC(0x3); + drv = GPIO_DRV_4X; switch (peripheral) { case PERIPH_ID_SDMMC0: bank = &gpio1->c0; bank_ext = &gpio1->c1; @@ -79,6 +83,12 @@ int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_SDMMC3: bank = &gpio1->c3; bank_ext = NULL; break; + case PERIPH_ID_SDMMC4: + bank = &gpio1->c0; bank_ext = &gpio1->c1; + pin = GPIO_FUNC(0x3); + pin_ext = GPIO_FUNC(0x4); + drv = GPIO_DRV_2X; + break; } if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { debug("SDMMC device %d does not support 8bit mode", @@ -87,20 +97,20 @@ int exynos5_pinmux_config(int peripheral, int flags) } if (flags & PINMUX_FLAG_8BIT_MODE) { for (i = 3; i <= 6; i++) { - s5p_gpio_cfg_pin(bank_ext, i, GPIO_FUNC(0x3)); + s5p_gpio_cfg_pin(bank_ext, i, pin_ext); s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X); + s5p_gpio_set_drv(bank_ext, i, drv); } } for (i = 0; i < 2; i++) { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(bank, i, pin); s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + s5p_gpio_set_drv(bank, i, drv); } for (i = 3; i <= 6; i++) { - s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2)); + s5p_gpio_cfg_pin(bank, i, pin); s5p_gpio_set_pull(bank, i, GPIO_PULL_UP); - s5p_gpio_set_drv(bank, i, GPIO_DRV_4X); + s5p_gpio_set_drv(bank, i, drv); } break; case PERIPH_ID_SROMC:
Hi,
On Fri, May 25, 2012 at 4:53 AM, Rajeshwari Shinde <rajeshwari.s@samsung.com
wrote:
Add pinmux support for SDMMC4 on EXYNOS5.
Signed-off-by: Terry Lambert tlambert@chromium.org Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com
Is this relevant only to EVT0? It's fine if this is just a step along the way, just wanted to check.
This patch is based on: "EXYNOS5: PINMUX: Added default pinumx settings" arch/arm/cpu/armv7/exynos/pinmux.c | 24 +++++++++++++++++------- 1 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 103bcbb..9319fd6 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -32,7 +32,7 @@ int exynos5_pinmux_config(int peripheral, int flags) struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); struct s5p_gpio_bank *bank, *bank_ext;
int i, start, count;
int i, start, count, pin, pin_ext, drv; switch (peripheral) { case PERIPH_ID_UART0:@@ -66,6 +66,10 @@ int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_SDMMC1: case PERIPH_ID_SDMMC2: case PERIPH_ID_SDMMC3:
case PERIPH_ID_SDMMC4:pin = GPIO_FUNC(0x2);pin_ext = GPIO_FUNC(0x3);drv = GPIO_DRV_4X; switch (peripheral) { case PERIPH_ID_SDMMC0: bank = &gpio1->c0; bank_ext = &gpio1->c1;@@ -79,6 +83,12 @@ int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_SDMMC3: bank = &gpio1->c3; bank_ext = NULL; break;
case PERIPH_ID_SDMMC4:bank = &gpio1->c0; bank_ext = &gpio1->c1;pin = GPIO_FUNC(0x3);pin_ext = GPIO_FUNC(0x4);drv = GPIO_DRV_2X;break; } if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { debug("SDMMC device %d does not support 8bit mode",@@ -87,20 +97,20 @@ int exynos5_pinmux_config(int peripheral, int flags) } if (flags & PINMUX_FLAG_8BIT_MODE) { for (i = 3; i <= 6; i++) {
s5p_gpio_cfg_pin(bank_ext, i,GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(bank_ext, i, pin_ext); s5p_gpio_set_pull(bank_ext, i,GPIO_PULL_UP);
s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
s5p_gpio_set_drv(bank_ext, i, drv); } } for (i = 0; i < 2; i++) {
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(bank, i, pin); s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
s5p_gpio_set_drv(bank, i, drv); } for (i = 3; i <= 6; i++) {
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(bank, i, pin); s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
s5p_gpio_set_drv(bank, i, drv); } break; case PERIPH_ID_SROMC:-- 1.7.4.4
Regards,
Simon
Hi Simon,
On Fri, Jun 1, 2012 at 7:03 AM, Simon Glass sjg@chromium.org wrote:
Hi,
On Fri, May 25, 2012 at 4:53 AM, Rajeshwari Shinde <rajeshwari.s@samsung.com
wrote:
Add pinmux support for SDMMC4 on EXYNOS5.
Signed-off-by: Terry Lambert tlambert@chromium.org Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com
Is this relevant only to EVT0? It's fine if this is just a step along the way, just wanted to check.
--Yes these patches are tested on EVT0
This patch is based on: "EXYNOS5: PINMUX: Added default pinumx settings" arch/arm/cpu/armv7/exynos/pinmux.c | 24 +++++++++++++++++------- 1 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 103bcbb..9319fd6 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -32,7 +32,7 @@ int exynos5_pinmux_config(int peripheral, int flags) struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *) samsung_get_base_gpio_part1(); struct s5p_gpio_bank *bank, *bank_ext;
- int i, start, count;
- int i, start, count, pin, pin_ext, drv;
switch (peripheral) { case PERIPH_ID_UART0: @@ -66,6 +66,10 @@ int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_SDMMC1: case PERIPH_ID_SDMMC2: case PERIPH_ID_SDMMC3:
- case PERIPH_ID_SDMMC4:
- pin = GPIO_FUNC(0x2);
- pin_ext = GPIO_FUNC(0x3);
- drv = GPIO_DRV_4X;
switch (peripheral) { case PERIPH_ID_SDMMC0: bank = &gpio1->c0; bank_ext = &gpio1->c1; @@ -79,6 +83,12 @@ int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_SDMMC3: bank = &gpio1->c3; bank_ext = NULL; break;
- case PERIPH_ID_SDMMC4:
- bank = &gpio1->c0; bank_ext = &gpio1->c1;
- pin = GPIO_FUNC(0x3);
- pin_ext = GPIO_FUNC(0x4);
- drv = GPIO_DRV_2X;
- break;
} if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { debug("SDMMC device %d does not support 8bit mode", @@ -87,20 +97,20 @@ int exynos5_pinmux_config(int peripheral, int flags) } if (flags & PINMUX_FLAG_8BIT_MODE) { for (i = 3; i <= 6; i++) {
- s5p_gpio_cfg_pin(bank_ext, i,
GPIO_FUNC(0x3));
- s5p_gpio_cfg_pin(bank_ext, i, pin_ext);
s5p_gpio_set_pull(bank_ext, i, GPIO_PULL_UP);
- s5p_gpio_set_drv(bank_ext, i, GPIO_DRV_4X);
- s5p_gpio_set_drv(bank_ext, i, drv);
} } for (i = 0; i < 2; i++) {
- s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
- s5p_gpio_cfg_pin(bank, i, pin);
s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
- s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
- s5p_gpio_set_drv(bank, i, drv);
} for (i = 3; i <= 6; i++) {
- s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
- s5p_gpio_cfg_pin(bank, i, pin);
s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
- s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
- s5p_gpio_set_drv(bank, i, drv);
} break; case PERIPH_ID_SROMC: -- 1.7.4.4
Regards,
Simon
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Regards, Rajeshwari Shinde.
Hi Rajeshwari,
On Fri, Jun 1, 2012 at 6:13 AM, Rajeshwari Birje <rajeshwari.birje@gmail.com
wrote:
Hi Simon,
On Fri, Jun 1, 2012 at 7:03 AM, Simon Glass sjg@chromium.org wrote:
Hi,
On Fri, May 25, 2012 at 4:53 AM, Rajeshwari Shinde <
rajeshwari.s@samsung.com
wrote:
Add pinmux support for SDMMC4 on EXYNOS5.
Signed-off-by: Terry Lambert tlambert@chromium.org Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com
Is this relevant only to EVT0? It's fine if this is just a step along the way, just wanted to check.
--Yes these patches are tested on EVT0
OK thanks. I suppose they will need a rebase now, so will wait for that.
Regards, Simon
This patch is based on: "EXYNOS5: PINMUX: Added default pinumx settings" arch/arm/cpu/armv7/exynos/pinmux.c | 24 +++++++++++++++++------- 1 files changed, 17 insertions(+), 7 deletions(-)
diff --git a/arch/arm/cpu/armv7/exynos/pinmux.c b/arch/arm/cpu/armv7/exynos/pinmux.c index 103bcbb..9319fd6 100644 --- a/arch/arm/cpu/armv7/exynos/pinmux.c +++ b/arch/arm/cpu/armv7/exynos/pinmux.c @@ -32,7 +32,7 @@ int exynos5_pinmux_config(int peripheral, int flags) struct exynos5_gpio_part1 *gpio1 = (struct exynos5_gpio_part1 *)
samsung_get_base_gpio_part1();
struct s5p_gpio_bank *bank, *bank_ext;
int i, start, count;
int i, start, count, pin, pin_ext, drv; switch (peripheral) { case PERIPH_ID_UART0:@@ -66,6 +66,10 @@ int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_SDMMC1: case PERIPH_ID_SDMMC2: case PERIPH_ID_SDMMC3:
case PERIPH_ID_SDMMC4:pin = GPIO_FUNC(0x2);pin_ext = GPIO_FUNC(0x3);drv = GPIO_DRV_4X; switch (peripheral) { case PERIPH_ID_SDMMC0: bank = &gpio1->c0; bank_ext = &gpio1->c1;@@ -79,6 +83,12 @@ int exynos5_pinmux_config(int peripheral, int flags) case PERIPH_ID_SDMMC3: bank = &gpio1->c3; bank_ext = NULL; break;
case PERIPH_ID_SDMMC4:bank = &gpio1->c0; bank_ext = &gpio1->c1;pin = GPIO_FUNC(0x3);pin_ext = GPIO_FUNC(0x4);drv = GPIO_DRV_2X;break; } if ((flags & PINMUX_FLAG_8BIT_MODE) && !bank_ext) { debug("SDMMC device %d does not support 8bitmode",
@@ -87,20 +97,20 @@ int exynos5_pinmux_config(int peripheral, int flags) } if (flags & PINMUX_FLAG_8BIT_MODE) { for (i = 3; i <= 6; i++) {
s5p_gpio_cfg_pin(bank_ext, i,GPIO_FUNC(0x3));
s5p_gpio_cfg_pin(bank_ext, i, pin_ext); s5p_gpio_set_pull(bank_ext, i,GPIO_PULL_UP);
s5p_gpio_set_drv(bank_ext, i,GPIO_DRV_4X);
s5p_gpio_set_drv(bank_ext, i, drv); } } for (i = 0; i < 2; i++) {
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(bank, i, pin); s5p_gpio_set_pull(bank, i, GPIO_PULL_NONE);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
s5p_gpio_set_drv(bank, i, drv); } for (i = 3; i <= 6; i++) {
s5p_gpio_cfg_pin(bank, i, GPIO_FUNC(0x2));
s5p_gpio_cfg_pin(bank, i, pin); s5p_gpio_set_pull(bank, i, GPIO_PULL_UP);
s5p_gpio_set_drv(bank, i, GPIO_DRV_4X);
s5p_gpio_set_drv(bank, i, drv); } break; case PERIPH_ID_SROMC:-- 1.7.4.4
Regards,
Simon
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Regards, Rajeshwari Shinde.
This patch adds the base address of MSHCI for EXYNOS4 and EXYNOS5.
Signed-off-by: Terry Lambert tlambert@chromium.org Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com --- This patch is based on: "EXYNOS: Add I2C base address" arch/arm/include/asm/arch-exynos/cpu.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 093bcc1..0d80e45 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -45,6 +45,7 @@ #define EXYNOS4_MIPI_DSIM_BASE 0x11C80000 #define EXYNOS4_USBOTG_BASE 0x12480000 #define EXYNOS4_MMC_BASE 0x12510000 +#define EXYNOS4_MSHC_BASE 0x12550000 #define EXYNOS4_SROMC_BASE 0x12570000 #define EXYNOS4_USBPHY_BASE 0x125B0000 #define EXYNOS4_UART_BASE 0x13800000 @@ -71,6 +72,7 @@ #define EXYNOS5_GPIO_PART1_BASE 0x11400000 #define EXYNOS5_MIPI_DSIM_BASE 0x11D00000 #define EXYNOS5_MMC_BASE 0x12200000 +#define EXYNOS5_MSHC_BASE 0x12240000 #define EXYNOS5_SROMC_BASE 0x12250000 #define EXYNOS5_USBOTG_BASE 0x12480000 #define EXYNOS5_USBPHY_BASE 0x12480000 @@ -156,6 +158,7 @@ SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE) SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE) SAMSUNG_BASE(pro_id, PRO_ID) SAMSUNG_BASE(mmc, MMC_BASE) +SAMSUNG_BASE(mshci, MSHC_BASE) SAMSUNG_BASE(modem, MODEM_BASE) SAMSUNG_BASE(sromc, SROMC_BASE) SAMSUNG_BASE(swreset, SWRESET)
On Fri, May 25, 2012 at 4:53 AM, Rajeshwari Shinde <rajeshwari.s@samsung.com
wrote:
This patch adds the base address of MSHCI for EXYNOS4 and EXYNOS5.
Signed-off-by: Terry Lambert tlambert@chromium.org Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com
Acked-by: Simon Glass sjg@chromium.org
This patch is based on: "EXYNOS: Add I2C base address" arch/arm/include/asm/arch-exynos/cpu.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/arch/arm/include/asm/arch-exynos/cpu.h b/arch/arm/include/asm/arch-exynos/cpu.h index 093bcc1..0d80e45 100644 --- a/arch/arm/include/asm/arch-exynos/cpu.h +++ b/arch/arm/include/asm/arch-exynos/cpu.h @@ -45,6 +45,7 @@ #define EXYNOS4_MIPI_DSIM_BASE 0x11C80000 #define EXYNOS4_USBOTG_BASE 0x12480000 #define EXYNOS4_MMC_BASE 0x12510000 +#define EXYNOS4_MSHC_BASE 0x12550000 #define EXYNOS4_SROMC_BASE 0x12570000 #define EXYNOS4_USBPHY_BASE 0x125B0000 #define EXYNOS4_UART_BASE 0x13800000 @@ -71,6 +72,7 @@ #define EXYNOS5_GPIO_PART1_BASE 0x11400000 #define EXYNOS5_MIPI_DSIM_BASE 0x11D00000 #define EXYNOS5_MMC_BASE 0x12200000 +#define EXYNOS5_MSHC_BASE 0x12240000 #define EXYNOS5_SROMC_BASE 0x12250000 #define EXYNOS5_USBOTG_BASE 0x12480000 #define EXYNOS5_USBPHY_BASE 0x12480000 @@ -156,6 +158,7 @@ SAMSUNG_BASE(gpio_part3, GPIO_PART3_BASE) SAMSUNG_BASE(gpio_part4, GPIO_PART4_BASE) SAMSUNG_BASE(pro_id, PRO_ID) SAMSUNG_BASE(mmc, MMC_BASE) +SAMSUNG_BASE(mshci, MSHC_BASE) SAMSUNG_BASE(modem, MODEM_BASE) SAMSUNG_BASE(sromc, SROMC_BASE) SAMSUNG_BASE(swreset, SWRESET) -- 1.7.4.4
This patchs enables MSHCI driver for EXYNOS5.
Signed-off-by: Terry Lambert tlambert@chromium.org Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com --- This patch is based on: "PMIC: SMDK5250: Enable MAX77686 pmic chip" board/samsung/smdk5250/smdk5250.c | 3 +++ include/configs/smdk5250.h | 1 + 2 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c index 58763fd..3d7a3ed 100644 --- a/board/samsung/smdk5250/smdk5250.c +++ b/board/samsung/smdk5250/smdk5250.c @@ -137,6 +137,9 @@ int board_mmc_init(bd_t *bis) }
err = s5p_mmc_init(2, 4); + + err = exynos_mshci_init(PERIPH_ID_SDMMC4, 8); + return err; } #endif diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 05729e6..8355695 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -79,6 +79,7 @@ #define CONFIG_GENERIC_MMC #define CONFIG_MMC #define CONFIG_S5P_MMC +#define CONFIG_EXYNOS_MSHCI
#define CONFIG_BOARD_EARLY_INIT_F
On Fri, May 25, 2012 at 4:53 AM, Rajeshwari Shinde <rajeshwari.s@samsung.com
wrote:
This patchs enables MSHCI driver for EXYNOS5.
Signed-off-by: Terry Lambert tlambert@chromium.org Signed-off-by: Rajeshwari Shinde rajeshwari.s@samsung.com
Acked-by: Simon Glass sjg@chromium.org
This patch is based on: "PMIC: SMDK5250: Enable MAX77686 pmic chip" board/samsung/smdk5250/smdk5250.c | 3 +++ include/configs/smdk5250.h | 1 + 2 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/board/samsung/smdk5250/smdk5250.c b/board/samsung/smdk5250/smdk5250.c index 58763fd..3d7a3ed 100644 --- a/board/samsung/smdk5250/smdk5250.c +++ b/board/samsung/smdk5250/smdk5250.c @@ -137,6 +137,9 @@ int board_mmc_init(bd_t *bis) }
err = s5p_mmc_init(2, 4);
err = exynos_mshci_init(PERIPH_ID_SDMMC4, 8);return err;} #endif diff --git a/include/configs/smdk5250.h b/include/configs/smdk5250.h index 05729e6..8355695 100644 --- a/include/configs/smdk5250.h +++ b/include/configs/smdk5250.h @@ -79,6 +79,7 @@ #define CONFIG_GENERIC_MMC #define CONFIG_MMC #define CONFIG_S5P_MMC +#define CONFIG_EXYNOS_MSHCI
#define CONFIG_BOARD_EARLY_INIT_F
-- 1.7.4.4
participants (3)
-
Rajeshwari Birje -
Rajeshwari Shinde -
Simon Glass