This has been stripped back for mainlining and supports only sun7i. These changes are not useful by themselves but are split out to make the patch sizes more manageable.

As well as the following signed-off-by the sunxi branch shows commits to these files authored by the following: Alejandro Mery Carl van Schaik Stefan Roese Tom Cubie yemao

Signed-off-by: Alexandru Gagniuc mr.nuke.me@gmail.com Signed-off-by: Chen-Yu Tsai wens@csie.org Signed-off-by: Emilio López emilio@elopez.com.ar Signed-off-by: Hans de Goede hdegoede@redhat.com Signed-off-by: Henrik Nordstrom henrik@henriknordstrom.net Signed-off-by: Jens Kuske jenskuske@gmail.com Signed-off-by: Luke Leighton lkcl@lkcl.net Signed-off-by: Oliver Schinagl oliver@schinagl.nl Signed-off-by: Ian Campbell ijc@hellion.org.uk

--- v2: Based on u-boot-sunxi.git#sunxi d9aa5dd3d15c "sunxi: mmc: checkpatch whitespace fixes" with v2014.04-rc2 merged in: - define magic numbers - simplify get_tbclk - correct clock_set_pll1 prototype - add CONFIG_SUN7I to simplify future SUN?I support. - defines for MMC AHB clocks

v1: Based on u-boot-sunxi.git#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in ldscripts" vs v2014.01. --- arch/arm/cpu/armv7/sunxi/Makefile | 11 ++ arch/arm/cpu/armv7/sunxi/clock.c | 180 +++++++++++++++++++++ arch/arm/cpu/armv7/sunxi/timer.c | 102 ++++++++++++ arch/arm/include/asm/arch-sunxi/clock.h | 237 ++++++++++++++++++++++++++++ arch/arm/include/asm/arch-sunxi/sys_proto.h | 17 ++ arch/arm/include/asm/arch-sunxi/timer.h | 88 +++++++++++ 6 files changed, 635 insertions(+) create mode 100644 arch/arm/cpu/armv7/sunxi/Makefile create mode 100644 arch/arm/cpu/armv7/sunxi/clock.c create mode 100644 arch/arm/cpu/armv7/sunxi/timer.c create mode 100644 arch/arm/include/asm/arch-sunxi/clock.h create mode 100644 arch/arm/include/asm/arch-sunxi/sys_proto.h create mode 100644 arch/arm/include/asm/arch-sunxi/timer.h

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile new file mode 100644 index 0000000..787a127 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -0,0 +1,11 @@ +# +# (C) Copyright 2012 Henrik Nordstrom henrik@henriknordstrom.net +# +# Based on some other Makefile +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-y += timer.o +obj-y += clock.o diff --git a/arch/arm/cpu/armv7/sunxi/clock.c b/arch/arm/cpu/armv7/sunxi/clock.c new file mode 100644 index 0000000..dd01be6 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/clock.c @@ -0,0 +1,180 @@ +/* + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie tangliang@allwinnertech.com + * + * (C) Copyright 2013 Luke Kenneth Casson Leighton lkcl@lkcl.net + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sys_proto.h> + +#ifdef CONFIG_SPL_BUILD +static void clock_init_safe(void) +{ + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* Set safe defaults until PMU is configured */ + writel(AXI_DIV_1 << AXI_DIV_SHIFT | + AHB_DIV_2 << AHB_DIV_SHIFT | + APB0_DIV_1 << APB0_DIV_SHIFT | + CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, + &ccm->cpu_ahb_apb0_cfg); + writel(PLL1_CFG_DEFAULT, &ccm->pll1_cfg); + sdelay(200); + writel(AXI_DIV_1 << AXI_DIV_SHIFT | + AHB_DIV_2 << AHB_DIV_SHIFT | + APB0_DIV_1 << APB0_DIV_SHIFT | + CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, + &ccm->cpu_ahb_apb0_cfg); +#ifdef CONFIG_SUN7I + writel(0x1 << AHB_GATE_OFFSET_DMA | readl(&ccm->ahb_gate0), + &ccm->ahb_gate0); + writel(0x1 << PLL6_ENABLE_OFFSET | readl(&ccm->pll6_cfg), + &ccm->pll6_cfg); +#endif +} +#endif + +int clock_init(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + +#ifdef CONFIG_SPL_BUILD + clock_init_safe(); +#endif + + /* uart clock source is apb1 */ + sr32(&ccm->apb1_clk_div_cfg, 24, 2, APB1_CLK_SRC_OSC24M); + sr32(&ccm->apb1_clk_div_cfg, 16, 2, APB1_FACTOR_N); + sr32(&ccm->apb1_clk_div_cfg, 0, 5, APB1_FACTOR_M); + + /* open the clock for uart */ + sr32(&ccm->apb1_gate, 16 + CONFIG_CONS_INDEX - 1, 1, CLK_GATE_OPEN); + + return 0; +} + +/* Return PLL5 frequency in Hz + * Note: Assumes PLL5 reference is 24MHz clock + */ +unsigned int clock_get_pll5(void) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + uint32_t rval = readl(&ccm->pll5_cfg); + int n = (rval >> 8) & 0x1f; + int k = ((rval >> 4) & 3) + 1; + int p = 1 << ((rval >> 16) & 3); + return 24000000 * n * k / p; +} + +int clock_twi_onoff(int port, int state) +{ + struct sunxi_ccm_reg *const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + if (port > 2) + return -1; + + /* set the apb1 clock gate for twi */ + sr32(&ccm->apb1_gate, 0 + port, 1, state); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +#define PLL1_CFG(N, K, M, P) (1 << 31 | 0 << 30 | 8 << 26 | 0 << 25 | \ + 16 << 20 | (P) << 16 | 2 << 13 | (N) << 8 | \ + (K) << 4 | 0 << 3 | 0 << 2 | (M) << 0) +#define RDIV(a, b) ((a + (b) - 1) / (b)) + +struct { + u32 pll1_cfg; + unsigned int freq; +} pll1_para[] = { + { PLL1_CFG(16, 0, 0, 0), 384000000 }, + { PLL1_CFG(16, 1, 0, 0), 768000000 }, + { PLL1_CFG(20, 1, 0, 0), 960000000 }, + { PLL1_CFG(21, 1, 0, 0), 1008000000}, + { PLL1_CFG(22, 1, 0, 0), 1056000000}, + { PLL1_CFG(23, 1, 0, 0), 1104000000}, + { PLL1_CFG(24, 1, 0, 0), 1152000000}, + { PLL1_CFG(25, 1, 0, 0), 1200000000}, + { PLL1_CFG(26, 1, 0, 0), 1248000000}, + { PLL1_CFG(27, 1, 0, 0), 1296000000}, + { PLL1_CFG(28, 1, 0, 0), 1344000000}, + { PLL1_CFG(29, 1, 0, 0), 1392000000}, + { PLL1_CFG(30, 1, 0, 0), 1440000000}, + { PLL1_CFG(31, 1, 0, 0), 1488000000}, + { PLL1_CFG(31, 1, 0, 0), ~0}, +}; + +void clock_set_pll1(int hz) +{ + int i = 0; + int axi, ahb, apb0; + struct sunxi_ccm_reg * const ccm = + (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + /* Find target frequency */ + while (pll1_para[i].freq < hz) + i++; + + hz = pll1_para[i].freq; + + /* Calculate system clock divisors */ + axi = RDIV(hz, 432000000); /* Max 450MHz */ + ahb = RDIV(hz/axi, 204000000); /* Max 250MHz */ + apb0 = 2; /* Max 150MHz */ + + printf("CPU: %dHz, AXI/AHB/APB: %d/%d/%d\n", hz, axi, ahb, apb0); + + /* Map divisors to register values */ + axi = axi - 1; + if (ahb > 4) + ahb = 3; + else if (ahb > 2) + ahb = 2; + else if (ahb > 1) + ahb = 1; + else + ahb = 0; + + apb0 = apb0 - 1; + + /* Switch to 24MHz clock while changing PLL1 */ + writel(AXI_DIV_1 << AXI_DIV_SHIFT | + AHB_DIV_2 << AHB_DIV_SHIFT | + APB0_DIV_1 << APB0_DIV_SHIFT | + CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, + &ccm->cpu_ahb_apb0_cfg); + sdelay(20); + + /* Configure sys clock divisors */ + writel(axi << AXI_DIV_SHIFT | + ahb << AHB_DIV_SHIFT | + apb0 << APB0_DIV_SHIFT | + CPU_CLK_SRC_OSC24M << CPU_CLK_SRC_SHIFT, + &ccm->cpu_ahb_apb0_cfg); + + /* Configure PLL1 at the desired frequency */ + writel(pll1_para[i].pll1_cfg, &ccm->pll1_cfg); + sdelay(200); + + /* Switch CPU to PLL1 */ + writel(axi << AXI_DIV_SHIFT | + ahb << AHB_DIV_SHIFT | + apb0 << APB0_DIV_SHIFT | + CPU_CLK_SRC_PLL1 << CPU_CLK_SRC_SHIFT, + &ccm->cpu_ahb_apb0_cfg); + sdelay(20); +} +#endif diff --git a/arch/arm/cpu/armv7/sunxi/timer.c b/arch/arm/cpu/armv7/sunxi/timer.c new file mode 100644 index 0000000..d0d9953 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/timer.c @@ -0,0 +1,102 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie tangliang@allwinnertech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/timer.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define TIMER_MODE (0x0 << 7) /* continuous mode */ +#define TIMER_DIV (0x0 << 4) /* pre scale 1 */ +#define TIMER_SRC (0x1 << 2) /* osc24m */ +#define TIMER_RELOAD (0x1 << 1) /* reload internal value */ +#define TIMER_EN (0x1 << 0) /* enable timer */ + +#define TIMER_CLOCK (24 * 1000 * 1000) +#define COUNT_TO_USEC(x) ((x) / 24) +#define USEC_TO_COUNT(x) ((x) * 24) +#define TICKS_PER_HZ (TIMER_CLOCK / CONFIG_SYS_HZ) +#define TICKS_TO_HZ(x) ((x) / TICKS_PER_HZ) + +#define TIMER_LOAD_VAL 0xffffffff + +#define TIMER_NUM 0 /* we use timer 0 */ + +static struct sunxi_timer *timer_base = + &((struct sunxi_timer_reg *)SUNXI_TIMER_BASE)->timer[TIMER_NUM]; + +/* macro to read the 32 bit timer: since it decrements, we invert read value */ +#define READ_TIMER() (~readl(&timer_base->val)) + +/* init timer register */ +int timer_init(void) +{ + writel(TIMER_LOAD_VAL, &timer_base->inter); + writel(TIMER_MODE | TIMER_DIV | TIMER_SRC | TIMER_RELOAD | TIMER_EN, + &timer_base->ctl); + + return 0; +} + +/* timer without interrupts */ +ulong get_timer(ulong base) +{ + return get_timer_masked() - base; +} + +ulong get_timer_masked(void) +{ + /* current tick value */ + ulong now = TICKS_TO_HZ(READ_TIMER()); + + if (now >= gd->arch.lastinc) /* normal (non rollover) */ + gd->arch.tbl += (now - gd->arch.lastinc); + else { + /* rollover */ + gd->arch.tbl += (TICKS_TO_HZ(TIMER_LOAD_VAL) + - gd->arch.lastinc) + now; + } + gd->arch.lastinc = now; + + return gd->arch.tbl; +} + +/* delay x useconds */ +void __udelay(unsigned long usec) +{ + long tmo = USEC_TO_COUNT(usec); + ulong now, last = READ_TIMER(); + + while (tmo > 0) { + now = READ_TIMER(); + if (now > last) /* normal (non rollover) */ + tmo -= now - last; + else /* rollover */ + tmo -= TIMER_LOAD_VAL - last + now; + last = now; + } +} + +/* + * This function is derived from PowerPC code (read timebase as long long). + * On ARM it just returns the timer value. + */ +unsigned long long get_ticks(void) +{ + return get_timer(0); +} + +/* + * This function is derived from PowerPC code (timebase clock frequency). + * On ARM it returns the number of timer ticks per second. + */ +ulong get_tbclk(void) +{ + return CONFIG_SYS_HZ; +} diff --git a/arch/arm/include/asm/arch-sunxi/clock.h b/arch/arm/include/asm/arch-sunxi/clock.h new file mode 100644 index 0000000..defd229 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/clock.h @@ -0,0 +1,237 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie tangliang@allwinnertech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CLOCK_H +#define _SUNXI_CLOCK_H + +#include <linux/types.h> + +/* clock control module regs definition */ + +struct sunxi_ccm_reg { + u32 pll1_cfg; /* 0x00 pll1 control */ + u32 pll1_tun; /* 0x04 pll1 tuning */ + u32 pll2_cfg; /* 0x08 pll2 control */ + u32 pll2_tun; /* 0x0c pll2 tuning */ + u32 pll3_cfg; /* 0x10 pll3 control */ + u8 res0[0x4]; + u32 pll4_cfg; /* 0x18 pll4 control */ + u8 res1[0x4]; + u32 pll5_cfg; /* 0x20 pll5 control */ + u32 pll5_tun; /* 0x24 pll5 tuning */ + u32 pll6_cfg; /* 0x28 pll6 control */ + u32 pll6_tun; /* 0x2c pll6 tuning */ + u32 pll7_cfg; /* 0x30 pll7 control */ + u32 pll1_tun2; /* 0x34 pll5 tuning2 */ + u8 res2[0x4]; + u32 pll5_tun2; /* 0x3c pll5 tuning2 */ + u8 res3[0xc]; + u32 pll_lock_dbg; /* 0x4c pll lock time debug */ + u32 osc24m_cfg; /* 0x50 osc24m control */ + u32 cpu_ahb_apb0_cfg; /* 0x54 cpu,ahb and apb0 divide ratio */ + u32 apb1_clk_div_cfg; /* 0x58 apb1 clock dividor */ + u32 axi_gate; /* 0x5c axi module clock gating */ + u32 ahb_gate0; /* 0x60 ahb module clock gating 0 */ + u32 ahb_gate1; /* 0x64 ahb module clock gating 1 */ + u32 apb0_gate; /* 0x68 apb0 module clock gating */ + u32 apb1_gate; /* 0x6c apb1 module clock gating */ + u8 res4[0x10]; + u32 nand_sclk_cfg; /* 0x80 nand sub clock control */ + u32 ms_sclk_cfg; /* 0x84 memory stick sub clock control */ + u32 sd0_clk_cfg; /* 0x88 sd0 clock control */ + u32 sd1_clk_cfg; /* 0x8c sd1 clock control */ + u32 sd2_clk_cfg; /* 0x90 sd2 clock control */ + u32 sd3_clk_cfg; /* 0x94 sd3 clock control */ + u32 ts_clk_cfg; /* 0x98 transport stream clock control */ + u32 ss_clk_cfg; /* 0x9c */ + u32 spi0_clk_cfg; /* 0xa0 */ + u32 spi1_clk_cfg; /* 0xa4 */ + u32 spi2_clk_cfg; /* 0xa8 */ + u32 pata_clk_cfg; /* 0xac */ + u32 ir0_clk_cfg; /* 0xb0 */ + u32 ir1_clk_cfg; /* 0xb4 */ + u32 iis_clk_cfg; /* 0xb8 */ + u32 ac97_clk_cfg; /* 0xbc */ + u32 spdif_clk_cfg; /* 0xc0 */ + u32 keypad_clk_cfg; /* 0xc4 */ + u32 sata_clk_cfg; /* 0xc8 */ + u32 usb_clk_cfg; /* 0xcc */ + u32 gps_clk_cfg; /* 0xd0 */ + u32 spi3_clk_cfg; /* 0xd4 */ + u8 res5[0x28]; + u32 dram_clk_cfg; /* 0x100 */ + u32 be0_clk_cfg; /* 0x104 */ + u32 be1_clk_cfg; /* 0x108 */ + u32 fe0_clk_cfg; /* 0x10c */ + u32 fe1_clk_cfg; /* 0x110 */ + u32 mp_clk_cfg; /* 0x114 */ + u32 lcd0_ch0_clk_cfg; /* 0x118 */ + u32 lcd1_ch0_clk_cfg; /* 0x11c */ + u32 csi_isp_clk_cfg; /* 0x120 */ + u8 res6[0x4]; + u32 tvd_clk_reg; /* 0x128 */ + u32 lcd0_ch1_clk_cfg; /* 0x12c */ + u32 lcd1_ch1_clk_cfg; /* 0x130 */ + u32 csi0_clk_cfg; /* 0x134 */ + u32 csi1_clk_cfg; /* 0x138 */ + u32 ve_clk_cfg; /* 0x13c */ + u32 audio_codec_clk_cfg; /* 0x140 */ + u32 avs_clk_cfg; /* 0x144 */ + u32 ace_clk_cfg; /* 0x148 */ + u32 lvds_clk_cfg; /* 0x14c */ + u32 hdmi_clk_cfg; /* 0x150 */ + u32 mali_clk_cfg; /* 0x154 */ + u8 res7[0x4]; + u32 mbus_clk_cfg; /* 0x15c */ + u8 res8[0x4]; + u32 gmac_clk_cfg; /* 0x164 */ +}; + +/* apb1 bit field */ +#define APB1_CLK_SRC_OSC24M 0 +#define APB1_FACTOR_M 0 +#define APB1_FACTOR_N 0 + +/* clock divide */ +#define AXI_DIV_SHIFT (0) +#define AXI_DIV_1 0 +#define AXI_DIV_2 1 +#define AXI_DIV_3 2 +#define AXI_DIV_4 3 +#define AHB_DIV_SHIFT (4) +#define AHB_DIV_1 0 +#define AHB_DIV_2 1 +#define AHB_DIV_4 2 +#define AHB_DIV_8 3 +#define APB0_DIV_SHIFT (8) +#define APB0_DIV_1 0 +#define APB0_DIV_2 1 +#define APB0_DIV_4 2 +#define APB0_DIV_8 3 +#define CPU_CLK_SRC_SHIFT (16) +#define CPU_CLK_SRC_OSC24M 1 +#define CPU_CLK_SRC_PLL1 2 + +#define PLL1_CFG_DEFAULT 0xa1005000 + +#define PLL6_ENABLE_OFFSET 31 + +#define CLK_GATE_OPEN 0x1 +#define CLK_GATE_CLOSE 0x0 + +/* nand clock */ +#define NAND_CLK_SRC_OSC24 0 +#define NAND_CLK_DIV_N 0 +#define NAND_CLK_DIV_M 0 + +/* gps clock */ +#define GPS_SCLK_GATING_OFF 0 +#define GPS_RESET 0 + +/* ahb clock gate bit offset */ +#define AHB_GATE_OFFSET_GPS 26 +#define AHB_GATE_OFFSET_SATA 25 +#define AHB_GATE_OFFSET_PATA 24 +#define AHB_GATE_OFFSET_SPI3 23 +#define AHB_GATE_OFFSET_SPI2 22 +#define AHB_GATE_OFFSET_SPI1 21 +#define AHB_GATE_OFFSET_SPI0 20 +#define AHB_GATE_OFFSET_TS0 18 +#define AHB_GATE_OFFSET_EMAC 17 +#define AHB_GATE_OFFSET_ACE 16 +#define AHB_GATE_OFFSET_DLL 15 +#define AHB_GATE_OFFSET_SDRAM 14 +#define AHB_GATE_OFFSET_NAND 13 +#define AHB_GATE_OFFSET_MS 12 +#define AHB_GATE_OFFSET_MMC3 11 +#define AHB_GATE_OFFSET_MMC2 10 +#define AHB_GATE_OFFSET_MMC1 9 +#define AHB_GATE_OFFSET_MMC0 8 +#define AHB_GATE_OFFSET_MMC(n) (AHB_GATE_OFFSET_MMC0 + (n)) +#define AHB_GATE_OFFSET_BIST 7 +#define AHB_GATE_OFFSET_DMA 6 +#define AHB_GATE_OFFSET_SS 5 +#define AHB_GATE_OFFSET_USB_OHCI1 4 +#define AHB_GATE_OFFSET_USB_EHCI1 3 +#define AHB_GATE_OFFSET_USB_OHCI0 2 +#define AHB_GATE_OFFSET_USB_EHCI0 1 +#define AHB_GATE_OFFSET_USB 0 + +/* ahb clock gate bit offset (second register) */ +#define AHB_GATE_OFFSET_GMAC 17 + +#define CCM_AHB_GATE_GPS (0x1 << 26) +#define CCM_AHB_GATE_SDRAM (0x1 << 14) +#define CCM_AHB_GATE_DLL (0x1 << 15) +#define CCM_AHB_GATE_ACE (0x1 << 16) + +#define CCM_PLL5_CTRL_M(n) (((n) & 0x3) << 0) +#define CCM_PLL5_CTRL_M_MASK CCM_PLL5_CTRL_M(0x3) +#define CCM_PLL5_CTRL_M_X(n) ((n) - 1) +#define CCM_PLL5_CTRL_M1(n) (((n) & 0x3) << 2) +#define CCM_PLL5_CTRL_M1_MASK CCM_PLL5_CTRL_M1(0x3) +#define CCM_PLL5_CTRL_M1_X(n) ((n) - 1) +#define CCM_PLL5_CTRL_K(n) (((n) & 0x3) << 4) +#define CCM_PLL5_CTRL_K_MASK CCM_PLL5_CTRL_K(0x3) +#define CCM_PLL5_CTRL_K_X(n) ((n) - 1) +#define CCM_PLL5_CTRL_LDO (0x1 << 7) +#define CCM_PLL5_CTRL_N(n) (((n) & 0x1f) << 8) +#define CCM_PLL5_CTRL_N_MASK CCM_PLL5_CTRL_N(0x1f) +#define CCM_PLL5_CTRL_N_X(n) (n) +#define CCM_PLL5_CTRL_P(n) (((n) & 0x3) << 16) +#define CCM_PLL5_CTRL_P_MASK CCM_PLL5_CTRL_P(0x3) +#define CCM_PLL5_CTRL_P_X(n) ((n) - 1) +#define CCM_PLL5_CTRL_BW (0x1 << 18) +#define CCM_PLL5_CTRL_VCO_GAIN (0x1 << 19) +#define CCM_PLL5_CTRL_BIAS(n) (((n) & 0x1f) << 20) +#define CCM_PLL5_CTRL_BIAS_MASK CCM_PLL5_CTRL_BIAS(0x1f) +#define CCM_PLL5_CTRL_BIAS_X(n) ((n) - 1) +#define CCM_PLL5_CTRL_VCO_BIAS (0x1 << 25) +#define CCM_PLL5_CTRL_DDR_CLK (0x1 << 29) +#define CCM_PLL5_CTRL_BYPASS (0x1 << 30) +#define CCM_PLL5_CTRL_EN (0x1 << 31) + +#define CCM_GPS_CTRL_RESET (0x1 << 0) +#define CCM_GPS_CTRL_GATE (0x1 << 1) + +#define CCM_DRAM_CTRL_DCLK_OUT (0x1 << 15) + +#define CCM_MBUS_CTRL_M(n) (((n) & 0xf) << 0) +#define CCM_MBUS_CTRL_M_MASK CCM_MBUS_CTRL_M(0xf) +#define CCM_MBUS_CTRL_M_X(n) ((n) - 1) +#define CCM_MBUS_CTRL_N(n) (((n) & 0xf) << 16) +#define CCM_MBUS_CTRL_N_MASK CCM_MBUS_CTRL_N(0xf) +#define CCM_MBUS_CTRL_N_X(n) (((n) >> 3) ? 3 : (((n) >> 2) ? 2 : (((n) >> 1) ? 1 : 0))) +#define CCM_MBUS_CTRL_CLK_SRC(n) (((n) & 0x3) << 24) +#define CCM_MBUS_CTRL_CLK_SRC_MASK CCM_MBUS_CTRL_CLK_SRC(0x3) +#define CCM_MBUS_CTRL_CLK_SRC_HOSC 0x0 +#define CCM_MBUS_CTRL_CLK_SRC_PLL6 0x1 +#define CCM_MBUS_CTRL_CLK_SRC_PLL5 0x2 +#define CCM_MBUS_CTRL_GATE (0x1 << 31) + +#define CCM_MMC_CTRL_OSCM24 (0x0 << 24) +#define CCM_MMC_CTRL_PLL6 (0x1 << 24) +#define CCM_MMC_CTRL_PLL5 (0x2 << 24) + +#define CCM_MMC_CTRL_ENABLE (0x1 << 31) + +#define CCM_GMAC_CTRL_TX_CLK_SRC_MII 0x0 +#define CCM_GMAC_CTRL_TX_CLK_SRC_EXT_RGMII 0x1 +#define CCM_GMAC_CTRL_TX_CLK_SRC_INT_RGMII 0x2 +#define CCM_GMAC_CTRL_GPIT_MII (0x0 << 2) +#define CCM_GMAC_CTRL_GPIT_RGMII (0x1 << 2) + + +#ifndef __ASSEMBLY__ +int clock_init(void); +int clock_twi_onoff(int port, int state); +void clock_set_pll1(int hz); +unsigned int clock_get_pll5(void); +#endif + +#endif /* _SUNXI_CLOCK_H */ diff --git a/arch/arm/include/asm/arch-sunxi/sys_proto.h b/arch/arm/include/asm/arch-sunxi/sys_proto.h new file mode 100644 index 0000000..61b29d8 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/sys_proto.h @@ -0,0 +1,17 @@ +/* + * (C) Copyright 2007-2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie tangliang@allwinnertech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SYS_PROTO_H_ +#define _SYS_PROTO_H_ + +#include <linux/types.h> + +void sr32(u32 *, u32, u32, u32); +void sdelay(unsigned long); + +#endif diff --git a/arch/arm/include/asm/arch-sunxi/timer.h b/arch/arm/include/asm/arch-sunxi/timer.h new file mode 100644 index 0000000..6aacfd7 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/timer.h @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie tangliang@allwinnertech.com + * + * Configuration settings for the Allwinner A10-evb board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_TIMER_H_ +#define _SUNXI_TIMER_H_ + +#ifndef __ASSEMBLY__ + +#include <linux/types.h> + +/* General purpose timer */ +struct sunxi_timer { + u32 ctl; + u32 inter; + u32 val; + u8 res[4]; +}; + +/* Audio video sync*/ +struct sunxi_avs { + u32 ctl; /* 0x80 */ + u32 cnt0; /* 0x84 */ + u32 cnt1; /* 0x88 */ + u32 div; /* 0x8c */ +}; + +/* 64 bit counter */ +struct sunxi_64cnt { + u32 ctl; /* 0xa0 */ + u32 lo; /* 0xa4 */ + u32 hi; /* 0xa8 */ +}; + +/* Watchdog */ +struct sunxi_wdog { + u32 ctl; /* 0x90 */ + u32 mode; /* 0x94 */ +}; + +/* Rtc */ +struct sunxi_rtc { + u32 ctl; /* 0x100 */ + u32 yymmdd; /* 0x104 */ + u32 hhmmss; /* 0x108 */ +}; + +/* Alarm */ +struct sunxi_alarm { + u32 ddhhmmss; /* 0x10c */ + u32 hhmmss; /* 0x110 */ + u32 en; /* 0x114 */ + u32 irqen; /* 0x118 */ + u32 irqsta; /* 0x11c */ +}; + +/* Timer general purpose register */ +struct sunxi_tgp { + u32 tgpd; +}; + +struct sunxi_timer_reg { + u32 tirqen; /* 0x00 */ + u32 tirqsta; /* 0x04 */ + u8 res1[8]; + struct sunxi_timer timer[6]; /* We have 6 timers */ + u8 res2[16]; + struct sunxi_avs avs; + struct sunxi_wdog wdog; + u8 res3[8]; + struct sunxi_64cnt cnt64; + u8 res4[0x58]; + struct sunxi_rtc rtc; + struct sunxi_alarm alarm; + struct sunxi_tgp tgp[4]; + u8 res5[8]; + u32 cpu_cfg; +}; + +#endif /* __ASSEMBLY__ */ + +#endif

This has been stripped back for mainlining and supports only sun7i. These changes are not useful by themselves but are split out to make the patch sizes more manageable.

As well as the following signed-off-by the sunxi branch shows commits to these files authored by the following: Almo Nito Carl van Schaik FUKAUMI Naoki hehopmajieh j Sergey Lapin Tom Cubie

Signed-off-by: Aleksei Mamlin mamlinav@gmail.com Signed-off-by: Alexandru Gagniuc mr.nuke.me@gmail.com Signed-off-by: Chen-Yu Tsai wens@csie.org Signed-off-by: Emilio López emilio@elopez.com.ar Signed-off-by: Hans de Goede hdegoede@redhat.com Signed-off-by: Henrik Nordstrom henrik@henriknordstrom.net Signed-off-by: Jens Kuske jenskuske@gmail.com Signed-off-by: Luc Verhaegen libv@skynet.be Signed-off-by: Luke Leighton lkcl@lkcl.net Signed-off-by: Oliver Schinagl oliver@schinagl.nl Signed-off-by: Patrick Wood patrickhwood@gmail.com Signed-off-by: Stefan Roese sr@denx.de Signed-off-by: Wills Wang wills.wang.open@gmail.com Signed-off-by: Ian Campbell ijc@hellion.org.uk --- v2: Based on u-boot-sunxi.git#sunxi d9aa5dd3d15c "sunxi: mmc: checkpatch whitespace fixes" with v2014.04-rc2 merged in: - just init dram once - remove clock ramping until power control is implemented - add CONFIG_SUN7I to simplify future SUN?I support. - fix a typo

v1: Based on u-boot-sunxi.git#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in ldscripts" vs v2014.01. --- arch/arm/cpu/armv7/sunxi/Makefile | 11 +++ arch/arm/cpu/armv7/sunxi/board.c | 88 ++++++++++++++++++++++++ arch/arm/cpu/armv7/sunxi/cpu_info.c | 19 ++++++ arch/arm/cpu/armv7/sunxi/start.c | 1 + arch/arm/include/asm/arch-sunxi/cpu.h | 122 ++++++++++++++++++++++++++++++++++ board/sunxi/Makefile | 11 +++ board/sunxi/board.c | 57 ++++++++++++++++ 7 files changed, 309 insertions(+) create mode 100644 arch/arm/cpu/armv7/sunxi/board.c create mode 100644 arch/arm/cpu/armv7/sunxi/cpu_info.c create mode 100644 arch/arm/cpu/armv7/sunxi/start.c create mode 100644 arch/arm/include/asm/arch-sunxi/cpu.h create mode 100644 board/sunxi/Makefile create mode 100644 board/sunxi/board.c

diff --git a/arch/arm/cpu/armv7/sunxi/Makefile b/arch/arm/cpu/armv7/sunxi/Makefile index 3485404..d85b647 100644 --- a/arch/arm/cpu/armv7/sunxi/Makefile +++ b/arch/arm/cpu/armv7/sunxi/Makefile @@ -9,5 +9,16 @@ # obj-y += timer.o obj-y += dram.o +obj-y += board.o obj-y += clock.o obj-y += pinmux.o + +ifndef CONFIG_SPL_BUILD +obj-y += cpu_info.o +endif + +ifdef CONFIG_SPL_BUILD +ifdef CONFIG_SPL_FEL +obj-y += start.o +endif +endif diff --git a/arch/arm/cpu/armv7/sunxi/board.c b/arch/arm/cpu/armv7/sunxi/board.c new file mode 100644 index 0000000..4a29b4b --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/board.c @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2012 Henrik Nordstrom henrik@henriknordstrom.net + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie tangliang@allwinnertech.com + * + * Some init for sunxi platform. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <serial.h> +#ifdef CONFIG_SPL_BUILD +#include <spl.h> +#endif +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/gpio.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/timer.h> + +#ifdef CONFIG_SPL_BUILD +/* Pointer to the global data structure for SPL */ +DECLARE_GLOBAL_DATA_PTR; + +/* The sunxi internal brom will try to loader external bootloader + * from mmc0, nand flash, mmc2. + * Unfortunately we can't check how SPL was loaded so assume + * it's always the first SD/MMC controller + */ +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_MMC1; +} + +/* No confirmation data available in SPL yet. Hardcode bootmode */ +u32 spl_boot_mode(void) +{ + return MMCSD_MODE_RAW; +} +#endif + +int gpio_init(void) +{ + sunxi_gpio_set_cfgpin(SUNXI_GPB(22), SUN4I_GPB22_UART0_TX); + sunxi_gpio_set_cfgpin(SUNXI_GPB(23), SUN4I_GPB23_UART0_RX); + sunxi_gpio_set_pull(SUNXI_GPB(23), 1); + + return 0; +} + +void reset_cpu(ulong addr) +{ +} + +/* do some early init */ +void s_init(void) +{ +#if !defined CONFIG_SPL_BUILD && defined CONFIG_SUN7I + /* Enable SMP mode for CPU0, by setting bit 6 of Auxiliary Ctl reg */ + asm volatile( + "mrc p15, 0, r0, c1, c0, 1\n" + "orr r0, r0, #0x40\n" + "mcr p15, 0, r0, c1, c0, 1\n"); +#endif + + clock_init(); + timer_init(); + gpio_init(); + +#ifdef CONFIG_SPL_BUILD + gd = &gdata; + preloader_console_init(); + + sunxi_board_init(); +#endif +} + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif diff --git a/arch/arm/cpu/armv7/sunxi/cpu_info.c b/arch/arm/cpu/armv7/sunxi/cpu_info.c new file mode 100644 index 0000000..b4c3d5c --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/cpu_info.c @@ -0,0 +1,19 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie tangliang@allwinnertech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/cpu.h> + +#ifdef CONFIG_DISPLAY_CPUINFO +int print_cpuinfo(void) +{ + puts("CPU: Allwinner A20 (SUN7I)\n"); + return 0; +} +#endif diff --git a/arch/arm/cpu/armv7/sunxi/start.c b/arch/arm/cpu/armv7/sunxi/start.c new file mode 100644 index 0000000..6b392fa --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/start.c @@ -0,0 +1 @@ +/* Intentionally empty. Only needed to get FEL SPL link line right */ diff --git a/arch/arm/include/asm/arch-sunxi/cpu.h b/arch/arm/include/asm/arch-sunxi/cpu.h new file mode 100644 index 0000000..9330058 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/cpu.h @@ -0,0 +1,122 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie tangliang@allwinnertech.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_CPU_H +#define _SUNXI_CPU_H + +#define SUNXI_SRAM_A1_BASE 0x00000000 +#define SUNXI_SRAM_A1_SIZE (16 * 1024) /* 16 kiB */ + +#define SUNXI_SRAM_A2_BASE 0x00004000 /* 16 kiB */ +#define SUNXI_SRAM_A3_BASE 0x00008000 /* 13 kiB */ +#define SUNXI_SRAM_A4_BASE 0x0000b400 /* 3 kiB */ +#define SUNXI_SRAM_D_BASE 0x01c00000 +#define SUNXI_SRAM_B_BASE 0x01c00000 /* 64 kiB (secure) */ + +#define SUNXI_SRAMC_BASE 0x01c00000 +#define SUNXI_DRAMC_BASE 0x01c01000 +#define SUNXI_DMA_BASE 0x01c02000 +#define SUNXI_NFC_BASE 0x01c03000 +#define SUNXI_TS_BASE 0x01c04000 +#define SUNXI_SPI0_BASE 0x01c05000 +#define SUNXI_SPI1_BASE 0x01c06000 +#define SUNXI_MS_BASE 0x01c07000 +#define SUNXI_TVD_BASE 0x01c08000 +#define SUNXI_CSI0_BASE 0x01c09000 +#define SUNXI_TVE0_BASE 0x01c0a000 +#define SUNXI_EMAC_BASE 0x01c0b000 +#define SUNXI_LCD0_BASE 0x01c0C000 +#define SUNXI_LCD1_BASE 0x01c0d000 +#define SUNXI_VE_BASE 0x01c0e000 +#define SUNXI_MMC0_BASE 0x01c0f000 +#define SUNXI_MMC1_BASE 0x01c10000 +#define SUNXI_MMC2_BASE 0x01c11000 +#define SUNXI_MMC3_BASE 0x01c12000 +#define SUNXI_USB0_BASE 0x01c13000 +#define SUNXI_USB1_BASE 0x01c14000 +#define SUNXI_SS_BASE 0x01c15000 +#define SUNXI_HDMI_BASE 0x01c16000 +#define SUNXI_SPI2_BASE 0x01c17000 +#define SUNXI_SATA_BASE 0x01c18000 +#define SUNXI_PATA_BASE 0x01c19000 +#define SUNXI_ACE_BASE 0x01c1a000 +#define SUNXI_TVE1_BASE 0x01c1b000 +#define SUNXI_USB2_BASE 0x01c1c000 +#define SUNXI_CSI1_BASE 0x01c1d000 +#define SUNXI_TZASC_BASE 0x01c1e000 +#define SUNXI_SPI3_BASE 0x01c1f000 + +#define SUNXI_CCM_BASE 0x01c20000 +#define SUNXI_INTC_BASE 0x01c20400 +#define SUNXI_PIO_BASE 0x01c20800 +#define SUNXI_TIMER_BASE 0x01c20c00 +#define SUNXI_SPDIF_BASE 0x01c21000 +#define SUNXI_AC97_BASE 0x01c21400 +#define SUNXI_IR0_BASE 0x01c21800 +#define SUNXI_IR1_BASE 0x01c21c00 + +#define SUNXI_IIS_BASE 0x01c22400 +#define SUNXI_LRADC_BASE 0x01c22800 +#define SUNXI_AD_DA_BASE 0x01c22c00 +#define SUNXI_KEYPAD_BASE 0x01c23000 +#define SUNXI_TZPC_BASE 0x01c23400 +#define SUNXI_SID_BASE 0x01c23800 +#define SUNXI_SJTAG_BASE 0x01c23c00 + +#define SUNXI_TP_BASE 0x01c25000 +#define SUNXI_PMU_BASE 0x01c25400 +#define SUNXI_CPUCFG_BASE 0x01c25c00 /* sun7i only ? */ + +#define SUNXI_UART0_BASE 0x01c28000 +#define SUNXI_UART1_BASE 0x01c28400 +#define SUNXI_UART2_BASE 0x01c28800 +#define SUNXI_UART3_BASE 0x01c28c00 +#define SUNXI_UART4_BASE 0x01c29000 +#define SUNXI_UART5_BASE 0x01c29400 +#define SUNXI_UART6_BASE 0x01c29800 +#define SUNXI_UART7_BASE 0x01c29c00 +#define SUNXI_PS2_0_BASE 0x01c2a000 +#define SUNXI_PS2_1_BASE 0x01c2a400 + +#define SUNXI_TWI0_BASE 0x01c2ac00 +#define SUNXI_TWI1_BASE 0x01c2b000 +#define SUNXI_TWI2_BASE 0x01c2b400 + +#define SUNXI_CAN_BASE 0x01c2bc00 + +#define SUNXI_SCR_BASE 0x01c2c400 + +#define SUNXI_GPS_BASE 0x01c30000 +#define SUNXI_MALI400_BASE 0x01c40000 +#define SUNXI_GMAC_BASE 0x01c50000 + +/* module sram */ +#define SUNXI_SRAM_C_BASE 0x01d00000 + +#define SUNXI_DE_FE0_BASE 0x01e00000 +#define SUNXI_DE_FE1_BASE 0x01e20000 +#define SUNXI_DE_BE0_BASE 0x01e60000 +#define SUNXI_DE_BE1_BASE 0x01e40000 +#define SUNXI_MP_BASE 0x01e80000 +#define SUNXI_AVG_BASE 0x01ea0000 + +/* CoreSight Debug Module */ +#define SUNXI_CSDM_BASE 0x3f500000 + +#define SUNXI_DDRII_DDRIII_BASE 0x40000000 /* 2 GiB */ + +#define SUNXI_BROM_BASE 0xffff0000 /* 32 kiB */ + +#define SUNXI_CPU_CFG (SUNXI_TIMER_BASE + 0x13c) + +#ifndef __ASSEMBLY__ +void sunxi_board_init(void); +extern void sunxi_reset(void); +#endif /* __ASSEMBLY__ */ + +#endif /* _CPU_H */ diff --git a/board/sunxi/Makefile b/board/sunxi/Makefile new file mode 100644 index 0000000..559112e --- /dev/null +++ b/board/sunxi/Makefile @@ -0,0 +1,11 @@ +# +# (C) Copyright 2012 Henrik Nordstrom henrik@henriknordstrom.net +# +# Based on some other board Makefile +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd@denx.de. +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-y += board.o diff --git a/board/sunxi/board.c b/board/sunxi/board.c new file mode 100644 index 0000000..328334a --- /dev/null +++ b/board/sunxi/board.c @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2012-2013 Henrik Nordstrom henrik@henriknordstrom.net + * (C) Copyright 2013 Luke Kenneth Casson Leighton lkcl@lkcl.net + * + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie tangliang@allwinnertech.com + * + * Some board init for the Allwinner A10-evb board. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/clock.h> +#include <asm/arch/dram.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* add board specific code here */ +int board_init(void) +{ + int id_pfr1; + + gd->bd->bi_boot_params = (PHYS_SDRAM_0 + 0x100); + + asm volatile("mrc p15, 0, %0, c0, c1, 1" : "=r"(id_pfr1)); + debug("id_pfr1: 0x%08x\n", id_pfr1); + /* Generic Timer Extension available? */ + if ((id_pfr1 >> 16) & 0xf) { + debug("Setting CNTFRQ\n"); + /* CNTFRQ == 24 MHz */ + asm volatile("mcr p15, 0, %0, c14, c0, 0" : : "r"(24000000)); + } + + return 0; +} + +int dram_init(void) +{ + gd->ram_size = get_ram_size((long *)PHYS_SDRAM_0, PHYS_SDRAM_0_SIZE); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +void sunxi_board_init(void) +{ + unsigned long ramsize; + + printf("DRAM:"); + ramsize = sunxi_dram_init(); + printf(" %lu MiB\n", ramsize >> 20); + if (!ramsize) + hang(); +} +#endif

Signed-off-by: Oliver Schinagl oliver@schinagl.nl Signed-off-by: Ian Campbell ijc@hellion.org.uk Reviewed-by: Tom Rini trini@ti.com --- v2: Based on u-boot-sunxi.git#sunxi d9aa5dd3d15c "sunxi: mmc: checkpatch whitespace fixes" with v2014.04-rc2 merged in.

v1: Based on u-boot-sunxi.git#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in ldscripts" vs v2014.01. --- board/sunxi/dram_cubietruck.c | 31 +++++++++++++++++++++++++++++++ boards.cfg | 1 + 2 files changed, 32 insertions(+) create mode 100644 board/sunxi/dram_cubietruck.c

diff --git a/board/sunxi/dram_cubietruck.c b/board/sunxi/dram_cubietruck.c new file mode 100644 index 0000000..1e7c94a --- /dev/null +++ b/board/sunxi/dram_cubietruck.c @@ -0,0 +1,31 @@ +/* this file is generated, don't edit it yourself */ + +#include <common.h> +#include <asm/arch/dram.h> + +static struct dram_para dram_para = { + .clock = 432, + .type = 3, + .rank_num = 1, + .density = 8192, + .io_width = 16, + .bus_width = 32, + .cas = 9, + .zq = 0x7f, + .odt_en = 0, + .size = 2048, + .tpr0 = 0x42d899b7, + .tpr1 = 0xa090, + .tpr2 = 0x22a00, + .tpr3 = 0x0, + .tpr4 = 0x1, + .tpr5 = 0x0, + .emr1 = 0x4, + .emr2 = 0x10, + .emr3 = 0x0, +}; + +unsigned long sunxi_dram_init(void) +{ + return dramc_init(&dram_para); +} diff --git a/boards.cfg b/boards.cfg index a32f46b..031da3d 100644 --- a/boards.cfg +++ b/boards.cfg @@ -366,6 +366,7 @@ Active arm armv7 rmobile renesas lager Active arm armv7 s5pc1xx samsung goni s5p_goni - Mateusz Zalega m.zalega@samsung.com Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang mk7.kang@samsung.com Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - +Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL - Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier mathieu.poirier@linaro.org Active arm armv7 u8500 st-ericsson u8500 u8500_href - - Active arm armv7 vf610 freescale vf610twr vf610twr vf610twr:IMX_CONFIG=board/freescale/vf610twr/imximage.cfg Alison Wang b18965@freescale.com

As well as the following signed-off-by the sunxi branch shows commits to these files authored by the following: Stefan Roese Tom Cubie yemao

Signed-off-by: Henrik Nordstrom henrik@henriknordstrom.net Signed-off-by: Luke Leighton lkcl@lkcl.net Signed-off-by: Oliver Schinagl oliver@schinagl.nl Signed-off-by: Wills Wang wills.wang.open@gmail.com Signed-off-by: Ian Campbell ijc@hellion.org.uk Cc: Pantelis Antoniou panto@antoniou-consulting.com --- Pantelis, most of your review comments have been addressed but not all, in particular the timeout loops aren't sorted yet, but I wanted to get the rest of the series reposted.

v2: Based on u-boot-sunxi.git#sunxi d9aa5dd3d15c "sunxi: mmc: checkpatch whitespace fixes" with v2014.04-rc2 merged in: - use proper gpio interfaces, removing awkward casts and some magic numbers. - remove magic numbers - other cleanups

v1: Based on linux-sunxi#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in ldscripts" vs v2014.01. --- arch/arm/include/asm/arch-sunxi/mmc.h | 124 +++++++ board/sunxi/board.c | 13 + drivers/mmc/Makefile | 1 + drivers/mmc/sunxi_mmc.c | 625 ++++++++++++++++++++++++++++++++++ include/configs/sunxi-common.h | 11 + 5 files changed, 774 insertions(+) create mode 100644 arch/arm/include/asm/arch-sunxi/mmc.h create mode 100644 drivers/mmc/sunxi_mmc.c

diff --git a/arch/arm/include/asm/arch-sunxi/mmc.h b/arch/arm/include/asm/arch-sunxi/mmc.h new file mode 100644 index 0000000..97b14c3 --- /dev/null +++ b/arch/arm/include/asm/arch-sunxi/mmc.h @@ -0,0 +1,124 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Aaron leafy.myeh@allwinnertech.com + * + * MMC register definition for allwinner sunxi platform. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _SUNXI_MMC_H +#define _SUNXI_MMC_H + +#include <linux/types.h> + +struct sunxi_mmc { + u32 gctrl; /* (0x00) SMC Global Control Register */ + u32 clkcr; /* (0x04) SMC Clock Control Register */ + u32 timeout; /* (0x08) SMC Time Out Register */ + u32 width; /* (0x0c) SMC Bus Width Register */ + u32 blksz; /* (0x10) SMC Block Size Register */ + u32 bytecnt; /* (0x14) SMC Byte Count Register */ + u32 cmd; /* (0x18) SMC Command Register */ + u32 arg; /* (0x1c) SMC Argument Register */ + u32 resp0; /* (0x20) SMC Response Register 0 */ + u32 resp1; /* (0x24) SMC Response Register 1 */ + u32 resp2; /* (0x28) SMC Response Register 2 */ + u32 resp3; /* (0x2c) SMC Response Register 3 */ + u32 imask; /* (0x30) SMC Interrupt Mask Register */ + u32 mint; /* (0x34) SMC Masked Interrupt Status Reg */ + u32 rint; /* (0x38) SMC Raw Interrupt Status Register */ + u32 status; /* (0x3c) SMC Status Register */ + u32 ftrglevel; /* (0x40) SMC FIFO Threshold Watermark Reg */ + u32 funcsel; /* (0x44) SMC Function Select Register */ + u32 cbcr; /* (0x48) SMC CIU Byte Count Register */ + u32 bbcr; /* (0x4c) SMC BIU Byte Count Register */ + u32 dbgc; /* (0x50) SMC Debug Enable Register */ + u32 res0[11]; /* (0x54~0x7c) */ + u32 dmac; /* (0x80) SMC IDMAC Control Register */ + u32 dlba; /* (0x84) SMC IDMAC Descr List Base Addr Reg */ + u32 idst; /* (0x88) SMC IDMAC Status Register */ + u32 idie; /* (0x8c) SMC IDMAC Interrupt Enable Register */ + u32 chda; /* (0x90) */ + u32 cbda; /* (0x94) */ + u32 res1[26]; /* (0x98~0xff) */ + u32 fifo; /* (0x100) SMC FIFO Access Address */ +}; + +#define SUNXI_MMC_CLK_POWERSAVE (0x1 << 17) +#define SUNXI_MMC_CLK_ENABLE (0x1 << 16) +#define SUNXI_MMC_CLK_DIVIDER_MASK (0xff) + +#define SUNXI_MMC_GCTRL_SOFT_RESET (0x1 << 0) +#define SUNXI_MMC_GCTRL_FIFO_RESET (0x1 << 1) +#define SUNXI_MMC_GCTRL_DMA_RESET (0x1 << 2) +#define SUNXI_MMC_GCTRL_RESET (SUNXI_MMC_GCTRL_SOFT_RESET|\ + SUNXI_MMC_GCTRL_FIFO_RESET|\ + SUNXI_MMC_GCTRL_DMA_RESET) +#define SUNXI_MMC_GCTRL_DMA_ENABLE (0x1 << 5) +#define SUNXI_MMC_GCTRL_ACCESS_BY_AHB (0x1 << 31) + +#define SUNXI_MMC_CMD_RESP_EXPIRE (0x1 << 6) +#define SUNXI_MMC_CMD_LONG_RESPONSE (0x1 << 7) +#define SUNXI_MMC_CMD_CHK_RESPONSE_CRC (0x1 << 8) +#define SUNXI_MMC_CMD_DATA_EXPIRE (0x1 << 9) +#define SUNXI_MMC_CMD_WRITE (0x1 << 10) +#define SUNXI_MMC_CMD_AUTO_STOP (0x1 << 12) +#define SUNXI_MMC_CMD_WAIT_PRE_OVER (0x1 << 13) +#define SUNXI_MMC_CMD_SEND_INIT_SEQ (0x1 << 15) +#define SUNXI_MMC_CMD_UPCLK_ONLY (0x1 << 21) +#define SUNXI_MMC_CMD_START (0x1 << 31) + +#define SUNXI_MMC_RINT_RESP_ERROR (0x1 << 1) +#define SUNXI_MMC_RINT_COMMAND_DONE (0x1 << 2) +#define SUNXI_MMC_RINT_DATA_OVER (0x1 << 3) +#define SUNXI_MMC_RINT_TX_DATA_REQUEST (0x1 << 4) +#define SUNXI_MMC_RINT_RX_DATA_REQUEST (0x1 << 5) +#define SUNXI_MMC_RINT_RESP_CRC_ERROR (0x1 << 6) +#define SUNXI_MMC_RINT_DATA_CRC_ERROR (0x1 << 7) +#define SUNXI_MMC_RINT_RESP_TIMEOUT (0x1 << 8) +#define SUNXI_MMC_RINT_DATA_TIMEOUT (0x1 << 9) +#define SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE (0x1 << 10) +#define SUNXI_MMC_RINT_FIFO_RUN_ERROR (0x1 << 11) +#define SUNXI_MMC_RINT_HARD_WARE_LOCKED (0x1 << 12) +#define SUNXI_MMC_RINT_START_BIT_ERROR (0x1 << 13) +#define SUNXI_MMC_RINT_AUTO_COMMAND_DONE (0x1 << 14) +#define SUNXI_MMC_RINT_END_BIT_ERROR (0x1 << 15) +#define SUNXI_MMC_RINT_SDIO_INTERRUPT (0x1 << 16) +#define SUNXI_MMC_RINT_CARD_INSERT (0x1 << 30) +#define SUNXI_MMC_RINT_CARD_REMOVE (0x1 << 31) +#define SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT \ + (SUNXI_MMC_RINT_RESP_ERROR | \ + SUNXI_MMC_RINT_RESP_CRC_ERROR | \ + SUNXI_MMC_RINT_DATA_CRC_ERROR | \ + SUNXI_MMC_RINT_RESP_TIMEOUT | \ + SUNXI_MMC_RINT_DATA_TIMEOUT | \ + SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE | \ + SUNXI_MMC_RINT_FIFO_RUN_ERROR | \ + SUNXI_MMC_RINT_HARD_WARE_LOCKED | \ + SUNXI_MMC_RINT_START_BIT_ERROR | \ + SUNXI_MMC_RINT_END_BIT_ERROR) /* 0xbfc2 */ +#define SUNXI_MMC_RINT_INTERRUPT_DONE_BIT \ + (SUNXI_MMC_RINT_AUTO_COMMAND_DONE | \ + SUNXI_MMC_RINT_DATA_OVER | \ + SUNXI_MMC_RINT_COMMAND_DONE | \ + SUNXI_MMC_RINT_VOLTAGE_CHANGE_DONE) + +#define SUNXI_MMC_STATUS_RXWL_FLAG (0x1 << 0) +#define SUNXI_MMC_STATUS_TXWL_FLAG (0x1 << 1) +#define SUNXI_MMC_STATUS_FIFO_EMPTY (0x1 << 2) +#define SUNXI_MMC_STATUS_FIFO_FULL (0x1 << 3) +#define SUNXI_MMC_STATUS_CARD_PRESENT (0x1 << 8) +#define SUNXI_MMC_STATUS_CARD_DATA_BUSY (0x1 << 9) +#define SUNXI_MMC_STATUS_DATA_FSM_BUSY (0x1 << 10) + +#define SUNXI_MMC_IDMAC_RESET (0x1 << 0) +#define SUNXI_MMC_IDMAC_FIXBURST (0x1 << 1) +#define SUNXI_MMC_IDMAC_ENABLE (0x1 << 7) + +#define SUNXI_MMC_IDIE_TXIRQ (0x1 << 0) +#define SUNXI_MMC_IDIE_RXIRQ (0x1 << 1) + +int sunxi_mmc_init(int sdc_no); +#endif /* _SUNXI_MMC_H */ diff --git a/board/sunxi/board.c b/board/sunxi/board.c index 328334a..06c9264 100644 --- a/board/sunxi/board.c +++ b/board/sunxi/board.c @@ -14,6 +14,7 @@ #include <common.h> #include <asm/arch/clock.h> #include <asm/arch/dram.h> +#include <asm/arch/mmc.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -43,6 +44,18 @@ int dram_init(void) return 0; }

+#ifdef CONFIG_GENERIC_MMC +int board_mmc_init(bd_t *bis) +{ + sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT); +#if !defined (CONFIG_SPL_BUILD) && defined (CONFIG_MMC_SUNXI_SLOT_EXTRA) + sunxi_mmc_init(CONFIG_MMC_SUNXI_SLOT_EXTRA); +#endif + + return 0; +} +#endif + #ifdef CONFIG_SPL_BUILD void sunxi_board_init(void) { diff --git a/drivers/mmc/Makefile b/drivers/mmc/Makefile index 931922b..5e67098 100644 --- a/drivers/mmc/Makefile +++ b/drivers/mmc/Makefile @@ -28,6 +28,7 @@ obj-$(CONFIG_SPEAR_SDHCI) += spear_sdhci.o obj-$(CONFIG_TEGRA_MMC) += tegra_mmc.o obj-$(CONFIG_DWMMC) += dw_mmc.o obj-$(CONFIG_EXYNOS_DWMMC) += exynos_dw_mmc.o +obj-$(CONFIG_MMC_SUNXI) += sunxi_mmc.o obj-$(CONFIG_ZYNQ_SDHCI) += zynq_sdhci.o obj-$(CONFIG_SOCFPGA_DWMMC) += socfpga_dw_mmc.o ifdef CONFIG_SPL_BUILD diff --git a/drivers/mmc/sunxi_mmc.c b/drivers/mmc/sunxi_mmc.c new file mode 100644 index 0000000..bb31e05 --- /dev/null +++ b/drivers/mmc/sunxi_mmc.c @@ -0,0 +1,625 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Aaron leafy.myeh@allwinnertech.com + * + * MMC driver for allwinner sunxi platform. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <malloc.h> +#include <mmc.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cpu.h> +#include <asm/arch/gpio.h> +#include <asm/arch/mmc.h> + +static void dumphex32(char *name, char *base, int len) +{ + __u32 i; + + debug("dump %s registers:", name); + for (i = 0; i < len; i += 4) { + if (!(i & 0xf)) + debug("\n0x%p : ", base + i); + debug("0x%08x ", readl(base + i)); + } + debug("\n"); +} + +static void dumpmmcreg(struct sunxi_mmc *reg) +{ + debug("dump mmc registers:\n"); + debug("gctrl 0x%08x\n", reg->gctrl); + debug("clkcr 0x%08x\n", reg->clkcr); + debug("timeout 0x%08x\n", reg->timeout); + debug("width 0x%08x\n", reg->width); + debug("blksz 0x%08x\n", reg->blksz); + debug("bytecnt 0x%08x\n", reg->bytecnt); + debug("cmd 0x%08x\n", reg->cmd); + debug("arg 0x%08x\n", reg->arg); + debug("resp0 0x%08x\n", reg->resp0); + debug("resp1 0x%08x\n", reg->resp1); + debug("resp2 0x%08x\n", reg->resp2); + debug("resp3 0x%08x\n", reg->resp3); + debug("imask 0x%08x\n", reg->imask); + debug("mint 0x%08x\n", reg->mint); + debug("rint 0x%08x\n", reg->rint); + debug("status 0x%08x\n", reg->status); + debug("ftrglevel 0x%08x\n", reg->ftrglevel); + debug("funcsel 0x%08x\n", reg->funcsel); + debug("dmac 0x%08x\n", reg->dmac); + debug("dlba 0x%08x\n", reg->dlba); + debug("idst 0x%08x\n", reg->idst); + debug("idie 0x%08x\n", reg->idie); +} + +struct sunxi_mmc_des { + u32 reserved1_1:1; + u32 dic:1; /* disable interrupt on completion */ + u32 last_des:1; /* 1-this data buffer is the last buffer */ + u32 first_des:1; /* 1-data buffer is the first buffer, + 0-data buffer contained in the next + descriptor is 1st buffer */ + u32 des_chain:1; /* 1-the 2nd address in the descriptor is the + next descriptor address */ + u32 end_of_ring:1; /* 1-last descriptor flag when using dual + data buffer in descriptor */ + u32 reserved1_2:24; + u32 card_err_sum:1; /* transfer error flag */ + u32 own:1; /* des owner:1-idma owns it, 0-host owns it */ +#define SDXC_DES_NUM_SHIFT 16 +#define SDXC_DES_BUFFER_MAX_LEN (1 << SDXC_DES_NUM_SHIFT) + u32 data_buf1_sz:16; + u32 data_buf2_sz:16; + u32 buf_addr_ptr1; + u32 buf_addr_ptr2; +}; + +struct sunxi_mmc_host { + unsigned mmc_no; + uint32_t *mclkreg; + unsigned database; + unsigned fatal_err; + unsigned mod_clk; + struct sunxi_mmc *reg; +}; + +/* support 4 mmc hosts */ +struct mmc mmc_dev[4]; +struct sunxi_mmc_host mmc_host[4]; + +static int mmc_resource_init(int sdc_no) +{ + struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no]; + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + debug("init mmc %d resource\n", sdc_no); + + switch (sdc_no) { + case 0: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC0_BASE; + mmchost->mclkreg = &ccm->sd0_clk_cfg; + break; + case 1: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC1_BASE; + mmchost->mclkreg = &ccm->sd1_clk_cfg; + break; + case 2: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC2_BASE; + mmchost->mclkreg = &ccm->sd2_clk_cfg; + break; + case 3: + mmchost->reg = (struct sunxi_mmc *)SUNXI_MMC3_BASE; + mmchost->mclkreg = &ccm->sd3_clk_cfg; + break; + default: + printf("Wrong mmc number %d\n", sdc_no); + return -1; + } + mmchost->database = (unsigned int)mmchost->reg + 0x100; + mmchost->mmc_no = sdc_no; + + return 0; +} + +static int mmc_clk_io_on(int sdc_no) +{ + unsigned int pin; + unsigned int rval; + unsigned int pll5_clk; + unsigned int divider; + struct sunxi_mmc_host *mmchost = &mmc_host[sdc_no]; + struct sunxi_ccm_reg *ccm = (struct sunxi_ccm_reg *)SUNXI_CCM_BASE; + + debug("init mmc %d clock and io\n", sdc_no); + + /* config gpio */ + switch (sdc_no) { + case 0: + /* D1-PF0, D0-PF1, CLK-PF2, CMD-PF3, D3-PF4, D4-PF5 */ + for (pin = SUNXI_GPF(0); pin <= SUNXI_GPF(5); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPF0_SDC0); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + break; + + case 1: +#if CONFIG_MMC1_PG + /* PG0-CMD, PG1-CLK, PG2~5-D0~3 : 4 */ + for (pin = SUNXI_GPG(0); pin <= SUNXI_GPG(5); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN4I_GPG0_SDC1); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } +#else + /* PH22-CMD, PH23-CLK, PH24~27-D0~D3 : 5 */ + for (pin = SUNXI_GPH(22); pin <= SUNXI_GPH(27); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN4I_GPH22_SDC1); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } +#endif + break; + + case 2: + /* CMD-PC6, CLK-PC7, D0-PC8, D1-PC9, D2-PC10, D3-PC11 */ + for (pin = SUNXI_GPC(6); pin <= SUNXI_GPC(11); pin++) { + sunxi_gpio_set_cfgpin(pin, SUNXI_GPC6_SDC2); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + break; + + case 3: + /* PI4-CMD, PI5-CLK, PI6~9-D0~D3 : 2 */ + for (pin = SUNXI_GPI(4); pin <= SUNXI_GPI(9); pin++) { + sunxi_gpio_set_cfgpin(pin, SUN4I_GPI4_SDC3); + sunxi_gpio_set_pull(pin, SUNXI_GPIO_PULL_UP); + sunxi_gpio_set_drv(pin, 2); + } + break; + + default: + return -1; + } + + /* config ahb clock */ + rval = readl(&ccm->ahb_gate0); + rval |= 1 << AHB_GATE_OFFSET_MMC(sdc_no); + writel(rval, &ccm->ahb_gate0); + + /* config mod clock */ + pll5_clk = clock_get_pll5(); + if (pll5_clk > 400000000) + divider = 4; + else + divider = 3; + writel(CCM_MMC_CTRL_ENABLE | CCM_MMC_CTRL_PLL5 | divider, + mmchost->mclkreg); + mmchost->mod_clk = pll5_clk / (divider + 1); + + dumphex32("ccmu", (char *)SUNXI_CCM_BASE, 0x100); + dumphex32("gpio", (char *)SUNXI_PIO_BASE, 0x100); + dumphex32("mmc", (char *)mmchost->reg, 0x100); + dumpmmcreg(mmchost->reg); + + return 0; +} + +static int mmc_update_clk(struct mmc *mmc) +{ + struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv; + unsigned int cmd; + unsigned timeout = 0xfffff; + + cmd = SUNXI_MMC_CMD_START | + SUNXI_MMC_CMD_UPCLK_ONLY | + SUNXI_MMC_CMD_WAIT_PRE_OVER; + writel(cmd, &mmchost->reg->cmd); + while ((readl(&mmchost->reg->cmd) & SUNXI_MMC_CMD_START) && timeout--) + ; + if (!timeout) + return -1; + + /* clock update sets various irq status bits, clear these */ + writel(readl(&mmchost->reg->rint), &mmchost->reg->rint); + + return 0; +} + +static int mmc_config_clock(struct mmc *mmc, unsigned div) +{ + struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv; + unsigned rval = readl(&mmchost->reg->clkcr); + + /* Disable Clock */ + rval &= ~SUNXI_MMC_CLK_ENABLE; + writel(rval, &mmchost->reg->clkcr); + if (mmc_update_clk(mmc)) + return -1; + + /* Change Divider Factor */ + rval &= ~SUNXI_MMC_CLK_DIVIDER_MASK; + rval |= div; + writel(rval, &mmchost->reg->clkcr); + if (mmc_update_clk(mmc)) + return -1; + /* Re-enable Clock */ + rval |= SUNXI_MMC_CLK_ENABLE; + writel(rval, &mmchost->reg->clkcr); + + if (mmc_update_clk(mmc)) + return -1; + + return 0; +} + +static void mmc_set_ios(struct mmc *mmc) +{ + struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv; + unsigned int clkdiv = 0; + + debug("set ios: bus_width: %x, clock: %d, mod_clk: %d\n", + mmc->bus_width, mmc->clock, mmchost->mod_clk); + + /* Change clock first */ + clkdiv = (mmchost->mod_clk + (mmc->clock >> 1)) / mmc->clock / 2; + if (mmc->clock) { + if (mmc_config_clock(mmc, clkdiv)) { + mmchost->fatal_err = 1; + return; + } + } + + /* Change bus width */ + if (mmc->bus_width == 8) + writel(0x2, &mmchost->reg->width); + else if (mmc->bus_width == 4) + writel(0x1, &mmchost->reg->width); + else + writel(0x0, &mmchost->reg->width); +} + +static int mmc_core_init(struct mmc *mmc) +{ + struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv; + + /* Reset controller */ + writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl); + + return 0; +} + +static int mmc_trans_data_by_cpu(struct mmc *mmc, struct mmc_data *data) +{ + struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv; + unsigned i; + unsigned byte_cnt = data->blocksize * data->blocks; + unsigned *buff; + unsigned timeout = 0xfffff; + + if (data->flags & MMC_DATA_READ) { + buff = (unsigned int *)data->dest; + for (i = 0; i < (byte_cnt >> 2); i++) { + while (--timeout && + (readl(&mmchost->reg->status) & + SUNXI_MMC_STATUS_FIFO_EMPTY)) + ; + if (timeout <= 0) + goto out; + buff[i] = readl(mmchost->database); + timeout = 0xfffff; + } + } else { + buff = (unsigned int *)data->src; + for (i = 0; i < (byte_cnt >> 2); i++) { + while (--timeout && + (readl(&mmchost->reg->status) & + SUNXI_MMC_STATUS_FIFO_FULL)) + ; + if (timeout <= 0) + goto out; + writel(buff[i], mmchost->database); + timeout = 0xfffff; + } + } + +out: + if (timeout <= 0) + return -1; + + return 0; +} + +static int mmc_trans_data_by_dma(struct mmc *mmc, struct mmc_data *data) +{ + struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv; + unsigned byte_cnt = data->blocksize * data->blocks; + unsigned char *buff; + unsigned des_idx = 0; + unsigned buff_frag_num = + (byte_cnt + SDXC_DES_BUFFER_MAX_LEN - 1) >> SDXC_DES_NUM_SHIFT; + unsigned remain; + unsigned i, rval; + ALLOC_CACHE_ALIGN_BUFFER(struct sunxi_mmc_des, pdes, buff_frag_num); + + buff = data->flags & MMC_DATA_READ ? + (unsigned char *)data->dest : (unsigned char *)data->src; + remain = byte_cnt & (SDXC_DES_BUFFER_MAX_LEN - 1); + if (!remain) + remain = SDXC_DES_BUFFER_MAX_LEN; + + flush_cache((unsigned long)buff, (unsigned long)byte_cnt); + for (i = 0; i < buff_frag_num; i++, des_idx++) { + memset((void *)&pdes[des_idx], 0, sizeof(struct sunxi_mmc_des)); + pdes[des_idx].des_chain = 1; + pdes[des_idx].own = 1; + pdes[des_idx].dic = 1; + if (buff_frag_num > 1 && i != buff_frag_num - 1) + pdes[des_idx].data_buf1_sz = + (SDXC_DES_BUFFER_MAX_LEN - + 1) & SDXC_DES_BUFFER_MAX_LEN; + else + pdes[des_idx].data_buf1_sz = remain; + + pdes[des_idx].buf_addr_ptr1 = + (u32) buff + i * SDXC_DES_BUFFER_MAX_LEN; + if (i == 0) + pdes[des_idx].first_des = 1; + + if (i == buff_frag_num - 1) { + pdes[des_idx].dic = 0; + pdes[des_idx].last_des = 1; + pdes[des_idx].end_of_ring = 1; + pdes[des_idx].buf_addr_ptr2 = 0; + } else { + pdes[des_idx].buf_addr_ptr2 = (u32)&pdes[des_idx + 1]; + } + debug("frag %d, remain %d, des[%d](%08x): ", + i, remain, des_idx, (u32)&pdes[des_idx]); + debug("[0] = %08x, [1] = %08x, [2] = %08x, [3] = %08x\n", + (u32)((u32 *)&pdes[des_idx])[0], + (u32)((u32 *)&pdes[des_idx])[1], + (u32)((u32 *)&pdes[des_idx])[2], + (u32)((u32 *)&pdes[des_idx])[3]); + } + flush_cache((unsigned long)pdes, + sizeof(struct sunxi_mmc_des) * (des_idx + 1)); + + rval = readl(&mmchost->reg->gctrl); + /* Enable DMA */ + writel(rval | SUNXI_MMC_GCTRL_DMA_RESET | SUNXI_MMC_GCTRL_DMA_ENABLE, + &mmchost->reg->gctrl); + /* Reset iDMA */ + writel(SUNXI_MMC_IDMAC_RESET, &mmchost->reg->dmac); + /* Enable iDMA */ + writel(SUNXI_MMC_IDMAC_FIXBURST | SUNXI_MMC_IDMAC_ENABLE, + &mmchost->reg->dmac); + rval = readl(&mmchost->reg->idie) & + ~(SUNXI_MMC_IDIE_TXIRQ|SUNXI_MMC_IDIE_RXIRQ); + if (data->flags & MMC_DATA_WRITE) + rval |= SUNXI_MMC_IDIE_TXIRQ; + else + rval |= SUNXI_MMC_IDIE_RXIRQ; + writel(rval, &mmchost->reg->idie); + writel((u32) pdes, &mmchost->reg->dlba); + writel((0x2 << 28) | (0x7 << 16) | (0x01 << 3), + &mmchost->reg->ftrglevel); + + return 0; +} + +static void mmc_enable_dma_accesses(struct mmc *mmc, int dma) +{ + struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv; + + unsigned int gctrl = readl(&mmchost->reg->gctrl); + if (dma) + gctrl &= ~SUNXI_MMC_GCTRL_ACCESS_BY_AHB; + else + gctrl |= SUNXI_MMC_GCTRL_ACCESS_BY_AHB; + writel(gctrl, &mmchost->reg->gctrl); +} + +static int mmc_rint_wait(struct mmc *mmc, signed int timeout, + unsigned int done_bit, const char *what) +{ + struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv; + unsigned int status; + + do { + status = readl(&mmchost->reg->rint); + if (!timeout-- || + (status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT)) { + debug("%s timeout %x\n", what, + status & SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT); + return TIMEOUT; + } + } while (!(status & done_bit)); + + return 0; +} + +static int mmc_send_cmd(struct mmc *mmc, struct mmc_cmd *cmd, + struct mmc_data *data) +{ + struct sunxi_mmc_host *mmchost = (struct sunxi_mmc_host *)mmc->priv; + unsigned int cmdval = SUNXI_MMC_CMD_START; + signed int timeout = 0; + int error = 0; + unsigned int status = 0; + unsigned int usedma = 0; + unsigned int bytecnt = 0; + + if (mmchost->fatal_err) + return -1; + if (cmd->resp_type & MMC_RSP_BUSY) + debug("mmc cmd %d check rsp busy\n", cmd->cmdidx); + if (cmd->cmdidx == 12) + return 0; + + if (!cmd->cmdidx) + cmdval |= SUNXI_MMC_CMD_SEND_INIT_SEQ; + if (cmd->resp_type & MMC_RSP_PRESENT) + cmdval |= SUNXI_MMC_CMD_RESP_EXPIRE; + if (cmd->resp_type & MMC_RSP_136) + cmdval |= SUNXI_MMC_CMD_LONG_RESPONSE; + if (cmd->resp_type & MMC_RSP_CRC) + cmdval |= SUNXI_MMC_CMD_CHK_RESPONSE_CRC; + + if (data) { + if ((u32) data->dest & 0x3) { + error = -1; + goto out; + } + + cmdval |= SUNXI_MMC_CMD_DATA_EXPIRE|SUNXI_MMC_CMD_WAIT_PRE_OVER; + if (data->flags & MMC_DATA_WRITE) + cmdval |= SUNXI_MMC_CMD_WRITE; + if (data->blocks > 1) + cmdval |= SUNXI_MMC_CMD_AUTO_STOP; + writel(data->blocksize, &mmchost->reg->blksz); + writel(data->blocks * data->blocksize, &mmchost->reg->bytecnt); + } + + debug("mmc %d, cmd %d(0x%08x), arg 0x%08x\n", mmchost->mmc_no, + cmd->cmdidx, cmdval | cmd->cmdidx, cmd->cmdarg); + writel(cmd->cmdarg, &mmchost->reg->arg); + + if (!data) + writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); + + /* + * transfer data and check status + * STATREG[2] : FIFO empty + * STATREG[3] : FIFO full + */ + if (data) { + int ret = 0; + + bytecnt = data->blocksize * data->blocks; + debug("trans data %d bytes\n", bytecnt); +#if defined(CONFIG_MMC_SUNXI_USE_DMA) && !defined(CONFIG_SPL_BUILD) + if (bytecnt > 64) { +#else + if (0) { +#endif + usedma = 1; + mmc_enable_dma_accesses(mmc, 1); + ret = mmc_trans_data_by_dma(mmc, data); + writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); + } else { + mmc_enable_dma_accesses(mmc, 0); + writel(cmdval | cmd->cmdidx, &mmchost->reg->cmd); + ret = mmc_trans_data_by_cpu(mmc, data); + } + if (ret) { + error = readl(&mmchost->reg->rint) & \ + SUNXI_MMC_RINT_INTERRUPT_ERROR_BIT; + error = TIMEOUT; + goto out; + } + } + + error = mmc_rint_wait(mmc, 0xfffff, SUNXI_MMC_RINT_COMMAND_DONE, "cmd"); + if (error) + goto out; + + if (data) { + timeout = usedma ? 0xffff * bytecnt : 0xffff; + debug("cacl timeout %x\n", timeout); + error = mmc_rint_wait(mmc, timeout, + data->blocks > 1 ? + SUNXI_MMC_RINT_AUTO_COMMAND_DONE : + SUNXI_MMC_RINT_DATA_OVER, + "data"); + if (error) + goto out; + } + + if (cmd->resp_type & MMC_RSP_BUSY) { + timeout = 0xfffff; + do { + status = readl(&mmchost->reg->status); + if (!timeout--) { + debug("busy timeout\n"); + error = TIMEOUT; + goto out; + } + } while (status & SUNXI_MMC_STATUS_CARD_DATA_BUSY); + } + + if (cmd->resp_type & MMC_RSP_136) { + cmd->response[0] = readl(&mmchost->reg->resp3); + cmd->response[1] = readl(&mmchost->reg->resp2); + cmd->response[2] = readl(&mmchost->reg->resp1); + cmd->response[3] = readl(&mmchost->reg->resp0); + debug("mmc resp 0x%08x 0x%08x 0x%08x 0x%08x\n", + cmd->response[3], cmd->response[2], + cmd->response[1], cmd->response[0]); + } else { + cmd->response[0] = readl(&mmchost->reg->resp0); + debug("mmc resp 0x%08x\n", cmd->response[0]); + } +out: + if (data && usedma) { + /* IDMASTAREG + * IDST[0] : idma tx int + * IDST[1] : idma rx int + * IDST[2] : idma fatal bus error + * IDST[4] : idma descriptor invalid + * IDST[5] : idma error summary + * IDST[8] : idma normal interrupt sumary + * IDST[9] : idma abnormal interrupt sumary + */ + status = readl(&mmchost->reg->idst); + writel(status, &mmchost->reg->idst); + writel(0, &mmchost->reg->idie); + writel(0, &mmchost->reg->dmac); + writel(readl(&mmchost->reg->gctrl) & ~SUNXI_MMC_GCTRL_DMA_ENABLE, + &mmchost->reg->gctrl); + } + if (error < 0) { + writel(SUNXI_MMC_GCTRL_RESET, &mmchost->reg->gctrl); + mmc_update_clk(mmc); + } + writel(0xffffffff, &mmchost->reg->rint); + writel(readl(&mmchost->reg->gctrl) | SUNXI_MMC_GCTRL_FIFO_RESET, + &mmchost->reg->gctrl); + + return error; +} + +int sunxi_mmc_init(int sdc_no) +{ + struct mmc *mmc; + + memset(&mmc_dev[sdc_no], 0, sizeof(struct mmc)); + memset(&mmc_host[sdc_no], 0, sizeof(struct sunxi_mmc_host)); + mmc = &mmc_dev[sdc_no]; + + sprintf(mmc->name, "SUNXI SD/MMC"); + mmc->priv = &mmc_host[sdc_no]; + mmc->send_cmd = mmc_send_cmd; + mmc->set_ios = mmc_set_ios; + mmc->init = mmc_core_init; + + mmc->voltages = MMC_VDD_32_33 | MMC_VDD_33_34; + mmc->host_caps = MMC_MODE_4BIT; + mmc->host_caps |= MMC_MODE_HS_52MHz | MMC_MODE_HS; + + mmc->f_min = 400000; + mmc->f_max = 52000000; + + mmc_resource_init(sdc_no); + mmc_clk_io_on(sdc_no); + + mmc_register(mmc); + + return 0; +} diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 1cb798d..ed70c4e 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -60,6 +60,16 @@ #define CONFIG_INITRD_TAG #define CONFIG_CMDLINE_EDITING

+/* mmc config */ +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_CMD_MMC +#define CONFIG_MMC_SUNXI +#define CONFIG_MMC_SUNXI_SLOT 0 +#define CONFIG_MMC_SUNXI_USE_DMA +#define CONFIG_ENV_IS_IN_MMC +#define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */ + /* * Size of malloc() pool * 1MB = 0x100000, 0x100000 = 1024 * 1024 @@ -102,6 +112,7 @@ #define CONFIG_SYS_MONITOR_LEN (512 << 10) /* 512 KiB */ #define CONFIG_IDENT_STRING " Allwinner Technology"

+#define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512) KiB */ #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */

#define CONFIG_EXTRA_ENV_SETTINGS \

As well as the following signed-off-by the sunxi branch shows commits to these files authored by the following: Henrik Nordstrom Tom Cubie

Signed-off-by: Stefan Roese sr@denx.de Signed-off-by: Ian Campbell ijc@hellion.org.uk --- v2: Based on u-boot-sunxi.git#sunxi d9aa5dd3d15c "sunxi: mmc: checkpatch whitespace fixes" with v2014.04-rc2 merged in: - mksunxiboot cleanups - rebase on Kbuild stuff

v1: Based on u-boot-sunxi.git#sunxi commit d854c4de2f57 "arm: Handle .gnu.hash section in ldscripts" vs v2014.01. --- Makefile | 10 +++ arch/arm/cpu/armv7/sunxi/config.mk | 8 ++ arch/arm/cpu/armv7/sunxi/u-boot-spl.lds | 52 +++++++++++ boards.cfg | 1 + include/configs/sunxi-common.h | 26 ++++++ spl/Makefile | 13 +++ tools/.gitignore | 1 + tools/Makefile | 2 + tools/mksunxiboot.README | 13 +++ tools/mksunxiboot.c | 153 ++++++++++++++++++++++++++++++++ 10 files changed, 279 insertions(+) create mode 100644 arch/arm/cpu/armv7/sunxi/config.mk create mode 100644 arch/arm/cpu/armv7/sunxi/u-boot-spl.lds create mode 100644 tools/mksunxiboot.README create mode 100644 tools/mksunxiboot.c

diff --git a/Makefile b/Makefile index b795338..31ea0ab 100644 --- a/Makefile +++ b/Makefile @@ -876,6 +876,13 @@ OBJCOPYFLAGS_u-boot.spr = -I binary -O binary --pad-to=$(CONFIG_SPL_PAD_TO) \ u-boot.spr: spl/u-boot-spl.img u-boot.img FORCE $(call if_changed,pad_cat)

+ifneq ($(CONFIG_SUNXI),) +OBJCOPYFLAGS_u-boot-sunxi-with-spl.bin = -I binary -O binary \ + --pad-to=$(CONFIG_SPL_PAD_TO) --gap-fill=0xff +u-boot-sunxi-with-spl.bin: spl/sunxi-spl.bin u-boot.img FORCE + $(call if_changed,pad_cat) +endif + ifneq ($(CONFIG_TEGRA),) OBJCOPYFLAGS_u-boot-nodtb-tegra.bin = -O binary --pad-to=$(CONFIG_SYS_TEXT_BASE) u-boot-nodtb-tegra.bin: spl/u-boot-spl u-boot.bin FORCE @@ -1087,6 +1094,9 @@ spl/u-boot-spl.bin: spl/u-boot-spl spl/u-boot-spl: tools prepare $(Q)$(MAKE) obj=spl -f $(srctree)/spl/Makefile all

+spl/sunxi-spl.bin: spl/u-boot-spl + @: + tpl/u-boot-tpl.bin: tools prepare $(Q)$(MAKE) obj=tpl -f $(srctree)/spl/Makefile all CONFIG_TPL_BUILD=y

diff --git a/arch/arm/cpu/armv7/sunxi/config.mk b/arch/arm/cpu/armv7/sunxi/config.mk new file mode 100644 index 0000000..00f5ffc --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/config.mk @@ -0,0 +1,8 @@ +# Build a combined spl + u-boot image +ifdef CONFIG_SPL +ifndef CONFIG_SPL_BUILD +ifndef CONFIG_SPL_FEL +ALL-y += u-boot-sunxi-with-spl.bin +endif +endif +endif diff --git a/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds new file mode 100644 index 0000000..5008028 --- /dev/null +++ b/arch/arm/cpu/armv7/sunxi/u-boot-spl.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2012 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie tangliang@allwinnertech.com + * + * Based on omap-common/u-boot-spl.lds: + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, garyj@denx.de + * + * (C) Copyright 2010 + * Texas Instruments, <www.ti.com> + * Aneesh V aneesh@ti.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ +MEMORY { .sram : ORIGIN = CONFIG_SPL_TEXT_BASE,\ + LENGTH = CONFIG_SPL_MAX_SIZE } +MEMORY { .sdram : ORIGIN = CONFIG_SPL_BSS_START_ADDR, \ + LENGTH = CONFIG_SPL_BSS_MAX_SIZE } + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + .text : + { + __start = .; + arch/arm/cpu/armv7/start.o (.text) + *(.text*) + } > .sram + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(.rodata*)) } >.sram + + . = ALIGN(4); + .data : { *(SORT_BY_ALIGNMENT(.data*)) } >.sram + + . = ALIGN(4); + __image_copy_end = .; + _end = .; + + .bss : + { + . = ALIGN(4); + __bss_start = .; + *(.bss*) + . = ALIGN(4); + __bss_end = .; + } > .sdram +} diff --git a/boards.cfg b/boards.cfg index 3134e9e..e8cdfbc 100644 --- a/boards.cfg +++ b/boards.cfg @@ -366,6 +366,7 @@ Active arm armv7 rmobile renesas lager Active arm armv7 s5pc1xx samsung goni s5p_goni - Mateusz Zalega m.zalega@samsung.com Active arm armv7 s5pc1xx samsung smdkc100 smdkc100 - Minkyu Kang mk7.kang@samsung.com Active arm armv7 socfpga altera socfpga socfpga_cyclone5 - - +Active arm armv7 sunxi - sunxi Cubietruck sun7i:CUBIETRUCK,SPL,SUNXI_GMAC,RGMII - Active arm armv7 sunxi - sunxi Cubietruck_FEL sun7i:CUBIETRUCK,SPL_FEL,SUNXI_GMAC,RGMII - Active arm armv7 u8500 st-ericsson snowball snowball - Mathieu Poirier mathieu.poirier@linaro.org Active arm armv7 u8500 st-ericsson u8500 u8500_href - - diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index ed70c4e..e6c2760 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -17,6 +17,11 @@ * High Level Configuration Options */ #define CONFIG_SUNXI /* sunxi family */ +#ifdef CONFIG_SPL_BUILD +#ifndef CONFIG_SPL_FEL +#define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */ +#endif +#endif

#include <asm/arch/cpu.h> /* get chip and board defs */

@@ -139,11 +144,32 @@ #define CONFIG_SPL_SERIAL_SUPPORT #define CONFIG_SPL_LIBGENERIC_SUPPORT

+#ifdef CONFIG_SPL_FEL + #define CONFIG_SPL #define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds" #define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7/sunxi" #define CONFIG_SPL_TEXT_BASE 0x2000 #define CONFIG_SPL_MAX_SIZE 0x4000 /* 16 KiB */ + +#else /* CONFIG_SPL */ + +#define CONFIG_SPL_BSS_START_ADDR 0x50000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KiB */ + +#define CONFIG_SPL_TEXT_BASE 0x20 /* sram start+header */ +#define CONFIG_SPL_MAX_SIZE 0x5fe0 /* 24KB on sun4i/sun7i */ + +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT + +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds" + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 80 /* 40KiB */ +#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ + +#endif /* CONFIG_SPL */ + /* end of 32 KiB in sram */ #define LOW_LEVEL_SRAM_STACK 0x00008000 #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK diff --git a/spl/Makefile b/spl/Makefile index bb3d349..9a6b265 100644 --- a/spl/Makefile +++ b/spl/Makefile @@ -188,6 +188,12 @@ ifdef CONFIG_SAMSUNG ALL-y += $(obj)/$(BOARD)-spl.bin endif

+ifdef CONFIG_SUNXI +ifndef CONFIG_SPL_FEL +ALL-y += $(obj)/sunxi-spl.bin +endif +endif + all: $(ALL-y)

ifdef CONFIG_SAMSUNG @@ -215,6 +221,13 @@ ifneq ($(CONFIG_SPL_TEXT_BASE),) LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE) endif

+ifdef CONFIG_SUNXI +quiet_cmd_mksunxiboot = MKSUNXI $@ +cmd_mksunxiboot = $(OBJTREE)/tools/mksunxiboot $< $@ +$(obj)/sunxi-spl.bin: $(obj)/$(SPL_BIN).bin + $(call if_changed,mksunxiboot) +endif + quiet_cmd_u-boot-spl = LD $@ cmd_u-boot-spl = cd $(obj) && $(LD) $(LDFLAGS) $(LDFLAGS_$(@F)) \ $(patsubst $(obj)/%,%,$(u-boot-spl-init)) --start-group \ diff --git a/tools/.gitignore b/tools/.gitignore index 2a90dfe..3ad5db3 100644 --- a/tools/.gitignore +++ b/tools/.gitignore @@ -9,6 +9,7 @@ /mkexynosspl /mpc86x_clk /mxsboot +/mksunxiboot /ncb /proftool /relocate-rela diff --git a/tools/Makefile b/tools/Makefile index bac6aaf..63e00a8 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -120,6 +120,8 @@ hostprogs-$(CONFIG_MX23) += mxsboot$(SFX) hostprogs-$(CONFIG_MX28) += mxsboot$(SFX) HOSTCFLAGS_mxsboot$(SFX).o := -pedantic

+hostprogs-$(CONFIG_SUNXI) += mksunxiboot$(SFX) + hostprogs-$(CONFIG_NETCONSOLE) += ncb$(SFX) hostprogs-$(CONFIG_SHA1_CHECK_UB_IMG) += ubsha1$(SFX)

diff --git a/tools/mksunxiboot.README b/tools/mksunxiboot.README new file mode 100644 index 0000000..5838778 --- /dev/null +++ b/tools/mksunxiboot.README @@ -0,0 +1,13 @@ +This program make a arm binary file can be loaded by Allwinner A10 and related +chips from storage media such as nand and mmc. + +More information about A10 boot, please refer to +http://rhombus-tech.net/allwinner_a10/a10_boot_process/ + +To compile this program, just type make, you will get 'mksunxiboot'. + +To use it, +$./mksunxiboot u-boot.bin u-boot-mmc.bin +then you can write it to a mmc card with dd. +$sudo dd if=u-boot-mmc.bin of=/dev/sdb bs=1024 seek=8 +then insert your mmc card to your A10 tablet, you can boot from mmc card. diff --git a/tools/mksunxiboot.c b/tools/mksunxiboot.c new file mode 100644 index 0000000..864841e --- /dev/null +++ b/tools/mksunxiboot.c @@ -0,0 +1,153 @@ +/* + * (C) Copyright 2007-2011 + * Allwinner Technology Co., Ltd. <www.allwinnertech.com> + * Tom Cubie tangliang@allwinnertech.com + * + * a simple tool to generate bootable image for sunxi platform. + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <fcntl.h> +#include <stdio.h> +#include <unistd.h> +#include <stdlib.h> +#include <string.h> +#include <errno.h> +#include <sys/types.h> +#include <sys/stat.h> + +typedef unsigned char u8; +typedef unsigned int u32; + +/* boot head definition from sun4i boot code */ +struct boot_file_head { + u32 jump_instruction; /* one intruction jumping to real code */ + u8 magic[8]; /* ="eGON.BT0" or "eGON.BT1", not C-style str */ + u32 check_sum; /* generated by PC */ + u32 length; /* generated by PC */ +#if 1 + /* We use a simplified header, only filling in what is needed by the + * boot ROM. To be compatible with Allwinner tools the larger header + * below should be used, followed by a custom header if desired. */ + u8 pad[12]; /* align to 32 bytes */ +#else + u32 pub_head_size; /* the size of boot_file_head */ + u8 pub_head_vsn[4]; /* the version of boot_file_head */ + u8 file_head_vsn[4]; /* the version of boot0_file_head or + boot1_file_head */ + u8 Boot_vsn[4]; /* Boot version */ + u8 eGON_vsn[4]; /* eGON version */ + u8 platform[8]; /* platform information */ +#endif +}; + +#define BOOT0_MAGIC "eGON.BT0" +#define STAMP_VALUE 0x5F0A6C39 + +/* check sum functon from sun4i boot code */ +int gen_check_sum(void *boot_buf) +{ + struct boot_file_head *head_p; + u32 length; + u32 *buf; + u32 loop; + u32 i; + u32 sum; + + head_p = (struct boot_file_head *)boot_buf; + length = head_p->length; + if ((length & 0x3) != 0) /* must 4-byte-aligned */ + return -1; + buf = (u32 *)boot_buf; + head_p->check_sum = STAMP_VALUE; /* fill stamp */ + loop = length >> 2; + + /* calculate the sum */ + for (i = 0, sum = 0; i < loop; i++) + sum += buf[i]; + + /* write back check sum */ + head_p->check_sum = sum; + + return 0; +} + +#define ALIGN(x, a) __ALIGN_MASK((x), (typeof(x))(a)-1) +#define __ALIGN_MASK(x, mask) (((x)+(mask))&~(mask)) + +#define SUN4I_SRAM_SIZE 0x7600 /* 0x7748+ is used by BROM */ +#define SRAM_LOAD_MAX_SIZE (SUN4I_SRAM_SIZE - sizeof(struct boot_file_head)) +#define BLOCK_SIZE 512 + +struct boot_img { + struct boot_file_head header; + char code[SRAM_LOAD_MAX_SIZE]; + char pad[BLOCK_SIZE]; +}; + +int main(int argc, char *argv[]) +{ + int fd_in, fd_out; + struct boot_img img; + unsigned file_size, load_size; + int count; + + if (argc < 2) { + printf("\tThis program makes an input bin file to sun4i " \ + "bootable image.\n" \ + "\tUsage: %s input_file out_putfile\n", argv[0]); + return EXIT_FAILURE; + } + + fd_in = open(argv[1], O_RDONLY); + if (fd_in < 0) { + perror("Open input file"); + return EXIT_FAILURE; + } + + memset((void *)img.pad, 0, BLOCK_SIZE); + + /* get input file size */ + file_size = lseek(fd_in, 0, SEEK_END); + + if (file_size > SRAM_LOAD_MAX_SIZE) { + fprintf(stderr, "ERROR: File too large!\n"); + return EXIT_FAILURE; + } else + load_size = ALIGN(file_size, sizeof(int)); + + fd_out = open(argv[2], O_WRONLY | O_CREAT, 0666); + if (fd_out < 0) { + perror("Open output file"); + return EXIT_FAILURE; + } + + /* read file to buffer to calculate checksum */ + lseek(fd_in, 0, SEEK_SET); + count = read(fd_in, img.code, load_size); + if (count != load_size) { + perror("Reading input image"); + return EXIT_FAILURE; + } + + /* fill the header */ + img.header.jump_instruction = /* b instruction */ + 0xEA000000 | /* jump to the first instr after the header */ + ((sizeof(struct boot_file_head) / sizeof(int) - 2) + & 0x00FFFFFF); + memcpy(img.header.magic, BOOT0_MAGIC, 8); /* no '0' termination */ + img.header.length = + ALIGN(load_size + sizeof(struct boot_file_head), BLOCK_SIZE); + gen_check_sum((void *)&img); + + count = write(fd_out, (void *)&img, img.header.length); + if (count != img.header.length) { + perror("Writing output"); + return EXIT_FAILURE; + } + + close(fd_in); + close(fd_out); + + return EXIT_SUCCESS; +}