pá 25. 3. 2022 v 13:11 odesílatel Michal Simek michal.simek@xilinx.com napsal:

From: Ashok Reddy Soma ashok.reddy.soma@xilinx.com

The DLL mode supported SD reference clocks are 50 MHz, 100 MHz and 200 MHz. When user select SD frequency as 200MHz in the design, the actual frequency is going to come around ~187MHz (<= 200MHz considering the parent clock and divisor selection). We need to set SDx_BASECLK as 200 in this case, setting 187 will result in tuning failures in mmc.

Set SDx_BASECLK to exact value of 200, 100 or 50 based on the frequency range.

Signed-off-by: Ashok Reddy Soma ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek michal.simek@xilinx.com

---

drivers/mmc/zynq_sdhci.c | 9 +++++++++ 1 file changed, 9 insertions(+)

diff --git a/drivers/mmc/zynq_sdhci.c b/drivers/mmc/zynq_sdhci.c index d96f5d543f54..a59d96c6bdad 100644 --- a/drivers/mmc/zynq_sdhci.c +++ b/drivers/mmc/zynq_sdhci.c @@ -765,6 +765,15 @@ static int sdhci_zynqmp_set_dynamic_config(struct arasan_sdhci_priv *priv,

    mhz = DIV64_U64_ROUND_UP(clock, 1000000);

•   if (mhz > 100 && mhz <= 200)
  

•           mhz = 200;
  

•   else if (mhz > 50 && mhz <= 100)
  

•           mhz = 100;
  

•   else if (mhz > 25 && mhz <= 50)
  

•           mhz = 50;
  

•   else
  

•           mhz = 25;
  

•   ret = zynqmp_pm_set_sd_config(node_id, SD_CONFIG_BASECLK, mhz);
    if (ret) {
            dev_err(dev, "SD_CONFIG_BASECLK failed\n");
  

-- 2.35.1

Applied. M