[PATCH 1/8] configs: HSD #1508104447-2: configs: socfpga: stratix10: Enable CONFIG_CMD_MTD
From: Ley Foon Tan ley.foon.tan@intel.com
Enable CONFIG_CMD_MTD. CONFIG_MTD_PARTITIONS is enabled by CONFIG_CMD_MTD. So, remove CONFIG_MTD_PARTITIONS from socfpga_stratix10_socdk.h.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- configs/socfpga_stratix10_defconfig | 1 + configs/socfpga_stratix10_qspi_defconfig | 1 + 2 files changed, 2 insertions(+)
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 07e9f20a41..39226a8b95 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -49,6 +49,7 @@ CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_WDT=y diff --git a/configs/socfpga_stratix10_qspi_defconfig b/configs/socfpga_stratix10_qspi_defconfig index 6d41356fe0..27730db8c8 100644 --- a/configs/socfpga_stratix10_qspi_defconfig +++ b/configs/socfpga_stratix10_qspi_defconfig @@ -31,6 +31,7 @@ CONFIG_CMD_MEMTEST=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y +CONFIG_CMD_MTD=y CONFIG_CMD_SPI=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y
From: Ley Foon Tan ley.foon.tan@intel.com
Move CONFIG_MTDIDS_DEFAULT to defconfig and add mtdids to ENV settings.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- configs/socfpga_stratix10_defconfig | 1 + configs/socfpga_stratix10_qspi_defconfig | 1 + 2 files changed, 2 insertions(+)
diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 39226a8b95..519a98e844 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -60,6 +60,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" CONFIG_ENV_IS_IN_MMC=y CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_USE_BOOTFILE=y diff --git a/configs/socfpga_stratix10_qspi_defconfig b/configs/socfpga_stratix10_qspi_defconfig index 27730db8c8..0c6c551822 100644 --- a/configs/socfpga_stratix10_qspi_defconfig +++ b/configs/socfpga_stratix10_qspi_defconfig @@ -41,6 +41,7 @@ CONFIG_CMD_CACHE=y CONFIG_CMD_EXT4=y CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y +CONFIG_MTDIDS_DEFAULT="nor0=ff705000.spi.0" CONFIG_ENV_IS_IN_SPI_FLASH=y CONFIG_NET_RANDOM_ETHADDR=y CONFIG_SPL_DM_SEQ_ALIAS=y
From: Ley Foon Tan ley.foon.tan@intel.com
Add NAND node to stratix10 base dtsi file.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- arch/arm/dts/socfpga_stratix10.dtsi | 12 ++++++++++++ 1 file changed, 12 insertions(+)
diff --git a/arch/arm/dts/socfpga_stratix10.dtsi b/arch/arm/dts/socfpga_stratix10.dtsi index 7a7777202c..9f3dbf615e 100755 --- a/arch/arm/dts/socfpga_stratix10.dtsi +++ b/arch/arm/dts/socfpga_stratix10.dtsi @@ -232,6 +232,18 @@ status = "disabled"; };
+ nand: nand@ffb90000 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "altr,socfpga-denali-nand"; + reg = <0xffb90000 0x10000>, + <0xffb80000 0x1000>; + reg-names = "nand_data", "denali_reg"; + interrupts = <0 97 4>; + resets = <&rst NAND_RESET>, <&rst NAND_OCP_RESET>; + status = "disabled"; + }; + ocram: sram@ffe00000 { compatible = "mmio-sram"; reg = <0xffe00000 0x100000>;
From: Ley Foon Tan ley.foon.tan@intel.com
Copied from Linux commit ID 3c0f3b8545e7 ("arm64: dts: add NAND board files for Stratix10 and Agilex")
The Stratix10 devkit supports a separate NAND daughter card. The NAND daughter card replaces the SDMMC slot that is on the default daughter card thus requires a separate board dts file.
Add flash0 label to QSPI node to reference it in other dts file later.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- arch/arm/dts/socfpga_stratix10_socdk_nand.dts | 223 ++++++++++++++++++ 1 file changed, 223 insertions(+) create mode 100644 arch/arm/dts/socfpga_stratix10_socdk_nand.dts
diff --git a/arch/arm/dts/socfpga_stratix10_socdk_nand.dts b/arch/arm/dts/socfpga_stratix10_socdk_nand.dts new file mode 100644 index 0000000000..ef3044b3ae --- /dev/null +++ b/arch/arm/dts/socfpga_stratix10_socdk_nand.dts @@ -0,0 +1,223 @@ +// SPDX-License-Identifier: GPL-2.0-only +/* + * Copyright Altera Corporation (C) 2015. All rights reserved. + */ + +#include "socfpga_stratix10.dtsi" + +/ { + model = "SoCFPGA Stratix 10 SoCDK"; + + aliases { + serial0 = &uart0; + ethernet0 = &gmac0; + ethernet1 = &gmac1; + ethernet2 = &gmac2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + leds { + compatible = "gpio-leds"; + hps0 { + label = "hps_led0"; + gpios = <&portb 20 GPIO_ACTIVE_HIGH>; + }; + + hps1 { + label = "hps_led1"; + gpios = <&portb 19 GPIO_ACTIVE_HIGH>; + }; + + hps2 { + label = "hps_led2"; + gpios = <&portb 21 GPIO_ACTIVE_HIGH>; + }; + }; + + memory { + device_type = "memory"; + /* We expect the bootloader to fill in the reg */ + reg = <0 0 0 0>; + }; + + ref_033v: 033-v-ref { + compatible = "regulator-fixed"; + regulator-name = "0.33V"; + regulator-min-microvolt = <330000>; + regulator-max-microvolt = <330000>; + }; + + soc { + clocks { + osc1 { + clock-frequency = <25000000>; + }; + }; + + eccmgr { + sdmmca-ecc@ff8c8c00 { + compatible = "altr,socfpga-s10-sdmmc-ecc", + "altr,socfpga-sdmmc-ecc"; + reg = <0xff8c8c00 0x100>; + altr,ecc-parent = <&mmc>; + interrupts = <14 4>, + <15 4>; + }; + }; + }; +}; + +&gpio1 { + status = "okay"; +}; + +&gmac2 { + status = "okay"; + phy-mode = "rgmii"; + phy-handle = <&phy0>; + + max-frame-size = <9000>; + + mdio0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy0: ethernet-phy@0 { + reg = <4>; + + txd0-skew-ps = <0>; /* -420ps */ + txd1-skew-ps = <0>; /* -420ps */ + txd2-skew-ps = <0>; /* -420ps */ + txd3-skew-ps = <0>; /* -420ps */ + rxd0-skew-ps = <420>; /* 0ps */ + rxd1-skew-ps = <420>; /* 0ps */ + rxd2-skew-ps = <420>; /* 0ps */ + rxd3-skew-ps = <420>; /* 0ps */ + txen-skew-ps = <0>; /* -420ps */ + txc-skew-ps = <900>; /* 0ps */ + rxdv-skew-ps = <420>; /* 0ps */ + rxc-skew-ps = <1680>; /* 780ps */ + }; + }; +}; + +&nand { + status = "okay"; + + flash@0 { + #address-cells = <1>; + #size-cells = <1>; + reg = <0>; + nand-bus-width = <16>; + + partition@0 { + label = "u-boot"; + reg = <0 0x200000>; + }; + + partition@200000 { + label = "env"; + reg = <0x200000 0x40000>; + }; + + partition@240000 { + label = "dtb"; + reg = <0x240000 0x40000>; + }; + + partition@280000 { + label = "kernel"; + reg = <0x280000 0x2000000>; + }; + + partition@2280000 { + label = "misc"; + reg = <0x2280000 0x2000000>; + }; + + partition@4280000 { + label = "rootfs"; + reg = <0x4280000 0x3bd80000>; + }; + }; +}; + +&uart0 { + status = "okay"; +}; + +&usb0 { + status = "okay"; + disable-over-current; +}; + +&watchdog0 { + status = "okay"; +}; + +&i2c2 { + status = "okay"; + clock-frequency = <100000>; + i2c-sda-falling-time-ns = <890>; /* hcnt */ + i2c-sdl-falling-time-ns = <890>; /* lcnt */ + + adc@14 { + compatible = "lltc,ltc2497"; + reg = <0x14>; + vref-supply = <&ref_033v>; + }; + + temp@4c { + compatible = "maxim,max1619"; + reg = <0x4c>; + }; + + eeprom@51 { + compatible = "atmel,24c32"; + reg = <0x51>; + pagesize = <32>; + }; + + rtc@68 { + compatible = "dallas,ds1339"; + reg = <0x68>; + }; +}; + +&qspi { + flash0: flash@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "n25q00a"; + reg = <0>; + spi-max-frequency = <100000000>; + + m25p,fast-read; + cdns,page-size = <256>; + cdns,block-size = <16>; + cdns,read-delay = <1>; + cdns,tshsl-ns = <50>; + cdns,tsd2d-ns = <50>; + cdns,tchsh-ns = <4>; + cdns,tslch-ns = <4>; + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + qspi_boot: partition@0 { + label = "Boot and fpga data"; + reg = <0x0 0x034B0000>; + }; + + qspi_rootfs: partition@4000000 { + label = "Root Filesystem - JFFS2"; + reg = <0x034B0000 0x0EB50000>; + }; + }; + }; +};
From: Ley Foon Tan ley.foon.tan@intel.com
Add new file socfpga_stratix10_socdk_nand-u-boot.dtsi for Uboot specific properties.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- .../socfpga_stratix10_socdk_nand-u-boot.dtsi | 36 +++++++++++++++++++ 1 file changed, 36 insertions(+) create mode 100644 arch/arm/dts/socfpga_stratix10_socdk_nand-u-boot.dtsi
diff --git a/arch/arm/dts/socfpga_stratix10_socdk_nand-u-boot.dtsi b/arch/arm/dts/socfpga_stratix10_socdk_nand-u-boot.dtsi new file mode 100644 index 0000000000..5d8c3e2f91 --- /dev/null +++ b/arch/arm/dts/socfpga_stratix10_socdk_nand-u-boot.dtsi @@ -0,0 +1,36 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright Altera Corporation (C) 2020. All rights reserved. + */ + +#include "socfpga_stratix10_socdk-u-boot.dtsi" + +/ { + chosen { + u-boot,boot0 = <&nand>; + }; + + memory { + #address-cells = <2>; + #size-cells = <2>; + device_type = "memory"; + /* 4GB */ + reg = <0 0x00000000 0 0x80000000>, + <1 0x80000000 0 0x80000000>; + u-boot,dm-pre-reloc; + }; + + soc { + eccmgr { + #address-cells = <1>; + #size-cells = <1>; + interrupt-controller; + #interrupt-cells = <2>; + }; + }; +}; + +&nand { + u-boot,dm-pre-reloc; + nand-bus-width = <16>; +};
From: Ley Foon Tan ley.foon.tan@intel.com
Enable build for socfpga_stratix10_socdk_nand.dtb.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- arch/arm/dts/Makefile | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 86e9407456..9a9d7163d9 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -438,6 +438,7 @@ dtb-$(CONFIG_ARCH_SOCFPGA) += \ socfpga_cyclone5_vining_fpga.dtb \ socfpga_n5x_socdk.dtb \ socfpga_stratix10_socdk.dtb \ + socfpga_stratix10_socdk_nand.dtb \ socfpga_stratix10_socdk_qspi.dtb
dtb-$(CONFIG_TARGET_DRA7XX_EVM) += dra72-evm.dtb dra7-evm.dtb \
From: Ley Foon Tan ley.foon.tan@intel.com
Add NAND defconfig for Stratix10.
Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- configs/socfpga_stratix10_nand_defconfig | 86 ++++++++++++++++++++++++ 1 file changed, 86 insertions(+) create mode 100644 configs/socfpga_stratix10_nand_defconfig
diff --git a/configs/socfpga_stratix10_nand_defconfig b/configs/socfpga_stratix10_nand_defconfig new file mode 100644 index 0000000000..ca141a17c5 --- /dev/null +++ b/configs/socfpga_stratix10_nand_defconfig @@ -0,0 +1,86 @@ +CONFIG_ARM=y +CONFIG_SPL_LDSCRIPT="arch/arm/mach-socfpga/u-boot-spl-soc64.lds" +CONFIG_ARCH_SOCFPGA=y +CONFIG_SYS_TEXT_BASE=0x1000 +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_NR_DRAM_BANKS=2 +CONFIG_ENV_SIZE=0x20000 +CONFIG_ENV_OFFSET=0x00200000 +CONFIG_SYS_SPI_U_BOOT_OFFS=0x02000000 +CONFIG_DM_GPIO=y +CONFIG_SPL_TEXT_BASE=0xFFE00000 +CONFIG_SPL_DRIVERS_MISC_SUPPORT=y +CONFIG_TARGET_SOCFPGA_STRATIX10_SOCDK=y +CONFIG_IDENT_STRING="socfpga_stratix10" +CONFIG_SPL_FS_FAT=y +CONFIG_ARMV8_SEC_FIRMWARE_SUPPORT=y +CONFIG_ARMV8_PSCI=y +CONFIG_DEFAULT_DEVICE_TREE="socfpga_stratix10_socdk_nand" +CONFIG_NAND_BOOT=y +CONFIG_BOOTDELAY=5 +CONFIG_USE_BOOTARGS=y +CONFIG_BOOTARGS="earlycon panic=-1" +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run nandload; run linux_qspi_enable; rsu dtb; run nandboot" +CONFIG_SPL_MTD_SUPPORT=y +CONFIG_SPL_NAND_SUPPORT=y +CONFIG_SPL_SPI_LOAD=y +CONFIG_HUSH_PARSER=y +CONFIG_SYS_PROMPT="SOCFPGA_STRATIX10 # " +CONFIG_CMD_MEMTEST=y +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_MTD=y +CONFIG_CMD_NAND_TRIMFFS=y +CONFIG_CMD_NAND_LOCK_UNLOCK=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_CACHE=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_MTDIDS_DEFAULT="nand0=ffb90000.nand.0" +CONFIG_MTDPARTS_DEFAULT="mtdparts=ffb90000.nand.0:2m(u-boot),256k(env),256k(dtb),32m(kernel),32m(misc),-(rootfs)" +CONFIG_ENV_IS_IN_NAND=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_SPL_DM_SEQ_ALIAS=y +CONFIG_SPL_ALTERA_SDRAM=y +CONFIG_FPGA_INTEL_PR=y +CONFIG_DWAPB_GPIO=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_DW=y +CONFIG_MISC=y +CONFIG_DM_MMC=y +CONFIG_MMC_DW=y +CONFIG_MTD=y +CONFIG_DM_MTD=y +CONFIG_NAND_DENALI_DT=y +CONFIG_SYS_NAND_U_BOOT_LOCATIONS=y +CONFIG_SYS_NAND_U_BOOT_OFFS=0x0 +CONFIG_SYS_NAND_U_BOOT_OFFS_REDUND=0x100000 +CONFIG_SPL_NAND_FRAMEWORK=y +CONFIG_SF_DEFAULT_MODE=0x2003 +CONFIG_SPI_FLASH_SPANSION=y +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_ETH_DESIGNWARE=y +CONFIG_MII=y +CONFIG_DM_RESET=y +CONFIG_SPI=y +CONFIG_CADENCE_QSPI=y +CONFIG_DESIGNWARE_SPI=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_DWC2=y +CONFIG_USB_STORAGE=y +CONFIG_DESIGNWARE_WATCHDOG=y +CONFIG_WDT=y +# CONFIG_SPL_USE_TINY_PRINTF is not set +CONFIG_PANIC_HANG=y
From: Ley Foon Tan ley.foon.tan@intel.com
Fixed delay 200us is not working in certain platform. Change to poll for reset completion status to have more reliable reset process.
Controller will set the rst_comp bit in intr_status register after controller has completed its reset and initialization process.
Signed-off-by: Radu Bacrau radu.bacrau@intel.com Signed-off-by: Ley Foon Tan ley.foon.tan@intel.com Signed-off-by: Jit Loon Lim jit.loon.lim@intel.com --- drivers/mtd/nand/raw/denali_dt.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/mtd/nand/raw/denali_dt.c b/drivers/mtd/nand/raw/denali_dt.c index cf4df0168a..5a4c11e159 100644 --- a/drivers/mtd/nand/raw/denali_dt.c +++ b/drivers/mtd/nand/raw/denali_dt.c @@ -154,8 +154,8 @@ static int denali_dt_probe(struct udevice *dev)
/* * When the reset is deasserted, the initialization sequence is - * kicked (bootstrap process). The driver must wait until it is - * finished. Otherwise, it will result in unpredictable behavior. + * kicked. The driver must wait until it is finished. Otherwise, + * it will result in unpredictable behavior. */ ret = denali_wait_reset_complete(denali); if (ret) {
participants (1)
-
Jit Loon Lim