[U-Boot] [PATCH 0/4] efikamx: update Efika MX support
This patchset relies on the previously submitted patch "mx5: add iomux-mx51.h include"
It may not boot reliably, completely at random, on Efika MX boards, without the previously submitted (series) "spi: fix mxc_spi_slave structure allocation to clear memory"
Matt Sealey (4): efikamx: move efikamx into a new directory in preparation for new boards efikamx: remove drive strength hack from early_init_f and move it to the DCD efikamx: update to Efika MX Smarttop and Smartbook boards efikamx: port USB setup to new iomux model
arch/arm/include/asm/arch-mx5/iomux-mx51.h | 28 ++ board/efikamx/Makefile | 49 -- board/efikamx/efikamx-usb.c | 216 -------- board/efikamx/efikamx.c | 735 ---------------------------- board/efikamx/imximage_mx.cfg | 122 ----- board/efikamx/imximage_sb.cfg | 122 ----- board/genesi/mx51_efikamx/Makefile | 49 ++ board/genesi/mx51_efikamx/efikamx-usb.c | 203 ++++++++ board/genesi/mx51_efikamx/efikamx.c | 507 +++++++++++++++++++ board/genesi/mx51_efikamx/imximage_mx.cfg | 113 +++++ board/genesi/mx51_efikamx/imximage_sb.cfg | 122 +++++ boards.cfg | 4 +- include/configs/efikamx.h | 274 ----------- include/configs/mx51_efikamx.h | 274 +++++++++++ 14 files changed, 1298 insertions(+), 1520 deletions(-) delete mode 100644 board/efikamx/Makefile delete mode 100644 board/efikamx/efikamx-usb.c delete mode 100644 board/efikamx/efikamx.c delete mode 100644 board/efikamx/imximage_mx.cfg delete mode 100644 board/efikamx/imximage_sb.cfg create mode 100644 board/genesi/mx51_efikamx/Makefile create mode 100644 board/genesi/mx51_efikamx/efikamx-usb.c create mode 100644 board/genesi/mx51_efikamx/efikamx.c create mode 100644 board/genesi/mx51_efikamx/imximage_mx.cfg create mode 100644 board/genesi/mx51_efikamx/imximage_sb.cfg delete mode 100644 include/configs/efikamx.h create mode 100644 include/configs/mx51_efikamx.h
* Move Efika MX boards into "genesi" directory. * Rename it to "mx51_efikamx" since there's an mx53 version out there.
Signed-off-by: Matt Sealey matt@genesi-usa.com --- board/efikamx/Makefile | 49 -- board/efikamx/efikamx-usb.c | 216 --------- board/efikamx/efikamx.c | 735 ----------------------------- board/efikamx/imximage_mx.cfg | 122 ----- board/efikamx/imximage_sb.cfg | 122 ----- board/genesi/mx51_efikamx/Makefile | 49 ++ board/genesi/mx51_efikamx/efikamx-usb.c | 216 +++++++++ board/genesi/mx51_efikamx/efikamx.c | 735 +++++++++++++++++++++++++++++ board/genesi/mx51_efikamx/imximage_mx.cfg | 122 +++++ board/genesi/mx51_efikamx/imximage_sb.cfg | 122 +++++ boards.cfg | 4 +- include/configs/efikamx.h | 274 ----------- include/configs/mx51_efikamx.h | 274 +++++++++++ 13 files changed, 1520 insertions(+), 1520 deletions(-) delete mode 100644 board/efikamx/Makefile delete mode 100644 board/efikamx/efikamx-usb.c delete mode 100644 board/efikamx/efikamx.c delete mode 100644 board/efikamx/imximage_mx.cfg delete mode 100644 board/efikamx/imximage_sb.cfg create mode 100644 board/genesi/mx51_efikamx/Makefile create mode 100644 board/genesi/mx51_efikamx/efikamx-usb.c create mode 100644 board/genesi/mx51_efikamx/efikamx.c create mode 100644 board/genesi/mx51_efikamx/imximage_mx.cfg create mode 100644 board/genesi/mx51_efikamx/imximage_sb.cfg delete mode 100644 include/configs/efikamx.h create mode 100644 include/configs/mx51_efikamx.h
diff --git a/board/efikamx/Makefile b/board/efikamx/Makefile deleted file mode 100644 index bd2174f..0000000 --- a/board/efikamx/Makefile +++ /dev/null @@ -1,49 +0,0 @@ -# -# Copyright (C) 2010, Marek Vasut marek.vasut@gmail.com -# -# BASED ON: imx51evk -# -# Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de -# -# (C) Copyright 2009 Freescale Semiconductor, Inc. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# - -include $(TOPDIR)/config.mk - -LIB = $(obj)lib$(BOARD).o - -COBJS := efikamx.o - -ifdef CONFIG_CMD_USB -COBJS += efikamx-usb.o -endif - -SRCS := $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(COBJS)) - -$(LIB): $(obj).depend $(OBJS) - $(call cmd_link_o_target, $(OBJS)) - -######################################################################### - -# defines $(obj).depend target -include $(SRCTREE)/rules.mk - -sinclude $(obj).depend - -######################################################################### diff --git a/board/efikamx/efikamx-usb.c b/board/efikamx/efikamx-usb.c deleted file mode 100644 index 618b39d..0000000 --- a/board/efikamx/efikamx-usb.c +++ /dev/null @@ -1,216 +0,0 @@ -/* - * Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <usb.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/mx5x_pins.h> -#include <asm/arch/iomux.h> -#include <asm/gpio.h> -#include <usb/ehci-fsl.h> -#include <usb/ulpi.h> -#include <errno.h> - -#include "../../drivers/usb/host/ehci.h" - -/* USB pin configuration */ -#define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \ - PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \ - PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL) - -/* - * Configure the USB H1 and USB H2 IOMUX - */ -void setup_iomux_usb(void) -{ - setup_iomux_usb_h1(); - - if (machine_is_efikasb()) - setup_iomux_usb_h2(); - - /* USB PHY reset */ - mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_PKE_ENABLE | - PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); - - /* USB HUB reset */ - mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_PKE_ENABLE | - PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); - - /* WIFI EN (act low) */ - mxc_request_iomux(MX51_PIN_EIM_A22, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_EIM_A22, 0); - /* WIFI RESET */ - mxc_request_iomux(MX51_PIN_EIM_A16, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_EIM_A16, 0); - /* BT EN (act low) */ - mxc_request_iomux(MX51_PIN_EIM_A17, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_EIM_A17, 0); -} - -/* - * Enable devices connected to USB BUSes - */ -static void efika_usb_enable_devices(void) -{ - /* Enable Bluetooth */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 0); - udelay(10000); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 1); - - /* Enable WiFi */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), 1); - udelay(10000); - - /* Reset the WiFi chip */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 0); - udelay(10000); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 1); -} - -/* - * Reset USB HUB (or HUBs on EfikaSB) - */ -static void efika_usb_hub_reset(void) -{ - /* HUB reset */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1); - udelay(1000); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 0); - udelay(1000); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1); -} - -/* - * Reset USB PHY (or PHYs on EfikaSB) - */ -static void efika_usb_phy_reset(void) -{ - /* SMSC 3317 PHY reset */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 0); - udelay(1000); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1); -} - -static void efika_ehci_init(struct usb_ehci *ehci, uint32_t stp_gpio, - uint32_t alt0, uint32_t alt1) -{ - int ret; - struct ulpi_regs *ulpi = (struct ulpi_regs *)0; - struct ulpi_viewport ulpi_vp; - - mxc_request_iomux(stp_gpio, alt0); - mxc_iomux_set_pad(stp_gpio, PAD_CTL_DRV_HIGH | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - gpio_direction_output(IOMUX_TO_GPIO(stp_gpio), 0); - udelay(1000); - gpio_set_value(IOMUX_TO_GPIO(stp_gpio), 1); - udelay(1000); - - mxc_request_iomux(stp_gpio, alt1); - mxc_iomux_set_pad(stp_gpio, USB_PAD_CONFIG); - udelay(10000); - - ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint; - ulpi_vp.port_num = 0; - - ret = ulpi_init(&ulpi_vp); - if (ret) { - printf("Efika USB ULPI initialization failed\n"); - return; - } - - /* ULPI set flags */ - ulpi_write(&ulpi_vp, &ulpi->otg_ctrl, - ULPI_OTG_DP_PULLDOWN | ULPI_OTG_DM_PULLDOWN | - ULPI_OTG_EXTVBUSIND); - ulpi_write(&ulpi_vp, &ulpi->function_ctrl, - ULPI_FC_FULL_SPEED | ULPI_FC_OPMODE_NORMAL | - ULPI_FC_SUSPENDM); - ulpi_write(&ulpi_vp, &ulpi->iface_ctrl, 0); - - /* Set VBus */ - ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, - ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); - - /* - * Set VBusChrg - * - * NOTE: This violates USB specification, but otherwise, USB on Efika - * doesn't work. - */ - ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, ULPI_OTG_CHRGVBUS); -} - -int board_ehci_hcd_init(int port) -{ - /* Init iMX51 EHCI */ - efika_usb_phy_reset(); - efika_usb_hub_reset(); - efika_usb_enable_devices(); - - return 0; -} - -void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) -{ - uint32_t port = OTG_BASE_ADDR + (0x200 * CONFIG_MXC_USB_PORT); - struct usb_ehci *ehci = (struct usb_ehci *)port; - struct ulpi_regs *ulpi = (struct ulpi_regs *)0; - struct ulpi_viewport ulpi_vp; - - ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint; - ulpi_vp.port_num = 0; - - ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, ULPI_OTG_CHRGVBUS); - - mdelay(50); - - /* terminate the reset */ - *reg = ehci_readl(status_reg); - *reg |= EHCI_PS_PE; -} - -void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) -{ - uint32_t tmp; - - if (port == 0) { - /* Adjust UTMI PHY frequency to 24MHz */ - tmp = readl(OTG_BASE_ADDR + 0x80c); - tmp = (tmp & ~0x3) | 0x01; - writel(tmp, OTG_BASE_ADDR + 0x80c); - } else if (port == 1) { - efika_ehci_init(ehci, MX51_PIN_USBH1_STP, - IOMUX_CONFIG_ALT2, IOMUX_CONFIG_ALT0); - } else if ((port == 2) && machine_is_efikasb()) { - efika_ehci_init(ehci, MX51_PIN_EIM_A26, - IOMUX_CONFIG_ALT1, IOMUX_CONFIG_ALT2); - } - - if (port) - mdelay(10); -} diff --git a/board/efikamx/efikamx.c b/board/efikamx/efikamx.c deleted file mode 100644 index e88b2ed..0000000 --- a/board/efikamx/efikamx.c +++ /dev/null @@ -1,735 +0,0 @@ -/* - * Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/mx5x_pins.h> -#include <asm/arch/iomux.h> -#include <asm/gpio.h> -#include <asm/errno.h> -#include <asm/arch/sys_proto.h> -#include <asm/arch/crm_regs.h> -#include <i2c.h> -#include <mmc.h> -#include <fsl_esdhc.h> -#include <pmic.h> -#include <fsl_pmic.h> -#include <mc13892.h> - -DECLARE_GLOBAL_DATA_PTR; - -/* - * Compile-time error checking - */ -#ifndef CONFIG_MXC_SPI -#error "CONFIG_MXC_SPI not set, this is essential for board's operation!" -#endif - -/* - * Shared variables / local defines - */ -/* LED */ -#define EFIKAMX_LED_BLUE 0x1 -#define EFIKAMX_LED_GREEN 0x2 -#define EFIKAMX_LED_RED 0x4 - -void efikamx_toggle_led(uint32_t mask); - -/* Board revisions */ -#define EFIKAMX_BOARD_REV_11 0x1 -#define EFIKAMX_BOARD_REV_12 0x2 -#define EFIKAMX_BOARD_REV_13 0x3 -#define EFIKAMX_BOARD_REV_14 0x4 - -#define EFIKASB_BOARD_REV_13 0x1 -#define EFIKASB_BOARD_REV_20 0x2 - -/* - * Board identification - */ -u32 get_efikamx_rev(void) -{ - u32 rev = 0; - /* - * Retrieve board ID: - * rev1.1: 1,1,1 - * rev1.2: 1,1,0 - * rev1.3: 1,0,1 - * rev1.4: 1,0,0 - */ - mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO); - /* set to 1 in order to get correct value on board rev1.1 */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1); - - mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0; - - mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1; - - mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2; - - return (~rev & 0x7) + 1; -} - -inline u32 get_efikasb_rev(void) -{ - u32 rev = 0; - - mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_EIM_CS3, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3))) << 0; - - mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_EIM_CS4, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4))) << 1; - - return rev; -} - -inline uint32_t get_efika_rev(void) -{ - if (machine_is_efikamx()) - return get_efikamx_rev(); - else - return get_efikasb_rev(); -} - -u32 get_board_rev(void) -{ - return get_cpu_rev() | (get_efika_rev() << 8); -} - -/* - * DRAM initialization - */ -int dram_init(void) -{ - /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); - return 0; -} - -/* - * UART configuration - */ -static void setup_iomux_uart(void) -{ - unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | - PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH; - - mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad); - mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad); -} - -/* - * SPI configuration - */ -#ifdef CONFIG_MXC_SPI -static void setup_iomux_spi(void) -{ - /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */ - mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - - /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - - /* Configure SS0 as a GPIO */ - mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0); - - /* Configure SS1 as a GPIO */ - mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1); - - /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); - - /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); -} -#else -static inline void setup_iomux_spi(void) { } -#endif - -/* - * PMIC configuration - */ -#ifdef CONFIG_MXC_SPI -static void power_init(void) -{ - unsigned int val; - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; - struct pmic *p; - - pmic_init(); - p = get_pmic(); - - /* Write needed to Power Gate 2 register */ - pmic_reg_read(p, REG_POWER_MISC, &val); - val &= ~PWGT2SPIEN; - pmic_reg_write(p, REG_POWER_MISC, val); - - /* Externally powered */ - pmic_reg_read(p, REG_CHARGE, &val); - val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB; - pmic_reg_write(p, REG_CHARGE, val); - - /* power up the system first */ - pmic_reg_write(p, REG_POWER_MISC, PWUP); - - /* Set core voltage to 1.1V */ - pmic_reg_read(p, REG_SW_0, &val); - val = (val & ~SWx_VOLT_MASK) | SWx_1_200V; - pmic_reg_write(p, REG_SW_0, val); - - /* Setup VCC (SW2) to 1.25 */ - pmic_reg_read(p, REG_SW_1, &val); - val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; - pmic_reg_write(p, REG_SW_1, val); - - /* Setup 1V2_DIG1 (SW3) to 1.25 */ - pmic_reg_read(p, REG_SW_2, &val); - val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; - pmic_reg_write(p, REG_SW_2, val); - udelay(50); - - /* Raise the core frequency to 800MHz */ - writel(0x0, &mxc_ccm->cacrr); - - /* Set switchers in Auto in NORMAL mode & STANDBY mode */ - /* Setup the switcher mode for SW1 & SW2*/ - pmic_reg_read(p, REG_SW_4, &val); - val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | - (SWMODE_MASK << SWMODE2_SHIFT))); - val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | - (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); - pmic_reg_write(p, REG_SW_4, val); - - /* Setup the switcher mode for SW3 & SW4 */ - pmic_reg_read(p, REG_SW_5, &val); - val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) | - (SWMODE_MASK << SWMODE4_SHIFT))); - val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) | - (SWMODE_AUTO_AUTO << SWMODE4_SHIFT); - pmic_reg_write(p, REG_SW_5, val); - - /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */ - pmic_reg_read(p, REG_SETTING_0, &val); - val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK); - val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6; - pmic_reg_write(p, REG_SETTING_0, val); - - /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ - pmic_reg_read(p, REG_SETTING_1, &val); - val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); - val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15; - pmic_reg_write(p, REG_SETTING_1, val); - - /* Enable VGEN1, VGEN2, VDIG, VPLL */ - pmic_reg_read(p, REG_MODE_0, &val); - val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN; - pmic_reg_write(p, REG_MODE_0, val); - - /* Configure VGEN3 and VCAM regulators to use external PNP */ - val = VGEN3CONFIG | VCAMCONFIG; - pmic_reg_write(p, REG_MODE_1, val); - udelay(200); - - /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ - val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | - VVIDEOEN | VAUDIOEN | VSDEN; - pmic_reg_write(p, REG_MODE_1, val); - - pmic_reg_read(p, REG_POWER_CTL2, &val); - val |= WDIRESET; - pmic_reg_write(p, REG_POWER_CTL2, val); - - udelay(2500); -} -#else -static inline void power_init(void) { } -#endif - -/* - * MMC configuration - */ -#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg esdhc_cfg[2] = { - {MMC_SDHC1_BASE_ADDR, 1}, - {MMC_SDHC2_BASE_ADDR, 1}, -}; - -static inline uint32_t efika_mmc_cd(void) -{ - if (machine_is_efikamx()) - return MX51_PIN_GPIO1_0; - else - return MX51_PIN_EIM_CS2; -} - -int board_mmc_getcd(struct mmc *mmc) -{ - struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - uint32_t cd = efika_mmc_cd(); - int ret; - - if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - ret = !gpio_get_value(IOMUX_TO_GPIO(cd)); - else - ret = !gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8)); - - return ret; -} - -int board_mmc_init(bd_t *bis) -{ - int ret; - uint32_t cd = efika_mmc_cd(); - - /* SDHC1 is used on all revisions, setup control pins first */ - mxc_request_iomux(cd, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(cd, - PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | - PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | - PAD_CTL_ODE_OPENDRAIN_NONE | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_GPIO1_1, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_1, - PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | - PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | - PAD_CTL_SRE_FAST); - - gpio_direction_input(IOMUX_TO_GPIO(cd)); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1)); - - /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */ - if (machine_is_efikasb() || (machine_is_efikamx() && - (get_efika_rev() < EFIKAMX_BOARD_REV_12))) { - /* SDHC1 IOMUX */ - mxc_request_iomux(MX51_PIN_SD1_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CMD, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_CLK, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CLK, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - /* SDHC2 IOMUX */ - mxc_request_iomux(MX51_PIN_SD2_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD2_CMD, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_CLK, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD2_CLK, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - /* SDHC2 Control lines IOMUX */ - mxc_request_iomux(MX51_PIN_GPIO1_7, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_7, - PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | - PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | - PAD_CTL_ODE_OPENDRAIN_NONE | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_GPIO1_8, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_8, - PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | - PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | - PAD_CTL_SRE_FAST); - - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8)); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7)); - - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); - if (!ret) - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]); - } else { /* New boards use only SDHC1 */ - /* SDHC1 IOMUX */ - mxc_request_iomux(MX51_PIN_SD1_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CMD, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_CLK, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CLK, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); - } - - return ret; -} -#endif - -/* - * ATA - */ -#ifdef CONFIG_MX51_PATA -#define ATA_PAD_CONFIG (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH) -void setup_iomux_ata(void) -{ - mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D0, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D1, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D2, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D3, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D4, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D5, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D6, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D7, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D8, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D9, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D10, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D11, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D12, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D13, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D14, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D15, ATA_PAD_CONFIG); -} -#else -static inline void setup_iomux_ata(void) { } -#endif - -/* - * EHCI USB - */ -#ifdef CONFIG_CMD_USB -extern void setup_iomux_usb(void); -#else -static inline void setup_iomux_usb(void) { } -#endif - -/* - * LED configuration - */ -void setup_iomux_led(void) -{ - if (machine_is_efikamx()) { - /* Blue LED */ - mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0); - - /* Green LED */ - mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), 0); - - /* Red LED */ - mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), 0); - } else { - /* CAPS-LOCK LED */ - mxc_request_iomux(MX51_PIN_EIM_CS0, IOMUX_CONFIG_GPIO); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0), 0); - - /* ALARM-LED LED */ - mxc_request_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_GPIO); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), 0); - } -} - -void efikamx_toggle_led(uint32_t mask) -{ - if (machine_is_efikamx()) { - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), - mask & EFIKAMX_LED_BLUE); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), - mask & EFIKAMX_LED_GREEN); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), - mask & EFIKAMX_LED_RED); - } else { - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0), - mask & EFIKAMX_LED_BLUE); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), - !(mask & EFIKAMX_LED_GREEN)); - } -} - -/* - * Board initialization - */ -static void init_drive_strength(void) -{ - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS, - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS, - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM); - - /* Setting pad options */ - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); -} - -int board_early_init_f(void) -{ - init_drive_strength(); - - setup_iomux_uart(); - setup_iomux_spi(); - setup_iomux_led(); - - return 0; -} - -int board_init(void) -{ - gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - - return 0; -} - -int board_late_init(void) -{ - setup_iomux_spi(); - - power_init(); - - setup_iomux_led(); - setup_iomux_ata(); - setup_iomux_usb(); - - if (machine_is_efikasb()) - setenv("preboot", "usb reset ; setenv stdin usbkbd\0"); - - setup_iomux_led(); - - efikamx_toggle_led(EFIKAMX_LED_BLUE); - - return 0; -} - -int checkboard(void) -{ - u32 rev = get_efika_rev(); - - if (machine_is_efikamx()) { - printf("Board: Efika MX, rev1.%i\n", rev & 0xf); - return 0; - } else { - switch (rev) { - case EFIKASB_BOARD_REV_13: - printf("Board: Efika SB rev1.3\n"); - break; - case EFIKASB_BOARD_REV_20: - printf("Board: Efika SB rev2.0\n"); - break; - default: - printf("Board: Efika SB, rev Unknown\n"); - break; - } - } - - return 0; -} diff --git a/board/efikamx/imximage_mx.cfg b/board/efikamx/imximage_mx.cfg deleted file mode 100644 index 6fe0ff9..0000000 --- a/board/efikamx/imximage_mx.cfg +++ /dev/null @@ -1,122 +0,0 @@ -# -# Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com -# -# BASED ON: imx51evk -# -# (C) Copyright 2009 -# Stefano Babic DENX Software Engineering sbabic@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not write to the Free Software -# Foundation Inc. 51 Franklin Street Fifth Floor Boston, -# MA 02110-1301 USA -# -# Refer docs/README.imxmage for more details about how-to configure -# and create imximage boot image -# -# The syntax is taken as close as possible with the kwbimage - -# Boot Device : one of -# spi, sd (the board has no nand neither onenand) -BOOT_FROM spi - -# Device Configuration Data (DCD) -# -# Each entry must have the format: -# Addr-type Address Value -# -# where: -# Addr-type register length (1,2 or 4 bytes) -# Address absolute address of the register -# value value to be stored in the register - -# Setting IOMUXC -DATA 4 0x73fa88a0 0x000 -DATA 4 0x73fa850c 0x20c5 -DATA 4 0x73fa8510 0x20c5 -DATA 4 0x73fa883c 0x5 -DATA 4 0x73fa8848 0x5 -DATA 4 0x73fa84b8 0xe7 -DATA 4 0x73fa84bc 0x45 -DATA 4 0x73fa84c0 0x45 -DATA 4 0x73fa84c4 0x45 -DATA 4 0x73fa84c8 0x45 -DATA 4 0x73fa8820 0x0 -DATA 4 0x73fa84a4 0x5 -DATA 4 0x73fa84a8 0x5 -DATA 4 0x73fa84ac 0xe5 -DATA 4 0x73fa84b0 0xe5 -DATA 4 0x73fa84b4 0xe5 -DATA 4 0x73fa84cc 0xe5 -DATA 4 0x73fa84d0 0xe4 - -DATA 4 0x73fa882c 0x4 -DATA 4 0x73fa88a4 0x4 -DATA 4 0x73fa88ac 0x4 -DATA 4 0x73fa88b8 0x4 - -# Setting DDR for micron -# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model -# CAS=3 BL=4 -# ESDCTL_ESDCTL0 -DATA 4 0x83fd9000 0x82a20000 -# ESDCTL_ESDCTL1 -DATA 4 0x83fd9008 0x82a20000 -# ESDCTL_ESDMISC -DATA 4 0x83fd9010 0xcaaaf6d0 -# ESDCTL_ESDCFG0 -DATA 4 0x83fd9004 0x3f3574aa -# ESDCTL_ESDCFG1 -DATA 4 0x83fd900c 0x3f3574aa - -# Init DRAM on CS0 -# ESDCTL_ESDSCR -DATA 4 0x83fd9014 0x04008008 -DATA 4 0x83fd9014 0x0000801a -DATA 4 0x83fd9014 0x0000801b -DATA 4 0x83fd9014 0x00448019 -DATA 4 0x83fd9014 0x07328018 -DATA 4 0x83fd9014 0x04008008 -DATA 4 0x83fd9014 0x00008010 -DATA 4 0x83fd9014 0x00008010 -DATA 4 0x83fd9014 0x06328018 -DATA 4 0x83fd9014 0x03808019 -DATA 4 0x83fd9014 0x00408019 -DATA 4 0x83fd9014 0x00008000 - -# Init DRAM on CS1 -DATA 4 0x83fd9014 0x0400800c -DATA 4 0x83fd9014 0x0000801e -DATA 4 0x83fd9014 0x0000801f -DATA 4 0x83fd9014 0x0000801d -DATA 4 0x83fd9014 0x0732801c -DATA 4 0x83fd9014 0x0400800c -DATA 4 0x83fd9014 0x00008014 -DATA 4 0x83fd9014 0x00008014 -DATA 4 0x83fd9014 0x0632801c -DATA 4 0x83fd9014 0x0380801d -DATA 4 0x83fd9014 0x0040801d -DATA 4 0x83fd9014 0x00008004 - -# Write to CTL0 -DATA 4 0x83fd9000 0xb2a20000 -# Write to CTL1 -DATA 4 0x83fd9008 0xb2a20000 -# ESDMISC -DATA 4 0x83fd9010 0x000ad6d0 -#ESDCTL_ESDCDLYGD -DATA 4 0x83fd9034 0x90000000 -DATA 4 0x83fd9014 0x00000000 diff --git a/board/efikamx/imximage_sb.cfg b/board/efikamx/imximage_sb.cfg deleted file mode 100644 index 878146f..0000000 --- a/board/efikamx/imximage_sb.cfg +++ /dev/null @@ -1,122 +0,0 @@ -# -# Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com -# -# BASED ON: imx51evk -# -# (C) Copyright 2009 -# Stefano Babic DENX Software Engineering sbabic@denx.de. -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not write to the Free Software -# Foundation Inc. 51 Franklin Street Fifth Floor Boston, -# MA 02110-1301 USA -# -# Refer docs/README.imxmage for more details about how-to configure -# and create imximage boot image -# -# The syntax is taken as close as possible with the kwbimage - -# Boot Device : one of -# spi, sd (the board has no nand neither onenand) -BOOT_FROM spi - -# Device Configuration Data (DCD) -# -# Each entry must have the format: -# Addr-type Address Value -# -# where: -# Addr-type register length (1,2 or 4 bytes) -# Address absolute address of the register -# value value to be stored in the register - -# Setting IOMUXC -DATA 4 0x73fa88a0 0x200 -DATA 4 0x73fa850c 0x20c3 -DATA 4 0x73fa8510 0x20c3 -DATA 4 0x73fa883c 0x2 -DATA 4 0x73fa8848 0x2 -DATA 4 0x73fa84b8 0xe7 -DATA 4 0x73fa84bc 0x45 -DATA 4 0x73fa84c0 0x45 -DATA 4 0x73fa84c4 0x45 -DATA 4 0x73fa84c8 0x45 -DATA 4 0x73fa8820 0x0 -DATA 4 0x73fa84a4 0x5 -DATA 4 0x73fa84a8 0x5 -DATA 4 0x73fa84ac 0xe3 -DATA 4 0x73fa84b0 0xe3 -DATA 4 0x73fa84b4 0xe3 -DATA 4 0x73fa84cc 0xe3 -DATA 4 0x73fa84d0 0xe2 - -DATA 4 0x73fa882c 0x4 -DATA 4 0x73fa88a4 0x4 -DATA 4 0x73fa88ac 0x4 -DATA 4 0x73fa88b8 0x4 - -# Setting DDR for micron -# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model -# CAS=3 BL=4 -# ESDCTL_ESDCTL0 -DATA 4 0x83fd9000 0x82a20000 -# ESDCTL_ESDCTL1 -DATA 4 0x83fd9008 0x82a20000 -# ESDCTL_ESDMISC -DATA 4 0x83fd9010 0xcaaaf6d0 -# ESDCTL_ESDCFG0 -DATA 4 0x83fd9004 0x333574aa -# ESDCTL_ESDCFG1 -DATA 4 0x83fd900c 0x333574aa - -# Init DRAM on CS0 -# ESDCTL_ESDSCR -DATA 4 0x83fd9014 0x04008008 -DATA 4 0x83fd9014 0x0000801a -DATA 4 0x83fd9014 0x0000801b -DATA 4 0x83fd9014 0x00448019 -DATA 4 0x83fd9014 0x07328018 -DATA 4 0x83fd9014 0x04008008 -DATA 4 0x83fd9014 0x00008010 -DATA 4 0x83fd9014 0x00008010 -DATA 4 0x83fd9014 0x06328018 -DATA 4 0x83fd9014 0x03808019 -DATA 4 0x83fd9014 0x00408019 -DATA 4 0x83fd9014 0x00008000 - -# Init DRAM on CS1 -DATA 4 0x83fd9014 0x0400800c -DATA 4 0x83fd9014 0x0000801e -DATA 4 0x83fd9014 0x0000801f -DATA 4 0x83fd9014 0x0000801d -DATA 4 0x83fd9014 0x0732801c -DATA 4 0x83fd9014 0x0400800c -DATA 4 0x83fd9014 0x00008014 -DATA 4 0x83fd9014 0x00008014 -DATA 4 0x83fd9014 0x0632801c -DATA 4 0x83fd9014 0x0380801d -DATA 4 0x83fd9014 0x0040801d -DATA 4 0x83fd9014 0x00008004 - -# Write to CTL0 -DATA 4 0x83fd9000 0xb2a20000 -# Write to CTL1 -DATA 4 0x83fd9008 0xb2a20000 -# ESDMISC -DATA 4 0x83fd9010 0xcaaaf6d0 -#ESDCTL_ESDCDLYGD -DATA 4 0x83fd9034 0x90000000 -DATA 4 0x83fd9014 0x00000000 diff --git a/board/genesi/mx51_efikamx/Makefile b/board/genesi/mx51_efikamx/Makefile new file mode 100644 index 0000000..bd2174f --- /dev/null +++ b/board/genesi/mx51_efikamx/Makefile @@ -0,0 +1,49 @@ +# +# Copyright (C) 2010, Marek Vasut marek.vasut@gmail.com +# +# BASED ON: imx51evk +# +# Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de +# +# (C) Copyright 2009 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS := efikamx.o + +ifdef CONFIG_CMD_USB +COBJS += efikamx-usb.o +endif + +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/genesi/mx51_efikamx/efikamx-usb.c b/board/genesi/mx51_efikamx/efikamx-usb.c new file mode 100644 index 0000000..e9273d0 --- /dev/null +++ b/board/genesi/mx51_efikamx/efikamx-usb.c @@ -0,0 +1,216 @@ +/* + * Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <usb.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx5x_pins.h> +#include <asm/arch/iomux.h> +#include <asm/gpio.h> +#include <usb/ehci-fsl.h> +#include <usb/ulpi.h> +#include <errno.h> + +#include "../../../drivers/usb/host/ehci.h" + +/* USB pin configuration */ +#define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \ + PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \ + PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL) + +/* + * Configure the USB H1 and USB H2 IOMUX + */ +void setup_iomux_usb(void) +{ + setup_iomux_usb_h1(); + + if (machine_is_efikasb()) + setup_iomux_usb_h2(); + + /* USB PHY reset */ + mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_PKE_ENABLE | + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); + + /* USB HUB reset */ + mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_PKE_ENABLE | + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); + + /* WIFI EN (act low) */ + mxc_request_iomux(MX51_PIN_EIM_A22, IOMUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX51_PIN_EIM_A22, 0); + /* WIFI RESET */ + mxc_request_iomux(MX51_PIN_EIM_A16, IOMUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX51_PIN_EIM_A16, 0); + /* BT EN (act low) */ + mxc_request_iomux(MX51_PIN_EIM_A17, IOMUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX51_PIN_EIM_A17, 0); +} + +/* + * Enable devices connected to USB BUSes + */ +static void efika_usb_enable_devices(void) +{ + /* Enable Bluetooth */ + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 0); + udelay(10000); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 1); + + /* Enable WiFi */ + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), 1); + udelay(10000); + + /* Reset the WiFi chip */ + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 0); + udelay(10000); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 1); +} + +/* + * Reset USB HUB (or HUBs on EfikaSB) + */ +static void efika_usb_hub_reset(void) +{ + /* HUB reset */ + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1); + udelay(1000); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 0); + udelay(1000); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1); +} + +/* + * Reset USB PHY (or PHYs on EfikaSB) + */ +static void efika_usb_phy_reset(void) +{ + /* SMSC 3317 PHY reset */ + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 0); + udelay(1000); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1); +} + +static void efika_ehci_init(struct usb_ehci *ehci, uint32_t stp_gpio, + uint32_t alt0, uint32_t alt1) +{ + int ret; + struct ulpi_regs *ulpi = (struct ulpi_regs *)0; + struct ulpi_viewport ulpi_vp; + + mxc_request_iomux(stp_gpio, alt0); + mxc_iomux_set_pad(stp_gpio, PAD_CTL_DRV_HIGH | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + gpio_direction_output(IOMUX_TO_GPIO(stp_gpio), 0); + udelay(1000); + gpio_set_value(IOMUX_TO_GPIO(stp_gpio), 1); + udelay(1000); + + mxc_request_iomux(stp_gpio, alt1); + mxc_iomux_set_pad(stp_gpio, USB_PAD_CONFIG); + udelay(10000); + + ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint; + ulpi_vp.port_num = 0; + + ret = ulpi_init(&ulpi_vp); + if (ret) { + printf("Efika USB ULPI initialization failed\n"); + return; + } + + /* ULPI set flags */ + ulpi_write(&ulpi_vp, &ulpi->otg_ctrl, + ULPI_OTG_DP_PULLDOWN | ULPI_OTG_DM_PULLDOWN | + ULPI_OTG_EXTVBUSIND); + ulpi_write(&ulpi_vp, &ulpi->function_ctrl, + ULPI_FC_FULL_SPEED | ULPI_FC_OPMODE_NORMAL | + ULPI_FC_SUSPENDM); + ulpi_write(&ulpi_vp, &ulpi->iface_ctrl, 0); + + /* Set VBus */ + ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, + ULPI_OTG_DRVVBUS | ULPI_OTG_DRVVBUS_EXT); + + /* + * Set VBusChrg + * + * NOTE: This violates USB specification, but otherwise, USB on Efika + * doesn't work. + */ + ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, ULPI_OTG_CHRGVBUS); +} + +int board_ehci_hcd_init(int port) +{ + /* Init iMX51 EHCI */ + efika_usb_phy_reset(); + efika_usb_hub_reset(); + efika_usb_enable_devices(); + + return 0; +} + +void ehci_powerup_fixup(uint32_t *status_reg, uint32_t *reg) +{ + uint32_t port = OTG_BASE_ADDR + (0x200 * CONFIG_MXC_USB_PORT); + struct usb_ehci *ehci = (struct usb_ehci *)port; + struct ulpi_regs *ulpi = (struct ulpi_regs *)0; + struct ulpi_viewport ulpi_vp; + + ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint; + ulpi_vp.port_num = 0; + + ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, ULPI_OTG_CHRGVBUS); + + mdelay(50); + + /* terminate the reset */ + *reg = ehci_readl(status_reg); + *reg |= EHCI_PS_PE; +} + +void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) +{ + uint32_t tmp; + + if (port == 0) { + /* Adjust UTMI PHY frequency to 24MHz */ + tmp = readl(OTG_BASE_ADDR + 0x80c); + tmp = (tmp & ~0x3) | 0x01; + writel(tmp, OTG_BASE_ADDR + 0x80c); + } else if (port == 1) { + efika_ehci_init(ehci, MX51_PIN_USBH1_STP, + IOMUX_CONFIG_ALT2, IOMUX_CONFIG_ALT0); + } else if ((port == 2) && machine_is_efikasb()) { + efika_ehci_init(ehci, MX51_PIN_EIM_A26, + IOMUX_CONFIG_ALT1, IOMUX_CONFIG_ALT2); + } + + if (port) + mdelay(10); +} diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c new file mode 100644 index 0000000..e88b2ed --- /dev/null +++ b/board/genesi/mx51_efikamx/efikamx.c @@ -0,0 +1,735 @@ +/* + * Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/imx-regs.h> +#include <asm/arch/mx5x_pins.h> +#include <asm/arch/iomux.h> +#include <asm/gpio.h> +#include <asm/errno.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/crm_regs.h> +#include <i2c.h> +#include <mmc.h> +#include <fsl_esdhc.h> +#include <pmic.h> +#include <fsl_pmic.h> +#include <mc13892.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Compile-time error checking + */ +#ifndef CONFIG_MXC_SPI +#error "CONFIG_MXC_SPI not set, this is essential for board's operation!" +#endif + +/* + * Shared variables / local defines + */ +/* LED */ +#define EFIKAMX_LED_BLUE 0x1 +#define EFIKAMX_LED_GREEN 0x2 +#define EFIKAMX_LED_RED 0x4 + +void efikamx_toggle_led(uint32_t mask); + +/* Board revisions */ +#define EFIKAMX_BOARD_REV_11 0x1 +#define EFIKAMX_BOARD_REV_12 0x2 +#define EFIKAMX_BOARD_REV_13 0x3 +#define EFIKAMX_BOARD_REV_14 0x4 + +#define EFIKASB_BOARD_REV_13 0x1 +#define EFIKASB_BOARD_REV_20 0x2 + +/* + * Board identification + */ +u32 get_efikamx_rev(void) +{ + u32 rev = 0; + /* + * Retrieve board ID: + * rev1.1: 1,1,1 + * rev1.2: 1,1,0 + * rev1.3: 1,0,1 + * rev1.4: 1,0,0 + */ + mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO); + /* set to 1 in order to get correct value on board rev1.1 */ + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1); + + mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU); + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0)); + rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0; + + mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU); + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1)); + rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1; + + mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU); + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3)); + rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2; + + return (~rev & 0x7) + 1; +} + +inline u32 get_efikasb_rev(void) +{ + u32 rev = 0; + + mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX51_PIN_EIM_CS3, PAD_CTL_100K_PU); + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3)); + rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3))) << 0; + + mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_GPIO); + mxc_iomux_set_pad(MX51_PIN_EIM_CS4, PAD_CTL_100K_PU); + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4)); + rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4))) << 1; + + return rev; +} + +inline uint32_t get_efika_rev(void) +{ + if (machine_is_efikamx()) + return get_efikamx_rev(); + else + return get_efikasb_rev(); +} + +u32 get_board_rev(void) +{ + return get_cpu_rev() | (get_efika_rev() << 8); +} + +/* + * DRAM initialization + */ +int dram_init(void) +{ + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, + PHYS_SDRAM_1_SIZE); + return 0; +} + +/* + * UART configuration + */ +static void setup_iomux_uart(void) +{ + unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH; + + mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST); + mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST); + mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad); + mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad); +} + +/* + * SPI configuration + */ +#ifdef CONFIG_MXC_SPI +static void setup_iomux_spi(void) +{ + /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */ + mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + + /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + + /* Configure SS0 as a GPIO */ + mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0); + + /* Configure SS1 as a GPIO */ + mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1); + + /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, + PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); + + /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */ + mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, + PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); +} +#else +static inline void setup_iomux_spi(void) { } +#endif + +/* + * PMIC configuration + */ +#ifdef CONFIG_MXC_SPI +static void power_init(void) +{ + unsigned int val; + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE; + struct pmic *p; + + pmic_init(); + p = get_pmic(); + + /* Write needed to Power Gate 2 register */ + pmic_reg_read(p, REG_POWER_MISC, &val); + val &= ~PWGT2SPIEN; + pmic_reg_write(p, REG_POWER_MISC, val); + + /* Externally powered */ + pmic_reg_read(p, REG_CHARGE, &val); + val |= ICHRG0 | ICHRG1 | ICHRG2 | ICHRG3 | CHGAUTOB; + pmic_reg_write(p, REG_CHARGE, val); + + /* power up the system first */ + pmic_reg_write(p, REG_POWER_MISC, PWUP); + + /* Set core voltage to 1.1V */ + pmic_reg_read(p, REG_SW_0, &val); + val = (val & ~SWx_VOLT_MASK) | SWx_1_200V; + pmic_reg_write(p, REG_SW_0, val); + + /* Setup VCC (SW2) to 1.25 */ + pmic_reg_read(p, REG_SW_1, &val); + val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; + pmic_reg_write(p, REG_SW_1, val); + + /* Setup 1V2_DIG1 (SW3) to 1.25 */ + pmic_reg_read(p, REG_SW_2, &val); + val = (val & ~SWx_VOLT_MASK) | SWx_1_250V; + pmic_reg_write(p, REG_SW_2, val); + udelay(50); + + /* Raise the core frequency to 800MHz */ + writel(0x0, &mxc_ccm->cacrr); + + /* Set switchers in Auto in NORMAL mode & STANDBY mode */ + /* Setup the switcher mode for SW1 & SW2*/ + pmic_reg_read(p, REG_SW_4, &val); + val = (val & ~((SWMODE_MASK << SWMODE1_SHIFT) | + (SWMODE_MASK << SWMODE2_SHIFT))); + val |= (SWMODE_AUTO_AUTO << SWMODE1_SHIFT) | + (SWMODE_AUTO_AUTO << SWMODE2_SHIFT); + pmic_reg_write(p, REG_SW_4, val); + + /* Setup the switcher mode for SW3 & SW4 */ + pmic_reg_read(p, REG_SW_5, &val); + val = (val & ~((SWMODE_MASK << SWMODE3_SHIFT) | + (SWMODE_MASK << SWMODE4_SHIFT))); + val |= (SWMODE_AUTO_AUTO << SWMODE3_SHIFT) | + (SWMODE_AUTO_AUTO << SWMODE4_SHIFT); + pmic_reg_write(p, REG_SW_5, val); + + /* Set VDIG to 1.8V, VGEN3 to 1.8V, VCAM to 2.6V */ + pmic_reg_read(p, REG_SETTING_0, &val); + val &= ~(VCAM_MASK | VGEN3_MASK | VDIG_MASK); + val |= VDIG_1_8 | VGEN3_1_8 | VCAM_2_6; + pmic_reg_write(p, REG_SETTING_0, val); + + /* Set VVIDEO to 2.775V, VAUDIO to 3V, VSD to 3.15V */ + pmic_reg_read(p, REG_SETTING_1, &val); + val &= ~(VVIDEO_MASK | VSD_MASK | VAUDIO_MASK); + val |= VSD_3_15 | VAUDIO_3_0 | VVIDEO_2_775 | VGEN1_1_2 | VGEN2_3_15; + pmic_reg_write(p, REG_SETTING_1, val); + + /* Enable VGEN1, VGEN2, VDIG, VPLL */ + pmic_reg_read(p, REG_MODE_0, &val); + val |= VGEN1EN | VDIGEN | VGEN2EN | VPLLEN; + pmic_reg_write(p, REG_MODE_0, val); + + /* Configure VGEN3 and VCAM regulators to use external PNP */ + val = VGEN3CONFIG | VCAMCONFIG; + pmic_reg_write(p, REG_MODE_1, val); + udelay(200); + + /* Enable VGEN3, VCAM, VAUDIO, VVIDEO, VSD regulators */ + val = VGEN3EN | VGEN3CONFIG | VCAMEN | VCAMCONFIG | + VVIDEOEN | VAUDIOEN | VSDEN; + pmic_reg_write(p, REG_MODE_1, val); + + pmic_reg_read(p, REG_POWER_CTL2, &val); + val |= WDIRESET; + pmic_reg_write(p, REG_POWER_CTL2, val); + + udelay(2500); +} +#else +static inline void power_init(void) { } +#endif + +/* + * MMC configuration + */ +#ifdef CONFIG_FSL_ESDHC +struct fsl_esdhc_cfg esdhc_cfg[2] = { + {MMC_SDHC1_BASE_ADDR, 1}, + {MMC_SDHC2_BASE_ADDR, 1}, +}; + +static inline uint32_t efika_mmc_cd(void) +{ + if (machine_is_efikamx()) + return MX51_PIN_GPIO1_0; + else + return MX51_PIN_EIM_CS2; +} + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + uint32_t cd = efika_mmc_cd(); + int ret; + + if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) + ret = !gpio_get_value(IOMUX_TO_GPIO(cd)); + else + ret = !gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8)); + + return ret; +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + uint32_t cd = efika_mmc_cd(); + + /* SDHC1 is used on all revisions, setup control pins first */ + mxc_request_iomux(cd, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(cd, + PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | + PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_request_iomux(MX51_PIN_GPIO1_1, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_GPIO1_1, + PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_SRE_FAST); + + gpio_direction_input(IOMUX_TO_GPIO(cd)); + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1)); + + /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */ + if (machine_is_efikasb() || (machine_is_efikamx() && + (get_efika_rev() < EFIKAMX_BOARD_REV_12))) { + /* SDHC1 IOMUX */ + mxc_request_iomux(MX51_PIN_SD1_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_SD1_CMD, + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX51_PIN_SD1_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_SD1_CLK, + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, + PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | + PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); + + /* SDHC2 IOMUX */ + mxc_request_iomux(MX51_PIN_SD2_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_SD2_CMD, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX51_PIN_SD2_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_SD2_CLK, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); + + /* SDHC2 Control lines IOMUX */ + mxc_request_iomux(MX51_PIN_GPIO1_7, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_GPIO1_7, + PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | + PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | + PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); + mxc_request_iomux(MX51_PIN_GPIO1_8, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_GPIO1_8, + PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | + PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | + PAD_CTL_SRE_FAST); + + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8)); + gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7)); + + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); + if (!ret) + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]); + } else { /* New boards use only SDHC1 */ + /* SDHC1 IOMUX */ + mxc_request_iomux(MX51_PIN_SD1_CMD, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_SD1_CMD, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX51_PIN_SD1_CLK, + IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); + mxc_iomux_set_pad(MX51_PIN_SD1_CLK, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); + + mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0); + mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, + PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); + + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); + } + + return ret; +} +#endif + +/* + * ATA + */ +#ifdef CONFIG_MX51_PATA +#define ATA_PAD_CONFIG (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH) +void setup_iomux_ata(void) +{ + mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D0, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D1, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D2, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D3, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D4, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D5, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D6, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D7, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D8, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D9, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D10, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D11, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D12, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D13, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D14, ATA_PAD_CONFIG); + mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1); + mxc_iomux_set_pad(MX51_PIN_NANDF_D15, ATA_PAD_CONFIG); +} +#else +static inline void setup_iomux_ata(void) { } +#endif + +/* + * EHCI USB + */ +#ifdef CONFIG_CMD_USB +extern void setup_iomux_usb(void); +#else +static inline void setup_iomux_usb(void) { } +#endif + +/* + * LED configuration + */ +void setup_iomux_led(void) +{ + if (machine_is_efikamx()) { + /* Blue LED */ + mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0); + + /* Green LED */ + mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), 0); + + /* Red LED */ + mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), 0); + } else { + /* CAPS-LOCK LED */ + mxc_request_iomux(MX51_PIN_EIM_CS0, IOMUX_CONFIG_GPIO); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0), 0); + + /* ALARM-LED LED */ + mxc_request_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_GPIO); + gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), 0); + } +} + +void efikamx_toggle_led(uint32_t mask) +{ + if (machine_is_efikamx()) { + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), + mask & EFIKAMX_LED_BLUE); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), + mask & EFIKAMX_LED_GREEN); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), + mask & EFIKAMX_LED_RED); + } else { + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0), + mask & EFIKAMX_LED_BLUE); + gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), + !(mask & EFIKAMX_LED_GREEN)); + } +} + +/* + * Board initialization + */ +static void init_drive_strength(void) +{ + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS, + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS, + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM); + mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM); + + /* Setting pad options */ + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); + mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3, + PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | + PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); +} + +int board_early_init_f(void) +{ + init_drive_strength(); + + setup_iomux_uart(); + setup_iomux_spi(); + setup_iomux_led(); + + return 0; +} + +int board_init(void) +{ + gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; + + return 0; +} + +int board_late_init(void) +{ + setup_iomux_spi(); + + power_init(); + + setup_iomux_led(); + setup_iomux_ata(); + setup_iomux_usb(); + + if (machine_is_efikasb()) + setenv("preboot", "usb reset ; setenv stdin usbkbd\0"); + + setup_iomux_led(); + + efikamx_toggle_led(EFIKAMX_LED_BLUE); + + return 0; +} + +int checkboard(void) +{ + u32 rev = get_efika_rev(); + + if (machine_is_efikamx()) { + printf("Board: Efika MX, rev1.%i\n", rev & 0xf); + return 0; + } else { + switch (rev) { + case EFIKASB_BOARD_REV_13: + printf("Board: Efika SB rev1.3\n"); + break; + case EFIKASB_BOARD_REV_20: + printf("Board: Efika SB rev2.0\n"); + break; + default: + printf("Board: Efika SB, rev Unknown\n"); + break; + } + } + + return 0; +} diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg new file mode 100644 index 0000000..6fe0ff9 --- /dev/null +++ b/board/genesi/mx51_efikamx/imximage_mx.cfg @@ -0,0 +1,122 @@ +# +# Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com +# +# BASED ON: imx51evk +# +# (C) Copyright 2009 +# Stefano Babic DENX Software Engineering sbabic@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not write to the Free Software +# Foundation Inc. 51 Franklin Street Fifth Floor Boston, +# MA 02110-1301 USA +# +# Refer docs/README.imxmage for more details about how-to configure +# and create imximage boot image +# +# The syntax is taken as close as possible with the kwbimage + +# Boot Device : one of +# spi, sd (the board has no nand neither onenand) +BOOT_FROM spi + +# Device Configuration Data (DCD) +# +# Each entry must have the format: +# Addr-type Address Value +# +# where: +# Addr-type register length (1,2 or 4 bytes) +# Address absolute address of the register +# value value to be stored in the register + +# Setting IOMUXC +DATA 4 0x73fa88a0 0x000 +DATA 4 0x73fa850c 0x20c5 +DATA 4 0x73fa8510 0x20c5 +DATA 4 0x73fa883c 0x5 +DATA 4 0x73fa8848 0x5 +DATA 4 0x73fa84b8 0xe7 +DATA 4 0x73fa84bc 0x45 +DATA 4 0x73fa84c0 0x45 +DATA 4 0x73fa84c4 0x45 +DATA 4 0x73fa84c8 0x45 +DATA 4 0x73fa8820 0x0 +DATA 4 0x73fa84a4 0x5 +DATA 4 0x73fa84a8 0x5 +DATA 4 0x73fa84ac 0xe5 +DATA 4 0x73fa84b0 0xe5 +DATA 4 0x73fa84b4 0xe5 +DATA 4 0x73fa84cc 0xe5 +DATA 4 0x73fa84d0 0xe4 + +DATA 4 0x73fa882c 0x4 +DATA 4 0x73fa88a4 0x4 +DATA 4 0x73fa88ac 0x4 +DATA 4 0x73fa88b8 0x4 + +# Setting DDR for micron +# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model +# CAS=3 BL=4 +# ESDCTL_ESDCTL0 +DATA 4 0x83fd9000 0x82a20000 +# ESDCTL_ESDCTL1 +DATA 4 0x83fd9008 0x82a20000 +# ESDCTL_ESDMISC +DATA 4 0x83fd9010 0xcaaaf6d0 +# ESDCTL_ESDCFG0 +DATA 4 0x83fd9004 0x3f3574aa +# ESDCTL_ESDCFG1 +DATA 4 0x83fd900c 0x3f3574aa + +# Init DRAM on CS0 +# ESDCTL_ESDSCR +DATA 4 0x83fd9014 0x04008008 +DATA 4 0x83fd9014 0x0000801a +DATA 4 0x83fd9014 0x0000801b +DATA 4 0x83fd9014 0x00448019 +DATA 4 0x83fd9014 0x07328018 +DATA 4 0x83fd9014 0x04008008 +DATA 4 0x83fd9014 0x00008010 +DATA 4 0x83fd9014 0x00008010 +DATA 4 0x83fd9014 0x06328018 +DATA 4 0x83fd9014 0x03808019 +DATA 4 0x83fd9014 0x00408019 +DATA 4 0x83fd9014 0x00008000 + +# Init DRAM on CS1 +DATA 4 0x83fd9014 0x0400800c +DATA 4 0x83fd9014 0x0000801e +DATA 4 0x83fd9014 0x0000801f +DATA 4 0x83fd9014 0x0000801d +DATA 4 0x83fd9014 0x0732801c +DATA 4 0x83fd9014 0x0400800c +DATA 4 0x83fd9014 0x00008014 +DATA 4 0x83fd9014 0x00008014 +DATA 4 0x83fd9014 0x0632801c +DATA 4 0x83fd9014 0x0380801d +DATA 4 0x83fd9014 0x0040801d +DATA 4 0x83fd9014 0x00008004 + +# Write to CTL0 +DATA 4 0x83fd9000 0xb2a20000 +# Write to CTL1 +DATA 4 0x83fd9008 0xb2a20000 +# ESDMISC +DATA 4 0x83fd9010 0x000ad6d0 +#ESDCTL_ESDCDLYGD +DATA 4 0x83fd9034 0x90000000 +DATA 4 0x83fd9014 0x00000000 diff --git a/board/genesi/mx51_efikamx/imximage_sb.cfg b/board/genesi/mx51_efikamx/imximage_sb.cfg new file mode 100644 index 0000000..878146f --- /dev/null +++ b/board/genesi/mx51_efikamx/imximage_sb.cfg @@ -0,0 +1,122 @@ +# +# Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com +# +# BASED ON: imx51evk +# +# (C) Copyright 2009 +# Stefano Babic DENX Software Engineering sbabic@denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not write to the Free Software +# Foundation Inc. 51 Franklin Street Fifth Floor Boston, +# MA 02110-1301 USA +# +# Refer docs/README.imxmage for more details about how-to configure +# and create imximage boot image +# +# The syntax is taken as close as possible with the kwbimage + +# Boot Device : one of +# spi, sd (the board has no nand neither onenand) +BOOT_FROM spi + +# Device Configuration Data (DCD) +# +# Each entry must have the format: +# Addr-type Address Value +# +# where: +# Addr-type register length (1,2 or 4 bytes) +# Address absolute address of the register +# value value to be stored in the register + +# Setting IOMUXC +DATA 4 0x73fa88a0 0x200 +DATA 4 0x73fa850c 0x20c3 +DATA 4 0x73fa8510 0x20c3 +DATA 4 0x73fa883c 0x2 +DATA 4 0x73fa8848 0x2 +DATA 4 0x73fa84b8 0xe7 +DATA 4 0x73fa84bc 0x45 +DATA 4 0x73fa84c0 0x45 +DATA 4 0x73fa84c4 0x45 +DATA 4 0x73fa84c8 0x45 +DATA 4 0x73fa8820 0x0 +DATA 4 0x73fa84a4 0x5 +DATA 4 0x73fa84a8 0x5 +DATA 4 0x73fa84ac 0xe3 +DATA 4 0x73fa84b0 0xe3 +DATA 4 0x73fa84b4 0xe3 +DATA 4 0x73fa84cc 0xe3 +DATA 4 0x73fa84d0 0xe2 + +DATA 4 0x73fa882c 0x4 +DATA 4 0x73fa88a4 0x4 +DATA 4 0x73fa88ac 0x4 +DATA 4 0x73fa88b8 0x4 + +# Setting DDR for micron +# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model +# CAS=3 BL=4 +# ESDCTL_ESDCTL0 +DATA 4 0x83fd9000 0x82a20000 +# ESDCTL_ESDCTL1 +DATA 4 0x83fd9008 0x82a20000 +# ESDCTL_ESDMISC +DATA 4 0x83fd9010 0xcaaaf6d0 +# ESDCTL_ESDCFG0 +DATA 4 0x83fd9004 0x333574aa +# ESDCTL_ESDCFG1 +DATA 4 0x83fd900c 0x333574aa + +# Init DRAM on CS0 +# ESDCTL_ESDSCR +DATA 4 0x83fd9014 0x04008008 +DATA 4 0x83fd9014 0x0000801a +DATA 4 0x83fd9014 0x0000801b +DATA 4 0x83fd9014 0x00448019 +DATA 4 0x83fd9014 0x07328018 +DATA 4 0x83fd9014 0x04008008 +DATA 4 0x83fd9014 0x00008010 +DATA 4 0x83fd9014 0x00008010 +DATA 4 0x83fd9014 0x06328018 +DATA 4 0x83fd9014 0x03808019 +DATA 4 0x83fd9014 0x00408019 +DATA 4 0x83fd9014 0x00008000 + +# Init DRAM on CS1 +DATA 4 0x83fd9014 0x0400800c +DATA 4 0x83fd9014 0x0000801e +DATA 4 0x83fd9014 0x0000801f +DATA 4 0x83fd9014 0x0000801d +DATA 4 0x83fd9014 0x0732801c +DATA 4 0x83fd9014 0x0400800c +DATA 4 0x83fd9014 0x00008014 +DATA 4 0x83fd9014 0x00008014 +DATA 4 0x83fd9014 0x0632801c +DATA 4 0x83fd9014 0x0380801d +DATA 4 0x83fd9014 0x0040801d +DATA 4 0x83fd9014 0x00008004 + +# Write to CTL0 +DATA 4 0x83fd9000 0xb2a20000 +# Write to CTL1 +DATA 4 0x83fd9008 0xb2a20000 +# ESDMISC +DATA 4 0x83fd9010 0xcaaaf6d0 +#ESDCTL_ESDCDLYGD +DATA 4 0x83fd9034 0x90000000 +DATA 4 0x83fd9014 0x00000000 diff --git a/boards.cfg b/boards.cfg index edd750c..a9ec44b 100644 --- a/boards.cfg +++ b/boards.cfg @@ -215,8 +215,8 @@ integratorcp_cm946es arm arm946es integrator armltd ca9x4_ct_vxp arm armv7 vexpress armltd am335x_evm arm armv7 am335x ti am33xx highbank arm armv7 highbank - highbank -efikamx arm armv7 efikamx - mx5 efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/efikamx/imximage_mx.cfg -efikasb arm armv7 efikamx - mx5 efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/efikamx/imximage_sb.cfg +mx51_efikamx arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKAMX,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_mx.cfg +mx51_efikasb arm armv7 mx51_efikamx genesi mx5 mx51_efikamx:MACH_TYPE=MACH_TYPE_MX51_EFIKASB,IMX_CONFIG=board/genesi/mx51_efikamx/imximage_sb.cfg mx51evk arm armv7 mx51evk freescale mx5 mx51evk:IMX_CONFIG=board/freescale/mx51evk/imximage.cfg mx53ard arm armv7 mx53ard freescale mx5 mx53ard:IMX_CONFIG=board/freescale/mx53ard/imximage_dd3.cfg mx53evk arm armv7 mx53evk freescale mx5 mx53evk:IMX_CONFIG=board/freescale/mx53evk/imximage.cfg diff --git a/include/configs/efikamx.h b/include/configs/efikamx.h deleted file mode 100644 index 143b0f0..0000000 --- a/include/configs/efikamx.h +++ /dev/null @@ -1,274 +0,0 @@ -/* - * Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. - * - * Configuration settings for the MX51EVK Board - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#ifndef __CONFIG_H -#define __CONFIG_H - -#include <config_cmd_default.h> - -/* - * High Level Board Configuration Options - */ -/* An i.MX51 CPU */ -#define CONFIG_MX51 - -#define machine_is_efikamx() (CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKAMX) -#define machine_is_efikasb() (CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKASB) - -#include <asm/arch/imx-regs.h> - -#define CONFIG_SYS_MX5_HCLK 24000000 -#define CONFIG_SYS_MX5_CLK32 32768 -#define CONFIG_DISPLAY_CPUINFO -#define CONFIG_DISPLAY_BOARDINFO - -#define CONFIG_SYS_TEXT_BASE 0x97800000 - -#define CONFIG_L2_OFF -#define CONFIG_SYS_ICACHE_OFF -#define CONFIG_SYS_DCACHE_OFF - -/* - * Bootloader Components Configuration - */ -#define CONFIG_CMD_SPI -#define CONFIG_CMD_SF -#define CONFIG_CMD_MMC -#define CONFIG_CMD_FAT -#define CONFIG_CMD_EXT2 -#define CONFIG_CMD_IDE -#define CONFIG_CMD_NET -#define CONFIG_CMD_DATE -#undef CONFIG_CMD_IMLS - -/* - * Environmental settings - */ - -#define CONFIG_ENV_OFFSET (6 * 64 * 1024) -#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024) -#define CONFIG_ENV_SIZE (4 * 1024) - -/* - * ATAG setup - */ -#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ -#define CONFIG_REVISION_TAG -#define CONFIG_SETUP_MEMORY_TAGS -#define CONFIG_INITRD_TAG - -#define CONFIG_OF_LIBFDT 1 - -/* - * Size of malloc() pool - */ -#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) - -#define CONFIG_BOARD_EARLY_INIT_F -#define CONFIG_BOARD_LATE_INIT - -/* - * Hardware drivers - */ -#define CONFIG_MXC_UART -#define CONFIG_MXC_UART_BASE UART1_BASE -#define CONFIG_CONS_INDEX 1 -#define CONFIG_BAUDRATE 115200 - -#define CONFIG_MXC_GPIO - -/* - * SPI Interface - */ -#ifdef CONFIG_CMD_SPI - -#define CONFIG_HARD_SPI -#define CONFIG_MXC_SPI -#define CONFIG_DEFAULT_SPI_BUS 1 -#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) - -/* SPI FLASH */ -#ifdef CONFIG_CMD_SF - -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_SST -#define CONFIG_SF_DEFAULT_CS (1 | 121 << 8) -#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) -#define CONFIG_SF_DEFAULT_SPEED 25000000 - -#define CONFIG_ENV_SPI_CS (1 | 121 << 8) -#define CONFIG_ENV_SPI_BUS 0 -#define CONFIG_ENV_SPI_MAX_HZ 25000000 -#define CONFIG_ENV_SPI_MODE (SPI_MODE_0) -#define CONFIG_FSL_ENV_IN_SF -#define CONFIG_ENV_IS_IN_SPI_FLASH -#define CONFIG_SYS_NO_FLASH - -#else -#define CONFIG_ENV_IS_NOWHERE -#endif - -/* SPI PMIC */ -#define CONFIG_PMIC -#define CONFIG_PMIC_SPI -#define CONFIG_PMIC_FSL -#define CONFIG_FSL_PMIC_BUS 0 -#define CONFIG_FSL_PMIC_CS (0 | 120 << 8) -#define CONFIG_FSL_PMIC_CLK 25000000 -#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) -#define CONFIG_FSL_PMIC_BITLEN 32 -#define CONFIG_RTC_MC13XXX -#endif - -/* - * MMC Configs - */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_MMC -#define CONFIG_GENERIC_MMC -#define CONFIG_FSL_ESDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_ESDHC_NUM 2 -#endif - -/* - * ATA/IDE - */ -#ifdef CONFIG_CMD_IDE -#define CONFIG_LBA48 -#undef CONFIG_IDE_LED -#undef CONFIG_IDE_RESET - -#define CONFIG_MX51_PATA - -#define __io - -#define CONFIG_SYS_IDE_MAXBUS 1 -#define CONFIG_SYS_IDE_MAXDEVICE 1 - -#define CONFIG_SYS_ATA_BASE_ADDR 0x83fe0000 -#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 - -#define CONFIG_SYS_ATA_DATA_OFFSET 0xa0 -#define CONFIG_SYS_ATA_REG_OFFSET 0xa0 -#define CONFIG_SYS_ATA_ALT_OFFSET 0xd8 - -#define CONFIG_SYS_ATA_STRIDE 4 - -#define CONFIG_IDE_PREINIT -#define CONFIG_MXC_ATA_PIO_MODE 4 -#endif - -/* - * USB - */ -#define CONFIG_CMD_USB -#ifdef CONFIG_CMD_USB -#define CONFIG_USB_EHCI /* Enable EHCI USB support */ -#define CONFIG_USB_EHCI_MX5 -#define CONFIG_USB_ULPI -#define CONFIG_USB_ULPI_VIEWPORT -#define CONFIG_MXC_USB_PORT 1 -#if (CONFIG_MXC_USB_PORT == 0) -#define CONFIG_MXC_USB_PORTSC (1 << 28) -#define CONFIG_MXC_USB_FLAGS MXC_EHCI_INTERNAL_PHY -#else -#define CONFIG_MXC_USB_PORTSC (2 << 30) -#define CONFIG_MXC_USB_FLAGS 0 -#endif -#define CONFIG_EHCI_IS_TDI -#define CONFIG_USB_STORAGE -#define CONFIG_USB_HOST_ETHER -#define CONFIG_USB_KEYBOARD -#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP -#define CONFIG_PREBOOT -/* USB NET */ -#ifdef CONFIG_CMD_NET -#define CONFIG_USB_ETHER_ASIX -#define CONFIG_CMD_PING -#define CONFIG_CMD_DHCP -#endif -#endif /* CONFIG_CMD_USB */ - -/* - * Filesystems - */ -#ifdef CONFIG_CMD_FAT -#define CONFIG_DOS_PARTITION -#ifdef CONFIG_CMD_NET -#define CONFIG_CMD_NFS -#endif -#endif - -/* - * Miscellaneous configurable options - */ -#define CONFIG_ENV_OVERWRITE -#define CONFIG_BOOTDELAY 3 -#define CONFIG_LOADADDR 0x90800000 - -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ -#define CONFIG_SYS_PROMPT "Efika> " -#define CONFIG_AUTO_COMPLETE -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x90000000 -#define CONFIG_SYS_MEMTEST_END 0x90010000 - -#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR - -#define CONFIG_SYS_HZ 1000 -#define CONFIG_CMDLINE_EDITING - -/*----------------------------------------------------------------------- - * Stack sizes - * - * The stack sizes are set up in start.S using the settings below - */ -#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ - -/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 -#define PHYS_SDRAM_1 CSD0_BASE_ADDR -#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) - -#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) -#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) -#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -#define CONFIG_SYS_DDR_CLKSEL 0 -#define CONFIG_SYS_CLKTL_CBCDR 0x59E35145 - -#endif diff --git a/include/configs/mx51_efikamx.h b/include/configs/mx51_efikamx.h new file mode 100644 index 0000000..143b0f0 --- /dev/null +++ b/include/configs/mx51_efikamx.h @@ -0,0 +1,274 @@ +/* + * Copyright (C) 2007, Guennadi Liakhovetski lg@denx.de + * + * (C) Copyright 2009 Freescale Semiconductor, Inc. + * + * Configuration settings for the MX51EVK Board + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <config_cmd_default.h> + +/* + * High Level Board Configuration Options + */ +/* An i.MX51 CPU */ +#define CONFIG_MX51 + +#define machine_is_efikamx() (CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKAMX) +#define machine_is_efikasb() (CONFIG_MACH_TYPE == MACH_TYPE_MX51_EFIKASB) + +#include <asm/arch/imx-regs.h> + +#define CONFIG_SYS_MX5_HCLK 24000000 +#define CONFIG_SYS_MX5_CLK32 32768 +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +#define CONFIG_SYS_TEXT_BASE 0x97800000 + +#define CONFIG_L2_OFF +#define CONFIG_SYS_ICACHE_OFF +#define CONFIG_SYS_DCACHE_OFF + +/* + * Bootloader Components Configuration + */ +#define CONFIG_CMD_SPI +#define CONFIG_CMD_SF +#define CONFIG_CMD_MMC +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_IDE +#define CONFIG_CMD_NET +#define CONFIG_CMD_DATE +#undef CONFIG_CMD_IMLS + +/* + * Environmental settings + */ + +#define CONFIG_ENV_OFFSET (6 * 64 * 1024) +#define CONFIG_ENV_SECT_SIZE (1 * 64 * 1024) +#define CONFIG_ENV_SIZE (4 * 1024) + +/* + * ATAG setup + */ +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_REVISION_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG + +#define CONFIG_OF_LIBFDT 1 + +/* + * Size of malloc() pool + */ +#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024) + +#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT + +/* + * Hardware drivers + */ +#define CONFIG_MXC_UART +#define CONFIG_MXC_UART_BASE UART1_BASE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_MXC_GPIO + +/* + * SPI Interface + */ +#ifdef CONFIG_CMD_SPI + +#define CONFIG_HARD_SPI +#define CONFIG_MXC_SPI +#define CONFIG_DEFAULT_SPI_BUS 1 +#define CONFIG_DEFAULT_SPI_MODE (SPI_MODE_0 | SPI_CS_HIGH) + +/* SPI FLASH */ +#ifdef CONFIG_CMD_SF + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SST +#define CONFIG_SF_DEFAULT_CS (1 | 121 << 8) +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) +#define CONFIG_SF_DEFAULT_SPEED 25000000 + +#define CONFIG_ENV_SPI_CS (1 | 121 << 8) +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_MAX_HZ 25000000 +#define CONFIG_ENV_SPI_MODE (SPI_MODE_0) +#define CONFIG_FSL_ENV_IN_SF +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_SYS_NO_FLASH + +#else +#define CONFIG_ENV_IS_NOWHERE +#endif + +/* SPI PMIC */ +#define CONFIG_PMIC +#define CONFIG_PMIC_SPI +#define CONFIG_PMIC_FSL +#define CONFIG_FSL_PMIC_BUS 0 +#define CONFIG_FSL_PMIC_CS (0 | 120 << 8) +#define CONFIG_FSL_PMIC_CLK 25000000 +#define CONFIG_FSL_PMIC_MODE (SPI_MODE_0 | SPI_CS_HIGH) +#define CONFIG_FSL_PMIC_BITLEN 32 +#define CONFIG_RTC_MC13XXX +#endif + +/* + * MMC Configs + */ +#ifdef CONFIG_CMD_MMC +#define CONFIG_MMC +#define CONFIG_GENERIC_MMC +#define CONFIG_FSL_ESDHC +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_NUM 2 +#endif + +/* + * ATA/IDE + */ +#ifdef CONFIG_CMD_IDE +#define CONFIG_LBA48 +#undef CONFIG_IDE_LED +#undef CONFIG_IDE_RESET + +#define CONFIG_MX51_PATA + +#define __io + +#define CONFIG_SYS_IDE_MAXBUS 1 +#define CONFIG_SYS_IDE_MAXDEVICE 1 + +#define CONFIG_SYS_ATA_BASE_ADDR 0x83fe0000 +#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0 + +#define CONFIG_SYS_ATA_DATA_OFFSET 0xa0 +#define CONFIG_SYS_ATA_REG_OFFSET 0xa0 +#define CONFIG_SYS_ATA_ALT_OFFSET 0xd8 + +#define CONFIG_SYS_ATA_STRIDE 4 + +#define CONFIG_IDE_PREINIT +#define CONFIG_MXC_ATA_PIO_MODE 4 +#endif + +/* + * USB + */ +#define CONFIG_CMD_USB +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_EHCI /* Enable EHCI USB support */ +#define CONFIG_USB_EHCI_MX5 +#define CONFIG_USB_ULPI +#define CONFIG_USB_ULPI_VIEWPORT +#define CONFIG_MXC_USB_PORT 1 +#if (CONFIG_MXC_USB_PORT == 0) +#define CONFIG_MXC_USB_PORTSC (1 << 28) +#define CONFIG_MXC_USB_FLAGS MXC_EHCI_INTERNAL_PHY +#else +#define CONFIG_MXC_USB_PORTSC (2 << 30) +#define CONFIG_MXC_USB_FLAGS 0 +#endif +#define CONFIG_EHCI_IS_TDI +#define CONFIG_USB_STORAGE +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP +#define CONFIG_PREBOOT +/* USB NET */ +#ifdef CONFIG_CMD_NET +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#endif +#endif /* CONFIG_CMD_USB */ + +/* + * Filesystems + */ +#ifdef CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#ifdef CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#endif +#endif + +/* + * Miscellaneous configurable options + */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_BOOTDELAY 3 +#define CONFIG_LOADADDR 0x90800000 + +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */ +#define CONFIG_SYS_PROMPT "Efika> " +#define CONFIG_AUTO_COMPLETE +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ + +#define CONFIG_SYS_MEMTEST_START 0x90000000 +#define CONFIG_SYS_MEMTEST_END 0x90010000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_HZ 1000 +#define CONFIG_CMDLINE_EDITING + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE_ADDR +#define PHYS_SDRAM_1_SIZE (512 * 1024 * 1024) + +#define CONFIG_SYS_SDRAM_BASE (PHYS_SDRAM_1) +#define CONFIG_SYS_INIT_RAM_ADDR (IRAM_BASE_ADDR) +#define CONFIG_SYS_INIT_RAM_SIZE (IRAM_SIZE) + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_DDR_CLKSEL 0 +#define CONFIG_SYS_CLKTL_CBCDR 0x59E35145 + +#endif
Dear Matt Sealey,
- Move Efika MX boards into "genesi" directory.
- Rename it to "mx51_efikamx" since there's an mx53 version out there.
Signed-off-by: Matt Sealey matt@genesi-usa.com
[...]
git format-patch -M -C will not generate such a huge patch. Please use that and resent after Stefano reviews.
Best regards, Marek Vasut
On Fri, Aug 17, 2012 at 4:01 PM, Marek Vasut marex@denx.de wrote:
Dear Matt Sealey,
- Move Efika MX boards into "genesi" directory.
- Rename it to "mx51_efikamx" since there's an mx53 version out there.
Signed-off-by: Matt Sealey matt@genesi-usa.com
[...]
git format-patch -M -C will not generate such a huge patch. Please use that and resent after Stefano reviews.
Waiting for review, then.
The i.MX Boot ROM lets us set up certain registers before U-Boot even gets executed. Rather than setting up DDR, putting U-Boot in place, and getting into pre-relocation init to set up DDR again, just do it once in the correct place. This also solves an issue where the Smarttop DDR pad settings were being applied on Smartbook.
While we're at it, configure PCBID0,1,2 and the LED GPIO since we've still got room in the DCD to do so.
Signed-off-by: Matt Sealey matt@genesi-usa.com --- board/genesi/mx51_efikamx/efikamx.c | 77 ------------------------- board/genesi/mx51_efikamx/imximage_mx.cfg | 89 +++++++++++++---------------- 2 files changed, 40 insertions(+), 126 deletions(-)
diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c index e88b2ed..12371c9 100644 --- a/board/genesi/mx51_efikamx/efikamx.c +++ b/board/genesi/mx51_efikamx/efikamx.c @@ -597,85 +597,8 @@ void efikamx_toggle_led(uint32_t mask) /* * Board initialization */ -static void init_drive_strength(void) -{ - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_DDR_INPUT_CMOS); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEADDR, PAD_CTL_PKE_ENABLE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPKS, PAD_CTL_PUE_KEEPER); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRAPUS, PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_A1, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A0, PAD_CTL_DRV_HIGH); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_A1, PAD_CTL_DRV_HIGH); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_RAS, - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CAS, - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_PKEDDR, PAD_CTL_PKE_ENABLE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPKS, PAD_CTL_PUE_KEEPER); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR0, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR1, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR2, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_HYSDDR3, PAD_CTL_HYS_NONE); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B0, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B1, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B2, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDR_SR_B4, PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DDRPUS, PAD_CTL_100K_PU); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_INMODE1, PAD_CTL_DDR_INPUT_CMOS); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B0, PAD_CTL_DRV_MEDIUM); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B1, PAD_CTL_DRV_MEDIUM); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B2, PAD_CTL_DRV_MEDIUM); - mxc_iomux_set_pad(MX51_PIN_CTL_GRP_DRAM_B4, PAD_CTL_DRV_MEDIUM); - - /* Setting pad options */ - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDWE, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCKE1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDCLK, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS2, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_SDQS3, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_CS1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM0, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM1, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM2, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - mxc_iomux_set_pad(MX51_PIN_CTL_DRAM_DQM3, - PAD_CTL_PKE_ENABLE | PAD_CTL_PUE_KEEPER | - PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); -} - int board_early_init_f(void) { - init_drive_strength(); - setup_iomux_uart(); setup_iomux_spi(); setup_iomux_led(); diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg index 6fe0ff9..ac9aa9a 100644 --- a/board/genesi/mx51_efikamx/imximage_mx.cfg +++ b/board/genesi/mx51_efikamx/imximage_mx.cfg @@ -1,7 +1,7 @@ # +# Copyright (C) 2009 Pegatron Corporation # Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com -# -# BASED ON: imx51evk +# Copyright (C) 2009-2012 Genesi USA, Inc. # # (C) Copyright 2009 # Stefano Babic DENX Software Engineering sbabic@denx.de. @@ -43,48 +43,44 @@ BOOT_FROM spi # Address absolute address of the register # value value to be stored in the register
-# Setting IOMUXC -DATA 4 0x73fa88a0 0x000 -DATA 4 0x73fa850c 0x20c5 -DATA 4 0x73fa8510 0x20c5 -DATA 4 0x73fa883c 0x5 -DATA 4 0x73fa8848 0x5 -DATA 4 0x73fa84b8 0xe7 -DATA 4 0x73fa84bc 0x45 -DATA 4 0x73fa84c0 0x45 -DATA 4 0x73fa84c4 0x45 -DATA 4 0x73fa84c8 0x45 -DATA 4 0x73fa8820 0x0 -DATA 4 0x73fa84a4 0x5 -DATA 4 0x73fa84a8 0x5 -DATA 4 0x73fa84ac 0xe5 -DATA 4 0x73fa84b0 0xe5 -DATA 4 0x73fa84b4 0xe5 -DATA 4 0x73fa84cc 0xe5 -DATA 4 0x73fa84d0 0xe4 +# Essential GPIO settings to be done as early as possible +# PCBID pad settings are all the defaults except #2 which needs HVE off +DATA 4 0x73fa8134 0x3 # PCBID0 ALT3 GPIO 3_16 +DATA 4 0x73fa8130 0x3 # PCBID1 ALT3 GPIO 3_17 +DATA 4 0x73fa8128 0x3 # PCBID2 ALT3 GPIO 3_11 +DATA 4 0x73fa8504 0xe4 # PCBID2 PAD ~HVE +DATA 4 0x73fa8198 0x3 # LED0 ALT3 GPIO 3_13 +DATA 4 0x73fa81c4 0x3 # LED1 ALT3 GPIO 3_14 +DATA 4 0x73fa81c8 0x3 # LED2 ALT3 GPIO 3_15
-DATA 4 0x73fa882c 0x4 -DATA 4 0x73fa88a4 0x4 -DATA 4 0x73fa88ac 0x4 -DATA 4 0x73fa88b8 0x4 +# DDR bus IOMUX PAD settings +DATA 4 0x73fa850c 0x20c5 # SDODT1 +DATA 4 0x73fa8510 0x20c5 # SDODT0 +DATA 4 0x73fa84ac 0xc5 # SDWE +DATA 4 0x73fa84b0 0xc5 # SDCKE0 +DATA 4 0x73fa84b4 0xc5 # SDCKE1 +DATA 4 0x73fa84cc 0xc5 # DRAM_CS0 +DATA 4 0x73fa84d0 0xc5 # DRAM_CS1 +DATA 4 0x73fa882c 0x2 # DRAM_B4 +DATA 4 0x73fa88a4 0x2 # DRAM_B0 +DATA 4 0x73fa88ac 0x2 # DRAM_B1 +DATA 4 0x73fa88b8 0x2 # DRAM_B2 +DATA 4 0x73fa84d4 0xc5 # DRAM_DQM0 +DATA 4 0x73fa84d8 0xc5 # DRAM_DQM1 +DATA 4 0x73fa84dc 0xc5 # DRAM_DQM2 +DATA 4 0x73fa84e0 0xc5 # DRAM_DQM3
-# Setting DDR for micron -# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model -# CAS=3 BL=4 -# ESDCTL_ESDCTL0 -DATA 4 0x83fd9000 0x82a20000 -# ESDCTL_ESDCTL1 -DATA 4 0x83fd9008 0x82a20000 -# ESDCTL_ESDMISC -DATA 4 0x83fd9010 0xcaaaf6d0 -# ESDCTL_ESDCFG0 -DATA 4 0x83fd9004 0x3f3574aa -# ESDCTL_ESDCFG1 -DATA 4 0x83fd900c 0x3f3574aa +# Setting DDR for Micron +# 13 Rows, 10 Cols, 32 bit +# SREF=4 Micron Model CAS=3 BL=4 +DATA 4 0x83fd9000 0x82a20000 # ESDCTL_ESDCTL0 +DATA 4 0x83fd9008 0x82a20000 # ESDCTL_ESDCTL1 +DATA 4 0x83fd9010 0xcaaaf6d0 # ESDCTL_ESDMISC +DATA 4 0x83fd9004 0x3f3574aa # ESDCTL_ESDCFG0 +DATA 4 0x83fd900c 0x3f3574aa # ESDCTL_ESDCFG1
# Init DRAM on CS0 -# ESDCTL_ESDSCR -DATA 4 0x83fd9014 0x04008008 +DATA 4 0x83fd9014 0x04008008 # ESDCTL_ESDSCR DATA 4 0x83fd9014 0x0000801a DATA 4 0x83fd9014 0x0000801b DATA 4 0x83fd9014 0x00448019 @@ -110,13 +106,8 @@ DATA 4 0x83fd9014 0x0632801c DATA 4 0x83fd9014 0x0380801d DATA 4 0x83fd9014 0x0040801d DATA 4 0x83fd9014 0x00008004 - -# Write to CTL0 -DATA 4 0x83fd9000 0xb2a20000 -# Write to CTL1 -DATA 4 0x83fd9008 0xb2a20000 -# ESDMISC -DATA 4 0x83fd9010 0x000ad6d0 -#ESDCTL_ESDCDLYGD -DATA 4 0x83fd9034 0x90000000 +DATA 4 0x83fd9000 0xb2a20000 # Write to CTL0 +DATA 4 0x83fd9008 0xb2a20000 # Write to CTL1 +DATA 4 0x83fd9010 0x000ad6d0 # ESDMISC +DATA 4 0x83fd9034 0x90000000 # ESDCTL_ESDCDLYGD DATA 4 0x83fd9014 0x00000000
Dear Matt Sealey,
The i.MX Boot ROM lets us set up certain registers before U-Boot even gets executed. Rather than setting up DDR, putting U-Boot in place, and getting into pre-relocation init to set up DDR again, just do it once in the correct place. This also solves an issue where the Smarttop DDR pad settings were being applied on Smartbook.
While we're at it, configure PCBID0,1,2 and the LED GPIO since we've still got room in the DCD to do so.
[...]
diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg index 6fe0ff9..ac9aa9a 100644 --- a/board/genesi/mx51_efikamx/imximage_mx.cfg +++ b/board/genesi/mx51_efikamx/imximage_mx.cfg @@ -1,7 +1,7 @@ # +# Copyright (C) 2009 Pegatron Corporation # Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com -# -# BASED ON: imx51evk
Adding and removing these at will won't work I'm afraid.
+# Copyright (C) 2009-2012 Genesi USA, Inc. # # (C) Copyright 2009 # Stefano Babic DENX Software Engineering sbabic@denx.de. @@ -43,48 +43,44 @@ BOOT_FROM spi # Address absolute address of the register # value value to be stored in the register
So what is the actual change in the file? You replaced it with different file, which makes it hard to review particular changes made.
-# Setting IOMUXC -DATA 4 0x73fa88a0 0x000 -DATA 4 0x73fa850c 0x20c5 -DATA 4 0x73fa8510 0x20c5 -DATA 4 0x73fa883c 0x5 -DATA 4 0x73fa8848 0x5 -DATA 4 0x73fa84b8 0xe7 -DATA 4 0x73fa84bc 0x45 -DATA 4 0x73fa84c0 0x45 -DATA 4 0x73fa84c4 0x45 -DATA 4 0x73fa84c8 0x45 -DATA 4 0x73fa8820 0x0 -DATA 4 0x73fa84a4 0x5 -DATA 4 0x73fa84a8 0x5 -DATA 4 0x73fa84ac 0xe5 -DATA 4 0x73fa84b0 0xe5 -DATA 4 0x73fa84b4 0xe5 -DATA 4 0x73fa84cc 0xe5 -DATA 4 0x73fa84d0 0xe4 +# Essential GPIO settings to be done as early as possible +# PCBID pad settings are all the defaults except #2 which needs HVE off +DATA 4 0x73fa8134 0x3 # PCBID0 ALT3 GPIO 3_16 +DATA 4 0x73fa8130 0x3 # PCBID1 ALT3 GPIO 3_17 +DATA 4 0x73fa8128 0x3 # PCBID2 ALT3 GPIO 3_11 +DATA 4 0x73fa8504 0xe4 # PCBID2 PAD ~HVE +DATA 4 0x73fa8198 0x3 # LED0 ALT3 GPIO 3_13 +DATA 4 0x73fa81c4 0x3 # LED1 ALT3 GPIO 3_14 +DATA 4 0x73fa81c8 0x3 # LED2 ALT3 GPIO 3_15
-DATA 4 0x73fa882c 0x4 -DATA 4 0x73fa88a4 0x4 -DATA 4 0x73fa88ac 0x4 -DATA 4 0x73fa88b8 0x4 +# DDR bus IOMUX PAD settings +DATA 4 0x73fa850c 0x20c5 # SDODT1 +DATA 4 0x73fa8510 0x20c5 # SDODT0 +DATA 4 0x73fa84ac 0xc5 # SDWE +DATA 4 0x73fa84b0 0xc5 # SDCKE0 +DATA 4 0x73fa84b4 0xc5 # SDCKE1 +DATA 4 0x73fa84cc 0xc5 # DRAM_CS0 +DATA 4 0x73fa84d0 0xc5 # DRAM_CS1 +DATA 4 0x73fa882c 0x2 # DRAM_B4 +DATA 4 0x73fa88a4 0x2 # DRAM_B0 +DATA 4 0x73fa88ac 0x2 # DRAM_B1 +DATA 4 0x73fa88b8 0x2 # DRAM_B2 +DATA 4 0x73fa84d4 0xc5 # DRAM_DQM0 +DATA 4 0x73fa84d8 0xc5 # DRAM_DQM1 +DATA 4 0x73fa84dc 0xc5 # DRAM_DQM2 +DATA 4 0x73fa84e0 0xc5 # DRAM_DQM3
-# Setting DDR for micron -# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model -# CAS=3 BL=4 -# ESDCTL_ESDCTL0 -DATA 4 0x83fd9000 0x82a20000 -# ESDCTL_ESDCTL1 -DATA 4 0x83fd9008 0x82a20000 -# ESDCTL_ESDMISC -DATA 4 0x83fd9010 0xcaaaf6d0 -# ESDCTL_ESDCFG0 -DATA 4 0x83fd9004 0x3f3574aa -# ESDCTL_ESDCFG1 -DATA 4 0x83fd900c 0x3f3574aa +# Setting DDR for Micron +# 13 Rows, 10 Cols, 32 bit +# SREF=4 Micron Model CAS=3 BL=4 +DATA 4 0x83fd9000 0x82a20000 # ESDCTL_ESDCTL0 +DATA 4 0x83fd9008 0x82a20000 # ESDCTL_ESDCTL1 +DATA 4 0x83fd9010 0xcaaaf6d0 # ESDCTL_ESDMISC +DATA 4 0x83fd9004 0x3f3574aa # ESDCTL_ESDCFG0 +DATA 4 0x83fd900c 0x3f3574aa # ESDCTL_ESDCFG1
# Init DRAM on CS0 -# ESDCTL_ESDSCR -DATA 4 0x83fd9014 0x04008008 +DATA 4 0x83fd9014 0x04008008 # ESDCTL_ESDSCR DATA 4 0x83fd9014 0x0000801a DATA 4 0x83fd9014 0x0000801b DATA 4 0x83fd9014 0x00448019 @@ -110,13 +106,8 @@ DATA 4 0x83fd9014 0x0632801c DATA 4 0x83fd9014 0x0380801d DATA 4 0x83fd9014 0x0040801d DATA 4 0x83fd9014 0x00008004
-# Write to CTL0 -DATA 4 0x83fd9000 0xb2a20000 -# Write to CTL1 -DATA 4 0x83fd9008 0xb2a20000 -# ESDMISC -DATA 4 0x83fd9010 0x000ad6d0 -#ESDCTL_ESDCDLYGD -DATA 4 0x83fd9034 0x90000000 +DATA 4 0x83fd9000 0xb2a20000 # Write to CTL0 +DATA 4 0x83fd9008 0xb2a20000 # Write to CTL1 +DATA 4 0x83fd9010 0x000ad6d0 # ESDMISC +DATA 4 0x83fd9034 0x90000000 # ESDCTL_ESDCDLYGD DATA 4 0x83fd9014 0x00000000
On Fri, Aug 17, 2012 at 4:03 PM, Marek Vasut marex@denx.de wrote:
Dear Matt Sealey,
The i.MX Boot ROM lets us set up certain registers before U-Boot even gets executed. Rather than setting up DDR, putting U-Boot in place, and getting into pre-relocation init to set up DDR again, just do it once in the correct place. This also solves an issue where the Smarttop DDR pad settings were being applied on Smartbook.
While we're at it, configure PCBID0,1,2 and the LED GPIO since we've still got room in the DCD to do so.
[...]
diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg index 6fe0ff9..ac9aa9a 100644 --- a/board/genesi/mx51_efikamx/imximage_mx.cfg +++ b/board/genesi/mx51_efikamx/imximage_mx.cfg @@ -1,7 +1,7 @@ # +# Copyright (C) 2009 Pegatron Corporation # Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com -# -# BASED ON: imx51evk
Adding and removing these at will won't work I'm afraid.
+# Copyright (C) 2009-2012 Genesi USA, Inc. # # (C) Copyright 2009 # Stefano Babic DENX Software Engineering sbabic@denx.de. @@ -43,48 +43,44 @@ BOOT_FROM spi # Address absolute address of the register # value value to be stored in the register
So what is the actual change in the file? You replaced it with different file, which makes it hard to review particular changes made.
Uhh no I edited each line manually and moved the comments to make it more readable. The actual changes is I reviewed the drive strength set function in efikamx.c and moved all the settings (minus any erroneously set bits and reproduced settings) into the DATA lines where necessary.
It's the same file but git doesn't do line-by-line diffs very well, it just seems to batch things into sections. I agree though I broke the copyright stuff, I got forced to use vim for about 10 minutes and I may have been a little heavy-handed :)
Dear Matt Sealey,
On Fri, Aug 17, 2012 at 4:03 PM, Marek Vasut marex@denx.de wrote:
Dear Matt Sealey,
The i.MX Boot ROM lets us set up certain registers before U-Boot even gets executed. Rather than setting up DDR, putting U-Boot in place, and getting into pre-relocation init to set up DDR again, just do it once in the correct place. This also solves an issue where the Smarttop DDR pad settings were being applied on Smartbook.
While we're at it, configure PCBID0,1,2 and the LED GPIO since we've still got room in the DCD to do so.
[...]
diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg index 6fe0ff9..ac9aa9a 100644 --- a/board/genesi/mx51_efikamx/imximage_mx.cfg +++ b/board/genesi/mx51_efikamx/imximage_mx.cfg @@ -1,7 +1,7 @@
#
+# Copyright (C) 2009 Pegatron Corporation
# Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com
-# -# BASED ON: imx51evk
Adding and removing these at will won't work I'm afraid.
+# Copyright (C) 2009-2012 Genesi USA, Inc.
# # (C) Copyright 2009 # Stefano Babic DENX Software Engineering sbabic@denx.de.
@@ -43,48 +43,44 @@ BOOT_FROM spi
# Address absolute address of the register # value value to be stored in the register
So what is the actual change in the file? You replaced it with different file, which makes it hard to review particular changes made.
Uhh no I edited each line manually and moved the comments to make it more readable. The actual changes is I reviewed the drive strength set function in efikamx.c and moved all the settings (minus any erroneously set bits and reproduced settings) into the DATA lines where necessary.
Maybe splitting it into smaller patches then won't hurt, with proper description etc.
It's the same file but git doesn't do line-by-line diffs very well, it just seems to batch things into sections. I agree though I broke the copyright stuff, I got forced to use vim for about 10 minutes and I may have been a little heavy-handed :)
Definitelly
Best regards, Marek Vasut
On 17/08/2012 20:19, Matt Sealey wrote:
The i.MX Boot ROM lets us set up certain registers before U-Boot even gets executed. Rather than setting up DDR, putting U-Boot in place, and getting into pre-relocation init to set up DDR again, just do it once in the correct place. This also solves an issue where the Smarttop DDR pad settings were being applied on Smartbook.
While we're at it, configure PCBID0,1,2 and the LED GPIO since we've still got room in the DCD to do so.
Signed-off-by: Matt Sealey matt@genesi-usa.com
Hi Matt,
diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg index 6fe0ff9..ac9aa9a 100644 --- a/board/genesi/mx51_efikamx/imximage_mx.cfg +++ b/board/genesi/mx51_efikamx/imximage_mx.cfg @@ -1,7 +1,7 @@ # +# Copyright (C) 2009 Pegatron Corporation
^---
Was this added for mistake ? I think you should add only yours.
# Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com -# -# BASED ON: imx51evk +# Copyright (C) 2009-2012 Genesi USA, Inc. # # (C) Copyright 2009 # Stefano Babic DENX Software Engineering sbabic@denx.de. @@ -43,48 +43,44 @@ BOOT_FROM spi # Address absolute address of the register # value value to be stored in the register
I agree with Marek that you break the copyright stuff.
-# Setting IOMUXC -DATA 4 0x73fa88a0 0x000 -DATA 4 0x73fa850c 0x20c5 -DATA 4 0x73fa8510 0x20c5 -DATA 4 0x73fa883c 0x5 -DATA 4 0x73fa8848 0x5 -DATA 4 0x73fa84b8 0xe7 -DATA 4 0x73fa84bc 0x45 -DATA 4 0x73fa84c0 0x45 -DATA 4 0x73fa84c4 0x45 -DATA 4 0x73fa84c8 0x45 -DATA 4 0x73fa8820 0x0 -DATA 4 0x73fa84a4 0x5 -DATA 4 0x73fa84a8 0x5 -DATA 4 0x73fa84ac 0xe5 -DATA 4 0x73fa84b0 0xe5 -DATA 4 0x73fa84b4 0xe5 -DATA 4 0x73fa84cc 0xe5 -DATA 4 0x73fa84d0 0xe4 +# Essential GPIO settings to be done as early as possible +# PCBID pad settings are all the defaults except #2 which needs HVE off +DATA 4 0x73fa8134 0x3 # PCBID0 ALT3 GPIO 3_16 +DATA 4 0x73fa8130 0x3 # PCBID1 ALT3 GPIO 3_17 +DATA 4 0x73fa8128 0x3 # PCBID2 ALT3 GPIO 3_11 +DATA 4 0x73fa8504 0xe4 # PCBID2 PAD ~HVE +DATA 4 0x73fa8198 0x3 # LED0 ALT3 GPIO 3_13 +DATA 4 0x73fa81c4 0x3 # LED1 ALT3 GPIO 3_14 +DATA 4 0x73fa81c8 0x3 # LED2 ALT3 GPIO 3_15
-DATA 4 0x73fa882c 0x4 -DATA 4 0x73fa88a4 0x4 -DATA 4 0x73fa88ac 0x4 -DATA 4 0x73fa88b8 0x4 +# DDR bus IOMUX PAD settings +DATA 4 0x73fa850c 0x20c5 # SDODT1 +DATA 4 0x73fa8510 0x20c5 # SDODT0 +DATA 4 0x73fa84ac 0xc5 # SDWE +DATA 4 0x73fa84b0 0xc5 # SDCKE0 +DATA 4 0x73fa84b4 0xc5 # SDCKE1 +DATA 4 0x73fa84cc 0xc5 # DRAM_CS0 +DATA 4 0x73fa84d0 0xc5 # DRAM_CS1 +DATA 4 0x73fa882c 0x2 # DRAM_B4 +DATA 4 0x73fa88a4 0x2 # DRAM_B0 +DATA 4 0x73fa88ac 0x2 # DRAM_B1 +DATA 4 0x73fa88b8 0x2 # DRAM_B2 +DATA 4 0x73fa84d4 0xc5 # DRAM_DQM0 +DATA 4 0x73fa84d8 0xc5 # DRAM_DQM1 +DATA 4 0x73fa84dc 0xc5 # DRAM_DQM2 +DATA 4 0x73fa84e0 0xc5 # DRAM_DQM3
-# Setting DDR for micron -# 13 Rows, 10 Cols, 32 bit, SREF=4 Micron Model -# CAS=3 BL=4 -# ESDCTL_ESDCTL0 -DATA 4 0x83fd9000 0x82a20000 -# ESDCTL_ESDCTL1 -DATA 4 0x83fd9008 0x82a20000 -# ESDCTL_ESDMISC -DATA 4 0x83fd9010 0xcaaaf6d0 -# ESDCTL_ESDCFG0 -DATA 4 0x83fd9004 0x3f3574aa -# ESDCTL_ESDCFG1 -DATA 4 0x83fd900c 0x3f3574aa +# Setting DDR for Micron +# 13 Rows, 10 Cols, 32 bit +# SREF=4 Micron Model CAS=3 BL=4 +DATA 4 0x83fd9000 0x82a20000 # ESDCTL_ESDCTL0 +DATA 4 0x83fd9008 0x82a20000 # ESDCTL_ESDCTL1 +DATA 4 0x83fd9010 0xcaaaf6d0 # ESDCTL_ESDMISC +DATA 4 0x83fd9004 0x3f3574aa # ESDCTL_ESDCFG0 +DATA 4 0x83fd900c 0x3f3574aa # ESDCTL_ESDCFG1
# Init DRAM on CS0 -# ESDCTL_ESDSCR -DATA 4 0x83fd9014 0x04008008 +DATA 4 0x83fd9014 0x04008008 # ESDCTL_ESDSCR DATA 4 0x83fd9014 0x0000801a DATA 4 0x83fd9014 0x0000801b DATA 4 0x83fd9014 0x00448019 @@ -110,13 +106,8 @@ DATA 4 0x83fd9014 0x0632801c DATA 4 0x83fd9014 0x0380801d DATA 4 0x83fd9014 0x0040801d DATA 4 0x83fd9014 0x00008004
-# Write to CTL0 -DATA 4 0x83fd9000 0xb2a20000 -# Write to CTL1 -DATA 4 0x83fd9008 0xb2a20000 -# ESDMISC -DATA 4 0x83fd9010 0x000ad6d0 -#ESDCTL_ESDCDLYGD -DATA 4 0x83fd9034 0x90000000 +DATA 4 0x83fd9000 0xb2a20000 # Write to CTL0 +DATA 4 0x83fd9008 0xb2a20000 # Write to CTL1 +DATA 4 0x83fd9010 0x000ad6d0 # ESDMISC +DATA 4 0x83fd9034 0x90000000 # ESDCTL_ESDCDLYGD DATA 4 0x83fd9014 0x00000000
I join Marek, it is quite difficult to review it and understand which was changed. It looks like a new file..
Best regards, Stefano Babic
On Sat, Aug 18, 2012 at 10:34 AM, Stefano Babic sbabic@denx.de wrote:
On 17/08/2012 20:19, Matt Sealey wrote:
The i.MX Boot ROM lets us set up certain registers before U-Boot even gets executed. Rather than setting up DDR, putting U-Boot in place, and getting into pre-relocation init to set up DDR again, just do it once in the correct place. This also solves an issue where the Smarttop DDR pad settings were being applied on Smartbook.
While we're at it, configure PCBID0,1,2 and the LED GPIO since we've still got room in the DCD to do so.
Signed-off-by: Matt Sealey matt@genesi-usa.com
Hi Matt,
diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg index 6fe0ff9..ac9aa9a 100644 --- a/board/genesi/mx51_efikamx/imximage_mx.cfg +++ b/board/genesi/mx51_efikamx/imximage_mx.cfg @@ -1,7 +1,7 @@ # +# Copyright (C) 2009 Pegatron Corporation
^---Was this added for mistake ? I think you should add only yours.
The drive strength settings came from Pegatron a long, long time ago (2009 :) and our old config and the function is copyrighted to them. Just because Marek took them out and recopyrighted the file I derived them from in this case doesn't mean they lost their copyright..
I join Marek, it is quite difficult to review it and understand which was changed. It looks like a new file..
It's just because I moved the comments to the end of the line, so it's blocking it up.
Sometimes it's nicer if it's
-this line +that line -this line +that line
.. but that's not how git does it when the change is more than a few characters and multiple lines changed.. I can submit it differently but I can't change the way it's producing the diff.
Dear Matt Sealey,
On Sat, Aug 18, 2012 at 10:34 AM, Stefano Babic sbabic@denx.de wrote:
On 17/08/2012 20:19, Matt Sealey wrote:
The i.MX Boot ROM lets us set up certain registers before U-Boot even gets executed. Rather than setting up DDR, putting U-Boot in place, and getting into pre-relocation init to set up DDR again, just do it once in the correct place. This also solves an issue where the Smarttop DDR pad settings were being applied on Smartbook.
While we're at it, configure PCBID0,1,2 and the LED GPIO since we've still got room in the DCD to do so.
Signed-off-by: Matt Sealey matt@genesi-usa.com
Hi Matt,
diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg index 6fe0ff9..ac9aa9a 100644 --- a/board/genesi/mx51_efikamx/imximage_mx.cfg +++ b/board/genesi/mx51_efikamx/imximage_mx.cfg @@ -1,7 +1,7 @@
#
+# Copyright (C) 2009 Pegatron Corporation
^---Was this added for mistake ? I think you should add only yours.
The drive strength settings came from Pegatron a long, long time ago (2009 :) and our old config and the function is copyrighted to them. Just because Marek took them out and recopyrighted the file I derived them from in this case doesn't mean they lost their copyright..
This file was taken from mx51evk. It's written there. Please stop this nonsense, it's troubling me.
I join Marek, it is quite difficult to review it and understand which was changed. It looks like a new file..
It's just because I moved the comments to the end of the line, so it's blocking it up.
Sometimes it's nicer if it's
-this line +that line -this line +that line
.. but that's not how git does it when the change is more than a few characters and multiple lines changed.. I can submit it differently but I can't change the way it's producing the diff.
Best regards, Marek Vasut
Am 19/08/2012 00:29, schrieb Marek Vasut:
Dear Matt Sealey,
On Sat, Aug 18, 2012 at 10:34 AM, Stefano Babic sbabic@denx.de wrote:
On 17/08/2012 20:19, Matt Sealey wrote:
The i.MX Boot ROM lets us set up certain registers before U-Boot even gets executed. Rather than setting up DDR, putting U-Boot in place, and getting into pre-relocation init to set up DDR again, just do it once in the correct place. This also solves an issue where the Smarttop DDR pad settings were being applied on Smartbook.
While we're at it, configure PCBID0,1,2 and the LED GPIO since we've still got room in the DCD to do so.
Signed-off-by: Matt Sealey matt@genesi-usa.com
Hi Matt,
diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg index 6fe0ff9..ac9aa9a 100644 --- a/board/genesi/mx51_efikamx/imximage_mx.cfg +++ b/board/genesi/mx51_efikamx/imximage_mx.cfg @@ -1,7 +1,7 @@
#
+# Copyright (C) 2009 Pegatron Corporation
^---Was this added for mistake ? I think you should add only yours.
The drive strength settings came from Pegatron a long, long time ago (2009 :) and our old config and the function is copyrighted to them. Just because Marek took them out and recopyrighted the file I derived them from in this case doesn't mean they lost their copyright..
This file was taken from mx51evk. It's written there. Please stop this nonsense, it's troubling me.
Then Pegatron has nothing to do with it. The original comes from Freescale, and the copyright was set.
Best regards, Stefano Babic
On Sat, Aug 18, 2012 at 5:56 PM, stefano babic sbabic@denx.de wrote:
Am 19/08/2012 00:29, schrieb Marek Vasut:
Dear Matt Sealey,
On Sat, Aug 18, 2012 at 10:34 AM, Stefano Babic sbabic@denx.de wrote:
On 17/08/2012 20:19, Matt Sealey wrote:
The i.MX Boot ROM lets us set up certain registers before U-Boot even gets executed. Rather than setting up DDR, putting U-Boot in place, and getting into pre-relocation init to set up DDR again, just do it once in the correct place. This also solves an issue where the Smarttop DDR pad settings were being applied on Smartbook.
While we're at it, configure PCBID0,1,2 and the LED GPIO since we've still got room in the DCD to do so.
Signed-off-by: Matt Sealey matt@genesi-usa.com
Hi Matt,
diff --git a/board/genesi/mx51_efikamx/imximage_mx.cfg b/board/genesi/mx51_efikamx/imximage_mx.cfg index 6fe0ff9..ac9aa9a 100644 --- a/board/genesi/mx51_efikamx/imximage_mx.cfg +++ b/board/genesi/mx51_efikamx/imximage_mx.cfg @@ -1,7 +1,7 @@
#
+# Copyright (C) 2009 Pegatron Corporation
^---Was this added for mistake ? I think you should add only yours.
The drive strength settings came from Pegatron a long, long time ago (2009 :) and our old config and the function is copyrighted to them. Just because Marek took them out and recopyrighted the file I derived them from in this case doesn't mean they lost their copyright..
This file was taken from mx51evk. It's written there. Please stop this nonsense, it's troubling me.
Then Pegatron has nothing to do with it. The original comes from Freescale, and the copyright was set.
Here is the pedigree of the code from initial table to current implementation, as it stands;
* 2009, Pegatron wrote their U-Boot port for the board * 2009, Pegatron gave us these drive strength settings based on some very expensive and laborious testing and calibration of the DDR implementation on the board. They did not update the settings in the DCD table, they just implemented this function which persisted in Marek's port to mainline * 2010, Marek took the mx51evk example and added the OLD DCD table to imximage.cfg and left the Pegatron drive strength code in there. Marek removed the Pegatron copyright, and Genesi's copyright, and Freescale's copyright but left the original code copyright he took from U-Boot. You cannot just remove the copyright pedigree from the chain just because you decided the "source" of the code was one guy when you copy paste it from some other place * 2012, we put the Pegatron copyrights back in, removed the drive strength function from the board file, re-integrated it into the imximage.cfg layout, and added our copyrights since we did the expensive and laborious testing of the values and cross-referencing of the manual.
The copyrights on every Efika MX file, since they were ALL ported from the original Pegatron reference code should be;
Copyright (C) 2009 Freescale Semiconductor Copyright (C) 2009 Pegatron Corporation Copyright (C) 2009-2012 Genesi USA, Inc. <name of the guy who you copied the mx51evk board file or imximage.cfg from> <your name here>
And that's that. We are looking to go about restoring the pedigree, that's all.
If this was a $5000 dog, you would be concerned if you found out someone had accidentally removed some history where it's grandmother bred with a mongrel and invalidated it's pure-bred status. I can assure you the money spent on coding this original code was more than the cost of a dog and the copyright chain should persist whether you think you "wrote" the code yourself or "copied" it from elsewhere in U-Boot.
The MX51EVK board files may have been where whoever originally committed them sourced it from, but this is not the true source of the code contained in the drive strength function we removed, the data contained in it, or the PCB ID table that's listed in the comments. The MX51EVK DDR settings in imximage.cfg are not the same as the ones in the old Efika MX file, so these have been ported from Pegatron's old DCD data. The new drive strength settings are sourced from the function and moved back into the DCD. All I did was verify they worked and we were not redundantly setting up the same register twice or pushing defaults information via the DCD to registers (since we only have 60 entries, doing every DDR pad control plus the required PCB ID setup overflows the maximum).
Am 18/08/2012 23:11, schrieb Matt Sealey:
@@ -1,7 +1,7 @@ # +# Copyright (C) 2009 Pegatron Corporation
^---Was this added for mistake ? I think you should add only yours.
The drive strength settings came from Pegatron a long, long time ago (2009 :) and our old config and the function is copyrighted to them. Just because Marek took them out and recopyrighted the file I derived them from in this case doesn't mean they lost their copyright..
Ok, explained - then it is a fixed for a missing copyright.
I join Marek, it is quite difficult to review it and understand which was changed. It looks like a new file..
It's just because I moved the comments to the end of the line, so it's blocking it up.
Sometimes it's nicer if it's
-this line +that line -this line +that line
.. but that's not how git does it when the change is more than a few characters and multiple lines changed.. I can submit it differently but I can't change the way it's producing the diff.
In principle I have not a problem with it - you are the best tester for the DCD table, and you report it is well tested for your board. It is customized for your board and it is not common i.MX code - I can't only make a review because it is difficult to read it.
Best regards, Stefano Babic
Change summary:
* Use iomux-mx51.h include to simplify board configuration. * Remove LED toggle function as it had no real users. * Red LED is now on for pre-reloc, Blue LED for "in U-Boot" * Function renames for readability. * Some board identification string changes * Reduce CPU core voltage to 1.1V (per TO3 spec) * Implicitly remove support for TO2 boards
Signed-off-by: Matt Sealey matt@genesi-usa.com --- board/genesi/mx51_efikamx/efikamx.c | 611 +++++++++++++---------------------- 1 file changed, 230 insertions(+), 381 deletions(-)
diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c index 12371c9..16e877f 100644 --- a/board/genesi/mx51_efikamx/efikamx.c +++ b/board/genesi/mx51_efikamx/efikamx.c @@ -1,7 +1,7 @@ /* + * Copyright (C) 2009 Freescale Semiconductor, Inc. * Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. + * Copyright (C) 2009-2012 Genesi USA, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -24,9 +24,7 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/mx5x_pins.h> -#include <asm/arch/iomux.h> +#include <asm/arch/iomux-mx51.h> #include <asm/gpio.h> #include <asm/errno.h> #include <asm/arch/sys_proto.h> @@ -48,16 +46,12 @@ DECLARE_GLOBAL_DATA_PTR; #endif
/* - * Shared variables / local defines + * Board revisions + * + * Note that we get these revisions here for convenience, but we only set + * up for the production model Smarttop (1.3) and Smartbook (2.0). + * */ -/* LED */ -#define EFIKAMX_LED_BLUE 0x1 -#define EFIKAMX_LED_GREEN 0x2 -#define EFIKAMX_LED_RED 0x4 - -void efikamx_toggle_led(uint32_t mask); - -/* Board revisions */ #define EFIKAMX_BOARD_REV_11 0x1 #define EFIKAMX_BOARD_REV_12 0x2 #define EFIKAMX_BOARD_REV_13 0x3 @@ -69,66 +63,67 @@ void efikamx_toggle_led(uint32_t mask); /* * Board identification */ -u32 get_efikamx_rev(void) +static u32 get_mx_rev(void) { u32 rev = 0; /* * Retrieve board ID: - * rev1.1: 1,1,1 - * rev1.2: 1,1,0 - * rev1.3: 1,0,1 - * rev1.4: 1,0,0 + * + * gpio: 16 17 11 + * ============== + * r1.1: 1+ 1 1 + * r1.2: 1 1 0 + * r1.3: 1 0 1 + * r1.4: 1 0 0 + * + * + note: r1.1 does not strap this pin properly so it needs to + * be hacked or ignored. */ - mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO); - /* set to 1 in order to get correct value on board rev1.1 */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1); + + /* set to 1 in order to get correct value on board rev 1.1 */ + gpio_direction_output(GPIO_NUMBER(3, 16), 1); + gpio_direction_input(GPIO_NUMBER(3, 11)); + gpio_direction_input(GPIO_NUMBER(3, 16)); + gpio_direction_input(GPIO_NUMBER(3, 17));
- mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0; - - mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1; - - mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2; + rev |= (!!gpio_get_value(GPIO_NUMBER(3, 16))) << 0; + rev |= (!!gpio_get_value(GPIO_NUMBER(3, 17))) << 1; + rev |= (!!gpio_get_value(GPIO_NUMBER(3, 11))) << 2;
return (~rev & 0x7) + 1; }
-inline u32 get_efikasb_rev(void) +static iomux_v3_cfg_t efikasb_revision_pads[] = { + MX51_PAD_EIM_CS3__GPIO2_28, + MX51_PAD_EIM_CS4__GPIO2_29, +}; + +static inline u32 get_sb_rev(void) { u32 rev = 0;
- mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_EIM_CS3, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3))) << 0; - - mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_EIM_CS4, PAD_CTL_100K_PU); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4)); - rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4))) << 1; + imx_iomux_v3_setup_multiple_pads(efikasb_revision_pads, ARRAY_SIZE(efikasb_revision_pads)); + gpio_direction_input(GPIO_NUMBER(2, 28)); + gpio_direction_input(GPIO_NUMBER(2, 29)); + + rev |= (!!gpio_get_value(GPIO_NUMBER(2, 28))) << 0; + rev |= (!!gpio_get_value(GPIO_NUMBER(2, 29))) << 1;
return rev; }
-inline uint32_t get_efika_rev(void) +inline uint32_t get_efikamx_rev(void) { - if (machine_is_efikamx()) - return get_efikamx_rev(); - else - return get_efikasb_rev(); + if (machine_is_efikamx()) { + return get_mx_rev(); + } else if (machine_is_efikasb()) { + return get_sb_rev(); + } }
u32 get_board_rev(void) { - return get_cpu_rev() | (get_efika_rev() << 8); + return get_cpu_rev() | (get_efikamx_rev() << 8); }
/* @@ -137,66 +132,35 @@ u32 get_board_rev(void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */ - gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, - PHYS_SDRAM_1_SIZE); + gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0; }
/* * UART configuration */ -static void setup_iomux_uart(void) -{ - unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE | - PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH; - - mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad); - mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad); -} +static iomux_v3_cfg_t efikamx_uart_pads[] = { + MX51_PAD_UART1_RXD__UART1_RXD, + MX51_PAD_UART1_TXD__UART1_TXD, + MX51_PAD_UART1_RTS__UART1_RTS, + MX51_PAD_UART1_CTS__UART1_CTS, +};
/* * SPI configuration */ -#ifdef CONFIG_MXC_SPI -static void setup_iomux_spi(void) -{ - /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */ - mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - - /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); - - /* Configure SS0 as a GPIO */ - mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0); - - /* Configure SS1 as a GPIO */ - mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1); - - /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY, - PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE); - - /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */ - mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK, - PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST); -} -#else -static inline void setup_iomux_spi(void) { } -#endif +static iomux_v3_cfg_t efikamx_spi_pads[]= { + MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI, + MX51_PAD_CSPI1_MISO__ECSPI1_MISO, + MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK, + MX51_PAD_CSPI1_SS0__GPIO4_24, + MX51_PAD_CSPI1_SS1__GPIO4_25, + MX51_PAD_GPIO1_6__GPIO1_6, +}; + +#define EFIKAMX_SPI_SS0 GPIO_NUMBER(4, 24) +#define EFIKAMX_SPI_SS1 GPIO_NUMBER(4, 25) +#define EFIKAMX_PMIC_IRQ GPIO_NUMBER(1, 6)
/* * PMIC configuration @@ -226,7 +190,7 @@ static void power_init(void)
/* Set core voltage to 1.1V */ pmic_reg_read(p, REG_SW_0, &val); - val = (val & ~SWx_VOLT_MASK) | SWx_1_200V; + val = (val & ~SWx_VOLT_MASK) | SWx_1_100V; pmic_reg_write(p, REG_SW_0, val);
/* Setup VCC (SW2) to 1.25 */ @@ -301,29 +265,64 @@ static inline void power_init(void) { } * MMC configuration */ #ifdef CONFIG_FSL_ESDHC + struct fsl_esdhc_cfg esdhc_cfg[2] = { {MMC_SDHC1_BASE_ADDR, 1}, {MMC_SDHC2_BASE_ADDR, 1}, };
-static inline uint32_t efika_mmc_cd(void) +static iomux_v3_cfg_t efikamx_sdhc1_pads[] = { + MX51_PAD_SD1_CMD__SD1_CMD, + MX51_PAD_SD1_CLK__SD1_CLK, + MX51_PAD_SD1_DATA0__SD1_DATA0, + MX51_PAD_SD1_DATA1__SD1_DATA1, + MX51_PAD_SD1_DATA2__SD1_DATA2, + MX51_PAD_SD1_DATA3__SD1_DATA3, + MX51_PAD_GPIO1_1__SD1_WP, +}; + +#define EFIKAMX_SDHC1_WP GPIO_NUMBER(1,1) + +static iomux_v3_cfg_t efikamx_sdhc1_cd_pads[] = { + MX51_PAD_GPIO1_0__SD1_CD, + MX51_PAD_EIM_CS2__SD1_CD, +}; + +#define EFIKAMX_SDHC1_CD GPIO_NUMBER(1,0) +#define EFIKASB_SDHC1_CD GPIO_NUMBER(2,27) + +static iomux_v3_cfg_t efikasb_sdhc2_pads[] = { + MX51_PAD_SD2_CMD__SD2_CMD, + MX51_PAD_SD2_CLK__SD2_CLK, + MX51_PAD_SD2_DATA0__SD2_DATA0, + MX51_PAD_SD2_DATA1__SD2_DATA1, + MX51_PAD_SD2_DATA2__SD2_DATA2, + MX51_PAD_SD2_DATA3__SD2_DATA3, + MX51_PAD_GPIO1_7__SD2_WP, + MX51_PAD_GPIO1_8__SD2_CD, +}; + +#define EFIKASB_SDHC2_CD GPIO_NUMBER(1,8) +#define EFIKASB_SDHC2_WP GPIO_NUMBER(1,7) + +static inline uint32_t efikamx_mmc_getcd(u32 base) { - if (machine_is_efikamx()) - return MX51_PIN_GPIO1_0; - else - return MX51_PIN_EIM_CS2; + if (base == MMC_SDHC1_BASE_ADDR) { + if (machine_is_efikamx()) { + return EFIKAMX_SDHC1_CD; + } else { + return EFIKASB_SDHC1_CD; + } + } else { + return EFIKASB_SDHC2_CD; + } }
int board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; - uint32_t cd = efika_mmc_cd(); - int ret; - - if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR) - ret = !gpio_get_value(IOMUX_TO_GPIO(cd)); - else - ret = !gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8)); + uint32_t cd = efikamx_mmc_getcd(cfg->esdhc_base); + int ret = !gpio_get_value(cd);
return ret; } @@ -331,214 +330,73 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { int ret; - uint32_t cd = efika_mmc_cd(); - - /* SDHC1 is used on all revisions, setup control pins first */ - mxc_request_iomux(cd, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(cd, - PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | - PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | - PAD_CTL_ODE_OPENDRAIN_NONE | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_GPIO1_1, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_1, - PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | - PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | - PAD_CTL_SRE_FAST); - - gpio_direction_input(IOMUX_TO_GPIO(cd)); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1)); - - /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */ - if (machine_is_efikasb() || (machine_is_efikamx() && - (get_efika_rev() < EFIKAMX_BOARD_REV_12))) { - /* SDHC1 IOMUX */ - mxc_request_iomux(MX51_PIN_SD1_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CMD, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_CLK, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CLK, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, - PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE | - PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST); - - /* SDHC2 IOMUX */ - mxc_request_iomux(MX51_PIN_SD2_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD2_CMD, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_CLK, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD2_CLK, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA0, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA1, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA2, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD2_DATA3, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - /* SDHC2 Control lines IOMUX */ - mxc_request_iomux(MX51_PIN_GPIO1_7, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_7, - PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | - PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU | - PAD_CTL_ODE_OPENDRAIN_NONE | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - mxc_request_iomux(MX51_PIN_GPIO1_8, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_GPIO1_8, - PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE | - PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE | - PAD_CTL_SRE_FAST); - - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8)); - gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7)); - - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); - if (!ret) - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]); - } else { /* New boards use only SDHC1 */ - /* SDHC1 IOMUX */ - mxc_request_iomux(MX51_PIN_SD1_CMD, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CMD, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_CLK, - IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION); - mxc_iomux_set_pad(MX51_PIN_SD1_CLK, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA0, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA1, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA2, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_SD1_DATA3, - PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST); - - ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); + + /* + * All Efika MX boards use eSDHC1 with a common write-protect GPIO + */ + imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads, ARRAY_SIZE(efikamx_sdhc1_pads)); + gpio_direction_input(EFIKAMX_SDHC1_WP); + + /* + * Smartbook and Smarttop differ on the location of eSDHC1 carrier-detect GPIO + */ + if (machine_is_efikamx()) { + imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]); + gpio_direction_input(EFIKAMX_SDHC1_CD); + } else if (machine_is_efikasb()) { + imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]); + gpio_direction_input(EFIKASB_SDHC1_CD); } + + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]); + + if (machine_is_efikasb()) {
+ imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads, ARRAY_SIZE(efikasb_sdhc2_pads)); + gpio_direction_input(EFIKASB_SDHC2_CD); + gpio_direction_input(EFIKASB_SDHC2_WP); + if (!ret) + ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]); + } + return ret; } #endif
/* - * ATA + * PATA */ -#ifdef CONFIG_MX51_PATA -#define ATA_PAD_CONFIG (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH) -void setup_iomux_ata(void) -{ - mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D0, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D1, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D2, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D3, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D4, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D5, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D6, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D7, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D8, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D9, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D10, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D11, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D12, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D13, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D14, ATA_PAD_CONFIG); - mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_NANDF_D15, ATA_PAD_CONFIG); -} -#else -static inline void setup_iomux_ata(void) { } -#endif +static iomux_v3_cfg_t efikamx_pata_pads[] = { + MX51_PAD_NANDF_WE_B__PATA_DIOW, + MX51_PAD_NANDF_RE_B__PATA_DIOR, + MX51_PAD_NANDF_ALE__PATA_BUFFER_EN, + MX51_PAD_NANDF_CLE__PATA_RESET_B, + MX51_PAD_NANDF_WP_B__PATA_DMACK, + MX51_PAD_NANDF_RB0__PATA_DMARQ, + MX51_PAD_NANDF_RB1__PATA_IORDY, + MX51_PAD_GPIO_NAND__PATA_INTRQ, + MX51_PAD_NANDF_CS2__PATA_CS_0, + MX51_PAD_NANDF_CS3__PATA_CS_1, + MX51_PAD_NANDF_CS4__PATA_DA_0, + MX51_PAD_NANDF_CS5__PATA_DA_1, + MX51_PAD_NANDF_CS6__PATA_DA_2, + MX51_PAD_NANDF_D15__PATA_DATA15, + MX51_PAD_NANDF_D14__PATA_DATA14, + MX51_PAD_NANDF_D13__PATA_DATA13, + MX51_PAD_NANDF_D12__PATA_DATA12, + MX51_PAD_NANDF_D11__PATA_DATA11, + MX51_PAD_NANDF_D10__PATA_DATA10, + MX51_PAD_NANDF_D9__PATA_DATA9, + MX51_PAD_NANDF_D8__PATA_DATA8, + MX51_PAD_NANDF_D7__PATA_DATA7, + MX51_PAD_NANDF_D6__PATA_DATA6, + MX51_PAD_NANDF_D5__PATA_DATA5, + MX51_PAD_NANDF_D4__PATA_DATA4, + MX51_PAD_NANDF_D3__PATA_DATA3, + MX51_PAD_NANDF_D2__PATA_DATA2, + MX51_PAD_NANDF_D1__PATA_DATA1, + MX51_PAD_NANDF_D0__PATA_DATA0, +};
/* * EHCI USB @@ -551,57 +409,55 @@ static inline void setup_iomux_usb(void) { }
/* * LED configuration + * + * Smarttop LED pad config is done in the DCD + * */ -void setup_iomux_led(void) -{ - if (machine_is_efikamx()) { - /* Blue LED */ - mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0); - - /* Green LED */ - mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), 0); +#define EFIKAMX_LED_BLUE GPIO_NUMBER(3, 13) +#define EFIKAMX_LED_GREEN GPIO_NUMBER(3, 14) +#define EFIKAMX_LED_RED GPIO_NUMBER(3, 15)
- /* Red LED */ - mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), 0); - } else { - /* CAPS-LOCK LED */ - mxc_request_iomux(MX51_PIN_EIM_CS0, IOMUX_CONFIG_GPIO); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0), 0); - - /* ALARM-LED LED */ - mxc_request_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_GPIO); - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), 0); - } -} +static iomux_v3_cfg_t efikasb_led_pads[] = { + MX51_PAD_GPIO1_3__GPIO1_3, + MX51_PAD_EIM_CS0__GPIO2_25, +};
-void efikamx_toggle_led(uint32_t mask) -{ - if (machine_is_efikamx()) { - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), - mask & EFIKAMX_LED_BLUE); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), - mask & EFIKAMX_LED_GREEN); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), - mask & EFIKAMX_LED_RED); - } else { - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0), - mask & EFIKAMX_LED_BLUE); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), - !(mask & EFIKAMX_LED_GREEN)); - } -} +#define EFIKASB_CAPSLOCK_LED GPIO_NUMBER(2, 25) +#define EFIKASB_MESSAGE_LED GPIO_NUMBER(1, 3) /* Note: active low */
/* * Board initialization */ int board_early_init_f(void) { - setup_iomux_uart(); - setup_iomux_spi(); - setup_iomux_led(); + if (machine_is_efikasb()) { + imx_iomux_v3_setup_multiple_pads(efikasb_led_pads, ARRAY_SIZE(efikasb_led_pads)); + gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0); + gpio_direction_output(EFIKASB_MESSAGE_LED, 1); + } else if (machine_is_efikamx()) { + /* + * Set up GPIO directions for LEDs. + * IOMUX has been done in the DCD already. + * Turn the red LED on for pre-relocation code. + */ + gpio_direction_output(EFIKAMX_LED_BLUE, 0); + gpio_direction_output(EFIKAMX_LED_GREEN, 0); + gpio_direction_output(EFIKAMX_LED_RED, 1); + } + + /* + * Both these pad configurations for UART and SPI are kind of redundant + * since they are the Power-On Defaults for the i.MX51. But, it seems we + * should make absolutely sure that they are set up correctly. + */ + imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads, ARRAY_SIZE(efikamx_uart_pads)); + imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads, ARRAY_SIZE(efikamx_spi_pads)); + + /* not technically required for U-Boot operation but set it up anyway. */ + gpio_direction_input(EFIKAMX_PMIC_IRQ); + /* Deselect both CS for now.. any other way and NOR doesn't probe properly. */ + gpio_direction_output(EFIKAMX_SPI_SS0, 0); + gpio_direction_output(EFIKAMX_SPI_SS1, 1);
return 0; } @@ -609,49 +465,42 @@ int board_early_init_f(void) int board_init(void) { gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100; - + return 0; }
int board_late_init(void) { - setup_iomux_spi(); - + if (machine_is_efikamx()) { + /* + * Set up Blue LED for "In U-Boot" status. + * We're all relocated and ready to U-Boot! + */ + gpio_set_value(EFIKAMX_LED_RED, 0); + gpio_set_value(EFIKAMX_LED_GREEN, 0); + gpio_set_value(EFIKAMX_LED_BLUE, 1); + } + power_init();
- setup_iomux_led(); - setup_iomux_ata(); + imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads, ARRAY_SIZE(efikamx_pata_pads)); setup_iomux_usb();
if (machine_is_efikasb()) setenv("preboot", "usb reset ; setenv stdin usbkbd\0");
- setup_iomux_led(); - - efikamx_toggle_led(EFIKAMX_LED_BLUE); - return 0; }
int checkboard(void) { - u32 rev = get_efika_rev(); + u32 rev = get_efikamx_rev();
+ printf("Board: Genesi Efika MX "); if (machine_is_efikamx()) { - printf("Board: Efika MX, rev1.%i\n", rev & 0xf); - return 0; - } else { - switch (rev) { - case EFIKASB_BOARD_REV_13: - printf("Board: Efika SB rev1.3\n"); - break; - case EFIKASB_BOARD_REV_20: - printf("Board: Efika SB rev2.0\n"); - break; - default: - printf("Board: Efika SB, rev Unknown\n"); - break; - } + printf("Smarttop (1.%i)\n", rev & 0xf); + } else if (machine_is_efikasb()) { + printf("Smartbook\n"); }
return 0;
Dear Matt Sealey,
Benoît Thébaudeau Application Engineer benoit.thebaudeau@advansee.com +33 2 40 50 21 73 ADVANSEE SARL 9, rue Alfred Kastler CS 30750 44307 Nantes CEDEX 3 France
----- Original Message -----
From: "Matt Sealey" matt@genesi-usa.com To: "U-Boot ML" u-boot@lists.denx.de Cc: "Steev Klimaszewski" steev@genesi-usa.com Sent: Friday, August 17, 2012 8:19:21 PM Subject: [U-Boot] [PATCH 3/4] efikamx: update to Efika MX Smarttop and Smartbook boards
Change summary:
- Use iomux-mx51.h include to simplify board configuration.
- Remove LED toggle function as it had no real users.
- Red LED is now on for pre-reloc, Blue LED for "in U-Boot"
- Function renames for readability.
- Some board identification string changes
- Reduce CPU core voltage to 1.1V (per TO3 spec)
- Implicitly remove support for TO2 boards
These are many unrelated changes that could be split.
Signed-off-by: Matt Sealey matt@genesi-usa.com
board/genesi/mx51_efikamx/efikamx.c | 611 +++++++++++++---------------------- 1 file changed, 230 insertions(+), 381 deletions(-)
diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c index 12371c9..16e877f 100644 --- a/board/genesi/mx51_efikamx/efikamx.c +++ b/board/genesi/mx51_efikamx/efikamx.c @@ -1,7 +1,7 @@ /*
- Copyright (C) 2009 Freescale Semiconductor, Inc.
- Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com
- (C) Copyright 2009 Freescale Semiconductor, Inc.
- Copyright (C) 2009-2012 Genesi USA, Inc.
- See file CREDITS for list of people who contributed to this
- project.
@@ -24,9 +24,7 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/mx5x_pins.h> -#include <asm/arch/iomux.h> +#include <asm/arch/iomux-mx51.h> #include <asm/gpio.h> #include <asm/errno.h> #include <asm/arch/sys_proto.h> @@ -48,16 +46,12 @@ DECLARE_GLOBAL_DATA_PTR; #endif
/*
- Shared variables / local defines
- Board revisions
- Note that we get these revisions here for convenience, but we
only set
- up for the production model Smarttop (1.3) and Smartbook (2.0).
*/
-/* LED */ -#define EFIKAMX_LED_BLUE 0x1 -#define EFIKAMX_LED_GREEN 0x2 -#define EFIKAMX_LED_RED 0x4
-void efikamx_toggle_led(uint32_t mask);
-/* Board revisions */ #define EFIKAMX_BOARD_REV_11 0x1 #define EFIKAMX_BOARD_REV_12 0x2 #define EFIKAMX_BOARD_REV_13 0x3 @@ -69,66 +63,67 @@ void efikamx_toggle_led(uint32_t mask); /*
- Board identification
*/ -u32 get_efikamx_rev(void) +static u32 get_mx_rev(void) { u32 rev = 0; /* * Retrieve board ID:
* rev1.1: 1,1,1* rev1.2: 1,1,0* rev1.3: 1,0,1* rev1.4: 1,0,0
** gpio: 16 17 11* ==============* r1.1: 1+ 1 1* r1.2: 1 1 0* r1.3: 1 0 1* r1.4: 1 0 0** + note: r1.1 does not strap this pin properly so it needs to* be hacked or ignored.
- mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
- /* set to 1 in order to get correct value on board rev1.1 */
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1);
- /* set to 1 in order to get correct value on board rev 1.1 */
- gpio_direction_output(GPIO_NUMBER(3, 16), 1);
- gpio_direction_input(GPIO_NUMBER(3, 11));
- gpio_direction_input(GPIO_NUMBER(3, 16));
- gpio_direction_input(GPIO_NUMBER(3, 17));
- mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU);
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0));
- rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0;
- mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU);
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1));
- rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1;
- mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU);
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3));
- rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2;
rev |= (!!gpio_get_value(GPIO_NUMBER(3, 16))) << 0;
rev |= (!!gpio_get_value(GPIO_NUMBER(3, 17))) << 1;
rev |= (!!gpio_get_value(GPIO_NUMBER(3, 11))) << 2;
return (~rev & 0x7) + 1;
}
-inline u32 get_efikasb_rev(void) +static iomux_v3_cfg_t efikasb_revision_pads[] = {
- MX51_PAD_EIM_CS3__GPIO2_28,
- MX51_PAD_EIM_CS4__GPIO2_29,
+};
+static inline u32 get_sb_rev(void) { u32 rev = 0;
- mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_EIM_CS3, PAD_CTL_100K_PU);
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3));
- rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3))) << 0;
- mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_EIM_CS4, PAD_CTL_100K_PU);
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4));
- rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4))) << 1;
- imx_iomux_v3_setup_multiple_pads(efikasb_revision_pads,
ARRAY_SIZE(efikasb_revision_pads));
gpio_direction_input(GPIO_NUMBER(2, 28));
gpio_direction_input(GPIO_NUMBER(2, 29));
rev |= (!!gpio_get_value(GPIO_NUMBER(2, 28))) << 0;
rev |= (!!gpio_get_value(GPIO_NUMBER(2, 29))) << 1;
return rev;
}
-inline uint32_t get_efika_rev(void) +inline uint32_t get_efikamx_rev(void) {
- if (machine_is_efikamx())
return get_efikamx_rev();- else
return get_efikasb_rev();
- if (machine_is_efikamx()) {
return get_mx_rev();- } else if (machine_is_efikasb()) {
return get_sb_rev();- }
}
u32 get_board_rev(void) {
- return get_cpu_rev() | (get_efika_rev() << 8);
- return get_cpu_rev() | (get_efikamx_rev() << 8);
}
/* @@ -137,66 +132,35 @@ u32 get_board_rev(void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE); return 0; }
/*
- UART configuration
*/ -static void setup_iomux_uart(void) -{
- unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;- mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
- mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
-} +static iomux_v3_cfg_t efikamx_uart_pads[] = {
- MX51_PAD_UART1_RXD__UART1_RXD,
- MX51_PAD_UART1_TXD__UART1_TXD,
- MX51_PAD_UART1_RTS__UART1_RTS,
- MX51_PAD_UART1_CTS__UART1_CTS,
+};
/*
- SPI configuration
*/ -#ifdef CONFIG_MXC_SPI -static void setup_iomux_spi(void) -{
- /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
- mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);- /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1.
*/
- mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);- /* Configure SS0 as a GPIO */
- mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO);
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0);
- /* Configure SS1 as a GPIO */
- mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO);
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1);
- /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);- /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1.
*/
- mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);-} -#else -static inline void setup_iomux_spi(void) { } -#endif +static iomux_v3_cfg_t efikamx_spi_pads[]= {
- MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
- MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
- MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
- MX51_PAD_CSPI1_SS0__GPIO4_24,
- MX51_PAD_CSPI1_SS1__GPIO4_25,
- MX51_PAD_GPIO1_6__GPIO1_6,
+};
Why don't you merge all these pad settings to a single board pad array, with a single call to imx_iomux_v3_setup_multiple_pads()?
+#define EFIKAMX_SPI_SS0 GPIO_NUMBER(4, 24) +#define EFIKAMX_SPI_SS1 GPIO_NUMBER(4, 25) +#define EFIKAMX_PMIC_IRQ GPIO_NUMBER(1, 6)
/*
- PMIC configuration
@@ -226,7 +190,7 @@ static void power_init(void)
/* Set core voltage to 1.1V */ pmic_reg_read(p, REG_SW_0, &val);
- val = (val & ~SWx_VOLT_MASK) | SWx_1_200V;
val = (val & ~SWx_VOLT_MASK) | SWx_1_100V; pmic_reg_write(p, REG_SW_0, val);
/* Setup VCC (SW2) to 1.25 */
@@ -301,29 +265,64 @@ static inline void power_init(void) { }
- MMC configuration
*/ #ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = { {MMC_SDHC1_BASE_ADDR, 1}, {MMC_SDHC2_BASE_ADDR, 1}, };
-static inline uint32_t efika_mmc_cd(void) +static iomux_v3_cfg_t efikamx_sdhc1_pads[] = {
- MX51_PAD_SD1_CMD__SD1_CMD,
- MX51_PAD_SD1_CLK__SD1_CLK,
- MX51_PAD_SD1_DATA0__SD1_DATA0,
- MX51_PAD_SD1_DATA1__SD1_DATA1,
- MX51_PAD_SD1_DATA2__SD1_DATA2,
- MX51_PAD_SD1_DATA3__SD1_DATA3,
- MX51_PAD_GPIO1_1__SD1_WP,
+};
+#define EFIKAMX_SDHC1_WP GPIO_NUMBER(1,1)
+static iomux_v3_cfg_t efikamx_sdhc1_cd_pads[] = {
- MX51_PAD_GPIO1_0__SD1_CD,
- MX51_PAD_EIM_CS2__SD1_CD,
+};
+#define EFIKAMX_SDHC1_CD GPIO_NUMBER(1,0) +#define EFIKASB_SDHC1_CD GPIO_NUMBER(2,27)
+static iomux_v3_cfg_t efikasb_sdhc2_pads[] = {
- MX51_PAD_SD2_CMD__SD2_CMD,
- MX51_PAD_SD2_CLK__SD2_CLK,
- MX51_PAD_SD2_DATA0__SD2_DATA0,
- MX51_PAD_SD2_DATA1__SD2_DATA1,
- MX51_PAD_SD2_DATA2__SD2_DATA2,
- MX51_PAD_SD2_DATA3__SD2_DATA3,
- MX51_PAD_GPIO1_7__SD2_WP,
- MX51_PAD_GPIO1_8__SD2_CD,
+};
+#define EFIKASB_SDHC2_CD GPIO_NUMBER(1,8) +#define EFIKASB_SDHC2_WP GPIO_NUMBER(1,7)
+static inline uint32_t efikamx_mmc_getcd(u32 base) {
- if (machine_is_efikamx())
return MX51_PIN_GPIO1_0;- else
return MX51_PIN_EIM_CS2;
- if (base == MMC_SDHC1_BASE_ADDR) {
if (machine_is_efikamx()) {return EFIKAMX_SDHC1_CD;} else {return EFIKASB_SDHC1_CD;}- } else {
return EFIKASB_SDHC2_CD;- }
}
int board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- uint32_t cd = efika_mmc_cd();
- int ret;
- if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
ret = !gpio_get_value(IOMUX_TO_GPIO(cd));- else
ret = !gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
uint32_t cd = efikamx_mmc_getcd(cfg->esdhc_base);
int ret = !gpio_get_value(cd);
return ret;
} @@ -331,214 +330,73 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { int ret;
- uint32_t cd = efika_mmc_cd();
- /* SDHC1 is used on all revisions, setup control pins first */
- mxc_request_iomux(cd,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);- mxc_iomux_set_pad(cd,
PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |PAD_CTL_ODE_OPENDRAIN_NONE |PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);- mxc_request_iomux(MX51_PIN_GPIO1_1,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);- mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |PAD_CTL_SRE_FAST);- gpio_direction_input(IOMUX_TO_GPIO(cd));
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1));
- /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */
- if (machine_is_efikasb() || (machine_is_efikamx() &&
(get_efika_rev() < EFIKAMX_BOARD_REV_12))) {/* SDHC1 IOMUX */mxc_request_iomux(MX51_PIN_SD1_CMD,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_SD1_CMD,PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_CLK,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_SD1_CLK,PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);/* SDHC2 IOMUX */mxc_request_iomux(MX51_PIN_SD2_CMD,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_SD2_CMD,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD2_CLK,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_SD2_CLK,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);/* SDHC2 Control lines IOMUX */mxc_request_iomux(MX51_PIN_GPIO1_7,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_GPIO1_7,PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |PAD_CTL_ODE_OPENDRAIN_NONE |PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_GPIO1_8,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_GPIO1_8,PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |PAD_CTL_SRE_FAST);gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7));ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);if (!ret)ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);- } else { /* New boards use only SDHC1 */
/* SDHC1 IOMUX */mxc_request_iomux(MX51_PIN_SD1_CMD,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_SD1_CMD,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_CLK,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_SD1_CLK,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
- /*
* All Efika MX boards use eSDHC1 with a common write-protect GPIO*/- imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads,
ARRAY_SIZE(efikamx_sdhc1_pads));
- gpio_direction_input(EFIKAMX_SDHC1_WP);
- /*
* Smartbook and Smarttop differ on the location of eSDHC1carrier-detect GPIO
*/if (machine_is_efikamx()) {
imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]);gpio_direction_input(EFIKAMX_SDHC1_CD);} else if (machine_is_efikasb()) {
imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]);gpio_direction_input(EFIKASB_SDHC1_CD);}
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
if (machine_is_efikasb()) {
imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads,ARRAY_SIZE(efikasb_sdhc2_pads));
gpio_direction_input(EFIKASB_SDHC2_CD);gpio_direction_input(EFIKASB_SDHC2_WP);if (!ret)ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);- }
- return ret;
} #endif
/*
- ATA
*/
- PATA
-#ifdef CONFIG_MX51_PATA -#define ATA_PAD_CONFIG (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH) -void setup_iomux_ata(void) -{
- mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D0, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D1, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D2, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D3, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D4, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D5, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D6, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D7, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D8, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D9, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D10, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D11, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D12, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D13, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D14, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D15, ATA_PAD_CONFIG);
-} -#else -static inline void setup_iomux_ata(void) { } -#endif +static iomux_v3_cfg_t efikamx_pata_pads[] = {
- MX51_PAD_NANDF_WE_B__PATA_DIOW,
- MX51_PAD_NANDF_RE_B__PATA_DIOR,
- MX51_PAD_NANDF_ALE__PATA_BUFFER_EN,
- MX51_PAD_NANDF_CLE__PATA_RESET_B,
- MX51_PAD_NANDF_WP_B__PATA_DMACK,
- MX51_PAD_NANDF_RB0__PATA_DMARQ,
- MX51_PAD_NANDF_RB1__PATA_IORDY,
- MX51_PAD_GPIO_NAND__PATA_INTRQ,
- MX51_PAD_NANDF_CS2__PATA_CS_0,
- MX51_PAD_NANDF_CS3__PATA_CS_1,
- MX51_PAD_NANDF_CS4__PATA_DA_0,
- MX51_PAD_NANDF_CS5__PATA_DA_1,
- MX51_PAD_NANDF_CS6__PATA_DA_2,
- MX51_PAD_NANDF_D15__PATA_DATA15,
- MX51_PAD_NANDF_D14__PATA_DATA14,
- MX51_PAD_NANDF_D13__PATA_DATA13,
- MX51_PAD_NANDF_D12__PATA_DATA12,
- MX51_PAD_NANDF_D11__PATA_DATA11,
- MX51_PAD_NANDF_D10__PATA_DATA10,
- MX51_PAD_NANDF_D9__PATA_DATA9,
- MX51_PAD_NANDF_D8__PATA_DATA8,
- MX51_PAD_NANDF_D7__PATA_DATA7,
- MX51_PAD_NANDF_D6__PATA_DATA6,
- MX51_PAD_NANDF_D5__PATA_DATA5,
- MX51_PAD_NANDF_D4__PATA_DATA4,
- MX51_PAD_NANDF_D3__PATA_DATA3,
- MX51_PAD_NANDF_D2__PATA_DATA2,
- MX51_PAD_NANDF_D1__PATA_DATA1,
- MX51_PAD_NANDF_D0__PATA_DATA0,
+};
/*
- EHCI USB
@@ -551,57 +409,55 @@ static inline void setup_iomux_usb(void) { }
/*
- LED configuration
- Smarttop LED pad config is done in the DCD
*/
-void setup_iomux_led(void) -{
- if (machine_is_efikamx()) {
/* Blue LED */mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3);gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0);/* Green LED */mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3);gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), 0);+#define EFIKAMX_LED_BLUE GPIO_NUMBER(3, 13) +#define EFIKAMX_LED_GREEN GPIO_NUMBER(3, 14) +#define EFIKAMX_LED_RED GPIO_NUMBER(3, 15)
/* Red LED */mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3);gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), 0);- } else {
/* CAPS-LOCK LED */mxc_request_iomux(MX51_PIN_EIM_CS0, IOMUX_CONFIG_GPIO);gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0), 0);/* ALARM-LED LED */mxc_request_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_GPIO);gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), 0);- }
-} +static iomux_v3_cfg_t efikasb_led_pads[] = {
- MX51_PAD_GPIO1_3__GPIO1_3,
- MX51_PAD_EIM_CS0__GPIO2_25,
+};
-void efikamx_toggle_led(uint32_t mask) -{
- if (machine_is_efikamx()) {
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9),mask & EFIKAMX_LED_BLUE);gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC),mask & EFIKAMX_LED_GREEN);gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC),mask & EFIKAMX_LED_RED);- } else {
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0),mask & EFIKAMX_LED_BLUE);gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3),!(mask & EFIKAMX_LED_GREEN));- }
-} +#define EFIKASB_CAPSLOCK_LED GPIO_NUMBER(2, 25) +#define EFIKASB_MESSAGE_LED GPIO_NUMBER(1, 3) /* Note: active low */
/*
- Board initialization
*/ int board_early_init_f(void) {
- setup_iomux_uart();
- setup_iomux_spi();
- setup_iomux_led();
- if (machine_is_efikasb()) {
imx_iomux_v3_setup_multiple_pads(efikasb_led_pads,ARRAY_SIZE(efikasb_led_pads));
gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0);gpio_direction_output(EFIKASB_MESSAGE_LED, 1);- } else if (machine_is_efikamx()) {
/** Set up GPIO directions for LEDs.* IOMUX has been done in the DCD already.* Turn the red LED on for pre-relocation code.*/gpio_direction_output(EFIKAMX_LED_BLUE, 0);gpio_direction_output(EFIKAMX_LED_GREEN, 0);gpio_direction_output(EFIKAMX_LED_RED, 1);- }
- /*
* Both these pad configurations for UART and SPI are kind ofredundant
* since they are the Power-On Defaults for the i.MX51. But, itseems we
* should make absolutely sure that they are set up correctly.*/- imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads,
ARRAY_SIZE(efikamx_uart_pads));
- imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads,
ARRAY_SIZE(efikamx_spi_pads));
- /* not technically required for U-Boot operation but set it up
anyway. */
- gpio_direction_input(EFIKAMX_PMIC_IRQ);
- /* Deselect both CS for now.. any other way and NOR doesn't probe
properly. */
gpio_direction_output(EFIKAMX_SPI_SS0, 0);
gpio_direction_output(EFIKAMX_SPI_SS1, 1);
return 0;
} @@ -609,49 +465,42 @@ int board_early_init_f(void) int board_init(void) { gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
- return 0;
}
int board_late_init(void) {
- setup_iomux_spi();
- if (machine_is_efikamx()) {
/** Set up Blue LED for "In U-Boot" status.* We're all relocated and ready to U-Boot!*/gpio_set_value(EFIKAMX_LED_RED, 0);gpio_set_value(EFIKAMX_LED_GREEN, 0);gpio_set_value(EFIKAMX_LED_BLUE, 1);- }
- power_init();
- setup_iomux_led();
- setup_iomux_ata();
- imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads,
ARRAY_SIZE(efikamx_pata_pads)); setup_iomux_usb();
if (machine_is_efikasb()) setenv("preboot", "usb reset ; setenv stdin usbkbd\0");
- setup_iomux_led();
- efikamx_toggle_led(EFIKAMX_LED_BLUE);
- return 0;
}
int checkboard(void) {
- u32 rev = get_efika_rev();
u32 rev = get_efikamx_rev();
printf("Board: Genesi Efika MX "); if (machine_is_efikamx()) {
printf("Board: Efika MX, rev1.%i\n", rev & 0xf);return 0;- } else {
switch (rev) {case EFIKASB_BOARD_REV_13:printf("Board: Efika SB rev1.3\n");break;case EFIKASB_BOARD_REV_20:printf("Board: Efika SB rev2.0\n");break;default:printf("Board: Efika SB, rev Unknown\n");break;}
printf("Smarttop (1.%i)\n", rev & 0xf);} else if (machine_is_efikasb()) {
printf("Smartbook\n");}
return 0;
Best regards, Benoît
On Fri, Aug 17, 2012 at 2:29 PM, Benoît Thébaudeau benoit.thebaudeau@advansee.com wrote:
Dear Matt Sealey,
- Use iomux-mx51.h include to simplify board configuration.
- Remove LED toggle function as it had no real users.
- Red LED is now on for pre-reloc, Blue LED for "in U-Boot"
- Function renames for readability.
- Some board identification string changes
- Reduce CPU core voltage to 1.1V (per TO3 spec)
- Implicitly remove support for TO2 boards
These are many unrelated changes that could be split.
Could be, but they're not going to be, the reasoning behind it being that it increases work for us to test each individual patch works in any particular order it may be committed to any tree, and increases work for patch maintainers whereby there are too many inter-dependent changes, extra fuzz, rebasing etc. which is just totally needless. In essence this is a cleanup patch intended to get rid of some things that made absolutely no sense but have persisted upstream for the longest time. It also ports to iomux-mx51.h as previously sent since that helps a lot on cleanup.
We tested every single part of this as a unit internally over 10 weeks, what's being sent to the list is the result. What isn't in the patch (or more accurately, what got removed) was code that would make more of a mess for very little functionality, code that was repeated or overcomplicated for no good reason (led setup for example) or was over-abstracted.
What went in to the process was the old code: functionality was tested and verified against expectations. What you get from the new code: almost exactly the same behavior (actually it works a little better as some redundant things were removed).
The sign-off is not just me hitting "-s" on my git command line, it's my explicit assurance that this is highly tested code that I am willing to maintain and answer questions on. Marex has been asking me to submit it for a long, long time and I refused because we were still going through QA; that got finished, to a level I am happy with at least (still a few weird things happening but they existed with the old code too). However, QA got done, and the result is clear, and splitting it up means going through QA again just to respin patches, so I'm going to refuse on that basis alone. If we just consider it a cleanup patch for the board and a reasonable example of the benefits of the new iomux model code, does that make it easier to accept?
Signed-off-by: Matt Sealey matt@genesi-usa.com
[snip]
MX51_PAD_CSPI1_SS1__GPIO4_25,MX51_PAD_GPIO1_6__GPIO1_6,+};
Why don't you merge all these pad settings to a single board pad array, with a single call to imx_iomux_v3_setup_multiple_pads()?
That has been done before (it was the way we did it in our ancient Linux kernels, it was the way Freescale did it in their ancient Linux kernels). We feel a huge board-specific array is hard to maintain and ugly to read, and the few differences would end up in tiny, separate arrays anyway. The U-Boot code was written that way in the first place, it made a lot of sense to keep the status quo for now. My preferred solution would be to split each part into a seperate source file and call them from the board file (as efikamx-usb.c is done now, but for MMC, ATA too) where such code would clean up the main board file significantly, but I think that would be too big a change for a lot of people. We can perform a more egregious cleanup later.
Dear Matt Sealey,
Change summary:
This patch does multiple unrelated changes, please split. You basically outlined how this should be split.
- Use iomux-mx51.h include to simplify board configuration.
- Remove LED toggle function as it had no real users.
- Red LED is now on for pre-reloc, Blue LED for "in U-Boot"
- Function renames for readability.
- Some board identification string changes
- Reduce CPU core voltage to 1.1V (per TO3 spec)
- Implicitly remove support for TO2 boards
There are TO2 baords out there, debian people do have some. Please do not remove this.
Signed-off-by: Matt Sealey matt@genesi-usa.com
[...]
Best regards, Marek Vasut
On Fri, Aug 17, 2012 at 4:07 PM, Marek Vasut marex@denx.de wrote:
Dear Matt Sealey,
Change summary:
This patch does multiple unrelated changes, please split. You basically outlined how this should be split.
- Use iomux-mx51.h include to simplify board configuration.
- Remove LED toggle function as it had no real users.
- Red LED is now on for pre-reloc, Blue LED for "in U-Boot"
- Function renames for readability.
- Some board identification string changes
- Reduce CPU core voltage to 1.1V (per TO3 spec)
- Implicitly remove support for TO2 boards
There are TO2 baords out there, debian people do have some. Please do not remove this.
The code I checked out from git master a week ago doesn't boot for precisely the same reason on TO2 r1.1 or r1.2 boards, so nothing changed here in real life. The TO2 code can't pass QA so it's been removed. Welcome to the wonderful world of commercial software development.
Dear Matt Sealey,
On Fri, Aug 17, 2012 at 4:07 PM, Marek Vasut marex@denx.de wrote:
Dear Matt Sealey,
Change summary:
This patch does multiple unrelated changes, please split. You basically outlined how this should be split.
- Use iomux-mx51.h include to simplify board configuration.
- Remove LED toggle function as it had no real users.
- Red LED is now on for pre-reloc, Blue LED for "in U-Boot"
- Function renames for readability.
- Some board identification string changes
- Reduce CPU core voltage to 1.1V (per TO3 spec)
- Implicitly remove support for TO2 boards
There are TO2 baords out there, debian people do have some. Please do not remove this.
The code I checked out from git master a week ago doesn't boot for precisely the same reason on TO2 r1.1 or r1.2 boards, so nothing changed here in real life. The TO2 code can't pass QA so it's been removed.
CCing Hector so he can supply further details about what debian does.
Welcome to the wonderful world of commercial software development.
Your commercial goo has zero influence on any opensource project and noone gives a splat, welcome to the wonderful world of _freedom_.*
* ok, maybe I'm negatively biased actually, especially due to the way you put it.
Best regards, Marek Vasut
On 17/08/2012 20:19, Matt Sealey wrote:
Change summary:
- Use iomux-mx51.h include to simplify board configuration.
- Remove LED toggle function as it had no real users.
- Red LED is now on for pre-reloc, Blue LED for "in U-Boot"
- Function renames for readability.
- Some board identification string changes
- Reduce CPU core voltage to 1.1V (per TO3 spec)
- Implicitly remove support for TO2 boards
Signed-off-by: Matt Sealey matt@genesi-usa.com
Hi Matt,
board/genesi/mx51_efikamx/efikamx.c | 611 +++++++++++++---------------------- 1 file changed, 230 insertions(+), 381 deletions(-)
diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c index 12371c9..16e877f 100644 --- a/board/genesi/mx51_efikamx/efikamx.c +++ b/board/genesi/mx51_efikamx/efikamx.c @@ -1,7 +1,7 @@ /*
- Copyright (C) 2009 Freescale Semiconductor, Inc.
- Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com
- (C) Copyright 2009 Freescale Semiconductor, Inc.
- Copyright (C) 2009-2012 Genesi USA, Inc.
- See file CREDITS for list of people who contributed to this
- project.
@@ -24,9 +24,7 @@
#include <common.h> #include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/mx5x_pins.h> -#include <asm/arch/iomux.h> +#include <asm/arch/iomux-mx51.h> #include <asm/gpio.h> #include <asm/errno.h> #include <asm/arch/sys_proto.h> @@ -48,16 +46,12 @@ DECLARE_GLOBAL_DATA_PTR; #endif
/*
- Shared variables / local defines
- Board revisions
- Note that we get these revisions here for convenience, but we only set
- up for the production model Smarttop (1.3) and Smartbook (2.0).
*/
-/* LED */ -#define EFIKAMX_LED_BLUE 0x1 -#define EFIKAMX_LED_GREEN 0x2 -#define EFIKAMX_LED_RED 0x4
-void efikamx_toggle_led(uint32_t mask);
-/* Board revisions */ #define EFIKAMX_BOARD_REV_11 0x1 #define EFIKAMX_BOARD_REV_12 0x2 #define EFIKAMX_BOARD_REV_13 0x3 @@ -69,66 +63,67 @@ void efikamx_toggle_led(uint32_t mask); /*
- Board identification
*/ -u32 get_efikamx_rev(void) +static u32 get_mx_rev(void) { u32 rev = 0; /* * Retrieve board ID:
* rev1.1: 1,1,1* rev1.2: 1,1,0* rev1.3: 1,0,1* rev1.4: 1,0,0
** gpio: 16 17 11* ==============* r1.1: 1+ 1 1* r1.2: 1 1 0* r1.3: 1 0 1* r1.4: 1 0 0** + note: r1.1 does not strap this pin properly so it needs to* be hacked or ignored.
- mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
- /* set to 1 in order to get correct value on board rev1.1 */
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0), 1);
- /* set to 1 in order to get correct value on board rev 1.1 */
- gpio_direction_output(GPIO_NUMBER(3, 16), 1);
- gpio_direction_input(GPIO_NUMBER(3, 11));
- gpio_direction_input(GPIO_NUMBER(3, 16));
- gpio_direction_input(GPIO_NUMBER(3, 17));
- mxc_request_iomux(MX51_PIN_NANDF_CS0, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS0, PAD_CTL_100K_PU);
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0));
- rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS0))) << 0;
- mxc_request_iomux(MX51_PIN_NANDF_CS1, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS1, PAD_CTL_100K_PU);
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1));
- rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_CS1))) << 1;
- mxc_request_iomux(MX51_PIN_NANDF_RB3, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RB3, PAD_CTL_100K_PU);
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3));
- rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_NANDF_RB3))) << 2;
rev |= (!!gpio_get_value(GPIO_NUMBER(3, 16))) << 0;
rev |= (!!gpio_get_value(GPIO_NUMBER(3, 17))) << 1;
rev |= (!!gpio_get_value(GPIO_NUMBER(3, 11))) << 2;
return (~rev & 0x7) + 1;
}
-inline u32 get_efikasb_rev(void) +static iomux_v3_cfg_t efikasb_revision_pads[] = {
- MX51_PAD_EIM_CS3__GPIO2_28,
- MX51_PAD_EIM_CS4__GPIO2_29,
+};
+static inline u32 get_sb_rev(void) { u32 rev = 0;
- mxc_request_iomux(MX51_PIN_EIM_CS3, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_EIM_CS3, PAD_CTL_100K_PU);
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3));
- rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS3))) << 0;
- mxc_request_iomux(MX51_PIN_EIM_CS4, IOMUX_CONFIG_GPIO);
- mxc_iomux_set_pad(MX51_PIN_EIM_CS4, PAD_CTL_100K_PU);
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4));
- rev |= (!!gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS4))) << 1;
imx_iomux_v3_setup_multiple_pads(efikasb_revision_pads, ARRAY_SIZE(efikasb_revision_pads));
gpio_direction_input(GPIO_NUMBER(2, 28));
gpio_direction_input(GPIO_NUMBER(2, 29));
rev |= (!!gpio_get_value(GPIO_NUMBER(2, 28))) << 0;
rev |= (!!gpio_get_value(GPIO_NUMBER(2, 29))) << 1;
return rev;
}
-inline uint32_t get_efika_rev(void) +inline uint32_t get_efikamx_rev(void) {
- if (machine_is_efikamx())
return get_efikamx_rev();- else
return get_efikasb_rev();
- if (machine_is_efikamx()) {
return get_mx_rev();- } else if (machine_is_efikasb()) {
return get_sb_rev();- }
}
u32 get_board_rev(void) {
- return get_cpu_rev() | (get_efika_rev() << 8);
- return get_cpu_rev() | (get_efikamx_rev() << 8);
}
/* @@ -137,66 +132,35 @@ u32 get_board_rev(void) int dram_init(void) { /* dram_init must store complete ramsize in gd->ram_size */
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE,
PHYS_SDRAM_1_SIZE);
- gd->ram_size = get_ram_size((void *)CONFIG_SYS_SDRAM_BASE, PHYS_SDRAM_1_SIZE); return 0;
}
/*
- UART configuration
*/ -static void setup_iomux_uart(void) -{
- unsigned int pad = PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE |
PAD_CTL_PUE_PULL | PAD_CTL_DRV_HIGH;- mxc_request_iomux(MX51_PIN_UART1_RXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_RXD, pad | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_UART1_TXD, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_TXD, pad | PAD_CTL_SRE_FAST);
- mxc_request_iomux(MX51_PIN_UART1_RTS, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_RTS, pad);
- mxc_request_iomux(MX51_PIN_UART1_CTS, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_UART1_CTS, pad);
-} +static iomux_v3_cfg_t efikamx_uart_pads[] = {
- MX51_PAD_UART1_RXD__UART1_RXD,
- MX51_PAD_UART1_TXD__UART1_TXD,
- MX51_PAD_UART1_RTS__UART1_RTS,
- MX51_PAD_UART1_CTS__UART1_CTS,
+};
/*
- SPI configuration
*/ -#ifdef CONFIG_MXC_SPI -static void setup_iomux_spi(void) -{
- /* 000: Select mux mode: ALT0 mux port: MOSI of instance: ecspi1 */
- mxc_request_iomux(MX51_PIN_CSPI1_MOSI, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_MOSI,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);- /* 000: Select mux mode: ALT0 mux port: MISO of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_MISO, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_MISO,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);- /* Configure SS0 as a GPIO */
- mxc_request_iomux(MX51_PIN_CSPI1_SS0, IOMUX_CONFIG_GPIO);
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS0), 0);
- /* Configure SS1 as a GPIO */
- mxc_request_iomux(MX51_PIN_CSPI1_SS1, IOMUX_CONFIG_GPIO);
- gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSPI1_SS1), 1);
- /* 000: Select mux mode: ALT0 mux port: SS2 of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_RDY, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_RDY,
PAD_CTL_HYS_ENABLE | PAD_CTL_PKE_ENABLE);- /* 000: Select mux mode: ALT0 mux port: SCLK of instance: ecspi1. */
- mxc_request_iomux(MX51_PIN_CSPI1_SCLK, IOMUX_CONFIG_ALT0);
- mxc_iomux_set_pad(MX51_PIN_CSPI1_SCLK,
PAD_CTL_HYS_ENABLE | PAD_CTL_DRV_HIGH | PAD_CTL_SRE_FAST);-} -#else -static inline void setup_iomux_spi(void) { } -#endif +static iomux_v3_cfg_t efikamx_spi_pads[]= {
- MX51_PAD_CSPI1_MOSI__ECSPI1_MOSI,
- MX51_PAD_CSPI1_MISO__ECSPI1_MISO,
- MX51_PAD_CSPI1_SCLK__ECSPI1_SCLK,
- MX51_PAD_CSPI1_SS0__GPIO4_24,
- MX51_PAD_CSPI1_SS1__GPIO4_25,
- MX51_PAD_GPIO1_6__GPIO1_6,
+};
+#define EFIKAMX_SPI_SS0 GPIO_NUMBER(4, 24) +#define EFIKAMX_SPI_SS1 GPIO_NUMBER(4, 25) +#define EFIKAMX_PMIC_IRQ GPIO_NUMBER(1, 6)
/*
- PMIC configuration
@@ -226,7 +190,7 @@ static void power_init(void)
/* Set core voltage to 1.1V */ pmic_reg_read(p, REG_SW_0, &val);
- val = (val & ~SWx_VOLT_MASK) | SWx_1_200V;
val = (val & ~SWx_VOLT_MASK) | SWx_1_100V; pmic_reg_write(p, REG_SW_0, val);
/* Setup VCC (SW2) to 1.25 */
@@ -301,29 +265,64 @@ static inline void power_init(void) { }
- MMC configuration
*/ #ifdef CONFIG_FSL_ESDHC
struct fsl_esdhc_cfg esdhc_cfg[2] = { {MMC_SDHC1_BASE_ADDR, 1}, {MMC_SDHC2_BASE_ADDR, 1}, };
-static inline uint32_t efika_mmc_cd(void) +static iomux_v3_cfg_t efikamx_sdhc1_pads[] = {
- MX51_PAD_SD1_CMD__SD1_CMD,
- MX51_PAD_SD1_CLK__SD1_CLK,
- MX51_PAD_SD1_DATA0__SD1_DATA0,
- MX51_PAD_SD1_DATA1__SD1_DATA1,
- MX51_PAD_SD1_DATA2__SD1_DATA2,
- MX51_PAD_SD1_DATA3__SD1_DATA3,
- MX51_PAD_GPIO1_1__SD1_WP,
+};
+#define EFIKAMX_SDHC1_WP GPIO_NUMBER(1,1)
+static iomux_v3_cfg_t efikamx_sdhc1_cd_pads[] = {
- MX51_PAD_GPIO1_0__SD1_CD,
- MX51_PAD_EIM_CS2__SD1_CD,
+};
+#define EFIKAMX_SDHC1_CD GPIO_NUMBER(1,0) +#define EFIKASB_SDHC1_CD GPIO_NUMBER(2,27)
+static iomux_v3_cfg_t efikasb_sdhc2_pads[] = {
- MX51_PAD_SD2_CMD__SD2_CMD,
- MX51_PAD_SD2_CLK__SD2_CLK,
- MX51_PAD_SD2_DATA0__SD2_DATA0,
- MX51_PAD_SD2_DATA1__SD2_DATA1,
- MX51_PAD_SD2_DATA2__SD2_DATA2,
- MX51_PAD_SD2_DATA3__SD2_DATA3,
- MX51_PAD_GPIO1_7__SD2_WP,
- MX51_PAD_GPIO1_8__SD2_CD,
+};
+#define EFIKASB_SDHC2_CD GPIO_NUMBER(1,8) +#define EFIKASB_SDHC2_WP GPIO_NUMBER(1,7)
+static inline uint32_t efikamx_mmc_getcd(u32 base) {
- if (machine_is_efikamx())
return MX51_PIN_GPIO1_0;- else
return MX51_PIN_EIM_CS2;
- if (base == MMC_SDHC1_BASE_ADDR) {
if (machine_is_efikamx()) {return EFIKAMX_SDHC1_CD;} else {return EFIKASB_SDHC1_CD;}- } else {
return EFIKASB_SDHC2_CD;- }
}
int board_mmc_getcd(struct mmc *mmc) { struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv;
- uint32_t cd = efika_mmc_cd();
- int ret;
- if (cfg->esdhc_base == MMC_SDHC1_BASE_ADDR)
ret = !gpio_get_value(IOMUX_TO_GPIO(cd));- else
ret = !gpio_get_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));
uint32_t cd = efikamx_mmc_getcd(cfg->esdhc_base);
int ret = !gpio_get_value(cd);
return ret;
} @@ -331,214 +330,73 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { int ret;
- uint32_t cd = efika_mmc_cd();
- /* SDHC1 is used on all revisions, setup control pins first */
- mxc_request_iomux(cd,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);- mxc_iomux_set_pad(cd,
PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |PAD_CTL_ODE_OPENDRAIN_NONE |PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);- mxc_request_iomux(MX51_PIN_GPIO1_1,
IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);- mxc_iomux_set_pad(MX51_PIN_GPIO1_1,
PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |PAD_CTL_SRE_FAST);- gpio_direction_input(IOMUX_TO_GPIO(cd));
- gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_1));
- /* Internal SDHC1 IOMUX + SDHC2 IOMUX on old boards */
- if (machine_is_efikasb() || (machine_is_efikamx() &&
(get_efika_rev() < EFIKAMX_BOARD_REV_12))) {/* SDHC1 IOMUX */mxc_request_iomux(MX51_PIN_SD1_CMD,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_SD1_CMD,PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_CLK,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_SD1_CLK,PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,PAD_CTL_PUE_KEEPER | PAD_CTL_PKE_ENABLE |PAD_CTL_DRV_HIGH | PAD_CTL_47K_PU | PAD_CTL_SRE_FAST);/* SDHC2 IOMUX */mxc_request_iomux(MX51_PIN_SD2_CMD,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_SD2_CMD,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD2_CLK,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_SD2_CLK,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD2_DATA0, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD2_DATA0,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD2_DATA1, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD2_DATA1,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD2_DATA2, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD2_DATA2,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD2_DATA3, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD2_DATA3,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);/* SDHC2 Control lines IOMUX */mxc_request_iomux(MX51_PIN_GPIO1_7,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_GPIO1_7,PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |PAD_CTL_PUE_KEEPER | PAD_CTL_100K_PU |PAD_CTL_ODE_OPENDRAIN_NONE |PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_GPIO1_8,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_GPIO1_8,PAD_CTL_DRV_HIGH | PAD_CTL_HYS_ENABLE |PAD_CTL_100K_PU | PAD_CTL_ODE_OPENDRAIN_NONE |PAD_CTL_SRE_FAST);gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_8));gpio_direction_input(IOMUX_TO_GPIO(MX51_PIN_GPIO1_7));ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);if (!ret)ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);- } else { /* New boards use only SDHC1 */
/* SDHC1 IOMUX */mxc_request_iomux(MX51_PIN_SD1_CMD,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_SD1_CMD,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_CLK,IOMUX_CONFIG_ALT0 | IOMUX_CONFIG_SION);mxc_iomux_set_pad(MX51_PIN_SD1_CLK,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA0, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA0,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA1, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA1,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA2, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA2,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);mxc_request_iomux(MX51_PIN_SD1_DATA3, IOMUX_CONFIG_ALT0);mxc_iomux_set_pad(MX51_PIN_SD1_DATA3,PAD_CTL_DRV_MAX | PAD_CTL_22K_PU | PAD_CTL_SRE_FAST);ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
/*
* All Efika MX boards use eSDHC1 with a common write-protect GPIO*/imx_iomux_v3_setup_multiple_pads(efikamx_sdhc1_pads, ARRAY_SIZE(efikamx_sdhc1_pads));
gpio_direction_input(EFIKAMX_SDHC1_WP);
/*
* Smartbook and Smarttop differ on the location of eSDHC1 carrier-detect GPIO*/if (machine_is_efikamx()) {
imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[0]);gpio_direction_input(EFIKAMX_SDHC1_CD);} else if (machine_is_efikasb()) {
imx_iomux_v3_setup_pad(efikamx_sdhc1_cd_pads[1]);gpio_direction_input(EFIKASB_SDHC1_CD);}
ret = fsl_esdhc_initialize(bis, &esdhc_cfg[0]);
if (machine_is_efikasb()) {
imx_iomux_v3_setup_multiple_pads(efikasb_sdhc2_pads, ARRAY_SIZE(efikasb_sdhc2_pads));gpio_direction_input(EFIKASB_SDHC2_CD);gpio_direction_input(EFIKASB_SDHC2_WP);if (!ret)ret = fsl_esdhc_initialize(bis, &esdhc_cfg[1]);}
return ret;
} #endif
/*
- ATA
*/
- PATA
-#ifdef CONFIG_MX51_PATA -#define ATA_PAD_CONFIG (PAD_CTL_DRV_HIGH | PAD_CTL_DRV_VOT_HIGH) -void setup_iomux_ata(void) -{
- mxc_request_iomux(MX51_PIN_NANDF_ALE, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_ALE, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CS2, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS2, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CS3, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS3, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CS4, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS4, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CS5, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS5, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CS6, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CS6, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_RE_B, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RE_B, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_WE_B, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_WE_B, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_CLE, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_CLE, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_RB0, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RB0, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_WP_B, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_WP_B, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_GPIO_NAND, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_GPIO_NAND, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_RB1, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_RB1, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D0, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D0, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D1, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D1, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D2, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D2, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D3, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D3, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D4, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D4, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D5, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D5, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D6, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D6, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D7, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D7, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D8, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D8, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D9, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D9, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D10, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D10, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D11, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D11, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D12, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D12, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D13, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D13, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D14, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D14, ATA_PAD_CONFIG);
- mxc_request_iomux(MX51_PIN_NANDF_D15, IOMUX_CONFIG_ALT1);
- mxc_iomux_set_pad(MX51_PIN_NANDF_D15, ATA_PAD_CONFIG);
-} -#else -static inline void setup_iomux_ata(void) { } -#endif +static iomux_v3_cfg_t efikamx_pata_pads[] = {
- MX51_PAD_NANDF_WE_B__PATA_DIOW,
- MX51_PAD_NANDF_RE_B__PATA_DIOR,
- MX51_PAD_NANDF_ALE__PATA_BUFFER_EN,
- MX51_PAD_NANDF_CLE__PATA_RESET_B,
- MX51_PAD_NANDF_WP_B__PATA_DMACK,
- MX51_PAD_NANDF_RB0__PATA_DMARQ,
- MX51_PAD_NANDF_RB1__PATA_IORDY,
- MX51_PAD_GPIO_NAND__PATA_INTRQ,
- MX51_PAD_NANDF_CS2__PATA_CS_0,
- MX51_PAD_NANDF_CS3__PATA_CS_1,
- MX51_PAD_NANDF_CS4__PATA_DA_0,
- MX51_PAD_NANDF_CS5__PATA_DA_1,
- MX51_PAD_NANDF_CS6__PATA_DA_2,
- MX51_PAD_NANDF_D15__PATA_DATA15,
- MX51_PAD_NANDF_D14__PATA_DATA14,
- MX51_PAD_NANDF_D13__PATA_DATA13,
- MX51_PAD_NANDF_D12__PATA_DATA12,
- MX51_PAD_NANDF_D11__PATA_DATA11,
- MX51_PAD_NANDF_D10__PATA_DATA10,
- MX51_PAD_NANDF_D9__PATA_DATA9,
- MX51_PAD_NANDF_D8__PATA_DATA8,
- MX51_PAD_NANDF_D7__PATA_DATA7,
- MX51_PAD_NANDF_D6__PATA_DATA6,
- MX51_PAD_NANDF_D5__PATA_DATA5,
- MX51_PAD_NANDF_D4__PATA_DATA4,
- MX51_PAD_NANDF_D3__PATA_DATA3,
- MX51_PAD_NANDF_D2__PATA_DATA2,
- MX51_PAD_NANDF_D1__PATA_DATA1,
- MX51_PAD_NANDF_D0__PATA_DATA0,
+};
/*
- EHCI USB
@@ -551,57 +409,55 @@ static inline void setup_iomux_usb(void) { }
/*
- LED configuration
- Smarttop LED pad config is done in the DCD
*/
-void setup_iomux_led(void) -{
- if (machine_is_efikamx()) {
/* Blue LED */mxc_request_iomux(MX51_PIN_CSI1_D9, IOMUX_CONFIG_ALT3);gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9), 0);/* Green LED */mxc_request_iomux(MX51_PIN_CSI1_VSYNC, IOMUX_CONFIG_ALT3);gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC), 0);+#define EFIKAMX_LED_BLUE GPIO_NUMBER(3, 13) +#define EFIKAMX_LED_GREEN GPIO_NUMBER(3, 14) +#define EFIKAMX_LED_RED GPIO_NUMBER(3, 15)
/* Red LED */mxc_request_iomux(MX51_PIN_CSI1_HSYNC, IOMUX_CONFIG_ALT3);gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC), 0);- } else {
/* CAPS-LOCK LED */mxc_request_iomux(MX51_PIN_EIM_CS0, IOMUX_CONFIG_GPIO);gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0), 0);/* ALARM-LED LED */mxc_request_iomux(MX51_PIN_GPIO1_3, IOMUX_CONFIG_GPIO);gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3), 0);- }
-} +static iomux_v3_cfg_t efikasb_led_pads[] = {
- MX51_PAD_GPIO1_3__GPIO1_3,
- MX51_PAD_EIM_CS0__GPIO2_25,
+};
-void efikamx_toggle_led(uint32_t mask) -{
- if (machine_is_efikamx()) {
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_D9),mask & EFIKAMX_LED_BLUE);gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_VSYNC),mask & EFIKAMX_LED_GREEN);gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_CSI1_HSYNC),mask & EFIKAMX_LED_RED);- } else {
gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_CS0),mask & EFIKAMX_LED_BLUE);gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_3),!(mask & EFIKAMX_LED_GREEN));- }
-} +#define EFIKASB_CAPSLOCK_LED GPIO_NUMBER(2, 25) +#define EFIKASB_MESSAGE_LED GPIO_NUMBER(1, 3) /* Note: active low */
/*
- Board initialization
*/ int board_early_init_f(void) {
- setup_iomux_uart();
- setup_iomux_spi();
- setup_iomux_led();
if (machine_is_efikasb()) {
imx_iomux_v3_setup_multiple_pads(efikasb_led_pads, ARRAY_SIZE(efikasb_led_pads));gpio_direction_output(EFIKASB_CAPSLOCK_LED, 0);gpio_direction_output(EFIKASB_MESSAGE_LED, 1);} else if (machine_is_efikamx()) {
/** Set up GPIO directions for LEDs.* IOMUX has been done in the DCD already.* Turn the red LED on for pre-relocation code.*/gpio_direction_output(EFIKAMX_LED_BLUE, 0);gpio_direction_output(EFIKAMX_LED_GREEN, 0);gpio_direction_output(EFIKAMX_LED_RED, 1);}
/*
* Both these pad configurations for UART and SPI are kind of redundant* since they are the Power-On Defaults for the i.MX51. But, it seems we* should make absolutely sure that they are set up correctly.*/imx_iomux_v3_setup_multiple_pads(efikamx_uart_pads, ARRAY_SIZE(efikamx_uart_pads));
imx_iomux_v3_setup_multiple_pads(efikamx_spi_pads, ARRAY_SIZE(efikamx_spi_pads));
/* not technically required for U-Boot operation but set it up anyway. */
gpio_direction_input(EFIKAMX_PMIC_IRQ);
/* Deselect both CS for now.. any other way and NOR doesn't probe properly. */
gpio_direction_output(EFIKAMX_SPI_SS0, 0);
gpio_direction_output(EFIKAMX_SPI_SS1, 1);
return 0;
} @@ -609,49 +465,42 @@ int board_early_init_f(void) int board_init(void) { gd->bd->bi_boot_params = PHYS_SDRAM_1 + 0x100;
- return 0;
}
int board_late_init(void) {
- setup_iomux_spi();
- if (machine_is_efikamx()) {
/** Set up Blue LED for "In U-Boot" status.* We're all relocated and ready to U-Boot!*/gpio_set_value(EFIKAMX_LED_RED, 0);gpio_set_value(EFIKAMX_LED_GREEN, 0);gpio_set_value(EFIKAMX_LED_BLUE, 1);- }
- power_init();
- setup_iomux_led();
- setup_iomux_ata();
imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads, ARRAY_SIZE(efikamx_pata_pads)); setup_iomux_usb();
if (machine_is_efikasb()) setenv("preboot", "usb reset ; setenv stdin usbkbd\0");
- setup_iomux_led();
- efikamx_toggle_led(EFIKAMX_LED_BLUE);
- return 0;
}
int checkboard(void) {
- u32 rev = get_efika_rev();
u32 rev = get_efikamx_rev();
printf("Board: Genesi Efika MX "); if (machine_is_efikamx()) {
printf("Board: Efika MX, rev1.%i\n", rev & 0xf);return 0;- } else {
switch (rev) {case EFIKASB_BOARD_REV_13:printf("Board: Efika SB rev1.3\n");break;case EFIKASB_BOARD_REV_20:printf("Board: Efika SB rev2.0\n");break;default:printf("Board: Efika SB, rev Unknown\n");break;}
printf("Smarttop (1.%i)\n", rev & 0xf);} else if (machine_is_efikasb()) {
printf("Smartbook\n");}
return 0;
In principle I am fine with this patch - ok, I read also the other comments and I can tell you my opinion.
Generally, we have patches for each issues. But everything here concerns only the efika boards and only a single file was changed, and changes are described in the commit message. We have also other examples doing the same, if we check in the git history. And as single patch, we konw that it is surely bisectable.
Regarding if it is better to set a single pad array or use an array for each single peripheral, well, this is a question of taste. When one choose one of them, the choice should be consistent, but both choices are praticable and have advantages and disadvantages.
Anyway, who will maintain the efikas in future ? Marek, do you hold it, or Matt will take this job ? In last case I would like to see a patch for the MAINTAINER file.
Best regards, Stefano Babic
On Sat, Aug 18, 2012 at 10:50 AM, Stefano Babic sbabic@denx.de wrote:
On 17/08/2012 20:19, Matt Sealey wrote:
Anyway, who will maintain the efikas in future ? Marek, do you hold it, or Matt will take this job ?
I'll do it but I doubt I'm going to be around as much as Marek. What I'm a little fearful of is having patches try and hit the Efika stuff and me not having much time that day to review, they either stagnate or get accepted anyway breaking something. I can't test every patch everyone sends, we just want to be sure it's hit a certain level of quality and solve some of the issues we hacked around at the Freescale BSP level are in mainline as we simply can't use the BSP version anymore (doesn't support bootz or device trees...)
In last case I would like to see a patch for the MAINTAINER file.
I'll submit it when I feel like we're actually being "forced" to maintain it. I am of two minds; I will be the responsible party if needs be, but that means Efika MX stuff is going to be commercially driven by our needs (i.e. runs our boot scripts, supports the board the way we dictate (no video, no usb keyboards..), no changes to support "developers" if they are simply being too needy), and if it doesn't suit us in terms of breaking something or changing behaviour wildly, we'll NACK the crap out of it. If that's acceptable, sure... Marek says U-Boot doesn't follow this development model, but that would put Denx out of business.
Dear Matt Sealey,
On Sat, Aug 18, 2012 at 10:50 AM, Stefano Babic sbabic@denx.de wrote:
On 17/08/2012 20:19, Matt Sealey wrote:
Anyway, who will maintain the efikas in future ? Marek, do you hold it, or Matt will take this job ?
I'll do it but I doubt I'm going to be around as much as Marek. What I'm a little fearful of is having patches try and hit the Efika stuff and me not having much time that day to review, they either stagnate or get accepted anyway breaking something.
So your commercial QA has to arrive at the RC stage and fix it if needed ... every around 3-4 months.
I can't test every patch everyone sends, we just want to be sure it's hit a certain level of quality and solve some of the issues we hacked around at the Freescale BSP level are in mainline as we simply can't use the BSP version anymore (doesn't support bootz or device trees...)
In last case I would like to see a patch for the MAINTAINER file.
I'll submit it when I feel like we're actually being "forced" to maintain it. I am of two minds; I will be the responsible party if needs be, but that means Efika MX stuff is going to be commercially driven by our needs (i.e. runs our boot scripts, supports the board the way we dictate (no video, no usb keyboards..), no changes to support "developers" if they are simply being too needy), and if it doesn't suit us in terms of breaking something or changing behaviour wildly, we'll NACK the crap out of it.
I think you need to understand that FOSS is a cooperative effort. It is not any commercial crap which you roll out and throw away when it made enough money. We will not stop hacking on mx51 only because it might break your platform, that's not how it works.
To put it into more "commercial" terms, we are not paid to support your platform, on the other hand, we already gave you the source code. So to restore the balance, you help us keeping it working well by investing in QA. Everyone's happy.
Besides, if you want to deploy less potent version, you can always configure your u-boot in such way and deploy it to customer, noone can prevent you from that. But since there is support for certain additional hardware in upstream already, I'd object to remove it.
If that's acceptable, sure... Marek says U-Boot doesn't follow this development model, but that would put Denx out of business.
Please stop putting words in my mouth, it is fairy insulting.
See how the mx28 stuff is being developed to see what I mean. Me, Fabio, Otavio and many others are adjusting each others boards and it works very well.
Best regards, Marek Vasut
On Sat, Aug 18, 2012 at 5:26 PM, Marek Vasut marex@denx.de wrote:
Dear Matt Sealey,
On Sat, Aug 18, 2012 at 10:50 AM, Stefano Babic sbabic@denx.de wrote:
On 17/08/2012 20:19, Matt Sealey wrote:
Anyway, who will maintain the efikas in future ? Marek, do you hold it, or Matt will take this job ?
I'll do it but I doubt I'm going to be around as much as Marek. What I'm a little fearful of is having patches try and hit the Efika stuff and me not having much time that day to review, they either stagnate or get accepted anyway breaking something.
So your commercial QA has to arrive at the RC stage and fix it if needed ... every around 3-4 months.
That is in fact the plan.
If we can get TO2 support back in at that time, we will do it, but for now it cannot just go in broken. We cannot test the mux code on these boards if they don't boot...
I think you need to understand that FOSS is a cooperative effort. It is not any commercial crap which you roll out and throw away when it made enough money. We will not stop hacking on mx51 only because it might break your platform, that's not how it works.
The problem here is that we don't make any money from MX51 anymore; there are no Efika MX systems to sell, stock is basically depleted. So this work is an offshoot of some other code. If, on the other hand, you want to cooperate and test it on TO2 and report your results and tell us what is broken, that would be fine, but we can't expend time and effort fixing something which represents barely a percentage point of customers; if you don't have a TO2, then you can't help, and you can't complain if you can't run it let alone test it.
To put it into more "commercial" terms, we are not paid to support your platform, on the other hand, we already gave you the source code. So to restore the balance, you help us keeping it working well by investing in QA. Everyone's happy.
Besides, if you want to deploy less potent version, you can always configure your u-boot in such way and deploy it to customer, noone can prevent you from that. But since there is support for certain additional hardware in upstream already, I'd object to remove it.
That is the way we're doing it, but we can't in good conscience deploy a non-neutered version with such heavy cleanups that we cannot guarantee booted in the first place let alone with our changes. Modifying the IOMUX setup method did not fix booting, but we cannot tell if it worked properly in the first place. Number of users of TO2 Efika MX boards r1.1 and r1.2 is so low, it's hard to imagine these people giving a rat's ass about whether mainline works on it or not (especially since there's no mainline Linux support for these boards as it stands - even with the old U-Boot we shipped on the boards that works, the kernel is less than reliable for various reasons).
See how the mx28 stuff is being developed to see what I mean. Me, Fabio, Otavio and many others are adjusting each others boards and it works very well.
I would like to see you justify again updating code that supports a board that hasn't actually booted mainline U-Boot in several months, if not years, with a code change that cannot be tested.
Once it's gone through testing and we work out for sure why U-Boot simply does not run on a cpu-revision 51025 i.MX processor on the r1.1 and r1.2 boards in any version, before my changes or after, we will patch back in confirmed and working support, but we shouldn't be told we have to maintain broken code just so it sticks around. You have git, you can see the changes made to remove the code (it's literally all of 3 lines extra to add it back in, it is mainly the second SD card slot definition and CD/WP pins). It is not like the information is lost in time.
I just don't see the point in making sure we update every line of code that exists, if that code simply never gets run, or never has the opportunity to run due to other problems.
This is a dead product, we simply want to make sure that SOME mainline support is both reliable and usable. The work directly influences the design of new products and existing products which are not in mainline; to get MX53 stuff in there or MX6 design stuff in there, common IOMUX setup, common GPIO, other common things which are otherwise awful to define and add to designs. If we evaluate the software development will take too much time and money it may be cut from the design. If the feature makes the board less user-friendly as a result, it will definitely never make it into a prototype.
Right now, we're trying to lay a good foundation for MX53 and MX6 designs we currently sell. Supporting the MX51 models is purely laying that good foundation to make sure that the effort we expend later on actual shipping products can be tested across the entire line where common code and configuration can and should exist. Unfortunately i.MX51 TO2 designs exist in the world in some number, but fortunately the number of people running them who require U-Boot to build and run on their boards is a big fat zero. If there are no users, the code can go.. if there is a user for it later, it can be re-evaluated by someone out there.
Would it make a difference if I was the maintainer? Yes, because you would be automatically overridden in asking to keep TO2 code in there because as maintainer I would not be willing to maintain such code. It doesn't matter in that position if YOU think it MIGHT be useful for someone else, as the a) designers b) vendors c) support network for this hardware, we have decided flat out, Efika MX r1.1 and r1.2 boards are not worth supporting in this patch and should definitely not leave code around which could be mistakenly run, or possibly just exist to confuse the configuration of the board.
Crashing before even reaching the relocation code is not user-friendly. As it stands, removing the TO2 support to reduce the amount of testing we have to do (in the sense that it cannot be tested while the bug exists) and then adding it back in once that testing is actually completed, while providing the vast majority of users working code in the meantime, is more important right now, making that common code work.
Dear Matt Sealey,
On Sat, Aug 18, 2012 at 5:26 PM, Marek Vasut marex@denx.de wrote:
Dear Matt Sealey,
On Sat, Aug 18, 2012 at 10:50 AM, Stefano Babic sbabic@denx.de wrote:
On 17/08/2012 20:19, Matt Sealey wrote:
Anyway, who will maintain the efikas in future ? Marek, do you hold it, or Matt will take this job ?
I'll do it but I doubt I'm going to be around as much as Marek. What I'm a little fearful of is having patches try and hit the Efika stuff and me not having much time that day to review, they either stagnate or get accepted anyway breaking something.
So your commercial QA has to arrive at the RC stage and fix it if needed ... every around 3-4 months.
That is in fact the plan.
If we can get TO2 support back in at that time, we will do it, but for now it cannot just go in broken. We cannot test the mux code on these boards if they don't boot...
I think you need to understand that FOSS is a cooperative effort. It is not any commercial crap which you roll out and throw away when it made enough money. We will not stop hacking on mx51 only because it might break your platform, that's not how it works.
The problem here is that we don't make any money from MX51 anymore; there are no Efika MX systems to sell, stock is basically depleted. So this work is an offshoot of some other code. If, on the other hand, you want to cooperate and test it on TO2 and report your results and tell us what is broken, that would be fine, but we can't expend time and effort fixing something which represents barely a percentage point of customers; if you don't have a TO2, then you can't help, and you can't complain if you can't run it let alone test it.
To put it into more "commercial" terms, we are not paid to support your platform, on the other hand, we already gave you the source code. So to restore the balance, you help us keeping it working well by investing in QA. Everyone's happy.
Besides, if you want to deploy less potent version, you can always configure your u-boot in such way and deploy it to customer, noone can prevent you from that. But since there is support for certain additional hardware in upstream already, I'd object to remove it.
That is the way we're doing it, but we can't in good conscience deploy a non-neutered version with such heavy cleanups that we cannot guarantee booted in the first place let alone with our changes. Modifying the IOMUX setup method did not fix booting, but we cannot tell if it worked properly in the first place. Number of users of TO2 Efika MX boards r1.1 and r1.2 is so low, it's hard to imagine these people giving a rat's ass about whether mainline works on it or not (especially since there's no mainline Linux support for these boards as it stands - even with the old U-Boot we shipped on the boards that works, the kernel is less than reliable for various reasons).
See how the mx28 stuff is being developed to see what I mean. Me, Fabio, Otavio and many others are adjusting each others boards and it works very well.
I would like to see you justify again updating code that supports a board that hasn't actually booted mainline U-Boot in several months, if not years, with a code change that cannot be tested.
Once it's gone through testing and we work out for sure why U-Boot simply does not run on a cpu-revision 51025 i.MX processor on the r1.1 and r1.2 boards in any version, before my changes or after, we will patch back in confirmed and working support, but we shouldn't be told we have to maintain broken code just so it sticks around. You have git, you can see the changes made to remove the code (it's literally all of 3 lines extra to add it back in, it is mainly the second SD card slot definition and CD/WP pins). It is not like the information is lost in time.
I just don't see the point in making sure we update every line of code that exists, if that code simply never gets run, or never has the opportunity to run due to other problems.
This is a dead product, we simply want to make sure that SOME mainline support is both reliable and usable. The work directly influences the design of new products and existing products which are not in mainline; to get MX53 stuff in there or MX6 design stuff in there, common IOMUX setup, common GPIO, other common things which are otherwise awful to define and add to designs. If we evaluate the software development will take too much time and money it may be cut from the design. If the feature makes the board less user-friendly as a result, it will definitely never make it into a prototype.
Right now, we're trying to lay a good foundation for MX53 and MX6 designs we currently sell. Supporting the MX51 models is purely laying that good foundation to make sure that the effort we expend later on actual shipping products can be tested across the entire line where common code and configuration can and should exist. Unfortunately i.MX51 TO2 designs exist in the world in some number, but fortunately the number of people running them who require U-Boot to build and run on their boards is a big fat zero. If there are no users, the code can go.. if there is a user for it later, it can be re-evaluated by someone out there.
Would it make a difference if I was the maintainer? Yes, because you would be automatically overridden in asking to keep TO2 code in there because as maintainer I would not be willing to maintain such code. It doesn't matter in that position if YOU think it MIGHT be useful for someone else, as the a) designers b) vendors c) support network for this hardware, we have decided flat out, Efika MX r1.1 and r1.2 boards are not worth supporting in this patch and should definitely not leave code around which could be mistakenly run, or possibly just exist to confuse the configuration of the board.
Crashing before even reaching the relocation code is not user-friendly. As it stands, removing the TO2 support to reduce the amount of testing we have to do (in the sense that it cannot be tested while the bug exists) and then adding it back in once that testing is actually completed, while providing the vast majority of users working code in the meantime, is more important right now, making that common code work.
Can you concentrate the information that completely sunk in the text above? What's your point? In a _few_ sentences please. Mailing list is not highschool, you don't get graded for writing an essay. Besides, you waste both yours and mine time.
Best regards, Marek Vasut
Am 18/08/2012 23:02, schrieb Matt Sealey:
On Sat, Aug 18, 2012 at 10:50 AM, Stefano Babic sbabic@denx.de wrote:
On 17/08/2012 20:19, Matt Sealey wrote:
Anyway, who will maintain the efikas in future ? Marek, do you hold it, or Matt will take this job ?
I can't test every patch everyone sends, we just want to be sure it's hit a certain level of quality and solve some of the issues we hacked around at the Freescale BSP level are in mainline as we simply can't use the BSP version anymore (doesn't support bootz or device trees...)
In last case I would like to see a patch for the MAINTAINER file.
I'll submit it when I feel like we're actually being "forced" to maintain it.
You are absolutely not forced - my was a simple question.
I am of two minds; I will be the responsible party if needs be, but that means Efika MX stuff is going to be commercially driven by our needs (i.e. runs our boot scripts, supports the board the way we dictate (no video, no usb keyboards..), no changes to support "developers" if they are simply being too needy),
You are confusing commercial goals with an open source project, as u-boot is.
and if it doesn't suit us in terms of breaking something or changing behaviour wildly, we'll NACK the crap out of it. If that's acceptable, sure...
You can propose your boot scripts to the ML, and they can be accepted or not, depending if they are helpful for the project.
Marek says U-Boot doesn't follow this development model, but that would put Denx out of business.
Not really - again, you are confusing the way you want to put your products on the market with an open source project. You can sell of course your product with the software you decide and you think it is better - this is your commercial decision. An open source project is developped with different goals, that are not strictly bound to a single commercial product.
Best regards, Stefano Babic
* Add required pin data to iomux-mx51.h * Port old iomux model to new iomux-v3 model * Remove some needless code * Function renames for readability
Signed-off-by: Matt Sealey matt@genesi-usa.com --- arch/arm/include/asm/arch-mx5/iomux-mx51.h | 28 +++++ board/genesi/mx51_efikamx/efikamx-usb.c | 159 +++++++++++++--------------- board/genesi/mx51_efikamx/efikamx.c | 6 +- 3 files changed, 104 insertions(+), 89 deletions(-)
diff --git a/arch/arm/include/asm/arch-mx5/iomux-mx51.h b/arch/arm/include/asm/arch-mx5/iomux-mx51.h index f944c13..0a99ae4 100644 --- a/arch/arm/include/asm/arch-mx5/iomux-mx51.h +++ b/arch/arm/include/asm/arch-mx5/iomux-mx51.h @@ -79,6 +79,20 @@
/* PAD MUX ALT INPSE PATH PADCTRL */ enum { + MX51_PAD_EIM_D16__USBH2_DATA0 = IOMUX_PAD(0x3f0, 0x05c, 2, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_EIM_D17__USBH2_DATA1 = IOMUX_PAD(0x3f4, 0x060, 2, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_EIM_D18__USBH2_DATA2 = IOMUX_PAD(0x3f8, 0x064, 2, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_EIM_D19__USBH2_DATA3 = IOMUX_PAD(0x3fc, 0x068, 2, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_EIM_D20__USBH2_DATA4 = IOMUX_PAD(0x400, 0x06c, 2, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_EIM_D21__USBH2_DATA5 = IOMUX_PAD(0x404, 0x070, 2, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_EIM_D22__USBH2_DATA6 = IOMUX_PAD(0x408, 0x074, 2, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_EIM_D23__USBH2_DATA7 = IOMUX_PAD(0x40c, 0x078, 2, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_EIM_D27__GPIO2_9 = IOMUX_PAD(0x41c, 0x088, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_EIM_A24__USBH2_CLK = IOMUX_PAD(0x450, 0x0bc, 2, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_EIM_A25__USBH2_DIR = IOMUX_PAD(0x454, 0x0c0, 2, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_EIM_A26__GPIO2_20 = IOMUX_PAD(0x458, 0x0c4, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_EIM_A26__USBH2_STP = IOMUX_PAD(0x458, 0x0c4, 2, __NA_, 0, NO_PAD_CTRL), + MX51_PAD_EIM_A27__USBH2_NXT = IOMUX_PAD(0x45c, 0x0c8, 2, __NA_, 0, NO_PAD_CTRL), MX51_PAD_EIM_CS0__GPIO2_25 = IOMUX_PAD(0x474, 0x0e0, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), MX51_PAD_EIM_CS2__SD1_CD = IOMUX_PAD(0x47c, 0x0e8, 1, __NA_, 0, MX51_ESDHC_PAD_CTRL), MX51_PAD_EIM_CS3__GPIO2_28 = IOMUX_PAD(0x480, 0x0ec, 1, __NA_, 0, MX51_GPIO_PAD_CTRL), @@ -121,6 +135,19 @@ enum { MX51_PAD_UART1_TXD__UART1_TXD = IOMUX_PAD(0x61c, 0x22c, 0, __NA_, 0, MX51_UART_PAD_CTRL), MX51_PAD_UART1_RTS__UART1_RTS = IOMUX_PAD(0x620, 0x230, 0, 0x9e0, 0, MX51_UART_PAD_CTRL), MX51_PAD_UART1_CTS__UART1_CTS = IOMUX_PAD(0x624, 0x234, 0, __NA_, 0, MX51_UART_PAD_CTRL), + MX51_PAD_USBH1_CLK__USBH1_CLK = IOMUX_PAD(0x678, 0x278, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), + MX51_PAD_USBH1_DIR__USBH1_DIR = IOMUX_PAD(0x67c, 0x27c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), + MX51_PAD_USBH1_STP__USBH1_STP = IOMUX_PAD(0x680, 0x280, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), + MX51_PAD_USBH1_STP__GPIO1_27 = IOMUX_PAD(0x680, 0x280, 2, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_USBH1_NXT__USBH1_NXT = IOMUX_PAD(0x684, 0x284, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), + MX51_PAD_USBH1_DATA0__USBH1_DATA0 = IOMUX_PAD(0x688, 0x288, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), + MX51_PAD_USBH1_DATA1__USBH1_DATA1 = IOMUX_PAD(0x68c, 0x28c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), + MX51_PAD_USBH1_DATA2__USBH1_DATA2 = IOMUX_PAD(0x690, 0x290, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), + MX51_PAD_USBH1_DATA3__USBH1_DATA3 = IOMUX_PAD(0x694, 0x294, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), + MX51_PAD_USBH1_DATA4__USBH1_DATA4 = IOMUX_PAD(0x698, 0x298, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), + MX51_PAD_USBH1_DATA5__USBH1_DATA5 = IOMUX_PAD(0x69c, 0x29c, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), + MX51_PAD_USBH1_DATA6__USBH1_DATA6 = IOMUX_PAD(0x6a0, 0x2a0, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), + MX51_PAD_USBH1_DATA7__USBH1_DATA7 = IOMUX_PAD(0x6a4, 0x2a4, 0, __NA_, 0, MX51_USBH1_PAD_CTRL), MX51_PAD_SD1_CMD__SD1_CMD = IOMUX_PAD(0x79c, 0x394, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), MX51_PAD_SD1_CLK__SD1_CLK = IOMUX_PAD(0x7a0, 0x398, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL | PAD_CTL_HYS), MX51_PAD_SD1_DATA0__SD1_DATA0 = IOMUX_PAD(0x7a4, 0x39c, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), @@ -136,6 +163,7 @@ enum { MX51_PAD_SD2_DATA2__SD2_DATA2 = IOMUX_PAD(0x7cc, 0x3c4, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), MX51_PAD_SD2_DATA3__SD2_DATA3 = IOMUX_PAD(0x7d0, 0x3c8, 0x10, __NA_, 0, MX51_SDHCI_PAD_CTRL), MX51_PAD_GPIO1_3__GPIO1_3 = IOMUX_PAD(0x7d8, 0x3d0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), + MX51_PAD_GPIO1_5__GPIO1_5 = IOMUX_PAD(0x808, 0x3dc, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), MX51_PAD_GPIO1_6__GPIO1_6 = IOMUX_PAD(0x80c, 0x3e0, 0, __NA_, 0, MX51_GPIO_PAD_CTRL), MX51_PAD_GPIO1_7__SD2_WP = IOMUX_PAD(0x810, 0x3e4, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL), MX51_PAD_GPIO1_8__SD2_CD = IOMUX_PAD(0x814, 0x3e8, 6, __NA_, 0, MX51_ESDHC_PAD_CTRL), diff --git a/board/genesi/mx51_efikamx/efikamx-usb.c b/board/genesi/mx51_efikamx/efikamx-usb.c index e9273d0..0935c38 100644 --- a/board/genesi/mx51_efikamx/efikamx-usb.c +++ b/board/genesi/mx51_efikamx/efikamx-usb.c @@ -1,7 +1,7 @@ /* + * Copyright (C) 2009 Freescale Semiconductor, Inc. * Copyright (C) 2010 Marek Vasut marek.vasut@gmail.com - * - * (C) Copyright 2009 Freescale Semiconductor, Inc. + * Copyright (C) 2009-2012 Genesi USA, Inc. * * See file CREDITS for list of people who contributed to this * project. @@ -25,9 +25,7 @@ #include <common.h> #include <usb.h> #include <asm/io.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/mx5x_pins.h> -#include <asm/arch/iomux.h> +#include <asm/arch/iomux-mx51.h> #include <asm/gpio.h> #include <usb/ehci-fsl.h> #include <usb/ulpi.h> @@ -35,103 +33,93 @@
#include "../../../drivers/usb/host/ehci.h"
-/* USB pin configuration */ -#define USB_PAD_CONFIG (PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST | \ - PAD_CTL_DRV_HIGH | PAD_CTL_100K_PU | \ - PAD_CTL_HYS_ENABLE | PAD_CTL_PUE_PULL) - -/* - * Configure the USB H1 and USB H2 IOMUX - */ -void setup_iomux_usb(void) +static iomux_v3_cfg_t efikamx_usbh1_pads[] = { + MX51_PAD_USBH1_CLK__USBH1_CLK, + MX51_PAD_USBH1_DIR__USBH1_DIR, + MX51_PAD_USBH1_STP__USBH1_STP, + MX51_PAD_USBH1_NXT__USBH1_NXT, + MX51_PAD_USBH1_DATA0__USBH1_DATA0, + MX51_PAD_USBH1_DATA1__USBH1_DATA1, + MX51_PAD_USBH1_DATA2__USBH1_DATA2, + MX51_PAD_USBH1_DATA3__USBH1_DATA3, + MX51_PAD_USBH1_DATA4__USBH1_DATA4, + MX51_PAD_USBH1_DATA5__USBH1_DATA5, + MX51_PAD_USBH1_DATA6__USBH1_DATA6, + MX51_PAD_USBH1_DATA7__USBH1_DATA7, +}; + +static iomux_v3_cfg_t efikasb_usbh2_pads[] = { + MX51_PAD_EIM_A24__USBH2_CLK, + MX51_PAD_EIM_A25__USBH2_DIR, + MX51_PAD_EIM_A26__USBH2_STP, + MX51_PAD_EIM_A27__USBH2_NXT, + MX51_PAD_EIM_D16__USBH2_DATA0, + MX51_PAD_EIM_D17__USBH2_DATA1, + MX51_PAD_EIM_D18__USBH2_DATA2, + MX51_PAD_EIM_D19__USBH2_DATA3, + MX51_PAD_EIM_D20__USBH2_DATA4, + MX51_PAD_EIM_D21__USBH2_DATA5, + MX51_PAD_EIM_D22__USBH2_DATA6, + MX51_PAD_EIM_D23__USBH2_DATA7, +}; + +static iomux_v3_cfg_t efikamx_usbctrl_pads[] = { + MX51_PAD_EIM_D27__GPIO2_9, + MX51_PAD_GPIO1_5__GPIO1_5, +}; + +#define EFIKAMX_USB_HUB_RESET GPIO_NUMBER(1, 5) +#define EFIKAMX_USB_PHY_RESET GPIO_NUMBER(2, 9) + +void efikamx_usb_setup_pads(void) { - setup_iomux_usb_h1(); - - if (machine_is_efikasb()) - setup_iomux_usb_h2(); - - /* USB PHY reset */ - mxc_request_iomux(MX51_PIN_EIM_D27, IOMUX_CONFIG_ALT1); - mxc_iomux_set_pad(MX51_PIN_EIM_D27, PAD_CTL_PKE_ENABLE | - PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); - - /* USB HUB reset */ - mxc_request_iomux(MX51_PIN_GPIO1_5, IOMUX_CONFIG_ALT0); - mxc_iomux_set_pad(MX51_PIN_GPIO1_5, PAD_CTL_PKE_ENABLE | - PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH); - - /* WIFI EN (act low) */ - mxc_request_iomux(MX51_PIN_EIM_A22, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_EIM_A22, 0); - /* WIFI RESET */ - mxc_request_iomux(MX51_PIN_EIM_A16, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_EIM_A16, 0); - /* BT EN (act low) */ - mxc_request_iomux(MX51_PIN_EIM_A17, IOMUX_CONFIG_GPIO); - mxc_iomux_set_pad(MX51_PIN_EIM_A17, 0); -} + imx_iomux_v3_setup_multiple_pads(efikamx_usbh1_pads, ARRAY_SIZE(efikamx_usbh1_pads));
-/* - * Enable devices connected to USB BUSes - */ -static void efika_usb_enable_devices(void) -{ - /* Enable Bluetooth */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 0); - udelay(10000); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A17), 1); - - /* Enable WiFi */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A22), 1); - udelay(10000); + if (machine_is_efikasb()) { + imx_iomux_v3_setup_multiple_pads(efikasb_usbh2_pads, ARRAY_SIZE(efikasb_usbh2_pads)); + }
- /* Reset the WiFi chip */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 0); - udelay(10000); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_A16), 1); + imx_iomux_v3_setup_multiple_pads(efikamx_usbctrl_pads, ARRAY_SIZE(efikamx_usbctrl_pads)); }
/* * Reset USB HUB (or HUBs on EfikaSB) */ -static void efika_usb_hub_reset(void) +static void efikamx_usb_hub_reset(void) { - /* HUB reset */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1); + gpio_direction_output(EFIKAMX_USB_HUB_RESET, 1); udelay(1000); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 0); + gpio_set_value(EFIKAMX_USB_HUB_RESET, 0); udelay(1000); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_GPIO1_5), 1); + gpio_set_value(EFIKAMX_USB_HUB_RESET, 1); }
/* * Reset USB PHY (or PHYs on EfikaSB) */ -static void efika_usb_phy_reset(void) +static void efikamx_usb_phy_reset(void) { /* SMSC 3317 PHY reset */ - gpio_direction_output(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 0); + gpio_direction_output(EFIKAMX_USB_PHY_RESET, 0); udelay(1000); - gpio_set_value(IOMUX_TO_GPIO(MX51_PIN_EIM_D27), 1); + gpio_set_value(EFIKAMX_USB_PHY_RESET, 1); }
-static void efika_ehci_init(struct usb_ehci *ehci, uint32_t stp_gpio, - uint32_t alt0, uint32_t alt1) +static void efikamx_usb_init(struct usb_ehci *ehci, + iomux_v3_cfg_t stp_pad, + iomux_v3_cfg_t gpio_pad, + u32 gpio_nr) { int ret; struct ulpi_regs *ulpi = (struct ulpi_regs *)0; struct ulpi_viewport ulpi_vp;
- mxc_request_iomux(stp_gpio, alt0); - mxc_iomux_set_pad(stp_gpio, PAD_CTL_DRV_HIGH | - PAD_CTL_PKE_ENABLE | PAD_CTL_SRE_FAST); - gpio_direction_output(IOMUX_TO_GPIO(stp_gpio), 0); + imx_iomux_v3_setup_pad(gpio_pad); + gpio_direction_output(gpio_nr, 0); udelay(1000); - gpio_set_value(IOMUX_TO_GPIO(stp_gpio), 1); + gpio_set_value(gpio_nr, 1); udelay(1000); - - mxc_request_iomux(stp_gpio, alt1); - mxc_iomux_set_pad(stp_gpio, USB_PAD_CONFIG); + imx_iomux_v3_setup_pad(stp_pad); udelay(10000);
ulpi_vp.viewport_addr = (u32)&ehci->ulpi_viewpoint; @@ -159,18 +147,18 @@ static void efika_ehci_init(struct usb_ehci *ehci, uint32_t stp_gpio, /* * Set VBusChrg * - * NOTE: This violates USB specification, but otherwise, USB on Efika + * NOTE: This violates USB specification, but otherwise, USB on Efika MX * doesn't work. */ ulpi_write(&ulpi_vp, &ulpi->otg_ctrl_set, ULPI_OTG_CHRGVBUS); + + mdelay(10); }
int board_ehci_hcd_init(int port) { - /* Init iMX51 EHCI */ - efika_usb_phy_reset(); - efika_usb_hub_reset(); - efika_usb_enable_devices(); + efikamx_usb_phy_reset(); + efikamx_usb_hub_reset();
return 0; } @@ -204,13 +192,12 @@ void board_ehci_hcd_postinit(struct usb_ehci *ehci, int port) tmp = (tmp & ~0x3) | 0x01; writel(tmp, OTG_BASE_ADDR + 0x80c); } else if (port == 1) { - efika_ehci_init(ehci, MX51_PIN_USBH1_STP, - IOMUX_CONFIG_ALT2, IOMUX_CONFIG_ALT0); + efikamx_usb_init(ehci, MX51_PAD_USBH1_STP__USBH1_STP, + MX51_PAD_USBH1_STP__GPIO1_27, + GPIO_NUMBER(1, 27)); } else if ((port == 2) && machine_is_efikasb()) { - efika_ehci_init(ehci, MX51_PIN_EIM_A26, - IOMUX_CONFIG_ALT1, IOMUX_CONFIG_ALT2); + efikamx_usb_init(ehci, MX51_PAD_EIM_A26__USBH2_STP, + MX51_PAD_EIM_A26__GPIO2_20, + GPIO_NUMBER(2, 20)); } - - if (port) - mdelay(10); } diff --git a/board/genesi/mx51_efikamx/efikamx.c b/board/genesi/mx51_efikamx/efikamx.c index 16e877f..a22db1e 100644 --- a/board/genesi/mx51_efikamx/efikamx.c +++ b/board/genesi/mx51_efikamx/efikamx.c @@ -402,9 +402,9 @@ static iomux_v3_cfg_t efikamx_pata_pads[] = { * EHCI USB */ #ifdef CONFIG_CMD_USB -extern void setup_iomux_usb(void); +extern void efikamx_usb_setup_pads(void); #else -static inline void setup_iomux_usb(void) { } +static inline void efikamx_usb_setup_pads(void) { } #endif
/* @@ -484,7 +484,7 @@ int board_late_init(void) power_init();
imx_iomux_v3_setup_multiple_pads(efikamx_pata_pads, ARRAY_SIZE(efikamx_pata_pads)); - setup_iomux_usb(); + efikamx_usb_setup_pads();
if (machine_is_efikasb()) setenv("preboot", "usb reset ; setenv stdin usbkbd\0");
Dear Matt Sealey,
This patchset relies on the previously submitted patch "mx5: add iomux-mx51.h include"
It may not boot reliably, completely at random, on Efika MX boards, without the previously submitted (series) "spi: fix mxc_spi_slave structure allocation to clear memory"
Please _ALWAYS_ CC the custodian. Read here before submitting:
http://www.denx.de/wiki/U-Boot/Patches
Matt Sealey (4): efikamx: move efikamx into a new directory in preparation for new boards efikamx: remove drive strength hack from early_init_f and move it to the DCD efikamx: update to Efika MX Smarttop and Smartbook boards efikamx: port USB setup to new iomux model
arch/arm/include/asm/arch-mx5/iomux-mx51.h | 28 ++ board/efikamx/Makefile | 49 -- board/efikamx/efikamx-usb.c | 216 -------- board/efikamx/efikamx.c | 735 ---------------------------- board/efikamx/imximage_mx.cfg | 122 ----- board/efikamx/imximage_sb.cfg | 122 ----- board/genesi/mx51_efikamx/Makefile | 49 ++ board/genesi/mx51_efikamx/efikamx-usb.c | 203 ++++++++ board/genesi/mx51_efikamx/efikamx.c | 507 +++++++++++++++++++ board/genesi/mx51_efikamx/imximage_mx.cfg | 113 +++++ board/genesi/mx51_efikamx/imximage_sb.cfg | 122 +++++ boards.cfg | 4 +- include/configs/efikamx.h | 274 ----------- include/configs/mx51_efikamx.h | 274 +++++++++++ 14 files changed, 1298 insertions(+), 1520 deletions(-) delete mode 100644 board/efikamx/Makefile delete mode 100644 board/efikamx/efikamx-usb.c delete mode 100644 board/efikamx/efikamx.c delete mode 100644 board/efikamx/imximage_mx.cfg delete mode 100644 board/efikamx/imximage_sb.cfg create mode 100644 board/genesi/mx51_efikamx/Makefile create mode 100644 board/genesi/mx51_efikamx/efikamx-usb.c create mode 100644 board/genesi/mx51_efikamx/efikamx.c create mode 100644 board/genesi/mx51_efikamx/imximage_mx.cfg create mode 100644 board/genesi/mx51_efikamx/imximage_sb.cfg delete mode 100644 include/configs/efikamx.h create mode 100644 include/configs/mx51_efikamx.h
Best regards, Marek Vasut
participants (5)
-
Benoît Thébaudeau -
Marek Vasut -
Matt Sealey -
Stefano Babic -
stefano babic