From: Jagan Teki jagan@amarulasolutions.com

L2CTLR read/write functions are common to armv7 so, move them in to include/asm/armv7.h and use them where ever it need.

Cc: Tom Warren twarren@nvidia.com Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- Changes for v2: - New patch

arch/arm/include/asm/armv7.h | 21 +++++++++++++++++++++ arch/arm/mach-rockchip/rk3288-board-spl.c | 22 +--------------------- arch/arm/mach-tegra/cache.c | 5 +++-- 3 files changed, 25 insertions(+), 23 deletions(-)

diff --git a/arch/arm/include/asm/armv7.h b/arch/arm/include/asm/armv7.h index a20702e..efc515e 100644 --- a/arch/arm/include/asm/armv7.h +++ b/arch/arm/include/asm/armv7.h @@ -61,6 +61,27 @@ #include <asm/io.h> #include <asm/barriers.h>

+/* read L2 control register (L2CTLR) */ +static inline uint32_t read_l2ctlr(void) +{ + uint32_t val = 0; + + asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); + + return val; +} + +/* write L2 control register (L2CTLR) */ +static inline void write_l2ctlr(uint32_t val) +{ + /* + * Note: L2CTLR can only be written when the L2 memory system + * is idle, ie before the MMU is enabled. + */ + asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory"); + isb(); +} + /* * Workaround for ARM errata # 798870 * Set L2ACTLR[7] to reissue any memory transaction in the L2 that has been diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 6b7bf85..8a1066c 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -13,6 +13,7 @@ #include <malloc.h> #include <ram.h> #include <spl.h> +#include <asm/armv7.h> #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/bootrom.h> @@ -80,27 +81,6 @@ u32 spl_boot_mode(const u32 boot_device) return MMCSD_MODE_RAW; }

-/* read L2 control register (L2CTLR) */ -static inline uint32_t read_l2ctlr(void) -{ - uint32_t val = 0; - - asm volatile ("mrc p15, 1, %0, c9, c0, 2" : "=r" (val)); - - return val; -} - -/* write L2 control register (L2CTLR) */ -static inline void write_l2ctlr(uint32_t val) -{ - /* - * Note: L2CTLR can only be written when the L2 memory system - * is idle, ie before the MMU is enabled. - */ - asm volatile("mcr p15, 1, %0, c9, c0, 2" : : "r" (val) : "memory"); - isb(); -} - static void configure_l2ctlr(void) { uint32_t l2ctlr; diff --git a/arch/arm/mach-tegra/cache.c b/arch/arm/mach-tegra/cache.c index 6dad403..2f3f822 100644 --- a/arch/arm/mach-tegra/cache.c +++ b/arch/arm/mach-tegra/cache.c @@ -7,6 +7,7 @@ /* Tegra cache routines */

#include <common.h> +#include <asm/armv7.h> #include <asm/io.h> #include <asm/arch-tegra/ap.h> #include <asm/arch/gp_padctrl.h> @@ -30,9 +31,9 @@ void config_cache(void) * Systems with an architectural L2 cache must not use the PL310. * Config L2CTLR here for a data RAM latency of 3 cycles. */ - asm("mrc p15, 1, %0, c9, c0, 2" : : "r" (reg)); + reg = read_l2ctlr(); reg &= ~7; reg |= 2; - asm("mcr p15, 1, %0, c9, c0, 2" : : "r" (reg)); + write_l2ctlr(reg); } #endif

From: Jagan Teki jagan@amarulasolutions.com

configure_l2ctlr will be shared between SPL and TPL so move them into asm/arch/sys_proto.h

Signed-off-by: Jagan Teki jagan@amarulasolutions.com --- Changes for v2: - New patch

arch/arm/include/asm/arch-rockchip/sys_proto.h | 23 +++++++++++++++++++++++ arch/arm/mach-rockchip/rk3288-board-spl.c | 21 +-------------------- 2 files changed, 24 insertions(+), 20 deletions(-)

diff --git a/arch/arm/include/asm/arch-rockchip/sys_proto.h b/arch/arm/include/asm/arch-rockchip/sys_proto.h index 35423e1..e428d59 100644 --- a/arch/arm/include/asm/arch-rockchip/sys_proto.h +++ b/arch/arm/include/asm/arch-rockchip/sys_proto.h @@ -7,4 +7,27 @@ #ifndef _ASM_ARCH_SYS_PROTO_H #define _ASM_ARCH_SYS_PROTO_H

+#ifdef CONFIG_ROCKCHIP_RK3288 +#include <asm/armv7.h> + +static void configure_l2ctlr(void) +{ + uint32_t l2ctlr; + + l2ctlr = read_l2ctlr(); + l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ + + /* + * Data RAM write latency: 2 cycles + * Data RAM read latency: 2 cycles + * Data RAM setup latency: 1 cycle + * Tag RAM write latency: 1 cycle + * Tag RAM read latency: 1 cycle + * Tag RAM setup latency: 1 cycle + */ + l2ctlr |= (1 << 3 | 1 << 0); + write_l2ctlr(l2ctlr); +} +#endif /* CONFIG_ROCKCHIP_RK3288 */ + #endif /* _ASM_ARCH_SYS_PROTO_H */ diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 8a1066c..23af653 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -13,7 +13,6 @@ #include <malloc.h> #include <ram.h> #include <spl.h> -#include <asm/armv7.h> #include <asm/gpio.h> #include <asm/io.h> #include <asm/arch/bootrom.h> @@ -21,6 +20,7 @@ #include <asm/arch/hardware.h> #include <asm/arch/periph.h> #include <asm/arch/sdram.h> +#include <asm/arch/sys_proto.h> #include <asm/arch/timer.h> #include <dm/pinctrl.h> #include <dm/root.h> @@ -81,25 +81,6 @@ u32 spl_boot_mode(const u32 boot_device) return MMCSD_MODE_RAW; }

-static void configure_l2ctlr(void) -{ - uint32_t l2ctlr; - - l2ctlr = read_l2ctlr(); - l2ctlr &= 0xfffc0000; /* clear bit0~bit17 */ - - /* - * Data RAM write latency: 2 cycles - * Data RAM read latency: 2 cycles - * Data RAM setup latency: 1 cycle - * Tag RAM write latency: 1 cycle - * Tag RAM read latency: 1 cycle - * Tag RAM setup latency: 1 cycle - */ - l2ctlr |= (1 << 3 | 1 << 0); - write_l2ctlr(l2ctlr); -} - #ifdef CONFIG_SPL_MMC_SUPPORT static int configure_emmc(struct udevice *pinctrl) {

From: Jagan Teki jagan@amarulasolutions.com

Since the size of SPL can't be exceeded 0x8000 bytes in RK3288, it is not possible add new SPL features like Falcon mode or etc.

So add TPL stage so-that adding new features to SPL is possible. - TPL: DRAM init, clocks - SPL: MMC, falcon, etc

Signed-off-by: Jagan Teki jagan@amarulasolutions.com Reviewed-by: Philipp Tomsich philipp.tomsich@theobroma-systems.com --- Changes for v2: - Drop console output from commit message - Updated licence note - Moved read/write L2CTRL and configure_l2ctlr to common - Moved debug header in include files list - Moved preprocessor macro to top Note: Idea is not to build this in SPL when TPL enabled, so CONFIG_SUPPORT_TPL work that case.

arch/arm/mach-rockchip/Makefile | 1 + arch/arm/mach-rockchip/rk3288-board-spl.c | 3 ++ arch/arm/mach-rockchip/rk3288-board-tpl.c | 84 +++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3288/Kconfig | 16 ++++++ configs/vyasa-rk3288_defconfig | 3 ++ doc/README.rockchip | 18 +++++++ include/configs/rk3288_common.h | 6 ++- 7 files changed, 130 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-rockchip/rk3288-board-tpl.c

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 79e9704..daafc8d 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -12,6 +12,7 @@ obj-spl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o obj-tpl-$(CONFIG_ROCKCHIP_BROM_HELPER) += bootrom.o save_boot_param.o

obj-tpl-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o +obj-tpl-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-tpl.o obj-tpl-$(CONFIG_ROCKCHIP_RK3368) += rk3368-board-tpl.o

obj-spl-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o diff --git a/arch/arm/mach-rockchip/rk3288-board-spl.c b/arch/arm/mach-rockchip/rk3288-board-spl.c index 23af653..5239cbc 100644 --- a/arch/arm/mach-rockchip/rk3288-board-spl.c +++ b/arch/arm/mach-rockchip/rk3288-board-spl.c @@ -204,12 +204,15 @@ void board_init_f(ulong dummy) } #endif

+#if !defined(CONFIG_SUPPORT_TPL) debug("\nspl:init dram\n"); ret = uclass_get_device(UCLASS_RAM, 0, &dev); if (ret) { debug("DRAM init failed: %d\n", ret); return; } +#endif + #if CONFIG_IS_ENABLED(ROCKCHIP_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) back_to_bootrom(); #endif diff --git a/arch/arm/mach-rockchip/rk3288-board-tpl.c b/arch/arm/mach-rockchip/rk3288-board-tpl.c new file mode 100644 index 0000000..3d08b5b --- /dev/null +++ b/arch/arm/mach-rockchip/rk3288-board-tpl.c @@ -0,0 +1,84 @@ +/* + * Copyright (C) 2017 Amarula Solutions + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <ram.h> +#include <spl.h> +#include <version.h> +#include <asm/io.h> +#include <asm/arch/bootrom.h> +#include <asm/arch/clock.h> +#include <asm/arch/grf_rk3288.h> +#include <asm/arch/periph.h> +#include <asm/arch/pmu_rk3288.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/timer.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define GRF_BASE 0xff770000 +void board_init_f(ulong dummy) +{ + struct udevice *dev; + int ret; + + /* Example code showing how to enable the debug UART on RK3288 */ + /* Enable early UART on the RK3288 */ + struct rk3288_grf * const grf = (void *)GRF_BASE; + + rk_clrsetreg(&grf->gpio7ch_iomux, GPIO7C7_MASK << GPIO7C7_SHIFT | + GPIO7C6_MASK << GPIO7C6_SHIFT, + GPIO7C7_UART2DBG_SOUT << GPIO7C7_SHIFT | + GPIO7C6_UART2DBG_SIN << GPIO7C6_SHIFT); + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + debug_uart_init(); + + ret = spl_early_init(); + if (ret) { + debug("spl_early_init() failed: %d\n", ret); + hang(); + } + + rockchip_timer_init(); + configure_l2ctlr(); + + ret = rockchip_get_clk(&dev); + if (ret) { + debug("CLK init failed: %d\n", ret); + return; + } + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return; + } +} + +void board_return_to_bootrom(void) +{ + back_to_bootrom(); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_BOOTROM; +} + +void spl_board_init(void) +{ + puts("\nU-Boot TPL " PLAIN_VERSION " (" U_BOOT_DATE " - " \ + U_BOOT_TIME ")\n"); +} diff --git a/arch/arm/mach-rockchip/rk3288/Kconfig b/arch/arm/mach-rockchip/rk3288/Kconfig index 4ad2940..6beb26f 100644 --- a/arch/arm/mach-rockchip/rk3288/Kconfig +++ b/arch/arm/mach-rockchip/rk3288/Kconfig @@ -87,6 +87,22 @@ config TARGET_POPMETAL_RK3288 config TARGET_VYASA_RK3288 bool "Vyasa-RK3288" select BOARD_LATE_INIT + select TPL + select SUPPORT_TPL + select TPL_DM + select TPL_REGMAP + select TPL_SYSCON + select TPL_CLK + select TPL_RAM + select TPL_OF_PLATDATA + select TPL_OF_CONTROL + select TPL_BOOTROM_SUPPORT + select TPL_NEEDS_SEPARATE_TEXT_BASE if SPL + select ROCKCHIP_BROM_HELPER + select TPL_DRIVERS_MISC_SUPPORT + select TPL_LIBCOMMON_SUPPORT + select TPL_LIBGENERIC_SUPPORT + select TPL_SERIAL_SUPPORT help Vyasa is a RK3288-based development board with 2 USB ports, HDMI, VGA, micro-SD card, audio, WiFi and Gigabit Ethernet, It diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index 7db7b0b..7bd6068 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -1,8 +1,11 @@ CONFIG_ARM=y +# CONFIG_SPL_USE_ARCH_MEMCPY is not set +# CONFIG_SPL_USE_ARCH_MEMSET is not set CONFIG_ARCH_ROCKCHIP=y CONFIG_SYS_MALLOC_F_LEN=0x2000 CONFIG_ROCKCHIP_RK3288=y CONFIG_TARGET_VYASA_RK3288=y +CONFIG_TPL_TEXT_BASE=0xff704004 CONFIG_SPL_STACK_R_ADDR=0x80000 CONFIG_DEFAULT_DEVICE_TREE="rk3288-vyasa" CONFIG_DEBUG_UART=y diff --git a/doc/README.rockchip b/doc/README.rockchip index 12fec38..4b7be0b 100644 --- a/doc/README.rockchip +++ b/doc/README.rockchip @@ -150,6 +150,24 @@ Note: rk3036 SDMMC and debug uart use the same iomux, so if you boot from SD, th debug uart must be disabled

+Booting from an SD card on RK3288 with TPL +========================================== + +Since the size of SPL can't be exceeded 0x8000 bytes in RK3288, it is not possible add +new SPL features like Falcon mode or etc. + +So introduce TPL so-that adding new features to SPL is possible because now TPL should +run minimal with code like DDR, clock etc and rest of new features in SPL. + +As of now TPL is added on Vyasa-RK3288 board. + +To write an image that boots from an SD card (assumed to be /dev/mmcblk0): + + ./tools/mkimage -n rk3288 -T rksd -d ./tpl/u-boot-tpl.bin out && + cat ./spl/u-boot-spl-dtb.bin >> out && + sudo dd if=out of=/dev/mmcblk0 seek=64 && + sudo dd if=u-boot-dtb.img of=/dev/mmcblk0 seek=256 + Booting from an SD card on RK3188 =================================

diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index e9e3c40..34f2558 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -32,7 +32,11 @@ #define CONFIG_SYS_INIT_SP_ADDR 0x00100000 #define CONFIG_SYS_LOAD_ADDR 0x00800800 #define CONFIG_SPL_STACK 0xff718000 -#define CONFIG_SPL_TEXT_BASE 0xff704004 +#if defined(CONFIG_SPL_BUILD) && defined(CONFIG_TPL_BOOTROM_SUPPORT) +# define CONFIG_SPL_TEXT_BASE 0x0 +#else +# define CONFIG_SPL_TEXT_BASE 0xff704004 +#endif

/* MMC/SD IP block */ #define CONFIG_BOUNCE_BUFFER