[U-Boot-Users] [PATCH 0/12] 85xx: various fixes for TQM85xx and support for TQM8548

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Re: [U-Boot-Users] uboot version...

Wolfgang Grandegger

28 May 2008 28 May '08

8:12 p.m.

This series of patches fixes various issues with TQM85xx modules and adds support for TQM8548 modules from TQ Components GmbH (http://www.tqc.de).

Note: The patches rely on "[PATCH] TQM: move TQM boards to board/tqc" sent a few minutes ago to this list.

Wolfgang.

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Wolfgang Grandegger

28 May 28 May

8:12 p.m.

New subject: [U-Boot-Users] [PATCH] MPC85xx: Beatify boot output of L2 cache configuration

The boot output is now aligned poperly with other boot output lines, e.g.:

FLASH: 128 MB L2: 512 KB enabled

Signed-off-by: Wolfgang Grandegger wg@grandegger.com --- cpu/mpc85xx/cpu.c | 2 +- cpu/mpc85xx/cpu_init.c | 18 ++++++++++-------- 2 files changed, 11 insertions(+), 9 deletions(-)

diff --git a/cpu/mpc85xx/cpu.c b/cpu/mpc85xx/cpu.c index 9873383..274b486 100644 --- a/cpu/mpc85xx/cpu.c +++ b/cpu/mpc85xx/cpu.c @@ -159,7 +159,7 @@ int checkcpu (void) }

#ifdef CONFIG_CPM2 - printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000); + printf("CPM: %lu Mhz\n", sysinfo.freqSystemBus / 1000000); #endif

puts("L1: D-cache 32 kB enabled\n I-cache 32 kB enabled\n"); diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index e3240b5..0fb36c4 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -265,6 +265,8 @@ int cpu_init_r(void) #endif #endif

+ puts ("L2: "); + #if defined(CONFIG_L2_CACHE) volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR; volatile uint cache_ctl; @@ -281,17 +283,17 @@ int cpu_init_r(void) case 0x20000000: if (ver == SVR_8548 || ver == SVR_8548_E || ver == SVR_8544 || ver == SVR_8568_E) { - printf ("L2 cache 512KB:"); + puts ("512 KB "); /* set L2E=1, L2I=1, & L2SRAM=0 */ cache_ctl = 0xc0000000; } else { - printf ("L2 cache 256KB:"); + puts("256 KB "); /* set L2E=1, L2I=1, & L2BLKSZ=2 (256 Kbyte) */ cache_ctl = 0xc8000000; } break; case 0x10000000: - printf ("L2 cache 256KB:"); + puts("256 KB "); if (ver == SVR_8544 || ver == SVR_8544_E) { cache_ctl = 0xc0000000; /* set L2E=1, L2I=1, & L2SRAM=0 */ } @@ -299,18 +301,18 @@ int cpu_init_r(void) case 0x30000000: case 0x00000000: default: - printf ("L2 cache unknown size (0x%08x)\n", cache_ctl); + printf(" unknown size (0x%08x)\n", cache_ctl); return -1; }

if (l2cache->l2ctl & 0x80000000) { - printf(" already enabled."); + puts("already enabled"); l2srbar = l2cache->l2srbar0; #ifdef CFG_INIT_L2_ADDR if (l2cache->l2ctl & 0x00010000 && l2srbar >= CFG_FLASH_BASE) { l2srbar = CFG_INIT_L2_ADDR; l2cache->l2srbar0 = l2srbar; - printf(" Moving to 0x%08x", CFG_INIT_L2_ADDR); + printf("moving to 0x%08x", CFG_INIT_L2_ADDR); } #endif /* CFG_INIT_L2_ADDR */ puts("\n"); @@ -318,10 +320,10 @@ int cpu_init_r(void) asm("msync;isync"); l2cache->l2ctl = cache_ctl; /* invalidate & enable */ asm("msync;isync"); - printf(" enabled\n"); + puts("enabled\n"); } #else - printf("L2 cache: disabled\n"); + puts("disabled\n"); #endif #ifdef CONFIG_QE uint qe_base = CFG_IMMR + 0x00080000; /* QE immr base */

-- 1.5.2.2

Wolfgang Grandegger

8:12 p.m.

New subject: [U-Boot-Users] [PATCH] TQM85xx: Various coding style fixes

Signed-off-by: Wolfgang Grandegger wg@grandegger.com --- board/tqc/tqm85xx/law.c | 12 +- board/tqc/tqm85xx/sdram.c | 56 ++++---- board/tqc/tqm85xx/tlb.c | 98 +++++++------ board/tqc/tqm85xx/tqm85xx.c | 330 +++++++++++++++++++++--------------------- include/configs/TQM85xx.h | 88 ++++++------ 5 files changed, 293 insertions(+), 291 deletions(-)

diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c index 224af6c..d937700 100644 --- a/board/tqc/tqm85xx/law.c +++ b/board/tqc/tqm85xx/law.c @@ -44,11 +44,11 @@ */

struct law_entry law_table[] = { - SET_LAW_ENTRY(1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), - SET_LAW_ENTRY(2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), - SET_LAW_ENTRY(4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY(5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW_ENTRY (1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), + SET_LAW_ENTRY (2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY (3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), + SET_LAW_ENTRY (4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), };

-int num_law_entries = ARRAY_SIZE(law_table); +int num_law_entries = ARRAY_SIZE (law_table); diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c index 788a48c..413567e 100644 --- a/board/tqc/tqm85xx/sdram.c +++ b/board/tqc/tqm85xx/sdram.c @@ -21,7 +21,6 @@ * MA 02111-1307 USA */

- #include <common.h> #include <asm/processor.h> #include <asm/immap_85xx.h> @@ -39,12 +38,12 @@ sdram_conf_t ddr_cs_conf[] = { {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */ {(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */ {(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */ - {(64 << 20), 0x80000001}, /* 64MB, 12x9(4) */ + {( 64 << 20), 0x80000001}, /* 64MB, 12x9(4) */ };

#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))

-int cas_latency(void); +int cas_latency (void);

/* * Autodetect onboard DDR SDRAM on 85xx platforms @@ -53,7 +52,7 @@ int cas_latency(void); * so this should be extended for other future boards * using this routine! */ -long int sdram_setup(int casl) +long int sdram_setup (int casl) { int i; volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); @@ -92,17 +91,18 @@ long int sdram_setup(int casl) ddr->sdram_interval = 0x05160100; /* autocharge,no open page */ ddr->err_disable = 0x0000000D;

- asm ("sync;isync;msync"); - udelay(1000); + asm ("sync; isync; msync"); + udelay (1000);

ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */ asm ("sync; isync; msync"); - udelay(1000); + udelay (1000);

- for (i=0; i<N_DDR_CS_CONF; i++) { + for (i = 0; i < N_DDR_CS_CONF; i++) { ddr->cs0_config = ddr_cs_conf[i].reg;

- if (get_ram_size(0, ddr_cs_conf[i].size) == ddr_cs_conf[i].size) { + if (get_ram_size (0, ddr_cs_conf[i].size) == + ddr_cs_conf[i].size) { /* * OK, size detected -> all done */ @@ -110,30 +110,30 @@ long int sdram_setup(int casl) } }

- return 0; /* nothing found ! */ + return 0; /* nothing found ! */ }

-void board_add_ram_info(int use_default) +void board_add_ram_info (int use_default) { int casl;

if (use_default) casl = CONFIG_DDR_DEFAULT_CL; else - casl = cas_latency(); + casl = cas_latency ();

- puts(" (CL="); + puts (" (CL="); switch (casl) { case 20: - puts("2)"); + puts ("2)"); break;

case 25: - puts("2.5)"); + puts ("2.5)"); break;

case 30: - puts("3)"); + puts ("3)"); break; } } @@ -149,7 +149,7 @@ long int initdram (int board_type) */ { volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); - int i,x; + int i, x;

x = 10;

@@ -157,32 +157,32 @@ long int initdram (int board_type) * Work around to stabilize DDR DLL */ gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); + asm ("sync; isync; msync"); udelay (200); while (gur->ddrdllcr != 0x81000100) { gur->devdisr = gur->devdisr | 0x00010000; - asm("sync;isync;msync"); - for (i=0; i<x; i++) + asm ("sync; isync; msync"); + for (i = 0; i < x; i++) ; gur->devdisr = gur->devdisr & 0xfff7ffff; - asm("sync;isync;msync"); + asm ("sync; isync; msync"); x++; } } #endif

- casl = cas_latency(); - dram_size = sdram_setup(casl); + casl = cas_latency (); + dram_size = sdram_setup (casl); if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) { /* * Try again with default CAS latency */ - puts("Problem with CAS lantency"); - board_add_ram_info(1); - puts(", using default CL!\n"); + puts ("Problem with CAS lantency"); + board_add_ram_info (1); + puts (", using default CL!\n"); casl = CONFIG_DDR_DEFAULT_CL; - dram_size = sdram_setup(casl); - puts(" "); + dram_size = sdram_setup (casl); + puts (" "); }

return dram_size; diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c index ad26cae..3e29062 100644 --- a/board/tqc/tqm85xx/tlb.c +++ b/board/tqc/tqm85xx/tlb.c @@ -28,87 +28,93 @@

struct fsl_e_tlb_entry tlb_table[] = { /* TLB 0 - for temp stack in cache */ - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 4 * 1024 , CFG_INIT_RAM_ADDR + 4 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 8 * 1024 , CFG_INIT_RAM_ADDR + 8 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - SET_TLB_ENTRY(0, CFG_INIT_RAM_ADDR + 12 * 1024 , CFG_INIT_RAM_ADDR + 12 * 1024, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 0, BOOKE_PAGESZ_4K, 0), - + SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR, CFG_INIT_RAM_ADDR, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 4 * 1024, + CFG_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 8 * 1024, + CFG_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY (0, CFG_INIT_RAM_ADDR + 12 * 1024, + CFG_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX | MAS3_SW | MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0),

/* * TLB 0, 1: 128M Non-cacheable, guarded * 0xf8000000 128M FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CFG_FLASH_BASE, CFG_FLASH_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_64M, 1), - SET_TLB_ENTRY(1, CFG_FLASH_BASE + 0x4000000, CFG_FLASH_BASE + 0x4000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_64M, 1), + SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 1, BOOKE_PAGESZ_64M, 1), + SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x4000000, + CFG_FLASH_BASE + 0x4000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 0, BOOKE_PAGESZ_64M, 1),

/* * TLB 2: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), + SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1),

/* * TLB 3: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ - SET_TLB_ENTRY(1, CFG_PCI1_MEM_PHYS + 0x10000000, CFG_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_256M, 1), + SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000, + CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1),

/* * TLB 4: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_256M, 1), + SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1),

/* * TLB 5: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ - SET_TLB_ENTRY(1, CFG_RIO_MEM_BASE + 0x10000000, CFG_RIO_MEM_BASE + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 5, BOOKE_PAGESZ_256M, 1), + SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE + 0x10000000, + CFG_RIO_MEM_BASE + 0x10000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1),

/* - * TLB 6: 64M Non-cacheable, guarded - * 0xe000_0000 1M CCSRBAR - * 0xe200_0000 16M PCI1 IO + * TLB 6: 64M Non-cacheable, guarded + * 0xe0000000 1M CCSRBAR + * 0xe2000000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_64M, 1), + SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 6, BOOKE_PAGESZ_64M, 1),

/* - * TLB 7+8: 512M DDR, cache disabled (needed for memory test) - * 0x00000000 512M DDR System memory + * TLB 7+8: 512M DDR, cache disabled (needed for memory test) + * 0x00000000 512M DDR System memory * Without SPD EEPROM configured DDR, this must be setup manually. * Make sure the TLB count at the top of this table is correct. * Likely it needs to be increased by two for these entries. */ - SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_256M, 1), + SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 7, BOOKE_PAGESZ_256M, 1),

- SET_TLB_ENTRY(1, CFG_DDR_SDRAM_BASE + 0x10000000, CFG_DDR_SDRAM_BASE + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_256M, 1), + SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000, + CFG_DDR_SDRAM_BASE + 0x10000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 8, BOOKE_PAGESZ_256M, 1), };

-int num_tlb_entries = ARRAY_SIZE(tlb_table); +int num_tlb_entries = ARRAY_SIZE (tlb_table); diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 8fa0162..31364d3 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -42,7 +42,7 @@ void local_bus_init (void); ulong flash_get_size (ulong base, int banknum);

#ifdef CONFIG_PS2MULT -void ps2mult_early_init(void); +void ps2mult_early_init (void); #endif

#ifdef CONFIG_CPM2 @@ -55,149 +55,149 @@ void ps2mult_early_init(void);

const iop_conf_t iop_conf_tab[4][32] = {

- /* Port A configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PA31 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII COL */ - /* PA30 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII CRS */ - /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_ER */ - /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 MII TX_EN */ - /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_DV */ - /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 MII RX_ER */ - /* PA25 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[0] */ - /* PA24 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[1] */ - /* PA23 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[2] */ - /* PA22 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXD[3] */ - /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[3] */ - /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[2] */ - /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[1] */ - /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 MII TxD[0] */ - /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[0] */ - /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[1] */ - /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[2] */ - /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 MII RxD[3] */ - /* PA13 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[3] */ - /* PA12 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[2] */ - /* PA11 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[1] */ - /* PA10 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXD[0] */ - /* PA9 */ { 0, 1, 1, 1, 0, 0 }, /* FCC1 L1TXD */ - /* PA8 */ { 0, 1, 1, 0, 0, 0 }, /* FCC1 L1RXD */ - /* PA7 */ { 0, 0, 0, 1, 0, 0 }, /* PA7 */ - /* PA6 */ { 0, 1, 1, 1, 0, 0 }, /* TDM A1 L1RSYNC */ - /* PA5 */ { 0, 0, 0, 1, 0, 0 }, /* PA5 */ - /* PA4 */ { 0, 0, 0, 1, 0, 0 }, /* PA4 */ - /* PA3 */ { 0, 0, 0, 1, 0, 0 }, /* PA3 */ - /* PA2 */ { 0, 0, 0, 1, 0, 0 }, /* PA2 */ - /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* FREERUN */ - /* PA0 */ { 0, 0, 0, 1, 0, 0 } /* PA0 */ - }, - - /* Port B configuration */ - { /* conf ppar psor pdir podr pdat */ - /* PB31 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TX_ER */ - /* PB30 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_DV */ - /* PB29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC2 MII TX_EN */ - /* PB28 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_ER */ - /* PB27 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII COL */ - /* PB26 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII CRS */ - /* PB25 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[3] */ - /* PB24 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[2] */ - /* PB23 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[1] */ - /* PB22 */ { 1, 1, 0, 1, 0, 0 }, /* FCC2 MII TxD[0] */ - /* PB21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[0] */ - /* PB20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[1] */ - /* PB19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[2] */ - /* PB18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RxD[3] */ - /* PB17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_DIV */ - /* PB16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RX_ERR */ - /* PB15 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_ERR */ - /* PB14 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TX_EN */ - /* PB13 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:COL */ - /* PB12 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:CRS */ - /* PB11 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB10 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB9 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB8 */ { 1, 1, 0, 0, 0, 0 }, /* FCC3:RXD */ - /* PB7 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB6 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB5 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB4 */ { 1, 1, 0, 1, 0, 0 }, /* FCC3:TXD */ - /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - }, - - /* Port C */ - { /* conf ppar psor pdir podr pdat */ - /* PC31 */ { 0, 0, 0, 1, 0, 0 }, /* PC31 */ - /* PC30 */ { 0, 0, 0, 1, 0, 0 }, /* PC30 */ - /* PC29 */ { 0, 1, 1, 0, 0, 0 }, /* SCC1 EN *CLSN */ - /* PC28 */ { 0, 0, 0, 1, 0, 0 }, /* PC28 */ - /* PC27 */ { 0, 0, 0, 1, 0, 0 }, /* UART Clock in */ - /* PC26 */ { 0, 0, 0, 1, 0, 0 }, /* PC26 */ - /* PC25 */ { 0, 0, 0, 1, 0, 0 }, /* PC25 */ - /* PC24 */ { 0, 0, 0, 1, 0, 0 }, /* PC24 */ - /* PC23 */ { 0, 1, 0, 1, 0, 0 }, /* ATMTFCLK */ - /* PC22 */ { 0, 1, 0, 0, 0, 0 }, /* ATMRFCLK */ - /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RXCLK */ - /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN TXCLK */ - /* PC19 */ { 1, 1, 0, 0, 0, 0 }, /* FCC2 MII RX_CLK CLK13 */ - /* PC18 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK14) */ - /* PC17 */ { 1, 1, 0, 0, 0, 0 }, /* PC17 */ - /* PC16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC Tx Clock (CLK16) */ - /* PC15 */ { 0, 1, 0, 0, 0, 0 }, /* PC15 */ - /* PC14 */ { 0, 1, 0, 0, 0, 0 }, /* SCC1 EN *CD */ - /* PC13 */ { 0, 1, 0, 0, 0, 0 }, /* PC13 */ - /* PC12 */ { 0, 1, 0, 1, 0, 0 }, /* PC12 */ - /* PC11 */ { 0, 0, 0, 1, 0, 0 }, /* LXT971 transmit control */ - /* PC10 */ { 0, 0, 0, 1, 0, 0 }, /* FETHMDC */ - /* PC9 */ { 0, 0, 0, 0, 0, 0 }, /* FETHMDIO */ - /* PC8 */ { 0, 0, 0, 1, 0, 0 }, /* PC8 */ - /* PC7 */ { 0, 0, 0, 1, 0, 0 }, /* PC7 */ - /* PC6 */ { 0, 0, 0, 1, 0, 0 }, /* PC6 */ - /* PC5 */ { 0, 0, 0, 1, 0, 0 }, /* PC5 */ - /* PC4 */ { 0, 0, 0, 1, 0, 0 }, /* PC4 */ - /* PC3 */ { 0, 0, 0, 1, 0, 0 }, /* PC3 */ - /* PC2 */ { 0, 0, 0, 1, 0, 1 }, /* ENET FDE */ - /* PC1 */ { 0, 0, 0, 1, 0, 0 }, /* ENET DSQE */ - /* PC0 */ { 0, 0, 0, 1, 0, 0 }, /* ENET LBK */ - }, - - /* Port D */ - { /* conf ppar psor pdir podr pdat */ - /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 EN RxD */ - /* PD30 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 EN TxD */ - /* PD29 */ { 1, 1, 0, 1, 0, 0 }, /* SCC1 EN TENA */ - /* PD28 */ { 1, 1, 0, 0, 0, 0 }, /* PD28 */ - /* PD27 */ { 1, 1, 0, 1, 0, 0 }, /* PD27 */ - /* PD26 */ { 1, 1, 0, 1, 0, 0 }, /* PD26 */ - /* PD25 */ { 0, 0, 0, 1, 0, 0 }, /* PD25 */ - /* PD24 */ { 0, 0, 0, 1, 0, 0 }, /* PD24 */ - /* PD23 */ { 0, 0, 0, 1, 0, 0 }, /* PD23 */ - /* PD22 */ { 0, 0, 0, 1, 0, 0 }, /* PD22 */ - /* PD21 */ { 0, 0, 0, 1, 0, 0 }, /* PD21 */ - /* PD20 */ { 0, 0, 0, 1, 0, 0 }, /* PD20 */ - /* PD19 */ { 0, 0, 0, 1, 0, 0 }, /* PD19 */ - /* PD18 */ { 0, 0, 0, 1, 0, 0 }, /* PD18 */ - /* PD17 */ { 0, 1, 0, 0, 0, 0 }, /* FCC1 ATMRXPRTY */ - /* PD16 */ { 0, 1, 0, 1, 0, 0 }, /* FCC1 ATMTXPRTY */ - /* PD15 */ { 0, 1, 1, 0, 1, 0 }, /* I2C SDA */ - /* PD14 */ { 0, 0, 0, 1, 0, 0 }, /* LED */ - /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ - /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ - /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ - /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ - /* PD9 */ { 0, 1, 0, 1, 0, 0 }, /* SMC1 TXD */ - /* PD8 */ { 0, 1, 0, 0, 0, 0 }, /* SMC1 RXD */ - /* PD7 */ { 0, 0, 0, 1, 0, 1 }, /* PD7 */ - /* PD6 */ { 0, 0, 0, 1, 0, 1 }, /* PD6 */ - /* PD5 */ { 0, 0, 0, 1, 0, 1 }, /* PD5 */ - /* PD4 */ { 0, 0, 0, 1, 0, 1 }, /* PD4 */ - /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* pin doesn't exist */ - /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* pin doesn't exist */ - } + /* Port A: conf, ppar, psor, pdir, podr, pdat */ + { + {1, 1, 1, 0, 0, 0}, /* PA31: FCC1 MII COL */ + {1, 1, 1, 0, 0, 0}, /* PA30: FCC1 MII CRS */ + {1, 1, 1, 1, 0, 0}, /* PA29: FCC1 MII TX_ER */ + {1, 1, 1, 1, 0, 0}, /* PA28: FCC1 MII TX_EN */ + {1, 1, 1, 0, 0, 0}, /* PA27: FCC1 MII RX_DV */ + {1, 1, 1, 0, 0, 0}, /* PA26: FCC1 MII RX_ER */ + {0, 1, 0, 1, 0, 0}, /* PA25: FCC1 ATMTXD[0] */ + {0, 1, 0, 1, 0, 0}, /* PA24: FCC1 ATMTXD[1] */ + {0, 1, 0, 1, 0, 0}, /* PA23: FCC1 ATMTXD[2] */ + {0, 1, 0, 1, 0, 0}, /* PA22: FCC1 ATMTXD[3] */ + {1, 1, 0, 1, 0, 0}, /* PA21: FCC1 MII TxD[3] */ + {1, 1, 0, 1, 0, 0}, /* PA20: FCC1 MII TxD[2] */ + {1, 1, 0, 1, 0, 0}, /* PA19: FCC1 MII TxD[1] */ + {1, 1, 0, 1, 0, 0}, /* PA18: FCC1 MII TxD[0] */ + {1, 1, 0, 0, 0, 0}, /* PA17: FCC1 MII RxD[0] */ + {1, 1, 0, 0, 0, 0}, /* PA16: FCC1 MII RxD[1] */ + {1, 1, 0, 0, 0, 0}, /* PA15: FCC1 MII RxD[2] */ + {1, 1, 0, 0, 0, 0}, /* PA14: FCC1 MII RxD[3] */ + {0, 1, 0, 0, 0, 0}, /* PA13: FCC1 ATMRXD[3] */ + {0, 1, 0, 0, 0, 0}, /* PA12: FCC1 ATMRXD[2] */ + {0, 1, 0, 0, 0, 0}, /* PA11: FCC1 ATMRXD[1] */ + {0, 1, 0, 0, 0, 0}, /* PA10: FCC1 ATMRXD[0] */ + {0, 1, 1, 1, 0, 0}, /* PA9 : FCC1 L1TXD */ + {0, 1, 1, 0, 0, 0}, /* PA8 : FCC1 L1RXD */ + {0, 0, 0, 1, 0, 0}, /* PA7 : PA7 */ + {0, 1, 1, 1, 0, 0}, /* PA6 : TDM A1 L1RSYNC */ + {0, 0, 0, 1, 0, 0}, /* PA5 : PA5 */ + {0, 0, 0, 1, 0, 0}, /* PA4 : PA4 */ + {0, 0, 0, 1, 0, 0}, /* PA3 : PA3 */ + {0, 0, 0, 1, 0, 0}, /* PA2 : PA2 */ + {0, 0, 0, 0, 0, 0}, /* PA1 : FREERUN */ + {0, 0, 0, 1, 0, 0} /* PA0 : PA0 */ + }, + + /* Port B: conf, ppar, psor, pdir, podr, pdat */ + { + {1, 1, 0, 1, 0, 0}, /* PB31: FCC2 MII TX_ER */ + {1, 1, 0, 0, 0, 0}, /* PB30: FCC2 MII RX_DV */ + {1, 1, 1, 1, 0, 0}, /* PB29: FCC2 MII TX_EN */ + {1, 1, 0, 0, 0, 0}, /* PB28: FCC2 MII RX_ER */ + {1, 1, 0, 0, 0, 0}, /* PB27: FCC2 MII COL */ + {1, 1, 0, 0, 0, 0}, /* PB26: FCC2 MII CRS */ + {1, 1, 0, 1, 0, 0}, /* PB25: FCC2 MII TxD[3] */ + {1, 1, 0, 1, 0, 0}, /* PB24: FCC2 MII TxD[2] */ + {1, 1, 0, 1, 0, 0}, /* PB23: FCC2 MII TxD[1] */ + {1, 1, 0, 1, 0, 0}, /* PB22: FCC2 MII TxD[0] */ + {1, 1, 0, 0, 0, 0}, /* PB21: FCC2 MII RxD[0] */ + {1, 1, 0, 0, 0, 0}, /* PB20: FCC2 MII RxD[1] */ + {1, 1, 0, 0, 0, 0}, /* PB19: FCC2 MII RxD[2] */ + {1, 1, 0, 0, 0, 0}, /* PB18: FCC2 MII RxD[3] */ + {1, 1, 0, 0, 0, 0}, /* PB17: FCC3:RX_DIV */ + {1, 1, 0, 0, 0, 0}, /* PB16: FCC3:RX_ERR */ + {1, 1, 0, 1, 0, 0}, /* PB15: FCC3:TX_ERR */ + {1, 1, 0, 1, 0, 0}, /* PB14: FCC3:TX_EN */ + {1, 1, 0, 0, 0, 0}, /* PB13: FCC3:COL */ + {1, 1, 0, 0, 0, 0}, /* PB12: FCC3:CRS */ + {1, 1, 0, 0, 0, 0}, /* PB11: FCC3:RXD */ + {1, 1, 0, 0, 0, 0}, /* PB10: FCC3:RXD */ + {1, 1, 0, 0, 0, 0}, /* PB9 : FCC3:RXD */ + {1, 1, 0, 0, 0, 0}, /* PB8 : FCC3:RXD */ + {1, 1, 0, 1, 0, 0}, /* PB7 : FCC3:TXD */ + {1, 1, 0, 1, 0, 0}, /* PB6 : FCC3:TXD */ + {1, 1, 0, 1, 0, 0}, /* PB5 : FCC3:TXD */ + {1, 1, 0, 1, 0, 0}, /* PB4 : FCC3:TXD */ + {0, 0, 0, 0, 0, 0}, /* PB3 : pin doesn't exist */ + {0, 0, 0, 0, 0, 0}, /* PB2 : pin doesn't exist */ + {0, 0, 0, 0, 0, 0}, /* PB1 : pin doesn't exist */ + {0, 0, 0, 0, 0, 0} /* PB0 : pin doesn't exist */ + }, + + /* Port C: conf, ppar, psor, pdir, podr, pdat */ + { + {0, 0, 0, 1, 0, 0}, /* PC31: PC31 */ + {0, 0, 0, 1, 0, 0}, /* PC30: PC30 */ + {0, 1, 1, 0, 0, 0}, /* PC29: SCC1 EN *CLSN */ + {0, 0, 0, 1, 0, 0}, /* PC28: PC28 */ + {0, 0, 0, 1, 0, 0}, /* PC27: UART Clock in */ + {0, 0, 0, 1, 0, 0}, /* PC26: PC26 */ + {0, 0, 0, 1, 0, 0}, /* PC25: PC25 */ + {0, 0, 0, 1, 0, 0}, /* PC24: PC24 */ + {0, 1, 0, 1, 0, 0}, /* PC23: ATMTFCLK */ + {0, 1, 0, 0, 0, 0}, /* PC22: ATMRFCLK */ + {1, 1, 0, 0, 0, 0}, /* PC21: SCC1 EN RXCLK */ + {1, 1, 0, 0, 0, 0}, /* PC20: SCC1 EN TXCLK */ + {1, 1, 0, 0, 0, 0}, /* PC19: FCC2 MII RX_CLK CLK13 */ + {1, 1, 0, 0, 0, 0}, /* PC18: FCC Tx Clock (CLK14) */ + {1, 1, 0, 0, 0, 0}, /* PC17: PC17 */ + {1, 1, 0, 0, 0, 0}, /* PC16: FCC Tx Clock (CLK16) */ + {0, 1, 0, 0, 0, 0}, /* PC15: PC15 */ + {0, 1, 0, 0, 0, 0}, /* PC14: SCC1 EN *CD */ + {0, 1, 0, 0, 0, 0}, /* PC13: PC13 */ + {0, 1, 0, 1, 0, 0}, /* PC12: PC12 */ + {0, 0, 0, 1, 0, 0}, /* PC11: LXT971 transmit control */ + {0, 0, 0, 1, 0, 0}, /* PC10: FETHMDC */ + {0, 0, 0, 0, 0, 0}, /* PC9 : FETHMDIO */ + {0, 0, 0, 1, 0, 0}, /* PC8 : PC8 */ + {0, 0, 0, 1, 0, 0}, /* PC7 : PC7 */ + {0, 0, 0, 1, 0, 0}, /* PC6 : PC6 */ + {0, 0, 0, 1, 0, 0}, /* PC5 : PC5 */ + {0, 0, 0, 1, 0, 0}, /* PC4 : PC4 */ + {0, 0, 0, 1, 0, 0}, /* PC3 : PC3 */ + {0, 0, 0, 1, 0, 1}, /* PC2 : ENET FDE */ + {0, 0, 0, 1, 0, 0}, /* PC1 : ENET DSQE */ + {0, 0, 0, 1, 0, 0}, /* PC0 : ENET LBK */ + }, + + /* Port D: conf, ppar, psor, pdir, podr, pdat */ + { + {1, 1, 0, 0, 0, 0}, /* PD31: SCC1 EN RxD */ + {1, 1, 1, 1, 0, 0}, /* PD30: SCC1 EN TxD */ + {1, 1, 0, 1, 0, 0}, /* PD29: SCC1 EN TENA */ + {1, 1, 0, 0, 0, 0}, /* PD28: PD28 */ + {1, 1, 0, 1, 0, 0}, /* PD27: PD27 */ + {1, 1, 0, 1, 0, 0}, /* PD26: PD26 */ + {0, 0, 0, 1, 0, 0}, /* PD25: PD25 */ + {0, 0, 0, 1, 0, 0}, /* PD24: PD24 */ + {0, 0, 0, 1, 0, 0}, /* PD23: PD23 */ + {0, 0, 0, 1, 0, 0}, /* PD22: PD22 */ + {0, 0, 0, 1, 0, 0}, /* PD21: PD21 */ + {0, 0, 0, 1, 0, 0}, /* PD20: PD20 */ + {0, 0, 0, 1, 0, 0}, /* PD19: PD19 */ + {0, 0, 0, 1, 0, 0}, /* PD18: PD18 */ + {0, 1, 0, 0, 0, 0}, /* PD17: FCC1 ATMRXPRTY */ + {0, 1, 0, 1, 0, 0}, /* PD16: FCC1 ATMTXPRTY */ + {0, 1, 1, 0, 1, 0}, /* PD15: I2C SDA */ + {0, 0, 0, 1, 0, 0}, /* PD14: LED */ + {0, 0, 0, 0, 0, 0}, /* PD13: PD13 */ + {0, 0, 0, 0, 0, 0}, /* PD12: PD12 */ + {0, 0, 0, 0, 0, 0}, /* PD11: PD11 */ + {0, 0, 0, 0, 0, 0}, /* PD10: PD10 */ + {0, 1, 0, 1, 0, 0}, /* PD9 : SMC1 TXD */ + {0, 1, 0, 0, 0, 0}, /* PD8 : SMC1 RXD */ + {0, 0, 0, 1, 0, 1}, /* PD7 : PD7 */ + {0, 0, 0, 1, 0, 1}, /* PD6 : PD6 */ + {0, 0, 0, 1, 0, 1}, /* PD5 : PD5 */ + {0, 0, 0, 1, 0, 1}, /* PD4 : PD4 */ + {0, 0, 0, 0, 0, 0}, /* PD3 : pin doesn't exist */ + {0, 0, 0, 0, 0, 0}, /* PD2 : pin doesn't exist */ + {0, 0, 0, 0, 0, 0}, /* PD1 : pin doesn't exist */ + {0, 0, 0, 0, 0, 0} /* PD0 : pin doesn't exist */ + } }; #endif /* CONFIG_CPM2 */

@@ -207,9 +207,9 @@ const iop_conf_t iop_conf_tab[4][32] = { static const int casl_table[] = { 20, 25, 30 }; #define N_CASL (sizeof(casl_table) / sizeof(casl_table[0]))

-int cas_latency(void) +int cas_latency (void) { - char *s = getenv("serial#"); + char *s = getenv ("serial#"); int casl; int val; int i; @@ -217,11 +217,11 @@ int cas_latency(void) casl = CONFIG_DDR_DEFAULT_CL;

if (s != NULL) { - if (strncmp(s + strlen(s) - strlen(CASL_STRING1), CASL_STRING2, - strlen(CASL_STRING2)) == 0) { - val = simple_strtoul(s + strlen(s) - 2, NULL, 10); + if (strncmp(s + strlen (s) - strlen (CASL_STRING1), + CASL_STRING2, strlen (CASL_STRING2)) == 0) { + val = simple_strtoul (s + strlen (s) - 2, NULL, 10);

- for (i=0; i<N_CASL; ++i) { + for (i = 0; i < N_CASL; ++i) { if (val == casl_table[i]) { return val; } @@ -234,14 +234,14 @@ int cas_latency(void)

int checkboard (void) { - char *s = getenv("serial#"); + char *s = getenv ("serial#");

- printf("Board: %s", CONFIG_BOARDNAME); + printf ("Board: %s", CONFIG_BOARDNAME); if (s != NULL) { - puts(", serial# "); - puts(s); + puts (", serial# "); + puts (s); } - putc('\n'); + putc ('\n');

#ifdef CONFIG_PCI printf ("PCI1: 32 bit, %d MHz (compiled)\n", @@ -272,13 +272,15 @@ int misc_init_r (void) * Check if boot FLASH isn't max size */ if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) { - memctl->or0 = gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff); - memctl->br0 = gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff); + memctl->or0 = + gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff); + memctl->br0 = + gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff);

/* * Re-check to get correct base address */ - flash_get_size(gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1); + flash_get_size (gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1); }

/* @@ -297,7 +299,8 @@ int misc_init_r (void)

/* Monitor protection ON by default */ flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, CFG_MONITOR_BASE + monitor_flash_len - 1, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, &flash_info[CFG_MAX_FLASH_BANKS - 1]);

/* Environment protection ON by default */ @@ -385,22 +388,19 @@ static struct pci_config_table pci_mpc85xxads_config_table[] = { PCI_IDSEL_NUMBER, PCI_ANY_ID, pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | - PCI_COMMAND_MASTER}}, + PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, {} }; #endif

- static struct pci_controller hose = { #ifndef CONFIG_PCI_PNP - config_table:pci_mpc85xxads_config_table, + config_table:pci_mpc85xxads_config_table, #endif };

#endif /* CONFIG_PCI */

- void pci_init_board (void) { #ifdef CONFIG_PCI @@ -412,7 +412,7 @@ void pci_init_board (void) int board_early_init_r (void) { #ifdef CONFIG_PS2MULT - ps2mult_early_init(); + ps2mult_early_init (); #endif /* CONFIG_PS2MULT */ return (0); } diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index fca5f74..f0e7318 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -50,7 +50,7 @@ #define CONFIG_CPM2 1 /* has CPM2 */ #endif

-#define CONFIG_FSL_LAW 1 /* Use common FSL init code */ +#define CONFIG_FSL_LAW 1 /* Use common FSL init code */

/* * sysclk for MPC85xx @@ -102,11 +102,11 @@ /* TQM8540 & 8560 need DLL-override */ #define CONFIG_DDR_DLL /* DLL fix needed */ #define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */ -#endif /* defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) */ +#endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */

#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ -#endif /* defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) */ +#endif /* CONFIG_TQM8541 || CONFIG_TQM8555 */

/* * Flash on the Local Bus @@ -116,51 +116,51 @@ #define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }

#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */ -#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */ +#define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */

#define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */ #define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */ #define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */ #define CFG_OR1_PRELIM 0xfc000040 /* 64MB Flash */

-#define CFG_FLASH_CFI /* flash is CFI compat. */ -#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/ +#define CFG_FLASH_CFI /* flash is CFI compat. */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/

-#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ -#define CFG_MAX_FLASH_SECT 512 /* sectors per device */ +#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ +#define CFG_MAX_FLASH_SECT 512 /* sectors per device */ #undef CFG_FLASH_CHECKSUM #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */

#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */

-#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ -#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ -#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ -#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ +#define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ +#define CFG_LBC_LBCR 0x00000000 /* LB config reg */ +#define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ +#define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/

#define CONFIG_L1_INIT_RAM #define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */

-#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET

-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon */ #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */

/* Serial Port */ #if defined(CONFIG_TQM8560)

-#define CONFIG_CONS_ON_SCC /* define if console on SCC */ -#undef CONFIG_CONS_NONE /* define if console on something else */ -#define CONFIG_CONS_INDEX 1 /* which serial channel for console */ +#define CONFIG_CONS_ON_SCC /* define if console on SCC */ +#undef CONFIG_CONS_NONE /* define if console on something else */ +#define CONFIG_CONS_INDEX 1 /* which serial channel for console */

-#else /* ! TQM8560 */ +#else /* !CONFIG_TQM8560 */

#define CONFIG_CONS_INDEX 1 #undef CONFIG_SERIAL_SOFTWARE_FIFO @@ -173,20 +173,18 @@ #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)

/* PS/2 Keyboard */ -#if !defined(CONFIG_TQM8560) #define CONFIG_PS2KBD /* AT-PS/2 Keyboard */ #define CONFIG_PS2MULT /* .. on PS/2 Multiplexer */ #define CONFIG_PS2SERIAL 2 /* .. on DUART2 */ #define CONFIG_PS2MULT_DELAY (CFG_HZ/2) /* Initial delay */ #define CONFIG_BOARD_EARLY_INIT_R 1 -#endif /* !CONFIG_TQM8560 */

#endif /* CONFIG_TQM8560 */

-#define CONFIG_BAUDRATE 115200 +#define CONFIG_BAUDRATE 115200

-#define CFG_BAUDRATE_TABLE \ - {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ @@ -194,11 +192,10 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif

- /* * I2C */ -#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ +#define CONFIG_FSL_I2C /* Use FSL common I2C driver */ #define CONFIG_HARD_I2C /* I2C with hardware support */ #undef CONFIG_SOFT_I2C /* I2C bit-banged */ #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ @@ -219,7 +216,7 @@ #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ #define CFG_EEPROM_PAGE_WRITE_ENABLE #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 -#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */ +#define CFG_I2C_MULTI_EEPROMS 1 /* more than one eeprom */

/* I2C SYSMON (LM75) */ #define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */ @@ -242,7 +239,7 @@ #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCI1_IO_BASE 0xe2000000 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */

#if defined(CONFIG_PCI)

@@ -254,8 +251,7 @@ #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */

-#endif /* CONFIG_PCI */ - +#endif /* CONFIG_PCI */

#define CONFIG_NET_MULTI 1

@@ -305,7 +301,7 @@ * FCC2: a - c (X50.2 - 1) */ #define CONFIG_ETHER_ON_FCC -#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */ +#define CONFIG_ETHER_INDEX 1 /* FCC channel for ethernet */ #endif

#if defined(CONFIG_TQM8560) @@ -321,12 +317,13 @@ * FCC3: a - d (X50.2 - 3) */ #define CONFIG_ETHER_ON_FCC -#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */ +#define CONFIG_ETHER_INDEX 3 /* FCC channel for ethernet */ #endif

#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 1) #define CONFIG_ETHER_ON_FCC1 -#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) +#define CFG_CMXFCR_MASK1 (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | \ + CMXFCR_TF1CS_MSK) #define CFG_CMXFCR_VALUE1 (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12) #define CFG_CPMFCR_RAMTYPE 0 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) @@ -334,7 +331,8 @@

#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 2) #define CONFIG_ETHER_ON_FCC2 -#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) +#define CFG_CMXFCR_MASK2 (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | \ + CMXFCR_TF2CS_MSK) #define CFG_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK16 | CMXFCR_TF2CS_CLK13) #define CFG_CPMFCR_RAMTYPE 0 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) @@ -342,7 +340,8 @@

#if defined(CONFIG_ETHER_ON_FCC) && (CONFIG_ETHER_INDEX == 3) #define CONFIG_ETHER_ON_FCC3 -#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | CMXFCR_TF3CS_MSK) +#define CFG_CMXFCR_MASK3 (CMXFCR_FC3 | CMXFCR_RF3CS_MSK | \ + CMXFCR_TF3CS_MSK) #define CFG_CMXFCR_VALUE3 (CMXFCR_RF3CS_CLK15 | CMXFCR_TF3CS_CLK14) #define CFG_CPMFCR_RAMTYPE 0 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) @@ -353,7 +352,7 @@ */ #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000) -#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ +#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ #define CFG_ENV_SIZE 0x2000 #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) @@ -361,8 +360,7 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */

-#define CONFIG_TIMESTAMP /* Print image info with ts */ - +#define CONFIG_TIMESTAMP /* Print image info with ts */

/* * BOOTP options @@ -372,7 +370,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME

- /* * Command line configuration. */ @@ -389,10 +386,9 @@ #define CONFIG_CMD_MII

#if defined(CONFIG_PCI) - #define CONFIG_CMD_PCI +#define CONFIG_CMD_PCI #endif

- #undef CONFIG_WATCHDOG /* watchdog disabled */

/* @@ -403,12 +399,13 @@ #define CFG_PROMPT "=> " /* Monitor Command Prompt */

#if defined(CONFIG_CMD_KGDB) - #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ #else - #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #endif

-#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */ +#define CFG_PBSIZE (CFG_CBSIZE + \ + sizeof(CFG_PROMPT) + 16) /* Print Buf Size */ #define CFG_MAXARGS 16 /* max number of command args */ #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ @@ -433,7 +430,6 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif

- #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/

#define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ @@ -467,10 +463,10 @@ "ramdisk_addr=FE180000\0" \ "load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ + "cp.b 100000 fffc0000 40000;" \ "setenv filesize;saveenv\0" \ "upd=run load update\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self"

-#endif /* __CONFIG_H */ +#endif /* __CONFIG_H */

-- 1.5.2.2

Wolfgang Grandegger

8:12 p.m.

New subject: [U-Boot-Users] [PATCH] TQM85xx: Fix CPM port pin configuration

Do not configure port pins PD30/PD31 as SCC1 TxD/RxD except for the TQM8560 board. On the other TQM85xx boards (TQM8541 and TQM8555) SCC1 is not used as serial interface anyway. Worse, on some board variants configuring the pins for SCC1 leads to short circuits (for example on the TQM8541-BG).

Signed-off-by: Martin Krause martin.krause@tqs.de --- board/tqc/tqm85xx/tqm85xx.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-)

diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 31364d3..af8c170 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -165,9 +165,15 @@ const iop_conf_t iop_conf_tab[4][32] = {

/* Port D: conf, ppar, psor, pdir, podr, pdat */ { +#ifdef CONFIG_TQM8560 {1, 1, 0, 0, 0, 0}, /* PD31: SCC1 EN RxD */ {1, 1, 1, 1, 0, 0}, /* PD30: SCC1 EN TxD */ {1, 1, 0, 1, 0, 0}, /* PD29: SCC1 EN TENA */ +#else /* !CONFIG_TQM8560 */ + {0, 0, 0, 0, 0, 0}, /* PD31: PD31 */ + {0, 0, 0, 0, 0, 0}, /* PD30: PD30 */ + {0, 0, 0, 0, 0, 0}, /* PD29: PD29 */ +#endif /* CONFIG_TQM8560 */ {1, 1, 0, 0, 0, 0}, /* PD28: PD28 */ {1, 1, 0, 1, 0, 0}, /* PD27: PD27 */ {1, 1, 0, 1, 0, 0}, /* PD26: PD26 */

-- 1.5.2.2

Wolfgang Grandegger

8:12 p.m.

New subject: [U-Boot-Users] [PATCH] TQM85xx: Support for Spansion 'N' type flashes added

The 'N' type Spansion flashes (S29GLxxxM series) have bigger sectors, than the formerly used 'M' types (S29GLxxxM series), so the flash layout needs to be changed -> new start address of the environment. The macro definition CONFIG_TQM_FLASH_N_TYPE is undefined by default and must be defined for boards with 'N' type flashes.

Signed-off-by: Martin Krause martin.krause@tqs.de Signed-off-by: Wolfgang Grandegger wg@grandegger.com --- include/configs/TQM85xx.h | 20 ++++++++++++++++---- 1 files changed, 16 insertions(+), 4 deletions(-)

diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index f0e7318..4011b2a 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -109,6 +109,13 @@ #endif /* CONFIG_TQM8541 || CONFIG_TQM8555 */

/* + * Old TQM85xx boards have 'M' type Spansion Flashes from the S29GLxxxM + * series while new boards have 'N' type Flashes from the S29GLxxxN + * series, which have bigger sectors: 128 instead of 256 KB. + */ +#undef CONFIG_TQM_FLASH_N_TYPE + +/* * Flash on the Local Bus */ #define CFG_FLASH0 0xFC000000 @@ -151,7 +158,7 @@ #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon */ -#define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ +#define CFG_MALLOC_LEN (256 * 1024) /* Reserved for malloc */

/* Serial Port */ #if defined(CONFIG_TQM8560) @@ -351,10 +358,15 @@ * Environment */ #define CFG_ENV_IS_IN_FLASH 1 -#define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x20000) -#define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ + +#ifdef CONFIG_TQM_FLASH_N_TYPE +#define CFG_ENV_SECT_SIZE 0x40000 /* 256K (one sector) for env */ +#else /* !CONFIG_TQM_FLASH_N_TYPE */ +#define CFG_ENV_SECT_SIZE 0x20000 /* 128K (one sector) for env */ +#endif /* CONFIG_TQM_FLASH_N_TYPE */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE 0x2000 -#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE) #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)

#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */

-- 1.5.2.2

Wolfgang Grandegger

8:12 p.m.

New subject: [U-Boot-Users] [PATCH] TQM85xx: Fix chip select configuration for second FLASH bank

This patch fixes the re-calculation of the automatic chip select configuration for boards with two populated FLASH banks.

Signed-off-by: Martin Krause martin.krause@tqs.de --- board/tqc/tqm85xx/tqm85xx.c | 86 +++++++++++++++++++++++------------------- 1 files changed, 47 insertions(+), 39 deletions(-)

diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index af8c170..f38b009 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -274,53 +274,61 @@ int misc_init_r (void) gd->bd->bi_flashstart = 0 - gd->bd->bi_flashsize; gd->bd->bi_flashoffset = 0;

- /* - * Check if boot FLASH isn't max size + /* + * Recalculate CS configuration if second FLASH bank is available */ - if (gd->bd->bi_flashsize < (0 - CFG_FLASH0)) { - memctl->or0 = - gd->bd->bi_flashstart | (CFG_OR0_PRELIM & 0x00007fff); - memctl->br0 = - gd->bd->bi_flashstart | (CFG_BR0_PRELIM & 0x00007fff); - + if (flash_info[0].size > 0) { + memctl->or1 = ((-flash_info[0].size) & 0xffff8000) | + (CFG_OR1_PRELIM & 0x00007fff); + memctl->br1 = gd->bd->bi_flashstart | + (CFG_BR1_PRELIM & 0x00007fff); /* - * Re-check to get correct base address + * Re-check to get correct base address for bank 1 */ - flash_get_size (gd->bd->bi_flashstart, CFG_MAX_FLASH_BANKS - 1); + flash_get_size (gd->bd->bi_flashstart, 0); + } else { + memctl->or1 = 0; + memctl->br1 = 0; }

/* - * Check if only one FLASH bank is available + * If bank 1 is equipped, bank 0 is mapped after bank 1 */ - if (gd->bd->bi_flashsize != CFG_MAX_FLASH_BANKS * (0 - CFG_FLASH0)) { - memctl->or1 = 0; - memctl->br1 = 0; + memctl->or0 = ((-flash_info[1].size) & 0xffff8000) | + (CFG_OR0_PRELIM & 0x00007fff); + memctl->br0 = (gd->bd->bi_flashstart + flash_info[0].size) | + (CFG_BR0_PRELIM & 0x00007fff); + /* + * Re-check to get correct base address for bank 0 + */ + flash_get_size (gd->bd->bi_flashstart + flash_info[0].size, 1);

- /* - * Re-do flash protection upon new addresses - */ - flash_protect (FLAG_PROTECT_CLEAR, - gd->bd->bi_flashstart, 0xffffffff, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); - - /* Monitor protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CFG_MONITOR_BASE, - CFG_MONITOR_BASE + monitor_flash_len - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); - - /* Environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR, - CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); - - /* Redundant environment protection ON by default */ - flash_protect (FLAG_PROTECT_SET, - CFG_ENV_ADDR_REDUND, - CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, - &flash_info[CFG_MAX_FLASH_BANKS - 1]); - } + /* + * Re-do flash protection upon new addresses + */ + flash_protect (FLAG_PROTECT_CLEAR, + gd->bd->bi_flashstart, 0xffffffff, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Monitor protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_MONITOR_BASE, + CFG_MONITOR_BASE + monitor_flash_len - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + + /* Environment protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR, + CFG_ENV_ADDR + CFG_ENV_SECT_SIZE - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); + +#ifdef CFG_ENV_ADDR_REDUND + /* Redundant environment protection ON by default */ + flash_protect (FLAG_PROTECT_SET, + CFG_ENV_ADDR_REDUND, + CFG_ENV_ADDR_REDUND + CFG_ENV_SIZE_REDUND - 1, + &flash_info[CFG_MAX_FLASH_BANKS - 1]); +#endif

return 0; }

-- 1.5.2.2

Wolfgang Grandegger

8:12 p.m.

New subject: [U-Boot-Users] [PATCH] TQM85xx: Bugfix in the SDRAM initialisation

The CS0_BNDS register is now set according to the detected memory size.

Signed-off-by Martin Krause martin.krause@tqs.de --- board/tqc/tqm85xx/sdram.c | 4 +++- 1 files changed, 3 insertions(+), 1 deletions(-)

diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c index 413567e..e005d84 100644 --- a/board/tqc/tqm85xx/sdram.c +++ b/board/tqc/tqm85xx/sdram.c @@ -104,8 +104,10 @@ long int sdram_setup (int casl) if (get_ram_size (0, ddr_cs_conf[i].size) == ddr_cs_conf[i].size) { /* - * OK, size detected -> all done + * size detected -> set Chip Select Bounds Register */ + ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24; + return ddr_cs_conf[i].size; } }

-- 1.5.2.2

Wolfgang Grandegger

8:12 p.m.

New subject: [U-Boot-Users] [PATCH] TQM85xx: Support for Intel 82527 compatible CAN controller

This patch adds initialization of the UPMC RAM to support up to two Intel 82527 compatible CAN controller on the TQM85xx modules.

Signed-off-by: Thomas Waehner thomas.waehner@tqs.de Signed-off-by: Wolfgang Grandegger wg@grandegger.com --- board/tqc/tqm85xx/law.c | 4 +++ board/tqc/tqm85xx/tlb.c | 1 + board/tqc/tqm85xx/tqm85xx.c | 59 +++++++++++++++++++++++++++++++++++++++++++ include/configs/TQM85xx.h | 11 ++++++++ include/mpc85xx.h | 5 +++ 5 files changed, 80 insertions(+), 0 deletions(-)

diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c index d937700..ad35464 100644 --- a/board/tqc/tqm85xx/law.c +++ b/board/tqc/tqm85xx/law.c @@ -35,6 +35,7 @@ * 0xc000_0000 0xdfff_ffff RapidIO 512M * 0xe000_0000 0xe000_ffff CCSR 1M * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xe300_0000 0xe3ff_ffff CAN 16M * 0xf800_0000 0xf80f_ffff BCSR 1M * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M * @@ -49,6 +50,9 @@ struct law_entry law_table[] = { SET_LAW_ENTRY (3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), SET_LAW_ENTRY (4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), +#ifdef CONFIG_CAN_DRIVER + SET_LAW_ENTRY (6, CFG_CAN_BASE, LAWAR_SIZE_16M, LAW_TRGT_IF_LBC), +#endif /* CONFIG_CAN_DRIVER */ };

int num_law_entries = ARRAY_SIZE (law_table); diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c index 3e29062..dc36201 100644 --- a/board/tqc/tqm85xx/tlb.c +++ b/board/tqc/tqm85xx/tlb.c @@ -95,6 +95,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 6: 64M Non-cacheable, guarded * 0xe0000000 1M CCSRBAR * 0xe2000000 16M PCI1 IO + * 0xe3000000 16M CAN */ SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index f38b009..bca59a3 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -31,6 +31,7 @@ #include <pci.h> #include <asm/processor.h> #include <asm/immap_85xx.h> +#include <asm/io.h> #include <ioports.h> #include <flash.h>

@@ -333,6 +334,28 @@ int misc_init_r (void) return 0; }

+#ifdef CONFIG_CAN_DRIVER +/* + * Initialize UPMC RAM + */ +static void upmc_write (u_char addr, uint val) +{ + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + + out_be32 (&lbc->mdr, val); + + out_be32 (&lbc->mcmr, + (in_be32 (&lbc->mcmr) & ~(MxMR_OP_NORM | MxMR_MAD)) | + MxMR_OP_WARR | (addr & MxMR_MAD)); + /* dummy access to perform write */ + out_8 ((void __iomem *)CFG_CAN_BASE, 0); + + /* normal operation */ + out_be32 (&lbc->mcmr, + (in_be32 (&lbc->mcmr) & ~MxMR_OP_WARR) | MxMR_OP_NORM); +} +#endif /* CONFIG_CAN_DRIVER */ + /* * Initialize Local Bus */ @@ -389,6 +412,42 @@ void local_bus_init (void) gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); asm ("sync;isync;msync"); } + +#ifdef CONFIG_CAN_DRIVER + /* Initialize OR2 / BR2 */ + lbc->or2 = CFG_OR2_CAN; + lbc->br2 = CFG_BR2_CAN; + + /* + * According to timing specifications EAD must be + * set if Local Bus Clock is > 83 MHz. + */ + if (lbc_hz > 83) + lbc->or2 |= ORxU_EAD; + + /* LGPL4 is UPWAIT */ + out_be32(&lbc->mcmr, MxMR_DSx_3_CYCL | MxMR_GPL4_DIS | MxMR_WLFx_3X); + + /* Initialize UPMC for CAN: single read */ + upmc_write (0x00, 0xFFFFED00); + upmc_write (0x01, 0xCCFFCC00); + upmc_write (0x02, 0x00FFCF00); + upmc_write (0x03, 0x00FFCF00); + upmc_write (0x04, 0x00FFDC00); + upmc_write (0x05, 0x00FFCF00); + upmc_write (0x06, 0x00FFED00); + upmc_write (0x07, 0x3FFFCC07); + + /* Initialize UPMC for CAN: single write */ + upmc_write (0x18, 0xFFFFED00); + upmc_write (0x19, 0xCCFFEC00); + upmc_write (0x1A, 0x00FFED80); + upmc_write (0x1B, 0x00FFED80); + upmc_write (0x1C, 0x00FFFC00); + upmc_write (0x1D, 0x0FFFEC00); + upmc_write (0x1E, 0x0FFFEF00); + upmc_write (0x1F, 0x3FFFEC05); +#endif /* CONFIG_CAN_DRIVER */ }

#if defined(CONFIG_PCI) diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 4011b2a..9eec858 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -52,6 +52,8 @@

#define CONFIG_FSL_LAW 1 /* Use common FSL init code */

+#undef CONFIG_CAN_DRIVER /* CAN Driver support */ + /* * sysclk for MPC85xx * @@ -199,6 +201,15 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif

+/* CAN */ +#ifdef CONFIG_CAN_DRIVER +#define CFG_CAN_BASE 0xE3000000 /* CAN base address */ +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 KiB address mask */ +#define CFG_OR2_CAN (CFG_CAN_OR_AM | ORxU_BI) +#define CFG_BR2_CAN ((CFG_CAN_BASE & BRx_BA_MSK) | \ + BRx_PS_8 | BRx_MS_UPMC | BRx_V) +#endif /* CONFIG_CAN_DRIVER */ + /* * I2C */ diff --git a/include/mpc85xx.h b/include/mpc85xx.h index 321b24f..9dbc9a8 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -53,7 +53,12 @@ #define ORxU_AM_MSK 0xffff8000 /* Address Mask Mask */

#define MxMR_OP_NORM 0x00000000 /* Normal Operation */ +#define MxMR_MAD 0x0000003F /* Machine address, RAM address ptr*/ +#define MxMR_WLFx_3X 0x00000C00 /* Write loop executed 3 times */ +#define MxMR_GPL4_DIS 0x00040000 /* GPL4 output line disable */ #define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */ +#define MxMR_DSx_3_CYCL 0x00800000 /* 3 cycle Disable Period */ +#define MxMR_DSx_4_CYCL 0x00C00000 /* 4 cycle Disable Period */ #define MxMR_OP_WARR 0x10000000 /* Write to Array */ #define MxMR_BSEL 0x80000000 /* Bus Select */

-- 1.5.2.2

Wolfgang Grandegger

8:12 p.m.

New subject: [U-Boot-Users] [PATCH] TQM85xx: Support for Flat Device Tree

This patch adds support for Linux kernels using the Flat Device Tree. It also re-defines the default environment settings for booting Linux with the FDT blob.

Signed-off-by: Wolfgang Grandegger wg@grandegger.com --- Makefile | 3 +- board/tqc/tqm85xx/tqm85xx.c | 24 ++++++++++++++++++++ include/configs/TQM85xx.h | 50 +++++++++++++++++++++++++++++++++--------- 3 files changed, 64 insertions(+), 13 deletions(-)

diff --git a/Makefile b/Makefile index 7d05d62..32c9643 100644 --- a/Makefile +++ b/Makefile @@ -2233,8 +2233,7 @@ TQM8560_config: unconfig echo "#define CONFIG_MPC$${CTYPE}">>$(obj)include/config.h; \ echo "#define CONFIG_TQM$${CTYPE}">>$(obj)include/config.h; \ echo "#define CONFIG_HOSTNAME tqm$${CTYPE}">>$(obj)include/config.h; \ - echo "#define CONFIG_BOARDNAME "TQM$${CTYPE}"">>$(obj)include/config.h; \ - echo "#define CFG_BOOTFILE_PATH "/tftpboot/tqm$${CTYPE}/uImage"">>$(obj)include/config.h + echo "#define CONFIG_BOARDNAME "TQM$${CTYPE}"">>$(obj)include/config.h; @$(MKCONFIG) -a TQM85xx ppc mpc85xx tqm85xx tqc

######################################################################### diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index bca59a3..8690fb1 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -34,6 +34,8 @@ #include <asm/io.h> #include <ioports.h> #include <flash.h> +#include <libfdt.h> +#include <fdt_support.h>

DECLARE_GLOBAL_DATA_PTR;

@@ -481,6 +483,28 @@ void pci_init_board (void) #endif /* CONFIG_PCI */ }

+#if defined(CONFIG_OF_BOARD_SETUP) +void ft_board_setup (void *blob, bd_t *bd) +{ + int node, tmp[2]; + const char *path; + + ft_cpu_setup (blob, bd); + + node = fdt_path_offset (blob, "/aliases"); + tmp[0] = 0; + if (node >= 0) { +#ifdef CONFIG_PCI + path = fdt_getprop (blob, node, "pci0", NULL); + if (path) { + tmp[1] = hose.last_busno - hose.first_busno; + do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1); + } +#endif + } +} +#endif + #ifdef CONFIG_BOARD_EARLY_INIT_R int board_early_init_r (void) { diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 9eec858..ef89ba4 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -201,6 +201,11 @@ #define CFG_PROMPT_HUSH_PS2 "> " #endif

+/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 +#define CONFIG_OF_STDOUT_VIA_ALIAS 1 + /* CAN */ #ifdef CONFIG_CAN_DRIVER #define CFG_CAN_BASE 0xE3000000 /* CAN base address */ @@ -463,10 +468,26 @@

#undef CONFIG_BOOTARGS /* the boot command will set bootargs */

+ +/* + * Setup some board specific values for the default environment variables + */ +#ifdef CONFIG_CPM2 +#define CFG_ENV_CONSDEV "consdev=ttyCPM0\0" +#else +#define CFG_ENV_CONSDEV "consdev=ttyS0\0" +#endif +#define CFG_ENV_FDT_FILE "fdt_file="MK_STR(CONFIG_HOSTNAME)"/" \ + MK_STR(CONFIG_HOSTNAME)".dtb\0" +#define CFG_ENV_BOOTFILE "bootfile="MK_STR(CONFIG_HOSTNAME)"/uImage\0" +#define CFG_ENV_UBOOT "uboot="MK_STR(CONFIG_HOSTNAME)"/u-boot.bin\0" \ + "uboot_addr="MK_STR(TEXT_BASE)"\0" + #define CONFIG_EXTRA_ENV_SETTINGS \ - "bootfile="CFG_BOOTFILE_PATH"\0" \ + CFG_ENV_BOOTFILE \ + CFG_ENV_FDT_FILE \ + CFG_ENV_CONSDEV \ "netdev=eth0\0" \ - "consdev=ttyS0\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=$serverip:$rootpath\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -476,17 +497,24 @@ "addcons=setenv bootargs $bootargs " \ "console=$consdev,$baudrate\0" \ "flash_nfs=run nfsargs addip addcons;" \ - "bootm $kernel_addr\0" \ + "bootm $kernel_addr - $fdt_addr\0" \ "flash_self=run ramargs addip addcons;" \ - "bootm $kernel_addr $ramdisk_addr\0" \ - "net_nfs=tftp $loadaddr $bootfile;" \ - "run nfsargs addip addcons;bootm\0" \ + "bootm $kernel_addr $ramdisk_addr $fdt_addr\0" \ + "net_nfs=tftp $kernel_addr_r $bootfile;" \ + "tftp $fdt_addr_r $fdt_file;" \ + "run nfsargs addip addcons;" \ + "bootm $kernel_addr_r - $fdt_addr_r\0" \ "rootpath=/opt/eldk/ppc_85xx\0" \ - "kernel_addr=FE000000\0" \ - "ramdisk_addr=FE180000\0" \ - "load=tftp 100000 /tftpboot/$hostname/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b 100000 fffc0000 40000;" \ + "fdt_addr_r=900000\0" \ + "kernel_addr_r=1000000\0" \ + "fdt_addr=ffec0000\0" \ + "kernel_addr=ffd00000\0" \ + "ramdisk_addr=ff800000\0" \ + CFG_ENV_UBOOT \ + "load=tftp 100000 $uboot\0" \ + "update=protect off $uboot_addr +$filesize;" \ + "erase $uboot_addr +$filesize;" \ + "cp.b 100000 $uboot_addr $filesize;" \ "setenv filesize;saveenv\0" \ "upd=run load update\0" \ ""

-- 1.5.2.2

Wolfgang Grandegger

8:12 p.m.

New subject: [U-Boot-Users] [PATCH] TQM8548: Basic support for the TQM8548 modules

This patch adds basic support for the TQM8548 module from TQ-Components (http://www.tqc.de/) including DDR2 SDRAM initialisation and support for eTSEC 3 and 4

Furthermore Flash buffer write has been enabled to speed up output to the Flash by approx. a factor of 10.

Signed-off-by: Thomas Waehner thomas.waehner@tqs.de Signed-off-by: Wolfgang Grandegger wg@grandegger.com --- MAKEALL | 1 + Makefile | 1 + board/tqc/tqm85xx/sdram.c | 150 ++++++++++++++++++++++++++++++++++++++++++- board/tqc/tqm85xx/tqm85xx.c | 113 ++++++++++++++++++++++++++++---- drivers/input/ps2ser.c | 31 ++++++--- include/configs/TQM85xx.h | 71 ++++++++++++++++++-- include/mpc85xx.h | 9 +++ 7 files changed, 343 insertions(+), 33 deletions(-)

diff --git a/MAKEALL b/MAKEALL index 0674069..ec20e62 100755 --- a/MAKEALL +++ b/MAKEALL @@ -359,6 +359,7 @@ LIST_85xx=" \ stxssa \ TQM8540 \ TQM8541 \ + TQM8548 \ TQM8555 \ TQM8560 \ " diff --git a/Makefile b/Makefile index 32c9643..3cca59c 100644 --- a/Makefile +++ b/Makefile @@ -2225,6 +2225,7 @@ stxssa_4M_config: unconfig

TQM8540_config \ TQM8541_config \ +TQM8548_config \ TQM8555_config \ TQM8560_config: unconfig @mkdir -p $(obj)include diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c index e005d84..442ff66 100644 --- a/board/tqc/tqm85xx/sdram.c +++ b/board/tqc/tqm85xx/sdram.c @@ -30,16 +30,27 @@ struct sdram_conf_s { unsigned long size; unsigned long reg; +#ifdef CONFIG_TQM8548 + unsigned long refresh; +#endif /* CONFIG_TQM8548 */ };

typedef struct sdram_conf_s sdram_conf_t;

+#ifdef CONFIG_TQM8548 +sdram_conf_t ddr_cs_conf[] = { + {(512 << 20), 0x80044102, 0x0001A000}, /* 512MB, 13x10(4) */ + {(256 << 20), 0x80040102, 0x00014000}, /* 256MB, 13x10(4) */ + {(128 << 20), 0x80040101, 0x0000C000}, /* 128MB, 13x9(4) */ +}; +#else /* !CONFIG_TQM8548 */ sdram_conf_t ddr_cs_conf[] = { {(512 << 20), 0x80000202}, /* 512MB, 14x10(4) */ {(256 << 20), 0x80000102}, /* 256MB, 13x10(4) */ {(128 << 20), 0x80000101}, /* 128MB, 13x9(4) */ {( 64 << 20), 0x80000001}, /* 64MB, 12x9(4) */ }; +#endif /* CONFIG_TQM8548 */

#define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))

@@ -56,8 +67,12 @@ long int sdram_setup (int casl) { int i; volatile ccsr_ddr_t *ddr = (void *)(CFG_MPC85xx_DDR_ADDR); +#ifdef CONFIG_TQM8548 + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); +#else /* !CONFIG_TQM8548 */ unsigned long cfg_ddr_timing1; unsigned long cfg_ddr_mode; +#endif /* CONFIG_TQM8548 */

/* * Disable memory controller. @@ -65,6 +80,122 @@ long int sdram_setup (int casl) ddr->cs0_config = 0; ddr->sdram_cfg = 0;

+#ifdef CONFIG_TQM8548 + ddr->cs0_bnds = (ddr_cs_conf[0].size - 1) >> 24; + ddr->cs0_config = ddr_cs_conf[0].reg; + ddr->timing_cfg_3 = 0x00010000; + + /* TIMING CFG 1, 533MHz + * PRETOACT: 4 Clocks + * ACTTOPRE: 12 Clocks + * ACTTORW: 4 Clocks + * CASLAT: 4 Clocks + * REFREC: 34 Clocks + * WRREC: 4 Clocks + * ACTTOACT: 3 Clocks + * WRTORD: 2 Clocks + */ + ddr->timing_cfg_1 = 0x4C47A432; + + /* TIMING CFG 2, 533MHz + * ADD_LAT: 3 Clocks + * CPO: READLAT + 1 + * WR_LAT: 3 Clocks + * RD_TO_PRE: 2 Clocks + * WR_DATA_DELAY: 1/2 Clock + * CKE_PLS: 1 Clock + * FOUR_ACT: 13 Clocks + */ + ddr->timing_cfg_2 = 0x3318484D; + + /* DDR SDRAM Mode, 533MHz + * MRS: Extended Mode Register + * OUT: Outputs enabled + * RDQS: no + * DQS: enabled + * OCD: default state + * RTT: 75 Ohms + * Posted CAS: 3 Clocks + * ODS: reduced strength + * DLL: enabled + * MR: Mode Register + * PD: fast exit + * WR: 4 Clocks + * DLL: no DLL reset + * TM: normal + * CAS latency: 4 Clocks + * BT: sequential + * Burst length: 4 + */ + ddr->sdram_mode = 0x439E0642; + + /* DDR SDRAM Interval, 533MHz + * REFINT: 1040 Clocks + * BSTOPRE: 256 + */ + ddr->sdram_interval = (1040 << 16) | 0x100; + + /* + * workaround for erratum DD10 of MPC8458 family below rev. 2.0: + * DDR IO receiver must be set to an acceptable bias point by modifying + * a hidden register. + */ + if (SVR_REV (get_svr ()) < 0x20) { + gur->ddrioovcr = 0x90000000; /* enable, VSEL 1.8V */ + } + + /* DDR SDRAM CFG 2 + * FRC_SR: normal mode + * SR_IE: no self-refresh interrupt + * DLL_RST_DIS: don't care, leave at reset value + * DQS_CFG: differential DQS signals + * ODT_CFG: assert ODT to internal IOs only during reads to DRAM + * LVWx_CFG: don't care, leave at reset value + * NUM_PR: 1 refresh will be issued at a time + * DM_CFG: don't care, leave at reset value + * D_INIT: no data initialization + */ + ddr->sdram_cfg_2 = 0x04401000; + + /* DDR SDRAM MODE 2 + * MRS: Extended Mode Register 2 + */ + ddr->sdram_mode_2 = 0x8000C000; + + /* DDR SDRAM CLK CNTL + * CLK_ADJUST: 1/2 Clock 0x02000000 + * CLK_ADJUST: 5/8 Clock 0x02800000 + */ + ddr->sdram_clk_cntl = 0x02800000; + + /* wait for clock stabilization */ + asm ("sync;isync;msync"); + udelay(1000); + + /* DDR SDRAM CLK CNTL + * MEM_EN: enabled + * SREN: don't care, leave at reset value + * ECC_EN: no error report + * RD_EN: no register DIMMs + * SDRAM_TYPE: DDR2 + * DYN_PWR: no power management + * 32_BE: don't care, leave at reset value + * 8_BE: 4 beat burst + * NCAP: don't care, leave at reset value + * 2T_EN: 1T Timing + * BA_INTLV_CTL: no interleaving + * x32_EN: x16 organization + * PCHB8: MA[10] for auto-precharge + * HSE: half strength for single and 2-layer stacks + * (full strength for 3- and 4-layer stacks no yet considered) + * MEM_HALT: no halt + * BI: automatic initialization + */ + ddr->sdram_cfg = 0x83000008; + asm ("sync; isync; msync"); + udelay(1000); + +#else /* !CONFIG_TQM8548 */ switch (casl) { case 20: cfg_ddr_timing1 = 0x47405331 | (3 << 16); @@ -97,6 +228,7 @@ long int sdram_setup (int casl) ddr->sdram_cfg = 0xc2000000; /* unbuffered,no DYN_PWR */ asm ("sync; isync; msync"); udelay (1000); +#endif /* CONFIG_TQM8548 */

for (i = 0; i < N_DDR_CS_CONF; i++) { ddr->cs0_config = ddr_cs_conf[i].reg; @@ -108,11 +240,25 @@ long int sdram_setup (int casl) */ ddr->cs0_bnds = (ddr_cs_conf[i].size - 1) >> 24;

- return ddr_cs_conf[i].size; + break; } }

- return 0; /* nothing found ! */ +#ifdef CONFIG_TQM8548 + if (i < N_DDR_CS_CONF) { + /* Adjust refresh rate for DDR2 */ + + ddr->timing_cfg_3 = ddr_cs_conf[i].refresh & 0x00070000; + + ddr->timing_cfg_1 = (ddr->timing_cfg_1 & 0xFFFF0FFF) | + (ddr_cs_conf[i].refresh & 0x0000F000); + + return ddr_cs_conf[i].size; + } +#endif /* CONFIG_TQM8548 */ + + /* return size if detected, else return 0 */ + return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0; }

void board_add_ram_info (int use_default) diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 8690fb1..4d06599 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -1,4 +1,9 @@ /* + * (C) Copyright 2008 Wolfgang Grandegger wg@denx.de + * + * (C) Copyright 2006 + * Thomas Waehner, TQ-Systems GmbH, thomas.waehner@tqs.de. + * * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * @@ -358,6 +363,30 @@ static void upmc_write (u_char addr, uint val) } #endif /* CONFIG_CAN_DRIVER */

+uint get_lbc_clock (void) +{ + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + sys_info_t sys_info; + ulong clkdiv = lbc->lcrr & 0x0f; + + get_sys_info (&sys_info); + + if (clkdiv == 2 || clkdiv == 4 || clkdiv == 8) { +#ifdef CONFIG_MPC8548 + /* + * Yes, the entire PQ38 family use the same + * bit-representation for twice the clock divider value. + */ + clkdiv *= 2; +#endif + return sys_info.freqSystemBus / clkdiv; + } + + puts("Invalid clock divider value in CFG_LBC_LCRR\n"); + + return 0; +} + /* * Initialize Local Bus */ @@ -365,10 +394,71 @@ void local_bus_init (void) { volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + uint lbc_mhz = get_lbc_clock () / 1000000;

- uint clkdiv; - uint lbc_hz; - sys_info_t sysinfo; +#ifdef CONFIG_MPC8548 + uint svr = get_svr (); + uint lcrr; + + /* + * MPC revision < 2.0 + * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU1: + * Modify engineering use only register at address 0xE_0F20. + * "1. Read register at offset 0xE_0F20 + * 2. And value with 0x0000_FFFF + * 3. OR result with 0x0000_0004 + * 4. Write result back to offset 0xE_0F20." + * + * According to MPC8548E_Device_Errata Rev. L, Erratum LBIU2: + * Modify engineering use only register at address 0xE_0F20. + * "1. Read register at offset 0xE_0F20 + * 2. And value with 0xFFFF_FFDF + * 3. Write result back to offset 0xE_0F20." + * + * Since it is the same register, we do the modification in one step. + */ + if (SVR_MAJ (svr) < 2) { + uint dummy = gur->lbiuiplldcr1; + dummy &= 0x0000FFDF; + dummy |= 0x00000004; + gur->lbiuiplldcr1 = dummy; + } + + lcrr = CFG_LBC_LCRR; + + /* + * Local Bus Clock > 83.3 MHz. According to timing + * specifications set LCRR[EADC] to 2 delay cycles. + */ + if (lbc_mhz > 83) { + lcrr &= ~LCRR_EADC_MSK; + lcrr |= LCRR_EADC_2; + } + + /* + * According to MPC8548ERMAD Rev. 1.3, 13.3.1.16, 13-30 + * disable PLL bypass for Local Bus Clock > 83 MHz. + */ + if (lbc_mhz >= 66) + lcrr &= (~LCRR_DBYP); /* DLL Enabled */ + + else + lcrr |= LCRR_DBYP; /* DLL Bypass */ + + lbc->lcrr = lcrr; + asm ("sync;isync;msync"); + + /* + * According to MPC8548ERMAD Rev.1.3 read back LCRR + * and terminate with isync + */ + lcrr = lbc->lcrr; + asm ("isync;"); + + /* let DLL stabilize */ + udelay (500); + +#else /* !CONFIG_MPC8548 */

/* * Errata LBC11. @@ -379,16 +469,12 @@ void local_bus_init (void) * Between 66 and 133, the DLL is enabled with an override workaround. */

- get_sys_info (&sysinfo); - clkdiv = lbc->lcrr & 0x0f; - lbc_hz = sysinfo.freqSystemBus / 1000000 / clkdiv; - - if (lbc_hz < 66) { - lbc->lcrr = CFG_LBC_LCRR | 0x80000000; /* DLL Bypass */ + if (lbc_mhz < 66) { + lbc->lcrr = CFG_LBC_LCRR | LCRR_DBYP; /* DLL Bypass */ lbc->ltedr = 0xa4c80000; /* DK: !!! */

- } else if (lbc_hz >= 133) { - lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + } else if (lbc_mhz >= 133) { + lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */

} else { /* @@ -403,7 +489,7 @@ void local_bus_init (void) lbc->lcrr = 0x10000004; }

- lbc->lcrr = CFG_LBC_LCRR & (~0x80000000); /* DLL Enabled */ + lbc->lcrr = CFG_LBC_LCRR & (~LCRR_DBYP); /* DLL Enabled */ udelay (200);

/* @@ -414,6 +500,7 @@ void local_bus_init (void) gur->lbcdllcr = (((temp_lbcdll & 0xff) << 16) | 0x80000000); asm ("sync;isync;msync"); } +#endif /* !CONFIG_MPC8548 */

#ifdef CONFIG_CAN_DRIVER /* Initialize OR2 / BR2 */ @@ -424,7 +511,7 @@ void local_bus_init (void) * According to timing specifications EAD must be * set if Local Bus Clock is > 83 MHz. */ - if (lbc_hz > 83) + if (lbc_mhz > 83) lbc->or2 |= ORxU_EAD;

/* LGPL4 is UPWAIT */ diff --git a/drivers/input/ps2ser.c b/drivers/input/ps2ser.c index 4e304f7..c1741ea 100644 --- a/drivers/input/ps2ser.c +++ b/drivers/input/ps2ser.c @@ -49,7 +49,8 @@ DECLARE_GLOBAL_DATA_PTR; #error CONFIG_PS2SERIAL must be in 1 ... 6 #endif

#if CONFIG_PS2SERIAL == 1 #define COM_BASE (CFG_CCSRBAR+0x4500) @@ -65,7 +66,9 @@ static int ps2ser_getc_hw(void); static void ps2ser_interrupt(void *dev_id);

extern struct serial_state rs_table[]; /* in serial.c */ -#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8541) && !defined(CONFIG_MPC8555) +#if !defined(CONFIG_MPC5xxx) && !defined(CONFIG_MPC8540) && \ + !defined(CONFIG_MPC8541) && !defined(CONFIG_MPC8548) && \ + !defined(CONFIG_MPC8555) static struct serial_state *state; #endif

@@ -120,7 +123,8 @@ int ps2ser_init(void) return (0); }

-#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) int ps2ser_init(void) { NS16550_t com_port = (NS16550_t)COM_BASE; @@ -186,7 +190,8 @@ void ps2ser_putc(int chr) { #ifdef CONFIG_MPC5xxx volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) NS16550_t com_port = (NS16550_t)COM_BASE; #endif #ifdef DEBUG @@ -197,7 +202,8 @@ void ps2ser_putc(int chr) while (!(psc->psc_status & PSC_SR_TXRDY));

psc->psc_buffer_8 = chr; -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) while ((com_port->lsr & LSR_THRE) == 0); com_port->thr = chr; #else @@ -211,7 +217,8 @@ static int ps2ser_getc_hw(void) { #ifdef CONFIG_MPC5xxx volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) NS16550_t com_port = (NS16550_t)COM_BASE; #endif int res = -1; @@ -220,7 +227,8 @@ static int ps2ser_getc_hw(void) if (psc->psc_status & PSC_SR_RXRDY) { res = (psc->psc_buffer_8); } -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) if (com_port->lsr & LSR_DR) { res = com_port->rbr; } @@ -279,7 +287,8 @@ static void ps2ser_interrupt(void *dev_id) { #ifdef CONFIG_MPC5xxx volatile struct mpc5xxx_psc *psc = (struct mpc5xxx_psc *)PSC_BASE; -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) NS16550_t com_port = (NS16550_t)COM_BASE; #endif int chr; @@ -289,7 +298,8 @@ static void ps2ser_interrupt(void *dev_id) chr = ps2ser_getc_hw(); #ifdef CONFIG_MPC5xxx status = psc->psc_status; -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) status = com_port->lsr; #else status = ps2ser_in(UART_IIR); @@ -305,7 +315,8 @@ static void ps2ser_interrupt(void *dev_id) } #ifdef CONFIG_MPC5xxx } while (status & PSC_SR_RXRDY); -#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || defined(CONFIG_MPC8555) +#elif defined(CONFIG_MPC8540) || defined(CONFIG_MPC8541) || \ + defined(CONFIG_MPC8548) || defined(CONFIG_MPC8555) } while (status & LSR_DR); #else } while (status & UART_IIR_RDI); diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index ef89ba4..da06ffd 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -1,4 +1,7 @@ /* + * (C) Copyright 2007 + * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de. + * * (C) Copyright 2005 * Stefan Roese, DENX Software Engineering, sr@denx.de. * @@ -27,7 +30,7 @@ */

/* - * TQM85xx (8560/40/55/41) board configuration file + * TQM85xx (8560/40/55/41/48) board configuration file */

#ifndef __CONFIG_H @@ -44,9 +47,9 @@ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */

/* - * Only MPC8540 doesn't have CPM module + * MPC8540 and MPC8548 don't have CPM module */ -#ifndef CONFIG_MPC8540 +#if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548) #define CONFIG_CPM2 1 /* has CPM2 */ #endif

@@ -58,8 +61,8 @@ * sysclk for MPC85xx * * Two valid values are: - * 33000000 - * 66000000 + * 33333333 + * 66666666 * * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz * is likely the desired value here, so that is now the default. @@ -106,16 +109,19 @@ #define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */ #endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */

-#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) +#if defined(CONFIG_TQM8541) || defined(CONFIG_TQM8555) || \ + defined(CONFIG_TQM8548) #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ -#endif /* CONFIG_TQM8541 || CONFIG_TQM8555 */ +#endif /* CONFIG_TQM8541 || CONFIG_TQM8555 || CONFIG_TQM8548 */

/* * Old TQM85xx boards have 'M' type Spansion Flashes from the S29GLxxxM * series while new boards have 'N' type Flashes from the S29GLxxxN * series, which have bigger sectors: 128 instead of 256 KB. */ -#undef CONFIG_TQM_FLASH_N_TYPE +#ifdef CONFIG_TQM8548 +#define CONFIG_TQM_FLASH_N_TYPE +#endif /* CONFIG_TQM8548 */

/* * Flash on the Local Bus @@ -127,6 +133,25 @@ #define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */ #define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */

+/* Default ORx timings are for <= 41.7 MHz Local Bus Clock. + * + * Note: According to timing specifications external addr latch delay + * (EAD, bit #0) must be set if Local Bus Clock is > 83 MHz. + * + * For other Local Bus Clocks see following table: + * + * Clock/MHz CFG_ORx_PRELIM + * 166 0x.....CA5 + * 133 0x.....C85 + * 100 0x.....C65 + * 83 0x.....FA2 + * 66 0x.....C82 + * 50 0x.....C60 + * 42 0x.....040 + * 33 0x.....030 + * 25 0x.....020 + * + */ #define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */ #define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */ #define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */ @@ -136,6 +161,7 @@ #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ #define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash*/ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* speed up output to Flash */

#define CFG_MAX_FLASH_BANKS 2 /* number of banks */ #define CFG_MAX_FLASH_SECT 512 /* sectors per device */ @@ -145,6 +171,14 @@

#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */

+/* + * Note: when changing the Local Bus clock divider you have to + * change the timing values in CFG_ORx_PRELIM. + * + * LCRR[00:03] CLKDIV: System (CCB) clock divider. Valid values are 2, 4, 8. + * LCRR[16:17] EADC : External address delay cycles. It should be set to 2 + * for Local Bus Clock > 83.3 MHz. + */ #define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ @@ -296,6 +330,27 @@ #define CONFIG_HAS_ETH1 #define CONFIG_HAS_ETH2

+#ifdef CONFIG_TQM8548 +/* + * TQM8548 has 4 ethernet ports. 4 ETSEC's. + * + * On the STK85xx Starterkit the ETSEC3/4 ports are on an + * additional adapter (AIO) between module and Starterkit. + */ +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "TSEC2" +#define CONFIG_TSEC4 1 +#define CONFIG_TSEC4_NAME "TSEC3" +#define TSEC3_PHY_ADDR 4 +#define TSEC4_PHY_ADDR 5 +#define TSEC3_PHYIDX 0 +#define TSEC4_PHYIDX 0 +#define TSEC3_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define CONFIG_HAS_ETH3 +#define CONFIG_HAS_ETH4 +#endif /* CONFIG_TQM8548 */ + /* Options are TSEC[0-1], FEC */ #define CONFIG_ETHPRIME "TSEC0"

diff --git a/include/mpc85xx.h b/include/mpc85xx.h index 9dbc9a8..c2a7510 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -49,6 +49,7 @@ #define ORxG_ACS_DIV2 0x00000600 /* CS is output 1/2 a clock later*/ #define ORxG_CSNT 0x00000800 /* Chip Select Negation Time */

+#define ORxU_EAD 0x00000001 /* External addr latch delay */ #define ORxU_BI 0x00000100 /* Burst Inhibit */ #define ORxU_AM_MSK 0xffff8000 /* Address Mask Mask */

@@ -66,4 +67,12 @@ #define P2SZ_TO_AM(s) ((~((s) - 1)) & 0xffff8000) /* must be pow of 2 */ #define MEG_TO_AM(m) P2SZ_TO_AM((m) << 20)

+/* Clock Ratio Register */ +#define LCRR_DBYP 0x80000000 /* PLL bypass */ +#define LCRR_EADC_MSK 0x00030000 /* external address delay cycles mask */ +#define LCRR_EADC_4 0x00000000 /* 4 cycles */ +#define LCRR_EADC_1 0x00010000 /* 1 cycle */ +#define LCRR_EADC_2 0x00020000 /* 2 cycles */ +#define LCRR_EADC_3 0x00030000 /* 3 cycles */ + #endif /* __MPC85xx_H__ */

-- 1.5.2.2

Wolfgang Grandegger

8:12 p.m.

New subject: [U-Boot-Users] [PATCH] TQM8548: PCI express support

This patch adds support for PCI express cards. The board support now uses common FSL PCI init code, for both, PCI and PCIe on all TQM85xx modules.

Signed-off-by: Thomas Waehner thomas.waehner@tqs.de Signed-off-by: Wolfgang Grandegger wg@grandegger.com --- board/tqc/tqm85xx/law.c | 15 +++- board/tqc/tqm85xx/tlb.c | 30 ++++++ board/tqc/tqm85xx/tqm85xx.c | 205 ++++++++++++++++++++++++++++++++++++------- include/configs/TQM85xx.h | 35 +++++++- 4 files changed, 249 insertions(+), 36 deletions(-)

diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c index ad35464..bec1ed5 100644 --- a/board/tqc/tqm85xx/law.c +++ b/board/tqc/tqm85xx/law.c @@ -32,11 +32,11 @@ * * 0x0000_0000 0x7fff_ffff DDR 2G * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M - * 0xc000_0000 0xdfff_ffff RapidIO 512M + * 0xc000_0000 0xdfff_ffff RapidIO or PCI express 512M * 0xe000_0000 0xe000_ffff CCSR 1M * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M * 0xe300_0000 0xe3ff_ffff CAN 16M - * 0xf800_0000 0xf80f_ffff BCSR 1M + * 0xef00_0000 0xefff_ffff PCI express IO 16M * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M * * Notes: @@ -49,10 +49,17 @@ struct law_entry law_table[] = { SET_LAW_ENTRY (2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), SET_LAW_ENTRY (3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), SET_LAW_ENTRY (4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAWAR_SIZE_512M, LAW_TRGT_IF_RIO), +#ifdef CONFIG_PCIE1 + SET_LAW_ENTRY (5, CFG_PCIE1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), +#else /* !CONFIG_PCIE1 */ + SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), +#endif /* CONFIG_PCIE1 */ #ifdef CONFIG_CAN_DRIVER - SET_LAW_ENTRY (6, CFG_CAN_BASE, LAWAR_SIZE_16M, LAW_TRGT_IF_LBC), + SET_LAW_ENTRY (6, CFG_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), #endif /* CONFIG_CAN_DRIVER */ +#ifdef CONFIG_PCIE1 + SET_LAW_ENTRY (7, CFG_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1), +#endif /* CONFIG_PCIE */ };

int num_law_entries = ARRAY_SIZE (law_table); diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c index dc36201..7c4b9a1 100644 --- a/board/tqc/tqm85xx/tlb.c +++ b/board/tqc/tqm85xx/tlb.c @@ -74,6 +74,24 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 3, BOOKE_PAGESZ_256M, 1),

+#ifdef CONFIG_PCIE1 + /* + * TLB 4: 256M Non-cacheable, guarded + * 0xc0000000 256M PCI express MEM First half + */ + SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 256M Non-cacheable, guarded + * 0xd0000000 256M PCI express MEM Second half + */ + SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE + 0x10000000, + CFG_PCIE1_MEM_BASE + 0x10000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), +#else /* !CONFIG_PCIE */ /* * TLB 4: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half @@ -90,6 +108,7 @@ struct fsl_e_tlb_entry tlb_table[] = { CFG_RIO_MEM_BASE + 0x10000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 5, BOOKE_PAGESZ_256M, 1), +#endif /* CONFIG_PCIE */

/* * TLB 6: 64M Non-cacheable, guarded @@ -116,6 +135,17 @@ struct fsl_e_tlb_entry tlb_table[] = { CFG_DDR_SDRAM_BASE + 0x10000000, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 8, BOOKE_PAGESZ_256M, 1), + +#ifdef CONFIG_PCIE1 + /* + * TLB 9: 16M Non-cacheable, guarded + * 0xef000000 16M PCI express IO + */ + SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 9, BOOKE_PAGESZ_16M, 1), +#endif /* CONFIG_PCIE */ + };

int num_tlb_entries = ARRAY_SIZE (tlb_table); diff --git a/board/tqc/tqm85xx/tqm85xx.c b/board/tqc/tqm85xx/tqm85xx.c index 4d06599..6459b7a 100644 --- a/board/tqc/tqm85xx/tqm85xx.c +++ b/board/tqc/tqm85xx/tqm85xx.c @@ -36,6 +36,7 @@ #include <pci.h> #include <asm/processor.h> #include <asm/immap_85xx.h> +#include <asm/immap_fsl_pci.h> #include <asm/io.h> #include <ioports.h> #include <flash.h> @@ -257,13 +258,6 @@ int checkboard (void) } putc ('\n');

-#ifdef CONFIG_PCI - printf ("PCI1: 32 bit, %d MHz (compiled)\n", - CONFIG_SYS_CLK_FREQ / 1000000); -#else - printf ("PCI1: disabled\n"); -#endif - /* * Initialize local bus. */ @@ -539,38 +533,180 @@ void local_bus_init (void) #endif /* CONFIG_CAN_DRIVER */ }

-#if defined(CONFIG_PCI) /* * Initialize PCI Devices, report devices found. */ +static int first_free_busno;

-#ifndef CONFIG_PCI_PNP -static struct pci_config_table pci_mpc85xxads_config_table[] = { - {PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, PCI_ANY_ID, - PCI_IDSEL_NUMBER, PCI_ANY_ID, - pci_cfgfunc_config_device, {PCI_ENET0_IOADDR, - PCI_ENET0_MEMADDR, - PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER}}, - {} -}; -#endif +#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) +static struct pci_controller pci1_hose; +#endif /* CONFIG_PCI || CONFIG_PCI1 */

-static struct pci_controller hose = { -#ifndef CONFIG_PCI_PNP - config_table:pci_mpc85xxads_config_table, +#ifdef CONFIG_PCIE1 +static struct pci_controller pcie1_hose; +#endif /* CONFIG_PCIE1 */ + +static inline void init_pci1(void) +{ + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); +#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCI1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pci1_hose; + + /* PORDEVSR[15] */ + uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; + /* PORDEVSR[14] */ + uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; + /* PORPLLSR[16] */ + uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; + + uint pci_agent = (host_agent == 3) || (host_agent == 4 ) || + (host_agent == 6); + + uint pci_speed = CONFIG_SYS_CLK_FREQ; /* PCI PSPEED in [4:5] */ + + if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { + printf ("PCI1: %d bit, %s MHz, %s, %s, %s\n", + (pci_32) ? 32 : 64, + (pci_speed == 33333333) ? "33" : + (pci_speed == 66666666) ? "66" : "unknown", + pci_clk_sel ? "sync" : "async", + pci_agent ? "agent" : "host", + pci_arb ? "arbiter" : "external-arbiter"); + + + /* inbound */ + pci_set_region (hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + + /* outbound memory */ + pci_set_region (hose->regions + 1, + CFG_PCI1_MEM_BASE, + CFG_PCI1_MEM_PHYS, + CFG_PCI1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region (hose->regions + 2, + CFG_PCI1_IO_BASE, + CFG_PCI1_IO_PHYS, + CFG_PCI1_IO_SIZE, + PCI_REGION_IO); + + hose->region_count = 3; + + hose->first_busno = first_free_busno; + pci_setup_indirect (hose, (int)&pci->cfg_addr, + (int)&pci->cfg_data); + + fsl_pci_init (hose); + + printf (" PCI on bus %02x..%02x\n", + hose->first_busno, hose->last_busno); + + first_free_busno = hose->last_busno + 1; +#ifdef CONFIG_PCIX_CHECK + if (!(gur->pordevsr & PORDEVSR_PCI)) { + ushort reg16 = + PCI_X_CMD_MAX_SPLIT | PCI_X_CMD_MAX_READ | + PCI_X_CMD_ERO | PCI_X_CMD_DPERR_E; + uint dev = PCI_BDF(hose->first_busno, 0, 0); + + /* PCI-X init */ + if (CONFIG_SYS_CLK_FREQ < 66000000) + puts ("PCI-X will only work at 66 MHz\n"); + + pci_hose_write_config_word (hose, dev, PCIX_COMMAND, + reg16); + } #endif -}; + } else { + puts ("PCI1: disabled\n"); + } +#else /* !(CONFIG_PCI || CONFIG_PCI1) */ + gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ +#endif /* CONFIG_PCI || CONFIG_PCI1) */ +} + +static inline void init_pcie1(void) +{ + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); +#ifdef CONFIG_PCIE1 + uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; + uint host_agent = (gur->porbmsr & MPC85xx_PORBMSR_HA) >> 16; + volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *)CFG_PCIE1_ADDR; + extern void fsl_pci_init(struct pci_controller *hose); + struct pci_controller *hose = &pcie1_hose; + int pcie_ep = (host_agent == 0) || (host_agent == 2 ) || + (host_agent == 3); + + int pcie_configured = io_sel >= 1; + + if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ + printf ("PCIe: %s, base address %x", + pcie_ep ? "End point" : "Root complex", (uint)pci); + + if (pci->pme_msg_det) { + pci->pme_msg_det = 0xffffffff; + debug (", with errors. Clearing. Now 0x%08x", + pci->pme_msg_det); + } + puts ("\n"); + + /* inbound */ + pci_set_region (hose->regions + 0, + CFG_PCI_MEMORY_BUS, + CFG_PCI_MEMORY_PHYS, + CFG_PCI_MEMORY_SIZE, + PCI_REGION_MEM | PCI_REGION_MEMORY); + + /* outbound memory */ + pci_set_region (hose->regions + 1, + CFG_PCIE1_MEM_BASE, + CFG_PCIE1_MEM_PHYS, + CFG_PCIE1_MEM_SIZE, + PCI_REGION_MEM); + + /* outbound io */ + pci_set_region (hose->regions + 2, + CFG_PCIE1_IO_BASE, + CFG_PCIE1_IO_PHYS, + CFG_PCIE1_IO_SIZE, + PCI_REGION_IO);

-#endif /* CONFIG_PCI */ + hose->region_count = 3; + + hose->first_busno = first_free_busno; + pci_setup_indirect(hose, (int)&pci->cfg_addr, + (int)&pci->cfg_data); + + fsl_pci_init (hose); + printf (" PCIe on bus %02x..%02x\n", + hose->first_busno, hose->last_busno); + + first_free_busno = hose->last_busno + 1; + + } else { + printf ("PCIe: disabled\n"); + } +#else /* !CONFIG_PCIE1 */ + gur->devdisr |= MPC85xx_DEVDISR_PCIE; /* disable */ +#endif /* CONFIG_PCIE1 */ +}

void pci_init_board (void) { -#ifdef CONFIG_PCI - pci_mpc85xx_init (&hose); -#endif /* CONFIG_PCI */ + init_pci1(); + init_pcie1(); }

-#if defined(CONFIG_OF_BOARD_SETUP) +#ifdef CONFIG_OF_BOARD_SETUP void ft_board_setup (void *blob, bd_t *bd) { int node, tmp[2]; @@ -581,16 +717,23 @@ void ft_board_setup (void *blob, bd_t *bd) node = fdt_path_offset (blob, "/aliases"); tmp[0] = 0; if (node >= 0) { -#ifdef CONFIG_PCI +#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) path = fdt_getprop (blob, node, "pci0", NULL); if (path) { - tmp[1] = hose.last_busno - hose.first_busno; + tmp[1] = pci1_hose.last_busno - pci1_hose.first_busno; do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1); } -#endif +#endif /* CONFIG_PCI || CONFIG_PCI1 */ +#ifdef CONFIG_PCIE1 + path = fdt_getprop (blob, node, "pci1", NULL); + if (path) { + tmp[1] = pcie1_hose.last_busno - pcie1_hose.first_busno; + do_fixup_by_path (blob, path, "bus-range", &tmp, 8, 1); + } +#endif /* CONFIG_PCIE1 */ } } -#endif +#endif /* CONFIG_OF_BOARD_SETUP */

#ifdef CONFIG_BOARD_EARLY_INIT_R int board_early_init_r (void) diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index da06ffd..6e62c34 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -42,6 +42,14 @@ #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */

#define CONFIG_PCI +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_PCIX_CHECK /* PCIX olny works at 66 MHz */ +#ifdef CONFIG_TQM8548 +#define CONFIG_PCI1 +#define CONFIG_PCIE1 +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ +#endif + #define CONFIG_TSEC_ENET /* tsec ethernet support */

#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ @@ -97,6 +105,10 @@ #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */

+#define CFG_PCI1_ADDR (CFG_CCSRBAR + 0x8000) +#define CFG_PCI2_ADDR (CFG_CCSRBAR + 0x9000) +#define CFG_PCIE1_ADDR (CFG_CCSRBAR + 0xa000) + /* * DDR Setup */ @@ -282,10 +294,12 @@ #define CFG_DTT_LOW_TEMP -30 #define CFG_DTT_HYSTERESIS 3

+#ifndef CONFIG_PCIE1 /* RapidIO MMU */ #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE -#define CFG_RIO_MEM_SIZE 0x20000000 /* 128M */ +#define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ +#endif /* CONFIG_PCIE1 */

/* * General PCI @@ -298,6 +312,25 @@ #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */

+/* PCI view of System Memory */ +#define CFG_PCI_MEMORY_BUS 0x00000000 +#define CFG_PCI_MEMORY_PHYS 0x00000000 +#define CFG_PCI_MEMORY_SIZE 0x80000000 + +#ifdef CONFIG_PCIE1 +/* + * General PCI express + * Addresses are mapped 1-1. + */ +#define CFG_PCIE1_MEM_BASE 0xc0000000 +#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE +#define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CFG_PCIE1_IO_BASE 0xef000000 +#define CFG_PCIE1_IO_PHYS CFG_PCIE1_IO_BASE +#define CFG_PCIE1_IO_SIZE 0x1000000 /* 16M */ + +#endif /* CONFIG_PCIE1 */ + #if defined(CONFIG_PCI)

#define CONFIG_PCI_PNP /* do pci plug-and-play */

-- 1.5.2.2

Wolfgang Grandegger

8:12 p.m.

New subject: [U-Boot-Users] [PATCH] TQM85xx: NAND support via local bus UPMB

This patch adds support for NAND FLASH on the TQM8548. It is disabled by default and can be enabled for the TQM8548 modules. Note that the R/B pin is not supported by that module requiring to use the specified maximum delay time.

Note: With NAND support enabled the size of the U-Boot image exceeds 256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk, doubling the image size :-(.

Signed-off-by: Thomas Waehner thomas.waehner@tqs.de Signed-off-by: Wolfgang Grandegger wg@grandegger.com --- board/tqc/tqm85xx/Makefile | 8 +- board/tqc/tqm85xx/law.c | 6 +- board/tqc/tqm85xx/nand.c | 597 ++++++++++++++++++++++++++++++++++++++++++++ board/tqc/tqm85xx/tlb.c | 2 +- include/configs/TQM85xx.h | 80 ++++++- include/mpc85xx.h | 4 + 6 files changed, 689 insertions(+), 8 deletions(-) create mode 100644 board/tqc/tqm85xx/nand.c

diff --git a/board/tqc/tqm85xx/Makefile b/board/tqc/tqm85xx/Makefile index 52f5ef9..8ea07f2 100644 --- a/board/tqc/tqm85xx/Makefile +++ b/board/tqc/tqm85xx/Makefile @@ -25,8 +25,14 @@ include $(TOPDIR)/config.mk

LIB = $(obj)lib$(BOARD).a

-COBJS := $(BOARD).o sdram.o law.o tlb.o +COBJS-y += $(BOARD).o +COBJS-y += sdram.o +COBJS-y += law.o +COBJS-y += tlb.o

+COBJS-$(CONFIG_NAND) += nand.o + +COBJS := $(COBJS-y) SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) SOBJS := $(addprefix $(obj),$(SOBJS)) diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c index bec1ed5..914ce68 100644 --- a/board/tqc/tqm85xx/law.c +++ b/board/tqc/tqm85xx/law.c @@ -35,7 +35,7 @@ * 0xc000_0000 0xdfff_ffff RapidIO or PCI express 512M * 0xe000_0000 0xe000_ffff CCSR 1M * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xe300_0000 0xe3ff_ffff CAN 16M + * 0xe300_0000 0xe3ff_ffff CAN and NAND Flash 16M * 0xef00_0000 0xefff_ffff PCI express IO 16M * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M * @@ -54,9 +54,9 @@ struct law_entry law_table[] = { #else /* !CONFIG_PCIE1 */ SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), #endif /* CONFIG_PCIE1 */ -#ifdef CONFIG_CAN_DRIVER +#if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND) SET_LAW_ENTRY (6, CFG_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), -#endif /* CONFIG_CAN_DRIVER */ +#endif /* CONFIG_CAN_DRIVER || CONFIG_NAND */ #ifdef CONFIG_PCIE1 SET_LAW_ENTRY (7, CFG_PCIE1_IO_BASE, LAW_SIZE_16M, LAW_TRGT_IF_PCIE_1), #endif /* CONFIG_PCIE */ diff --git a/board/tqc/tqm85xx/nand.c b/board/tqc/tqm85xx/nand.c new file mode 100644 index 0000000..4ae8475 --- /dev/null +++ b/board/tqc/tqm85xx/nand.c @@ -0,0 +1,597 @@ +/* + * (C) Copyright 2008 Wolfgang Grandegger wg@denx.de + * + * (C) Copyright 2006 + * Thomas Waehner, TQ-System GmbH, thomas.waehner@tqs.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/immap_85xx.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/io.h> +#include <asm/errno.h> +#include <ioports.h> + +#include <nand.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern uint get_lbc_clock (void); + +/* index of UPM RAM array run pattern for NAND command cycle */ +#define CFG_NAND_UPM_WRITE_CMD_OFS 0x08 + +/* index of UPM RAM array run pattern for NAND address cycle */ +#define CFG_NAND_UPM_WRITE_ADDR_OFS 0x10 + +/* Structure for table with supported UPM timings */ +struct upm_freq { + ulong freq; + const ulong *upm_patt; + uchar gpl4_disable; + uchar ehtr; + uchar ead; +}; + +/* NAND-FLASH UPM tables for TQM85XX according to TQM8548.pq.timing.101.doc */ + +/* UPM pattern for bus clock = 25 MHz */ +static const ulong upm_patt_25[] = { + /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff32000, 0x0fa32000, 0x3fb32005, 0xfffffc00, + /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 33.3 MHz */ +static const ulong upm_patt_33[] = { + /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00, + /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 41.7 MHz */ +static const ulong upm_patt_42[] = { + /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff32000, 0x0fa32100, 0x3fb32005, 0xfffffc00, + /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff2c30, 0x00ff2c30, 0x0fff2c35, 0xfffffc00, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3ec30, 0x00f3ec30, 0x0ff3ec35, 0xfffffc00, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f32c00, 0x00f32c00, 0x0ff32c05, 0xfffffc00, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 50 MHz */ +static const ulong upm_patt_50[] = { + /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff33000, 0x0fa33100, 0x0fa33005, 0xfffffc00, + /* 0x04 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c35, 0xfffffc00, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc35, 0xfffffc00, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c05, 0xfffffc00, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 66.7 MHz */ +static const ulong upm_patt_67[] = { + /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000, + /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff3d30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3fd30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f33d00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 83.3 MHz */ +static const ulong upm_patt_83[] = { + /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff33000, 0x0fe33000, 0x0fa33100, 0x0fa33000, + /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff3e30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3fe30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f33e00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 100 MHz */ +static const ulong upm_patt_100[] = { + /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33200, 0x0fa33000, + /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff3f30, 0x00ff3c30, 0x0fff3c30, 0x0fff3c35, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3ff30, 0x00f3fc30, 0x0ff3fc30, 0x0ff3fc35, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f33f00, 0x00f33c00, 0x0ff33c00, 0x0ff33c05, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 133.3 MHz */ +static const ulong upm_patt_133[] = { + /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff33100, 0x0fe33000, 0x0fa33300, 0x0fa33000, + /* 0x04 */ 0x0fa33000, 0x0fa33005, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff3f30, 0x00ff3d30, 0x0fff3d30, 0x0fff3c35, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3ff30, 0x00f3fd30, 0x0ff3fd30, 0x0ff3fc35, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f33f00, 0x00f33d00, 0x0ff33d00, 0x0ff33c05, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* UPM pattern for bus clock = 166.7 MHz */ +static const ulong upm_patt_167[] = { + /* Offset *//* UPM Read Single RAM array entry -> NAND Read Data */ + /* 0x00 */ 0x0ff33200, 0x0fe33000, 0x0fa33300, 0x0fa33300, + /* 0x04 */ 0x0fa33005, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write CMD */ + /* 0x08 */ 0x00ff3f30, 0x00ff3f30, 0x0fff3e30, 0xffff3c35, + /* 0x0C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Read Burst RAM array entry -> NAND Write ADDR */ + /* 0x10 */ 0x00f3ff30, 0x00f3ff30, 0x0ff3fe30, 0x0ff3fc35, + /* 0x14 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Single RAM array entry -> NAND Write Data */ + /* 0x18 */ 0x00f33f00, 0x00f33f00, 0x0ff33e00, 0x0ff33c05, + /* 0x1C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + + /* UPM Write Burst RAM array entry -> unused */ + /* 0x20 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x24 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x28 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x2C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Refresh Timer RAM array entry -> unused */ + /* 0x30 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x34 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc00, + /* 0x38 */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, + + /* UPM Exception RAM array entry -> unsused */ + /* 0x3C */ 0xfffffc00, 0xfffffc00, 0xfffffc00, 0xfffffc01, +}; + +/* Supported UPM timings */ +struct upm_freq upm_freq_table[] = { + /* nominal freq. | ptr to table | GPL4 dis. | EHTR | EAD */ + {25000000, upm_patt_25, 1, 0, 0}, + {33333333, upm_patt_33, 1, 0, 0}, + {41666666, upm_patt_42, 1, 0, 0}, + {50000000, upm_patt_50, 0, 0, 0}, + {66666666, upm_patt_67, 0, 0, 0}, + {83333333, upm_patt_83, 0, 0, 0}, + {100000000, upm_patt_100, 0, 1, 1}, + {133333333, upm_patt_133, 0, 1, 1}, + {166666666, upm_patt_167, 0, 1, 1}, +}; + +#define UPM_FREQS (sizeof(upm_freq_table) / sizeof(struct upm_freq)) + +static int nand_upm_init_done; + +/* nand flash base address */ +static u8 hwctl; + +/* + * write into UPMB ram + */ +static void upmb_write (u_char addr, ulong val) +{ + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + + out_be32 (&lbc->mdr, val); + + out_be32 (&lbc->mbmr, + (in_be32 (&lbc->mbmr) & ~(MxMR_OP_NORM | MxMR_MAD)) | + MxMR_OP_WARR | (addr & MxMR_MAD)); + + /* dummy access to perform write */ + out_8 ((void __iomem *)CFG_NAND0_BASE, 0); + + out_be32 (&lbc->mbmr, + (in_be32 (&lbc->mbmr) & ~MxMR_OP_WARR) | MxMR_OP_NORM); +} + +/* + * Initialize UPM for NAND flash access. + */ +void nand_upm_init (void) +{ + uint i; + uint or3 = CFG_OR3_PRELIM; + uint clock = get_lbc_clock (); + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + volatile const ulong *upm_patt = NULL; + + lbc->br3 = 0; /* disable bank and reset all bits */ + + lbc->br3 = CFG_BR3_PRELIM; + + /* + * Search appropriate UPM table for bus clock. + * If the bus clock exceeds a tolerated value, take the UPM timing for + * the next higher supported frequency to ensure that access works + * (even the access may be slower then). + */ + for (i = 0; (i < UPM_FREQS) && (clock > upm_freq_table[i].freq); i++) + ; + + if (i >= UPM_FREQS) + /* no valid entry found */ + /* take last entry with configuration for max. bus clock */ + i--; + + if (upm_freq_table[i].ehtr) { + /* EHTR must be set due to TQM8548 timing specification */ + or3 |= ORxU_EHTR; + } + if (upm_freq_table[i].ead) + /* EAD must be set due to TQM8548 timing specification */ + or3 |= ORxU_EAD; + + lbc->or3 = or3; + + /* Assign address of table */ + upm_patt = upm_freq_table[i].upm_patt; + + for (i = 0; i < 64; i++) { + upmb_write (i, *upm_patt); + upm_patt++; + } + + /* Put UPM back to normal operation mode */ + if (upm_freq_table[i].gpl4_disable) + /* GPL4 must be disabled according to timing specification */ + lbc->mbmr = MxMR_OP_NORM | MxMR_GPL4_DIS; + + nand_upm_init_done = 1; + + return; +} + +/* + * nand_upm_exec - exectutes an UPM run pattern + */ +void nand_upm_exec (struct mtd_info *mtd, int offset, unsigned char byte) +{ + struct nand_chip *chip = mtd->priv; + volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); + int i; + + /* Put UPM to run pattern mode for NAND command write */ + out_be32 (&lbc->mbmr, + (in_be32 (&lbc->mbmr) & ~(MxMR_OP_MSK | MxMR_MAD)) | + MxMR_OP_RUN | offset); + + /* Just output address on AD[0..7] (=MSB) */ + out_be32 (&lbc->mar, byte << 24); + + /* UPM dummy write */ + out_8 (chip->IO_ADDR_W, 0x0); + + /* give upm time to run pattern */ + for (i = 0; i < 300; i++) + asm ("nop"); + + /* Put UPM back to normal operation mode */ + out_be32 (&lbc->mbmr, + (in_be32 (&lbc->mbmr) & ~MxMR_OP_MSK) | MxMR_OP_NORM); +} + +static void upmnand_hwcontrol (struct mtd_info *mtdinfo, int cmd) +{ + switch (cmd) { + case NAND_CTL_SETCLE: + hwctl |= 0x1; + break; + case NAND_CTL_CLRCLE: + hwctl &= ~0x1; + break; + + case NAND_CTL_SETALE: + hwctl |= 0x2; + break; + + case NAND_CTL_CLRALE: + hwctl &= ~0x2; + break; + } +} + +static void upmnand_write_byte (struct mtd_info *mtdinfo, u_char byte) +{ + struct nand_chip *chip = mtdinfo->priv; + + if (hwctl & 0x1) + nand_upm_exec (mtdinfo, CFG_NAND_UPM_WRITE_CMD_OFS, byte); + else if (hwctl & 0x2) + nand_upm_exec (mtdinfo, CFG_NAND_UPM_WRITE_ADDR_OFS, byte); + else + out_8 (chip->IO_ADDR_W, byte); +} + +static u_char upmnand_read_byte (struct mtd_info *mtdinfo) +{ + struct nand_chip *chip = mtdinfo->priv; + u8 val = in_8 (chip->IO_ADDR_R); + + return val; +} + +#ifdef CONFIG_HAVE_NAND_RB +static int tqm_dev_ready (struct mtd_info *mtdinfo) +{ + /** FIXME query GPIO PIN where NAND R/B is attached to */ + + /* constant delay (see also tR in the datasheet) */ + udelay (NAND_BIG_DELAY_US); + return 1; +} +#endif /* CONFIG_HAVE_NAND_RB */ + +#ifndef CONFIG_NAND_SPL +static void tqm_read_buf (struct mtd_info *mtdinfo, uint8_t * buf, int len) +{ + struct nand_chip *chip = mtdinfo->priv; + int i; + + for (i = 0; i < len; i++) + buf[i] = in_8 (chip->IO_ADDR_R); +} + +static void tqm_write_buf (struct mtd_info *mtdinfo, const uint8_t * buf, + int len) +{ + struct nand_chip *chip = mtdinfo->priv; + int i; + + for (i = 0; i < len; i++) + out_8 (chip->IO_ADDR_W, buf[i]); +} + +static int tqm_verify_buf (struct mtd_info *mtdinfo, const uint8_t * buf, + int len) +{ + struct nand_chip *chip = mtdinfo->priv; + int i; + + for (i = 0; i < len; i++) { + if (buf[i] != in_8 (chip->IO_ADDR_R)) + return -EFAULT; + } + + return 0; +} +#endif /* !CONFIG_NAND_SPL */ + +void board_nand_select_device (struct nand_chip *nand, int chip) +{ +} + +int board_nand_init (struct nand_chip *nand) +{ + /* initialize LBC3 for nand flash */ + + if (!nand_upm_init_done) + nand_upm_init (); + + nand->eccmode = NAND_ECC_SOFT; + + nand->hwcontrol = upmnand_hwcontrol; + nand->read_byte = upmnand_read_byte; + nand->write_byte = upmnand_write_byte; + nand->chip_delay = NAND_BIG_DELAY_US; +#ifdef CONFIG_HAVE_NAND_RB + nand->dev_ready = tqm_dev_ready; +#endif /* CONFIG_HAVE_NAND_RB */ + +#ifndef CONFIG_NAND_SPL + nand->write_buf = tqm_write_buf; + nand->read_buf = tqm_read_buf; + nand->verify_buf = tqm_verify_buf; +#endif /* CONFIG_NAND_SPL */ + + board_nand_select_device (nand, 0); + return 0; +} diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c index 7c4b9a1..7f4efc1 100644 --- a/board/tqc/tqm85xx/tlb.c +++ b/board/tqc/tqm85xx/tlb.c @@ -114,7 +114,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * TLB 6: 64M Non-cacheable, guarded * 0xe0000000 1M CCSRBAR * 0xe2000000 16M PCI1 IO - * 0xe3000000 16M CAN + * 0xe3000000 16M CAN and NAND Flash */ SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 6e62c34..1e58066 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -55,6 +55,14 @@ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */

/* + * NAND flash support (disabled by default) + * + * Warning: NAND support will likely increase the U-Boot image size + * to more than 256 KB. Please adjust TEXT_BASE if necessary. + */ +#undef CONFIG_NAND + +/* * MPC8540 and MPC8548 don't have CPM module */ #if !defined(CONFIG_MPC8540) && !defined(CONFIG_MPC8548) @@ -205,8 +213,8 @@ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET

-#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon */ -#define CFG_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ +#define CFG_MONITOR_LEN (~TEXT_BASE + 1)/* Reserved for Monitor */ +#define CFG_MALLOC_LEN (384 * 1024) /* Reserved for malloc */

/* Serial Port */ #if defined(CONFIG_TQM8560) @@ -253,8 +261,8 @@ #define CONFIG_OF_STDOUT_VIA_ALIAS 1

/* CAN */ -#ifdef CONFIG_CAN_DRIVER #define CFG_CAN_BASE 0xE3000000 /* CAN base address */ +#ifdef CONFIG_CAN_DRIVER #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 KiB address mask */ #define CFG_OR2_CAN (CFG_CAN_OR_AM | ORxU_BI) #define CFG_BR2_CAN ((CFG_CAN_BASE & BRx_BA_MSK) | \ @@ -301,6 +309,52 @@ #define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ #endif /* CONFIG_PCIE1 */

+/* NAND FLASH */ +#ifdef CONFIG_NAND + +#undef CFG_NAND_LEGACY + +/* use JFFS2 ECC */ +#define CONFIG_MTD_NAND_ECC_JFFS2 1 + +/* address distance between chip selects */ +#define CFG_NAND_SELECT_DEVICE 1 +#define CFG_NAND_CS_DIST 0x200 + +#define CFG_NAND_SIZE 0x8000 +#define CFG_NAND0_BASE 0xE3010000 +#define CFG_NAND1_BASE (CFG_NAND0_BASE + CFG_NAND_CS_DIST) +#define CFG_NAND2_BASE (CFG_NAND1_BASE + CFG_NAND_CS_DIST) +#define CFG_NAND3_BASE (CFG_NAND2_BASE + CFG_NAND_CS_DIST) + +#define CFG_MAX_NAND_DEVICE 2 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS 1 + +#if (CFG_MAX_NAND_DEVICE == 1) +#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE } +#elif (CFG_MAX_NAND_DEVICE == 2) +#define CFG_NAND_QUIET_TEST 1 +#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \ + CFG_NAND1_BASE, \ +} +#elif (CFG_MAX_NAND_DEVICE == 4) +#define CFG_NAND_QUIET_TEST 1 +#define CFG_NAND_BASE_LIST { CFG_NAND0_BASE, \ + CFG_NAND1_BASE, \ + CFG_NAND2_BASE, \ + CFG_NAND3_BASE, \ +} +#endif + +/* CS3 for NAND Flash */ +#define CFG_BR3_PRELIM ((CFG_NAND0_BASE & BRx_BA_MSK) | BRx_PS_8 | \ + BRx_MS_UPMB | BRx_V ) +#define CFG_OR3_PRELIM (P2SZ_TO_AM(CFG_NAND_SIZE) | ORxU_BI) + +#define NAND_BIG_DELAY_US 25 /* max tR for Samsung devices */ + +#endif /* CONFIG_NAND */ + /* * General PCI * Addresses are mapped 1-1. @@ -486,6 +540,26 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME

+#ifdef CONFIG_NAND +/* + * Use NAND-FLash as JFFS2 device + */ +#define CONFIG_CMD_NAND +#define CONFIG_CMD_JFFS2 + +#define CONFIG_JFFS2_NAND 1 + +#ifdef CONFIG_JFFS2_CMDLINE +#define MTDIDS_DEFAULT "nand0=TQM85xx-nand" +#define MTDPARTS_DEFAULT "mtdparts=TQM85xx-nand:-" +#else +#define CONFIG_JFFS2_DEV "nand0" /* NAND device jffs2 lives on */ +#define CONFIG_JFFS2_PART_OFFSET 0 /* start of jffs2 partition */ +#define CONFIG_JFFS2_PART_SIZE 0x200000 /* size of jffs2 partition */ +#endif /* CONFIG_JFFS2_CMDLINE */ + +#endif /* CONFIG_NAND */ + /* * Command line configuration. */ diff --git a/include/mpc85xx.h b/include/mpc85xx.h index c2a7510..d76957d 100644 --- a/include/mpc85xx.h +++ b/include/mpc85xx.h @@ -50,6 +50,7 @@ #define ORxG_CSNT 0x00000800 /* Chip Select Negation Time */

#define ORxU_EAD 0x00000001 /* External addr latch delay */ +#define ORxU_EHTR 0x00000002 /* extended hold time on read */ #define ORxU_BI 0x00000100 /* Burst Inhibit */ #define ORxU_AM_MSK 0xffff8000 /* Address Mask Mask */

@@ -60,7 +61,10 @@ #define MxMR_DSx_2_CYCL 0x00400000 /* 2 cycle Disable Period */ #define MxMR_DSx_3_CYCL 0x00800000 /* 3 cycle Disable Period */ #define MxMR_DSx_4_CYCL 0x00C00000 /* 4 cycle Disable Period */ +#define MxMR_OP_MSK 0x30000000 /* Command opcode mask */ #define MxMR_OP_WARR 0x10000000 /* Write to Array */ +#define MxMR_OP_RARR 0x20000000 /* Write to Array */ +#define MxMR_OP_RUN 0x30000000 /* Write to Array */ #define MxMR_BSEL 0x80000000 /* Bus Select */

/* helpers to convert values into an OR address mask (GPCM mode) */

-- 1.5.2.2

Wolfgang Grandegger

8:12 p.m.

New subject: [U-Boot-Users] [PATCH] TQM85xx: Change memory map to support Flash memory > 128 MiB

Some TQM85xx boards could be equipped with up to 1 GiB (NOR) Flash memory. The current memory map only supports up to 128 MiB Flash. This patch adds the configuration option CONFIG_TQM_BIGFLASH. If set, up to 1 GiB flash is supported. To achieve this, the memory map has to be adjusted in great parts (for example the CCSRBAR is moved from 0xE0000000 to 0xA0000000).

If you want to boot Linux with CONFIG_TQM_BIGFLASH set, the new memory map also has to be considered in the kernel (changed CCSRBAR address, changed PCI IO base address, ...). Please use an appropriate Flat Device Tree blob (tqm8548.dtb).

Signed-off-by: Martin Krause martin.krause@tqs.de Signed-off-by: Wolfgang Grandegger wg@grandegger.com --- board/tqc/tqm85xx/law.c | 29 ++++++++++++-- board/tqc/tqm85xx/tlb.c | 97 +++++++++++++++++++++++++++++++++++++++++++++ include/configs/TQM85xx.h | 52 +++++++++++++++++++++--- 3 files changed, 167 insertions(+), 11 deletions(-)

diff --git a/board/tqc/tqm85xx/law.c b/board/tqc/tqm85xx/law.c index 914ce68..b4e663b 100644 --- a/board/tqc/tqm85xx/law.c +++ b/board/tqc/tqm85xx/law.c @@ -30,6 +30,8 @@ /* * LAW(Local Access Window) configuration: * + * Standard mapping: + * * 0x0000_0000 0x7fff_ffff DDR 2G * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M * 0xc000_0000 0xdfff_ffff RapidIO or PCI express 512M @@ -37,22 +39,41 @@ * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M * 0xe300_0000 0xe3ff_ffff CAN and NAND Flash 16M * 0xef00_0000 0xefff_ffff PCI express IO 16M - * 0xfe00_0000 0xffff_ffff FLASH (boot bank) 32M + * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 128M + * + * Big FLASH mapping: + * + * 0x0000_0000 0x7fff_ffff DDR 2G + * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xa000_ffff CCSR 1M + * 0xa200_0000 0xa2ff_ffff PCI1 IO 16M + * 0xa300_0000 0xa3ff_ffff CAN and NAND Flash 16M + * 0xaf00_0000 0xafff_ffff PCI express IO 16M + * 0xb000_0000 0xbfff_ffff RapidIO or PCI express 256M + * 0xc000_0000 0xffff_ffff FLASH (boot bank) 1G * * Notes: * CCSRBAR and L2-as-SRAM don't need a configured Local Access Window. * If flash is 8M at default position (last 8M), no LAW needed. */

+#ifdef CONFIG_TQM_BIGFLASH +#define LAW_3_SIZE LAW_SIZE_1G +#define LAW_5_SIZE LAW_SIZE_256M +#else +#define LAW_3_SIZE LAW_SIZE_128M +#define LAW_5_SIZE LAW_SIZE_512M +#endif + struct law_entry law_table[] = { SET_LAW_ENTRY (1, CFG_DDR_SDRAM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_DDR), SET_LAW_ENTRY (2, CFG_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW_ENTRY (3, CFG_LBC_FLASH_BASE, LAW_SIZE_128M, LAW_TRGT_IF_LBC), + SET_LAW_ENTRY (3, CFG_LBC_FLASH_BASE, LAW_3_SIZE, LAW_TRGT_IF_LBC), SET_LAW_ENTRY (4, CFG_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), #ifdef CONFIG_PCIE1 - SET_LAW_ENTRY (5, CFG_PCIE1_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW_ENTRY (5, CFG_PCIE1_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_PCIE_1), #else /* !CONFIG_PCIE1 */ - SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), + SET_LAW_ENTRY (5, CFG_RIO_MEM_BASE, LAW_5_SIZE, LAW_TRGT_IF_RIO), #endif /* CONFIG_PCIE1 */ #if defined(CONFIG_CAN_DRIVER) || defined(CONFIG_NAND) SET_LAW_ENTRY (6, CFG_CAN_BASE, LAW_SIZE_16M, LAW_TRGT_IF_LBC), diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c index 7f4efc1..380448a 100644 --- a/board/tqc/tqm85xx/tlb.c +++ b/board/tqc/tqm85xx/tlb.c @@ -44,6 +44,7 @@ struct fsl_e_tlb_entry tlb_table[] = { MAS3_SX | MAS3_SW | MAS3_SR, 0, 0, 0, BOOKE_PAGESZ_4K, 0),

+#ifndef CONFIG_TQM_BIGFLASH /* * TLB 0, 1: 128M Non-cacheable, guarded * 0xf8000000 128M FLASH @@ -146,6 +147,102 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 9, BOOKE_PAGESZ_16M, 1), #endif /* CONFIG_PCIE */

+#else /* CONFIG_TQM_BIGFLASH */ + + /* + * TLB 0,1,2,3: 1G Non-cacheable, guarded + * 0xc0000000 1G FLASH + * Out of reset this entry is only 4K. + */ + SET_TLB_ENTRY (1, CFG_FLASH_BASE, CFG_FLASH_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x10000000, + CFG_FLASH_BASE + 0x10000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 2, BOOKE_PAGESZ_256M, 1), + SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x20000000, + CFG_FLASH_BASE + 0x20000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 1, BOOKE_PAGESZ_256M, 1), + SET_TLB_ENTRY (1, CFG_FLASH_BASE + 0x30000000, + CFG_FLASH_BASE + 0x30000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 0, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 4: 256M Non-cacheable, guarded + * 0x80000000 256M PCI1 MEM First half + */ + SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS, CFG_PCI1_MEM_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 4, BOOKE_PAGESZ_256M, 1), + + /* + * TLB 5: 256M Non-cacheable, guarded + * 0x90000000 256M PCI1 MEM Second half + */ + SET_TLB_ENTRY (1, CFG_PCI1_MEM_PHYS + 0x10000000, + CFG_PCI1_MEM_PHYS + 0x10000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 5, BOOKE_PAGESZ_256M, 1), + +#ifdef CONFIG_PCIE1 + /* + * TLB 6: 256M Non-cacheable, guarded + * 0xc0000000 256M PCI express MEM First half + */ + SET_TLB_ENTRY (1, CFG_PCIE1_MEM_BASE, CFG_PCIE1_MEM_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 6, BOOKE_PAGESZ_256M, 1), +#else /* !CONFIG_PCIE */ + /* + * TLB 6: 256M Non-cacheable, guarded + * 0xb0000000 256M Rapid IO MEM First half + */ + SET_TLB_ENTRY (1, CFG_RIO_MEM_BASE, CFG_RIO_MEM_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 6, BOOKE_PAGESZ_256M, 1), + +#endif /* CONFIG_PCIE */ + + /* + * TLB 7: 64M Non-cacheable, guarded + * 0xa0000000 1M CCSRBAR + * 0xa2000000 16M PCI1 IO + * 0xa3000000 16M CAN and NAND Flash + */ + SET_TLB_ENTRY (1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 7, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 8+9: 512M DDR, cache disabled (needed for memory test) + * 0x00000000 512M DDR System memory + * Without SPD EEPROM configured DDR, this must be setup manually. + * Make sure the TLB count at the top of this table is correct. + * Likely it needs to be increased by two for these entries. + */ + SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE, CFG_DDR_SDRAM_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 8, BOOKE_PAGESZ_256M, 1), + + SET_TLB_ENTRY (1, CFG_DDR_SDRAM_BASE + 0x10000000, + CFG_DDR_SDRAM_BASE + 0x10000000, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 9, BOOKE_PAGESZ_256M, 1), + +#ifdef CONFIG_PCIE1 + /* + * TLB 10: 16M Non-cacheable, guarded + * 0xaf000000 16M PCI express IO + */ + SET_TLB_ENTRY (1, CFG_PCIE1_IO_BASE, CFG_PCIE1_IO_BASE, + MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, + 0, 10, BOOKE_PAGESZ_16M, 1), +#endif /* CONFIG_PCIE */ + +#endif /* CONFIG_TQM_BIGFLASH */ };

int num_tlb_entries = ARRAY_SIZE (tlb_table); diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 1e58066..eb044ab 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -54,6 +54,16 @@

#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */

+ /* + * Configuration for big NOR Flashes + * + * Define CONFIG_TQM_BIGFLASH for boards with more than 128 MiB NOR Flash. + * Please be aware, that this changes the whole memory map (new CCSRBAR + * address, etc). You have to use an adapted Linux kernel or FDT blob + * if this option is set. + */ +#undef CONFIG_TQM_BIGFLASH + /* * NAND flash support (disabled by default) * @@ -109,7 +119,11 @@ * actual resources get mapped (not physical addresses) */ #define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ +#ifdef CONFIG_TQM_BIGFLASH +#define CFG_CCSRBAR 0xA0000000 /* relocated CCSRBAR */ +#else /* !CONFIG_TQM_BIGFLASH */ #define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ +#endif /* CONFIG_TQM_BIGFLASH */ #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */

@@ -146,8 +160,13 @@ /* * Flash on the Local Bus */ +#ifdef CONFIG_TQM_BIGFLASH +#define CFG_FLASH0 0xE0000000 +#define CFG_FLASH1 0xC0000000 +#else /* !CONFIG_TQM_BIGFLASH */ #define CFG_FLASH0 0xFC000000 #define CFG_FLASH1 0xF8000000 +#endif /* CONFIG_TQM_BIGFLASH */ #define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 }

#define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */ @@ -172,10 +191,17 @@ * 25 0x.....020 * */ +#ifdef CONFIG_TQM_BIGFLASH +#define CFG_BR0_PRELIM 0xE0001801 /* port size 32bit */ +#define CFG_OR0_PRELIM 0xE0000040 /* 512MB Flash */ +#define CFG_BR1_PRELIM 0xC0001801 /* port size 32bit */ +#define CFG_OR1_PRELIM 0xE0000040 /* 512MB Flash */ +#else /* !CONFIG_TQM_BIGFLASH */ #define CFG_BR0_PRELIM 0xfc001801 /* port size 32bit */ #define CFG_OR0_PRELIM 0xfc000040 /* 64MB Flash */ #define CFG_BR1_PRELIM 0xf8001801 /* port size 32bit */ #define CFG_OR1_PRELIM 0xfc000040 /* 64MB Flash */ +#endif /* CONFIG_TQM_BIGFLASH */

#define CFG_FLASH_CFI /* flash is CFI compat. */ #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ @@ -206,7 +232,8 @@

#define CONFIG_L1_INIT_RAM #define CFG_INIT_RAM_LOCK 1 -#define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ +#define CFG_INIT_RAM_ADDR (CFG_CCSRBAR \ + + 0x04010000) /* Initial RAM address */ #define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */

#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ @@ -261,7 +288,8 @@ #define CONFIG_OF_STDOUT_VIA_ALIAS 1

/* CAN */ -#define CFG_CAN_BASE 0xE3000000 /* CAN base address */ +#define CFG_CAN_BASE (CFG_CCSRBAR \ + + 0x03000000) /* CAN base address */ #ifdef CONFIG_CAN_DRIVER #define CFG_CAN_OR_AM 0xFFFF8000 /* 32 KiB address mask */ #define CFG_OR2_CAN (CFG_CAN_OR_AM | ORxU_BI) @@ -304,9 +332,14 @@

#ifndef CONFIG_PCIE1 /* RapidIO MMU */ +#ifdef CONFIG_TQM_BIGFLASH +#define CFG_RIO_MEM_BASE 0xb0000000 /* base address */ +#define CFG_RIO_MEM_SIZE 0x10000000 /* 256M */ +#else /* !CONFIG_TQM_BIGFLASH */ #define CFG_RIO_MEM_BASE 0xc0000000 /* base address */ -#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE #define CFG_RIO_MEM_SIZE 0x20000000 /* 512M */ +#endif /* CONFIG_TQM_BIGFLASH */ +#define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE #endif /* CONFIG_PCIE1 */

/* NAND FLASH */ @@ -322,7 +355,7 @@ #define CFG_NAND_CS_DIST 0x200

#define CFG_NAND_SIZE 0x8000 -#define CFG_NAND0_BASE 0xE3010000 +#define CFG_NAND0_BASE (CFG_CCSRBAR + 0x03010000) #define CFG_NAND1_BASE (CFG_NAND0_BASE + CFG_NAND_CS_DIST) #define CFG_NAND2_BASE (CFG_NAND1_BASE + CFG_NAND_CS_DIST) #define CFG_NAND3_BASE (CFG_NAND2_BASE + CFG_NAND_CS_DIST) @@ -362,7 +395,7 @@ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 +#define CFG_PCI1_IO_BASE (CFG_CCSRBAR + 0x02000000) #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE #define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */

@@ -376,13 +409,18 @@ * General PCI express * Addresses are mapped 1-1. */ +#ifdef CONFIG_TQM_BIGFLASH +#define CFG_PCIE1_MEM_BASE 0xb0000000 +#define CFG_PCIE1_MEM_SIZE 0x10000000 /* 512M */ +#define CFG_PCIE1_IO_BASE 0xaf000000 +#else /* !CONFIG_TQM_BIGFLASH */ #define CFG_PCIE1_MEM_BASE 0xc0000000 -#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE #define CFG_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CFG_PCIE1_IO_BASE 0xef000000 +#endif /* CONFIG_TQM_BIGFLASH */ +#define CFG_PCIE1_MEM_PHYS CFG_PCIE1_MEM_BASE #define CFG_PCIE1_IO_PHYS CFG_PCIE1_IO_BASE #define CFG_PCIE1_IO_SIZE 0x1000000 /* 16M */ - #endif /* CONFIG_PCIE1 */

#if defined(CONFIG_PCI)

-- 1.5.2.2

Scott Wood

8:25 p.m.

New subject: [U-Boot-Users] [PATCH] TQM85xx: NAND support via local bus UPMB

On Wed, May 28, 2008 at 08:12:28PM +0200, Wolfgang Grandegger wrote:

...

This patch adds support for NAND FLASH on the TQM8548. It is disabled by default and can be enabled for the TQM8548 modules. Note that the R/B pin is not supported by that module requiring to use the specified maximum delay time.

Note: With NAND support enabled the size of the U-Boot image exceeds 256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk, doubling the image size :-(.

What does this do differently from the code in drivers/mtd/nand/fsl_upm.c?

How much of this is board-specific?

-Scott

Wolfgang Grandegger

8:38 p.m.

New subject: [U-Boot-Users] [PATCH] TQM85xx: NAND support via local bus UPMB

Scott Wood wrote:

...

On Wed, May 28, 2008 at 08:12:28PM +0200, Wolfgang Grandegger wrote:

...
This patch adds support for NAND FLASH on the TQM8548. It is disabled by default and can be enabled for the TQM8548 modules. Note that the R/B pin is not supported by that module requiring to use the specified maximum delay time.

Note: With NAND support enabled the size of the U-Boot image exceeds 256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk, doubling the image size :-(.

What does this do differently from the code in drivers/mtd/nand/fsl_upm.c?

Maybe it does not support multi banks on a NAND chip. I have to check.

...

How much of this is board-specific?

Well, I already gave drivers/mtd/nand/fsl_upm.c a try but was unable to get it working on this board. Therefore I decided to keep this known to work driver which we have already for a while.

With Linux, I had more success.

Wolfgang.

Anton Vorontsov

29 May 29 May

1:39 p.m.

New subject: [U-Boot-Users] [PATCH] TQM85xx: NAND support via local bus UPMB

On Wed, May 28, 2008 at 08:38:37PM +0200, Wolfgang Grandegger wrote:

...

Scott Wood wrote:

...
On Wed, May 28, 2008 at 08:12:28PM +0200, Wolfgang Grandegger wrote:

...
This patch adds support for NAND FLASH on the TQM8548. It is disabled by default and can be enabled for the TQM8548 modules. Note that the R/B pin is not supported by that module requiring to use the specified maximum delay time.

Note: With NAND support enabled the size of the U-Boot image exceeds 256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk, doubling the image size :-(.

What does this do differently from the code in drivers/mtd/nand/fsl_upm.c?

Maybe it does not support multi banks on a NAND chip. I have to check.

Me thinks that you'll have to call fsl_upm_nand_init() for each chip, and that's all. If not, feel free to patch it as you feel appropriate, I'll able to regress-test this driver on MPC8360E-RDK.

...

...
How much of this is board-specific?

Well, I already gave drivers/mtd/nand/fsl_upm.c a try but was unable to get it working on this board. Therefore I decided to keep this known to work driver which we have already for a while.

This isn't really an excuse to duplicate drivers. :-) This driver was tested on MPC8555 and MPC8360 CPUs, so it should work with no drastic changes. Some issues might still be there, and if so, fixes are highly appreciated.

...

With Linux, I had more success.

..especially if general idea works well, we should use single driver.

Thanks,

-- Anton Vorontsov email: cbouatmailru@gmail.com irc://irc.freenode.net/bd2

Wolfgang Grandegger

1:58 p.m.

New subject: [U-Boot-Users] [PATCH] TQM85xx: NAND support via local bus UPMB

Anton Vorontsov wrote:

...

On Wed, May 28, 2008 at 08:38:37PM +0200, Wolfgang Grandegger wrote:

...
Scott Wood wrote:

...
On Wed, May 28, 2008 at 08:12:28PM +0200, Wolfgang Grandegger wrote:

...
This patch adds support for NAND FLASH on the TQM8548. It is disabled by default and can be enabled for the TQM8548 modules. Note that the R/B pin is not supported by that module requiring to use the specified maximum delay time.

Note: With NAND support enabled the size of the U-Boot image exceeds 256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk, doubling the image size :-(.

What does this do differently from the code in drivers/mtd/nand/fsl_upm.c?

Maybe it does not support multi banks on a NAND chip. I have to check.

Me thinks that you'll have to call fsl_upm_nand_init() for each chip, and that's all. If not, feel free to patch it as you feel appropriate, I'll able to regress-test this driver on MPC8360E-RDK.

That seems not to be a minor problem. If CFG_MAX_NAND_DEVICE > 1, board_nand_init() will be called twice with the base address from CFG_NAND_BASE_LIST. The only problem I see is that the UPM interface is setup twice.

...

...
...
How much of this is board-specific?

Well, I already gave drivers/mtd/nand/fsl_upm.c a try but was unable to get it working on this board. Therefore I decided to keep this known to work driver which we have already for a while.

This isn't really an excuse to duplicate drivers. :-) This driver was tested on MPC8555 and MPC8360 CPUs, so it should work with no drastic changes. Some issues might still be there, and if so, fixes are highly appreciated.

I know, sniff.

...

...
With Linux, I had more success.

..especially if general idea works well, we should use single driver.

I already had a closer look and realized a difference in writing the UPM array. In fsl_upm.c there is:

static void fsl_upm_setup(struct fsl_upm *upm) { int i;

/* write upm array */ out_be32(upm->mxmr, FSL_UPM_MxMR_OP_WA);

for (i = 0; i < 64; i++) { out_be32(upm->mdr, upm->array[i]); out_8(upm->io_addr, 0x0); }

/* normal operation */ out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO); while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO) eieio(); }

But in my driver I fold the machine address into mbmr for each value:

out_be32 (&lbc->mbmr, (in_be32 (&lbc->mbmr) & ~(MxMR_OP_NORM | MxMR_MAD)) | MxMR_OP_WARR | (i & MxMR_MAD)); ^

Seem also that defines a duplicated :-(.

Has it been tested with an MPC85xx? I will do some more test now.

Wolfgang.

Anton Vorontsov

2:44 p.m.

New subject: [U-Boot-Users] [PATCH] TQM85xx: NAND support via local bus UPMB

On Thu, May 29, 2008 at 01:58:14PM +0200, Wolfgang Grandegger wrote:

...

Anton Vorontsov wrote:

...
On Wed, May 28, 2008 at 08:38:37PM +0200, Wolfgang Grandegger wrote:

...
Scott Wood wrote:

...
On Wed, May 28, 2008 at 08:12:28PM +0200, Wolfgang Grandegger wrote:

...
This patch adds support for NAND FLASH on the TQM8548. It is disabled by default and can be enabled for the TQM8548 modules. Note that the R/B pin is not supported by that module requiring to use the specified maximum delay time.

Note: With NAND support enabled the size of the U-Boot image exceeds 256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk, doubling the image size :-(.

What does this do differently from the code in drivers/mtd/nand/fsl_upm.c?

Maybe it does not support multi banks on a NAND chip. I have to check.

Me thinks that you'll have to call fsl_upm_nand_init() for each chip, and that's all. If not, feel free to patch it as you feel appropriate, I'll able to regress-test this driver on MPC8360E-RDK.

That seems not to be a minor problem. If CFG_MAX_NAND_DEVICE > 1, board_nand_init() will be called twice with the base address from CFG_NAND_BASE_LIST. The only problem I see is that the UPM interface is setup twice.

Personally I think we should remove UPM programming code from the fsl_upm_nand.c, and program the UPM via its own interface, see this post:

From: David Saada David.Saada@ecitele.com To: "'u-boot-users@lists.sourceforge.net'" u-boot-users@lists.sourceforge.net Date: Mon, 19 May 2008 19:05:04 +0300 Subject: [U-Boot-Users] [PATCH][resubmit] MPC85xx, MPC83xx: Add/Fix UPM configuration support

^^^ But this is still WIP, and I'm not sure if this is suitable for our needs (didn't try it).

...

...
...
...
How much of this is board-specific?

Well, I already gave drivers/mtd/nand/fsl_upm.c a try but was unable to get it working on this board. Therefore I decided to keep this known to work driver which we have already for a while.

This isn't really an excuse to duplicate drivers. :-) This driver was tested on MPC8555 and MPC8360 CPUs, so it should work with no drastic changes. Some issues might still be there, and if so, fixes are highly appreciated.

I know, sniff.

...
...
With Linux, I had more success.

..especially if general idea works well, we should use single driver.

I already had a closer look and realized a difference in writing the UPM array. In fsl_upm.c there is:

static void fsl_upm_setup(struct fsl_upm *upm) { int i;

/* write upm array */ out_be32(upm->mxmr, FSL_UPM_MxMR_OP_WA);

for (i = 0; i < 64; i++) { out_be32(upm->mdr, upm->array[i]); out_8(upm->io_addr, 0x0); }

/* normal operation */ out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO); while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO) eieio(); }

But in my driver I fold the machine address into mbmr for each value:
    out_be32 (&lbc->mbmr,
             (in_be32 (&lbc->mbmr) & ~(MxMR_OP_NORM | MxMR_MAD)) |
              MxMR_OP_WARR | (i & MxMR_MAD));
                              ^

I see. I think there will be a problem with a

static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset) { out_be32(upm->mxmr, FSL_UPM_MxMR_OP_RP | pat_offset); }

static void fsl_upm_end_pattern(struct fsl_upm *upm) { out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO); while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO) eieio(); }

Since it zeroes these values. No problem though, this should be replaced by the Linux' versions, that is

clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset); for start_pattern, and clrbits32(upm->mxmr, MxMR_OP_RP); for end_pattern.

So, this will leave your values intact, and will work for all boards as well.

...

Seem also that defines a duplicated :-(.

No problem. Please, remove the ones you don't like, and leave the ones you do like. :-) Feel completely free to do everything you need to make fsl_upm_nand.c work on your hardware, and then we'll see what we can do to make our hardware work together.

As for UPM programming, as I've said, just remove UPM programming code from the NAND driver, and leave it in the board file until (if) we'll start using generic interface.

...

Has it been tested with an MPC85xx? I will do some more test now.

Yup, MPC8555.

-- Anton Vorontsov email: cbouatmailru@gmail.com irc://irc.freenode.net/bd2

Wolfgang Grandegger

30 May 30 May

8 p.m.

New subject: [U-Boot-Users] [PATCH] TQM85xx: NAND support via local bus UPMB

Anton Vorontsov wrote:

...

On Thu, May 29, 2008 at 01:58:14PM +0200, Wolfgang Grandegger wrote:

...
Anton Vorontsov wrote:

...
On Wed, May 28, 2008 at 08:38:37PM +0200, Wolfgang Grandegger wrote:

...
Scott Wood wrote:

...
On Wed, May 28, 2008 at 08:12:28PM +0200, Wolfgang Grandegger wrote:

...
This patch adds support for NAND FLASH on the TQM8548. It is disabled by default and can be enabled for the TQM8548 modules. Note that the R/B pin is not supported by that module requiring to use the specified maximum delay time.

Note: With NAND support enabled the size of the U-Boot image exceeds 256 KB and TEXT_BASE must therefore be set to 0xfff80000 in config.mk, doubling the image size :-(.

What does this do differently from the code in drivers/mtd/nand/fsl_upm.c?

Maybe it does not support multi banks on a NAND chip. I have to check.

Me thinks that you'll have to call fsl_upm_nand_init() for each chip, and that's all. If not, feel free to patch it as you feel appropriate, I'll able to regress-test this driver on MPC8360E-RDK.

That seems not to be a minor problem. If CFG_MAX_NAND_DEVICE > 1, board_nand_init() will be called twice with the base address from CFG_NAND_BASE_LIST. The only problem I see is that the UPM interface is setup twice.

Personally I think we should remove UPM programming code from the fsl_upm_nand.c, and program the UPM via its own interface, see this post:

From: David Saada David.Saada@ecitele.com To: "'u-boot-users@lists.sourceforge.net'" u-boot-users@lists.sourceforge.net Date: Mon, 19 May 2008 19:05:04 +0300 Subject: [U-Boot-Users] [PATCH][resubmit] MPC85xx, MPC83xx: Add/Fix UPM configuration support

^^^ But this is still WIP, and I'm not sure if this is suitable for our needs (didn't try it).

OK.

...

...
...
...
...
How much of this is board-specific?

Well, I already gave drivers/mtd/nand/fsl_upm.c a try but was unable to get it working on this board. Therefore I decided to keep this known to work driver which we have already for a while.

This isn't really an excuse to duplicate drivers. :-) This driver was tested on MPC8555 and MPC8360 CPUs, so it should work with no drastic changes. Some issues might still be there, and if so, fixes are highly appreciated.

I know, sniff.

...
...
With Linux, I had more success.

..especially if general idea works well, we should use single driver.

I already had a closer look and realized a difference in writing the UPM array. In fsl_upm.c there is:

static void fsl_upm_setup(struct fsl_upm *upm) { int i;

/* write upm array */ out_be32(upm->mxmr, FSL_UPM_MxMR_OP_WA);

for (i = 0; i < 64; i++) { out_be32(upm->mdr, upm->array[i]); out_8(upm->io_addr, 0x0); }

/* normal operation */ out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO); while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO) eieio(); }

But in my driver I fold the machine address into mbmr for each value:
    out_be32 (&lbc->mbmr,
             (in_be32 (&lbc->mbmr) & ~(MxMR_OP_NORM | MxMR_MAD)) |
              MxMR_OP_WARR | (i & MxMR_MAD));
                              ^
I see. I think there will be a problem with a

static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset) { out_be32(upm->mxmr, FSL_UPM_MxMR_OP_RP | pat_offset); }

static void fsl_upm_end_pattern(struct fsl_upm *upm) { out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO); while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO) eieio(); }

Since it zeroes these values. No problem though, this should be replaced by the Linux' versions, that is

clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RP | pat_offset); for start_pattern, and clrbits32(upm->mxmr, MxMR_OP_RP); for end_pattern.

So, this will leave your values intact, and will work for all boards as well.

Fix that, but I can still not access the device properly. I'm a bit puzzled because it uses a different algorithm to access the device. While my and the Linux fsl_upm driver uses NAND_ALE, NAND_CLE and friends to manage the access via hwcontrol callback, the fsl_upm driver of U-Boot uses the cmdfunc callback doing different things. What is the difference? It seems to work on the MPC8555, at least, as you mention below.

...

...
Seem also that defines a duplicated :-(.

No problem. Please, remove the ones you don't like, and leave the ones you do like. :-) Feel completely free to do everything you need to make fsl_upm_nand.c work on your hardware, and then we'll see what we can do to make our hardware work together.

OK. The defines should go to fsl_lbc.h nowadays.

...

As for UPM programming, as I've said, just remove UPM programming code from the NAND driver, and leave it in the board file until (if) we'll start using generic interface.

...
Has it been tested with an MPC85xx? I will do some more test now.

Yup, MPC8555.

Wolfgang.

Anton Vorontsov

8:28 p.m.

New subject: [U-Boot-Users] [PATCH] TQM85xx: NAND support via local bus UPMB

On Fri, May 30, 2008 at 08:00:32PM +0200, Wolfgang Grandegger wrote: [...]

...

Fix that, but I can still not access the device properly. I'm a bit puzzled because it uses a different algorithm to access the device. While my and the Linux fsl_upm driver uses NAND_ALE, NAND_CLE and friends to manage the access via hwcontrol callback, the fsl_upm driver of U-Boot uses the cmdfunc callback doing different things.

I wonder if your NAND chip is a large page one? Because currently fsl_upm_nand hardcodes OOB stuff (bad thing, but with old mtd subsystem I didn't find better way ;-).

As for u-boot and linux doing different things... with this patch u-boot and linux are identical:

http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot/u-boot-nand-flash.git;a=commi...

This is in U-Boot's mtd-2.6.22.1 branch though. :-/ Your approach with hwctl seem to be more universal (for old mtd subsystem), since it doesn't duplicate MTD cmdfunc, thus should work for all NAND chips...

Could you prepare a patch that replacing fsl_upm_nand.c's current logic with yours (that should work for your NAND chip), and I'll test it on MPC8360E-RDK?

-- Anton Vorontsov email: cbouatmailru@gmail.com irc://irc.freenode.net/bd2

Wolfgang Grandegger

31 May 31 May

9:06 a.m.

New subject: [U-Boot-Users] [PATCH] TQM85xx: NAND support via local bus UPMB

Anton Vorontsov wrote:

...

On Fri, May 30, 2008 at 08:00:32PM +0200, Wolfgang Grandegger wrote: [...]

...
Fix that, but I can still not access the device properly. I'm a bit puzzled because it uses a different algorithm to access the device. While my and the Linux fsl_upm driver uses NAND_ALE, NAND_CLE and friends to manage the access via hwcontrol callback, the fsl_upm driver of U-Boot uses the cmdfunc callback doing different things.

I wonder if your NAND chip is a large page one? Because currently fsl_upm_nand hardcodes OOB stuff (bad thing, but with old mtd subsystem I didn't find better way ;-).

On my TQM8548 there is a Micron MT29F8G08FABWP, page size 2048 + 64 bytes, block size 128K + 4K bytes.

...

As for u-boot and linux doing different things... with this patch u-boot and linux are identical:

http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot/u-boot-nand-flash.git;a=commi...

This is in U-Boot's mtd-2.6.22.1 branch though. :-/ Your approach with hwctl seem to be more universal (for old mtd subsystem), since it doesn't duplicate MTD cmdfunc, thus should work for all NAND chips...

A closer look to the code confirms that.

...

Could you prepare a patch that replacing fsl_upm_nand.c's current logic with yours (that should work for your NAND chip), and I'll test it on MPC8360E-RDK?

The attached preliminary patch works for me. Compared to my specific driver, it saves start_pattern and end_pattern calls :-). It now also supports a bus width of 8, 16 and 32 bits and width is now in bits like in the Linux driver. I'm going to prepare a proper patch series beginning of next week.

Wolfgang.

Wolfgang Grandegger

9:11 a.m.

New subject: [U-Boot-Users] [PATCH] TQM85xx: NAND support via local bus UPMB

Wolfgang Grandegger wrote:

...

Anton Vorontsov wrote:

...
On Fri, May 30, 2008 at 08:00:32PM +0200, Wolfgang Grandegger wrote: [...]

...
Fix that, but I can still not access the device properly. I'm a bit puzzled because it uses a different algorithm to access the device. While my and the Linux fsl_upm driver uses NAND_ALE, NAND_CLE and friends to manage the access via hwcontrol callback, the fsl_upm driver of U-Boot uses the cmdfunc callback doing different things.

I wonder if your NAND chip is a large page one? Because currently fsl_upm_nand hardcodes OOB stuff (bad thing, but with old mtd subsystem I didn't find better way ;-).

On my TQM8548 there is a Micron MT29F8G08FABWP, page size 2048 + 64 bytes, block size 128K + 4K bytes.

...
As for u-boot and linux doing different things... with this patch u-boot and linux are identical:

http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot/u-boot-nand-flash.git;a=commi...

This is in U-Boot's mtd-2.6.22.1 branch though. :-/ Your approach with hwctl seem to be more universal (for old mtd subsystem), since it doesn't duplicate MTD cmdfunc, thus should work for all NAND chips...

A closer look to the code confirms that.

...
Could you prepare a patch that replacing fsl_upm_nand.c's current logic with yours (that should work for your NAND chip), and I'll test it on MPC8360E-RDK?

The attached preliminary patch works for me. Compared to my specific driver, it saves start_pattern and end_pattern calls :-). It now also supports a bus width of 8, 16 and 32 bits and width is now in bits like in the Linux driver. I'm going to prepare a proper patch series beginning of next week.

Here is the missing patch:

--- drivers/mtd/nand/fsl_upm.c | 132 +++++++++++++++++---------------------------- include/asm-ppc/io.h | 28 +++++++++ 2 files changed, 79 insertions(+), 81 deletions(-)

Index: u-boot/drivers/mtd/nand/fsl_upm.c =================================================================== --- u-boot.orig/drivers/mtd/nand/fsl_upm.c +++ u-boot/drivers/mtd/nand/fsl_upm.c @@ -20,112 +20,89 @@ #include <linux/mtd/fsl_upm.h> #include <nand.h>

-#define FSL_UPM_MxMR_OP_NO (0 << 28) /* normal operation */ -#define FSL_UPM_MxMR_OP_WA (1 << 28) /* write array */ -#define FSL_UPM_MxMR_OP_RA (2 << 28) /* read array */ -#define FSL_UPM_MxMR_OP_RP (3 << 28) /* run pattern */ +static int fsl_upm_in_pattern;

static void fsl_upm_start_pattern(struct fsl_upm *upm, u32 pat_offset) { - out_be32(upm->mxmr, FSL_UPM_MxMR_OP_RP | pat_offset); + clrsetbits_be32(upm->mxmr, MxMR_MAD, MxMR_OP_RUN | pat_offset); }

static void fsl_upm_end_pattern(struct fsl_upm *upm) { - out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO); - while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO) + clrbits32(upm->mxmr, MxMR_OP_RUN); + + while (in_be32(upm->mxmr) & MxMR_OP_RUN) eieio(); }

static void fsl_upm_run_pattern(struct fsl_upm *upm, int width, u32 cmd) { - out_be32(upm->mar, cmd << (32 - width * 8)); - out_8(upm->io_addr, 0x0); -} - -static void fsl_upm_setup(struct fsl_upm *upm) -{ - int i; - - /* write upm array */ - out_be32(upm->mxmr, FSL_UPM_MxMR_OP_WA); - - for (i = 0; i < 64; i++) { - out_be32(upm->mdr, upm->array[i]); - out_8(upm->io_addr, 0x0); + out_be32(upm->mar, cmd << (32 - width)); + switch (width) { + case 8: + out_8(io_base, 0x0); + break; + case 16: + out_be16(io_base, 0x0); + break; + case 32: + out_be32(io_base, 0x0); + break; } - - /* normal operation */ - out_be32(upm->mxmr, FSL_UPM_MxMR_OP_NO); - while (in_be32(upm->mxmr) != FSL_UPM_MxMR_OP_NO) - eieio(); }

-static void fun_cmdfunc(struct mtd_info *mtd, unsigned command, int column, - int page_addr) +static void nand_hwcontrol (struct mtd_info *mtd, int cmd) { struct nand_chip *chip = mtd->priv; struct fsl_upm_nand *fun = chip->priv;

- fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset); - - if (command == NAND_CMD_SEQIN) { - int readcmd; - - if (column >= mtd->oobblock) { - /* OOB area */ - column -= mtd->oobblock; - readcmd = NAND_CMD_READOOB; - } else if (column < 256) { - /* First 256 bytes --> READ0 */ - readcmd = NAND_CMD_READ0; - } else { - column -= 256; - readcmd = NAND_CMD_READ1; - } - fsl_upm_run_pattern(&fun->upm, fun->width, readcmd); + switch (cmd) { + case NAND_CTL_SETCLE: + fsl_upm_start_pattern(&fun->upm, fun->upm_cmd_offset); + fsl_upm_in_pattern++; + break; + case NAND_CTL_SETALE: + fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset); + fsl_upm_in_pattern++; + break; + case NAND_CTL_CLRCLE: + case NAND_CTL_CLRALE: + fsl_upm_end_pattern(&fun->upm); + fsl_upm_in_pattern--; + break; } +#if 1 + /* Temorary check */ + if (fsl_upm_in_pattern < 0 || fsl_upm_in_pattern > 1) + printf("fsl_upm: Oops, unexpected fsl_upm_in_pattern %d\n", + fsl_upm_in_pattern); +#endif +}

- fsl_upm_run_pattern(&fun->upm, fun->width, command); - - fsl_upm_end_pattern(&fun->upm); - - fsl_upm_start_pattern(&fun->upm, fun->upm_addr_offset); - - if (column != -1) - fsl_upm_run_pattern(&fun->upm, fun->width, column); +static void nand_write_byte(struct mtd_info *mtd, u_char byte) +{ + struct nand_chip *chip = mtd->priv;

- if (page_addr != -1) { - fsl_upm_run_pattern(&fun->upm, fun->width, page_addr); - fsl_upm_run_pattern(&fun->upm, fun->width, - (page_addr >> 8) & 0xFF); - if (chip->chipsize > (32 << 20)) { - fsl_upm_run_pattern(&fun->upm, fun->width, - (page_addr >> 16) & 0x0f); - } - } + if (fsl_upm_in_pattern) { + struct fsl_upm_nand *fun = chip->priv;

- fsl_upm_end_pattern(&fun->upm); + fsl_upm_run_pattern(&fun->upm, fun->width, byte);

- if (fun->wait_pattern) { /* * Some boards/chips needs this. At least on MPC8360E-RDK we * need it. Probably weird chip, because I don't see any need * for this on MPC8555E + Samsung K9F1G08U0A. Usually here are * 0-2 unexpected busy states per block read. */ - while (!fun->dev_ready()) - debug("unexpected busy state\n"); + if (fun->wait_pattern) { + while (!fun->dev_ready()) + debug("unexpected busy state\n"); + } + } else { + out_8(chip->IO_ADDR_W, byte); } }

-static void nand_write_byte(struct mtd_info *mtd, u_char byte) -{ - struct nand_chip *chip = mtd->priv; - - out_8(chip->IO_ADDR_W, byte); -} - static u8 nand_read_byte(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; @@ -164,10 +141,6 @@ static int nand_verify_buf(struct mtd_in return 0; }

-static void nand_hwcontrol(struct mtd_info *mtd, int cmd) -{ -} - static int nand_dev_ready(struct mtd_info *mtd) { struct nand_chip *chip = mtd->priv; @@ -179,15 +152,12 @@ static int nand_dev_ready(struct mtd_inf int fsl_upm_nand_init(struct nand_chip *chip, struct fsl_upm_nand *fun) { /* yet only 8 bit accessors implemented */ - if (fun->width != 1) + if (fun->width != 8 && fun->width != 16 && fun->width != 32) return -ENOSYS;

- fsl_upm_setup(&fun->upm); - chip->priv = fun; chip->chip_delay = fun->chip_delay; chip->eccmode = NAND_ECC_SOFT; - chip->cmdfunc = fun_cmdfunc; chip->hwcontrol = nand_hwcontrol; chip->read_byte = nand_read_byte; chip->read_buf = nand_read_buf; Index: u-boot/include/asm-ppc/io.h =================================================================== --- u-boot.orig/include/asm-ppc/io.h +++ u-boot/include/asm-ppc/io.h @@ -238,6 +238,34 @@ extern inline void out_be32(volatile uns __asm__ __volatile__("sync; stw%U0%X0 %1,%0" : "=m" (*addr) : "r" (val)); }

+/* access ports */ +#define setbits32(_addr, _v) out_be32((_addr), in_be32(_addr) | (_v)) +#define clrbits32(_addr, _v) out_be32((_addr), in_be32(_addr) & ~(_v)) + +#define setbits16(_addr, _v) out_be16((_addr), in_be16(_addr) | (_v)) +#define clrbits16(_addr, _v) out_be16((_addr), in_be16(_addr) & ~(_v)) + +#define setbits8(_addr, _v) out_8((_addr), in_8(_addr) | (_v)) +#define clrbits8(_addr, _v) out_8((_addr), in_8(_addr) & ~(_v)) + +/* Clear and set bits in one shot. These macros can be used to clear and + * set multiple bits in a register using a single read-modify-write. These + * macros can also be used to set a multiple-bit bit pattern using a mask, + * by specifying the mask in the 'clear' parameter and the new bit pattern + * in the 'set' parameter. + */ + +#define clrsetbits(type, addr, clear, set) \ + out_##type((addr), (in_##type(addr) & ~(clear)) | (set)) + +#define clrsetbits_be32(addr, clear, set) clrsetbits(be32, addr, clear, set) +#define clrsetbits_le32(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrsetbits_be16(addr, clear, set) clrsetbits(be16, addr, clear, set) +#define clrsetbits_le16(addr, clear, set) clrsetbits(le32, addr, clear, set) + +#define clrsetbits_8(addr, clear, set) clrsetbits(8, addr, clear, set) + /* * Given a physical address and a length, return a virtual address * that can be used to access the memory range with the caching

Wolfgang Grandegger

2 Jun 2 Jun

12:06 p.m.

New subject: [U-Boot-Users] [PATCH] TQM85xx: NAND support via local bus UPMB

Anton Vorontsov wrote:

...

On Fri, May 30, 2008 at 08:00:32PM +0200, Wolfgang Grandegger wrote: [...]

...
Fix that, but I can still not access the device properly. I'm a bit puzzled because it uses a different algorithm to access the device. While my and the Linux fsl_upm driver uses NAND_ALE, NAND_CLE and friends to manage the access via hwcontrol callback, the fsl_upm driver of U-Boot uses the cmdfunc callback doing different things.

I wonder if your NAND chip is a large page one? Because currently fsl_upm_nand hardcodes OOB stuff (bad thing, but with old mtd subsystem I didn't find better way ;-).

As for u-boot and linux doing different things... with this patch u-boot and linux are identical:

http://www.denx.de/cgi-bin/gitweb.cgi?p=u-boot/u-boot-nand-flash.git;a=commi...

This is in U-Boot's mtd-2.6.22.1 branch though. :-/ Your approach with hwctl seem to be more universal (for old mtd subsystem), since it doesn't duplicate MTD cmdfunc, thus should work for all NAND chips...

Could you prepare a patch that replacing fsl_upm_nand.c's current logic with yours (that should work for your NAND chip), and I'll test it on MPC8360E-RDK?

Here we go. I'm going to send 4 patches that work for me on my TQM8548 module. Could you please give it a try?

Thanks,

Wolfgang.

Andy Fleming

3 Jun 3 Jun

5:15 a.m.

New subject: [U-Boot-Users] [PATCH] MPC85xx: Beatify boot output of L2 cache configuration

On Wed, May 28, 2008 at 1:12 PM, Wolfgang Grandegger wg@grandegger.com wrote:

...

The boot output is now aligned poperly with other boot output lines, e.g.:

FLASH: 128 MB L2: 512 KB enabled

Signed-off-by: Wolfgang Grandegger wg@grandegger.com

A silly comment, but let's spell it "Beautify"

Andy

Wolfgang Grandegger

9:28 a.m.

New subject: [U-Boot-Users] [PATCH] MPC85xx: Beatify boot output of L2 cache configuration

Andy Fleming wrote:

...

On Wed, May 28, 2008 at 1:12 PM, Wolfgang Grandegger wg@grandegger.com wrote:

...
The boot output is now aligned poperly with other boot output lines, e.g.:

FLASH: 128 MB L2: 512 KB enabled

Signed-off-by: Wolfgang Grandegger wg@grandegger.com

A silly comment, but let's spell it "Beautify"

Of course, I didn't want to beatify this part of the code. New patch will follow.

BTW: what is the correct way to send an updated version of a patch. Should the subject be unchanged or is adding "v2" to [PATCH] preferred.

Wolfgang.

Detlev Zundel

6:50 p.m.

New subject: [U-Boot-Users] [PATCH] MPC85xx: Beatify boot output of L2 cache configuration

Hi Wolfgang,

...

Andy Fleming wrote:

...
On Wed, May 28, 2008 at 1:12 PM, Wolfgang Grandegger wg@grandegger.com wrote:

...
The boot output is now aligned poperly with other boot output lines, e.g.:

FLASH: 128 MB L2: 512 KB enabled

Signed-off-by: Wolfgang Grandegger wg@grandegger.com

A silly comment, but let's spell it "Beautify"

Of course, I didn't want to beatify this part of the code. New patch will follow.

BTW: what is the correct way to send an updated version of a patch. Should the subject be unchanged or is adding "v2" to [PATCH] preferred.

Please change the subject, so it is easier to follow what iteration is being discussed. git-format-patch will help out nicely here:

git-format-patch --subject-prefix="PATCH v2" ...

Cheers Detlev

-- Cyberwar is certainly not a myth. But you haven't seen it yet, despite the attacks on Estonia. Cyberwar is warfare in cyberspace. And warfare involves massive death and destruction. When you see it, you'll know it. -- Bruce Schneier, Nov. 2007 -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-40 Fax: (+49)-8142-66989-80 Email: dzu@denx.de

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Andy Fleming
Anton Vorontsov
Detlev Zundel
Scott Wood
Wolfgang Grandegger