CONFIG_CONSOLE_MUX and CONFIG_SYS_CONSOLE_IS_IN_ENV are not applicable for SPL. Update the console code to use CONFIG_IS_ENABLED(), so that these options will be inactive in SPL.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: - update iomux.c and usb_kbd.c also

Changes in v2: None

common/console.c | 30 +++++++++++++++--------------- common/iomux.c | 4 ++-- common/usb_kbd.c | 6 +++--- 3 files changed, 20 insertions(+), 20 deletions(-)

diff --git a/common/console.c b/common/console.c index e1d84763bdc..1232808df52 100644 --- a/common/console.c +++ b/common/console.c @@ -41,14 +41,14 @@ static int on_console(const char *name, const char *value, enum env_op op, case env_op_create: case env_op_overwrite:

-#ifdef CONFIG_CONSOLE_MUX +#if CONFIG_IS_ENABLED(CONSOLE_MUX) if (iomux_doenv(console, value)) return 1; #else /* Try assigning specified device */ if (console_assign(console, value) < 0) return 1; -#endif /* CONFIG_CONSOLE_MUX */ +#endif return 0;

case env_op_delete: @@ -85,7 +85,7 @@ static int on_silent(const char *name, const char *value, enum env_op op, U_BOOT_ENV_CALLBACK(silent, on_silent); #endif

-#ifdef CONFIG_SYS_CONSOLE_IS_IN_ENV +#if CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV) /* * if overwrite_console returns 1, the stdin, stderr and stdout * are switched to the serial port, else the settings in the @@ -98,7 +98,7 @@ extern int overwrite_console(void); #define OVERWRITE_CONSOLE 0 #endif /* CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE */

-#endif /* CONFIG_SYS_CONSOLE_IS_IN_ENV */ +#endif /* CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV) */

static int console_setfile(int file, struct stdio_dev * dev) { @@ -145,7 +145,7 @@ static int console_setfile(int file, struct stdio_dev * dev) return error; }

-#if defined(CONFIG_CONSOLE_MUX) +#if CONFIG_IS_ENABLED(CONSOLE_MUX) /** Console I/O multiplexing *******************************************/

static struct stdio_dev *tstcdev; @@ -265,7 +265,7 @@ static inline void console_doenv(int file, struct stdio_dev *dev) { console_setfile(file, dev); } -#endif /* defined(CONFIG_CONSOLE_MUX) */ +#endif /* CONIFIG_IS_ENABLED(CONSOLE_MUX) */

/** U-Boot INITIAL CONSOLE-NOT COMPATIBLE FUNCTIONS *************************/

@@ -290,7 +290,7 @@ int serial_printf(const char *fmt, ...) int fgetc(int file) { if (file < MAX_FILES) { -#if defined(CONFIG_CONSOLE_MUX) +#if CONFIG_IS_ENABLED(CONSOLE_MUX) /* * Effectively poll for input wherever it may be available. */ @@ -736,7 +736,7 @@ void stdio_print_current_devices(void) } }

-#ifdef CONFIG_SYS_CONSOLE_IS_IN_ENV +#if CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV) /* Called after the relocation - use desired console functions */ int console_init_r(void) { @@ -745,7 +745,7 @@ int console_init_r(void) #ifdef CONFIG_SYS_CONSOLE_ENV_OVERWRITE int i; #endif /* CONFIG_SYS_CONSOLE_ENV_OVERWRITE */ -#ifdef CONFIG_CONSOLE_MUX +#if CONFIG_IS_ENABLED(CONSOLE_MUX) int iomux_err = 0; #endif

@@ -766,7 +766,7 @@ int console_init_r(void) inputdev = search_device(DEV_FLAGS_INPUT, stdinname); outputdev = search_device(DEV_FLAGS_OUTPUT, stdoutname); errdev = search_device(DEV_FLAGS_OUTPUT, stderrname); -#ifdef CONFIG_CONSOLE_MUX +#if CONFIG_IS_ENABLED(CONSOLE_MUX) iomux_err = iomux_doenv(stdin, stdinname); iomux_err += iomux_doenv(stdout, stdoutname); iomux_err += iomux_doenv(stderr, stderrname); @@ -799,7 +799,7 @@ int console_init_r(void) console_doenv(stdin, inputdev); }

-#ifdef CONFIG_CONSOLE_MUX +#if CONFIG_IS_ENABLED(CONSOLE_MUX) done: #endif

@@ -829,7 +829,7 @@ done: return 0; }

-#else /* CONFIG_SYS_CONSOLE_IS_IN_ENV */ +#else /* !CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV) */

/* Called after the relocation - use desired console functions */ int console_init_r(void) @@ -873,7 +873,7 @@ int console_init_r(void) if (outputdev != NULL) { console_setfile(stdout, outputdev); console_setfile(stderr, outputdev); -#ifdef CONFIG_CONSOLE_MUX +#if CONFIG_IS_ENABLED(CONSOLE_MUX) console_devices[stdout][0] = outputdev; console_devices[stderr][0] = outputdev; #endif @@ -882,7 +882,7 @@ int console_init_r(void) /* Initializes input console */ if (inputdev != NULL) { console_setfile(stdin, inputdev); -#ifdef CONFIG_CONSOLE_MUX +#if CONFIG_IS_ENABLED(CONSOLE_MUX) console_devices[stdin][0] = inputdev; #endif } @@ -907,4 +907,4 @@ int console_init_r(void) return 0; }

-#endif /* CONFIG_SYS_CONSOLE_IS_IN_ENV */ +#endif /* CONFIG_IS_ENABLED(SYS_CONSOLE_IS_IN_ENV) */ diff --git a/common/iomux.c b/common/iomux.c index 3d8d00b4486..0e4e6803e7a 100644 --- a/common/iomux.c +++ b/common/iomux.c @@ -10,7 +10,7 @@ #include <serial.h> #include <malloc.h>

-#ifdef CONFIG_CONSOLE_MUX +#if CONFIG_IS_ENABLED(CONSOLE_MUX) void iomux_printdevs(const int console) { int i; @@ -145,4 +145,4 @@ int iomux_doenv(const int console, const char *arg) free(cons_set); return 0; } -#endif /* CONFIG_CONSOLE_MUX */ +#endif /* CONSOLE_MUX */ diff --git a/common/usb_kbd.c b/common/usb_kbd.c index 5f9a64ad1c5..d2d29cc98f5 100644 --- a/common/usb_kbd.c +++ b/common/usb_kbd.c @@ -516,7 +516,7 @@ static int probe_usb_keyboard(struct usb_device *dev) return error;

stdinname = getenv("stdin"); -#ifdef CONFIG_CONSOLE_MUX +#if CONFIG_IS_ENABLED(CONSOLE_MUX) error = iomux_doenv(stdin, stdinname); if (error) return error; @@ -581,7 +581,7 @@ int usb_kbd_deregister(int force) data = usb_kbd_dev->privptr; if (stdio_deregister_dev(dev, force) != 0) return 1; -#ifdef CONFIG_CONSOLE_MUX +#if CONFIG_IS_ENABLED(CONSOLE_MUX) if (iomux_doenv(stdin, getenv("stdin")) != 0) return 1; #endif @@ -626,7 +626,7 @@ static int usb_kbd_remove(struct udevice *dev) ret = -EPERM; goto err; } -#ifdef CONFIG_CONSOLE_MUX +#if CONFIG_IS_ENABLED(CONSOLE_MUX) if (iomux_doenv(stdin, getenv("stdin"))) { ret = -ENOLINK; goto err;

This currently fails silently. Add a debug message to aid debugging.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: - Show the error value in spl_spi_load_image()

common/spl/spl_spi.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/common/spl/spl_spi.c b/common/spl/spl_spi.c index cd1d6b285ef..925a1b14915 100644 --- a/common/spl/spl_spi.c +++ b/common/spl/spl_spi.c @@ -96,8 +96,11 @@ static int spl_spi_load_image(struct spl_image_info *spl_image, /* Load u-boot, mkimage header is 64 bytes. */ err = spi_flash_read(flash, CONFIG_SYS_SPI_U_BOOT_OFFS, 0x40, (void *)header); - if (err) + if (err) { + debug("%s: Failed to read from SPI flash (err=%d)\n", + __func__, err); return err; + }

if (IS_ENABLED(CONFIG_SPL_LOAD_FIT) && image_get_magic(header) == FDT_MAGIC) {

This Makefile variable can be used in the architecture's main Makefile but at present it is not set up until later. Set it just before this Makefile is included.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: None

scripts/Makefile.spl | 6 ++++++ 1 file changed, 6 insertions(+)

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index c962bbca2c1..ced10e6f95a 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -35,6 +35,12 @@ else SPL_BIN := u-boot-spl endif

+ifdef CONFIG_SPL_BUILD +SPL_ := SPL_ +else +SPL_ := +endif + include $(srctree)/config.mk include $(srctree)/arch/$(ARCH)/Makefile

Add a new Kconfig option to allow CPU drivers to be used in SPL.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: None

common/spl/Kconfig | 10 ++++++++++ drivers/Makefile | 1 + 2 files changed, 11 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig index b1aa1483c97..4c07f49dafa 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -150,6 +150,16 @@ config SPL_SHA256_SUPPORT SHA256 variant is supported: SHA512 and others are not currently supported in U-Boot.

+config SPL_CPU_SUPPORT + bool "Support CPU drivers" + depends on SPL + help + Enable this to support CPU drivers in SPL. These drivers can set + up CPUs and provide information about them such as the model and + name. This can be useful in SPL since setting up the CPUs earlier + may improve boot performance. Enable this option to build the + drivers in drivers/cpu as part of an SPL build. + config SPL_CRYPTO_SUPPORT bool "Support crypto drivers" depends on SPL diff --git a/drivers/Makefile b/drivers/Makefile index c19fa142f3a..4ced2bbb6c5 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -10,6 +10,7 @@ obj-$(CONFIG_$(SPL_)RAM) += ram/

ifdef CONFIG_SPL_BUILD

+obj-$(CONFIG_SPL_CPU_SUPPORT) += cpu/ obj-$(CONFIG_SPL_CRYPTO_SUPPORT) += crypto/ obj-$(CONFIG_SPL_I2C_SUPPORT) += i2c/ obj-$(CONFIG_SPL_GPIO_SUPPORT) += gpio/

Add a new Kconfig option to allow PCI drivers to be used in SPL.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: None

common/spl/Kconfig | 9 +++++++++ drivers/Makefile | 1 + 2 files changed, 10 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 4c07f49dafa..f361f2c122a 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -436,6 +436,15 @@ config SYS_OS_BASE

endif # SPL_OS_BOOT

+config SPL_PCI_SUPPORT + bool "Support PCI drivers" + depends on SPL + help + Enable support for PCI in SPL. For platforms that need PCI to boot, + or must perform some init using PCI in SPL, this provides the + necessary driver support. This enables the drivers in drivers/pci + as part of an SPL build. + config SPL_POST_MEM_SUPPORT bool "Support POST drivers" depends on SPL diff --git a/drivers/Makefile b/drivers/Makefile index 4ced2bbb6c5..553577acad5 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -33,6 +33,7 @@ obj-$(CONFIG_SPL_DMA_SUPPORT) += dma/ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/ obj-$(CONFIG_SPL_USBETH_SUPPORT) += net/phy/ +obj-$(CONFIG_SPL_PCI_SUPPORT) += pci/ obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/ obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/ obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/udc/

Add a new Kconfig option to allow RTC drivers to be used in SPL.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: None

common/spl/Kconfig | 10 ++++++++++ drivers/Makefile | 1 + 2 files changed, 11 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig index f361f2c122a..503adaf6707 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -485,6 +485,16 @@ config SPL_RAM_DEVICE be already in memory when SPL takes over, e.g. loaded by the boot ROM.

+config SPL_RTC_SUPPORT + bool "Support RTC drivers" + depends on SPL + help + Enable RTC (Real-time Clock) support in SPL. This includes support + for reading and setting the time. Some RTC devices also have some + non-volatile (battery-backed) memory which is accessible if + needed. This enables the drivers in drivers/rtc as part of an SPL + build. + config SPL_SATA_SUPPORT bool "Support loading from SATA" depends on SPL diff --git a/drivers/Makefile b/drivers/Makefile index 553577acad5..f070ea9b2bc 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/ obj-$(CONFIG_SPL_USBETH_SUPPORT) += net/phy/ obj-$(CONFIG_SPL_PCI_SUPPORT) += pci/ +obj-$(CONFIG_SPL_RTC_SUPPORT) += rtc/ obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/ obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/ obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/udc/

Add a new Kconfig option to allow timer drivers to be used in SPL.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: None

common/spl/Kconfig | 9 +++++++++ drivers/Makefile | 1 + 2 files changed, 10 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 503adaf6707..57d38924c84 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -538,6 +538,15 @@ config SPL_SPI_SUPPORT enable SPI drivers that are needed for other purposes also, such as a SPI PMIC.

+config SPL_TIMER_SUPPORT + bool "Support timer drivers" + depends on SPL + help + Enable support for timer drivers in SPL. These can be used to get + a timer value when in SPL, or perhaps for implementing a delay + function. This enables the drivers in drivers/timer as part of an + SPL build. + config SPL_USB_HOST_SUPPORT bool "Support USB host drivers" depends on SPL diff --git a/drivers/Makefile b/drivers/Makefile index f070ea9b2bc..00dc041f1b2 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -35,6 +35,7 @@ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/ obj-$(CONFIG_SPL_USBETH_SUPPORT) += net/phy/ obj-$(CONFIG_SPL_PCI_SUPPORT) += pci/ obj-$(CONFIG_SPL_RTC_SUPPORT) += rtc/ +obj-$(CONFIG_SPL_TIMER_SUPPORT) += timer/ obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/ obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/ obj-$(CONFIG_SPL_USB_GADGET_SUPPORT) += usb/gadget/udc/

Add an option for building Platorm Controller Hub drivers in SPL.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: None

common/spl/Kconfig | 9 +++++++++ drivers/Makefile | 1 + 2 files changed, 10 insertions(+)

diff --git a/common/spl/Kconfig b/common/spl/Kconfig index 57d38924c84..e07a6c8f853 100644 --- a/common/spl/Kconfig +++ b/common/spl/Kconfig @@ -445,6 +445,15 @@ config SPL_PCI_SUPPORT necessary driver support. This enables the drivers in drivers/pci as part of an SPL build.

+config SPL_PCH_SUPPORT + bool "Support PCH drivers" + depends on SPL + help + Enable support for PCH (Platform Controller Hub) devices in SPL. + These are used to set up GPIOs and the SPI peripheral early in + boot. This enables the drivers in drivers/pch as part of an SPL + build. + config SPL_POST_MEM_SUPPORT bool "Support POST drivers" depends on SPL diff --git a/drivers/Makefile b/drivers/Makefile index 00dc041f1b2..34c55bfb2ff 100644 --- a/drivers/Makefile +++ b/drivers/Makefile @@ -34,6 +34,7 @@ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/ obj-$(CONFIG_SPL_ETH_SUPPORT) += net/phy/ obj-$(CONFIG_SPL_USBETH_SUPPORT) += net/phy/ obj-$(CONFIG_SPL_PCI_SUPPORT) += pci/ +obj-$(CONFIG_SPL_PCH_SUPPORT) += pch/ obj-$(CONFIG_SPL_RTC_SUPPORT) += rtc/ obj-$(CONFIG_SPL_TIMER_SUPPORT) += timer/ obj-$(CONFIG_SPL_MUSB_NEW_SUPPORT) += usb/musb-new/

When BSS does not immediate follow the SPL image we don't need padding before the device tree. Remove it in this case.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: None

scripts/Makefile.spl | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index ced10e6f95a..82cfc601b29 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -191,7 +191,8 @@ quiet_cmd_copy = COPY $@ cmd_copy = cp $< $@

ifeq ($(CONFIG_SPL_OF_CONTROL)$(CONFIG_OF_SEPARATE)$(CONFIG_SPL_OF_PLATDATA),yy) -$(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin $(obj)/$(SPL_BIN)-pad.bin \ +$(obj)/$(SPL_BIN)-dtb.bin: $(obj)/$(SPL_BIN)-nodtb.bin \ + $(if $(CONFIG_SPL_SEPARATE_BSS),,$(obj)/$(SPL_BIN)-pad.bin) \ $(obj)/$(SPL_BIN).dtb FORCE $(call if_changed,cat)

We should use unsigned long rather than u32 for addresses. Update this so that the table-generation code builds correctly on 64-bit machines.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: - Move table-related changes from a later patch - Rebase to mainline - Drop the write_smbios_table_wrapper() function

arch/x86/cpu/irq.c | 2 +- arch/x86/include/asm/acpi_table.h | 2 +- arch/x86/include/asm/mpspec.h | 2 +- arch/x86/include/asm/sfi.h | 2 +- arch/x86/include/asm/tables.h | 2 +- arch/x86/lib/acpi_table.c | 4 ++-- arch/x86/lib/mpspec.c | 2 +- arch/x86/lib/sfi.c | 6 +++--- arch/x86/lib/tables.c | 11 ++--------- arch/x86/lib/zimage.c | 2 +- drivers/misc/qfw.c | 4 ++-- include/smbios.h | 4 ++-- lib/smbios.c | 22 +++++++++++----------- 13 files changed, 29 insertions(+), 36 deletions(-)

diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index 9364410a0f8..e3e928bb79b 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -264,7 +264,7 @@ int irq_router_probe(struct udevice *dev) return irq_router_common_init(dev); }

-u32 write_pirq_routing_table(u32 addr) +ulong write_pirq_routing_table(ulong addr) { if (!pirq_routing_table) return addr; diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index caff4d8a1e0..bbd80a1dd9a 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -316,4 +316,4 @@ int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, u8 cpu, u16 flags, u8 lint); u32 acpi_fill_madt(u32 current); void acpi_create_gnvs(struct acpi_global_nvs *gnvs); -u32 write_acpi_tables(u32 start); +ulong write_acpi_tables(ulong start); diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h index ad8eba947b9..146a4b0cbb8 100644 --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -456,6 +456,6 @@ int mp_determine_pci_dstirq(int bus, int dev, int func, int pirq); * @addr: start address to write MP table * @return: end address of MP table */ -u32 write_mp_table(u32 addr); +ulong write_mp_table(ulong addr);

#endif /* __ASM_MPSPEC_H */ diff --git a/arch/x86/include/asm/sfi.h b/arch/x86/include/asm/sfi.h index d1f0f0cb6b8..d6c44c978a9 100644 --- a/arch/x86/include/asm/sfi.h +++ b/arch/x86/include/asm/sfi.h @@ -132,6 +132,6 @@ typedef int (*sfi_table_handler) (struct sfi_table_header *table); * @base: Address to write table to * @return address to use for the next table */ -u32 write_sfi_table(u32 base); +ulong write_sfi_table(ulong base);

#endif /*_LINUX_SFI_H */ diff --git a/arch/x86/include/asm/tables.h b/arch/x86/include/asm/tables.h index 81f98f27745..d1b23880219 100644 --- a/arch/x86/include/asm/tables.h +++ b/arch/x86/include/asm/tables.h @@ -65,6 +65,6 @@ void write_tables(void); * @start: start address to write PIRQ routing table * @return: end address of PIRQ routing table */ -u32 write_pirq_routing_table(u32 start); +ulong write_pirq_routing_table(ulong start);

#endif /* _X86_TABLES_H_ */ diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 7001e8ba348..355456dc19e 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -327,7 +327,7 @@ static void enter_acpi_mode(int pm1_cnt) * QEMU's version of write_acpi_tables is defined in * arch/x86/cpu/qemu/acpi_table.c */ -u32 write_acpi_tables(u32 start) +ulong write_acpi_tables(ulong start) { u32 current; struct acpi_rsdp *rsdp; @@ -345,7 +345,7 @@ u32 write_acpi_tables(u32 start) /* Align ACPI tables to 16 byte */ current = ALIGN(current, 16);

- debug("ACPI: Writing ACPI tables at %x\n", start); + debug("ACPI: Writing ACPI tables at %lx\n", start);

/* We need at least an RSDP and an RSDT Table */ rsdp = (struct acpi_rsdp *)current; diff --git a/arch/x86/lib/mpspec.c b/arch/x86/lib/mpspec.c index 6ab43f1055f..516d7b3452c 100644 --- a/arch/x86/lib/mpspec.c +++ b/arch/x86/lib/mpspec.c @@ -365,7 +365,7 @@ static void mptable_add_lintsrc(struct mp_config_table *mc, int bus_isa) bus_isa, 0, MP_APIC_ALL, 1); }

-u32 write_mp_table(u32 addr) +ulong write_mp_table(ulong addr) { struct mp_config_table *mc; int ioapic_id, ioapic_ver; diff --git a/arch/x86/lib/sfi.c b/arch/x86/lib/sfi.c index 3d3658088ad..507e037b998 100644 --- a/arch/x86/lib/sfi.c +++ b/arch/x86/lib/sfi.c @@ -38,14 +38,14 @@ static void *get_entry_start(struct table_info *tab) tab->table[tab->count] = tab->entry_start; tab->entry_start += sizeof(struct sfi_table_header);

- return (void *)tab->entry_start; + return (void *)(uintptr_t)tab->entry_start; }

static void finish_table(struct table_info *tab, const char *sig, void *entry) { struct sfi_table_header *hdr;

- hdr = (struct sfi_table_header *)(tab->base + tab->ptr); + hdr = (struct sfi_table_header *)(uintptr_t)(tab->base + tab->ptr); strcpy(hdr->sig, sig); hdr->len = sizeof(*hdr) + ((ulong)entry - tab->entry_start); hdr->rev = 1; @@ -131,7 +131,7 @@ static int sfi_write_xsdt(struct table_info *tab) return 0; }

-u32 write_sfi_table(u32 base) +ulong write_sfi_table(ulong base) { struct table_info table;

diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index 5966e5862a3..4f5fe742882 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -12,20 +12,13 @@ #include <asm/acpi_table.h> #include <asm/coreboot_tables.h>

-#ifdef CONFIG_GENERATE_SMBIOS_TABLE -static u32 write_smbios_table_wrapper(u32 addr) -{ - return write_smbios_table(addr); -} -#endif - /** * Function prototype to write a specific configuration table * * @addr: start address to write the table * @return: end address of the table */ -typedef u32 (*table_write)(u32 addr); +typedef ulong (*table_write)(ulong addr);

static table_write table_write_funcs[] = { #ifdef CONFIG_GENERATE_PIRQ_TABLE @@ -41,7 +34,7 @@ static table_write table_write_funcs[] = { write_acpi_tables, #endif #ifdef CONFIG_GENERATE_SMBIOS_TABLE - write_smbios_table_wrapper, + write_smbios_table, #endif };

diff --git a/arch/x86/lib/zimage.c b/arch/x86/lib/zimage.c index 1b33c771391..b6b0f2beb3a 100644 --- a/arch/x86/lib/zimage.c +++ b/arch/x86/lib/zimage.c @@ -165,7 +165,7 @@ struct boot_params *load_zimage(char *image, unsigned long kernel_size, * A very old kernel MUST have its real-mode code * loaded at 0x90000 */ - if ((u32)setup_base != 0x90000) { + if ((ulong)setup_base != 0x90000) { /* Copy the real-mode kernel */ memmove((void *)0x90000, setup_base, setup_size);

diff --git a/drivers/misc/qfw.c b/drivers/misc/qfw.c index d43d1d300ac..a8af9e0c537 100644 --- a/drivers/misc/qfw.c +++ b/drivers/misc/qfw.c @@ -32,7 +32,7 @@ static LIST_HEAD(fw_list); * be ignored. * @return: 0 on success, or negative value on failure */ -static int bios_linker_allocate(struct bios_linker_entry *entry, u32 *addr) +static int bios_linker_allocate(struct bios_linker_entry *entry, ulong *addr) { uint32_t size, align; struct fw_file *file; @@ -147,7 +147,7 @@ static int bios_linker_add_checksum(struct bios_linker_entry *entry) }

/* This function loads and patches ACPI tables provided by QEMU */ -u32 write_acpi_tables(u32 addr) +ulong write_acpi_tables(ulong addr) { int i, ret = 0; struct fw_file *file; diff --git a/include/smbios.h b/include/smbios.h index d582d4f7abb..c24d00e38dd 100644 --- a/include/smbios.h +++ b/include/smbios.h @@ -225,7 +225,7 @@ static inline void fill_smbios_header(void *table, int type, * @handle: the structure's handle, a unique 16-bit number * @return: size of the structure */ -typedef int (*smbios_write_type)(uintptr_t *addr, int handle); +typedef int (*smbios_write_type)(ulong *addr, int handle);

/** * write_smbios_table() - Write SMBIOS table @@ -235,6 +235,6 @@ typedef int (*smbios_write_type)(uintptr_t *addr, int handle); * @addr: start address to write SMBIOS table * @return: end address of SMBIOS table */ -uintptr_t write_smbios_table(uintptr_t addr); +ulong write_smbios_table(ulong addr);

#endif /* _SMBIOS_H_ */ diff --git a/lib/smbios.c b/lib/smbios.c index ce1974d86f7..22ca247fec8 100644 --- a/lib/smbios.c +++ b/lib/smbios.c @@ -73,7 +73,7 @@ static int smbios_string_table_len(char *start) return len + 1; }

-static int smbios_write_type0(uintptr_t *current, int handle) +static int smbios_write_type0(ulong *current, int handle) { struct smbios_type0 *t = (struct smbios_type0 *)*current; int len = sizeof(struct smbios_type0); @@ -108,7 +108,7 @@ static int smbios_write_type0(uintptr_t *current, int handle) return len; }

-static int smbios_write_type1(uintptr_t *current, int handle) +static int smbios_write_type1(ulong *current, int handle) { struct smbios_type1 *t = (struct smbios_type1 *)*current; int len = sizeof(struct smbios_type1); @@ -129,7 +129,7 @@ static int smbios_write_type1(uintptr_t *current, int handle) return len; }

-static int smbios_write_type2(uintptr_t *current, int handle) +static int smbios_write_type2(ulong *current, int handle) { struct smbios_type2 *t = (struct smbios_type2 *)*current; int len = sizeof(struct smbios_type2); @@ -147,7 +147,7 @@ static int smbios_write_type2(uintptr_t *current, int handle) return len; }

-static int smbios_write_type3(uintptr_t *current, int handle) +static int smbios_write_type3(ulong *current, int handle) { struct smbios_type3 *t = (struct smbios_type3 *)*current; int len = sizeof(struct smbios_type3); @@ -199,7 +199,7 @@ static void smbios_write_type4_dm(struct smbios_type4 *t) t->processor_version = smbios_add_string(t->eos, name); }

-static int smbios_write_type4(uintptr_t *current, int handle) +static int smbios_write_type4(ulong *current, int handle) { struct smbios_type4 *t = (struct smbios_type4 *)*current; int len = sizeof(struct smbios_type4); @@ -221,7 +221,7 @@ static int smbios_write_type4(uintptr_t *current, int handle) return len; }

-static int smbios_write_type32(uintptr_t *current, int handle) +static int smbios_write_type32(ulong *current, int handle) { struct smbios_type32 *t = (struct smbios_type32 *)*current; int len = sizeof(struct smbios_type32); @@ -234,7 +234,7 @@ static int smbios_write_type32(uintptr_t *current, int handle) return len; }

-static int smbios_write_type127(uintptr_t *current, int handle) +static int smbios_write_type127(ulong *current, int handle) { struct smbios_type127 *t = (struct smbios_type127 *)*current; int len = sizeof(struct smbios_type127); @@ -257,10 +257,10 @@ static smbios_write_type smbios_write_funcs[] = { smbios_write_type127 };

-uintptr_t write_smbios_table(uintptr_t addr) +ulong write_smbios_table(ulong addr) { struct smbios_entry *se; - u32 tables; + ulong tables; int len = 0; int max_struct_size = 0; int handle = 0; @@ -271,7 +271,7 @@ uintptr_t write_smbios_table(uintptr_t addr) /* 16 byte align the table address */ addr = ALIGN(addr, 16);

- se = (struct smbios_entry *)addr; + se = (struct smbios_entry *)(uintptr_t)addr; memset(se, 0, sizeof(struct smbios_entry));

addr += sizeof(struct smbios_entry); @@ -280,7 +280,7 @@ uintptr_t write_smbios_table(uintptr_t addr)

/* populate minimum required tables */ for (i = 0; i < ARRAY_SIZE(smbios_write_funcs); i++) { - int tmp = smbios_write_funcs[i](&addr, handle++); + int tmp = smbios_write_funcs[i]((ulong *)&addr, handle++); max_struct_size = max(max_struct_size, tmp); len += tmp; }

At present this uses u32 to store an address. We should use unsigned long and avoid special types in function return values and parameters unless necessary. This makes the code more portable.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: - Drop WIP tag as this patch is actually needed

Changes in v2: None

arch/x86/include/asm/mpspec.h | 8 ++++---- arch/x86/lib/mpspec.c | 12 ++++++------ 2 files changed, 10 insertions(+), 10 deletions(-)

diff --git a/arch/x86/include/asm/mpspec.h b/arch/x86/include/asm/mpspec.h index 146a4b0cbb8..30dbdca90db 100644 --- a/arch/x86/include/asm/mpspec.h +++ b/arch/x86/include/asm/mpspec.h @@ -224,9 +224,9 @@ struct mp_ext_compat_address_space { * @mc: configuration table header address * @return: configuration table end address */ -static inline u32 mp_next_mpc_entry(struct mp_config_table *mc) +static inline ulong mp_next_mpc_entry(struct mp_config_table *mc) { - return (u32)mc + mc->mpc_length; + return (ulong)mc + mc->mpc_length; }

/** @@ -254,9 +254,9 @@ static inline void mp_add_mpc_entry(struct mp_config_table *mc, uint length) * @mc: configuration table header address * @return: configuration table end address */ -static inline u32 mp_next_mpe_entry(struct mp_config_table *mc) +static inline ulong mp_next_mpe_entry(struct mp_config_table *mc) { - return (u32)mc + mc->mpc_length + mc->mpe_length; + return (ulong)mc + mc->mpc_length + mc->mpe_length; }

/** diff --git a/arch/x86/lib/mpspec.c b/arch/x86/lib/mpspec.c index 516d7b3452c..17e977ce5e3 100644 --- a/arch/x86/lib/mpspec.c +++ b/arch/x86/lib/mpspec.c @@ -25,10 +25,10 @@ static bool isa_irq_occupied[16];

struct mp_config_table *mp_write_floating_table(struct mp_floating_table *mf) { - u32 mc; + ulong mc;

memcpy(mf->mpf_signature, MPF_SIGNATURE, 4); - mf->mpf_physptr = (u32)mf + sizeof(struct mp_floating_table); + mf->mpf_physptr = (ulong)mf + sizeof(struct mp_floating_table); mf->mpf_length = 1; mf->mpf_spec = MPSPEC_V14; mf->mpf_checksum = 0; @@ -41,7 +41,7 @@ struct mp_config_table *mp_write_floating_table(struct mp_floating_table *mf) mf->mpf_feature5 = 0; mf->mpf_checksum = table_compute_checksum(mf, mf->mpf_length * 16);

- mc = (u32)mf + sizeof(struct mp_floating_table); + mc = (ulong)mf + sizeof(struct mp_floating_table); return (struct mp_config_table *)mc; }

@@ -219,14 +219,14 @@ void mp_write_compat_address_space(struct mp_config_table *mc, int busid,

u32 mptable_finalize(struct mp_config_table *mc) { - u32 end; + ulong end;

mc->mpe_checksum = table_compute_checksum((void *)mp_next_mpc_entry(mc), mc->mpe_length); mc->mpc_checksum = table_compute_checksum(mc, mc->mpc_length); end = mp_next_mpe_entry(mc);

- debug("Write the MP table at: %x - %x\n", (u32)mc, end); + debug("Write the MP table at: %lx - %lx\n", (ulong)mc, end);

return end; } @@ -371,7 +371,7 @@ ulong write_mp_table(ulong addr) int ioapic_id, ioapic_ver; int bus_isa = 0xff; int ret; - u32 end; + ulong end;

/* 16 byte align the table address */ addr = ALIGN(addr, 16);

Some files are missing this declaration. Add it to avoid build errors when we actually need the declaration.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: - Drop change to gma.c

arch/x86/cpu/ivybridge/bd82x6x.c | 2 ++ arch/x86/cpu/ivybridge/lpc.c | 2 ++ arch/x86/cpu/ivybridge/model_206ax.c | 2 ++ arch/x86/cpu/ivybridge/northbridge.c | 2 ++ drivers/video/ivybridge_igd.c | 2 ++ 5 files changed, 10 insertions(+)

diff --git a/arch/x86/cpu/ivybridge/bd82x6x.c b/arch/x86/cpu/ivybridge/bd82x6x.c index e63ea6b22e3..e3eff69cf67 100644 --- a/arch/x86/cpu/ivybridge/bd82x6x.c +++ b/arch/x86/cpu/ivybridge/bd82x6x.c @@ -19,6 +19,8 @@ #include <asm/arch/pch.h> #include <asm/arch/sandybridge.h>

+DECLARE_GLOBAL_DATA_PTR; + #define GPIO_BASE 0x48 #define BIOS_CTRL 0xdc

diff --git a/arch/x86/cpu/ivybridge/lpc.c b/arch/x86/cpu/ivybridge/lpc.c index 4af89b3a7cb..aef1206be41 100644 --- a/arch/x86/cpu/ivybridge/lpc.c +++ b/arch/x86/cpu/ivybridge/lpc.c @@ -20,6 +20,8 @@ #include <asm/pci.h> #include <asm/arch/pch.h>

+DECLARE_GLOBAL_DATA_PTR; + #define NMI_OFF 0

#define ENABLE_ACPI_MODE_IN_COREBOOT 0 diff --git a/arch/x86/cpu/ivybridge/model_206ax.c b/arch/x86/cpu/ivybridge/model_206ax.c index 09b534255ca..d5f32196ae3 100644 --- a/arch/x86/cpu/ivybridge/model_206ax.c +++ b/arch/x86/cpu/ivybridge/model_206ax.c @@ -22,6 +22,8 @@ #include <asm/turbo.h> #include <asm/arch/model_206ax.h>

+DECLARE_GLOBAL_DATA_PTR; + static void enable_vmx(void) { struct cpuid_result regs; diff --git a/arch/x86/cpu/ivybridge/northbridge.c b/arch/x86/cpu/ivybridge/northbridge.c index 491f2894f9e..94f31c40beb 100644 --- a/arch/x86/cpu/ivybridge/northbridge.c +++ b/arch/x86/cpu/ivybridge/northbridge.c @@ -19,6 +19,8 @@ #include <asm/arch/model_206ax.h> #include <asm/arch/sandybridge.h>

+DECLARE_GLOBAL_DATA_PTR; + int bridge_silicon_revision(struct udevice *dev) { struct cpuid_result result; diff --git a/drivers/video/ivybridge_igd.c b/drivers/video/ivybridge_igd.c index 94db3dda442..95d62a5392d 100644 --- a/drivers/video/ivybridge_igd.c +++ b/drivers/video/ivybridge_igd.c @@ -18,6 +18,8 @@ #include <asm/arch/pch.h> #include <asm/arch/sandybridge.h>

+DECLARE_GLOBAL_DATA_PTR; + struct gt_powermeter { u16 reg; u32 value;

Add various debug() messages in places where errors occur. This aids with debugging.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: - Output error code values in debug() statements

arch/x86/cpu/ivybridge/cpu.c | 4 +++- arch/x86/cpu/ivybridge/sdram.c | 37 ++++++++++++++++++++++++++++--------- 2 files changed, 31 insertions(+), 10 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/cpu.c b/arch/x86/cpu/ivybridge/cpu.c index 85e361a58f0..c4aca08f0df 100644 --- a/arch/x86/cpu/ivybridge/cpu.c +++ b/arch/x86/cpu/ivybridge/cpu.c @@ -169,8 +169,10 @@ int print_cpuinfo(void)

/* Enable SPD ROMs and DDR-III DRAM */ ret = uclass_first_device_err(UCLASS_I2C, &dev); - if (ret) + if (ret) { + debug("%s: Failed to get I2C (ret=%d)\n", __func__, ret); return ret; + }

/* Prepare USB controller early in S3 resume */ if (boot_mode == PEI_BOOT_RESUME) { diff --git a/arch/x86/cpu/ivybridge/sdram.c b/arch/x86/cpu/ivybridge/sdram.c index e0b06b5ada5..201368c9c7c 100644 --- a/arch/x86/cpu/ivybridge/sdram.c +++ b/arch/x86/cpu/ivybridge/sdram.c @@ -207,8 +207,10 @@ static int copy_spd(struct udevice *dev, struct pei_data *peid) int ret;

ret = mrc_locate_spd(dev, sizeof(peid->spd_data[0]), &data); - if (ret) + if (ret) { + debug("%s: Could not locate SPD (ret=%d)\n", __func__, ret); return ret; + }

memcpy(peid->spd_data[0], data, sizeof(peid->spd_data[0]));

@@ -460,18 +462,27 @@ int dram_init(void)

/* We need the pinctrl set up early */ ret = syscon_get_by_driver_data(X86_SYSCON_PINCONF, &dev); - if (ret) + if (ret) { + debug("%s: Could not get pinconf (ret=%d)\n", __func__, ret); return ret; + }

ret = uclass_first_device_err(UCLASS_NORTHBRIDGE, &dev); - if (ret) + if (ret) { + debug("%s: Could not get northbridge (ret=%d)\n", __func__, + ret); return ret; + } ret = syscon_get_by_driver_data(X86_SYSCON_ME, &me_dev); - if (ret) + if (ret) { + debug("%s: Could not get ME (ret=%d)\n", __func__, ret); return ret; + } ret = copy_spd(dev, pei_data); - if (ret) + if (ret) { + debug("%s: Could not get SPD (ret=%d)\n", __func__, ret); return ret; + } pei_data->boot_mode = gd->arch.pei_boot_mode; debug("Boot mode %d\n", gd->arch.pei_boot_mode); debug("mrc_input %p\n", pei_data->mrc_input); @@ -498,19 +509,27 @@ int dram_init(void)

/* Wait for ME to be ready */ ret = intel_early_me_init(me_dev); - if (ret) + if (ret) { + debug("%s: Could not init ME (ret=%d)\n", __func__, ret); return ret; + } ret = intel_early_me_uma_size(me_dev); - if (ret < 0) + if (ret < 0) { + debug("%s: Could not get UMA size (ret=%d)\n", __func__, ret); return ret; + }

ret = mrc_common_init(dev, pei_data, false); - if (ret) + if (ret) { + debug("%s: mrc_common_init() failed (ret=%d)\n", __func__, ret); return ret; + }

ret = sdram_find(dev); - if (ret) + if (ret) { + debug("%s: sdram_find() failed (ret=%d)\n", __func__, ret); return ret; + } gd->ram_size = gd->arch.meminfo.total_32bit_memory;

debug("MRC output data length %#x at %p\n", pei_data->mrc_output_len,

Fix a few types that causes warnings on 64-bit machines.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: - Fix cast in bd82x6x_video_probe() also

arch/x86/cpu/ivybridge/sata.c | 4 ++-- drivers/video/ivybridge_igd.c | 4 ++-- 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/sata.c b/arch/x86/cpu/ivybridge/sata.c index 87ff872e20a..c7ffbc11fd9 100644 --- a/arch/x86/cpu/ivybridge/sata.c +++ b/arch/x86/cpu/ivybridge/sata.c @@ -53,7 +53,7 @@ static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch)

mode = fdt_getprop(blob, node, "intel,sata-mode", NULL); if (!mode || !strcmp(mode, "ahci")) { - u32 abar; + ulong abar;

debug("SATA: Controller in AHCI mode\n");

@@ -72,7 +72,7 @@ static void bd82x6x_sata_init(struct udevice *dev, struct udevice *pch)

/* Initialize AHCI memory-mapped space */ abar = dm_pci_read_bar32(dev, 5); - debug("ABAR: %08X\n", abar); + debug("ABAR: %08lx\n", abar); /* CAP (HBA Capabilities) : enable power management */ reg32 = readl(abar + 0x00); reg32 |= 0x0c006000; /* set PSC+SSC+SALP+SSS */ diff --git a/drivers/video/ivybridge_igd.c b/drivers/video/ivybridge_igd.c index 95d62a5392d..f16d725f3c7 100644 --- a/drivers/video/ivybridge_igd.c +++ b/drivers/video/ivybridge_igd.c @@ -802,7 +802,7 @@ static int gma_func0_init(struct udevice *dev) mtrr_add_request(MTRR_TYPE_WRCOMB, base, 256 << 20); mtrr_commit(true);

- gtt_bar = (void *)dm_pci_read_bar32(dev, 0); + gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0); debug("GT bar %p\n", gtt_bar); ret = gma_pm_init_pre_vbios(gtt_bar, rev); if (ret) @@ -824,7 +824,7 @@ static int bd82x6x_video_probe(struct udevice *dev) return ret;

/* Post VBIOS init */ - gtt_bar = (void *)dm_pci_read_bar32(dev, 0); + gtt_bar = (void *)(ulong)dm_pci_read_bar32(dev, 0); ret = gma_pm_init_post_vbios(dev, rev, gtt_bar); if (ret) return ret;

We almost always need the serial port before relocation, so mark it as such. This will ensure that it appears in the device tree for SPL, if used.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: None

arch/x86/dts/serial.dtsi | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/x86/dts/serial.dtsi b/arch/x86/dts/serial.dtsi index 54c3faf4514..22f7b54fed3 100644 --- a/arch/x86/dts/serial.dtsi +++ b/arch/x86/dts/serial.dtsi @@ -1,5 +1,6 @@ / { serial: serial { + u-boot,dm-pre-reloc; compatible = "ns16550"; reg = <0x3f8 8>; reg-shift = <0>;

Fix a cast in get_next_hob() that causes warnings on 64-bit machines.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: - Fix cast in get_guid_hob_data() also

arch/x86/include/asm/fsp/fsp_hob.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/include/asm/fsp/fsp_hob.h b/arch/x86/include/asm/fsp/fsp_hob.h index 3fb3546e27f..7c22bcd5cd8 100644 --- a/arch/x86/include/asm/fsp/fsp_hob.h +++ b/arch/x86/include/asm/fsp/fsp_hob.h @@ -139,7 +139,7 @@ struct hob_guid { */ static inline const struct hob_header *get_next_hob(const struct hob_header *hdr) { - return (const struct hob_header *)((u32)hdr + hdr->len); + return (const struct hob_header *)((uintptr_t)hdr + hdr->len); }

/** @@ -172,7 +172,7 @@ static inline bool end_of_hob(const struct hob_header *hdr) */ static inline void *get_guid_hob_data(const struct hob_header *hdr) { - return (void *)((u32)hdr + sizeof(struct hob_guid)); + return (void *)((uintptr_t)hdr + sizeof(struct hob_guid)); }

/**

Fix various compiler warnings in the x86 library code.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: - Move table-related changes to an earlier patch

arch/x86/lib/bios.c | 4 ++-- arch/x86/lib/pinctrl_ich6.c | 2 +- arch/x86/lib/pirq_routing.c | 4 ++-- 3 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/arch/x86/lib/bios.c b/arch/x86/lib/bios.c index 9324bdb83e8..66d7629a6dd 100644 --- a/arch/x86/lib/bios.c +++ b/arch/x86/lib/bios.c @@ -157,7 +157,7 @@ static void setup_realmode_idt(void) for (i = 0; i < 256; i++) { idts[i].cs = 0; idts[i].offset = 0x1000 + (i * __idt_handler_size); - write_idt_stub((void *)((u32)idts[i].offset), i); + write_idt_stub((void *)((ulong)idts[i].offset), i); }

/* @@ -227,7 +227,7 @@ static void vbe_set_graphics(int vesa_mode, struct vbe_mode_info *mode_info) mode_info->video_mode = (1 << 14) | vesa_mode; vbe_get_mode_info(mode_info);

- framebuffer = (unsigned char *)mode_info->vesa.phys_base_ptr; + framebuffer = (unsigned char *)(ulong)mode_info->vesa.phys_base_ptr; debug("VBE: resolution: %dx%d@%d\n", le16_to_cpu(mode_info->vesa.x_resolution), le16_to_cpu(mode_info->vesa.y_resolution), diff --git a/arch/x86/lib/pinctrl_ich6.c b/arch/x86/lib/pinctrl_ich6.c index 3f94cdf2dac..fb2d2940c95 100644 --- a/arch/x86/lib/pinctrl_ich6.c +++ b/arch/x86/lib/pinctrl_ich6.c @@ -104,7 +104,7 @@ static int ich6_pinctrl_cfg_pin(s32 gpiobase, s32 iobase, int pin_node)

/* if iobase is present, let's configure the pad */ if (iobase != -1) { - int iobase_addr; + ulong iobase_addr;

/* * The offset for the same pin for the IOBASE and GPIOBASE are diff --git a/arch/x86/lib/pirq_routing.c b/arch/x86/lib/pirq_routing.c index a93d355d8a2..c98526d6aa8 100644 --- a/arch/x86/lib/pirq_routing.c +++ b/arch/x86/lib/pirq_routing.c @@ -114,14 +114,14 @@ u32 copy_pirq_routing_table(u32 addr, struct irq_routing_table *rt) addr = ALIGN(addr, 16);

debug("Copying Interrupt Routing Table to 0x%x\n", addr); - memcpy((void *)addr, rt, rt->size); + memcpy((void *)(uintptr_t)addr, rt, rt->size);

/* * We do the sanity check here against the copied table after memcpy, * as something might go wrong after the memcpy, which is normally * due to the F segment decode is not turned on to systeam RAM. */ - rom_rt = (struct irq_routing_table *)addr; + rom_rt = (struct irq_routing_table *)(uintptr_t)addr; if (rom_rt->signature != PIRQ_SIGNATURE || rom_rt->version != PIRQ_VERSION || rom_rt->size % 16) { printf("Interrupt Routing Table not valid\n");

Add a new CONFIG_X86_64 option which will eventually cause U-Boot to be built as a 64-bit application, with SPL doing the 16/32-bit init.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: - Use tab instead of space in Kconfig help line

Changes in v2: None

arch/x86/Kconfig | 46 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 46 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 0884af22a79..5cd58d450b5 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -5,6 +5,52 @@ config SYS_ARCH default "x86"

choice + prompt "Run U-Boot in 32/64-bit mode" + default X86_RUN_32BIT + help + U-Boot can be built as a 32-bit binary which runs in 32-bit mode + even on 64-bit machines. In this case SPL is not used, and U-Boot + runs directly from the reset vector (via 16-bit start-up). + + Alternatively it can be run as a 64-bit binary, thus requiring a + 64-bit machine. In this case SPL runs in 32-bit mode (via 16-bit + start-up) then jumps to U-Boot in 64-bit mode. + + For now, 32-bit mode is recommended, as 64-bit is still + experimental and is missing a lot of features. + +config X86_RUN_32BIT + bool "32-bit" + help + Build U-Boot as a 32-bit binary with no SPL. This is the currently + supported normal setup. U-Boot will stay in 32-bit mode even on + 64-bit machines. When booting a 64-bit kernel, U-Boot will switch + to 64-bit just before starting the kernel. Only the bottom 4GB of + memory can be accessed through normal means, although + arch_phys_memset() can be used for basic access to other memory. + +config X86_RUN_64BIT + bool "64-bit" + select X86_64 + select SUPPORT_SPL + select SPL + select SPL_SEPARATE_BSS + help + Build U-Boot as a 64-bit binary with a 32-bit SPL. This is + experimental and many features are missing. U-Boot SPL starts up, + runs through the 16-bit and 32-bit init, then switches to 64-bit + mode and jumps to U-Boot proper. + +endchoice + +config X86_64 + bool + +config SPL_X86_64 + bool + depends on SPL + +choice prompt "Mainboard vendor" default VENDOR_EMULATION

At present all 16/32-bit init is controlled by CONFIG_X86_RESET_VECTOR. If this is enabled, then U-Boot is the 'first' boot loader and handles execution from the reset vector through to U-Boot's command prompt. If it is not enabled then U-Boot starts at the 32-bit entry and skips most of its init, assuming that the previous boot loader has done this already.

With the move to suport 64-bit operation, we have more cases to consider. The 16-bit and 32-bit init may be in SPL rather than in U-Boot proper.

Add Kconfig options which control the location of the 16-bit and the 32-bit init. These are not intended to be user-setting except for experimentation. Their values should be determined by whether 64-bit U-Boot is used.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: - Fix s/32-bit init/16-bit init/ and expand the comment

Changes in v2: None

arch/x86/Kconfig | 40 ++++++++++++++++++++++++++++++++++++++++ 1 file changed, 40 insertions(+)

diff --git a/arch/x86/Kconfig b/arch/x86/Kconfig index 5cd58d450b5..675b56f617e 100644 --- a/arch/x86/Kconfig +++ b/arch/x86/Kconfig @@ -135,6 +135,46 @@ config X86_RESET_VECTOR bool default n

+# The following options control where the 16-bit and 32-bit init lies +# If SPL is enabled then it normally holds this init code, and U-Boot proper +# is normally a 64-bit build. +# +# The 16-bit init refers to the reset vector and the small amount of code to +# get the processor into 32-bit mode. It may be in SPL or in U-Boot proper, +# or missing altogether if U-Boot is started from EFI or coreboot. +# +# The 32-bit init refers to processor init, running binary blobs including +# FSP, setting up interrupts and anything else that needs to be done in +# 32-bit code. It is normally in the same place as 16-bit init if that is +# enabled (i.e. they are both in SPL, or both in U-Boot proper). +config X86_16BIT_INIT + bool + depends on X86_RESET_VECTOR + default y if X86_RESET_VECTOR && !SPL + help + This is enabled when 16-bit init is in U-Boot proper + +config SPL_X86_16BIT_INIT + bool + depends on X86_RESET_VECTOR + default y if X86_RESET_VECTOR && SPL + help + This is enabled when 16-bit init is in SPL + +config X86_32BIT_INIT + bool + depends on X86_RESET_VECTOR + default y if X86_RESET_VECTOR && !SPL + help + This is enabled when 32-bit init is in U-Boot proper + +config SPL_X86_32BIT_INIT + bool + depends on X86_RESET_VECTOR + default y if X86_RESET_VECTOR && SPL + help + This is enabled when 32-bit init is in SPL + config RESET_SEG_START hex depends on X86_RESET_VECTOR

Use this new option to control the location of 16-bit init. This will allow us to place this in SPL if needed.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: None

Makefile | 7 ++++--- arch/x86/Makefile | 6 ++---- arch/x86/cpu/Makefile | 2 +- arch/x86/cpu/u-boot.lds | 2 +- 4 files changed, 8 insertions(+), 9 deletions(-)

diff --git a/Makefile b/Makefile index 262df7cd63b..1361e5d04f5 100644 --- a/Makefile +++ b/Makefile @@ -883,7 +883,7 @@ u-boot.hex u-boot.srec: u-boot FORCE $(call if_changed,objcopy)

OBJCOPYFLAGS_u-boot-nodtb.bin := -O binary \ - $(if $(CONFIG_X86_RESET_VECTOR),-R .start16 -R .resetvec) + $(if $(CONFIG_X86_16BIT_INIT),-R .start16 -R .resetvec)

binary_size_check: u-boot-nodtb.bin FORCE @file_size=$(shell wc -c u-boot-nodtb.bin | awk '{print $$1}') ; \ @@ -1076,8 +1076,9 @@ quiet_cmd_ldr = LD $@ cmd_ldr = $(LD) $(LDFLAGS_$(@F)) \ $(filter-out FORCE,$^) -o $@

-u-boot.rom: u-boot-x86-16bit.bin u-boot.bin FORCE \ - $(if $(CONFIG_HAVE_REFCODE),refcode.bin) +u-boot.rom: u-boot-x86-16bit.bin u-boot.bin \ + $(if $(CONFIG_SPL_X86_16BIT_INIT),spl/u-boot-spl.bin) \ + $(if $(CONFIG_HAVE_REFCODE),refcode.bin) FORCE $(call if_changed,binman)

OBJCOPYFLAGS_u-boot-x86-16bit.bin := -O binary -j .start16 -j .resetvec diff --git a/arch/x86/Makefile b/arch/x86/Makefile index d104a497301..dd0e22f970d 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -5,10 +5,8 @@ ifeq ($(CONFIG_EFI_APP),) head-y := arch/x86/cpu/start.o endif -ifeq ($(CONFIG_SPL_BUILD),y) -head-y += arch/x86/cpu/start16.o -head-y += arch/x86/cpu/resetvec.o -endif +head-$(CONFIG_$(SPL_)X86_16BIT_INIT) += arch/x86/cpu/start16.o +head-$(CONFIG_$(SPL_)X86_16BIT_INIT) += arch/x86/cpu/resetvec.o

libs-y += arch/x86/cpu/ libs-y += arch/x86/lib/ diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index f5b8c9e3632..fd81310df69 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -9,7 +9,7 @@ #

extra-y = start.o -obj-$(CONFIG_X86_RESET_VECTOR) += resetvec.o start16.o +extra-$(CONFIG_$(SPL_)X86_16BIT_INIT) += resetvec.o start16.o obj-y += interrupts.o cpu.o cpu_x86.o call64.o setjmp.o

AFLAGS_REMOVE_call32.o := -mregparm=3 \ diff --git a/arch/x86/cpu/u-boot.lds b/arch/x86/cpu/u-boot.lds index cca536b2723..186718d8f9d 100644 --- a/arch/x86/cpu/u-boot.lds +++ b/arch/x86/cpu/u-boot.lds @@ -103,7 +103,7 @@ SECTIONS /DISCARD/ : { *(.interp*) } /DISCARD/ : { *(.gnu*) }

-#ifdef CONFIG_X86_RESET_VECTOR +#ifdef CONFIG_X86_16BIT_INIT /* * The following expressions place the 16-bit Real-Mode code and * Reset Vector at the end of the Flash ROM

Use this new option to control the location of 32-bit init. This will allow us to place this in SPL if needed.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: None

arch/x86/cpu/intel_common/Makefile | 10 ++++++---- arch/x86/lib/init_helpers.c | 2 +- 2 files changed, 7 insertions(+), 5 deletions(-)

diff --git a/arch/x86/cpu/intel_common/Makefile b/arch/x86/cpu/intel_common/Makefile index 804c539ca4b..1145e7896cc 100644 --- a/arch/x86/cpu/intel_common/Makefile +++ b/arch/x86/cpu/intel_common/Makefile @@ -4,13 +4,15 @@ # SPDX-License-Identifier: GPL-2.0+ #

-obj-$(CONFIG_HAVE_MRC) += car.o +ifdef CONFIG_HAVE_MRC +obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += car.o +obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += me_status.o +obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += report_platform.o +obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += mrc.o +endif obj-y += cpu.o obj-y += lpc.o -obj-$(CONFIG_HAVE_MRC) += me_status.o ifndef CONFIG_TARGET_EFI obj-y += microcode.o endif obj-y += pch.o -obj-$(CONFIG_HAVE_MRC) += report_platform.o -obj-$(CONFIG_HAVE_MRC) += mrc.o diff --git a/arch/x86/lib/init_helpers.c b/arch/x86/lib/init_helpers.c index 2a186fc22f6..420393b843e 100644 --- a/arch/x86/lib/init_helpers.c +++ b/arch/x86/lib/init_helpers.c @@ -19,7 +19,7 @@ __weak ulong board_get_usable_ram_top(ulong total_size)

int init_cache_f_r(void) { -#if defined(CONFIG_X86_RESET_VECTOR) & !defined(CONFIG_HAVE_FSP) +#if CONFIG_IS_ENABLED(X86_32BIT_INIT) && !defined(CONFIG_HAVE_FSP) int ret;

ret = mtrr_commit(false);

Update the Makefile so that some 32-bit init can be built into SPL rather than U-Boot proper.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: None

arch/x86/cpu/ivybridge/Makefile | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/cpu/ivybridge/Makefile b/arch/x86/cpu/ivybridge/Makefile index 498e71a1b90..d13d0d3f694 100644 --- a/arch/x86/cpu/ivybridge/Makefile +++ b/arch/x86/cpu/ivybridge/Makefile @@ -7,12 +7,12 @@ ifdef CONFIG_HAVE_FSP obj-y += fsp_configs.o ivybridge.o else -obj-y += cpu.o +obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += cpu.o obj-y += early_me.o obj-y += lpc.o obj-y += model_206ax.o obj-y += northbridge.o obj-y += sata.o -obj-y += sdram.o +obj-$(CONFIG_$(SPL_)X86_32BIT_INIT) += sdram.o endif obj-y += bd82x6x.o

Add code to start up U-Boot in 64-bit mode. It is fairly simple since we are running from RAM and SPL has done the low-level init.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v3: - Drop unused headers - Drop unused board_debug_uart_init function - Use call instead of callq

Changes in v2: None

arch/x86/Makefile | 5 +++++ arch/x86/cpu/Makefile | 4 ++++ arch/x86/cpu/start64.S | 28 ++++++++++++++++++++++++++++ 3 files changed, 37 insertions(+) create mode 100644 arch/x86/cpu/start64.S

diff --git a/arch/x86/Makefile b/arch/x86/Makefile index dd0e22f970d..4be1c353cc9 100644 --- a/arch/x86/Makefile +++ b/arch/x86/Makefile @@ -3,8 +3,13 @@ #

ifeq ($(CONFIG_EFI_APP),) +ifdef CONFIG_$(SPL_)X86_64 +head-y := arch/x86/cpu/start64.o +else head-y := arch/x86/cpu/start.o endif +endif + head-$(CONFIG_$(SPL_)X86_16BIT_INIT) += arch/x86/cpu/start16.o head-$(CONFIG_$(SPL_)X86_16BIT_INIT) += arch/x86/cpu/resetvec.o

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index fd81310df69..97b26b0fe76 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -8,7 +8,11 @@ # SPDX-License-Identifier: GPL-2.0+ #

+ifeq ($(CONFIG_$(SPL_)X86_64),y) +extra-y = start64.o +else extra-y = start.o +endif extra-$(CONFIG_$(SPL_)X86_16BIT_INIT) += resetvec.o start16.o obj-y += interrupts.o cpu.o cpu_x86.o call64.o setjmp.o

diff --git a/arch/x86/cpu/start64.S b/arch/x86/cpu/start64.S new file mode 100644 index 00000000000..651f16ac89c --- /dev/null +++ b/arch/x86/cpu/start64.S @@ -0,0 +1,28 @@ +/* + * 64-bit x86 Startup Code + * + * (C) Copyright 216 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> + +.section .text +.code64 +.globl _start +.type _start, @function +_start: + /* Set up memory using the existing stack */ + mov %rsp, %rdi + call board_init_f_alloc_reserve + mov %rax, %rsp + + call board_init_f_init_reserve + + call board_init_f + call board_init_f_r + + /* Should not return here */ + jmp .

Since 'gd' is just a normal variable on 64-bit x86, it is relocated by the time we get to board_init_r(). The old 'gd' variable is passed in as parameter to board_init_r(), presumably for this situation.

Assign it on 64-bit x86 so that gd points to the correct data.

Options to improve this: - Make gd a fixed register and remove the board_init_r() parameter - Make all archs use this board_init_r() parameter

The second has a TODO in the code. The first has a TODO in a future commit ('x86: Support global_data on x86_64')

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v3: - Add a TODO to board_init_r() regarding the use of the new_gd parameter

Changes in v2: None

common/board_r.c | 10 ++++++++++ 1 file changed, 10 insertions(+)

diff --git a/common/board_r.c b/common/board_r.c index 1bdd5a35366..ddfb1e1fcad 100644 --- a/common/board_r.c +++ b/common/board_r.c @@ -974,6 +974,16 @@ static init_fnc_t init_sequence_r[] = {

void board_init_r(gd_t *new_gd, ulong dest_addr) { + /* + * Set up the new global data pointer. So far only x86 does this + * here. + * TODO(sjg@chromium.org): Consider doing this for all archs, or + * dropping the new_gd parameter. + */ +#if CONFIG_IS_ENABLED(X86_64) + arch_setup_gd(new_gd); +#endif + #ifdef CONFIG_NEEDS_MANUAL_RELOC int i; #endif

Add a 64-bit relocation function. SPL loads U-Boot into RAM at a fixed address and runs it. U-Boot then relocates itself to the top of RAM using this relocation function.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: None

arch/x86/lib/relocate.c | 45 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 45 insertions(+)

diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c index 861e6675b3b..d207fddb756 100644 --- a/arch/x86/lib/relocate.c +++ b/arch/x86/lib/relocate.c @@ -47,6 +47,46 @@ int clear_bss(void) return 0; }

+#if CONFIG_IS_ENABLED(X86_64) +static void do_elf_reloc_fixups64(unsigned int text_base, uintptr_t size, + Elf64_Rela *re_src, Elf64_Rela *re_end) +{ + Elf64_Addr *offset_ptr_rom, *last_offset = NULL; + Elf64_Addr *offset_ptr_ram; + + do { + /* Get the location from the relocation entry */ + offset_ptr_rom = (Elf64_Addr *)(uintptr_t)re_src->r_offset; + + /* Check that the location of the relocation is in .text */ + if (offset_ptr_rom >= (Elf64_Addr *)(uintptr_t)text_base && + offset_ptr_rom > last_offset) { + /* Switch to the in-RAM version */ + offset_ptr_ram = (Elf64_Addr *)((ulong)offset_ptr_rom + + gd->reloc_off); + + /* Check that the target points into .text */ + if (*offset_ptr_ram >= text_base && + *offset_ptr_ram <= text_base + size) { + *offset_ptr_ram = gd->reloc_off + + re_src->r_addend; + } else { + debug(" %p: %lx: rom reloc %lx, ram %p, value %lx, limit %" + PRIXPTR "\n", + re_src, (ulong)re_src->r_info, + (ulong)re_src->r_offset, offset_ptr_ram, + (ulong)*offset_ptr_ram, text_base + size); + } + } else { + debug(" %p: %lx: rom reloc %lx, last %p\n", re_src, + (ulong)re_src->r_info, (ulong)re_src->r_offset, + last_offset); + } + last_offset = offset_ptr_rom; + + } while (++re_src < re_end); +} +#else static void do_elf_reloc_fixups32(unsigned int text_base, uintptr_t size, Elf32_Rel *re_src, Elf32_Rel *re_end) { @@ -84,6 +124,7 @@ static void do_elf_reloc_fixups32(unsigned int text_base, uintptr_t size,

} while (++re_src < re_end); } +#endif

/* * This function has more error checking than you might expect. Please see @@ -109,7 +150,11 @@ int do_elf_reloc_fixups(void) #else panic("No CONFIG_SYS_TEXT_BASE"); #endif +#if CONFIG_IS_ENABLED(X86_64) + do_elf_reloc_fixups64(text_base, size, re_src, re_end); +#else do_elf_reloc_fixups32(text_base, size, re_src, re_end); +#endif

return 0; }

Addresses should not be cast to size_t. Use uintptr_t instead.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: None

arch/x86/lib/relocate.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/lib/relocate.c b/arch/x86/lib/relocate.c index d207fddb756..1da5210d27b 100644 --- a/arch/x86/lib/relocate.c +++ b/arch/x86/lib/relocate.c @@ -26,7 +26,7 @@ DECLARE_GLOBAL_DATA_PTR;

int copy_uboot_to_ram(void) { - size_t len = (size_t)&__data_end - (size_t)&__text_start; + size_t len = (uintptr_t)&__data_end - (uintptr_t)&__text_start;

if (gd->flags & GD_FLG_SKIP_RELOC) return 0; @@ -38,7 +38,7 @@ int copy_uboot_to_ram(void) int clear_bss(void) { ulong dst_addr = (ulong)&__bss_start + gd->reloc_off; - size_t len = (size_t)&__bss_end - (size_t)&__bss_start; + size_t len = (uintptr_t)&__bss_end - (uintptr_t)&__bss_start;

if (gd->flags & GD_FLG_SKIP_RELOC) return 0;

SPL needs to set up the machine ready for loading 64-bit U-Boot and jumping to it. Call the existing init routines in order to accomplish this.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v3: - Update copyright year - Drop duplicate line in header commment - Add a comment about stack position to x86_spl_init() - Add a parameter to the use of the SPL_LOAD_IMAGE_METHOD() macro - Fix printf() warning in spl_board_load_image()

Changes in v2: None

arch/x86/include/asm/spl.h | 8 +++ arch/x86/lib/Makefile | 1 + arch/x86/lib/spl.c | 153 +++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 162 insertions(+) create mode 100644 arch/x86/include/asm/spl.h create mode 100644 arch/x86/lib/spl.c

diff --git a/arch/x86/include/asm/spl.h b/arch/x86/include/asm/spl.h new file mode 100644 index 00000000000..d48a3fcb741 --- /dev/null +++ b/arch/x86/include/asm/spl.h @@ -0,0 +1,8 @@ +/* + * Copyright (C) 2017 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + * + * This file is required for SPL to build, but is empty. + */ diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 723288f7b2b..67117c36e83 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -37,6 +37,7 @@ endif obj-y += tables.o obj-$(CONFIG_CMD_ZBOOT) += zimage.o obj-$(CONFIG_HAVE_FSP) += fsp/ +obj-$(CONFIG_SPL_BUILD) += spl.o

extra-$(CONFIG_USE_PRIVATE_LIBGCC) += lib.a

diff --git a/arch/x86/lib/spl.c b/arch/x86/lib/spl.c new file mode 100644 index 00000000000..7403d152125 --- /dev/null +++ b/arch/x86/lib/spl.c @@ -0,0 +1,153 @@ +/* + * Copyright (c) 2016 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <debug_uart.h> +#include <spl.h> +#include <asm/cpu.h> +#include <asm/init_helpers.h> +#include <asm/mtrr.h> +#include <asm/processor.h> +#include <asm-generic/sections.h> + +DECLARE_GLOBAL_DATA_PTR; + +static int x86_spl_init(void) +{ + /* + * TODO(sjg@chromium.org): We use this area of RAM for the stack + * and global_data in SPL. Once U-Boot starts up and releocates it + * is not needed. We could make this a CONFIG option or perhaps + * place it immediately below CONFIG_SYS_TEXT_BASE. + */ + char *ptr = (char *)0x110000; + int ret; + + debug("%s starting\n", __func__); + ret = spl_init(); + if (ret) { + debug("%s: spl_init() failed\n", __func__); + return ret; + } + preloader_console_init(); + + ret = arch_cpu_init(); + if (ret) { + debug("%s: arch_cpu_init() failed\n", __func__); + return ret; + } + ret = arch_cpu_init_dm(); + if (ret) { + debug("%s: arch_cpu_init_dm() failed\n", __func__); + return ret; + } + ret = print_cpuinfo(); + if (ret) { + debug("%s: print_cpuinfo() failed\n", __func__); + return ret; + } + ret = dram_init(); + if (ret) { + debug("%s: dram_init() failed\n", __func__); + return ret; + } + memset(&__bss_start, 0, (ulong)&__bss_end - (ulong)&__bss_start); + + /* TODO(sjg@chromium.org): Consider calling cpu_init_r() here */ + ret = interrupt_init(); + if (ret) { + debug("%s: interrupt_init() failed\n", __func__); + return ret; + } + + /* + * The stack grows down from ptr. Put the global data at ptr. This + * will only be used for SPL. Once SPL loads U-Boot proper it will + * set up its own stack. + */ + gd->new_gd = (struct global_data *)ptr; + memcpy(gd->new_gd, gd, sizeof(*gd)); + arch_setup_gd(gd->new_gd); + gd->start_addr_sp = (ulong)ptr; + + /* Cache the SPI flash. Otherwise copying the code to RAM takes ages */ + ret = mtrr_add_request(MTRR_TYPE_WRBACK, + (1ULL << 32) - CONFIG_XIP_ROM_SIZE, + CONFIG_XIP_ROM_SIZE); + if (ret) { + debug("%s: SPI cache setup failed\n", __func__); + return ret; + } + + return 0; +} + +void board_init_f(ulong flags) +{ + int ret; + + ret = x86_spl_init(); + if (ret) { + debug("Error %d\n", ret); + hang(); + } + + /* Uninit CAR and jump to board_init_f_r() */ + board_init_f_r_trampoline(gd->start_addr_sp); +} + +void board_init_f_r(void) +{ + init_cache_f_r(); + gd->flags &= ~GD_FLG_SERIAL_READY; + debug("cache status %d\n", dcache_status()); + board_init_r(gd, 0); +} + +u32 spl_boot_device(void) +{ + return BOOT_DEVICE_BOARD; +} + +int spl_start_uboot(void) +{ + return 0; +} + +void spl_board_announce_boot_device(void) +{ + printf("SPI flash"); +} + +static int spl_board_load_image(struct spl_image_info *spl_image, + struct spl_boot_device *bootdev) +{ + spl_image->size = CONFIG_SYS_MONITOR_LEN; + spl_image->entry_point = CONFIG_SYS_TEXT_BASE; + spl_image->load_addr = CONFIG_SYS_TEXT_BASE; + spl_image->os = IH_OS_U_BOOT; + spl_image->name = "U-Boot"; + + debug("Loading to %lx\n", spl_image->load_addr); + + return 0; +} +SPL_LOAD_IMAGE_METHOD("SPI", 0, BOOT_DEVICE_BOARD, spl_board_load_image); + +int spl_spi_load_image(void) +{ + return -EPERM; +} + +void __noreturn jump_to_image_no_args(struct spl_image_info *spl_image) +{ + int ret; + + printf("Jumping to 64-bit U-Boot: Note many features are missing\n"); + ret = cpu_jump_to_64bit_uboot(spl_image->entry_point); + debug("ret=%d\n", ret); + while (1); +}

When SPL and U-Boot proper have different settings for this flag, we need to use the correct one. Fix this up in the interrupt code.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: None

arch/x86/cpu/i386/interrupt.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/cpu/i386/interrupt.c b/arch/x86/cpu/i386/interrupt.c index 8dfbb4880fd..a05830326b5 100644 --- a/arch/x86/cpu/i386/interrupt.c +++ b/arch/x86/cpu/i386/interrupt.c @@ -234,7 +234,7 @@ int disable_interrupts(void) { long flags;

-#ifdef CONFIG_X86_64 +#if CONFIG_IS_ENABLED(X86_64) asm volatile ("pushfq ; popq %0 ; cli\n" : "=g" (flags) : ); #else asm volatile ("pushfl ; popl %0 ; cli\n" : "=g" (flags) : );

This needs a different image format from 32-bit x86, so add a new link script.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: None

arch/x86/cpu/config.mk | 6 ++++ arch/x86/cpu/u-boot-64.lds | 76 ++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 82 insertions(+) create mode 100644 arch/x86/cpu/u-boot-64.lds

diff --git a/arch/x86/cpu/config.mk b/arch/x86/cpu/config.mk index 1263221e699..4c99a35621d 100644 --- a/arch/x86/cpu/config.mk +++ b/arch/x86/cpu/config.mk @@ -15,3 +15,9 @@ LDPPFLAGS += -DRESET_SEG_SIZE=$(CONFIG_RESET_SEG_SIZE) LDPPFLAGS += -DRESET_VEC_LOC=$(CONFIG_RESET_VEC_LOC) LDPPFLAGS += -DSTART_16=$(CONFIG_SYS_X86_START16) LDPPFLAGS += -DRESET_BASE="CONFIG_SYS_TEXT_BASE + (CONFIG_SYS_MONITOR_LEN - RESET_SEG_SIZE)" + +ifdef CONFIG_X86_64 +ifndef CONFIG_SPL_BUILD +LDSCRIPT = $(srctree)/arch/x86/cpu/u-boot-64.lds +endif +endif diff --git a/arch/x86/cpu/u-boot-64.lds b/arch/x86/cpu/u-boot-64.lds new file mode 100644 index 00000000000..718790c79a9 --- /dev/null +++ b/arch/x86/cpu/u-boot-64.lds @@ -0,0 +1,76 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +OUTPUT_FORMAT("elf64-x86-64", "elf64-x86-64", "elf64-x86-64") +OUTPUT_ARCH(i386:x86-64) +ENTRY(_start) + +SECTIONS +{ +#ifndef CONFIG_CMDLINE + /DISCARD/ : { *(.u_boot_list_2_cmd_*) } +#endif + + . = CONFIG_SYS_TEXT_BASE; /* Location of bootcode in flash */ + __text_start = .; + .text : { *(.text*); } + + . = ALIGN(4); + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data*) } + + . = ALIGN(4); + .hash : { *(.hash*) } + + . = ALIGN(4); + .got : { *(.got*) } + + . = ALIGN(4); + __data_end = .; + __init_end = .; + + . = ALIGN(4); + .dynsym : { *(.dynsym*) } + + . = ALIGN(4); + __rel_dyn_start = .; + .rela.dyn : { + *(.rela*) + } + __rel_dyn_end = .; + . = ALIGN(4); + + .dynamic : { *(.dynamic) } + + . = ALIGN(4); + _end = .; + + .bss __rel_dyn_start (OVERLAY) : { + __bss_start = .; + *(.bss) + *(COM*) + . = ALIGN(4); + __bss_end = .; + } + + /DISCARD/ : { *(.dynsym) } + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } +}

If SPL is used it is always build in 32-bit mode. Add a link script to handle the correct placement of the sections.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: None

arch/x86/cpu/u-boot-spl.lds | 74 +++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 74 insertions(+) create mode 100644 arch/x86/cpu/u-boot-spl.lds

diff --git a/arch/x86/cpu/u-boot-spl.lds b/arch/x86/cpu/u-boot-spl.lds new file mode 100644 index 00000000000..8a38d58f123 --- /dev/null +++ b/arch/x86/cpu/u-boot-spl.lds @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2002 + * Daniel Engström, Omicron Ceti AB, daniel@omicron.se. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +OUTPUT_FORMAT("elf32-i386", "elf32-i386", "elf32-i386") +OUTPUT_ARCH(i386) +ENTRY(_start) + +SECTIONS +{ +#ifndef CONFIG_CMDLINE + /DISCARD/ : { *(.u_boot_list_2_cmd_*) } +#endif + + . = CONFIG_SPL_TEXT_BASE; /* Location of bootcode in flash */ + __text_start = .; + .text : { *(.text*); } + + . = ALIGN(4); + + . = ALIGN(4); + .u_boot_list : { + KEEP(*(SORT(.u_boot_list*))); + } + + . = ALIGN(4); + .rodata : { *(SORT_BY_ALIGNMENT(SORT_BY_NAME(.rodata*))) } + + . = ALIGN(4); + .data : { *(.data*) } + + . = ALIGN(4); + __data_end = .; + __init_end = .; + + _image_binary_end = .; + + . = 0x120000; + .bss (OVERLAY) : { + __bss_start = .; + *(.bss*) + *(COM*) + . = ALIGN(4); + __bss_end = .; + } + __bss_size = __bss_end - __bss_start; + + /DISCARD/ : { *(.dynstr*) } + /DISCARD/ : { *(.dynamic*) } + /DISCARD/ : { *(.plt*) } + /DISCARD/ : { *(.interp*) } + /DISCARD/ : { *(.gnu*) } + +#ifdef CONFIG_SPL_X86_16BIT_INIT + /* + * The following expressions place the 16-bit Real-Mode code and + * Reset Vector at the end of the Flash ROM + */ + . = START_16 - RESET_SEG_START; + .start16 : AT (START_16) { + KEEP(*(.start16)); + } + + . = RESET_VEC_LOC - RESET_SEG_START; + .resetvec : AT (RESET_VEC_LOC) { + KEEP(*(.resetvec)); + } +#endif + +}

When SPL is used we need to build the 16-bit start-up code. Add Makefile rules to handle this.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: None

scripts/Makefile.spl | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)

diff --git a/scripts/Makefile.spl b/scripts/Makefile.spl index 82cfc601b29..b52f9963f7d 100644 --- a/scripts/Makefile.spl +++ b/scripts/Makefile.spl @@ -179,6 +179,8 @@ ifeq ($(CONFIG_SYS_SOC),"at91") ALL-y += boot.bin endif

+ALL-$(CONFIG_SPL_X86_16BIT_INIT) += $(obj)/u-boot-x86-16bit-spl.bin + ALL-$(CONFIG_ARCH_ZYNQ) += $(obj)/boot.bin ALL-$(CONFIG_ARCH_ZYNQMP) += $(obj)/boot.bin

@@ -263,11 +265,16 @@ endif quiet_cmd_objcopy = OBJCOPY $@ cmd_objcopy = $(OBJCOPY) $(OBJCOPYFLAGS) $(OBJCOPYFLAGS_$(@F)) $< $@

-OBJCOPYFLAGS_$(SPL_BIN)-nodtb.bin = $(SPL_OBJCFLAGS) -O binary +OBJCOPYFLAGS_$(SPL_BIN)-nodtb.bin = $(SPL_OBJCFLAGS) -O binary \ + $(if $(CONFIG_SPL_X86_16BIT_INIT),-R .start16 -R .resetvec)

$(obj)/$(SPL_BIN)-nodtb.bin: $(obj)/$(SPL_BIN) FORCE $(call if_changed,objcopy)

+OBJCOPYFLAGS_u-boot-x86-16bit-spl.bin := -O binary -j .start16 -j .resetvec +$(obj)/u-boot-x86-16bit-spl.bin: $(obj)/u-boot-spl FORCE + $(call if_changed,objcopy) + LDFLAGS_$(SPL_BIN) += -T u-boot-spl.lds $(LDFLAGS_FINAL) ifneq ($(CONFIG_SPL_TEXT_BASE),) LDFLAGS_$(SPL_BIN) += -Ttext $(CONFIG_SPL_TEXT_BASE)

Remove the very old x86 code and add support for 64-bit.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: None

arch/x86/include/asm/byteorder.h | 17 +++++++++-------- 1 file changed, 9 insertions(+), 8 deletions(-)

diff --git a/arch/x86/include/asm/byteorder.h b/arch/x86/include/asm/byteorder.h index 7dfeb8bbed2..a2d1fd8703b 100644 --- a/arch/x86/include/asm/byteorder.h +++ b/arch/x86/include/asm/byteorder.h @@ -8,24 +8,25 @@

static __inline__ __u32 ___arch__swab32(__u32 x) { -#ifdef CONFIG_X86_BSWAP __asm__("bswap %0" : "=r" (x) : "0" (x)); -#else - __asm__("xchgb %b0,%h0\n\t" /* swap lower bytes */ - "rorl $16,%0\n\t" /* swap words */ - "xchgb %b0,%h0" /* swap higher bytes */ - :"=q" (x) - : "0" (x)); -#endif + return x; }

+#define _constant_swab16(x) ((__u16)( \ + (((__u16)(x) & (__u16)0x00ffU) << 8) | \ + (((__u16)(x) & (__u16)0xff00U) >> 8))) + static __inline__ __u16 ___arch__swab16(__u16 x) { +#if CONFIG_IS_ENABLED(X86_64) + return _constant_swab16(x); +#else __asm__("xchgb %b0,%h0" /* swap bytes */ \ : "=q" (x) \ : "0" (x)); \ return x; +#endif }

#define __arch__swab32(x) ___arch__swab32(x)

This doesn't build at present and is not used in a 64-bit build. Disable it for now.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: None

arch/x86/include/asm/cpu.h | 3 +++ 1 file changed, 3 insertions(+)

diff --git a/arch/x86/include/asm/cpu.h b/arch/x86/include/asm/cpu.h index 540024a8592..b408515582c 100644 --- a/arch/x86/include/asm/cpu.h +++ b/arch/x86/include/asm/cpu.h @@ -159,6 +159,8 @@ static inline unsigned int cpuid_edx(unsigned int op) return edx; }

+#if !CONFIG_IS_ENABLED(X86_64) + /* Standard macro to see if a specific flag is changeable */ static inline int flag_is_changeable_p(uint32_t flag) { @@ -179,6 +181,7 @@ static inline int flag_is_changeable_p(uint32_t flag) : "ir" (flag)); return ((f1^f2) & flag) != 0; } +#endif

static inline void mfence(void) {

Adjust types as needed to support 64-bit compilation.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v3: None Changes in v2: None

arch/x86/include/asm/posix_types.h | 5 +++++ arch/x86/include/asm/types.h | 5 +++++ 2 files changed, 10 insertions(+)

diff --git a/arch/x86/include/asm/posix_types.h b/arch/x86/include/asm/posix_types.h index 5529f32702c..717f6cb8e01 100644 --- a/arch/x86/include/asm/posix_types.h +++ b/arch/x86/include/asm/posix_types.h @@ -16,8 +16,13 @@ typedef int __kernel_pid_t; typedef unsigned short __kernel_ipc_pid_t; typedef unsigned short __kernel_uid_t; typedef unsigned short __kernel_gid_t; +#if CONFIG_IS_ENABLED(X86_64) +typedef unsigned long __kernel_size_t; +typedef long __kernel_ssize_t; +#else typedef unsigned int __kernel_size_t; typedef int __kernel_ssize_t; +#endif typedef int __kernel_ptrdiff_t; typedef long __kernel_time_t; typedef long __kernel_suseconds_t; diff --git a/arch/x86/include/asm/types.h b/arch/x86/include/asm/types.h index 880dcb488a5..a47e581fe3a 100644 --- a/arch/x86/include/asm/types.h +++ b/arch/x86/include/asm/types.h @@ -44,7 +44,12 @@ typedef __INT64_TYPE__ s64; typedef __UINT64_TYPE__ u64; #endif

+#if CONFIG_IS_ENABLED(X86_64) +#define BITS_PER_LONG 64 +#else #define BITS_PER_LONG 32 +#endif + /* Dma addresses are 32-bits wide. */

typedef u32 dma_addr_t;

This is not supported, so disable it for now.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: None

arch/x86/lib/Makefile | 2 ++ drivers/pci/pci_rom.c | 2 +- 2 files changed, 3 insertions(+), 1 deletion(-)

diff --git a/arch/x86/lib/Makefile b/arch/x86/lib/Makefile index 67117c36e83..f737b7ecc2e 100644 --- a/arch/x86/lib/Makefile +++ b/arch/x86/lib/Makefile @@ -5,9 +5,11 @@ # SPDX-License-Identifier: GPL-2.0+ #

+ifndef CONFIG_X86_64 obj-y += bios.o obj-y += bios_asm.o obj-y += bios_interrupts.o +endif obj-$(CONFIG_CMD_BOOTM) += bootm.o obj-y += cmd_boot.o obj-$(CONFIG_SEABIOS) += coreboot_table.o diff --git a/drivers/pci/pci_rom.c b/drivers/pci/pci_rom.c index cd083f7dde8..57204c4f3f1 100644 --- a/drivers/pci/pci_rom.c +++ b/drivers/pci/pci_rom.c @@ -334,7 +334,7 @@ int dm_pci_run_vga_bios(struct udevice *dev, int (*int15_handler)(void), goto err; #endif } else { -#ifdef CONFIG_X86 +#if defined(CONFIG_X86) && CONFIG_IS_ENABLED(X86_32BIT_INIT) bios_set_interrupt_handler(0x15, int15_handler);

bios_run_on_x86(dev, (unsigned long)ram, vesa_mode,

These are currently not supported. Calling 64-bit code from 64-bit U-Boot is much simpler, so this code is not needed. setjmp() is not yet implemented for 64-bit.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v3: - Add a TODO indicating that booting 32- and 64-bit kernels should be supported

Changes in v2: None

arch/x86/cpu/Makefile | 6 +++++- arch/x86/lib/bootm.c | 7 +++++++ 2 files changed, 12 insertions(+), 1 deletion(-)

diff --git a/arch/x86/cpu/Makefile b/arch/x86/cpu/Makefile index 7f89ff047fa..f0135a759e9 100644 --- a/arch/x86/cpu/Makefile +++ b/arch/x86/cpu/Makefile @@ -14,7 +14,11 @@ else extra-y = start.o endif extra-$(CONFIG_$(SPL_)X86_16BIT_INIT) += resetvec.o start16.o -obj-y += cpu.o cpu_x86.o call64.o setjmp.o +ifndef CONFIG_$(SPL_)X86_64 +obj-y += call64.o setjmp.o +endif + +obj-y += cpu.o cpu_x86.o

AFLAGS_REMOVE_call32.o := -mregparm=3 \ $(if $(CONFIG_EFI_STUB_64BIT),-march=i386 -m32) diff --git a/arch/x86/lib/bootm.c b/arch/x86/lib/bootm.c index e5e63f6888e..3c3d9e1e800 100644 --- a/arch/x86/lib/bootm.c +++ b/arch/x86/lib/bootm.c @@ -155,7 +155,14 @@ int boot_linux_kernel(ulong setup_base, ulong load_address, bool image_64bit) puts("Cannot boot 64-bit kernel on 32-bit machine\n"); return -EFAULT; } + /* At present 64-bit U-Boot does not support booting a + * kernel. + * TODO(sjg@chromium.org): Support booting both 32-bit and + * 64-bit kernels from 64-bit U-Boot. + */ +#if !CONFIG_IS_ENABLED(X86_64) return cpu_jump_to_64bit(setup_base, load_address); +#endif } else { /* * Set %ebx, %ebp, and %edi to 0, %esi to point to the

To avoid using BSS in SPL before SDRAM is set up, move this field to global_data.

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v3: None Changes in v2: None

arch/x86/cpu/turbo.c | 8 ++++---- arch/x86/include/asm/global_data.h | 1 + 2 files changed, 5 insertions(+), 4 deletions(-)

diff --git a/arch/x86/cpu/turbo.c b/arch/x86/cpu/turbo.c index 254d0de0e4b..bbd255efc0a 100644 --- a/arch/x86/cpu/turbo.c +++ b/arch/x86/cpu/turbo.c @@ -12,6 +12,8 @@ #include <asm/processor.h> #include <asm/turbo.h>

+DECLARE_GLOBAL_DATA_PTR; + #if CONFIG_CPU_INTEL_TURBO_NOT_PACKAGE_SCOPED static inline int get_global_turbo_state(void) { @@ -22,16 +24,14 @@ static inline void set_global_turbo_state(int state) { } #else -static int g_turbo_state = TURBO_UNKNOWN; - static inline int get_global_turbo_state(void) { - return g_turbo_state; + return gd->arch.turbo_state; }

static inline void set_global_turbo_state(int state) { - g_turbo_state = state; + gd->arch.turbo_state = state; } #endif

diff --git a/arch/x86/include/asm/global_data.h b/arch/x86/include/asm/global_data.h index 43a59a3b0c9..4570bc7a4ad 100644 --- a/arch/x86/include/asm/global_data.h +++ b/arch/x86/include/asm/global_data.h @@ -93,6 +93,7 @@ struct arch_global_data { char *mrc_output; unsigned int mrc_output_len; ulong table; /* Table pointer from previous loader */ + int turbo_state; /* Current turbo state */ struct irq_routing_table *pirq_routing_table; #ifdef CONFIG_SEABIOS u32 high_table_ptr;

Update config.mk settings to support both 32-bit and 64-bit U-Boot.

Signed-off-by: Simon Glass sjg@chromium.org Reviewed-by: Bin Meng bmeng.cn@gmail.com ---

Changes in v3: None Changes in v2: None

arch/x86/config.mk | 30 ++++++++++++++++++++++++++++-- arch/x86/cpu/config.mk | 2 -- 2 files changed, 28 insertions(+), 4 deletions(-)

diff --git a/arch/x86/config.mk b/arch/x86/config.mk index 1697dca47fb..74b87ceac54 100644 --- a/arch/x86/config.mk +++ b/arch/x86/config.mk @@ -15,11 +15,25 @@ PF_CPPFLAGS_X86 := $(call cc-option, -fno-toplevel-reorder, \

PLATFORM_CPPFLAGS += $(PF_CPPFLAGS_X86) PLATFORM_CPPFLAGS += -fno-dwarf2-cfi-asm + +ifdef CONFIG_SPL_BUILD +IS_32BIT := y +else +ifndef CONFIG_X86_64 +IS_32BIT := y +endif +endif + +ifeq ($(IS_32BIT),y) PLATFORM_CPPFLAGS += -march=i386 -m32 +else +PLATFORM_CPPFLAGS += $(if $(CONFIG_SPL_BUILD),,-fpic) -fno-common +endif

PLATFORM_RELFLAGS += -ffunction-sections -fvisibility=hidden

-PLATFORM_LDFLAGS += -Bsymbolic -Bsymbolic-functions -m elf_i386 +PLATFORM_LDFLAGS += -Bsymbolic -Bsymbolic-functions +PLATFORM_LDFLAGS += -m $(if $(IS_32BIT),elf_i386,elf_x86_64)

LDFLAGS_FINAL += --wrap=__divdi3 --wrap=__udivdi3 LDFLAGS_FINAL += --wrap=__moddi3 --wrap=__umoddi3 @@ -31,7 +45,9 @@ LDFLAGS_EFI_PAYLOAD := -Bsymbolic -Bsymbolic-functions -shared --no-undefined OBJCOPYFLAGS_EFI := -j .text -j .sdata -j .data -j .dynamic -j .dynsym \ -j .rel -j .rela -j .reloc

+ifeq ($(IS_32BIT),y) CFLAGS_NON_EFI := -mregparm=3 +endif CFLAGS_EFI := -fpic -fshort-wchar

ifeq ($(CONFIG_EFI_STUB_64BIT),) @@ -62,8 +78,18 @@ else

PLATFORM_CPPFLAGS += $(CFLAGS_NON_EFI) PLATFORM_LDFLAGS += --emit-relocs -LDFLAGS_FINAL += --gc-sections -pie +LDFLAGS_FINAL += --gc-sections $(if $(CONFIG_SPL_BUILD),,-pie) + +endif

+ifdef CONFIG_X86_64 +ifndef CONFIG_SPL_BUILD +PLATFORM_CPPFLAGS += -D__x86_64__ +else +PLATFORM_CPPFLAGS += -D__I386__ +endif +else +PLATFORM_CPPFLAGS += -D__I386__ endif

ifneq ($(CONFIG_EFI_STUB)$(CONFIG_CMD_BOOTEFI_HELLO_COMPILE),) diff --git a/arch/x86/cpu/config.mk b/arch/x86/cpu/config.mk index 4c99a35621d..b519f433acf 100644 --- a/arch/x86/cpu/config.mk +++ b/arch/x86/cpu/config.mk @@ -7,8 +7,6 @@

CROSS_COMPILE ?= i386-linux-

-PLATFORM_CPPFLAGS += -D__I386__ - # DO NOT MODIFY THE FOLLOWING UNLESS YOU REALLY KNOW WHAT YOU ARE DOING! LDPPFLAGS += -DRESET_SEG_START=$(CONFIG_RESET_SEG_START) LDPPFLAGS += -DRESET_SEG_SIZE=$(CONFIG_RESET_SEG_SIZE)

Add a new link config which uses 64-bit U-Boot. This is not fully functional but is it a start. Missing features:

- SDRAM sizing - Booting linux - EFI support - SCSI device init (and others)

Signed-off-by: Simon Glass sjg@chromium.org ---

Changes in v3: - Drop patch 'x86: Add basic support for U-Boot as a 64-bit EFI application' - Drop patch 'Mention the MRC region in the README' - Drop patch 'x86: link: Add build options for SPL' - Drop unnecessary defconfig options for chromebook_link64 - Avoid including helloworld.efi in the 64-bit U-Boot

Changes in v2: - Drop patch 'video: Use ulong for video frame buffer address' - Add a new 64-bit link config instead of changing the existing one

board/google/Kconfig | 7 +++ board/google/chromebook_link/Kconfig | 2 +- board/google/chromebook_link/MAINTAINERS | 7 +++ configs/chromebook_link64_defconfig | 89 ++++++++++++++++++++++++++++++++ 4 files changed, 104 insertions(+), 1 deletion(-) create mode 100644 configs/chromebook_link64_defconfig

diff --git a/board/google/Kconfig b/board/google/Kconfig index 7ba73a2461d..e56c026ef6d 100644 --- a/board/google/Kconfig +++ b/board/google/Kconfig @@ -22,6 +22,13 @@ config TARGET_CHROMEBOOK_LINK and it provides a 2560x1700 high resolution touch-enabled LCD display.

+config TARGET_CHROMEBOOK_LINK64 + bool "Chromebook link 64-bit" + help + This is the Chromebook Pixel released in 2013. With this config + U-Boot is built as a 64-bit binary. This allows testing while this + feature is being completed. + config TARGET_CHROMEBOX_PANTHER bool "Chromebox panther (not available)" select n diff --git a/board/google/chromebook_link/Kconfig b/board/google/chromebook_link/Kconfig index 5c57945d77a..8999b582943 100644 --- a/board/google/chromebook_link/Kconfig +++ b/board/google/chromebook_link/Kconfig @@ -1,4 +1,4 @@ -if TARGET_CHROMEBOOK_LINK +if TARGET_CHROMEBOOK_LINK || TARGET_CHROMEBOOK_LINK64

config SYS_BOARD default "chromebook_link" diff --git a/board/google/chromebook_link/MAINTAINERS b/board/google/chromebook_link/MAINTAINERS index bc253a2ba7b..e7aef53390c 100644 --- a/board/google/chromebook_link/MAINTAINERS +++ b/board/google/chromebook_link/MAINTAINERS @@ -4,3 +4,10 @@ S: Maintained F: board/google/chromebook_link/ F: include/configs/chromebook_link.h F: configs/chromebook_link_defconfig + +CHROMEBOOK LINK 64-bit BOARD +M: Simon Glass sjg@chromium.org +S: Maintained +F: board/google/chromebook_link/ +F: include/configs/chromebook_link.h +F: configs/chromebook_link64_defconfig diff --git a/configs/chromebook_link64_defconfig b/configs/chromebook_link64_defconfig new file mode 100644 index 00000000000..dd8175ec767 --- /dev/null +++ b/configs/chromebook_link64_defconfig @@ -0,0 +1,89 @@ +CONFIG_X86=y +CONFIG_SPL_GPIO_SUPPORT=y +CONFIG_SPL_LIBCOMMON_SUPPORT=y +CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_SYS_MALLOC_F_LEN=0x2000 +CONFIG_SPL_I2C_SUPPORT=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL_SPI_FLASH_SUPPORT=y +CONFIG_SPL_SPI_SUPPORT=y +CONFIG_X86_RUN_64BIT=y +CONFIG_VENDOR_GOOGLE=y +CONFIG_DEFAULT_DEVICE_TREE="chromebook_link" +CONFIG_TARGET_CHROMEBOOK_LINK=y +CONFIG_ENABLE_MRC_CACHE=y +CONFIG_HAVE_MRC=y +CONFIG_SMP=y +CONFIG_HAVE_VGA_BIOS=y +CONFIG_FIT=y +CONFIG_SPL_LOAD_FIT=y +CONFIG_BOOTSTAGE=y +CONFIG_BOOTSTAGE_REPORT=y +CONFIG_SYS_CONSOLE_INFO_QUIET=y +CONFIG_SPL_SYS_MALLOC_SIMPLE=y +CONFIG_SPL_CPU_SUPPORT=y +CONFIG_SPL_NET_SUPPORT=y +CONFIG_SPL_PCI_SUPPORT=y +CONFIG_SPL_PCH_SUPPORT=y +CONFIG_SPL_RTC_SUPPORT=y +CONFIG_SPL_TIMER_SUPPORT=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_CPU=y +# CONFIG_CMD_IMLS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_SF=y +CONFIG_CMD_SPI=y +CONFIG_CMD_USB=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +# CONFIG_CMD_NFS is not set +CONFIG_CMD_PING=y +CONFIG_CMD_TIME=y +CONFIG_CMD_BOOTSTAGE=y +CONFIG_CMD_TPM=y +CONFIG_CMD_TPM_TEST=y +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_OF_CONTROL=y +CONFIG_SPL_OF_CONTROL=y +CONFIG_SPL_DM=y +CONFIG_REGMAP=y +CONFIG_SPL_REGMAP=y +CONFIG_SYSCON=y +CONFIG_SPL_SYSCON=y +CONFIG_CPU=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_INTEL=y +CONFIG_CROS_EC=y +CONFIG_CROS_EC_LPC=y +CONFIG_SPI_FLASH=y +CONFIG_SPI_FLASH_GIGADEVICE=y +CONFIG_SPI_FLASH_MACRONIX=y +CONFIG_SPI_FLASH_WINBOND=y +CONFIG_DM_PCI=y +CONFIG_DM_RTC=y +CONFIG_DEBUG_UART=y +CONFIG_DEBUG_UART_BASE=0x3f8 +CONFIG_DEBUG_UART_CLOCK=1843200 +CONFIG_DEBUG_UART_BOARD_INIT=y +CONFIG_SYS_NS16550=y +CONFIG_ICH_SPI=y +CONFIG_TIMER=y +CONFIG_TPM_TIS_LPC=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DM_VIDEO=y +CONFIG_USB_KEYBOARD=y +CONFIG_VIDEO_VESA=y +CONFIG_FRAMEBUFFER_SET_VESA_MODE=y +CONFIG_FRAMEBUFFER_VESA_MODE_11A=y +CONFIG_VIDEO_IVYBRIDGE_IGD=y +CONFIG_CONSOLE_SCROLL_LINES=5 +CONFIG_USE_PRIVATE_LIBGCC=y +CONFIG_TPM=y +# CONFIG_CMD_BOOTEFI_HELLO_COMPILE is not set