[U-Boot] [PATCH 1/2 v3] powerpc/85xx: Add C29x SoC support
From: Mingkai Hu Mingkai.Hu@freescale.com
The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features:
- 512K L2 Cache/SRAM and 512 KB platform SRAM - DDR3/DDR3L 32bit DDR controller - One PCI express (x1, x2, x4) Gen 2.0 Controller - Trust Architecture 2.0 - SEC6.0 engine
Signed-off-by: Mingkai Hu Mingkai.Hu@freescale.com Signed-off-by: Po Liu Po.Liu@freescale.com --- Changes for v2: - Remove define CONFIG_C291/CONFIG_C292/CONFIG_C293, replace with CONFIG_C29X Changes for v3: - Replace CONFIG_C29X with CONFIG_PPC_C29X arch/powerpc/cpu/mpc85xx/Makefile | 2 + arch/powerpc/cpu/mpc85xx/c29x_serdes.c | 65 +++++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc8xxx/cpu.c | 3 ++ arch/powerpc/include/asm/config_mpc85xx.h | 12 ++++++ arch/powerpc/include/asm/fsl_law.h | 1 + arch/powerpc/include/asm/immap_85xx.h | 23 +++++++++++ arch/powerpc/include/asm/processor.h | 3 ++ 7 files changed, 109 insertions(+) create mode 100644 arch/powerpc/cpu/mpc85xx/c29x_serdes.c
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 4669883..3cb2a78 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -62,6 +62,7 @@ COBJS-$(CONFIG_MPC8568) += ddr-gen2.o COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
# supports ddr1/2/3 +COBJS-$(CONFIG_PPC_C29X) += ddr-gen3.o COBJS-$(CONFIG_MPC8572) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += ddr-gen3.o COBJS-$(CONFIG_MPC8569) += ddr-gen3.o @@ -116,6 +117,7 @@ COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
# SoC specific SERDES support +COBJS-$(CONFIG_PPC_C29X) += c29x_serdes.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o COBJS-$(CONFIG_MPC8544) += mpc8544_serdes.o COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c new file mode 100644 index 0000000..4b3214d --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c @@ -0,0 +1,65 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 + +static u32 serdes1_prtcl_map; + +struct serdes_config { + u32 protocol; + u8 lanes[SRDS1_MAX_LANES]; +}; + +static const struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {1, {PCIE1, PCIE1, PCIE1, PCIE1} }, + {2, {PCIE1, PCIE1, PCIE1, PCIE1} }, + {3, {PCIE1, PCIE1, NONE, NONE} }, + {4, {PCIE1, PCIE1, NONE, NONE} }, + {5, {PCIE1, NONE, NONE, NONE} }, + {6, {PCIE1, NONE, NONE, NONE} }, + {} +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + return (1 << device) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + const struct serdes_config *ptr; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + ptr = &serdes1_cfg_tbl[srds_cfg]; + if (!ptr->protocol) + return; + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = ptr->lanes[lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index bc26855..2eed872 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -95,6 +95,9 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(BSC9131, 9131, 1), CPU_TYPE_ENTRY(BSC9132, 9132, 2), CPU_TYPE_ENTRY(BSC9232, 9232, 2), + CPU_TYPE_ENTRY(C291, C291, 1), + CPU_TYPE_ENTRY(C292, C292, 1), + CPU_TYPE_ENTRY(C293, C293, 1), #elif defined(CONFIG_MPC86xx) CPU_TYPE_ENTRY(8610, 8610, 1), CPU_TYPE_ENTRY(8641, 8641, 2), diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 1d46b14..3f48802 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -626,6 +626,18 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+#elif defined(CONFIG_PPC_C29X) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_FSL_SDHC_V2_3 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 +#define CONFIG_TSECV2_1 +#define CONFIG_SYS_FSL_SEC_COMPAT 6 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 + #else #error Processor type not defined for this platform #endif diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index bea1636..9eb3e13 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -92,6 +92,7 @@ enum law_trgt_if { LAW_TRGT_IF_LBC = 0x04, LAW_TRGT_IF_CCSR = 0x08, LAW_TRGT_IF_DSP_CCSR = 0x09, + LAW_TRGT_IF_PLATFORM_SRAM = 0x0a, LAW_TRGT_IF_DDR_INTRLV = 0x0b, LAW_TRGT_IF_RIO = 0x0c, LAW_TRGT_IF_RIO_2 = 0x0d, diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index db70d04..af3853a 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2147,6 +2147,11 @@ typedef struct ccsr_gur { #ifdef CONFIG_MPC8536 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 +#elif defined(CONFIG_PPC_C29X) +#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 +#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \ + & MPC85xx_PORDEVSR2_DDR_SPD_0) \ + >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT)) #else #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132) #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 @@ -2194,6 +2199,9 @@ typedef struct ccsr_gur { #elif defined(CONFIG_BSC9132) #define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17 +#elif defined(CONFIG_PPC_C29X) +#define MPC85xx_PORDEVSR_IO_SEL 0x00e00000 +#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 #else #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 @@ -2209,6 +2217,10 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 u32 pordbgmsr; /* POR debug mode status */ u32 pordevsr2; /* POR I/O device status 2 */ +#if defined(CONFIG_PPC_C29X) +#define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008 +#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3 +#endif /* The 8544 RM says this is bit 26, but it's really bit 24 */ #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 u8 res1[8]; @@ -2355,6 +2367,11 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000 #define MPC85xx_PMUXCR0_SIM_SEL 0x00014000 #endif +#if defined(CONFIG_PPC_C29X) +#define MPC85xx_PMUXCR_SPI_MASK 0x00000300 +#define MPC85xx_PMUXCR_SPI 0x00000000 +#define MPC85xx_PMUXCR_SPI_GPIO 0x00000100 +#endif u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ #if defined(CONFIG_P1010) || defined(CONFIG_P1014) #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000 @@ -3024,12 +3041,18 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000 #ifdef CONFIG_TSECV2 #define CONFIG_SYS_TSEC1_OFFSET 0xB0000 +#elif defined(CONFIG_TSECV2_1) +#define CONFIG_SYS_TSEC1_OFFSET 0x10000 #else #define CONFIG_SYS_TSEC1_OFFSET 0x24000 #endif #define CONFIG_SYS_MDIO1_OFFSET 0x24000 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 +#if defined(CONFIG_PPC_C29X) +#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000 +#else #define CONFIG_SYS_FSL_SEC_OFFSET 0x30000 +#endif #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 #define CONFIG_SYS_SNVS_OFFSET 0xE6000 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 56b22d8..64a6f9c 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1119,6 +1119,9 @@ #define SVR_T4240 0x824000 #define SVR_T4120 0x824001 #define SVR_T4160 0x824100 +#define SVR_C291 0x850000 +#define SVR_C292 0x850020 +#define SVR_C293 0x850030 #define SVR_B4860 0X868000 #define SVR_G4860 0x868001 #define SVR_G4060 0x868003
From: Mingkai Hu Mingkai.Hu@freescale.com
C29XPCIE board is a series of Freescale PCIe add-in cards to perform as public key crypto accelerator or secure key management module. It includes C293PCIE board, C293PCIE board and C291PCIE board.
- 512KB platform SRAM in addition to 512K L2 Cache/SRAM - 512MB soldered DDR3 32bit memory - CPLD System Logic - 64MB x16 NOR flash and 4GB x8 NAND flash - 16MB SPI flash
Signed-off-by: Mingkai Hu Mingkai.Hu@freescale.com Singed-off-by: Po Liu Po.Liu@freescale.com --- Changes for v2: - Remove define CONFIG_C291/CONFIG_C292/CONFIG_C293, replace with CONFIG_C29X - Adjust the TLB config mode - Add SEC node removal method by check the CPU SVR - Clean up the C29XPCIE.h file Changes for v3: - Replace CONFIG_C29X with CONFIG_PPC_C29X board/freescale/c29xpcie/Makefile | 34 +++ board/freescale/c29xpcie/c29xpcie.c | 150 +++++++++++ board/freescale/c29xpcie/cpld.c | 155 ++++++++++++ board/freescale/c29xpcie/cpld.h | 53 ++++ board/freescale/c29xpcie/ddr.c | 89 +++++++ board/freescale/c29xpcie/law.c | 22 ++ board/freescale/c29xpcie/tlb.c | 89 +++++++ boards.cfg | 2 + include/configs/C29XPCIE.h | 490 ++++++++++++++++++++++++++++++++++++ 9 files changed, 1084 insertions(+) create mode 100644 board/freescale/c29xpcie/Makefile create mode 100644 board/freescale/c29xpcie/c29xpcie.c create mode 100644 board/freescale/c29xpcie/cpld.c create mode 100644 board/freescale/c29xpcie/cpld.h create mode 100644 board/freescale/c29xpcie/ddr.c create mode 100644 board/freescale/c29xpcie/law.c create mode 100644 board/freescale/c29xpcie/tlb.c create mode 100644 include/configs/C29XPCIE.h
diff --git a/board/freescale/c29xpcie/Makefile b/board/freescale/c29xpcie/Makefile new file mode 100644 index 0000000..15bef9a --- /dev/null +++ b/board/freescale/c29xpcie/Makefile @@ -0,0 +1,34 @@ +# +# Copyright 2013 Freescale Semiconductor, Inc. +# +# This program is free software; you can redistribute it and/or modify it +# under the terms of the GNU General Public License as published by the Free +# Software Foundation; either version 2 of the License, or (at your option) +# any later version. +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).o + +COBJS-y += $(BOARD).o +COBJS-y += cpld.o +COBJS-y += ddr.o +COBJS-y += law.o +COBJS-y += tlb.o + +SRCS := $(SOBJS:.o=.S) $(COBJS-y:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS-y)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(call cmd_link_o_target, $(OBJS)) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/freescale/c29xpcie/c29xpcie.c b/board/freescale/c29xpcie/c29xpcie.c new file mode 100644 index 0000000..21f3892 --- /dev/null +++ b/board/freescale/c29xpcie/c29xpcie.c @@ -0,0 +1,150 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <common.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <asm/cache.h> +#include <asm/immap_85xx.h> +#include <asm/io.h> +#include <miiphy.h> +#include <libfdt.h> +#include <fdt_support.h> +#include <fsl_mdio.h> +#include <tsec.h> +#include <mmc.h> +#include <netdev.h> +#include <pci.h> +#include <asm/fsl_ifc.h> +#include <asm/fsl_pci.h> + +#include "cpld.h" + +DECLARE_GLOBAL_DATA_PTR; + +int checkboard(void) +{ + struct cpu_type *cpu = gd->arch.cpu; + + printf("Board: %sPCIe, ", cpu->name); + printf("CPLD Ver: 0x%02x\n", CPLD_READ(cpldver)); + + return 0; +} + +int board_early_init_f(void) +{ + struct fsl_ifc *ifc = (void *)CONFIG_SYS_IFC_ADDR; + + /* Clock configuration to access CPLD using IFC(GPCM) */ + setbits_be32(&ifc->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); + + return 0; +} + +int board_early_init_r(void) +{ + const unsigned long flashbase = CONFIG_SYS_FLASH_BASE; + const u8 flash_esel = find_tlb_idx((void *)flashbase, 1); + + /* + * Remap Boot flash region to caching-inhibited + * so that flash can be erased properly. + */ + + /* Flush d-cache and invalidate i-cache of any FLASH data */ + flush_dcache(); + invalidate_icache(); + + /* invalidate existing TLB entry for flash */ + disable_tlb(flash_esel); + + set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, flash_esel, BOOKE_PAGESZ_64M, 1); + + return 0; +} + +#ifdef CONFIG_PCI +void pci_init_board(void) +{ + fsl_pcie_init_board(0); +} +#endif /* ifdef CONFIG_PCI */ + +#ifdef CONFIG_TSEC_ENET +int board_eth_init(bd_t *bis) +{ + struct fsl_pq_mdio_info mdio_info; + struct tsec_info_struct tsec_info[2]; + int num = 0; + +#ifdef CONFIG_TSEC1 + SET_STD_TSEC_INFO(tsec_info[num], 1); + num++; +#endif +#ifdef CONFIG_TSEC2 + SET_STD_TSEC_INFO(tsec_info[num], 2); + num++; +#endif + if (!num) { + printf("No TSECs initialized\n"); + return 0; + } + + /* Register 1G MDIO bus */ + mdio_info.regs = (struct tsec_mii_mng *)CONFIG_SYS_MDIO_BASE_ADDR; + mdio_info.name = DEFAULT_MII_NAME; + + fsl_pq_mdio_init(bis, &mdio_info); + + tsec_eth_init(bis, tsec_info, num); + + return pci_eth_init(bis); +} +#endif + +#if defined(CONFIG_OF_BOARD_SETUP) +void fdt_del_sec(void *blob, int offset) +{ + int nodeoff = 0; + + while ((nodeoff = fdt_node_offset_by_compat_reg(blob, "fsl,sec-v6.0", + CONFIG_SYS_CCSRBAR_PHYS + CONFIG_SYS_FSL_SEC_OFFSET + + offset * 0x20000)) >= 0) { + fdt_del_node(blob, nodeoff); + offset++; + } +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + phys_addr_t base; + phys_size_t size; + struct cpu_type *cpu; + + cpu = gd->arch.cpu; + + ft_cpu_setup(blob, bd); + + base = getenv_bootm_low(); + size = getenv_bootm_size(); + +#if defined(CONFIG_PCI) + FT_FSL_PCI_SETUP; +#endif + + fdt_fixup_memory(blob, (u64)base, (u64)size); + if (cpu->soc_ver == SVR_C291) + fdt_del_sec(blob, 1); + else if (cpu->soc_ver == SVR_C292) + fdt_del_sec(blob, 2); +} +#endif diff --git a/board/freescale/c29xpcie/cpld.c b/board/freescale/c29xpcie/cpld.c new file mode 100644 index 0000000..54a8820 --- /dev/null +++ b/board/freescale/c29xpcie/cpld.c @@ -0,0 +1,155 @@ +/** + * Copyright 2013 Freescale Semiconductor + * Author: Mingkai Hu Mingkai.hu@freescale.com + * Po Liu Po.Liu@freescale.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This file provides support for the board-specific CPLD used on some Freescale + * reference boards. + * + * The following macros need to be defined: + * + * CONFIG_SYS_CPLD_BASE - The virtual address of the base of the + * CPLD register map + * + */ + +#include <common.h> +#include <command.h> +#include <asm/io.h> + +#include "cpld.h" + +static u8 __cpld_read(unsigned int reg) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + return in_8(p + reg); +} + +u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read"))); + +static void __cpld_write(unsigned int reg, u8 value) +{ + void *p = (void *)CONFIG_SYS_CPLD_BASE; + + out_8(p + reg, value); +} + +void cpld_write(unsigned int reg, u8 value) + __attribute__((weak, alias("__cpld_write"))); + +/** + * Set the boot bank to the alternate bank + */ +void __cpld_set_altbank(u8 banksel) +{ + u8 reg11 = CPLD_READ(flhcsr); + + switch (banksel) { + case 1: + CPLD_WRITE(flhcsr, (reg11 & CPLD_BANKSEL_MASK) + | CPLD_BANKSEL_EN | CPLD_SELECT_BANK1); + break; + case 2: + CPLD_WRITE(flhcsr, (reg11 & CPLD_BANKSEL_MASK) + | CPLD_BANKSEL_EN | CPLD_SELECT_BANK2); + break; + case 3: + CPLD_WRITE(flhcsr, (reg11 & CPLD_BANKSEL_MASK) + | CPLD_BANKSEL_EN | CPLD_SELECT_BANK3); + break; + case 4: + CPLD_WRITE(flhcsr, (reg11 & CPLD_BANKSEL_MASK) + | CPLD_BANKSEL_EN | CPLD_SELECT_BANK4); + break; + default: + printf("Invalid value! [1-4]\n"); + return; + } + + udelay(100); + do_reset(NULL, 0, 0, NULL); +} + +void cpld_set_altbank(u8 banksel) + __attribute__((weak, alias("__cpld_set_altbank"))); + +/** + * Set the boot bank to the default bank + */ +void __cpld_set_defbank(void) +{ + __cpld_set_altbank(4); +} + +void cpld_set_defbank(void) + __attribute__((weak, alias("__cpld_set_defbank"))); + +#ifdef DEBUG +static void cpld_dump_regs(void) +{ + printf("chipid1 = 0x%02x\n", CPLD_READ(chipid1)); + printf("chipid2 = 0x%02x\n", CPLD_READ(chipid2)); + printf("hwver = 0x%02x\n", CPLD_READ(hwver)); + printf("cpldver = 0x%02x\n", CPLD_READ(cpldver)); + printf("rstcon = 0x%02x\n", CPLD_READ(rstcon)); + printf("flhcsr = 0x%02x\n", CPLD_READ(flhcsr)); + printf("wdcsr = 0x%02x\n", CPLD_READ(wdcsr)); + printf("wdkick = 0x%02x\n", CPLD_READ(wdkick)); + printf("fancsr = 0x%02x\n", CPLD_READ(fancsr)); + printf("ledcsr = 0x%02x\n", CPLD_READ(ledcsr)); + printf("misc = 0x%02x\n", CPLD_READ(misccsr)); + printf("bootor = 0x%02x\n", CPLD_READ(bootor)); + printf("bootcfg1 = 0x%02x\n", CPLD_READ(bootcfg1)); + printf("bootcfg2 = 0x%02x\n", CPLD_READ(bootcfg2)); + printf("bootcfg3 = 0x%02x\n", CPLD_READ(bootcfg3)); + printf("bootcfg4 = 0x%02x\n", CPLD_READ(bootcfg4)); + putc('\n'); +} +#endif + +int cpld_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) +{ + int rc = 0; + unsigned char value; + + if (argc <= 1) + return cmd_usage(cmdtp); + + if (strcmp(argv[1], "reset") == 0) { + if (!strcmp(argv[2], "altbank") && argv[3]) { + value = (u8)simple_strtoul(argv[3], NULL, 16); + cpld_set_altbank(value); + } else if (!argv[2]) + cpld_set_defbank(); + else + cmd_usage(cmdtp); +#ifdef DEBUG + } else if (strcmp(argv[1], "dump") == 0) { + cpld_dump_regs(); +#endif + } else + rc = cmd_usage(cmdtp); + + return rc; +} + +U_BOOT_CMD( + cpld_cmd, CONFIG_SYS_MAXARGS, 1, cpld_cmd, + "Reset the board using the CPLD sequencer", + "reset - hard reset to default bank 4\n" + "cpld_cmd reset altbank [bank]- reset to alternate bank\n" + " - [bank] bank value select 1-4\n" + " - bank 1 on the flash 0x0000000~0x0ffffff\n" + " - bank 2 on the flash 0x1000000~0x1ffffff\n" + " - bank 3 on the flash 0x2000000~0x2ffffff\n" + " - bank 4 on the flash 0x3000000~0x3ffffff\n" +#ifdef DEBUG + "cpld_cmd dump - display the CPLD registers\n" +#endif + ); diff --git a/board/freescale/c29xpcie/cpld.h b/board/freescale/c29xpcie/cpld.h new file mode 100644 index 0000000..15d33cd --- /dev/null +++ b/board/freescale/c29xpcie/cpld.h @@ -0,0 +1,53 @@ +/** + * Copyright 2013 Freescale Semiconductor + * Author: Mingkai Hu Mingkai.Hu@freescale.com + * Po Liu Po.Liu@freescale.com + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + * + * This file provides support for the ngPIXIS, a board-specific FPGA used on + * some Freescale reference boards. + */ + +/* + * CPLD register set. Feel free to add board-specific #ifdefs where necessary. + */ +struct cpld_data { + u8 chipid1; /* 0x0 - CPLD Chip ID1 Register */ + u8 chipid2; /* 0x1 - CPLD Chip ID2 Register */ + u8 hwver; /* 0x2 - Hardware Version Register */ + u8 cpldver; /* 0x3 - Software Version Register */ + u8 res[12]; + u8 rstcon; /* 0x10 - Reset control register */ + u8 flhcsr; /* 0x11 - Flash control and status Register */ + u8 wdcsr; /* 0x12 - Watchdog control and status Register */ + u8 wdkick; /* 0x13 - Watchdog kick Register */ + u8 fancsr; /* 0x14 - Fan control and status Register */ + u8 ledcsr; /* 0x15 - LED control and status Register */ + u8 misccsr; /* 0x16 - Misc control and status Register */ + u8 bootor; /* 0x17 - Boot configure override Register */ + u8 bootcfg1; /* 0x18 - Boot configure 1 Register */ + u8 bootcfg2; /* 0x19 - Boot configure 2 Register */ + u8 bootcfg3; /* 0x1a - Boot configure 3 Register */ + u8 bootcfg4; /* 0x1b - Boot configure 4 Register */ +}; + +/* Pointer to the CPLD register set */ +#define cpld ((struct cpld_data *)CONFIG_SYS_CPLD_BASE) + +u8 cpld_read(unsigned int reg); +void cpld_write(unsigned int reg, u8 value); + +#define CPLD_BANKSEL_EN 0x02 +#define CPLD_BANKSEL_MASK 0x3f +#define CPLD_SELECT_BANK1 0xc0 +#define CPLD_SELECT_BANK2 0x80 +#define CPLD_SELECT_BANK3 0x40 +#define CPLD_SELECT_BANK4 0x00 + +#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value) cpld_write(offsetof(struct cpld_data, reg), \ + value) diff --git a/board/freescale/c29xpcie/ddr.c b/board/freescale/c29xpcie/ddr.c new file mode 100644 index 0000000..62476ca --- /dev/null +++ b/board/freescale/c29xpcie/ddr.c @@ -0,0 +1,89 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/fsl_ddr_sdram.h> +#include <asm/fsl_ddr_dimm_params.h> + +/* + * Micron MT41J128M16HA-15E + * */ +dimm_params_t ddr_raw_timing = { + .n_ranks = 1, + .rank_density = 536870912u, + .capacity = 536870912u, + .primary_sdram_width = 32, + .ec_sdram_width = 8, + .registered_dimm = 0, + .mirrored_dimm = 0, + .n_row_addr = 14, + .n_col_addr = 10, + .n_banks_per_sdram_device = 8, + .edc_config = 2, + .burst_lengths_bitmask = 0x0c, + + .tCKmin_X_ps = 1650, + .caslat_X = 0x7e << 4, /* 5,6,7,8,9,10 */ + .tAA_ps = 14050, + .tWR_ps = 15000, + .tRCD_ps = 13500, + .tRRD_ps = 75000, + .tRP_ps = 13500, + .tRAS_ps = 40000, + .tRC_ps = 49500, + .tRFC_ps = 160000, + .tWTR_ps = 75000, + .tRTP_ps = 75000, + .refresh_rate_ps = 7800000, + .tFAW_ps = 30000, +}; + +int fsl_ddr_get_dimm_params(dimm_params_t *pdimm, + unsigned int controller_number, + unsigned int dimm_number) +{ + const char dimm_model[] = "Fixed DDR on board"; + + if ((controller_number == 0) && (dimm_number == 0)) { + memcpy(pdimm, &ddr_raw_timing, sizeof(dimm_params_t)); + memset(pdimm->mpart, 0, sizeof(pdimm->mpart)); + memcpy(pdimm->mpart, dimm_model, sizeof(dimm_model) - 1); + } + + return 0; +} + +void fsl_ddr_board_options(memctl_options_t *popts, + dimm_params_t *pdimm, + unsigned int ctrl_num) +{ + int i; + popts->clk_adjust = 2; + popts->cpo_override = 0x1f; + popts->write_data_delay = 4; + popts->half_strength_driver_enable = 1; + popts->bstopre = 0x3cf; + popts->quad_rank_present = 1; + popts->rtt_override = 1; + popts->rtt_override_value = 1; + popts->dynamic_power = 1; + /* Write leveling override */ + popts->wrlvl_en = 1; + popts->wrlvl_override = 1; + popts->wrlvl_sample = 0xf; + popts->wrlvl_start = 0x4; + popts->trwt_override = 1; + popts->trwt = 0; + + for (i = 0; i < CONFIG_CHIP_SELECTS_PER_CTRL; i++) { + popts->cs_local_opts[i].odt_rd_cfg = FSL_DDR_ODT_NEVER; + popts->cs_local_opts[i].odt_wr_cfg = FSL_DDR_ODT_CS; + } +} diff --git a/board/freescale/c29xpcie/law.c b/board/freescale/c29xpcie/law.c new file mode 100644 index 0000000..064fa71 --- /dev/null +++ b/board/freescale/c29xpcie/law.c @@ -0,0 +1,22 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <common.h> +#include <asm/fsl_law.h> +#include <asm/mmu.h> + +struct law_entry law_table[] = { + SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_IFC), + SET_LAW(CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, LAW_SIZE_512K, + LAW_TRGT_IF_PLATFORM_SRAM), +}; + +int num_law_entries = ARRAY_SIZE(law_table); diff --git a/board/freescale/c29xpcie/tlb.c b/board/freescale/c29xpcie/tlb.c new file mode 100644 index 0000000..575cdbe --- /dev/null +++ b/board/freescale/c29xpcie/tlb.c @@ -0,0 +1,89 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <common.h> +#include <asm/mmu.h> + +struct fsl_e_tlb_entry tlb_table[] = { + /* TLB 0 - for temp stack in cache */ + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR, CONFIG_SYS_INIT_RAM_ADDR, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 4 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 8 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + SET_TLB_ENTRY(0, CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024 , + CONFIG_SYS_INIT_RAM_ADDR + 12 * 1024, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 0, BOOKE_PAGESZ_4K, 0), + + /* TLB 1 */ + /* *I*** - Covers boot page */ + SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 0, BOOKE_PAGESZ_4K, 1), + + /* *I*G* - CCSRBAR */ + SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 1, BOOKE_PAGESZ_1M, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS, + MAS3_SX|MAS3_SR, MAS2_W|MAS2_G, + 0, 2, BOOKE_PAGESZ_64M, 1), + +#ifdef CONFIG_PCI + /* *I*G* - PCI */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_MEM_VIRT, CONFIG_SYS_PCIE1_MEM_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 3, BOOKE_PAGESZ_256M, 1), + + /* *I*G* - PCI I/O */ + SET_TLB_ENTRY(1, CONFIG_SYS_PCIE1_IO_VIRT, CONFIG_SYS_PCIE1_IO_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 4, BOOKE_PAGESZ_256K, 1), +#endif + + /* *I*G - Board CPLD */ + SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 5, BOOKE_PAGESZ_4K, 1), + + SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS, + MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 6, BOOKE_PAGESZ_1M, 1), + + /* *I*G - platform SRAM */ + SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE, + CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 7, BOOKE_PAGESZ_256K, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE + 0x40000, + CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS + 0x40000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 8, BOOKE_PAGESZ_256K, 1), + +#ifdef CONFIG_SYS_RAMBOOT + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, + CONFIG_SYS_DDR_SDRAM_BASE, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 9, BOOKE_PAGESZ_256M, 1), + SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, + CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 10, BOOKE_PAGESZ_256M, 1), +#endif +}; + +int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/boards.cfg b/boards.cfg index c0c4282..4c68e9f 100644 --- a/boards.cfg +++ b/boards.cfg @@ -771,6 +771,8 @@ MPC8569MDS_NAND powerpc mpc85xx mpc8569mds freesca MPC8572DS powerpc mpc85xx mpc8572ds freescale - MPC8572DS MPC8572DS_36BIT powerpc mpc85xx mpc8572ds freescale - MPC8572DS:36BIT MPC8572DS_NAND powerpc mpc85xx mpc8572ds freescale - MPC8572DS:NAND +C29XPCIE powerpc mpc85xx c29xpcie freescale - C29XPCIE:C29XPCIE,36BIT +C29XPCIE_SPIFLASH powerpc mpc85xx c29xpcie freescale - C29XPCIE:C29XPCIE,36BIT,SPIFLASH P1010RDB_36BIT_NAND powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,NAND P1010RDB_36BIT_NAND_SECBOOT powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT,NAND_SECBOOT,SECURE_BOOT P1010RDB_36BIT_NOR powerpc mpc85xx p1010rdb freescale - P1010RDB:P1010RDB,36BIT diff --git a/include/configs/C29XPCIE.h b/include/configs/C29XPCIE.h new file mode 100644 index 0000000..891ea34 --- /dev/null +++ b/include/configs/C29XPCIE.h @@ -0,0 +1,490 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * C29XPCIE board configuration file + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_PHYS_64BIT + +#ifdef CONFIG_C29XPCIE +#define CONFIG_PPC_C29X +#endif + +#ifdef CONFIG_SPIFLASH +#define CONFIG_RAMBOOT_SPIFLASH +#define CONFIG_SYS_TEXT_BASE 0x11000000 +#define CONFIG_RESET_VECTOR_ADDRESS 0x1107fffc +#endif + +#ifndef CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_TEXT_BASE 0xeff80000 +#endif + +#ifndef CONFIG_RESET_VECTOR_ADDRESS +#define CONFIG_RESET_VECTOR_ADDRESS 0xeffffffc +#endif + +#ifndef CONFIG_SYS_MONITOR_BASE +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE +#endif + +/* High Level Configuration Options */ +#define CONFIG_BOOKE /* BOOKE */ +#define CONFIG_E500 /* BOOKE e500 family */ +#define CONFIG_MPC85xx +#define CONFIG_FSL_IFC /* Enable IFC Support */ +#define CONFIG_SYS_HAS_SERDES /* common SERDES init code */ + +#define CONFIG_PCI /* Enable PCI/PCIE */ +#ifdef CONFIG_PCI +#define CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_FSL_PCIE_RESET /* need PCIe reset errata */ +#define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ + +#define CONFIG_CMD_NET +#define CONFIG_CMD_PCI + +#define CONFIG_E1000 + +/* + * PCI Windows + * Memory space is mapped 1-1, but I/O space must start from 0. + */ +/* controller 1, Slot 1, tgtid 1, Base address a000 */ +#define CONFIG_SYS_PCIE1_NAME "Slot 1" +#define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull + +#define CONFIG_PCI_PNP /* do pci plug-and-play */ + +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CONFIG_DOS_PARTITION +#endif + +#define CONFIG_FSL_LAW /* Use common FSL init code */ +#define CONFIG_TSEC_ENET +#define CONFIG_ENV_OVERWRITE + +#define CONFIG_DDR_CLK_FREQ 100000000 +#define CONFIG_SYS_CLK_FREQ 66666666 + +#define CONFIG_HWCONFIG + +/* + * These can be toggled for performance analysis, otherwise use default. + */ +#define CONFIG_L2_CACHE /* toggle L2 cache */ +#define CONFIG_BTB /* toggle branch predition */ + +#define CONFIG_ADDR_STREAMING /* toggle addr streaming */ + +#define CONFIG_ENABLE_36BIT_PHYS + +#define CONFIG_ADDR_MAP 1 +#define CONFIG_SYS_NUM_ADDR_MAP 16 /* number of TLB1 entries */ + +#define CONFIG_SYS_MEMTEST_START 0x00200000 +#define CONFIG_SYS_MEMTEST_END 0x00400000 +#define CONFIG_PANIC_HANG + +/* DDR Setup */ +#define CONFIG_FSL_DDR3 +#define CONFIG_DDR_SPD +#define CONFIG_SYS_SPD_BUS_NUM 0 +#define SPD_EEPROM_ADDRESS 0x50 +#define CONFIG_SYS_DDR_RAW_TIMING + +#define CONFIG_DDR_ECC + +#ifdef CONFIG_DDR_ECC +#define CONFIG_MEM_INIT_VALUE 0xDeadBeef +#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER +#endif + +#define CONFIG_SYS_SDRAM_SIZE 512 +#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 +#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE + +#define CONFIG_DIMM_SLOTS_PER_CTLR 1 +#define CONFIG_CHIP_SELECTS_PER_CTRL 1 + +#define CONFIG_SYS_CCSRBAR 0xffe00000 +#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR + +/* Platform SRAM setting */ +#define CONFIG_SYS_PLATFORM_SRAM_BASE 0xffb00000 +#define CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS \ + (0xf00000000ull | CONFIG_SYS_PLATFORM_SRAM_BASE) +#define CONFIG_SYS_PLATFORM_SRAM_SIZE (512 << 10) + +/* + * IFC Definitions + */ +/* NOR Flash on IFC */ +#define CONFIG_SYS_FLASH_BASE 0xec000000 +#define CONFIG_SYS_MAX_FLASH_SECT 512 /* 64M */ + +#define CONFIG_SYS_FLASH_BASE_PHYS (0xf00000000ull | CONFIG_SYS_FLASH_BASE) + +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE_PHYS } +#define CONFIG_SYS_MAX_FLASH_BANKS 1 + +#define CONFIG_SYS_FLASH_QUIET_TEST +#define CONFIG_FLASH_SHOW_PROGRESS 45 +#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* in ms */ +#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* in ms */ + +/* 16Bit NOR Flash - S29GL512S10TFI01 */ +#define CONFIG_SYS_NOR_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | \ + CSPR_PORT_SIZE_16 | \ + CSPR_MSEL_NOR | \ + CSPR_V) +#define CONFIG_SYS_NOR_AMASK IFC_AMASK(64*1024*1024) +#define CONFIG_SYS_NOR_CSOR CSOR_NOR_ADM_SHIFT(4) +#define CONFIG_SYS_NOR_FTIM0 (FTIM0_NOR_TACSE(0x4) | \ + FTIM0_NOR_TEADC(0x5) | \ + FTIM0_NOR_TEAHC(0x5)) +#define CONFIG_SYS_NOR_FTIM1 (FTIM1_NOR_TACO(0x1e) | \ + FTIM1_NOR_TRAD_NOR(0x0f) | \ + FTIM1_NOR_TSEQRAD_NOR(0x0f)) +#define CONFIG_SYS_NOR_FTIM2 (FTIM2_NOR_TCS(0x4) | \ + FTIM2_NOR_TCH(0x4) | \ + FTIM2_NOR_TWP(0x1c)) +#define CONFIG_SYS_NOR_FTIM3 0x0 + +/* CFI for NOR Flash */ +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_SYS_FLASH_EMPTY_INFO +#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE + +/* NAND Flash on IFC */ +#define CONFIG_NAND_FSL_IFC +#define CONFIG_SYS_NAND_BASE 0xff800000 +#define CONFIG_SYS_NAND_BASE_PHYS 0xfff800000ull + +#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } + +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_MTD_NAND_VERIFY_WRITE +#define CONFIG_CMD_NAND +#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) + +/* 8Bit NAND Flash - K9F1G08U0B */ +#define CONFIG_SYS_NAND_CSPR (CSPR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_NAND \ + | CSPR_V) +#define CONFIG_SYS_NAND_AMASK IFC_AMASK(64*1024) +#define CONFIG_SYS_NAND_CSOR (CSOR_NAND_ECC_ENC_EN /* ECC on encode */ \ + | CSOR_NAND_ECC_DEC_EN /* ECC on decode */ \ + | CSOR_NAND_ECC_MODE_4 /* 4-bit ECC */ \ + | CSOR_NAND_RAL_2 /* RAL = 2 Bytes */ \ + | CSOR_NAND_PGS_2K /* Page Size = 2k */ \ + | CSOR_NAND_SPRZ_64 /* Spare size = 64 */ \ + | CSOR_NAND_PB(64)) /* 64 Pages Per Block */ +#define CONFIG_SYS_NAND_FTIM0 (FTIM0_NAND_TCCST(0x01) | \ + FTIM0_NAND_TWP(0x0c) | \ + FTIM0_NAND_TWCHT(0x08) | \ + FTIM0_NAND_TWH(0x06)) +#define CONFIG_SYS_NAND_FTIM1 (FTIM1_NAND_TADLE(0x28) | \ + FTIM1_NAND_TWBE(0x1d) | \ + FTIM1_NAND_TRR(0x08) | \ + FTIM1_NAND_TRP(0x0c)) +#define CONFIG_SYS_NAND_FTIM2 (FTIM2_NAND_TRAD(0x0c) | \ + FTIM2_NAND_TREH(0x0a) | \ + FTIM2_NAND_TWHRE(0x18)) +#define CONFIG_SYS_NAND_FTIM3 (FTIM3_NAND_TWW(0x04)) + +#define CONFIG_SYS_NAND_DDR_LAW 11 + +/* Set up IFC registers for boot location NOR/NAND */ +#define CONFIG_SYS_CSPR0 CONFIG_SYS_NOR_CSPR +#define CONFIG_SYS_AMASK0 CONFIG_SYS_NOR_AMASK +#define CONFIG_SYS_CSOR0 CONFIG_SYS_NOR_CSOR +#define CONFIG_SYS_CS0_FTIM0 CONFIG_SYS_NOR_FTIM0 +#define CONFIG_SYS_CS0_FTIM1 CONFIG_SYS_NOR_FTIM1 +#define CONFIG_SYS_CS0_FTIM2 CONFIG_SYS_NOR_FTIM2 +#define CONFIG_SYS_CS0_FTIM3 CONFIG_SYS_NOR_FTIM3 +#define CONFIG_SYS_CSPR1 CONFIG_SYS_NAND_CSPR +#define CONFIG_SYS_AMASK1 CONFIG_SYS_NAND_AMASK +#define CONFIG_SYS_CSOR1 CONFIG_SYS_NAND_CSOR +#define CONFIG_SYS_CS1_FTIM0 CONFIG_SYS_NAND_FTIM0 +#define CONFIG_SYS_CS1_FTIM1 CONFIG_SYS_NAND_FTIM1 +#define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 +#define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3 + +/* CPLD on IFC, selected by CS2 */ +#define CONFIG_SYS_CPLD_BASE 0xffdf0000 +#define CONFIG_SYS_CPLD_BASE_PHYS (0xf00000000ull \ + | CONFIG_SYS_CPLD_BASE) + +#define CONFIG_SYS_CSPR2 (CSPR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) \ + | CSPR_PORT_SIZE_8 \ + | CSPR_MSEL_GPCM \ + | CSPR_V) +#define CONFIG_SYS_AMASK2 IFC_AMASK(64*1024) +#define CONFIG_SYS_CSOR2 0x0 +/* CPLD Timing parameters for IFC CS2 */ +#define CONFIG_SYS_CS2_FTIM0 (FTIM0_GPCM_TACSE(0x0e) | \ + FTIM0_GPCM_TEADC(0x0e) | \ + FTIM0_GPCM_TEAHC(0x0e)) +#define CONFIG_SYS_CS2_FTIM1 (FTIM1_GPCM_TACO(0x0e) | \ + FTIM1_GPCM_TRAD(0x1f)) +#define CONFIG_SYS_CS2_FTIM2 (FTIM2_GPCM_TCS(0x0e) | \ + FTIM2_GPCM_TCH(0x0) | \ + FTIM2_GPCM_TWP(0x1f)) +#define CONFIG_SYS_CS2_FTIM3 0x0 + +#if defined(CONFIG_RAMBOOT_SPIFLASH) +#define CONFIG_SYS_RAMBOOT +#define CONFIG_SYS_EXTRA_ENV_RELOC +#else +#undef CONFIG_SYS_RAMBOOT +#endif + +#define CONFIG_BOARD_EARLY_INIT_R + +#define CONFIG_SYS_INIT_RAM_LOCK +#define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 +#define CONFIG_SYS_INIT_RAM_END 0x00004000 + +#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END \ + - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET + +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) + +/* Serial Port */ +#define CONFIG_CONS_INDEX 1 +#define CONFIG_SYS_NS16550 +#define CONFIG_SYS_NS16550_SERIAL +#define CONFIG_SYS_NS16550_REG_SIZE 1 +#define CONFIG_SYS_NS16550_CLK get_bus_freq(0) + +#define CONFIG_SERIAL_MULTI /* Enable both serial ports */ +#define CONFIG_SYS_CONSOLE_IS_IN_ENV + +#define CONFIG_SYS_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) +#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) + +/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif + +/* + * Pass open firmware flat tree + */ +#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_OF_STDOUT_VIA_ALIAS + +/* new uImage format support */ +#define CONFIG_FIT +#define CONFIG_FIT_VERBOSE /* enable fit_format_{error,warning}() */ + +#define CONFIG_FSL_I2C +#define CONFIG_HARD_I2C +#define CONFIG_I2C_MULTI_BUS +#define CONFIG_I2C_CMD_TREE +#define CONFIG_SYS_I2C_SPEED 400000 +#define CONFIG_SYS_I2C_SLAVE 0x7F +#define CONFIG_SYS_I2C_OFFSET 0x3000 +#define CONFIG_SYS_I2C2_OFFSET 0x3100 + +/* I2C EEPROM */ +/* enable read and write access to EEPROM */ +#define CONFIG_CMD_EEPROM +#define CONFIG_SYS_I2C_MULTI_EEPROMS +#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 +#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5 + +#define CONFIG_CMD_I2C + +/* eSPI - Enhanced SPI */ +#define CONFIG_FSL_ESPI +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_SPANSION +#define CONFIG_SPI_FLASH_EON +#define CONFIG_CMD_SF +#define CONFIG_SF_DEFAULT_SPEED 10000000 +#define CONFIG_SF_DEFAULT_MODE SPI_MODE_0 + +#ifdef CONFIG_TSEC_ENET +#ifndef CONFIG_NET_MULTI +#define CONFIG_NET_MULTI +#endif + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_MII_DEFAULT_TSEC 1 /* Allow unregistered phys */ +#define CONFIG_TSEC1 1 +#define CONFIG_TSEC1_NAME "eTSEC1" +#define CONFIG_TSEC2 1 +#define CONFIG_TSEC2_NAME "eTSEC2" + +/* Default mode is RGMII mode */ +#define TSEC1_PHY_ADDR 0 +#define TSEC2_PHY_ADDR 2 + +#define TSEC1_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) +#define TSEC2_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) + +#define CONFIG_ETHPRIME "eTSEC1" + +#define CONFIG_PHY_GIGE +#endif /* CONFIG_TSEC_ENET */ + +/* + * Environment + */ +#if defined(CONFIG_SYS_RAMBOOT) +#if defined(CONFIG_RAMBOOT_SPIFLASH) +#define CONFIG_ENV_IS_IN_SPI_FLASH +#define CONFIG_ENV_SPI_BUS 0 +#define CONFIG_ENV_SPI_CS 0 +#define CONFIG_ENV_SPI_MAX_HZ 10000000 +#define CONFIG_ENV_SPI_MODE 0 +#define CONFIG_ENV_OFFSET 0x100000 /* 1MB */ +#define CONFIG_ENV_SECT_SIZE 0x10000 +#define CONFIG_ENV_SIZE 0x2000 +#endif +#else +#define CONFIG_ENV_IS_IN_FLASH +#if CONFIG_SYS_MONITOR_BASE > 0xfff80000 +#define CONFIG_ENV_ADDR 0xfff80000 +#else +#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) +#endif +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_ENV_SECT_SIZE 0x20000 +#endif + +#define CONFIG_LOADS_ECHO +#define CONFIG_SYS_LOADS_BAUD_CHANGE + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ERRATA +#define CONFIG_CMD_ELF +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SETEXPR +#define CONFIG_CMD_REGINFO + +/* + * Miscellaneous configurable options + */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ +#define CONFIG_AUTO_COMPLETE /* add autocompletion support */ +#define CONFIG_SYS_LOAD_ADDR 0x2000000 /* default load address */ +#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ + +#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) + /* Print Buffer Size */ +#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE/* Boot Argument Buffer Size */ +#define CONFIG_SYS_HZ 1000 /* dec freq: 1ms ticks */ + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 64 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CONFIG_SYS_BOOTMAPSZ (64 << 20) /* Initial Memory map for Linux */ +#define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */ + +/* + * Environment Configuration + */ + +#ifdef CONFIG_TSEC_ENET +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#endif + +#define CONFIG_ROOTPATH "/opt/nfsroot" +#define CONFIG_BOOTFILE "uImage" +#define CONFIG_UBOOTPATH u-boot.bin/* U-Boot image on TFTP server */ + +/* default location for tftp and bootm */ +#define CONFIG_LOADADDR 1000000 + +#define CONFIG_BOOTDELAY 10 /* -1 disables auto-boot */ + +#define CONFIG_BAUDRATE 115200 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "hwconfig=" __stringify(CONFIG_DEF_HWCONFIG) "\0" \ + "netdev=eth0\0" \ + "uboot=" __stringify(CONFIG_UBOOTPATH) "\0" \ + "loadaddr=1000000\0" \ + "consoledev=ttyS0\0" \ + "ramdiskaddr=2000000\0" \ + "ramdiskfile=rootfs.ext2.gz.uboot\0" \ + "fdtaddr=c00000\0" \ + "fdtfile=name/of/device-tree.dtb\0" \ + "othbootargs=ramdisk_size=600000\0" \ + +#define CONFIG_RAMBOOTCOMMAND \ + "setenv bootargs root=/dev/ram rw " \ + "console=$consoledev,$baudrate $othbootargs; " \ + "tftp $ramdiskaddr $ramdiskfile;" \ + "tftp $loadaddr $bootfile;" \ + "tftp $fdtaddr $fdtfile;" \ + "bootm $loadaddr $ramdiskaddr $fdtaddr" + +#define CONFIG_BOOTCOMMAND CONFIG_RAMBOOTCOMMAND + +#endif /* __CONFIG_H */
On 07/02/2013 01:39:09 AM, Po Liu wrote:
+int board_early_init_r(void) +{
- const unsigned long flashbase = CONFIG_SYS_FLASH_BASE;
- const u8 flash_esel = find_tlb_idx((void *)flashbase, 1);
- /*
* Remap Boot flash region to caching-inhibited* so that flash can be erased properly.*/- /* Flush d-cache and invalidate i-cache of any FLASH data */
- flush_dcache();
- invalidate_icache();
- /* invalidate existing TLB entry for flash */
- disable_tlb(flash_esel);
- set_tlb(1, flashbase, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,0, flash_esel, BOOKE_PAGESZ_64M, 1);
Don't set MAS3_SX on I/O regions.
+#if defined(CONFIG_OF_BOARD_SETUP) +void fdt_del_sec(void *blob, int offset) +{
- int nodeoff = 0;
- while ((nodeoff = fdt_node_offset_by_compat_reg(blob,
"fsl,sec-v6.0",
CONFIG_SYS_CCSRBAR_PHYS +CONFIG_SYS_FSL_SEC_OFFSET
+ offset * 0x20000)) >= 0) {fdt_del_node(blob, nodeoff);offset++;}+}
Whitespace
+static u8 __cpld_read(unsigned int reg) +{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
- return in_8(p + reg);
+}
+u8 cpld_read(unsigned int reg) __attribute__((weak, alias("__cpld_read")));
+static void __cpld_write(unsigned int reg, u8 value) +{
- void *p = (void *)CONFIG_SYS_CPLD_BASE;
- out_8(p + reg, value);
+}
+void cpld_write(unsigned int reg, u8 value)
- __attribute__((weak, alias("__cpld_write")));
Why does this need to be weak? Where do you expect to call cpld_read/write that isn't specific to this board? What sort of behavior could a non-board-specific caller possibly expect?
+/**
- Set the boot bank to the alternate bank
- */
+void __cpld_set_altbank(u8 banksel) +{
- u8 reg11 = CPLD_READ(flhcsr);
- switch (banksel) {
- case 1:
CPLD_WRITE(flhcsr, (reg11 & CPLD_BANKSEL_MASK)| CPLD_BANKSEL_EN | CPLD_SELECT_BANK1);break;- case 2:
CPLD_WRITE(flhcsr, (reg11 & CPLD_BANKSEL_MASK)| CPLD_BANKSEL_EN | CPLD_SELECT_BANK2);break;- case 3:
CPLD_WRITE(flhcsr, (reg11 & CPLD_BANKSEL_MASK)| CPLD_BANKSEL_EN | CPLD_SELECT_BANK3);break;- case 4:
CPLD_WRITE(flhcsr, (reg11 & CPLD_BANKSEL_MASK)| CPLD_BANKSEL_EN | CPLD_SELECT_BANK4);break;
So there's a __cpld_write, a cpld_write, *and* a CPLD_WRITE?
+#define CPLD_READ(reg) cpld_read(offsetof(struct cpld_data, reg)) +#define CPLD_WRITE(reg, value) cpld_write(offsetof(struct cpld_data, reg), \
value)
Ugh. Why not just initialize a pointer to CONFIG_SYS_CPLD_BASE, and use normal I/O accessors on that, just like every other driver that isn't the p2041rdb CPLD code you copied this from?
+struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M,
LAW_TRGT_IF_IFC),
- SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_4K,
LAW_TRGT_IF_IFC),
- SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_1M,
LAW_TRGT_IF_IFC),
The NAND SRAM window is 16K. There is no reason to make the LAW 1M.
- /* TLB 1 */
- /* *I*** - Covers boot page */
- SET_TLB_ENTRY(1, 0xfffff000, 0xfffff000,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,0, 0, BOOKE_PAGESZ_4K, 1),
Comment says *I*** but code says *I*G*.
Do we still use this mapping at all?
- /* *I*G* - CCSRBAR */
- SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,0, 1, BOOKE_PAGESZ_1M, 1),- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE,
CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,0, 2, BOOKE_PAGESZ_64M, 1),
Why do most of these entries have a comment but some (like this flash entry) don't? Be consistent. Probably better to remove all of these comments since they don't say anything that isn't clear from the code, and are often wrong.
- SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE,
CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,0, 6, BOOKE_PAGESZ_1M, 1),
Again, this can be 16K.
- /* *I*G - platform SRAM */
- SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE,
CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS,MAS3_SX|MAS3_SW|MAS3_SR, 0,0, 7, BOOKE_PAGESZ_256K, 1),- SET_TLB_ENTRY(1, CONFIG_SYS_PLATFORM_SRAM_BASE + 0x40000,
CONFIG_SYS_PLATFORM_SRAM_BASE_PHYS + 0x40000,MAS3_SX|MAS3_SW|MAS3_SR, 0,0, 8, BOOKE_PAGESZ_256K, 1),
Comment says *I*G but it isn't.
+/* Use the HUSH parser */ +#define CONFIG_SYS_HUSH_PARSER +#ifdef CONFIG_SYS_HUSH_PARSER +#define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#endif
Again, "Please go through this file and only retain things which actually continue to make sense."
This is a pointless ifdef, and a pointless define of CONFIG_SYS_PROMPT_HUSH_PS2 since that's the same as the default.
+/*
- Internal Definitions
- Boot Flags
- */
+#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */
Sigh.
-Scott
From: Mingkai Hu Mingkai.Hu@freescale.com
The Freescale C29x family is a high performance crypto co-processor. It combines a single e500v2 core with necessary SEC engine. There're three SoC types(C291, C292, C293) with the following features:
- 512K L2 Cache/SRAM and 512 KB platform SRAM - DDR3/DDR3L 32bit DDR controller - One PCI express (x1, x2, x4) Gen 2.0 Controller - Trust Architecture 2.0 - SEC6.0 engine
Signed-off-by: Mingkai Hu Mingkai.Hu@freescale.com Signed-off-by: Po Liu Po.Liu@freescale.com --- Changes for v2: - Remove define CONFIG_C291/CONFIG_C292/CONFIG_C293, replace with CONFIG_C29X Changes for v3: - Replace CONFIG_C29X with CONFIG_PPC_C29X Changes for v4: - None Changes for v5: - None
arch/powerpc/cpu/mpc85xx/Makefile | 2 + arch/powerpc/cpu/mpc85xx/c29x_serdes.c | 65 +++++++++++++++++++++++++++++++ arch/powerpc/cpu/mpc8xxx/cpu.c | 3 ++ arch/powerpc/include/asm/config_mpc85xx.h | 12 ++++++ arch/powerpc/include/asm/fsl_law.h | 1 + arch/powerpc/include/asm/immap_85xx.h | 23 +++++++++++ arch/powerpc/include/asm/processor.h | 3 ++ 7 files changed, 109 insertions(+) create mode 100644 arch/powerpc/cpu/mpc85xx/c29x_serdes.c
diff --git a/arch/powerpc/cpu/mpc85xx/Makefile b/arch/powerpc/cpu/mpc85xx/Makefile index 4669883..3cb2a78 100644 --- a/arch/powerpc/cpu/mpc85xx/Makefile +++ b/arch/powerpc/cpu/mpc85xx/Makefile @@ -62,6 +62,7 @@ COBJS-$(CONFIG_MPC8568) += ddr-gen2.o COBJS-$(CONFIG_MPC8544) += ddr-gen2.o
# supports ddr1/2/3 +COBJS-$(CONFIG_PPC_C29X) += ddr-gen3.o COBJS-$(CONFIG_MPC8572) += ddr-gen3.o COBJS-$(CONFIG_MPC8536) += ddr-gen3.o COBJS-$(CONFIG_MPC8569) += ddr-gen3.o @@ -116,6 +117,7 @@ COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS1) += fsl_corenet_serdes.o COBJS-$(CONFIG_SYS_FSL_QORIQ_CHASSIS2) += fsl_corenet2_serdes.o
# SoC specific SERDES support +COBJS-$(CONFIG_PPC_C29X) += c29x_serdes.o COBJS-$(CONFIG_MPC8536) += mpc8536_serdes.o COBJS-$(CONFIG_MPC8544) += mpc8544_serdes.o COBJS-$(CONFIG_MPC8548) += mpc8548_serdes.o diff --git a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c new file mode 100644 index 0000000..4b3214d --- /dev/null +++ b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c @@ -0,0 +1,65 @@ +/* + * Copyright 2013 Freescale Semiconductor, Inc. + * + * This program is free software; you can redistribute it and/or modify it + * under the terms of the GNU General Public License as published by the Free + * Software Foundation; either version 2 of the License, or (at your option) + * any later version. + */ + +#include <config.h> +#include <common.h> +#include <asm/io.h> +#include <asm/immap_85xx.h> +#include <asm/fsl_serdes.h> + +#define SRDS1_MAX_LANES 4 + +static u32 serdes1_prtcl_map; + +struct serdes_config { + u32 protocol; + u8 lanes[SRDS1_MAX_LANES]; +}; + +static const struct serdes_config serdes1_cfg_tbl[] = { + /* SerDes 1 */ + {1, {PCIE1, PCIE1, PCIE1, PCIE1} }, + {2, {PCIE1, PCIE1, PCIE1, PCIE1} }, + {3, {PCIE1, PCIE1, NONE, NONE} }, + {4, {PCIE1, PCIE1, NONE, NONE} }, + {5, {PCIE1, NONE, NONE, NONE} }, + {6, {PCIE1, NONE, NONE, NONE} }, + {} +}; + +int is_serdes_configured(enum srds_prtcl device) +{ + return (1 << device) & serdes1_prtcl_map; +} + +void fsl_serdes_init(void) +{ + ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + u32 pordevsr = in_be32(&gur->pordevsr); + u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> + MPC85xx_PORDEVSR_IO_SEL_SHIFT; + const struct serdes_config *ptr; + int lane; + + debug("PORDEVSR[IO_SEL_SRDS] = %x\n", srds_cfg); + + if (srds_cfg > ARRAY_SIZE(serdes1_cfg_tbl)) { + printf("Invalid PORDEVSR[IO_SEL_SRDS] = %d\n", srds_cfg); + return; + } + + ptr = &serdes1_cfg_tbl[srds_cfg]; + if (!ptr->protocol) + return; + + for (lane = 0; lane < SRDS1_MAX_LANES; lane++) { + enum srds_prtcl lane_prtcl = ptr->lanes[lane]; + serdes1_prtcl_map |= (1 << lane_prtcl); + } +} diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index bc26855..2eed872 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -95,6 +95,9 @@ static struct cpu_type cpu_type_list[] = { CPU_TYPE_ENTRY(BSC9131, 9131, 1), CPU_TYPE_ENTRY(BSC9132, 9132, 2), CPU_TYPE_ENTRY(BSC9232, 9232, 2), + CPU_TYPE_ENTRY(C291, C291, 1), + CPU_TYPE_ENTRY(C292, C292, 1), + CPU_TYPE_ENTRY(C293, C293, 1), #elif defined(CONFIG_MPC86xx) CPU_TYPE_ENTRY(8610, 8610, 1), CPU_TYPE_ENTRY(8641, 8641, 2), diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index 1d46b14..3f48802 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -626,6 +626,18 @@ #define CONFIG_SYS_FSL_USB_INTERNAL_UTMI_PHY #define CONFIG_SYS_CCSRBAR_DEFAULT 0xfe000000
+#elif defined(CONFIG_PPC_C29X) +#define CONFIG_MAX_CPUS 1 +#define CONFIG_FSL_SDHC_V2_3 +#define CONFIG_SYS_FSL_NUM_LAWS 12 +#define CONFIG_SYS_PPC_E500_DEBUG_TLB 3 +#define CONFIG_TSECV2_1 +#define CONFIG_SYS_FSL_SEC_COMPAT 6 +#define CONFIG_SYS_FSL_ERRATUM_ESDHC111 +#define CONFIG_NUM_DDR_CONTROLLERS 1 +#define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 +#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 + #else #error Processor type not defined for this platform #endif diff --git a/arch/powerpc/include/asm/fsl_law.h b/arch/powerpc/include/asm/fsl_law.h index bea1636..9eb3e13 100644 --- a/arch/powerpc/include/asm/fsl_law.h +++ b/arch/powerpc/include/asm/fsl_law.h @@ -92,6 +92,7 @@ enum law_trgt_if { LAW_TRGT_IF_LBC = 0x04, LAW_TRGT_IF_CCSR = 0x08, LAW_TRGT_IF_DSP_CCSR = 0x09, + LAW_TRGT_IF_PLATFORM_SRAM = 0x0a, LAW_TRGT_IF_DDR_INTRLV = 0x0b, LAW_TRGT_IF_RIO = 0x0c, LAW_TRGT_IF_RIO_2 = 0x0d, diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index db70d04..af3853a 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2147,6 +2147,11 @@ typedef struct ccsr_gur { #ifdef CONFIG_MPC8536 #define MPC85xx_PORPLLSR_DDR_RATIO 0x3e000000 #define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT 25 +#elif defined(CONFIG_PPC_C29X) +#define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 +#define MPC85xx_PORPLLSR_DDR_RATIO_SHIFT (9 - ((gur->pordevsr2 \ + & MPC85xx_PORDEVSR2_DDR_SPD_0) \ + >> MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT)) #else #if defined(CONFIG_BSC9131) || defined(CONFIG_BSC9132) #define MPC85xx_PORPLLSR_DDR_RATIO 0x00003f00 @@ -2194,6 +2199,9 @@ typedef struct ccsr_gur { #elif defined(CONFIG_BSC9132) #define MPC85xx_PORDEVSR_IO_SEL 0x00FE0000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 17 +#elif defined(CONFIG_PPC_C29X) +#define MPC85xx_PORDEVSR_IO_SEL 0x00e00000 +#define MPC85xx_PORDEVSR_IO_SEL_SHIFT 21 #else #define MPC85xx_PORDEVSR_IO_SEL 0x00780000 #define MPC85xx_PORDEVSR_IO_SEL_SHIFT 19 @@ -2209,6 +2217,10 @@ typedef struct ccsr_gur { #define MPC85xx_PORDEVSR_RIO_DEV_ID 0x00000007 u32 pordbgmsr; /* POR debug mode status */ u32 pordevsr2; /* POR I/O device status 2 */ +#if defined(CONFIG_PPC_C29X) +#define MPC85xx_PORDEVSR2_DDR_SPD_0 0x00000008 +#define MPC85xx_PORDEVSR2_DDR_SPD_0_SHIFT 3 +#endif /* The 8544 RM says this is bit 26, but it's really bit 24 */ #define MPC85xx_PORDEVSR2_SEC_CFG 0x00000080 u8 res1[8]; @@ -2355,6 +2367,11 @@ typedef struct ccsr_gur { #define MPC85xx_PMUXCR0_SIM_SEL_MASK 0x0003b000 #define MPC85xx_PMUXCR0_SIM_SEL 0x00014000 #endif +#if defined(CONFIG_PPC_C29X) +#define MPC85xx_PMUXCR_SPI_MASK 0x00000300 +#define MPC85xx_PMUXCR_SPI 0x00000000 +#define MPC85xx_PMUXCR_SPI_GPIO 0x00000100 +#endif u32 pmuxcr2; /* Alt. function signal multiplex control 2 */ #if defined(CONFIG_P1010) || defined(CONFIG_P1014) #define MPC85xx_PMUXCR2_UART_GPIO 0x40000000 @@ -3024,12 +3041,18 @@ struct ccsr_pman { #define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000 #ifdef CONFIG_TSECV2 #define CONFIG_SYS_TSEC1_OFFSET 0xB0000 +#elif defined(CONFIG_TSECV2_1) +#define CONFIG_SYS_TSEC1_OFFSET 0x10000 #else #define CONFIG_SYS_TSEC1_OFFSET 0x24000 #endif #define CONFIG_SYS_MDIO1_OFFSET 0x24000 #define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 +#if defined(CONFIG_PPC_C29X) +#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000 +#else #define CONFIG_SYS_FSL_SEC_OFFSET 0x30000 +#endif #define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 #define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 #define CONFIG_SYS_SNVS_OFFSET 0xE6000 diff --git a/arch/powerpc/include/asm/processor.h b/arch/powerpc/include/asm/processor.h index 56b22d8..64a6f9c 100644 --- a/arch/powerpc/include/asm/processor.h +++ b/arch/powerpc/include/asm/processor.h @@ -1119,6 +1119,9 @@ #define SVR_T4240 0x824000 #define SVR_T4120 0x824001 #define SVR_T4160 0x824100 +#define SVR_C291 0x850000 +#define SVR_C292 0x850020 +#define SVR_C293 0x850030 #define SVR_B4860 0X868000 #define SVR_G4860 0x868001 #define SVR_G4060 0x868003
participants (2)
-
Po Liu -
Scott Wood