[PATCH 01/21] Convert CONFIG_SYS_I2C_INIT_BOARD to Kconfig
This converts the following to Kconfig: CONFIG_SYS_I2C_INIT_BOARD
Signed-off-by: Tom Rini trini@konsulko.com --- README | 11 ----------- board/keymile/Kconfig | 3 +++ board/samsung/common/board.c | 4 ---- board/samsung/goni/goni.c | 10 ---------- drivers/i2c/fsl_i2c.c | 7 ------- drivers/i2c/mv_i2c.c | 24 ------------------------ include/configs/km/pg-wcom-ls102xa.h | 1 - 7 files changed, 3 insertions(+), 57 deletions(-)
diff --git a/README b/README index 186f1f9a5ffb..92ad191ae76d 100644 --- a/README +++ b/README @@ -1126,17 +1126,6 @@ The following options need to be configured: You should define these to the GPIO value as given directly to the generic GPIO functions.
- CONFIG_SYS_I2C_INIT_BOARD - - When a board is reset during an i2c bus transfer - chips might think that the current transfer is still - in progress. On some boards it is possible to access - the i2c SCLK line directly, either by using the - processor pin as a GPIO or by having a second pin - connected to the bus. If this option is defined a - custom i2c_init_board() routine in boards/xxx/board.c - is run early in the boot sequence. - CONFIG_I2C_MULTI_BUS
This option allows the use of multiple I2C buses, each of which diff --git a/board/keymile/Kconfig b/board/keymile/Kconfig index 9f784430b1d5..b8f0578a286f 100644 --- a/board/keymile/Kconfig +++ b/board/keymile/Kconfig @@ -11,6 +11,9 @@ if VENDOR_KM
menu "KM Board Setup"
+config SYS_I2C_INIT_BOARD + def_bool y if ARM + config HUSH_INIT_VAR def_bool y
diff --git a/board/samsung/common/board.c b/board/samsung/common/board.c index ff178b7fe677..e476400ecdc8 100644 --- a/board/samsung/common/board.c +++ b/board/samsung/common/board.c @@ -177,10 +177,6 @@ int board_early_init_f(void) return err; }
-#ifdef CONFIG_SYS_I2C_INIT_BOARD - board_i2c_init(gd->fdt_blob); -#endif - return exynos_early_init_f(); } #endif diff --git a/board/samsung/goni/goni.c b/board/samsung/goni/goni.c index ba25ba27b863..535f8e1e0129 100644 --- a/board/samsung/goni/goni.c +++ b/board/samsung/goni/goni.c @@ -33,16 +33,6 @@ int board_init(void) return 0; }
-#ifdef CONFIG_SYS_I2C_INIT_BOARD -void i2c_init_board(void) -{ - gpio_request(S5PC110_GPIO_J43, "i2c_clk"); - gpio_request(S5PC110_GPIO_J40, "i2c_data"); - gpio_direction_output(S5PC110_GPIO_J43, 1); - gpio_direction_output(S5PC110_GPIO_J40, 1); -} -#endif - int dram_init(void) { gd->ram_size = PHYS_SDRAM_1_SIZE + PHYS_SDRAM_2_SIZE + diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 9a3c8241bc64..edbcd83b6469 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -271,13 +271,6 @@ static void __i2c_init(const struct fsl_i2c_base *base, int speed, int const unsigned long long timeout = usec2ticks(CONFIG_I2C_MBB_TIMEOUT); unsigned long long timeval;
-#ifdef CONFIG_SYS_I2C_INIT_BOARD - /* Call board specific i2c bus reset routine before accessing the - * environment, which might be in a chip on that bus. For details - * about this problem see doc/I2C_Edge_Conditions. - */ - i2c_init_board(); -#endif writeb(0, &base->cr); /* stop I2C controller */ udelay(5); /* let it shutdown in peace */ set_i2c_bus_speed(base, i2c_clk, speed); diff --git a/drivers/i2c/mv_i2c.c b/drivers/i2c/mv_i2c.c index 0eff3531618c..8ee17f0a4501 100644 --- a/drivers/i2c/mv_i2c.c +++ b/drivers/i2c/mv_i2c.c @@ -374,27 +374,6 @@ static int __i2c_write(struct mv_i2c *base, uchar chip, u8 *addr, int alen,
static struct mv_i2c *base_glob;
-static void i2c_board_init(struct mv_i2c *base) -{ -#ifdef CONFIG_SYS_I2C_INIT_BOARD - u32 icr; - /* - * call board specific i2c bus reset routine before accessing the - * environment, which might be in a chip on that bus. For details - * about this problem see doc/I2C_Edge_Conditions. - * - * disable I2C controller first, otherwhise it thinks we want to - * talk to the slave port... - */ - icr = readl(&base->icr); - writel(readl(&base->icr) & ~(ICR_SCLE | ICR_IUE), &base->icr); - - i2c_init_board(); - - writel(icr, &base->icr); -#endif -} - #ifdef CONFIG_I2C_MULTI_BUS static unsigned long i2c_regs[CONFIG_MV_I2C_NUM] = CONFIG_MV_I2C_REG; static unsigned int bus_initialized[CONFIG_MV_I2C_NUM]; @@ -411,7 +390,6 @@ int i2c_set_bus_num(unsigned int bus) current_bus = bus;
if (!bus_initialized[current_bus]) { - i2c_board_init(base_glob); bus_initialized[current_bus] = 1; }
@@ -441,8 +419,6 @@ void i2c_init(int speed, int slaveaddr) else val = ICR_SM; clrsetbits_le32(&base_glob->icr, ICR_MODE_MASK, val); - - i2c_board_init(base_glob); }
static int __i2c_probe_chip(struct mv_i2c *base, uchar chip) diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 43471e08d604..9565cea083e0 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -155,7 +155,6 @@ /* * I2C */ -#define CONFIG_SYS_I2C_INIT_BOARD
#define CONFIG_I2C_MULTI_BUS #define CONFIG_SYS_I2C_MAX_HOPS 1
This converts the following to Kconfig: CONFIG_SYS_INIT_RAM_LOCK
Signed-off-by: Tom Rini trini@konsulko.com --- arch/powerpc/Kconfig | 4 ++++ arch/powerpc/include/asm/cache.h | 2 -- configs/MPC837XERDB_defconfig | 1 + configs/MPC8548CDS_36BIT_defconfig | 1 + configs/MPC8548CDS_defconfig | 1 + configs/MPC8548CDS_legacy_defconfig | 1 + configs/P1010RDB-PA_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PA_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 1 + configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PA_NAND_defconfig | 1 + configs/P1010RDB-PA_NOR_defconfig | 1 + configs/P1010RDB-PA_SDCARD_defconfig | 1 + configs/P1010RDB-PA_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PB_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 1 + configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_NAND_defconfig | 1 + configs/P1010RDB-PB_NOR_defconfig | 1 + configs/P1010RDB-PB_SDCARD_defconfig | 1 + configs/P1010RDB-PB_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_defconfig | 1 + configs/P1020RDB-PC_NAND_defconfig | 1 + configs/P1020RDB-PC_SDCARD_defconfig | 1 + configs/P1020RDB-PC_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_defconfig | 1 + configs/P1020RDB-PD_NAND_defconfig | 1 + configs/P1020RDB-PD_SDCARD_defconfig | 1 + configs/P1020RDB-PD_SPIFLASH_defconfig | 1 + configs/P1020RDB-PD_defconfig | 1 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_36BIT_defconfig | 1 + configs/P2020RDB-PC_NAND_defconfig | 1 + configs/P2020RDB-PC_SDCARD_defconfig | 1 + configs/P2020RDB-PC_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_defconfig | 1 + configs/P2041RDB_NAND_defconfig | 1 + configs/P2041RDB_SDCARD_defconfig | 1 + configs/P2041RDB_SPIFLASH_defconfig | 1 + configs/P2041RDB_defconfig | 1 + configs/T1024RDB_NAND_defconfig | 1 + configs/T1024RDB_SDCARD_defconfig | 1 + configs/T1024RDB_SPIFLASH_defconfig | 1 + configs/T1024RDB_defconfig | 1 + configs/T1042D4RDB_NAND_defconfig | 1 + configs/T1042D4RDB_SDCARD_defconfig | 1 + configs/T1042D4RDB_SPIFLASH_defconfig | 1 + configs/T1042D4RDB_defconfig | 1 + configs/T2080QDS_NAND_defconfig | 1 + configs/T2080QDS_SDCARD_defconfig | 1 + configs/T2080QDS_SECURE_BOOT_defconfig | 1 + configs/T2080QDS_SPIFLASH_defconfig | 1 + configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 1 + configs/T2080QDS_defconfig | 1 + configs/T2080RDB_NAND_defconfig | 1 + configs/T2080RDB_SDCARD_defconfig | 1 + configs/T2080RDB_SPIFLASH_defconfig | 1 + configs/T2080RDB_defconfig | 1 + configs/T2080RDB_revD_NAND_defconfig | 1 + configs/T2080RDB_revD_SDCARD_defconfig | 1 + configs/T2080RDB_revD_SPIFLASH_defconfig | 1 + configs/T2080RDB_revD_defconfig | 1 + configs/T4240RDB_SDCARD_defconfig | 1 + configs/T4240RDB_defconfig | 1 + configs/gazerbeam_defconfig | 1 + configs/kmcent2_defconfig | 1 + configs/kmcoge5ne_defconfig | 1 + configs/kmeter1_defconfig | 1 + configs/kmopti2_defconfig | 1 + configs/kmsupx5_defconfig | 1 + configs/kmtepr2_defconfig | 1 + configs/socrates_defconfig | 1 + configs/tuge1_defconfig | 1 + configs/tuxx1_defconfig | 1 + include/configs/MPC837XERDB.h | 1 - include/configs/MPC8548CDS.h | 1 - include/configs/P1010RDB.h | 1 - include/configs/P2041RDB.h | 1 - include/configs/T102xRDB.h | 1 - include/configs/T104xRDB.h | 1 - include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240RDB.h | 1 - include/configs/gazerbeam.h | 1 - include/configs/km/km-mpc83xx.h | 1 - include/configs/kmcent2.h | 1 - include/configs/p1_p2_rdb_pc.h | 1 - include/configs/socrates.h | 1 - 94 files changed, 82 insertions(+), 16 deletions(-)
diff --git a/arch/powerpc/Kconfig b/arch/powerpc/Kconfig index 3b518c269513..c355a954537d 100644 --- a/arch/powerpc/Kconfig +++ b/arch/powerpc/Kconfig @@ -40,6 +40,10 @@ config HIGH_BATS Enable BATs (block address translation registers) 4-7 on machines that support them.
+config SYS_INIT_RAM_LOCK + bool "Lock some portion of L1 for initial ram stack" + depends on MPC83xx || MPC85xx + source "arch/powerpc/cpu/mpc83xx/Kconfig" source "arch/powerpc/cpu/mpc85xx/Kconfig" source "arch/powerpc/cpu/mpc8xx/Kconfig" diff --git a/arch/powerpc/include/asm/cache.h b/arch/powerpc/include/asm/cache.h index f753ddf799ee..b94faa5408e1 100644 --- a/arch/powerpc/include/asm/cache.h +++ b/arch/powerpc/include/asm/cache.h @@ -45,9 +45,7 @@ extern void invalidate_dcache_range(unsigned long start, unsigned long stop); extern void flush_dcache(void); extern void invalidate_dcache(void); extern void invalidate_icache(void); -#ifdef CONFIG_SYS_INIT_RAM_LOCK extern void unlock_ram_in_cache(void); -#endif /* CONFIG_SYS_INIT_RAM_LOCK */ #endif /* __ASSEMBLY__ */
#if defined(__KERNEL__) && !defined(__ASSEMBLY__) diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 6188e88cc31b..16740c8cb9c5 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -9,6 +9,7 @@ CONFIG_ENV_ADDR=0xFE080000 # CONFIG_SYS_PCI_64BIT is not set CONFIG_MPC83xx=y CONFIG_HIGH_BATS=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_MPC837XERDB=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_FACTOR_5_1=y diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index 50bc6d6bdb29..eb284d2bf727 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -7,6 +7,7 @@ CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds_36b" CONFIG_ENV_ADDR=0xFFF60000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 535b65e5fce9..54d2c840c393 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -7,6 +7,7 @@ CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds" CONFIG_ENV_ADDR=0xFFF60000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index bd865daae325..99b9f6b6962e 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -7,6 +7,7 @@ CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="mpc8548cds" CONFIG_ENV_ADDR=0xFFF60000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index c2e79fda7edd..43c2738d7c8f 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index 0764bda66725..2df781e22b37 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -6,6 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa_36b" CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index 2b3cfa098094..30eb359e55e9 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 7114c0ee5e50..fe37bb63d2de 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index e5064dfd4bc2..2b2c92e69de9 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index d83b61aaaac9..7f3fa16bcebd 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -6,6 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pa" CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index 079dc8477d89..c0fcd935fa27 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index 54a7dc1d8dfe..5f7b1e1bdd6b 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PA=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index bd431c26721c..fa5d305879a7 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 4e482f8bc14b..92f491f133b9 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -6,6 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb_36b" CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index e80e39bfbb37..c85ca4f95401 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 6dd33e302a1b..39a6a217f112 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index de3a96d8f6da..4572abd5280c 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 6637090ecd7b..065020890a3e 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -6,6 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="p1010rdb-pb" CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index f096fbc5e7ae..5f09f994ff67 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index 5da7ccbea23b..f881e4328c32 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P1010RDB_PB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 4f5e89c0e9d4..96224bb349a3 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -13,6 +13,7 @@ CONFIG_TPL_SERIAL=y CONFIG_SPL=y CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 2f8dc8ab8ed6..f2ec6d8315f1 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index b0c60524c8d2..607ae5c9fa6a 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -13,6 +13,7 @@ CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 4ad8ac801582..4411ca006e5e 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -6,6 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc_36b" CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index a82ba02020d9..a5f4acbb3e6e 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -13,6 +13,7 @@ CONFIG_TPL_SERIAL=y CONFIG_SPL=y CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 51fb0e6acee3..8672b663e7b0 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index b6d49d799aff..61d4b55d25e3 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -13,6 +13,7 @@ CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index c553f2ea079f..b04da8a86ff3 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -6,6 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pc" CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PC=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index eb921d993224..47cc14b39942 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -13,6 +13,7 @@ CONFIG_TPL_SERIAL=y CONFIG_SPL=y CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 3197c3487c67..2de84f5d0bf5 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index 80a8273143c6..503123f61c78 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -13,6 +13,7 @@ CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index 31f0c9a1aabc..aa520f85b31e 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -6,6 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="p1020rdb-pd" CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P1020RDB_PD=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index bfa59af3bf0b..3e76317ba3af 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -13,6 +13,7 @@ CONFIG_TPL_SERIAL=y CONFIG_SPL=y CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index fed2a0d542c3..6e288196989a 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 6071fe1456cd..64199f279239 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -13,6 +13,7 @@ CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 51200f85fe26..512271010fd4 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -6,6 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc_36b" CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 4e1a91268d35..0fad104d3cd3 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -13,6 +13,7 @@ CONFIG_TPL_SERIAL=y CONFIG_SPL=y CONFIG_TPL_MAX_SIZE=0x20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index d6e1903a5a45..6aaba451d386 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index b048e44eef37..f08e939c9974 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -13,6 +13,7 @@ CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 21b473c61cf1..2a96c8e19250 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -6,6 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="p2020rdb-pc" CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_P2020RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index b1c6f9dd5ceb..26211f74683b 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -5,6 +5,7 @@ CONFIG_ENV_SIZE=0x20000 CONFIG_ENV_OFFSET=0xE0000 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 66ce4a55e793..ae0ba5494506 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -5,6 +5,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_ENV_OFFSET=0xCF400 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index e82b6289a641..69cdff4e6ca9 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -6,6 +6,7 @@ CONFIG_ENV_OFFSET=0x100000 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index a5f7a08bcfad..06a5b1f5b9e5 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -6,6 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="p2041rdb" CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_P2041RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index 1c8944e89b87..a0da36197efb 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T1024RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 8ee3c2eb44c4..442e7e53b3e4 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T1024RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 374f222d03ba..3985a9443e86 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T1024RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index d354fb889bb7..a0d36467bd47 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -6,6 +6,7 @@ CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="t1024rdb" CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T1024RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 438ffbd46f03..1c4ab7bf074e 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T1042D4RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index 0101620d962c..f71ade16137d 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T1042D4RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index dca2dd019997..a32e86df705a 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -13,6 +13,7 @@ CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T1042D4RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 3b124af21c26..c1749a1cb903 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -5,6 +5,7 @@ CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="t1042d4rdb" CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T1042D4RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index aa21c367009e..beb8817b656f 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T2080QDS=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index bdb3c5d4d7d2..bb5d05c7e5b2 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T2080QDS=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index 55ea54b146df..a33097391d18 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -3,6 +3,7 @@ CONFIG_SYS_TEXT_BASE=0xEFF40000 CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T2080QDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 6c2671bdb7e3..2fb1d7eb29ee 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -13,6 +13,7 @@ CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T2080QDS=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index f3c0b93dabd8..252017f73334 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -4,6 +4,7 @@ CONFIG_ENV_SIZE=0x2000 CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_ENV_ADDR=0xFFE20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T2080QDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index 8b966cc22ef1..f9a105bc3697 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -5,6 +5,7 @@ CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="t2080qds" CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T2080QDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index 2a278ac7c8dd..df4deafc1ab1 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T2080RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index cc26ade01f22..534770b43ec5 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T2080RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index d8216b00dfa6..278acb87719e 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -13,6 +13,7 @@ CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T2080RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index afeba15ea336..5422214f198a 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -5,6 +5,7 @@ CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T2080RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig index 6d43071143f5..75dce6042f22 100644 --- a/configs/T2080RDB_revD_NAND_defconfig +++ b/configs/T2080RDB_revD_NAND_defconfig @@ -10,6 +10,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T2080RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig index 03254fc11737..7d67f728b4c8 100644 --- a/configs/T2080RDB_revD_SDCARD_defconfig +++ b/configs/T2080RDB_revD_SDCARD_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T2080RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig index 1fab5d9abf11..0f7658b88890 100644 --- a/configs/T2080RDB_revD_SPIFLASH_defconfig +++ b/configs/T2080RDB_revD_SPIFLASH_defconfig @@ -13,6 +13,7 @@ CONFIG_SPL=y CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T2080RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig index fbfd4a428f79..f9c85dfccfdd 100644 --- a/configs/T2080RDB_revD_defconfig +++ b/configs/T2080RDB_revD_defconfig @@ -5,6 +5,7 @@ CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="t2080rdb" CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T2080RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index bff883901d0c..59ecbf43816c 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T4240RDB=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_BOOK3E_HV=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index 361769d9c22a..3735d82a51ff 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -5,6 +5,7 @@ CONFIG_ENV_SECT_SIZE=0x20000 CONFIG_DEFAULT_DEVICE_TREE="t4240rdb" CONFIG_ENV_ADDR=0xEFF20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_T4240RDB=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig index a432c0515cfb..e3b1b0e8272e 100644 --- a/configs/gazerbeam_defconfig +++ b/configs/gazerbeam_defconfig @@ -10,6 +10,7 @@ CONFIG_IDENT_STRING=" gazerbeam 0.01" CONFIG_SYS_CLK_FREQ=33333333 CONFIG_ENV_ADDR=0xFE080000 CONFIG_MPC83xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_GAZERBEAM=y CONFIG_SYSTEM_PLL_VCO_DIV_2=y CONFIG_SYSTEM_PLL_FACTOR_4_1=y diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig index a13d799f3674..c9fcc963bfb7 100644 --- a/configs/kmcent2_defconfig +++ b/configs/kmcent2_defconfig @@ -8,6 +8,7 @@ CONFIG_SYS_BOOTCOUNT_ADDR=0xFB000020 CONFIG_SYS_CLK_FREQ=66666666 CONFIG_ENV_ADDR=0xebf20000 CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_KMCENT2=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 34ab31565ca4..99d92752db9c 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ENV_ADDR=0xF00C0000 CONFIG_MPC83xx=y CONFIG_HIGH_BATS=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_KMCOGE5NE=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_VCO_DIV_4=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 98f23dbbf175..96d4f10d3641 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ENV_ADDR=0xF00C0000 CONFIG_MPC83xx=y CONFIG_HIGH_BATS=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_KMETER1=y CONFIG_DDR_MC_CLOCK_MODE_1_1=y CONFIG_SYSTEM_PLL_VCO_DIV_4=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index 6a6f20890a76..a764de67536c 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ENV_ADDR=0xF00C0000 CONFIG_MPC83xx=y CONFIG_HIGH_BATS=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_KMOPTI2=y CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index d251eba0d04b..c521c94ebcf0 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ENV_ADDR=0xF00C0000 CONFIG_MPC83xx=y CONFIG_HIGH_BATS=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_KMSUPX5=y CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index 5bb3d9c1160a..e587670bea12 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ENV_ADDR=0xF00C0000 CONFIG_MPC83xx=y CONFIG_HIGH_BATS=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_KMTEPR2=y CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index bb73f28b36b2..0da3a4379275 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -7,6 +7,7 @@ CONFIG_DEFAULT_DEVICE_TREE="socrates" CONFIG_ENV_ADDR=0xFFF40000 # CONFIG_SYS_PCI_64BIT is not set CONFIG_MPC85xx=y +CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_SOCRATES=y CONFIG_ENABLE_36BIT_PHYS=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 0d1c99c62c50..0b8a50003300 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ENV_ADDR=0xF00C0000 CONFIG_MPC83xx=y CONFIG_HIGH_BATS=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_TUGE1=y CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 3fe731fd188a..c1548aa5cf1e 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ENV_ADDR=0xF00C0000 CONFIG_MPC83xx=y CONFIG_HIGH_BATS=y +CONFIG_SYS_INIT_RAM_LOCK=y CONFIG_TARGET_TUXX1=y CONFIG_CORE_PLL_RATIO_25_1=y CONFIG_QUICC_MULT_FACTOR_3=y diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index c2f4f2bee2c0..dd5c26d7e0d9 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -131,7 +131,6 @@ /* * Initial RAM Base Address Setup */ -#define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index eb7a8351794b..bce4faca9fe4 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -229,7 +229,6 @@ #define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR #endif
-#define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 8492a64d4392..bf9227a3c204 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -297,7 +297,6 @@ extern unsigned long get_sdram_size(void); FTIM2_GPCM_TWP(0x1f)) #define CONFIG_SYS_CS3_FTIM3 0x0
-#define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 /* End of used area in RAM */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 925720d23409..0bd3bac97e43 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -145,7 +145,6 @@
/* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* Initial L1 address */ #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index e0aa2b9598cf..7630be245c1f 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -279,7 +279,6 @@
/* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 918aabcbb5c0..19e3dfbfdb12 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -255,7 +255,6 @@
/* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index e852fc4cdc8f..7c83423f99ff 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -259,7 +259,6 @@
/* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 68cf13581ade..78ff50196c2f 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -219,7 +219,6 @@
/* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index bba82f1e0cd3..53641fad543a 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -75,7 +75,6 @@
/* define to use L1 as initial stack */ #define CONFIG_L1_INIT_RAM -#define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h index e592dc44e4d7..771a30106c1b 100644 --- a/include/configs/gazerbeam.h +++ b/include/configs/gazerbeam.h @@ -30,7 +30,6 @@ /* * Initial RAM Base Address Setup */ -#define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* Size of used area in RAM */
diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index 04192d86b700..61c713459543 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -31,7 +31,6 @@ /* * Initial RAM Base Address Setup */ -#define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xE6000000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x1000 /* End of used area in RAM */ /* diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 1b1900179ef6..3def00164748 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -314,7 +314,6 @@ #define CONFIG_HWCONFIG
/* define to use L1 as initial stack */ -#define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xfdd00000 /* Initial L1 address */ #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW 0xfe03c000 diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index d201c72a6c45..845578d6990b 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -245,7 +245,6 @@ #endif #endif /* CONFIG_NAND_FSL_ELBC */
-#define CONFIG_SYS_INIT_RAM_LOCK #define CONFIG_SYS_INIT_RAM_ADDR 0xffd00000 /* stack in RAM */ #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_INIT_RAM_ADDR_PHYS_HIGH 0xf diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 762ba44542d3..fc00931e0ae1 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -92,7 +92,6 @@ #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ #define CONFIG_SYS_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/
-#define CONFIG_SYS_INIT_RAM_LOCK 1 #define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size used area in RAM*/
On Fri, 28 Oct 2022 at 18:28, Tom Rini trini@konsulko.com wrote:
This converts the following to Kconfig: CONFIG_SYS_INIT_RAM_LOCK
Signed-off-by: Tom Rini trini@konsulko.com
Reviewed-by: Simon Glass sjg@chromium.org
This header is unreferenced, remove.
Signed-off-by: Tom Rini trini@konsulko.com --- include/w83c553f.h | 161 --------------------------------------------- 1 file changed, 161 deletions(-) delete mode 100644 include/w83c553f.h
diff --git a/include/w83c553f.h b/include/w83c553f.h deleted file mode 100644 index 2403e3401a6f..000000000000 --- a/include/w83c553f.h +++ /dev/null @@ -1,161 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2000 - * Rob Taylor, Flying Pig Systems. robt@flyingpig.com. - */ - - /* winbond access routines and defines*/ - -/* from the winbond data sheet - - The W83C553F SIO controller with PCI arbiter is a multi-function PCI device. - Function 0 is the ISA bridge, and Function 1 is the bus master IDE controller. -*/ - -/*ISA bridge configuration space*/ - -#define W83C553F_VID 0x10AD -#define W83C553F_DID 0x0565 - -#define WINBOND_PCICONTR 0x40 /*pci control reg*/ -#define WINBOND_SGBAR 0x41 /*scatter/gather base address reg*/ -#define WINBOND_LBCR 0x42 /*Line Buffer Control reg*/ -#define WINBOND_IDEIRCR 0x43 /*IDE Interrupt Routing Control Reg*/ -#define WINBOND_PCIIRCR 0x44 /*PCI Interrupt Routing Control Reg*/ -#define WINBOND_BTBAR 0x46 /*BIOS Timer Base Address Register*/ -#define WINBOND_IPADCR 0x48 /*ISA to PCI Address Decoder Control Register*/ -#define WINBOND_IRADCR 0x49 /*ISA ROM Address Decoder Control Register*/ -#define WINBOND_IPMHSAR 0x4a /*ISA to PCI Memory Hole STart Address Register*/ -#define WINBOND_IPMHSR 0x4b /*ISA to PCI Memory Hols Size Register*/ -#define WINBOND_CDR 0x4c /*Clock Divisor Register*/ -#define WINBOND_CSCR 0x4d /*Chip Select Control Register*/ -#define WINBOND_ATSCR 0x4e /*AT System Control register*/ -#define WINBOND_ATBCR 0x4f /*AT Bus ControL Register*/ -#define WINBOND_IRQBEE0R 0x60 /*IRQ Break Event Enable 0 Register*/ -#define WINBOND_IRQBEE1R 0x61 /*IRQ Break Event Enable 1 Register*/ -#define WINBOND_ABEER 0x62 /*Additional Break Event Enable Register*/ -#define WINBOND_DMABEER 0x63 /*DMA Break Event Enable Register*/ - -#define WINDOND_IDECSR 0x40 /*IDE Control/Status Register, Function 1*/ - -#define IPADCR_MBE512 0x1 -#define IPADCR_MBE640 0x2 -#define IPADCR_IPATOM4 0x10 -#define IPADCR_IPATOM5 0x20 -#define IPADCR_IPATOM6 0x40 -#define IPADCR_IPATOM7 0x80 - -#define CSCR_UBIOSCSE 0x10 -#define CSCR_BIOSWP 0x20 - -#define IDECSR_P0EN 0x01 -#define IDECSR_P0F16 0x02 -#define IDECSR_P1EN 0x10 -#define IDECSR_P1F16 0x20 -#define IDECSR_LEGIRQ 0x800 - -/* - * Interrupt controller - */ -#define W83C553F_PIC1_ICW1 CONFIG_SYS_ISA_IO + 0x20 -#define W83C553F_PIC1_ICW2 CONFIG_SYS_ISA_IO + 0x21 -#define W83C553F_PIC1_ICW3 CONFIG_SYS_ISA_IO + 0x21 -#define W83C553F_PIC1_ICW4 CONFIG_SYS_ISA_IO + 0x21 -#define W83C553F_PIC1_OCW1 CONFIG_SYS_ISA_IO + 0x21 -#define W83C553F_PIC1_OCW2 CONFIG_SYS_ISA_IO + 0x20 -#define W83C553F_PIC1_OCW3 CONFIG_SYS_ISA_IO + 0x20 -#define W83C553F_PIC1_ELC CONFIG_SYS_ISA_IO + 0x4D0 -#define W83C553F_PIC2_ICW1 CONFIG_SYS_ISA_IO + 0xA0 -#define W83C553F_PIC2_ICW2 CONFIG_SYS_ISA_IO + 0xA1 -#define W83C553F_PIC2_ICW3 CONFIG_SYS_ISA_IO + 0xA1 -#define W83C553F_PIC2_ICW4 CONFIG_SYS_ISA_IO + 0xA1 -#define W83C553F_PIC2_OCW1 CONFIG_SYS_ISA_IO + 0xA1 -#define W83C553F_PIC2_OCW2 CONFIG_SYS_ISA_IO + 0xA0 -#define W83C553F_PIC2_OCW3 CONFIG_SYS_ISA_IO + 0xA0 -#define W83C553F_PIC2_ELC CONFIG_SYS_ISA_IO + 0x4D1 - -#define W83C553F_TMR1_CMOD CONFIG_SYS_ISA_IO + 0x43 - -/* - * DMA controller - */ -#define W83C553F_DMA1 CONFIG_SYS_ISA_IO + 0x000 /* channel 0 - 3 */ -#define W83C553F_DMA2 CONFIG_SYS_ISA_IO + 0x0C0 /* channel 4 - 7 */ - -/* command/status register bit definitions */ - -#define W83C553F_CS_COM_DACKAL (1<<7) /* DACK# assert level */ -#define W83C553F_CS_COM_DREQSAL (1<<6) /* DREQ sense assert level */ -#define W83C553F_CS_COM_GAP (1<<4) /* group arbitration priority */ -#define W83C553F_CS_COM_CGE (1<<2) /* channel group enable */ - -#define W83C553F_CS_STAT_CH0REQ (1<<4) /* channel 0 (4) DREQ status */ -#define W83C553F_CS_STAT_CH1REQ (1<<5) /* channel 1 (5) DREQ status */ -#define W83C553F_CS_STAT_CH2REQ (1<<6) /* channel 2 (6) DREQ status */ -#define W83C553F_CS_STAT_CH3REQ (1<<7) /* channel 3 (7) DREQ status */ - -#define W83C553F_CS_STAT_CH0TC (1<<0) /* channel 0 (4) TC status */ -#define W83C553F_CS_STAT_CH1TC (1<<1) /* channel 1 (5) TC status */ -#define W83C553F_CS_STAT_CH2TC (1<<2) /* channel 2 (6) TC status */ -#define W83C553F_CS_STAT_CH3TC (1<<3) /* channel 3 (7) TC status */ - -/* mode register bit definitions */ - -#define W83C553F_MODE_TM_DEMAND (0<<6) /* transfer mode - demand */ -#define W83C553F_MODE_TM_SINGLE (1<<6) /* transfer mode - single */ -#define W83C553F_MODE_TM_BLOCK (2<<6) /* transfer mode - block */ -#define W83C553F_MODE_TM_CASCADE (3<<6) /* transfer mode - cascade */ -#define W83C553F_MODE_ADDRDEC (1<<5) /* address increment/decrement select */ -#define W83C553F_MODE_AUTOINIT (1<<4) /* autoinitialize enable */ -#define W83C553F_MODE_TT_VERIFY (0<<2) /* transfer type - verify */ -#define W83C553F_MODE_TT_WRITE (1<<2) /* transfer type - write */ -#define W83C553F_MODE_TT_READ (2<<2) /* transfer type - read */ -#define W83C553F_MODE_TT_ILLEGAL (3<<2) /* transfer type - illegal */ -#define W83C553F_MODE_CH0SEL (0<<0) /* channel 0 (4) select */ -#define W83C553F_MODE_CH1SEL (1<<0) /* channel 1 (5) select */ -#define W83C553F_MODE_CH2SEL (2<<0) /* channel 2 (6) select */ -#define W83C553F_MODE_CH3SEL (3<<0) /* channel 3 (7) select */ - -/* request register bit definitions */ - -#define W83C553F_REQ_CHSERREQ (1<<2) /* channel service request */ -#define W83C553F_REQ_CH0SEL (0<<0) /* channel 0 (4) select */ -#define W83C553F_REQ_CH1SEL (1<<0) /* channel 1 (5) select */ -#define W83C553F_REQ_CH2SEL (2<<0) /* channel 2 (6) select */ -#define W83C553F_REQ_CH3SEL (3<<0) /* channel 3 (7) select */ - -/* write single mask bit register bit definitions */ - -#define W83C553F_WSMB_CHMASKSEL (1<<2) /* channel mask select */ -#define W83C553F_WSMB_CH0SEL (0<<0) /* channel 0 (4) select */ -#define W83C553F_WSMB_CH1SEL (1<<0) /* channel 1 (5) select */ -#define W83C553F_WSMB_CH2SEL (2<<0) /* channel 2 (6) select */ -#define W83C553F_WSMB_CH3SEL (3<<0) /* channel 3 (7) select */ - -/* read/write all mask bits register bit definitions */ - -#define W83C553F_RWAMB_CH0MASK (1<<0) /* channel 0 (4) mask */ -#define W83C553F_RWAMB_CH1MASK (1<<1) /* channel 1 (5) mask */ -#define W83C553F_RWAMB_CH2MASK (1<<2) /* channel 2 (6) mask */ -#define W83C553F_RWAMB_CH3MASK (1<<3) /* channel 3 (7) mask */ - -/* typedefs */ - -#define W83C553F_DMA1_CS 0x8 -#define W83C553F_DMA1_WR 0x9 -#define W83C553F_DMA1_WSMB 0xA -#define W83C553F_DMA1_WM 0xB -#define W83C553F_DMA1_CBP 0xC -#define W83C553F_DMA1_MC 0xD -#define W83C553F_DMA1_CM 0xE -#define W83C553F_DMA1_RWAMB 0xF - -#define W83C553F_DMA2_CS 0x10 -#define W83C553F_DMA2_WR 0x12 -#define W83C553F_DMA2_WSMB 0x14 -#define W83C553F_DMA2_WM 0x16 -#define W83C553F_DMA2_CBP 0x18 -#define W83C553F_DMA2_MC 0x1A -#define W83C553F_DMA2_CM 0x1C -#define W83C553F_DMA2_RWAMB 0x1E - -void initialise_w83c553f(void);
On Fri, 28 Oct 2022 at 18:28, Tom Rini trini@konsulko.com wrote:
This header is unreferenced, remove.
Signed-off-by: Tom Rini trini@konsulko.com
include/w83c553f.h | 161 --------------------------------------------- 1 file changed, 161 deletions(-) delete mode 100644 include/w83c553f.h
Reviewed-by: Simon Glass sjg@chromium.org
This converts the following to Kconfig: CONFIG_SYS_INTERLAKEN CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS
Signed-off-by: Tom Rini trini@konsulko.com --- drivers/rtc/mc146818.c | 2 +- include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240RDB.h | 1 - include/configs/edison.h | 3 --- include/configs/malta.h | 2 -- include/configs/x86-common.h | 6 ------ include/mk48t59.h | 4 ++-- 8 files changed, 3 insertions(+), 17 deletions(-)
diff --git a/drivers/rtc/mc146818.c b/drivers/rtc/mc146818.c index 71f96e282e82..122691b97842 100644 --- a/drivers/rtc/mc146818.c +++ b/drivers/rtc/mc146818.c @@ -22,7 +22,7 @@ /* Set this to 1 to clear the CMOS RAM */ #define CLEAR_CMOS 0
-#define RTC_PORT_MC146818 CONFIG_SYS_ISA_IO_BASE_ADDRESS + 0x70 +#define RTC_PORT_MC146818 0x70 #define RTC_SECONDS 0x00 #define RTC_SECONDS_ALARM 0x01 #define RTC_MINUTES 0x02 diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 7c83423f99ff..6700560123b7 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -405,7 +405,6 @@ #define CONFIG_SYS_PMAN #define CONFIG_SYS_DPAA_DCE #define CONFIG_SYS_DPAA_RMAN /* RMan */ -#define CONFIG_SYS_INTERLAKEN #endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 78ff50196c2f..4de4a72999e9 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -359,7 +359,6 @@ #define CONFIG_SYS_PMAN #define CONFIG_SYS_DPAA_DCE #define CONFIG_SYS_DPAA_RMAN /* RMan */ -#define CONFIG_SYS_INTERLAKEN #endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 53641fad543a..dc507473b259 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -366,7 +366,6 @@ #define CONFIG_SYS_PMAN #define CONFIG_SYS_DPAA_DCE #define CONFIG_SYS_DPAA_RMAN -#define CONFIG_SYS_INTERLAKEN #endif /* CONFIG_NOBQFMAN */
#ifdef CONFIG_SYS_DPAA_FMAN diff --git a/include/configs/edison.h b/include/configs/edison.h index 34536ecf8505..c71ef25233bd 100644 --- a/include/configs/edison.h +++ b/include/configs/edison.h @@ -14,7 +14,4 @@
#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
-/* RTC */ -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 - #endif diff --git a/include/configs/malta.h b/include/configs/malta.h index 5a42ceef2121..8ffd1f372044 100644 --- a/include/configs/malta.h +++ b/include/configs/malta.h @@ -13,8 +13,6 @@
#define CONFIG_MEMSIZE_IN_BYTES
-#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 - /* * CPU Configuration */ diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index 42b2cb2fc85a..8e22d6e5d876 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -18,12 +18,6 @@ /* Generic TPM interfaced through LPC bus */ #define CONFIG_TPM_TIS_BASE_ADDRESS 0xfed40000
-/*----------------------------------------------------------------------- - * Real Time Clock Configuration - */ -#define CONFIG_SYS_ISA_IO_BASE_ADDRESS 0 -#define CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS - /*----------------------------------------------------------------------- * Serial Configuration */ diff --git a/include/mk48t59.h b/include/mk48t59.h index 5d863ef94160..f95d349c17fb 100644 --- a/include/mk48t59.h +++ b/include/mk48t59.h @@ -11,9 +11,9 @@
#if defined(CONFIG_RTC_MK48T59) && defined(CONFIG_CMD_DATE)
-#define RTC_PORT_ADDR0 CONFIG_SYS_ISA_IO + 0x70 +#define RTC_PORT_ADDR0 0x70 #define RTC_PORT_ADDR1 RTC_PORT_ADDR0 + 0x1 -#define RTC_PORT_DATA CONFIG_SYS_ISA_IO + 0x76 +#define RTC_PORT_DATA 0x76
/* RTC Offsets */ #define RTC_SECONDS 0x1FF9
Hi Tom.
On Fri, 28 Oct 2022 at 18:27, Tom Rini trini@konsulko.com wrote:
This converts the following to Kconfig: CONFIG_SYS_INTERLAKEN CONFIG_SYS_ISA_IO CONFIG_SYS_ISA_IO_BASE_ADDRESS
Signed-off-by: Tom Rini trini@konsulko.com
drivers/rtc/mc146818.c | 2 +- include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240RDB.h | 1 - include/configs/edison.h | 3 --- include/configs/malta.h | 2 -- include/configs/x86-common.h | 6 ------ include/mk48t59.h | 4 ++-- 8 files changed, 3 insertions(+), 17 deletions(-)
I don't actually see any new Kconfig options, but from the look of the patch, it doesn't matter.
Reviewed-by: Simon Glass sjg@chromium.org
Regards, Simon
This removes the following symbols: CONFIG_RTC_MCFRRTC CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_JFFS2_FIRST_SECTOR CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_LBC_CACHE_BASE CONFIG_SYS_LIME_SIZE CONFIG_SYS_MAMR CONFIG_SYS_MCFRRTC_BASE CONFIG_SYS_MONITOR_SEC
Signed-off-by: Tom Rini trini@konsulko.com --- README | 8 -------- doc/README.JFFS2 | 10 ---------- include/configs/astro_mcf5373l.h | 11 ----------- include/configs/at91sam9263ek.h | 1 - include/configs/socrates.h | 3 --- include/configs/stmark2.h | 4 ---- include/configs/tuxx1.h | 4 ---- 7 files changed, 41 deletions(-)
diff --git a/README b/README index 92ad191ae76d..0e01176d4f65 100644 --- a/README +++ b/README @@ -762,11 +762,6 @@ The following options need to be configured: entering dfuMANIFEST state. Host waits this timeout, before sending again an USB request to the device.
-- Journaling Flash filesystem support: - CONFIG_SYS_JFFS2_FIRST_SECTOR, - CONFIG_SYS_JFFS2_FIRST_BANK, CONFIG_SYS_JFFS2_NUM_BANKS - Define these for a default partition on a NOR device - - Keyboard Support: See Kconfig help for available keyboard drivers.
@@ -1814,9 +1809,6 @@ Low Level (hardware related) configuration options: - CONFIG_SYS_OR_TIMING_SDRAM: SDRAM timing
-- CONFIG_SYS_MAMR_PTA: - periodic timer for refresh - - CONFIG_SYS_SRIO: Chip has SRIO or not
diff --git a/doc/README.JFFS2 b/doc/README.JFFS2 index 0245da0488fb..fddefb174690 100644 --- a/doc/README.JFFS2 +++ b/doc/README.JFFS2 @@ -21,16 +21,6 @@ Sorting is done while inserting into the fragment list, which is more or less a bubble sort. That algorithm is known to be O(n^2), thus you should really consider if you can avoid it!
- -There only one way for JFFS2 to find the disk. It uses the flash_info -structure to find the start of a JFFS2 disk (called partition in the code) -and you can change where the partition is with two defines. - -CONFIG_SYS_JFFS2_FIRST_BANK - defined the first flash bank to use - -CONFIG_SYS_JFFS2_FIRST_SECTOR - defines the first sector to use ---
TODO. diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index adfadd7c6d72..c79f9ca8f0f4 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -46,9 +46,6 @@ */ #ifdef CONFIG_RAM #define CONFIG_MONITOR_IS_IN_RAM -#define ENABLE_JFFS 0 -#else -#define ENABLE_JFFS 1 #endif
/* I2C */ @@ -210,14 +207,6 @@ . = DEFINED(env_offset) ? env_offset : .; \ env/embedded.o(.text*)
-#if ENABLE_JFFS -/* JFFS Partition offset set */ -#define CONFIG_SYS_JFFS2_FIRST_BANK 0 -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 -/* 512k reserved for u-boot */ -#define CONFIG_SYS_JFFS2_FIRST_SECTOR 0x40 -#endif - /* Cache Configuration */
#define ICACHE_STATUS (CONFIG_SYS_INIT_RAM_ADDR + \ diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index 8c6d1cd1d9d4..4d32e55c642e 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -41,7 +41,6 @@ #define PHYS_FLASH_1 0x10000000 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_SEC 1:0-3 #define CONFIG_SYS_MONITOR_LEN (256 << 10)
/* Address and size of Primary Environment Sector */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index fc00931e0ae1..c75991badab4 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -78,8 +78,6 @@ /* * Flash on the LocalBus */ -#define CONFIG_SYS_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ - #define CONFIG_SYS_FLASH0 0xFE000000 #define CONFIG_SYS_FLASH1 0xFC000000 #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH1, CONFIG_SYS_FLASH0 } @@ -108,7 +106,6 @@
/* LIME GDC */ #define CONFIG_SYS_LIME_BASE 0xc8000000 -#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
/* * General PCI diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index d8a334868f31..8167d250f27f 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -34,10 +34,6 @@ "sf write ${loadaddr} 0x00800000 ${filesize}\0" \ ""
-/* Realtime clock */ -#define CONFIG_RTC_MCFRRTC -#define CONFIG_SYS_MCFRRTC_BASE 0xFC0A8000 - #define CONFIG_SYS_SBFHDR_SIZE 0x7
/* Input, PCI, Flexbus, and VCO */ diff --git a/include/configs/tuxx1.h b/include/configs/tuxx1.h index f5a9f1284a3d..7eed31c35f03 100644 --- a/include/configs/tuxx1.h +++ b/include/configs/tuxx1.h @@ -31,8 +31,4 @@ #include "km/km-mpc83xx.h" #include "km/km-mpc832x.h"
-#define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ - 0x0000c000 | \ - MxMR_WLFx_2X) - #endif /* __CONFIG_H */
On Fri, 28 Oct 2022 at 18:27, Tom Rini trini@konsulko.com wrote:
This removes the following symbols: CONFIG_RTC_MCFRRTC CONFIG_SYS_JFFS2_FIRST_BANK CONFIG_SYS_JFFS2_FIRST_SECTOR CONFIG_SYS_JFFS2_NUM_BANKS CONFIG_SYS_LBC_CACHE_BASE CONFIG_SYS_LIME_SIZE CONFIG_SYS_MAMR CONFIG_SYS_MCFRRTC_BASE CONFIG_SYS_MONITOR_SEC
Signed-off-by: Tom Rini trini@konsulko.com
README | 8 -------- doc/README.JFFS2 | 10 ---------- include/configs/astro_mcf5373l.h | 11 ----------- include/configs/at91sam9263ek.h | 1 - include/configs/socrates.h | 3 --- include/configs/stmark2.h | 4 ---- include/configs/tuxx1.h | 4 ---- 7 files changed, 41 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
Move the symbol SYS_JFFS2_SORT_FRAGMENTS to Kconfig and use the only remaining part of doc/README.JFFS2 that is still relevant and useful to the help for this option.
Signed-off-by: Tom Rini trini@konsulko.com --- doc/README.JFFS2 | 30 ------------------------------ fs/jffs2/Kconfig | 12 ++++++++++++ 2 files changed, 12 insertions(+), 30 deletions(-) delete mode 100644 doc/README.JFFS2
diff --git a/doc/README.JFFS2 b/doc/README.JFFS2 deleted file mode 100644 index fddefb174690..000000000000 --- a/doc/README.JFFS2 +++ /dev/null @@ -1,30 +0,0 @@ -JFFS2 options and usage. ------------------------ - -JFFS2 in U-Boot is a read only implementation of the file system in -Linux with the same name. To use JFFS2 define CONFIG_CMD_JFFS2. - -The module adds three new commands. -fsload - load binary file from a file system image -fsinfo - print information about file systems -ls - list files in a directory -chpart - change active partition - -If you do now need the commands, you can enable the filesystem separately -with CONFIG_FS_JFFS2 and call the jffs2 functions yourself. - -If you boot from a partition which is mounted writable, and you -update your boot environment by replacing single files on that -partition, you should also define CONFIG_SYS_JFFS2_SORT_FRAGMENTS. Scanning -the JFFS2 filesystem takes *much* longer with this feature, though. -Sorting is done while inserting into the fragment list, which is -more or less a bubble sort. That algorithm is known to be O(n^2), -thus you should really consider if you can avoid it! - ---- - -TODO. - - Remove the assumption that JFFS can dereference a pointer - into the disk. The current code do not work with memory holes - or hardware with a sliding window (PCMCIA). diff --git a/fs/jffs2/Kconfig b/fs/jffs2/Kconfig index 0e79c3409062..3bf01cd03137 100644 --- a/fs/jffs2/Kconfig +++ b/fs/jffs2/Kconfig @@ -17,3 +17,15 @@ config JFFS2_NAND depends on FS_JFFS2 help Enable support for NAND flash as the backing store for JFFS2. + +config SYS_JFFS2_SORT_FRAGMENTS + bool "Enable JFFS2 sorting of filesystem fragments (SLOW!)" + depends on FS_JFFS2 + help + If you boot from a partition which is mounted writable, and you + update your boot environment by replacing single files on that + partition, you should also define CONFIG_SYS_JFFS2_SORT_FRAGMENTS. + Scanning the JFFS2 filesystem takes *much* longer with this feature, + though. Sorting is done while inserting into the fragment list, + which is more or less a bubble sort. That algorithm is known to be + O(n^2), thus you should really consider if you can avoid it!
On Fri, 28 Oct 2022 at 18:28, Tom Rini trini@konsulko.com wrote:
Move the symbol SYS_JFFS2_SORT_FRAGMENTS to Kconfig and use the only remaining part of doc/README.JFFS2 that is still relevant and useful to the help for this option.
Signed-off-by: Tom Rini trini@konsulko.com
doc/README.JFFS2 | 30 ------------------------------ fs/jffs2/Kconfig | 12 ++++++++++++ 2 files changed, 12 insertions(+), 30 deletions(-) delete mode 100644 doc/README.JFFS2
Reviewed-by: Simon Glass sjg@chromium.org
Introduce two options, one for each observed L2 cache size, and have the size select'd as needed.
Signed-off-by: Tom Rini trini@konsulko.com --- arch/powerpc/cpu/mpc85xx/Kconfig | 16 ++++++++++++++++ include/configs/P1010RDB.h | 3 --- include/configs/p1_p2_rdb_pc.h | 3 --- 3 files changed, 16 insertions(+), 6 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 27f069a1fb37..7abfe26d35dd 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -113,6 +113,7 @@ config TARGET_P1010RDB_PA select BOARD_LATE_INIT if CHAIN_OF_TRUST select SUPPORT_SPL select SUPPORT_TPL + select SYS_L2_SIZE_256KB imply CMD_EEPROM imply CMD_SATA imply PANIC_HANG @@ -123,6 +124,7 @@ config TARGET_P1010RDB_PB select BOARD_LATE_INIT if CHAIN_OF_TRUST select SUPPORT_SPL select SUPPORT_TPL + select SYS_L2_SIZE_256KB imply CMD_EEPROM imply CMD_SATA imply PANIC_HANG @@ -132,6 +134,7 @@ config TARGET_P1020RDB_PC select SUPPORT_SPL select SUPPORT_TPL select ARCH_P1020 + select SYS_L2_SIZE_256KB imply CMD_EEPROM imply CMD_SATA imply PANIC_HANG @@ -141,6 +144,7 @@ config TARGET_P1020RDB_PD select SUPPORT_SPL select SUPPORT_TPL select ARCH_P1020 + select SYS_L2_SIZE_256KB imply CMD_EEPROM imply CMD_SATA imply PANIC_HANG @@ -150,6 +154,7 @@ config TARGET_P2020RDB select SUPPORT_SPL select SUPPORT_TPL select ARCH_P2020 + select SYS_L2_SIZE_512KB imply CMD_EEPROM imply CMD_SATA imply SATA_SIL @@ -1277,6 +1282,17 @@ config SYS_ETVPE_CLK default 1 endif
+config SYS_L2_SIZE_256KB + bool + +config SYS_L2_SIZE_512KB + bool + +config SYS_L2_SIZE + int + default 262144 if SYS_L2_SIZE_256KB + default 524288 if SYS_L2_SIZE_512KB + config BACKSIDE_L2_CACHE bool
diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index bf9227a3c204..06188cac44f2 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -311,18 +311,15 @@ extern unsigned long get_sdram_size(void); #if defined(CONFIG_SDCARD) || defined(CONFIG_SPIFLASH) #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #elif defined(CONFIG_MTD_RAW_NAND) #ifdef CONFIG_TPL_BUILD #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #else #define CONFIG_SYS_INIT_L2_ADDR 0xD0000000 #define CONFIG_SYS_INIT_L2_ADDR_PHYS CONFIG_SYS_INIT_L2_ADDR -#define CONFIG_SYS_L2_SIZE (256 << 10) #define CONFIG_SYS_INIT_L2_END (CONFIG_SYS_INIT_L2_ADDR + CONFIG_SYS_L2_SIZE) #endif #endif diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 845578d6990b..e632d852ed54 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -27,7 +27,6 @@ #define __SW_BOOT_NOR_BANK_UP 0x5c /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */ #define __SW_BOOT_NOR_BANK_LO 0x5e /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */ #define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */ -#define CONFIG_SYS_L2_SIZE (256 << 10) #endif
/* @@ -58,7 +57,6 @@ #define __SW_BOOT_NOR_BANK_UP 0x64 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */ #define __SW_BOOT_NOR_BANK_LO 0x66 /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */ #define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */ -#define CONFIG_SYS_L2_SIZE (256 << 10) /* * Dynamic MTD Partition support with mtdparts */ @@ -79,7 +77,6 @@ #define __SW_BOOT_NOR_BANK_UP 0xc8 /* (__SW_BOOT_NOR | __SW_NOR_BANK_UP) */ #define __SW_BOOT_NOR_BANK_LO 0xca /* (__SW_BOOT_NOR | __SW_NOR_BANK_LO) */ #define __SW_BOOT_NOR_BANK_MASK 0x01 /* (__SW_BOOT_MASK & __SW_NOR_BANK_MASK) */ -#define CONFIG_SYS_L2_SIZE (512 << 10) /* * Dynamic MTD Partition support with mtdparts */
On Fri, 28 Oct 2022 at 18:28, Tom Rini trini@konsulko.com wrote:
Introduce two options, one for each observed L2 cache size, and have the size select'd as needed.
Signed-off-by: Tom Rini trini@konsulko.com
arch/powerpc/cpu/mpc85xx/Kconfig | 16 ++++++++++++++++ include/configs/P1010RDB.h | 3 --- include/configs/p1_p2_rdb_pc.h | 3 --- 3 files changed, 16 insertions(+), 6 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
Introduce three options, one for each observed L3 cache size, and have the size select'd as needed.
Signed-off-by: Tom Rini trini@konsulko.com --- arch/powerpc/cpu/mpc85xx/Kconfig | 24 ++++++++++++++++++++++++ include/configs/P2041RDB.h | 2 -- include/configs/T102xRDB.h | 1 - include/configs/T104xRDB.h | 1 - include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240RDB.h | 1 - include/configs/kmcent2.h | 1 - 8 files changed, 24 insertions(+), 8 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/Kconfig b/arch/powerpc/cpu/mpc85xx/Kconfig index 7abfe26d35dd..24d3f1f20c25 100644 --- a/arch/powerpc/cpu/mpc85xx/Kconfig +++ b/arch/powerpc/cpu/mpc85xx/Kconfig @@ -165,6 +165,7 @@ config TARGET_P2041RDB select BOARD_LATE_INIT if CHAIN_OF_TRUST select FSL_CORENET select PHYS_64BIT + select SYS_L3_SIZE_1024KB imply CMD_SATA imply FSL_SATA
@@ -182,6 +183,7 @@ config TARGET_T1024RDB select SUPPORT_SPL select PHYS_64BIT select FSL_DDR_INTERACTIVE + select SYS_L3_SIZE_256KB imply CMD_EEPROM imply PANIC_HANG
@@ -191,6 +193,7 @@ config TARGET_T1042RDB select BOARD_LATE_INIT if CHAIN_OF_TRUST select SUPPORT_SPL select PHYS_64BIT + select SYS_L3_SIZE_256KB
config TARGET_T1042D4RDB bool "Support T1042D4RDB" @@ -198,6 +201,7 @@ config TARGET_T1042D4RDB select BOARD_LATE_INIT if CHAIN_OF_TRUST select SUPPORT_SPL select PHYS_64BIT + select SYS_L3_SIZE_256KB imply PANIC_HANG
config TARGET_T1042RDB_PI @@ -206,6 +210,7 @@ config TARGET_T1042RDB_PI select BOARD_LATE_INIT if CHAIN_OF_TRUST select SUPPORT_SPL select PHYS_64BIT + select SYS_L3_SIZE_256KB imply PANIC_HANG
config TARGET_T2080QDS @@ -216,6 +221,7 @@ config TARGET_T2080QDS select PHYS_64BIT select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE select FSL_DDR_INTERACTIVE + select SYS_L3_SIZE_512KB imply CMD_SATA
config TARGET_T2080RDB @@ -224,6 +230,7 @@ config TARGET_T2080RDB select BOARD_LATE_INIT if CHAIN_OF_TRUST select SUPPORT_SPL select PHYS_64BIT + select SYS_L3_SIZE_512KB imply CMD_SATA imply PANIC_HANG
@@ -233,6 +240,7 @@ config TARGET_T4240RDB select SUPPORT_SPL select PHYS_64BIT select FSL_DDR_FIRST_SLOT_QUAD_CAPABLE + select SYS_L3_SIZE_512KB imply CMD_SATA imply PANIC_HANG
@@ -244,6 +252,7 @@ config TARGET_KMCENT2 bool "Support kmcent2" select VENDOR_KM select FSL_CORENET + select SYS_L3_SIZE_256KB
endchoice
@@ -1296,6 +1305,21 @@ config SYS_L2_SIZE config BACKSIDE_L2_CACHE bool
+config SYS_L3_SIZE_256KB + bool + +config SYS_L3_SIZE_512KB + bool + +config SYS_L3_SIZE_1024KB + bool + +config SYS_L3_SIZE + int + default 262144 if SYS_L3_SIZE_256KB + default 524288 if SYS_L3_SIZE_512KB + default 1048576 if SYS_L3_SIZE_512KB + config SYS_PPC64 bool
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 0bd3bac97e43..7ccde665607b 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -59,8 +59,6 @@ #else #define CONFIG_SYS_INIT_L3_ADDR_PHYS CONFIG_SYS_INIT_L3_ADDR #endif -#define CONFIG_SYS_L3_SIZE (1024 << 10) -#define CONFIG_SYS_INIT_L3_END (CONFIG_SYS_INIT_L3_ADDR + CONFIG_SYS_L3_SIZE)
#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_DCSRBAR 0xf0000000 diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 7630be245c1f..c5c2f8c038b2 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -104,7 +104,6 @@ * Config the L3 Cache as L3 SRAM */ #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 -#define CONFIG_SYS_L3_SIZE (256 << 10) #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#ifdef CONFIG_PHYS_64BIT diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 19e3dfbfdb12..532a5541dc87 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -78,7 +78,6 @@ * (CONFIG_SYS_INIT_L3_VADDR) will be different. */ #define CONFIG_SYS_INIT_L3_VADDR 0xFFFC0000 -#define CONFIG_SYS_L3_SIZE 256 << 10 #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000 diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 6700560123b7..f97d0fc515b6 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -76,7 +76,6 @@ * Config the L3 Cache as L3 SRAM */ #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 -#define CONFIG_SYS_L3_SIZE (512 << 10) #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000 diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 4de4a72999e9..b765cbbadc41 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -71,7 +71,6 @@ * Config the L3 Cache as L3 SRAM */ #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 -#define CONFIG_SYS_L3_SIZE (512 << 10) #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000 diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index dc507473b259..384b9c1e02b9 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -52,7 +52,6 @@ * Config the L3 Cache as L3 SRAM */ #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 -#define CONFIG_SYS_L3_SIZE (512 << 10) #define SPL_ENV_ADDR (CONFIG_SPL_GD_ADDR + 4 * 1024)
#define CONFIG_SYS_DCSRBAR 0xf0000000 diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 3def00164748..e5cc62ebdc27 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -154,7 +154,6 @@ * Config the L3 Cache as L3 SRAM */ #define CONFIG_SYS_INIT_L3_ADDR 0xFFFC0000 -#define CONFIG_SYS_L3_SIZE 256 << 10
#define CONFIG_SYS_DCSRBAR 0xf0000000 #define CONFIG_SYS_DCSRBAR_PHYS 0xf00000000ull
On Fri, 28 Oct 2022 at 18:28, Tom Rini trini@konsulko.com wrote:
Introduce three options, one for each observed L3 cache size, and have the size select'd as needed.
Signed-off-by: Tom Rini trini@konsulko.com
arch/powerpc/cpu/mpc85xx/Kconfig | 24 ++++++++++++++++++++++++ include/configs/P2041RDB.h | 2 -- include/configs/T102xRDB.h | 1 - include/configs/T104xRDB.h | 1 - include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240RDB.h | 1 - include/configs/kmcent2.h | 1 - 8 files changed, 24 insertions(+), 8 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
This converts the following to Kconfig: CONFIG_SYS_LOADS_BAUD_CHANGE CONFIG_LOADS_ECHO
As part of this, we move CMD_SAVES to be after CMD_LOADS as they are logically related (load or save an s-record format file) and this makes grouping of CONFIG_SYS_LOADS_BAUD_CHANGE easier.
Signed-off-by: Tom Rini trini@konsulko.com --- README | 12 --------- cmd/Kconfig | 28 +++++++++++++++----- configs/MPC837XERDB_defconfig | 2 ++ configs/MPC8548CDS_36BIT_defconfig | 2 ++ configs/MPC8548CDS_defconfig | 2 ++ configs/MPC8548CDS_legacy_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_NAND_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_NOR_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 2 ++ configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PA_NAND_defconfig | 2 ++ configs/P1010RDB-PA_NOR_defconfig | 2 ++ configs/P1010RDB-PA_SDCARD_defconfig | 2 ++ configs/P1010RDB-PA_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_NAND_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_NOR_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 2 ++ configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1010RDB-PB_NAND_defconfig | 2 ++ configs/P1010RDB-PB_NOR_defconfig | 2 ++ configs/P1010RDB-PB_SDCARD_defconfig | 2 ++ configs/P1010RDB-PB_SPIFLASH_defconfig | 2 ++ configs/P1020RDB-PC_36BIT_NAND_defconfig | 2 ++ configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 2 ++ configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 2 ++ configs/P1020RDB-PC_36BIT_defconfig | 2 ++ configs/P1020RDB-PC_NAND_defconfig | 2 ++ configs/P1020RDB-PC_SDCARD_defconfig | 2 ++ configs/P1020RDB-PC_SPIFLASH_defconfig | 2 ++ configs/P1020RDB-PC_defconfig | 2 ++ configs/P1020RDB-PD_NAND_defconfig | 2 ++ configs/P1020RDB-PD_SDCARD_defconfig | 2 ++ configs/P1020RDB-PD_SPIFLASH_defconfig | 2 ++ configs/P1020RDB-PD_defconfig | 2 ++ configs/P2020RDB-PC_36BIT_NAND_defconfig | 2 ++ configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 2 ++ configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 2 ++ configs/P2020RDB-PC_36BIT_defconfig | 2 ++ configs/P2020RDB-PC_NAND_defconfig | 2 ++ configs/P2020RDB-PC_SDCARD_defconfig | 2 ++ configs/P2020RDB-PC_SPIFLASH_defconfig | 2 ++ configs/P2020RDB-PC_defconfig | 2 ++ configs/P2041RDB_NAND_defconfig | 2 ++ configs/P2041RDB_SDCARD_defconfig | 2 ++ configs/P2041RDB_SPIFLASH_defconfig | 2 ++ configs/P2041RDB_defconfig | 2 ++ configs/T1024RDB_NAND_defconfig | 2 ++ configs/T1024RDB_SDCARD_defconfig | 2 ++ configs/T1024RDB_SPIFLASH_defconfig | 2 ++ configs/T1024RDB_defconfig | 2 ++ configs/T1042D4RDB_NAND_defconfig | 2 ++ configs/T1042D4RDB_SDCARD_defconfig | 2 ++ configs/T1042D4RDB_SPIFLASH_defconfig | 2 ++ configs/T1042D4RDB_defconfig | 2 ++ configs/T2080QDS_NAND_defconfig | 2 ++ configs/T2080QDS_SDCARD_defconfig | 2 ++ configs/T2080QDS_SECURE_BOOT_defconfig | 2 ++ configs/T2080QDS_SPIFLASH_defconfig | 2 ++ configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 2 ++ configs/T2080QDS_defconfig | 2 ++ configs/T4240RDB_SDCARD_defconfig | 2 ++ configs/T4240RDB_defconfig | 2 ++ configs/gazerbeam_defconfig | 2 ++ configs/kmcent2_defconfig | 2 ++ configs/kmcoge5ne_defconfig | 2 ++ configs/kmeter1_defconfig | 2 ++ configs/kmopti2_defconfig | 2 ++ configs/kmsupx5_defconfig | 2 ++ configs/kmtepr2_defconfig | 2 ++ configs/pg_wcom_expu1_defconfig | 2 ++ configs/pg_wcom_expu1_update_defconfig | 2 ++ configs/pg_wcom_seli8_defconfig | 2 ++ configs/pg_wcom_seli8_update_defconfig | 2 ++ configs/qemu-ppce500_defconfig | 1 + configs/socrates_defconfig | 2 ++ configs/tuge1_defconfig | 2 ++ configs/tuxx1_defconfig | 2 ++ include/configs/MCR3000.h | 2 -- include/configs/MPC837XERDB.h | 7 ----- include/configs/MPC8548CDS.h | 7 ----- include/configs/P1010RDB.h | 3 --- include/configs/P2041RDB.h | 6 ----- include/configs/T102xRDB.h | 6 ----- include/configs/T104xRDB.h | 6 ----- include/configs/T208xQDS.h | 6 ----- include/configs/T4240RDB.h | 6 ----- include/configs/blanche.h | 2 -- include/configs/gazerbeam.h | 7 ----- include/configs/km/keymile-common.h | 3 --- include/configs/p1_p2_rdb_pc.h | 3 --- include/configs/qemu-ppce500.h | 6 ----- include/configs/socrates.h | 7 ----- 92 files changed, 170 insertions(+), 96 deletions(-)
diff --git a/README b/README index 0e01176d4f65..9b672d49a68a 100644 --- a/README +++ b/README @@ -435,15 +435,6 @@ The following options need to be configured: Define this variable to enable hw flow control in serial driver. Current user of this option is drivers/serial/nsl16550.c driver
-- Serial Download Echo Mode: - CONFIG_LOADS_ECHO - If defined to 1, all characters received during a - serial download (using the "loads" command) are - echoed back. This might be needed by some terminal - emulations (like "cu"), but may as well just take - time on others. This setting #define's the initial - value of the "loads_echo" environment variable. - - Removal of commands If no commands are needed to boot, you can disable CONFIG_CMDLINE to remove them. In this case, the command line @@ -1529,9 +1520,6 @@ Configuration Settings: the RAM base is not zero, or RAM is divided into banks, this variable needs to be recalcuated to get the address.
-- CONFIG_SYS_LOADS_BAUD_CHANGE: - Enable temporary baudrate change while serial download - - CONFIG_SYS_SDRAM_BASE: Physical start address of SDRAM. _Must_ be 0 here.
diff --git a/cmd/Kconfig b/cmd/Kconfig index 41cf1d46fb17..6b4cdf045f60 100644 --- a/cmd/Kconfig +++ b/cmd/Kconfig @@ -1194,11 +1194,31 @@ config CMD_LOADM Load a binary over memory mapped.
config CMD_LOADS - bool "loads" + bool "loads - Load a file over serial in S-Record format" default y help Load an S-Record file over serial line
+config LOADS_ECHO + bool "Echo all characters received during a loads back to console" + depends on CMD_LOADS + help + If enabled, all characters received during a serial download (using + the "loads" command) are echoed back. This might be needed by some + terminal emulations (like "cu"), but may as well just take time on + others. This sets the initial value of the "loads_echo" environment + variable to 1. + +config CMD_SAVES + bool "saves - Save a file over serial in S-Record format" + help + Provides a way to save a binary file using the Motorola S-Record + format over the serial line. + +config SYS_LOADS_BAUD_CHANGE + bool "Enable a temporary baudrate change during loads/saves command" + depends on CMD_LOADS || CMD_SAVES + config CMD_LOADXY_TIMEOUT int "loadxy_timeout" range 0 2000 @@ -1398,12 +1418,6 @@ config CMD_SATA Attachment, where AT refers to an IBM AT (Advanced Technology) computer released in 1984.
-config CMD_SAVES - bool "saves - Save a file over serial in S-Record format" - help - Provides a way to save a binary file using the Motorola S-Record - format over the serial line. - config CMD_SCSI bool "scsi - Access to SCSI devices" default y if SCSI diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 16740c8cb9c5..50abb797d287 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -157,6 +157,8 @@ CONFIG_HUSH_PARSER=y CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_SATA=y diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index eb284d2bf727..b4475799c7ba 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -28,6 +28,8 @@ CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_PCI=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 54d2c840c393..7d096dcddffe 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -27,6 +27,8 @@ CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_PCI=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index 99b9f6b6962e..159028a84e6a 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -28,6 +28,8 @@ CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_PCI=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_MII=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index 43c2738d7c8f..2808763cc2bc 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -61,6 +61,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index 2df781e22b37..c857d0693899 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -31,6 +31,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index 30eb359e55e9..c3432bac6926 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -52,6 +52,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index fe37bb63d2de..9c272991008b 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -54,6 +54,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index 2b2c92e69de9..24efd95dac6c 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -60,6 +60,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index 7f3fa16bcebd..0cf331645b36 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -30,6 +30,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index c0fcd935fa27..cda3bcff5104 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -51,6 +51,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index 5f7b1e1bdd6b..f55eec2c6f19 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -53,6 +53,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index fa5d305879a7..d04cae88baa3 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -62,6 +62,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 92f491f133b9..2b45dd00c3a5 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -32,6 +32,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index c85ca4f95401..cf3ffdd8544b 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -53,6 +53,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 39a6a217f112..8c0e996f9137 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -55,6 +55,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index 4572abd5280c..e68276530b29 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -61,6 +61,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 065020890a3e..6918a906047c 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -31,6 +31,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index 5f09f994ff67..9913cd2c4cf1 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -52,6 +52,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index f881e4328c32..2832e58eddd4 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -54,6 +54,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 96224bb349a3..c3672d1760bc 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -62,6 +62,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index f2ec6d8315f1..5ea1cb5245cf 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -54,6 +54,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 607ae5c9fa6a..0177ae5eb58a 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -56,6 +56,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 4411ca006e5e..82e11dabffe1 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -34,6 +34,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index a5f4acbb3e6e..887a0d90a70b 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -61,6 +61,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 8672b663e7b0..76d1b8c3cb60 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -53,6 +53,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 61d4b55d25e3..996fa5dcc085 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -55,6 +55,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index b04da8a86ff3..1519cf6d9014 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -33,6 +33,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 47cc14b39942..00f9df246bd3 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -61,6 +61,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 2de84f5d0bf5..f8cc037a4e61 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -53,6 +53,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index 503123f61c78..ab1d3f1355e4 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -55,6 +55,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index aa520f85b31e..a5008a5bc3ed 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -33,6 +33,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_MII=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 3e76317ba3af..6f51ab625437 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -62,6 +62,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 6e288196989a..7ccdc1f5c948 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -54,6 +54,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index 64199f279239..bbdc5452debc 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -56,6 +56,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 512271010fd4..c97eb4b96b4f 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -34,6 +34,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 0fad104d3cd3..58e461ba4467 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -61,6 +61,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 6aaba451d386..60a295933869 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -53,6 +53,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index f08e939c9974..188a22b76dcd 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -55,6 +55,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 2a96c8e19250..4e414d45958f 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -33,6 +33,8 @@ CONFIG_CMD_IMLS=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=5 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_PCI=y CONFIG_CMD_USB=y diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index 26211f74683b..e48d9fba6399 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -38,6 +38,8 @@ CONFIG_CMD_GREPENV=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_DM=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index ae0ba5494506..6c589b464b77 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -38,6 +38,8 @@ CONFIG_CMD_GREPENV=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_DM=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index 69cdff4e6ca9..d8017c3c6cc9 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -40,6 +40,8 @@ CONFIG_CMD_GREPENV=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_DM=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index 06a5b1f5b9e5..bca9e3794d2d 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -36,6 +36,8 @@ CONFIG_CMD_GREPENV=y CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_CMD_DM=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index a0da36197efb..eb5e70b88112 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -68,6 +68,8 @@ CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 442e7e53b3e4..4c8fb8252653 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -67,6 +67,8 @@ CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 3985a9443e86..8405d25f10e1 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -70,6 +70,8 @@ CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index a0d36467bd47..44ef30577c70 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -42,6 +42,8 @@ CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_DM=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 1c4ab7bf074e..d7e0a9f57516 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -61,6 +61,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DM=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index f71ade16137d..c3c3303d82c0 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -60,6 +60,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DM=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index a32e86df705a..c9bf6db4407a 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -63,6 +63,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DM=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index c1749a1cb903..3ce7270cc315 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -35,6 +35,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DM=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index beb8817b656f..ff72ec9452ba 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -65,6 +65,8 @@ CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index bb5d05c7e5b2..2f209166263d 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -64,6 +64,8 @@ CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index a33097391d18..10757091b4e3 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -39,6 +39,8 @@ CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index 2fb1d7eb29ee..edef62e00878 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -67,6 +67,8 @@ CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 252017f73334..612bb6a444c8 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -39,6 +39,8 @@ CONFIG_SYS_PBSIZE=276 CONFIG_CMD_GREPENV=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index f9a105bc3697..d2dc24fb036b 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -39,6 +39,8 @@ CONFIG_SYS_PBSIZE=276 CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index 59ecbf43816c..de25f325990c 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -61,6 +61,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DM=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index 3735d82a51ff..bd125980d051 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -36,6 +36,8 @@ CONFIG_CMD_IMLS=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DM=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig index e3b1b0e8272e..a184e81fb9dc 100644 --- a/configs/gazerbeam_defconfig +++ b/configs/gazerbeam_defconfig @@ -140,6 +140,8 @@ CONFIG_CMD_MEMTEST=y CONFIG_SYS_ALT_MEMTEST=y CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_AXI=y # CONFIG_CMD_SETEXPR is not set diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig index c9fcc963bfb7..144edd4da508 100644 --- a/configs/kmcent2_defconfig +++ b/configs/kmcent2_defconfig @@ -35,6 +35,8 @@ CONFIG_SYS_CBSIZE=512 CONFIG_SYS_PBSIZE=532 CONFIG_CMD_DM=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_MMC=y CONFIG_CMD_MTD=y CONFIG_CMD_NAND_TRIMFFS=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 99d92752db9c..686644393204 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -181,6 +181,8 @@ CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_NAND=y # CONFIG_CMD_PINMUX is not set CONFIG_CMD_DHCP=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 96d4f10d3641..79567261f9b1 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -151,6 +151,8 @@ CONFIG_SYS_I2C_EEPROM_ADDR_LEN=2 CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y # CONFIG_CMD_PINMUX is not set CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index a764de67536c..af8ec9da9a9d 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -163,6 +163,8 @@ CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y # CONFIG_CMD_PINMUX is not set CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index c521c94ebcf0..945593df5391 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -143,6 +143,8 @@ CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_MII=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index e587670bea12..be0f858dffd5 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -163,6 +163,8 @@ CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_MII=y diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig index 73ae5290edbc..d972c29c03ca 100644 --- a/configs/pg_wcom_expu1_defconfig +++ b/configs/pg_wcom_expu1_defconfig @@ -52,6 +52,8 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_BOOTP_BOOTFILESIZE=y diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig index 3473457fd6ce..66e21ddf2330 100644 --- a/configs/pg_wcom_expu1_update_defconfig +++ b/configs/pg_wcom_expu1_update_defconfig @@ -50,6 +50,8 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_BOOTP_BOOTFILESIZE=y diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig index f926cdcf0399..fecb62e679bd 100644 --- a/configs/pg_wcom_seli8_defconfig +++ b/configs/pg_wcom_seli8_defconfig @@ -52,6 +52,8 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_BOOTP_BOOTFILESIZE=y diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig index c7329f17a1bd..828a961b4625 100644 --- a/configs/pg_wcom_seli8_update_defconfig +++ b/configs/pg_wcom_seli8_update_defconfig @@ -50,6 +50,8 @@ CONFIG_CMD_MEMINFO=y CONFIG_CMD_MEMTEST=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_NAND=y CONFIG_CMD_NAND_TRIMFFS=y CONFIG_BOOTP_BOOTFILESIZE=y diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index 4e2e77a1b6c9..70807bf00b04 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -24,6 +24,7 @@ CONFIG_CMD_BOOTZ=y CONFIG_CMD_GREPENV=y CONFIG_CMD_DM=y CONFIG_CMD_GPIO=y +CONFIG_LOADS_ECHO=y CONFIG_CMD_PCI=y CONFIG_CMD_POWEROFF=y CONFIG_CMD_DHCP=y diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index 0da3a4379275..dd6bf60af317 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -33,6 +33,8 @@ CONFIG_SYS_BOOTM_LEN=0x800000 CONFIG_CMD_IMLS=y CONFIG_CMD_DM=y CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_NAND=y CONFIG_CMD_PCI=y CONFIG_CMD_SDRAM=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 0b8a50003300..9237ff04fc22 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -143,6 +143,8 @@ CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_MII=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index c1548aa5cf1e..9fd6cc55e8be 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -165,6 +165,8 @@ CONFIG_CMD_EEPROM=y CONFIG_SYS_EEPROM_PAGE_WRITE_BITS=3 CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS=10 CONFIG_CMD_I2C=y +CONFIG_LOADS_ECHO=y +CONFIG_SYS_LOADS_BAUD_CHANGE=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y CONFIG_CMD_MII=y diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h index 9d0683829ecb..4b47c564418c 100644 --- a/include/configs/MCR3000.h +++ b/include/configs/MCR3000.h @@ -56,8 +56,6 @@ #define CONFIG_SERVERIP 192.168.0.1 #define CONFIG_NETMASK 255.0.0.0
-#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ - /* Miscellaneous configurable options */
/* Definitions for initial stack pointer and data area (in DPRAM) */ diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index dd5c26d7e0d9..476b7dfc0651 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -216,13 +216,6 @@ #endif #endif
-/* - * Environment - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - #ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC_PIN_MUX #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index bce4faca9fe4..a9486c421a6c 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -329,13 +329,6 @@ #define TSEC4_FLAGS (TSEC_GIGABIT | TSEC_REDUCED) #endif /* CONFIG_TSEC_ENET */
-/* - * Environment - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - /* * Miscellaneous configurable options */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 06188cac44f2..b87118c1ed26 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -407,9 +407,6 @@ extern unsigned long get_sdram_size(void); #endif #endif
-#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - #if defined(CONFIG_MMC) || defined(CONFIG_USB_EHCI_HCD) \ || defined(CONFIG_FSL_SATA) #endif diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 7ccde665607b..044e2d0d42b5 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -310,12 +310,6 @@ #define CONFIG_SYS_TBIPA_VALUE 8 #endif
-/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - #ifdef CONFIG_MMC #define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR #endif diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index c5c2f8c038b2..a15121cc4dae 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -426,12 +426,6 @@ * Dynamic MTD Partition support with mtdparts */
-/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - /* * Miscellaneous configurable options */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 532a5541dc87..751f6c7db8ef 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -415,12 +415,6 @@ #endif #endif
-/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - /* * Miscellaneous configurable options */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index f97d0fc515b6..59edb5013510 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -431,12 +431,6 @@ * Dynamic MTD Partition support with mtdparts */
-/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - /* * Miscellaneous configurable options */ diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 384b9c1e02b9..61f3b98b7dc6 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -133,12 +133,6 @@ #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull
-/* - * Environment - */ -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - /* * Miscellaneous configurable options */ diff --git a/include/configs/blanche.h b/include/configs/blanche.h index 959c521b6c91..0b1fc91d9e17 100644 --- a/include/configs/blanche.h +++ b/include/configs/blanche.h @@ -21,8 +21,6 @@ #define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024) #define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
-#undef CONFIG_SYS_LOADS_BAUD_CHANGE - /* FLASH */ #if !defined(CONFIG_MTD_NOR_FLASH) #define CONFIG_SH_QSPI_BASE 0xE6B10000 diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h index 771a30106c1b..8bab723e5699 100644 --- a/include/configs/gazerbeam.h +++ b/include/configs/gazerbeam.h @@ -42,13 +42,6 @@ #define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200}
-/* - * Environment - */ - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - /* * Miscellaneous configurable options */ diff --git a/include/configs/km/keymile-common.h b/include/configs/km/keymile-common.h index 1bfc89bf44ca..35cf27a2eb90 100644 --- a/include/configs/km/keymile-common.h +++ b/include/configs/km/keymile-common.h @@ -15,9 +15,6 @@
#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 }
-#define CONFIG_LOADS_ECHO -#define CONFIG_SYS_LOADS_BAUD_CHANGE - #ifndef CONFIG_KM_DEF_ENV_BOOTPARAMS #define CONFIG_KM_DEF_ENV_BOOTPARAMS \ "actual_bank=0\0" diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index e632d852ed54..448fc3bb0654 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -415,9 +415,6 @@ #endif #endif
-#define CONFIG_LOADS_ECHO /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE /* allow baudrate change */ - /* * USB */ diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index 5181792b7b73..621135fe1012 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -51,12 +51,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void); /* RTC */ #define CONFIG_RTC_PT7C4338
-/* - * Environment - */ - -#define CONFIG_LOADS_ECHO /* echo on for serial download */ - /* * Miscellaneous configurable options */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index c75991badab4..00e8136cc9c0 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -135,13 +135,6 @@
/* Options are: TSEC[0,1] */
-/* - * Environment - */ - -#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ -#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ - /* * Miscellaneous configurable options */
On Fri, 28 Oct 2022 at 18:29, Tom Rini trini@konsulko.com wrote:
This converts the following to Kconfig: CONFIG_SYS_LOADS_BAUD_CHANGE CONFIG_LOADS_ECHO
As part of this, we move CMD_SAVES to be after CMD_LOADS as they are logically related (load or save an s-record format file) and this makes grouping of CONFIG_SYS_LOADS_BAUD_CHANGE easier.
Signed-off-by: Tom Rini trini@konsulko.com
README | 12 --------- cmd/Kconfig | 28 +++++++++++++++-----
Reviewed-by: Simon Glass sjg@chromium.org
These drivers are not enabled anywhere, remove them.
Signed-off-by: Tom Rini trini@konsulko.com --- drivers/rtc/Makefile | 4 - drivers/rtc/m41t11.c | 168 -------------------------- drivers/rtc/m41t60.c | 239 ------------------------------------- drivers/rtc/m41t94.c | 123 ------------------- drivers/rtc/m48t35ax.c | 135 --------------------- include/configs/m53menlo.h | 1 - 6 files changed, 670 deletions(-) delete mode 100644 drivers/rtc/m41t11.c delete mode 100644 drivers/rtc/m41t60.c delete mode 100644 drivers/rtc/m41t94.c delete mode 100644 drivers/rtc/m48t35ax.c
diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index d621be622848..009dd9d28c95 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -27,11 +27,7 @@ obj-$(CONFIG_RTC_FTRTC010) += ftrtc010.o obj-$(CONFIG_SANDBOX) += i2c_rtc_emul.o obj-$(CONFIG_RTC_IMXDI) += imxdi.o obj-$(CONFIG_RTC_ISL1208) += isl1208.o -obj-$(CONFIG_RTC_M41T11) += m41t11.o -obj-$(CONFIG_RTC_M41T60) += m41t60.o obj-$(CONFIG_RTC_M41T62) += m41t62.o -obj-$(CONFIG_RTC_M41T94) += m41t94.o -obj-$(CONFIG_RTC_M48T35A) += m48t35ax.o obj-$(CONFIG_RTC_MAX6900) += max6900.o obj-$(CONFIG_RTC_MC13XXX) += mc13xxx-rtc.o obj-$(CONFIG_RTC_MC146818) += mc146818.o diff --git a/drivers/rtc/m41t11.c b/drivers/rtc/m41t11.c deleted file mode 100644 index 706b7188cf83..000000000000 --- a/drivers/rtc/m41t11.c +++ /dev/null @@ -1,168 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2002 - * Andrew May, Viasat Inc, amay@viasat.com - */ - -/* - * M41T11 Serial Access Timekeeper(R) SRAM - * can you believe a trademark on that? - */ - -/* #define DEBUG 1 */ - -#include <common.h> -#include <command.h> -#include <log.h> -#include <rtc.h> -#include <i2c.h> - -/* - I Don't have an example config file but this - is what should be done. - -#define CONFIG_RTC_M41T11 1 -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#if 0 -#define CONFIG_SYS_M41T11_EXT_CENTURY_DATA -#else -#define CONFIG_SYS_M41T11_BASE_YEAR 2000 -#endif -*/ - -/* ------------------------------------------------------------------------- */ -/* - these are simple defines for the chip local to here so they aren't too - verbose - DAY/DATE aren't nice but that is how they are on the data sheet -*/ -#define RTC_SEC_ADDR 0x0 -#define RTC_MIN_ADDR 0x1 -#define RTC_HOUR_ADDR 0x2 -#define RTC_DAY_ADDR 0x3 -#define RTC_DATE_ADDR 0x4 -#define RTC_MONTH_ADDR 0x5 -#define RTC_YEARS_ADDR 0x6 - -#define RTC_REG_CNT 7 - -#define RTC_CONTROL_ADDR 0x7 - - -#ifndef CONFIG_SYS_M41T11_EXT_CENTURY_DATA - -#define REG_CNT (RTC_REG_CNT+1) - -/* - you only get 00-99 for the year we will asume you - want from the year 2000 if you don't set the config -*/ -#ifndef CONFIG_SYS_M41T11_BASE_YEAR -#define CONFIG_SYS_M41T11_BASE_YEAR 2000 -#endif - -#else -/* we will store extra year info in byte 9*/ -#define M41T11_YEAR_DATA 0x8 -#define M41T11_YEAR_SIZE 1 -#define REG_CNT (RTC_REG_CNT+1+M41T11_YEAR_SIZE) -#endif - -#define M41T11_STORAGE_SZ (64-REG_CNT) - -int rtc_get (struct rtc_time *tmp) -{ - int rel = 0; - uchar data[RTC_REG_CNT]; - - i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, data, RTC_REG_CNT); - - if( data[RTC_SEC_ADDR] & 0x80 ){ - printf( "m41t11 RTC Clock stopped!!!\n" ); - rel = -1; - } - tmp->tm_sec = bcd2bin (data[RTC_SEC_ADDR] & 0x7F); - tmp->tm_min = bcd2bin (data[RTC_MIN_ADDR] & 0x7F); - tmp->tm_hour = bcd2bin (data[RTC_HOUR_ADDR] & 0x3F); - tmp->tm_mday = bcd2bin (data[RTC_DATE_ADDR] & 0x3F); - tmp->tm_mon = bcd2bin (data[RTC_MONTH_ADDR]& 0x1F); -#ifndef CONFIG_SYS_M41T11_EXT_CENTURY_DATA - tmp->tm_year = CONFIG_SYS_M41T11_BASE_YEAR - + bcd2bin(data[RTC_YEARS_ADDR]) - + ((data[RTC_HOUR_ADDR]&0x40) ? 100 : 0); -#else - { - unsigned char cent; - i2c_read(CONFIG_SYS_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, ¢, M41T11_YEAR_SIZE); - if( !(data[RTC_HOUR_ADDR] & 0x80) ){ - printf( "m41t11 RTC: cann't keep track of years without CEB set\n" ); - rel = -1; - } - if( (cent & 0x1) != ((data[RTC_HOUR_ADDR]&0x40)>>7) ){ - /*century flip store off new year*/ - cent += 1; - i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, ¢, M41T11_YEAR_SIZE); - } - tmp->tm_year =((int)cent*100)+bcd2bin(data[RTC_YEARS_ADDR]); - } -#endif - tmp->tm_wday = bcd2bin (data[RTC_DAY_ADDR] & 0x07); - tmp->tm_yday = 0; - tmp->tm_isdst= 0; - - debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - return rel; -} - -int rtc_set (struct rtc_time *tmp) -{ - uchar data[RTC_REG_CNT]; - - debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - data[RTC_SEC_ADDR] = bin2bcd(tmp->tm_sec) & 0x7F;/*just in case*/ - data[RTC_MIN_ADDR] = bin2bcd(tmp->tm_min); - data[RTC_HOUR_ADDR] = bin2bcd(tmp->tm_hour) & 0x3F;/*handle cent stuff later*/ - data[RTC_DATE_ADDR] = bin2bcd(tmp->tm_mday) & 0x3F; - data[RTC_MONTH_ADDR] = bin2bcd(tmp->tm_mon); - data[RTC_DAY_ADDR] = bin2bcd(tmp->tm_wday) & 0x07; - - data[RTC_HOUR_ADDR] |= 0x80;/*we will always use CEB*/ - - data[RTC_YEARS_ADDR] = bin2bcd(tmp->tm_year%100);/*same thing either way*/ -#ifndef CONFIG_SYS_M41T11_EXT_CENTURY_DATA - if( ((tmp->tm_year - CONFIG_SYS_M41T11_BASE_YEAR) > 200) || - (tmp->tm_year < CONFIG_SYS_M41T11_BASE_YEAR) ){ - printf( "m41t11 RTC setting year out of range!!need recompile\n" ); - } - data[RTC_HOUR_ADDR] |= (tmp->tm_year - CONFIG_SYS_M41T11_BASE_YEAR) > 100 ? 0x40 : 0; -#else - { - unsigned char cent; - cent = tmp->tm_year ? tmp->tm_year / 100 : 0; - data[RTC_HOUR_ADDR] |= (cent & 0x1) ? 0x40 : 0; - i2c_write(CONFIG_SYS_I2C_RTC_ADDR, M41T11_YEAR_DATA, 1, ¢, M41T11_YEAR_SIZE); - } -#endif - i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, data, RTC_REG_CNT); - - return 0; -} - -void rtc_reset (void) -{ - unsigned char val; - /* clear all control & status registers */ - i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, &val, 1); - val = val & 0x7F;/*make sure we are running*/ - i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC_ADDR, 1, &val, RTC_REG_CNT); - - i2c_read(CONFIG_SYS_I2C_RTC_ADDR, RTC_CONTROL_ADDR, 1, &val, 1); - val = val & 0x3F;/*turn off freq test keep calibration*/ - i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_CONTROL_ADDR, 1, &val, 1); -} diff --git a/drivers/rtc/m41t60.c b/drivers/rtc/m41t60.c deleted file mode 100644 index b8ad33e01256..000000000000 --- a/drivers/rtc/m41t60.c +++ /dev/null @@ -1,239 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2007 - * Larry Johnson, lrj@acm.org - * - * based on rtc/m41t11.c which is ... - * - * (C) Copyright 2002 - * Andrew May, Viasat Inc, amay@viasat.com - */ - -/* - * STMicroelectronics M41T60 serial access real-time clock - */ - -/* #define DEBUG 1 */ - -#include <common.h> -#include <command.h> -#include <env.h> -#include <log.h> -#include <rtc.h> -#include <i2c.h> - -/* - * Convert between century and "century bits" (CB1 and CB0). These routines - * assume years are in the range 1900 - 2299. - */ - -static unsigned char year2cb(unsigned const year) -{ - if (year < 1900 || year >= 2300) - printf("M41T60 RTC: year %d out of range\n", year); - - return (year / 100) & 0x3; -} - -static unsigned cb2year(unsigned const cb) -{ - return 1900 + 100 * ((cb + 1) & 0x3); -} - -/* - * These are simple defines for the chip local to here so they aren't too - * verbose. DAY/DATE aren't nice but that is how they are on the data sheet. - */ -#define RTC_SEC 0x0 -#define RTC_MIN 0x1 -#define RTC_HOUR 0x2 -#define RTC_DAY 0x3 -#define RTC_DATE 0x4 -#define RTC_MONTH 0x5 -#define RTC_YEAR 0x6 - -#define RTC_REG_CNT 7 - -#define RTC_CTRL 0x7 - -#if defined(DEBUG) -static void rtc_dump(char const *const label) -{ - uchar data[8]; - - if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) { - printf("I2C read failed in rtc_dump()\n"); - return; - } - printf("RTC dump %s: %02X-%02X-%02X-%02X-%02X-%02X-%02X-%02X\n", - label, data[0], data[1], data[2], data[3], - data[4], data[5], data[6], data[7]); -} -#else -#define rtc_dump(label) -#endif - -static uchar *rtc_validate(void) -{ - /* - * This routine uses the OUT bit and the validity of the time values to - * determine whether there has been an initial power-up since the last - * time the routine was run. It assumes that the OUT bit is not being - * used for any other purpose. - */ - static const uchar daysInMonth[0x13] = { - 0x00, 0x31, 0x29, 0x31, 0x30, 0x31, 0x30, 0x31, - 0x31, 0x30, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, - 0x31, 0x30, 0x31 - }; - static uchar data[8]; - uchar min, date, month, years; - - rtc_dump("begin validate"); - if (i2c_read(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) { - printf("I2C read failed in rtc_validate()\n"); - return 0; - } - /* - * If the OUT bit is "1", there has been a loss of power, so stop the - * oscillator so it can be "kick-started" as per data sheet. - */ - if (0x00 != (data[RTC_CTRL] & 0x80)) { - printf("M41T60 RTC clock lost power.\n"); - data[RTC_SEC] = 0x80; - if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_SEC, 1, data, 1)) { - printf("I2C write failed in rtc_validate()\n"); - return 0; - } - } - /* - * If the oscillator is stopped or the date is invalid, then reset the - * OUT bit to "0", reset the date registers, and start the oscillator. - */ - min = data[RTC_MIN] & 0x7F; - date = data[RTC_DATE]; - month = data[RTC_MONTH] & 0x3F; - years = data[RTC_YEAR]; - if (0x59 < data[RTC_SEC] || 0x09 < (data[RTC_SEC] & 0x0F) || - 0x59 < min || 0x09 < (min & 0x0F) || - 0x23 < data[RTC_HOUR] || 0x09 < (data[RTC_HOUR] & 0x0F) || - 0x07 < data[RTC_DAY] || 0x00 == data[RTC_DAY] || - 0x12 < month || - 0x99 < years || 0x09 < (years & 0x0F) || - daysInMonth[month] < date || 0x09 < (date & 0x0F) || 0x00 == date || - (0x29 == date && 0x02 == month && - ((0x00 != (years & 0x03)) || - (0x00 == years && 0x00 != (data[RTC_MONTH] & 0xC0))))) { - printf("Resetting M41T60 RTC clock.\n"); - /* - * Set to 00:00:00 1900-01-01 (Monday) - */ - data[RTC_SEC] = 0x00; - data[RTC_MIN] &= 0x80; /* preserve OFIE bit */ - data[RTC_HOUR] = 0x00; - data[RTC_DAY] = 0x02; - data[RTC_DATE] = 0x01; - data[RTC_MONTH] = 0xC1; - data[RTC_YEAR] = 0x00; - data[RTC_CTRL] &= 0x7F; /* reset OUT bit */ - - if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, sizeof(data))) { - printf("I2C write failed in rtc_validate()\n"); - return 0; - } - } - return data; -} - -int rtc_get(struct rtc_time *tmp) -{ - uchar const *const data = rtc_validate(); - - if (!data) - return -1; - - tmp->tm_sec = bcd2bin(data[RTC_SEC] & 0x7F); - tmp->tm_min = bcd2bin(data[RTC_MIN] & 0x7F); - tmp->tm_hour = bcd2bin(data[RTC_HOUR] & 0x3F); - tmp->tm_mday = bcd2bin(data[RTC_DATE] & 0x3F); - tmp->tm_mon = bcd2bin(data[RTC_MONTH] & 0x1F); - tmp->tm_year = cb2year(data[RTC_MONTH] >> 6) + bcd2bin(data[RTC_YEAR]); - tmp->tm_wday = bcd2bin(data[RTC_DAY] & 0x07) - 1; - tmp->tm_yday = 0; - tmp->tm_isdst = 0; - - debug("Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - return 0; -} - -int rtc_set(struct rtc_time *tmp) -{ - uchar *const data = rtc_validate(); - - if (!data) - return -1; - - debug("Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - data[RTC_SEC] = (data[RTC_SEC] & 0x80) | (bin2bcd(tmp->tm_sec) & 0x7F); - data[RTC_MIN] = (data[RTC_MIN] & 0X80) | (bin2bcd(tmp->tm_min) & 0X7F); - data[RTC_HOUR] = bin2bcd(tmp->tm_hour) & 0x3F; - data[RTC_DATE] = bin2bcd(tmp->tm_mday) & 0x3F; - data[RTC_MONTH] = bin2bcd(tmp->tm_mon) & 0x1F; - data[RTC_YEAR] = bin2bcd(tmp->tm_year % 100); - data[RTC_MONTH] |= year2cb(tmp->tm_year) << 6; - data[RTC_DAY] = bin2bcd(tmp->tm_wday + 1) & 0x07; - if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, 0, 1, data, RTC_REG_CNT)) { - printf("I2C write failed in rtc_set()\n"); - return -1; - } - - return 0; -} - -void rtc_reset(void) -{ - uchar *const data = rtc_validate(); - char const *const s = env_get("rtccal"); - - if (!data) - return; - - rtc_dump("begin reset"); - /* - * If environmental variable "rtccal" is present, it must be a hex value - * between 0x00 and 0x3F, inclusive. The five least-significan bits - * represent the calibration magnitude, and the sixth bit the sign bit. - * If these do not match the contents of the hardware register, that - * register is updated. The value 0x00 imples no correction. Consult - * the M41T60 documentation for further details. - */ - if (s) { - unsigned long const l = hextoul(s, 0); - - if (l <= 0x3F) { - if ((data[RTC_CTRL] & 0x3F) != l) { - printf("Setting RTC calibration to 0x%02lX\n", - l); - data[RTC_CTRL] &= 0xC0; - data[RTC_CTRL] |= (uchar) l; - } - } else - printf("environment parameter "rtccal" not valid: " - "ignoring\n"); - } - /* - * Turn off frequency test. - */ - data[RTC_CTRL] &= 0xBF; - if (i2c_write(CONFIG_SYS_I2C_RTC_ADDR, RTC_CTRL, 1, data + RTC_CTRL, 1)) { - printf("I2C write failed in rtc_reset()\n"); - return; - } - rtc_dump("end reset"); -} diff --git a/drivers/rtc/m41t94.c b/drivers/rtc/m41t94.c deleted file mode 100644 index 5b665bb01333..000000000000 --- a/drivers/rtc/m41t94.c +++ /dev/null @@ -1,123 +0,0 @@ -/* - * Driver for ST M41T94 SPI RTC - * - * Taken from the Linux kernel drivier: - * Copyright (C) 2008 Kim B. Heino - * - * Adaptation for U-Boot: - * Copyright (C) 2009 - * Albin Tonnerre, Free Electrons albin.tonnerre@free-electrons.com - * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - */ - -#include <common.h> -#include <rtc.h> -#include <spi.h> - -static struct spi_slave *slave; - -#define M41T94_REG_SECONDS 0x01 -#define M41T94_REG_MINUTES 0x02 -#define M41T94_REG_HOURS 0x03 -#define M41T94_REG_WDAY 0x04 -#define M41T94_REG_DAY 0x05 -#define M41T94_REG_MONTH 0x06 -#define M41T94_REG_YEAR 0x07 -#define M41T94_REG_HT 0x0c - -#define M41T94_BIT_HALT 0x40 -#define M41T94_BIT_STOP 0x80 -#define M41T94_BIT_CB 0x40 -#define M41T94_BIT_CEB 0x80 - -int rtc_set(struct rtc_time *tm) -{ - u8 buf[8]; /* write cmd + 7 registers */ - int ret; - - if (!slave) { - slave = spi_setup_slave(CONFIG_M41T94_SPI_BUS, - CONFIG_M41T94_SPI_CS, 1000000, - SPI_MODE_3); - if (!slave) - return -1; - } - spi_claim_bus(slave); - - buf[0] = 0x80 | M41T94_REG_SECONDS; /* write time + date */ - buf[M41T94_REG_SECONDS] = bin2bcd(tm->tm_sec); - buf[M41T94_REG_MINUTES] = bin2bcd(tm->tm_min); - buf[M41T94_REG_HOURS] = bin2bcd(tm->tm_hour); - buf[M41T94_REG_WDAY] = bin2bcd(tm->tm_wday + 1); - buf[M41T94_REG_DAY] = bin2bcd(tm->tm_mday); - buf[M41T94_REG_MONTH] = bin2bcd(tm->tm_mon + 1); - - buf[M41T94_REG_HOURS] |= M41T94_BIT_CEB; - if (tm->tm_year >= 100) - buf[M41T94_REG_HOURS] |= M41T94_BIT_CB; - buf[M41T94_REG_YEAR] = bin2bcd(tm->tm_year % 100); - - ret = spi_xfer(slave, 64, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END); - spi_release_bus(slave); - return ret; -} - -int rtc_get(struct rtc_time *tm) -{ - u8 buf[2]; - int ret, hour; - - if (!slave) { - slave = spi_setup_slave(CONFIG_M41T94_SPI_BUS, - CONFIG_M41T94_SPI_CS, 1000000, - SPI_MODE_3); - if (!slave) - return -1; - } - spi_claim_bus(slave); - - /* clear halt update bit */ - ret = spi_w8r8(slave, M41T94_REG_HT); - if (ret < 0) - return ret; - if (ret & M41T94_BIT_HALT) { - buf[0] = 0x80 | M41T94_REG_HT; - buf[1] = ret & ~M41T94_BIT_HALT; - spi_xfer(slave, 16, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END); - } - - /* clear stop bit */ - ret = spi_w8r8(slave, M41T94_REG_SECONDS); - if (ret < 0) - return ret; - if (ret & M41T94_BIT_STOP) { - buf[0] = 0x80 | M41T94_REG_SECONDS; - buf[1] = ret & ~M41T94_BIT_STOP; - spi_xfer(slave, 16, buf, NULL, SPI_XFER_BEGIN | SPI_XFER_END); - } - - tm->tm_sec = bcd2bin(spi_w8r8(slave, M41T94_REG_SECONDS)); - tm->tm_min = bcd2bin(spi_w8r8(slave, M41T94_REG_MINUTES)); - hour = spi_w8r8(slave, M41T94_REG_HOURS); - tm->tm_hour = bcd2bin(hour & 0x3f); - tm->tm_wday = bcd2bin(spi_w8r8(slave, M41T94_REG_WDAY)) - 1; - tm->tm_mday = bcd2bin(spi_w8r8(slave, M41T94_REG_DAY)); - tm->tm_mon = bcd2bin(spi_w8r8(slave, M41T94_REG_MONTH)) - 1; - tm->tm_year = bcd2bin(spi_w8r8(slave, M41T94_REG_YEAR)); - if ((hour & M41T94_BIT_CB) || !(hour & M41T94_BIT_CEB)) - tm->tm_year += 100; - - spi_release_bus(slave); - return 0; -} - -void rtc_reset(void) -{ - /* - * Could not be tested as the reset pin is not wired on - * the sbc35-ag20 board - */ -} diff --git a/drivers/rtc/m48t35ax.c b/drivers/rtc/m48t35ax.c deleted file mode 100644 index 1cc24cccae73..000000000000 --- a/drivers/rtc/m48t35ax.c +++ /dev/null @@ -1,135 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2001 - * Erik Theisen, Wave 7 Optics, etheisen@mindspring.com. - */ - -/* - * Date & Time support for ST Electronics M48T35Ax RTC - */ - -/*#define DEBUG */ - - -#include <common.h> -#include <command.h> -#include <rtc.h> -#include <config.h> - -static uchar rtc_read (uchar reg); -static void rtc_write (uchar reg, uchar val); - -/* ------------------------------------------------------------------------- */ - -int rtc_get (struct rtc_time *tmp) -{ - uchar sec, min, hour, cent_day, date, month, year; - uchar ccr; /* Clock control register */ - - /* Lock RTC for read using clock control register */ - ccr = rtc_read(0); - ccr = ccr | 0x40; - rtc_write(0, ccr); - - sec = rtc_read (0x1); - min = rtc_read (0x2); - hour = rtc_read (0x3); - cent_day= rtc_read (0x4); - date = rtc_read (0x5); - month = rtc_read (0x6); - year = rtc_read (0x7); - - /* UNLock RTC */ - ccr = rtc_read(0); - ccr = ccr & 0xBF; - rtc_write(0, ccr); - - debug ( "Get RTC year: %02x month: %02x date: %02x cent_day: %02x " - "hr: %02x min: %02x sec: %02x\n", - year, month, date, cent_day, - hour, min, sec ); - - tmp->tm_sec = bcd2bin (sec & 0x7F); - tmp->tm_min = bcd2bin (min & 0x7F); - tmp->tm_hour = bcd2bin (hour & 0x3F); - tmp->tm_mday = bcd2bin (date & 0x3F); - tmp->tm_mon = bcd2bin (month & 0x1F); - tmp->tm_year = bcd2bin (year) + ((cent_day & 0x10) ? 2000 : 1900); - tmp->tm_wday = bcd2bin (cent_day & 0x07); - tmp->tm_yday = 0; - tmp->tm_isdst= 0; - - debug ( "Get DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - return 0; -} - -int rtc_set (struct rtc_time *tmp) -{ - uchar ccr; /* Clock control register */ - uchar century; - - debug ( "Set DATE: %4d-%02d-%02d (wday=%d) TIME: %2d:%02d:%02d\n", - tmp->tm_year, tmp->tm_mon, tmp->tm_mday, tmp->tm_wday, - tmp->tm_hour, tmp->tm_min, tmp->tm_sec); - - /* Lock RTC for write using clock control register */ - ccr = rtc_read(0); - ccr = ccr | 0x80; - rtc_write(0, ccr); - - rtc_write (0x07, bin2bcd(tmp->tm_year % 100)); - rtc_write (0x06, bin2bcd(tmp->tm_mon)); - rtc_write (0x05, bin2bcd(tmp->tm_mday)); - - century = ((tmp->tm_year >= 2000) ? 0x10 : 0) | 0x20; - rtc_write (0x04, bin2bcd(tmp->tm_wday) | century); - - rtc_write (0x03, bin2bcd(tmp->tm_hour)); - rtc_write (0x02, bin2bcd(tmp->tm_min )); - rtc_write (0x01, bin2bcd(tmp->tm_sec )); - - /* UNLock RTC */ - ccr = rtc_read(0); - ccr = ccr & 0x7F; - rtc_write(0, ccr); - - return 0; -} - -void rtc_reset (void) -{ - uchar val; - - /* Clear all clock control registers */ - rtc_write (0x0, 0x80); /* No Read Lock or calibration */ - - /* Clear stop bit */ - val = rtc_read (0x1); - val &= 0x7f; - rtc_write(0x1, val); - - /* Enable century / disable frequency test */ - val = rtc_read (0x4); - val = (val & 0xBF) | 0x20; - rtc_write(0x4, val); - - /* Clear write lock */ - rtc_write(0x0, 0); -} - -/* ------------------------------------------------------------------------- */ - -static uchar rtc_read (uchar reg) -{ - return *(unsigned char *) - ((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg); -} - -static void rtc_write (uchar reg, uchar val) -{ - *(unsigned char *) - ((CONFIG_SYS_NVRAM_BASE_ADDR + CONFIG_SYS_NVRAM_SIZE - 8) + reg) = val; -} diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 0499e633512b..31a3e04bcbb0 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -66,7 +66,6 @@ */ #ifdef CONFIG_CMD_DATE #define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_M41T11_BASE_YEAR 2000 #endif
/*
On Fri, 28 Oct 2022 at 18:29, Tom Rini trini@konsulko.com wrote:
These drivers are not enabled anywhere, remove them.
Signed-off-by: Tom Rini trini@konsulko.com
drivers/rtc/Makefile | 4 - drivers/rtc/m41t11.c | 168 -------------------------- drivers/rtc/m41t60.c | 239 ------------------------------------- drivers/rtc/m41t94.c | 123 ------------------- drivers/rtc/m48t35ax.c | 135 --------------------- include/configs/m53menlo.h | 1 - 6 files changed, 670 deletions(-) delete mode 100644 drivers/rtc/m41t11.c delete mode 100644 drivers/rtc/m41t60.c delete mode 100644 drivers/rtc/m41t94.c delete mode 100644 drivers/rtc/m48t35ax.c
Reviewed-by: Simon Glass sjg@chromium.org
This converts the following to Kconfig: CONFIG_SYS_MAX_NAND_DEVICE
Signed-off-by: Tom Rini trini@konsulko.com --- configs/CHIP_pro_defconfig | 1 + configs/Nintendo_NES_Classic_Edition_defconfig | 1 + configs/etamin_defconfig | 1 + doc/README.nand | 3 --- drivers/mtd/nand/raw/Kconfig | 4 ++++ include/configs/M5329EVB.h | 1 - include/configs/M5373EVB.h | 1 - include/configs/MCR3000.h | 1 - include/configs/P1010RDB.h | 1 - include/configs/P2041RDB.h | 1 - include/configs/T102xRDB.h | 1 - include/configs/T104xRDB.h | 1 - include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240RDB.h | 1 - include/configs/at91sam9260ek.h | 1 - include/configs/at91sam9261ek.h | 1 - include/configs/at91sam9263ek.h | 1 - include/configs/at91sam9m10g45ek.h | 1 - include/configs/at91sam9n12ek.h | 1 - include/configs/at91sam9rlek.h | 1 - include/configs/at91sam9x5ek.h | 1 - include/configs/bk4r1.h | 1 - include/configs/broadcom_bcm963158.h | 4 ---- include/configs/broadcom_bcm96753ref.h | 4 ---- include/configs/broadcom_bcm968360bg.h | 4 ---- include/configs/broadcom_bcm968380gerg.h | 3 --- include/configs/broadcom_bcm968580xref.h | 4 ---- include/configs/cm_fx6.h | 1 - include/configs/colibri-imx6ull.h | 1 - include/configs/colibri_imx7.h | 1 - include/configs/colibri_t20.h | 1 - include/configs/colibri_vf.h | 1 - include/configs/comtrend_vr3032u.h | 3 --- include/configs/corvus.h | 1 - include/configs/da850evm.h | 1 - include/configs/devkit3250.h | 1 - include/configs/etamin.h | 2 -- include/configs/ethernut5.h | 1 - include/configs/gardena-smart-gateway-at91sam.h | 1 - include/configs/gw_ventana.h | 1 - include/configs/harmony.h | 1 - include/configs/imx27lite-common.h | 1 - include/configs/imx6-engicam.h | 1 - include/configs/imx6_logic.h | 1 - include/configs/imx6ulz_smm_m2.h | 1 - include/configs/imx8mn_bsh_smm_s2.h | 1 - include/configs/imx8mp_rsb3720.h | 1 - include/configs/km/km-mpc83xx.h | 1 - include/configs/km/pg-wcom-ls102xa.h | 1 - include/configs/kmcent2.h | 1 - include/configs/kmcoge5ne.h | 1 - include/configs/ls1021aqds.h | 1 - include/configs/ls1043aqds.h | 1 - include/configs/ls1043ardb.h | 1 - include/configs/ls1046afrwy.h | 1 - include/configs/ls1046aqds.h | 1 - include/configs/ls1046ardb.h | 1 - include/configs/ls1088aqds.h | 1 - include/configs/ls1088ardb.h | 1 - include/configs/ls2080aqds.h | 1 - include/configs/ls2080ardb.h | 1 - include/configs/m53menlo.h | 1 - include/configs/medcom-wide.h | 1 - include/configs/meesc.h | 1 - include/configs/mt7621.h | 1 - include/configs/mv-common.h | 3 --- include/configs/mvebu_armada-8k.h | 2 -- include/configs/mx6sabreauto.h | 1 - include/configs/mx6sxsabreauto.h | 1 - include/configs/mx7dsabresd.h | 1 - include/configs/mxs.h | 1 - include/configs/mys_6ulx.h | 1 - include/configs/npi_imx6ull.h | 1 - include/configs/octeontx_common.h | 4 ---- include/configs/omap3_beagle.h | 1 - include/configs/omap3_evm.h | 1 - include/configs/omap3_logic.h | 1 - include/configs/omapl138_lcdk.h | 1 - include/configs/p1_p2_rdb_pc.h | 1 - include/configs/pcl063.h | 1 - include/configs/pcl063_ull.h | 1 - include/configs/pcm052.h | 2 -- include/configs/pcm058.h | 1 - include/configs/plutux.h | 1 - include/configs/pm9261.h | 1 - include/configs/pm9263.h | 1 - include/configs/pm9g45.h | 1 - include/configs/presidio_asic.h | 1 - include/configs/sam9x60ek.h | 1 - include/configs/sama5d2_ptc_ek.h | 1 - include/configs/sama5d3_xplained.h | 1 - include/configs/sama5d3xek.h | 1 - include/configs/sama5d4_xplained.h | 1 - include/configs/sama5d4ek.h | 1 - include/configs/seaboard.h | 1 - include/configs/siemens-am33x-common.h | 2 -- include/configs/smartweb.h | 1 - include/configs/snapper9g45.h | 1 - include/configs/socfpga_common.h | 1 - include/configs/socrates.h | 1 - include/configs/stm32mp13_common.h | 1 - include/configs/stm32mp15_common.h | 1 - include/configs/sunxi-common.h | 1 - include/configs/taurus.h | 1 - include/configs/tec.h | 1 - include/configs/ti816x_evm.h | 1 - include/configs/ti_armv7_keystone2.h | 1 - include/configs/ti_armv7_omap.h | 1 - include/configs/uniphier.h | 1 - include/configs/usb_a9263.h | 1 - include/configs/vf610twr.h | 1 - include/configs/work_92105.h | 1 - include/configs/x530.h | 1 - include/configs/xilinx_zynqmp.h | 4 ---- include/configs/zynq-common.h | 4 ---- 116 files changed, 7 insertions(+), 145 deletions(-)
diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig index 29179601907a..5a12fbb8cdaa 100644 --- a/configs/CHIP_pro_defconfig +++ b/configs/CHIP_pro_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_I2C_SPEED=400000 # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y +CONFIG_SYS_MAX_NAND_DEVICE=8 CONFIG_SYS_NAND_BLOCK_SIZE=0x40000 CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_SYS_NAND_PAGE_SIZE=0x1000 diff --git a/configs/Nintendo_NES_Classic_Edition_defconfig b/configs/Nintendo_NES_Classic_Edition_defconfig index b66023418aec..89fb441cc738 100644 --- a/configs/Nintendo_NES_Classic_Edition_defconfig +++ b/configs/Nintendo_NES_Classic_Edition_defconfig @@ -14,6 +14,7 @@ CONFIG_CMD_MTDPARTS=y # CONFIG_MMC is not set CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y +CONFIG_SYS_MAX_NAND_DEVICE=8 CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_ONFI_DETECTION=y CONFIG_SYS_NAND_PAGE_SIZE=0x800 diff --git a/configs/etamin_defconfig b/configs/etamin_defconfig index af59b27445bf..8fb667f7dc22 100644 --- a/configs/etamin_defconfig +++ b/configs/etamin_defconfig @@ -98,6 +98,7 @@ CONFIG_MMC_OMAP_HS=y CONFIG_MTD=y CONFIG_MTD_CONCAT=y CONFIG_MTD_RAW_NAND=y +CONFIG_SYS_MAX_NAND_DEVICE=3 CONFIG_NAND_OMAP_ECCSCHEME_BCH16_CODE_HW=y CONFIG_SYS_NAND_BLOCK_SIZE=0x80000 CONFIG_SYS_NAND_ONFI_DETECTION=y diff --git a/doc/README.nand b/doc/README.nand index ffcea9079990..d1ce30768b92 100644 --- a/doc/README.nand +++ b/doc/README.nand @@ -99,9 +99,6 @@ Configuration Options: CONFIG_CMD_NAND_TORTURE Enables the torture command (see description of this command below).
- CONFIG_SYS_MAX_NAND_DEVICE - The maximum number of NAND devices you want to support. - CONFIG_SYS_NAND_MAX_ECCPOS If specified, overrides the maximum number of ECC bytes supported. Useful for reducing image size, especially with SPL. diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index ce67d1abde25..2c03676bf78b 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -26,6 +26,10 @@ config TPL_SYS_NAND_SELF_INIT config TPL_NAND_INIT bool
+config SYS_MAX_NAND_DEVICE + int "Maximum number of NAND devices to support" + default 1 + config SYS_NAND_DRIVER_ECC_LAYOUT bool "Omit standard ECC layouts to save space" help diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index a6c953f1a46c..474480cc1c24 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -95,7 +95,6 @@ #endif
#ifdef CONFIG_CMD_NAND -# define CONFIG_SYS_MAX_NAND_DEVICE 1 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE # define CONFIG_SYS_NAND_SIZE 1 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index f519bef24744..2e1c8579e909 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -96,7 +96,6 @@ # define CONFIG_SYS_FLASH_SIZE 0x800000 /* Max size that the board might have */ #endif
-# define CONFIG_SYS_MAX_NAND_DEVICE 1 # define CONFIG_SYS_NAND_BASE CONFIG_SYS_CS2_BASE # define CONFIG_SYS_NAND_SIZE 1 # define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h index 4b47c564418c..a861ddb5bdd1 100644 --- a/include/configs/MCR3000.h +++ b/include/configs/MCR3000.h @@ -83,7 +83,6 @@ /* Ethernet configuration part */
/* NAND configuration part */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x0C000000
#endif /* __CONFIG_H */ diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index b87118c1ed26..88d9bec9d927 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -202,7 +202,6 @@ extern unsigned long get_sdram_size(void); #endif
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1
#if defined(CONFIG_TARGET_P1010RDB_PA) /* NAND Flash Timing Params */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 044e2d0d42b5..4a2546213d0b 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -119,7 +119,6 @@ #endif
#define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE} -#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* NAND flash config */ #define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index a15121cc4dae..cbe572153468 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -236,7 +236,6 @@
#define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1
#if defined(CONFIG_MTD_RAW_NAND) #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 751f6c7db8ef..269c55405695 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -212,7 +212,6 @@
#define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1
#if defined(CONFIG_MTD_RAW_NAND) #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 59edb5013510..d3b2c448abd9 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -200,7 +200,6 @@
#define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1
#if defined(CONFIG_MTD_RAW_NAND) #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index b765cbbadc41..b3abe56410a2 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -176,7 +176,6 @@
#define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1
#if defined(CONFIG_MTD_RAW_NAND) #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 61f3b98b7dc6..4b20705db0ff 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -235,7 +235,6 @@
#define CONFIG_SYS_NAND_DDR_LAW 11 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1
#if defined(CONFIG_MTD_RAW_NAND) #define CONFIG_SYS_CSPR0_EXT CONFIG_SYS_NAND_CSPR_EXT diff --git a/include/configs/at91sam9260ek.h b/include/configs/at91sam9260ek.h index ef9335c523f4..69aa0357b566 100644 --- a/include/configs/at91sam9260ek.h +++ b/include/configs/at91sam9260ek.h @@ -43,7 +43,6 @@
/* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) diff --git a/include/configs/at91sam9261ek.h b/include/configs/at91sam9261ek.h index 12726c10bd6d..12e36b236e54 100644 --- a/include/configs/at91sam9261ek.h +++ b/include/configs/at91sam9261ek.h @@ -31,7 +31,6 @@
/* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD22 */ diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index 4d32e55c642e..3bbc37ec5921 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -159,7 +159,6 @@
/* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index b55d2e392553..4409179e123f 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -25,7 +25,6 @@
/* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 4d492988eba7..0a0074c5a057 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -26,7 +26,6 @@
/* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) diff --git a/include/configs/at91sam9rlek.h b/include/configs/at91sam9rlek.h index e418edddfbe5..f39df708799b 100644 --- a/include/configs/at91sam9rlek.h +++ b/include/configs/at91sam9rlek.h @@ -32,7 +32,6 @@
/* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 0e7665843dba..71246ce0e2bc 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -27,7 +27,6 @@
/* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ diff --git a/include/configs/bk4r1.h b/include/configs/bk4r1.h index b3e1fddc02fc..ca2bc1907e39 100644 --- a/include/configs/bk4r1.h +++ b/include/configs/bk4r1.h @@ -51,7 +51,6 @@ #include <linux/sizes.h>
/* NAND support */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define IMX_FEC1_BASE ENET1_BASE_ADDR
diff --git a/include/configs/broadcom_bcm963158.h b/include/configs/broadcom_bcm963158.h index 0c8d352be97c..ca3f6f7446aa 100644 --- a/include/configs/broadcom_bcm963158.h +++ b/include/configs/broadcom_bcm963158.h @@ -23,10 +23,6 @@
/* U-Boot */
-#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#endif /* CONFIG_MTD_RAW_NAND */ - /* * bcm963158 */ diff --git a/include/configs/broadcom_bcm96753ref.h b/include/configs/broadcom_bcm96753ref.h index 33c70c73c1fc..6af8226f8bcd 100644 --- a/include/configs/broadcom_bcm96753ref.h +++ b/include/configs/broadcom_bcm96753ref.h @@ -23,10 +23,6 @@
/* U-Boot */
-#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#endif /* CONFIG_MTD_RAW_NAND */ - /* * 96753ref */ diff --git a/include/configs/broadcom_bcm968360bg.h b/include/configs/broadcom_bcm968360bg.h index 8a8023571236..67b68e451749 100644 --- a/include/configs/broadcom_bcm968360bg.h +++ b/include/configs/broadcom_bcm968360bg.h @@ -23,10 +23,6 @@
/* U-Boot */
-#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#endif /* CONFIG_MTD_RAW_NAND */ - /* * 968360bg */ diff --git a/include/configs/broadcom_bcm968380gerg.h b/include/configs/broadcom_bcm968380gerg.h index c1c1b37fabd9..bad143981a70 100644 --- a/include/configs/broadcom_bcm968380gerg.h +++ b/include/configs/broadcom_bcm968380gerg.h @@ -6,6 +6,3 @@ #include <configs/bmips_common.h> #include <configs/bmips_bcm6838.h>
-#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#endif /* CONFIG_MTD_RAW_NAND */ diff --git a/include/configs/broadcom_bcm968580xref.h b/include/configs/broadcom_bcm968580xref.h index abc2da3d1fe3..6a7f4d150778 100644 --- a/include/configs/broadcom_bcm968580xref.h +++ b/include/configs/broadcom_bcm968580xref.h @@ -23,10 +23,6 @@
/* U-Boot */
-#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#endif /* CONFIG_MTD_RAW_NAND */ - /* * 968580xref */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index cbba72644002..e5e8c13090a8 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -129,7 +129,6 @@
/* NAND */ #define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* APBH DMA is required for NAND support */
/* Ethernet */ diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 79b1284cc7a9..2d29503a985d 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -122,7 +122,6 @@
#ifdef CONFIG_TARGET_COLIBRI_IMX6ULL_NAND /* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* used to initialize CONFIG_SYS_NAND_BASE_LIST which is unused */ #define CONFIG_SYS_NAND_BASE -1 #endif diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index b8d0dc959a73..c95b732f8dcc 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -166,7 +166,6 @@
#ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND /* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_MX7_GPMI_62_ECC_BYTES #endif diff --git a/include/configs/colibri_t20.h b/include/configs/colibri_t20.h index 73d18444215a..b758086b86d5 100644 --- a/include/configs/colibri_t20.h +++ b/include/configs/colibri_t20.h @@ -16,7 +16,6 @@ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTA_BASE
/* NAND support */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define UBOOT_UPDATE \ "update_uboot=nand erase.part u-boot && " \ diff --git a/include/configs/colibri_vf.h b/include/configs/colibri_vf.h index 268afbb7fa38..0f6f99d244f9 100644 --- a/include/configs/colibri_vf.h +++ b/include/configs/colibri_vf.h @@ -15,7 +15,6 @@ #include <linux/sizes.h>
/* NAND support */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_IPADDR 192.168.10.2 #define CONFIG_NETMASK 255.255.255.0 diff --git a/include/configs/comtrend_vr3032u.h b/include/configs/comtrend_vr3032u.h index a46b3946bf53..e8b0724988ff 100644 --- a/include/configs/comtrend_vr3032u.h +++ b/include/configs/comtrend_vr3032u.h @@ -6,6 +6,3 @@ #include <configs/bmips_common.h> #include <configs/bmips_bcm63268.h>
-#ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#endif /* CONFIG_MTD_RAW_NAND */ diff --git a/include/configs/corvus.h b/include/configs/corvus.h index 698da6b6dac8..23276fc431df 100644 --- a/include/configs/corvus.h +++ b/include/configs/corvus.h @@ -37,7 +37,6 @@
/* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 58c902431d13..3625f923a5c1 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -114,7 +114,6 @@ #define CONFIG_SYS_NAND_MASK_CLE 0x10 #define CONFIG_SYS_NAND_MASK_ALE 0x8 #undef CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x40000 #define CONFIG_SYS_NAND_U_BOOT_DST 0xc1080000 diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 7916ca8a6cd4..03adae8e18f9 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -36,7 +36,6 @@ * NAND controller */ #define CONFIG_SYS_NAND_BASE SLC_NAND_BASE -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
/* diff --git a/include/configs/etamin.h b/include/configs/etamin.h index 7923fbb599d1..75322a37322c 100644 --- a/include/configs/etamin.h +++ b/include/configs/etamin.h @@ -45,8 +45,6 @@ #define CONFIG_SYS_NAND_ECCSIZE 512 #define CONFIG_SYS_NAND_ECCBYTES 26
-#undef CONFIG_SYS_MAX_NAND_DEVICE -#define CONFIG_SYS_MAX_NAND_DEVICE 3 #define CONFIG_SYS_NAND_BASE2 (0x18000000) /* physical address */ #define CONFIG_SYS_NAND_BASE_LIST {CONFIG_SYS_NAND_BASE, \ CONFIG_SYS_NAND_BASE2} diff --git a/include/configs/ethernut5.h b/include/configs/ethernut5.h index 7a3c800dca9c..22647abee0d3 100644 --- a/include/configs/ethernut5.h +++ b/include/configs/ethernut5.h @@ -37,7 +37,6 @@
/* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h index 331e9ca8ba19..39fc7b36663c 100644 --- a/include/configs/gardena-smart-gateway-at91sam.h +++ b/include/configs/gardena-smart-gateway-at91sam.h @@ -22,7 +22,6 @@ #define CONFIG_SYS_SDRAM_SIZE 0x08000000 /* 128 megs */
/* NAND flash */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 82076ff74ff6..7300fcd90ba9 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -20,7 +20,6 @@ #define CONFIG_MXC_UART_BASE UART2_BASE
/* NAND */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0 diff --git a/include/configs/harmony.h b/include/configs/harmony.h index 879bd5c9539a..fe4b02c0ce2c 100644 --- a/include/configs/harmony.h +++ b/include/configs/harmony.h @@ -24,7 +24,6 @@ #endif
/* NAND support */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Environment in NAND (which is 512M), aligned to start of last sector */
diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 6ebdc3d6f976..40428452954a 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -97,7 +97,6 @@ * NAND */ #define CONFIG_MXC_NAND_REGS_BASE 0xd8000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0xd8000000 #define CONFIG_MXC_NAND_HWECC
diff --git a/include/configs/imx6-engicam.h b/include/configs/imx6-engicam.h index a2d5080a10e4..55e2eb78b25b 100644 --- a/include/configs/imx6-engicam.h +++ b/include/configs/imx6-engicam.h @@ -126,7 +126,6 @@
/* NAND */ #ifdef CONFIG_NAND_MXS -# define CONFIG_SYS_MAX_NAND_DEVICE 1 # define CONFIG_SYS_NAND_BASE 0x40000000 # define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 2913549c8835..619399366a23 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -116,7 +116,6 @@ /* Environment organization */
/* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/imx6ulz_smm_m2.h b/include/configs/imx6ulz_smm_m2.h index 50885c53b3bd..46a96f1f828e 100644 --- a/include/configs/imx6ulz_smm_m2.h +++ b/include/configs/imx6ulz_smm_m2.h @@ -71,7 +71,6 @@ #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x20000000
diff --git a/include/configs/imx8mn_bsh_smm_s2.h b/include/configs/imx8mn_bsh_smm_s2.h index c6b296281424..a2323bd6716f 100644 --- a/include/configs/imx8mn_bsh_smm_s2.h +++ b/include/configs/imx8mn_bsh_smm_s2.h @@ -43,7 +43,6 @@ #define PHYS_SDRAM_SIZE SZ_256M
/* NAND */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BASE 0x20000000
diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index ddc035ae2286..8eb7456f94ed 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -171,7 +171,6 @@ #ifdef CONFIG_NAND_MXS
/* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x20000000 #endif /* CONFIG_NAND_MXS */
diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index 61c713459543..f05aeaca24fb 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -60,7 +60,6 @@
#if defined(CONFIG_CMD_NAND) #define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE #endif
diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 9565cea083e0..1f5a025017d5 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -119,7 +119,6 @@ #define CONFIG_SYS_CS1_FTIM2 CONFIG_SYS_NAND_FTIM2 #define CONFIG_SYS_CS1_FTIM3 CONFIG_SYS_NAND_FTIM3
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE }
/* QRIO FPGA Definitions */ diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index e5cc62ebdc27..6032f3913cc7 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -277,7 +277,6 @@
/* More NAND Flash Params */ #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* QRIO on IFC CS2 */ #define CONFIG_SYS_QRIO_BASE 0xfb000000 diff --git a/include/configs/kmcoge5ne.h b/include/configs/kmcoge5ne.h index b9d20c9c8eb9..d6b60d8139a3 100644 --- a/include/configs/kmcoge5ne.h +++ b/include/configs/kmcoge5ne.h @@ -11,7 +11,6 @@ #define CONFIG_HOSTNAME "kmcoge5ne" #define CONFIG_NAND_ECC_BCH #define CONFIG_NAND_KMETER1 -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define NAND_MAX_CHIPS 1 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index d383b6c655b8..4281a2637287 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -107,7 +107,6 @@ #define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #endif
/* diff --git a/include/configs/ls1043aqds.h b/include/configs/ls1043aqds.h index 4158d15cc0fc..d207e475fc06 100644 --- a/include/configs/ls1043aqds.h +++ b/include/configs/ls1043aqds.h @@ -111,7 +111,6 @@ #define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #endif
diff --git a/include/configs/ls1043ardb.h b/include/configs/ls1043ardb.h index 4bfe4e3ecd05..206de7e1380c 100644 --- a/include/configs/ls1043ardb.h +++ b/include/configs/ls1043ardb.h @@ -82,7 +82,6 @@ #define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE
#ifdef CONFIG_NAND_BOOT diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index 2df5f3f6c0bd..582b1ee93cd0 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -45,7 +45,6 @@ #define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE
/* IFC Timing Params */ diff --git a/include/configs/ls1046aqds.h b/include/configs/ls1046aqds.h index 1f54e5164551..1a2faff900d0 100644 --- a/include/configs/ls1046aqds.h +++ b/include/configs/ls1046aqds.h @@ -127,7 +127,6 @@ #define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE #endif
diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index 5d329577a631..f5f16bae2d60 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -50,7 +50,6 @@ #define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE
/* diff --git a/include/configs/ls1088aqds.h b/include/configs/ls1088aqds.h index 2d3351e6b4fb..d50b76b89ae5 100644 --- a/include/configs/ls1088aqds.h +++ b/include/configs/ls1088aqds.h @@ -102,7 +102,6 @@ #define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index d98ed39812a7..4edf40b0b722 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -86,7 +86,6 @@ #define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE
#define CONFIG_SYS_I2C_FPGA_ADDR 0x66 diff --git a/include/configs/ls2080aqds.h b/include/configs/ls2080aqds.h index d02d7fc58867..1fa4aa3734d1 100644 --- a/include/configs/ls2080aqds.h +++ b/include/configs/ls2080aqds.h @@ -103,7 +103,6 @@ #define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE
#define QIXIS_LBMAP_SWITCH 0x06 diff --git a/include/configs/ls2080ardb.h b/include/configs/ls2080ardb.h index 09484dc6094b..e1c66c5dcc0d 100644 --- a/include/configs/ls2080ardb.h +++ b/include/configs/ls2080ardb.h @@ -100,7 +100,6 @@ #define CONFIG_SYS_NAND_FTIM3 0x0
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_MTD_NAND_VERIFY_WRITE
#define QIXIS_LBMAP_SWITCH 0x06 diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index 31a3e04bcbb0..bf1560b23b95 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -44,7 +44,6 @@ * NAND */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR_AXI #define CONFIG_MXC_NAND_REGS_BASE NFC_BASE_ADDR_AXI #define CONFIG_MXC_NAND_IP_REGS_BASE NFC_BASE_ADDR diff --git a/include/configs/medcom-wide.h b/include/configs/medcom-wide.h index b35ba59aba99..b90a84da8ad7 100644 --- a/include/configs/medcom-wide.h +++ b/include/configs/medcom-wide.h @@ -19,7 +19,6 @@ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* NAND support */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Environment in NAND, aligned to start of last sector */
diff --git a/include/configs/meesc.h b/include/configs/meesc.h index 6b2296788dc7..5cf95a7ff1af 100644 --- a/include/configs/meesc.h +++ b/include/configs/meesc.h @@ -52,7 +52,6 @@
/* NAND flash */ #ifdef CONFIG_CMD_NAND -# define CONFIG_SYS_MAX_NAND_DEVICE 1 # define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* 0x40000000 */ # define CONFIG_SYS_NAND_DBW_8 # define CONFIG_SYS_NAND_MASK_ALE (1 << 21) diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index 1f6899708033..86e48f93349d 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -23,7 +23,6 @@ #define MMC_SUPPORTS_TUNING
/* NAND */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Serial SPL */ #if defined(CONFIG_SPL_BUILD) && defined(CONFIG_SPL_SERIAL) diff --git a/include/configs/mv-common.h b/include/configs/mv-common.h index 384a8f7d1dd8..9c0eb41b7872 100644 --- a/include/configs/mv-common.h +++ b/include/configs/mv-common.h @@ -61,8 +61,5 @@ /* * Common NAND configuration */ -#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#endif
#endif /* _MV_COMMON_H */ diff --git a/include/configs/mvebu_armada-8k.h b/include/configs/mvebu_armada-8k.h index 5a956f0a3e36..5debd9117c6e 100644 --- a/include/configs/mvebu_armada-8k.h +++ b/include/configs/mvebu_armada-8k.h @@ -25,8 +25,6 @@
/* When runtime detection fails this is the default */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 - /* USB ethernet */
/* diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index c76e7ea1605a..7e54bb2312bc 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -36,7 +36,6 @@ #define CONFIG_SYS_FSL_USDHC_NUM 2
/* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000
/* DMA stuff, needed for GPMI/MXS NAND support */ diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index c87804140046..407b64383ee6 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -86,7 +86,6 @@ #define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
/* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000
/* DMA stuff, needed for GPMI/MXS NAND support */ diff --git a/include/configs/mx7dsabresd.h b/include/configs/mx7dsabresd.h index b96341a587c4..2a97d2fac465 100644 --- a/include/configs/mx7dsabresd.h +++ b/include/configs/mx7dsabresd.h @@ -93,7 +93,6 @@ */ #ifdef CONFIG_NAND_MXS /* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000
/* DMA stuff, needed for GPMI/MXS NAND support */ diff --git a/include/configs/mxs.h b/include/configs/mxs.h index fc15ed82c6ed..e8610386f04e 100644 --- a/include/configs/mxs.h +++ b/include/configs/mxs.h @@ -83,7 +83,6 @@
/* NAND */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x60000000 #endif
diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index 4162ee8caa21..bb68ddbd39da 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -30,7 +30,6 @@ #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000
/* USB Configs */ diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 217427a302e7..8ff26feb741d 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -31,7 +31,6 @@ #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000
/* USB Configs */ diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h index e7a6bd41db05..b5d8cc15ac77 100644 --- a/include/configs/octeontx_common.h +++ b/include/configs/octeontx_common.h @@ -46,8 +46,4 @@
/** EMMC specific defines */
-#if defined(CONFIG_NAND_OCTEONTX) -#define CONFIG_SYS_MAX_NAND_DEVICE 8 -#endif - #endif /* __OCTEONTX_COMMON_H__ */ diff --git a/include/configs/omap3_beagle.h b/include/configs/omap3_beagle.h index ad3dbbcac52f..d46ca337d5f8 100644 --- a/include/configs/omap3_beagle.h +++ b/include/configs/omap3_beagle.h @@ -21,7 +21,6 @@ /* NAND */ #if defined(CONFIG_MTD_RAW_NAND) #define CONFIG_SYS_FLASH_BASE NAND_BASE -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 diff --git a/include/configs/omap3_evm.h b/include/configs/omap3_evm.h index c47d5573c46a..77629d7fc1ea 100644 --- a/include/configs/omap3_evm.h +++ b/include/configs/omap3_evm.h @@ -26,7 +26,6 @@ /* NAND */ #if defined(CONFIG_MTD_RAW_NAND) #define CONFIG_SYS_FLASH_BASE NAND_BASE -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ 10, 11, 12, 13} #define CONFIG_SYS_NAND_ECCSIZE 512 diff --git a/include/configs/omap3_logic.h b/include/configs/omap3_logic.h index 1af87b271c4f..442a3cad2206 100644 --- a/include/configs/omap3_logic.h +++ b/include/configs/omap3_logic.h @@ -16,7 +16,6 @@
/* Board NAND Info. */ #ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of */ /* NAND devices */ #define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9, 10, 11, 12, \ 13, 14, 16, 17, 18, 19, 20, 21, 22, \ diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index c644768ae7d7..df4a16fd0815 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -112,7 +112,6 @@ #define CONFIG_SYS_NAND_MASK_CLE 0x10 #define CONFIG_SYS_NAND_MASK_ALE 0x8 #undef CONFIG_SYS_NAND_HW_ECC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ #define CONFIG_SYS_NAND_HW_ECC_OOBFIRST #define CONFIG_NAND_6BYTES_OOB_FREE_10BYTES_ECC #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 448fc3bb0654..da3b18e99889 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -215,7 +215,6 @@ #endif
#define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } -#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \ | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \ diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 6e593da936cd..5b38a94aa5d1 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -42,7 +42,6 @@ #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000
/* USB Configs */ diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index ae81b8e214e2..688d161964a4 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -44,7 +44,6 @@ #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* NAND */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000
/* USB Configs */ diff --git a/include/configs/pcm052.h b/include/configs/pcm052.h index a8cfec965959..a04a03a7e181 100644 --- a/include/configs/pcm052.h +++ b/include/configs/pcm052.h @@ -14,8 +14,6 @@
/* NAND support */
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 - /* if no target-specific extra environment settings were defined by the target, define an empty one */ #ifndef PCM052_EXTRA_ENV_SETTINGS diff --git a/include/configs/pcm058.h b/include/configs/pcm058.h index cff71df1c962..01190904cf6f 100644 --- a/include/configs/pcm058.h +++ b/include/configs/pcm058.h @@ -15,7 +15,6 @@ #define PHYS_SDRAM_SIZE (1u * 1024 * 1024 * 1024)
/* Enable NAND support */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/plutux.h b/include/configs/plutux.h index 9a4a632a521d..09f0ed9b9a1b 100644 --- a/include/configs/plutux.h +++ b/include/configs/plutux.h @@ -19,7 +19,6 @@ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* NAND support */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Environment in NAND, aligned to start of last sector */
diff --git a/include/configs/pm9261.h b/include/configs/pm9261.h index 797e44f844de..e0b83cb6bab9 100644 --- a/include/configs/pm9261.h +++ b/include/configs/pm9261.h @@ -136,7 +136,6 @@ #define PHYS_SDRAM_SIZE 0x04000000 /* 64 megs */
/* NAND flash */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD22 */ diff --git a/include/configs/pm9263.h b/include/configs/pm9263.h index bb5bd8b60646..91794e0190b9 100644 --- a/include/configs/pm9263.h +++ b/include/configs/pm9263.h @@ -152,7 +152,6 @@
/* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_DBW_8 1 /* our ALE is AD21 */ diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index 69f3d0658784..fa47a3ed7935 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -25,7 +25,6 @@
/* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 /* our ALE is AD21 */ diff --git a/include/configs/presidio_asic.h b/include/configs/presidio_asic.h index 90f548cc6c13..ebf5467ef41e 100644 --- a/include/configs/presidio_asic.h +++ b/include/configs/presidio_asic.h @@ -58,7 +58,6 @@
/* nand driver parameters */ #ifdef CONFIG_TARGET_PRESIDIO_ASIC - #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_NAND_BASE_LIST { CONFIG_SYS_NAND_BASE } #endif diff --git a/include/configs/sam9x60ek.h b/include/configs/sam9x60ek.h index b9b56d9f1a04..70c6ec5b65c6 100644 --- a/include/configs/sam9x60ek.h +++ b/include/configs/sam9x60ek.h @@ -28,7 +28,6 @@
/* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 #define CONFIG_SYS_NAND_MASK_ALE BIT(21) #define CONFIG_SYS_NAND_MASK_CLE BIT(22) diff --git a/include/configs/sama5d2_ptc_ek.h b/include/configs/sama5d2_ptc_ek.h index 3b91e83683a6..9281c7ccc402 100644 --- a/include/configs/sama5d2_ptc_ek.h +++ b/include/configs/sama5d2_ptc_ek.h @@ -21,7 +21,6 @@
/* NAND Flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE BIT(21) diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index fad65cb11234..301e8c900c4b 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -29,7 +29,6 @@
/* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x60000000 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index b48e40bee440..e211aa52ed0e 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -41,7 +41,6 @@
/* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x60000000 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index d5cd45ca5c3a..eac41449cb00 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -17,7 +17,6 @@
/* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x80000000 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index 411ed29ab3cb..bc5312d32c6b 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -17,7 +17,6 @@
/* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x80000000 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) diff --git a/include/configs/seaboard.h b/include/configs/seaboard.h index e6c200f76122..c7f03a1e7543 100644 --- a/include/configs/seaboard.h +++ b/include/configs/seaboard.h @@ -29,7 +29,6 @@ /* NAND support */
/* Max number of NAND devices */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1
#include "tegra-common-post.h"
diff --git a/include/configs/siemens-am33x-common.h b/include/configs/siemens-am33x-common.h index fcb0fd5cec3b..d822f3985456 100644 --- a/include/configs/siemens-am33x-common.h +++ b/include/configs/siemens-am33x-common.h @@ -368,8 +368,6 @@ #define CONFIG_SYS_NAND_BASE (0x08000000) /* physical address */ /* to access nand at */ /* CS0 */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND - devices */ #endif
#endif /* ! __CONFIG_SIEMENS_AM33X_COMMON_H */ diff --git a/include/configs/smartweb.h b/include/configs/smartweb.h index 1a3ac817fbfc..15a86c5b67a4 100644 --- a/include/configs/smartweb.h +++ b/include/configs/smartweb.h @@ -54,7 +54,6 @@ */
/* NAND flash settings */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) diff --git a/include/configs/snapper9g45.h b/include/configs/snapper9g45.h index 59bba7d143e2..c56fb378312b 100644 --- a/include/configs/snapper9g45.h +++ b/include/configs/snapper9g45.h @@ -30,7 +30,6 @@
/* NAND Flash */ #define CONFIG_SYS_NAND_ECC_BASE ATMEL_BASE_ECC -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index c3f30afe2b55..f0a33ed27dd5 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -80,7 +80,6 @@ * NAND Support */ #ifdef CONFIG_NAND_DENALI -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS #define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS #endif diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 00e8136cc9c0..122aec2287f4 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -102,7 +102,6 @@ #define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70) -#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* LIME GDC */ #define CONFIG_SYS_LIME_BASE 0xc8000000 diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h index 78089b965ae4..222e69c20c01 100644 --- a/include/configs/stm32mp13_common.h +++ b/include/configs/stm32mp13_common.h @@ -25,7 +25,6 @@ #define CONFIG_SYS_MMC_MAX_DEVICE 2
/* NAND support */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1
/*****************************************************************************/ #ifdef CONFIG_DISTRO_DEFAULTS diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index bd8e16bc1b99..9dad2a8ebdca 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -25,7 +25,6 @@ #define CONFIG_SYS_MMC_MAX_DEVICE 3
/* NAND support */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Ethernet need */ #ifdef CONFIG_DWC_ETH_QOS diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index fe90d55bd454..93a56b5c575b 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -73,7 +73,6 @@
#ifdef CONFIG_NAND_SUNXI #define CONFIG_SYS_NAND_MAX_ECCPOS 1664 -#define CONFIG_SYS_MAX_NAND_DEVICE 8 #endif
/* mmc config */ diff --git a/include/configs/taurus.h b/include/configs/taurus.h index 4758e23f5572..8d0b73e089d2 100644 --- a/include/configs/taurus.h +++ b/include/configs/taurus.h @@ -54,7 +54,6 @@
/* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 #define CONFIG_SYS_NAND_DBW_8 #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) diff --git a/include/configs/tec.h b/include/configs/tec.h index 432ccbdc32b9..2377b47e0541 100644 --- a/include/configs/tec.h +++ b/include/configs/tec.h @@ -19,7 +19,6 @@ #define CONFIG_SYS_NS16550_COM1 NV_PA_APB_UARTD_BASE
/* NAND support */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* Environment in NAND, aligned to start of last sector */
diff --git a/include/configs/ti816x_evm.h b/include/configs/ti816x_evm.h index 1aca83a9bceb..82add65ec0dd 100644 --- a/include/configs/ti816x_evm.h +++ b/include/configs/ti816x_evm.h @@ -43,7 +43,6 @@ * access CS0 at is 0x8000000. */ #define CONFIG_SYS_NAND_BASE 0x8000000 -#define CONFIG_SYS_MAX_NAND_DEVICE 1
/* NAND: SPL related configs */
diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 29a6038f8985..4078413d0f51 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -69,7 +69,6 @@
#define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, } -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_NO_SUBPAGE_WRITE
#define DFU_ALT_INFO_MMC \ diff --git a/include/configs/ti_armv7_omap.h b/include/configs/ti_armv7_omap.h index 727c6483193a..44706c7733a0 100644 --- a/include/configs/ti_armv7_omap.h +++ b/include/configs/ti_armv7_omap.h @@ -19,7 +19,6 @@ #ifndef CONFIG_SYS_NAND_BASE #define CONFIG_SYS_NAND_BASE 0x8000000 #endif -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #endif
/* Now for the remaining common defines */ diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index d9e95abcc121..b92fe3894214 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -42,7 +42,6 @@ #define CONFIG_SYS_TIMER_RATE 1000000 #endif
-#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_REGS_BASE 0x68100000 #define CONFIG_SYS_NAND_DATA_BASE 0x68000000
diff --git a/include/configs/usb_a9263.h b/include/configs/usb_a9263.h index e0dde1cc8365..44eaeda432a7 100644 --- a/include/configs/usb_a9263.h +++ b/include/configs/usb_a9263.h @@ -33,7 +33,6 @@
/* NAND flash */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 /* our ALE is AD21 */ #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index c13f2ba196e6..dde6d130caa6 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -14,7 +14,6 @@ /* NAND support */
#ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE NFC_BASE_ADDR
/* Dynamic MTD partition support */ diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 8d1eee2fcac8..9164f818e9a9 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -42,7 +42,6 @@ */
/* driver configuration */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_MAX_NAND_CHIPS 1 #define CONFIG_SYS_NAND_BASE MLC_NAND_BASE
diff --git a/include/configs/x530.h b/include/configs/x530.h index cb126837b9ca..0add626e81a5 100644 --- a/include/configs/x530.h +++ b/include/configs/x530.h @@ -27,7 +27,6 @@ */
/* NAND */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define BBT_CUSTOM_SCAN #define BBT_CUSTOM_SCAN_PAGE 0 diff --git a/include/configs/xilinx_zynqmp.h b/include/configs/xilinx_zynqmp.h index f72f3e644768..60f007a10fcd 100644 --- a/include/configs/xilinx_zynqmp.h +++ b/include/configs/xilinx_zynqmp.h @@ -27,10 +27,6 @@ EFI_GUID(0xcf9ecfd4, 0x938b, 0x41c5, 0x85, 0x51, \ 0x1f, 0x88, 0x3a, 0xb7, 0xdc, 0x18)
-#ifdef CONFIG_NAND_ARASAN -# define CONFIG_SYS_MAX_NAND_DEVICE 1 -#endif - /* Miscellaneous configurable options */
#if defined(CONFIG_ZYNQMP_USB) diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index dc0cba001036..e194e77e5b77 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -40,10 +40,6 @@ # define CONFIG_FLASH_SHOW_PROGRESS 10 #endif
-#ifdef CONFIG_NAND_ZYNQ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#endif - #ifdef CONFIG_USB_EHCI_ZYNQ # define DFU_DEFAULT_POLL_TIMEOUT 300 # define CONFIG_THOR_RESET_OFF
Hi Tom,
On Fri, 28 Oct 2022 at 18:29, Tom Rini trini@konsulko.com wrote:
This converts the following to Kconfig: CONFIG_SYS_MAX_NAND_DEVICE
Signed-off-by: Tom Rini trini@konsulko.com
configs/CHIP_pro_defconfig | 1 + configs/Nintendo_NES_Classic_Edition_defconfig | 1 + configs/etamin_defconfig | 1 + doc/README.nand | 3 --- drivers/mtd/nand/raw/Kconfig | 4 ++++ include/configs/M5329EVB.h | 1 - include/configs/M5373EVB.h | 1 - include/configs/MCR3000.h | 1 - include/configs/P1010RDB.h | 1 - include/configs/P2041RDB.h | 1 - include/configs/T102xRDB.h | 1 - include/configs/T104xRDB.h | 1 - include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240RDB.h | 1 - include/configs/at91sam9260ek.h | 1 - include/configs/at91sam9261ek.h | 1 - include/configs/at91sam9263ek.h | 1 - include/configs/at91sam9m10g45ek.h | 1 - include/configs/at91sam9n12ek.h | 1 - include/configs/at91sam9rlek.h | 1 - include/configs/at91sam9x5ek.h | 1 - include/configs/bk4r1.h | 1 - include/configs/broadcom_bcm963158.h | 4 ---- include/configs/broadcom_bcm96753ref.h | 4 ---- include/configs/broadcom_bcm968360bg.h | 4 ---- include/configs/broadcom_bcm968380gerg.h | 3 --- include/configs/broadcom_bcm968580xref.h | 4 ---- include/configs/cm_fx6.h | 1 - include/configs/colibri-imx6ull.h | 1 - include/configs/colibri_imx7.h | 1 - include/configs/colibri_t20.h | 1 - include/configs/colibri_vf.h | 1 - include/configs/comtrend_vr3032u.h | 3 --- include/configs/corvus.h | 1 - include/configs/da850evm.h | 1 - include/configs/devkit3250.h | 1 - include/configs/etamin.h | 2 -- include/configs/ethernut5.h | 1 - include/configs/gardena-smart-gateway-at91sam.h | 1 - include/configs/gw_ventana.h | 1 - include/configs/harmony.h | 1 - include/configs/imx27lite-common.h | 1 - include/configs/imx6-engicam.h | 1 - include/configs/imx6_logic.h | 1 - include/configs/imx6ulz_smm_m2.h | 1 - include/configs/imx8mn_bsh_smm_s2.h | 1 - include/configs/imx8mp_rsb3720.h | 1 - include/configs/km/km-mpc83xx.h | 1 - include/configs/km/pg-wcom-ls102xa.h | 1 - include/configs/kmcent2.h | 1 - include/configs/kmcoge5ne.h | 1 - include/configs/ls1021aqds.h | 1 - include/configs/ls1043aqds.h | 1 - include/configs/ls1043ardb.h | 1 - include/configs/ls1046afrwy.h | 1 - include/configs/ls1046aqds.h | 1 - include/configs/ls1046ardb.h | 1 - include/configs/ls1088aqds.h | 1 - include/configs/ls1088ardb.h | 1 - include/configs/ls2080aqds.h | 1 - include/configs/ls2080ardb.h | 1 - include/configs/m53menlo.h | 1 - include/configs/medcom-wide.h | 1 - include/configs/meesc.h | 1 - include/configs/mt7621.h | 1 - include/configs/mv-common.h | 3 --- include/configs/mvebu_armada-8k.h | 2 -- include/configs/mx6sabreauto.h | 1 - include/configs/mx6sxsabreauto.h | 1 - include/configs/mx7dsabresd.h | 1 - include/configs/mxs.h | 1 - include/configs/mys_6ulx.h | 1 - include/configs/npi_imx6ull.h | 1 - include/configs/octeontx_common.h | 4 ---- include/configs/omap3_beagle.h | 1 - include/configs/omap3_evm.h | 1 - include/configs/omap3_logic.h | 1 - include/configs/omapl138_lcdk.h | 1 - include/configs/p1_p2_rdb_pc.h | 1 - include/configs/pcl063.h | 1 - include/configs/pcl063_ull.h | 1 - include/configs/pcm052.h | 2 -- include/configs/pcm058.h | 1 - include/configs/plutux.h | 1 - include/configs/pm9261.h | 1 - include/configs/pm9263.h | 1 - include/configs/pm9g45.h | 1 - include/configs/presidio_asic.h | 1 - include/configs/sam9x60ek.h | 1 - include/configs/sama5d2_ptc_ek.h | 1 - include/configs/sama5d3_xplained.h | 1 - include/configs/sama5d3xek.h | 1 - include/configs/sama5d4_xplained.h | 1 - include/configs/sama5d4ek.h | 1 - include/configs/seaboard.h | 1 - include/configs/siemens-am33x-common.h | 2 -- include/configs/smartweb.h | 1 - include/configs/snapper9g45.h | 1 - include/configs/socfpga_common.h | 1 - include/configs/socrates.h | 1 - include/configs/stm32mp13_common.h | 1 - include/configs/stm32mp15_common.h | 1 - include/configs/sunxi-common.h | 1 - include/configs/taurus.h | 1 - include/configs/tec.h | 1 - include/configs/ti816x_evm.h | 1 - include/configs/ti_armv7_keystone2.h | 1 - include/configs/ti_armv7_omap.h | 1 - include/configs/uniphier.h | 1 - include/configs/usb_a9263.h | 1 - include/configs/vf610twr.h | 1 - include/configs/work_92105.h | 1 - include/configs/x530.h | 1 - include/configs/xilinx_zynqmp.h | 4 ---- include/configs/zynq-common.h | 4 ---- 116 files changed, 7 insertions(+), 145 deletions(-)
Almost everything is 1.
Reviewed-by: Simon Glass sjg@chromium.org
Regards, Simon
This converts the following to Kconfig: CONFIG_SYS_MMC_MAX_BLK_COUNT
Signed-off-by: Tom Rini trini@konsulko.com --- configs/hikey960_defconfig | 1 + configs/octeontx2_95xx_defconfig | 1 + configs/octeontx2_96xx_defconfig | 1 + configs/octeontx_81xx_defconfig | 1 + configs/octeontx_83xx_defconfig | 1 + configs/socfpga_agilex_atf_defconfig | 1 + configs/socfpga_agilex_defconfig | 1 + configs/socfpga_agilex_vab_defconfig | 1 + configs/socfpga_arria10_defconfig | 1 + configs/socfpga_arria5_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_dbm_soc1_defconfig | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_de10_nano_defconfig | 1 + configs/socfpga_de10_standard_defconfig | 1 + configs/socfpga_de1_soc_defconfig | 1 + configs/socfpga_mcvevk_defconfig | 1 + configs/socfpga_n5x_atf_defconfig | 1 + configs/socfpga_n5x_defconfig | 1 + configs/socfpga_n5x_vab_defconfig | 1 + configs/socfpga_secu1_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/socfpga_sr1500_defconfig | 1 + configs/socfpga_stratix10_atf_defconfig | 1 + configs/socfpga_stratix10_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + configs/total_compute_defconfig | 1 + configs/vexpress_ca9x4_defconfig | 1 + drivers/mmc/Kconfig | 7 +++++++ include/configs/hikey960.h | 1 - include/configs/octeontx2_common.h | 2 -- include/configs/octeontx_common.h | 2 -- include/configs/socfpga_common.h | 9 --------- include/configs/socfpga_soc64_common.h | 3 --- include/configs/total_compute.h | 2 -- include/configs/vexpress_common.h | 2 -- include/mmc.h | 5 ----- 38 files changed, 36 insertions(+), 26 deletions(-)
diff --git a/configs/hikey960_defconfig b/configs/hikey960_defconfig index f212f3b91642..153260d93cc6 100644 --- a/configs/hikey960_defconfig +++ b/configs/hikey960_defconfig @@ -29,6 +29,7 @@ CONFIG_ENV_IS_IN_EXT4=y CONFIG_ENV_EXT4_INTERFACE="mmc" CONFIG_ENV_EXT4_DEVICE_AND_PART="0:2" CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=1024 CONFIG_MMC_DW=y CONFIG_MMC_DW_K3=y CONFIG_PINCTRL=y diff --git a/configs/octeontx2_95xx_defconfig b/configs/octeontx2_95xx_defconfig index 700d49ebeda3..de860235152f 100644 --- a/configs/octeontx2_95xx_defconfig +++ b/configs/octeontx2_95xx_defconfig @@ -83,6 +83,7 @@ CONFIG_NET_RANDOM_ETHADDR=y CONFIG_TFTP_TSIZE=y CONFIG_DM_I2C=y CONFIG_MISC=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=8192 CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_HS400_SUPPORT=y diff --git a/configs/octeontx2_96xx_defconfig b/configs/octeontx2_96xx_defconfig index fe67c4860a11..3945b8b1e78e 100644 --- a/configs/octeontx2_96xx_defconfig +++ b/configs/octeontx2_96xx_defconfig @@ -89,6 +89,7 @@ CONFIG_I2C_SET_DEFAULT_BUS_NUM=y CONFIG_I2C_MUX=y CONFIG_I2C_MUX_PCA954x=y CONFIG_MISC=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=8192 CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_HS400_SUPPORT=y diff --git a/configs/octeontx_81xx_defconfig b/configs/octeontx_81xx_defconfig index c4a22cfd7f22..2be23524bc4b 100644 --- a/configs/octeontx_81xx_defconfig +++ b/configs/octeontx_81xx_defconfig @@ -87,6 +87,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_DM_I2C=y CONFIG_MISC=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=8192 CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OCTEONTX=y diff --git a/configs/octeontx_83xx_defconfig b/configs/octeontx_83xx_defconfig index 4bd662a3180d..9417ab723839 100644 --- a/configs/octeontx_83xx_defconfig +++ b/configs/octeontx_83xx_defconfig @@ -84,6 +84,7 @@ CONFIG_LBA48=y CONFIG_SYS_64BIT_LBA=y CONFIG_DM_I2C=y CONFIG_MISC=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=8192 CONFIG_SUPPORT_EMMC_RPMB=y CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_MMC_OCTEONTX=y diff --git a/configs/socfpga_agilex_atf_defconfig b/configs/socfpga_agilex_atf_defconfig index 4356171c143e..43b9f5c18460 100644 --- a/configs/socfpga_agilex_atf_defconfig +++ b/configs/socfpga_agilex_atf_defconfig @@ -71,6 +71,7 @@ CONFIG_SPL_ALTERA_SDRAM=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_SF_DEFAULT_MODE=0x2003 diff --git a/configs/socfpga_agilex_defconfig b/configs/socfpga_agilex_defconfig index 0603dd15ecbe..fabb2d25f47a 100644 --- a/configs/socfpga_agilex_defconfig +++ b/configs/socfpga_agilex_defconfig @@ -65,6 +65,7 @@ CONFIG_SPL_ALTERA_SDRAM=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y CONFIG_SF_DEFAULT_MODE=0x2003 CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/socfpga_agilex_vab_defconfig b/configs/socfpga_agilex_vab_defconfig index f568f5525ea6..911562710cd4 100644 --- a/configs/socfpga_agilex_vab_defconfig +++ b/configs/socfpga_agilex_vab_defconfig @@ -72,6 +72,7 @@ CONFIG_SPL_ALTERA_SDRAM=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_SF_DEFAULT_MODE=0x2003 diff --git a/configs/socfpga_arria10_defconfig b/configs/socfpga_arria10_defconfig index 6fe8d5500291..08ae6c502b41 100644 --- a/configs/socfpga_arria10_defconfig +++ b/configs/socfpga_arria10_defconfig @@ -55,6 +55,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DWAPB_GPIO=y CONFIG_FS_LOADER=y CONFIG_SPL_FS_LOADER=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_PHY_MICREL=y diff --git a/configs/socfpga_arria5_defconfig b/configs/socfpga_arria5_defconfig index 2632c0af4ea6..2951574464bd 100644 --- a/configs/socfpga_arria5_defconfig +++ b/configs/socfpga_arria5_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/socfpga_cyclone5_defconfig b/configs/socfpga_cyclone5_defconfig index 451de03e1da6..9c3c0f66b2ea 100644 --- a/configs/socfpga_cyclone5_defconfig +++ b/configs/socfpga_cyclone5_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/socfpga_dbm_soc1_defconfig b/configs/socfpga_dbm_soc1_defconfig index 7786843427e6..b3ba9ff21e2e 100644 --- a/configs/socfpga_dbm_soc1_defconfig +++ b/configs/socfpga_dbm_soc1_defconfig @@ -63,6 +63,7 @@ CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_SPI_FLASH_MTD=y diff --git a/configs/socfpga_de0_nano_soc_defconfig b/configs/socfpga_de0_nano_soc_defconfig index cfc8b50e2b20..5f5706fbdb22 100644 --- a/configs/socfpga_de0_nano_soc_defconfig +++ b/configs/socfpga_de0_nano_soc_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_SPI_FLASH_MTD=y diff --git a/configs/socfpga_de10_nano_defconfig b/configs/socfpga_de10_nano_defconfig index 53c4ff5ffd28..1f835bea9275 100644 --- a/configs/socfpga_de10_nano_defconfig +++ b/configs/socfpga_de10_nano_defconfig @@ -51,6 +51,7 @@ CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_SPI_FLASH_MTD=y diff --git a/configs/socfpga_de10_standard_defconfig b/configs/socfpga_de10_standard_defconfig index 15d45995261b..412b0da0dbd1 100644 --- a/configs/socfpga_de10_standard_defconfig +++ b/configs/socfpga_de10_standard_defconfig @@ -51,6 +51,7 @@ CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_SPI_FLASH_MTD=y diff --git a/configs/socfpga_de1_soc_defconfig b/configs/socfpga_de1_soc_defconfig index 2a1593680685..68a36892fb3d 100644 --- a/configs/socfpga_de1_soc_defconfig +++ b/configs/socfpga_de1_soc_defconfig @@ -48,6 +48,7 @@ CONFIG_VERSION_VARIABLE=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_PHY_MICREL=y diff --git a/configs/socfpga_mcvevk_defconfig b/configs/socfpga_mcvevk_defconfig index 35ea73a59875..8be8b85c0c25 100644 --- a/configs/socfpga_mcvevk_defconfig +++ b/configs/socfpga_mcvevk_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_SPI_FLASH_MTD=y diff --git a/configs/socfpga_n5x_atf_defconfig b/configs/socfpga_n5x_atf_defconfig index 775e1111a265..76cb8d2c2296 100644 --- a/configs/socfpga_n5x_atf_defconfig +++ b/configs/socfpga_n5x_atf_defconfig @@ -70,6 +70,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_SF_DEFAULT_MODE=0x2003 diff --git a/configs/socfpga_n5x_defconfig b/configs/socfpga_n5x_defconfig index 59f46a1f086c..39a1658ce1d1 100644 --- a/configs/socfpga_n5x_defconfig +++ b/configs/socfpga_n5x_defconfig @@ -62,6 +62,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y CONFIG_SF_DEFAULT_MODE=0x2003 CONFIG_SPI_FLASH_SPANSION=y diff --git a/configs/socfpga_n5x_vab_defconfig b/configs/socfpga_n5x_vab_defconfig index 073c1fbaebdb..649a5dbd2194 100644 --- a/configs/socfpga_n5x_vab_defconfig +++ b/configs/socfpga_n5x_vab_defconfig @@ -71,6 +71,7 @@ CONFIG_SPL_DM_SEQ_ALIAS=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_SF_DEFAULT_MODE=0x2003 diff --git a/configs/socfpga_secu1_defconfig b/configs/socfpga_secu1_defconfig index a6106f2a43df..debe22f30ac2 100644 --- a/configs/socfpga_secu1_defconfig +++ b/configs/socfpga_secu1_defconfig @@ -83,6 +83,7 @@ CONFIG_DM_I2C_GPIO=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_DM_MTD=y diff --git a/configs/socfpga_sockit_defconfig b/configs/socfpga_sockit_defconfig index 0539d2937eff..31cc03a5fd89 100644 --- a/configs/socfpga_sockit_defconfig +++ b/configs/socfpga_sockit_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/socfpga_socrates_defconfig b/configs/socfpga_socrates_defconfig index a81f74d329e5..72a70375360c 100644 --- a/configs/socfpga_socrates_defconfig +++ b/configs/socfpga_socrates_defconfig @@ -54,6 +54,7 @@ CONFIG_SYS_DFU_DATA_BUF_SIZE=0x1000000 CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_SPI_FLASH_MACRONIX=y diff --git a/configs/socfpga_sr1500_defconfig b/configs/socfpga_sr1500_defconfig index 59d809ca0ed6..44e9ba6c8844 100644 --- a/configs/socfpga_sr1500_defconfig +++ b/configs/socfpga_sr1500_defconfig @@ -61,6 +61,7 @@ CONFIG_SYS_BOOTCOUNT_BE=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_SF_DEFAULT_SPEED=100000000 diff --git a/configs/socfpga_stratix10_atf_defconfig b/configs/socfpga_stratix10_atf_defconfig index 9ffbd83031af..3a27444e7303 100644 --- a/configs/socfpga_stratix10_atf_defconfig +++ b/configs/socfpga_stratix10_atf_defconfig @@ -72,6 +72,7 @@ CONFIG_SPL_ALTERA_SDRAM=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_SF_DEFAULT_MODE=0x2003 diff --git a/configs/socfpga_stratix10_defconfig b/configs/socfpga_stratix10_defconfig index 4915d534d3be..e72e56a0232e 100644 --- a/configs/socfpga_stratix10_defconfig +++ b/configs/socfpga_stratix10_defconfig @@ -69,6 +69,7 @@ CONFIG_SPL_ALTERA_SDRAM=y CONFIG_DWAPB_GPIO=y CONFIG_DM_I2C=y CONFIG_SYS_I2C_DW=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_SF_DEFAULT_MODE=0x2003 diff --git a/configs/socfpga_vining_fpga_defconfig b/configs/socfpga_vining_fpga_defconfig index 3a99667811ae..96c0ebbc0cd1 100644 --- a/configs/socfpga_vining_fpga_defconfig +++ b/configs/socfpga_vining_fpga_defconfig @@ -88,6 +88,7 @@ CONFIG_LED_STATUS_CMD=y CONFIG_MISC=y CONFIG_I2C_EEPROM=y CONFIG_SYS_I2C_EEPROM_ADDR=0x50 +CONFIG_SYS_MMC_MAX_BLK_COUNT=256 CONFIG_MMC_DW=y CONFIG_MTD=y CONFIG_SF_DEFAULT_SPEED=40000000 diff --git a/configs/total_compute_defconfig b/configs/total_compute_defconfig index fd16e6ebe5a7..4ad72cfdc7b1 100644 --- a/configs/total_compute_defconfig +++ b/configs/total_compute_defconfig @@ -48,6 +48,7 @@ CONFIG_OF_CONTROL=y CONFIG_CLK=y # CONFIG_MMC_WRITE is not set CONFIG_ARM_PL180_MMCI=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=127 CONFIG_MTD=y CONFIG_MTD_NOR_FLASH=y CONFIG_FLASH_CFI_DRIVER=y diff --git a/configs/vexpress_ca9x4_defconfig b/configs/vexpress_ca9x4_defconfig index 72090deac875..50b60d9e97c0 100644 --- a/configs/vexpress_ca9x4_defconfig +++ b/configs/vexpress_ca9x4_defconfig @@ -39,6 +39,7 @@ CONFIG_ENV_OVERWRITE=y CONFIG_ENV_IS_IN_FLASH=y CONFIG_CLK=y CONFIG_ARM_PL180_MMCI=y +CONFIG_SYS_MMC_MAX_BLK_COUNT=127 CONFIG_MTD=y CONFIG_DM_MTD=y CONFIG_MTD_NOR_FLASH=y diff --git a/drivers/mmc/Kconfig b/drivers/mmc/Kconfig index 56f42820c745..bf4d994ff695 100644 --- a/drivers/mmc/Kconfig +++ b/drivers/mmc/Kconfig @@ -93,6 +93,13 @@ config MMC_QUIRKS are enabled by default, other may require additional flags or are enabled by the host driver.
+config SYS_MMC_MAX_BLK_COUNT + int "Block count limit" + default 65535 + help + The block count limit on MMC based devices. We default to 65535 due + to a 16bit register limit on some hardware. + config MMC_HW_PARTITIONING bool "Support for HW partitioning command(eMMC)" default y diff --git a/include/configs/hikey960.h b/include/configs/hikey960.h index ad070439d002..6fc3b7515aeb 100644 --- a/include/configs/hikey960.h +++ b/include/configs/hikey960.h @@ -39,6 +39,5 @@ BOOTENV
/* TODO: Remove this once the SD clock is fixed */ -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 1024
#endif /* __HIKEY_H */ diff --git a/include/configs/octeontx2_common.h b/include/configs/octeontx2_common.h index 2c430e8d3762..2681996fd195 100644 --- a/include/configs/octeontx2_common.h +++ b/include/configs/octeontx2_common.h @@ -19,8 +19,6 @@ "loadaddr=20080000\0" \ "ethrotate=yes\0"
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 8192 - #if defined(CONFIG_MMC_OCTEONTX) #define MMC_SUPPORTS_TUNING /** EMMC specific defines */ diff --git a/include/configs/octeontx_common.h b/include/configs/octeontx_common.h index b5d8cc15ac77..11fc6c7b84ff 100644 --- a/include/configs/octeontx_common.h +++ b/include/configs/octeontx_common.h @@ -42,8 +42,6 @@
/** Heap size for U-Boot */
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 8192 - /** EMMC specific defines */
#endif /* __OCTEONTX_COMMON_H__ */ diff --git a/include/configs/socfpga_common.h b/include/configs/socfpga_common.h index f0a33ed27dd5..704a7141d7e3 100644 --- a/include/configs/socfpga_common.h +++ b/include/configs/socfpga_common.h @@ -67,15 +67,6 @@ */ #define CONFIG_DW_WDT_CLOCK_KHZ 25000
-/* - * MMC Driver - */ -#ifdef CONFIG_CMD_MMC -/* FIXME */ -/* using smaller max blk cnt to avoid flooding the limited stack we have */ -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */ -#endif - /* * NAND Support */ diff --git a/include/configs/socfpga_soc64_common.h b/include/configs/socfpga_soc64_common.h index 06198ddd82a3..86cc3771ba59 100644 --- a/include/configs/socfpga_soc64_common.h +++ b/include/configs/socfpga_soc64_common.h @@ -81,9 +81,6 @@ /* * SDMMC configurations */ -#ifdef CONFIG_CMD_MMC -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 -#endif /* * Flash configurations */ diff --git a/include/configs/total_compute.h b/include/configs/total_compute.h index 7c77a8d53690..ab6cd0633215 100644 --- a/include/configs/total_compute.h +++ b/include/configs/total_compute.h @@ -28,8 +28,6 @@ #define PHYS_SDRAM_2 0x8080000000 #define PHYS_SDRAM_2_SIZE 0x180000000
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127 - #define CONFIG_EXTRA_ENV_SETTINGS \ "bootm_size=0x20000000\0" \ "load_addr=0xa0000000\0" \ diff --git a/include/configs/vexpress_common.h b/include/configs/vexpress_common.h index 7c0856ae325a..5d773060d826 100644 --- a/include/configs/vexpress_common.h +++ b/include/configs/vexpress_common.h @@ -124,8 +124,6 @@ #define CONFIG_SYS_SERIAL0 V2M_UART0 #define CONFIG_SYS_SERIAL1 V2M_UART1
-#define CONFIG_SYS_MMC_MAX_BLK_COUNT 127 - /* Miscellaneous configurable options */ #define LINUX_BOOT_PARAM_ADDR (V2M_BASE + 0x2000)
diff --git a/include/mmc.h b/include/mmc.h index 027e8bcc73a6..571fa625d02d 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -952,11 +952,6 @@ int mmc_get_env_dev(void); /* Minimum partition switch timeout in units of 10-milliseconds */ #define MMC_MIN_PART_SWITCH_TIME 30 /* 300 ms */
-/* Set block count limit because of 16 bit register limit on some hardware*/ -#ifndef CONFIG_SYS_MMC_MAX_BLK_COUNT -#define CONFIG_SYS_MMC_MAX_BLK_COUNT 65535 -#endif - /** * mmc_get_blk_desc() - Get the block descriptor for an MMC device *
On Fri, 28 Oct 2022 at 18:29, Tom Rini trini@konsulko.com wrote:
This converts the following to Kconfig: CONFIG_SYS_MMC_MAX_BLK_COUNT
Signed-off-by: Tom Rini trini@konsulko.com
configs/hikey960_defconfig | 1 + configs/octeontx2_95xx_defconfig | 1 + configs/octeontx2_96xx_defconfig | 1 + configs/octeontx_81xx_defconfig | 1 + configs/octeontx_83xx_defconfig | 1 + configs/socfpga_agilex_atf_defconfig | 1 + configs/socfpga_agilex_defconfig | 1 + configs/socfpga_agilex_vab_defconfig | 1 + configs/socfpga_arria10_defconfig | 1 + configs/socfpga_arria5_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_dbm_soc1_defconfig | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_de10_nano_defconfig | 1 + configs/socfpga_de10_standard_defconfig | 1 + configs/socfpga_de1_soc_defconfig | 1 + configs/socfpga_mcvevk_defconfig | 1 + configs/socfpga_n5x_atf_defconfig | 1 + configs/socfpga_n5x_defconfig | 1 + configs/socfpga_n5x_vab_defconfig | 1 + configs/socfpga_secu1_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/socfpga_sr1500_defconfig | 1 + configs/socfpga_stratix10_atf_defconfig | 1 + configs/socfpga_stratix10_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + configs/total_compute_defconfig | 1 + configs/vexpress_ca9x4_defconfig | 1 + drivers/mmc/Kconfig | 7 +++++++ include/configs/hikey960.h | 1 - include/configs/octeontx2_common.h | 2 -- include/configs/octeontx_common.h | 2 -- include/configs/socfpga_common.h | 9 --------- include/configs/socfpga_soc64_common.h | 3 --- include/configs/total_compute.h | 2 -- include/configs/vexpress_common.h | 2 -- include/mmc.h | 5 ----- 38 files changed, 36 insertions(+), 26 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
-----Original Message----- From: U-Boot [mailto:u-boot-bounces@lists.denx.de] On Behalf Of Simon Glass Sent: Sunday, October 30, 2022 10:44 AM To: Tom Rini trini@konsulko.com Cc: u-boot@lists.denx.de Subject: Re: [PATCH 12/21] Convert CONFIG_SYS_MMC_MAX_BLK_COUNT to Kconfig
On Fri, 28 Oct 2022 at 18:29, Tom Rini trini@konsulko.com wrote:
This converts the following to Kconfig: CONFIG_SYS_MMC_MAX_BLK_COUNT
Signed-off-by: Tom Rini trini@konsulko.com
configs/hikey960_defconfig | 1 + configs/octeontx2_95xx_defconfig | 1 + configs/octeontx2_96xx_defconfig | 1 + configs/octeontx_81xx_defconfig | 1 + configs/octeontx_83xx_defconfig | 1 + configs/socfpga_agilex_atf_defconfig | 1 + configs/socfpga_agilex_defconfig | 1 + configs/socfpga_agilex_vab_defconfig | 1 + configs/socfpga_arria10_defconfig | 1 + configs/socfpga_arria5_defconfig | 1 + configs/socfpga_cyclone5_defconfig | 1 + configs/socfpga_dbm_soc1_defconfig | 1 + configs/socfpga_de0_nano_soc_defconfig | 1 + configs/socfpga_de10_nano_defconfig | 1 + configs/socfpga_de10_standard_defconfig | 1 + configs/socfpga_de1_soc_defconfig | 1 + configs/socfpga_mcvevk_defconfig | 1 + configs/socfpga_n5x_atf_defconfig | 1 + configs/socfpga_n5x_defconfig | 1 + configs/socfpga_n5x_vab_defconfig | 1 + configs/socfpga_secu1_defconfig | 1 + configs/socfpga_sockit_defconfig | 1 + configs/socfpga_socrates_defconfig | 1 + configs/socfpga_sr1500_defconfig | 1 + configs/socfpga_stratix10_atf_defconfig | 1 + configs/socfpga_stratix10_defconfig | 1 + configs/socfpga_vining_fpga_defconfig | 1 + configs/total_compute_defconfig | 1 + configs/vexpress_ca9x4_defconfig | 1 + drivers/mmc/Kconfig | 7 +++++++ include/configs/hikey960.h | 1 - include/configs/octeontx2_common.h | 2 -- include/configs/octeontx_common.h | 2 -- include/configs/socfpga_common.h | 9 --------- include/configs/socfpga_soc64_common.h | 3 --- include/configs/total_compute.h | 2 -- include/configs/vexpress_common.h | 2 -- include/mmc.h | 5 ----- 38 files changed, 36 insertions(+), 26 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
Reviewed-by: Jaehoon Chung jh80.chung@samsung.com
This converts the following to Kconfig: CONFIG_SYS_MMC_MAX_DEVICE
Signed-off-by: Tom Rini trini@konsulko.com --- api/Kconfig | 5 +++++ api/api_storage.c | 4 ---- include/configs/am335x_evm.h | 18 ------------------ include/configs/stm32mp13_common.h | 3 --- include/configs/stm32mp15_common.h | 3 --- include/configs/sunxi-common.h | 2 -- include/configs/tegra-common.h | 7 ------- include/configs/zynq-common.h | 3 --- 8 files changed, 5 insertions(+), 40 deletions(-)
diff --git a/api/Kconfig b/api/Kconfig index 382aa4ad3f02..eb8d5d0596a7 100644 --- a/api/Kconfig +++ b/api/Kconfig @@ -5,4 +5,9 @@ config API help This option enables the U-Boot API. See api/README for more information.
+config SYS_MMC_MAX_DEVICE + int "Maximum number of MMC devices exposed via the API" + depends on API + default 1 + endmenu diff --git a/api/api_storage.c b/api/api_storage.c index adca44b4fd22..997e8727a965 100644 --- a/api/api_storage.c +++ b/api/api_storage.c @@ -44,10 +44,6 @@ struct stor_spec {
static struct stor_spec specs[ENUM_MAX] = { { 0, 0, 0, 0, NULL }, };
-#ifndef CONFIG_SYS_MMC_MAX_DEVICE -#define CONFIG_SYS_MMC_MAX_DEVICE 1 -#endif - void dev_stor_init(void) { #if defined(CONFIG_IDE) diff --git a/include/configs/am335x_evm.h b/include/configs/am335x_evm.h index bd7e2f1bf503..8eefaf24b28d 100644 --- a/include/configs/am335x_evm.h +++ b/include/configs/am335x_evm.h @@ -192,24 +192,6 @@ DFU_ALT_INFO_NAND #endif
-/* - * Default to using SPI for environment, etc. - * 0x000000 - 0x020000 : SPL (128KiB) - * 0x020000 - 0x0A0000 : U-Boot (512KiB) - * 0x0A0000 - 0x0BFFFF : First copy of U-Boot Environment (128KiB) - * 0x0C0000 - 0x0DFFFF : Second copy of U-Boot Environment (128KiB) - * 0x0E0000 - 0x442000 : Linux Kernel - * 0x442000 - 0x800000 : Userland - */ -#if defined(CONFIG_SPI_BOOT) -/* SPL related */ -#elif defined(CONFIG_EMMC_BOOT) -#define CONFIG_SYS_MMC_MAX_DEVICE 2 -#endif - -/* Network. */ -/* Enable Atheros phy driver */ - /* * NOR Size = 16 MiB * Number of Sectors/Blocks = 128 diff --git a/include/configs/stm32mp13_common.h b/include/configs/stm32mp13_common.h index 222e69c20c01..07a5bfc8a86e 100644 --- a/include/configs/stm32mp13_common.h +++ b/include/configs/stm32mp13_common.h @@ -21,9 +21,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ SZ_256M
-/*MMC SD*/ -#define CONFIG_SYS_MMC_MAX_DEVICE 2 - /* NAND support */
/*****************************************************************************/ diff --git a/include/configs/stm32mp15_common.h b/include/configs/stm32mp15_common.h index 9dad2a8ebdca..66b4638b312f 100644 --- a/include/configs/stm32mp15_common.h +++ b/include/configs/stm32mp15_common.h @@ -21,9 +21,6 @@ */ #define CONFIG_SYS_BOOTMAPSZ SZ_256M
-/*MMC SD*/ -#define CONFIG_SYS_MMC_MAX_DEVICE 3 - /* NAND support */
/* Ethernet need */ diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 93a56b5c575b..183af45f556f 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -78,8 +78,6 @@ /* mmc config */ #define CONFIG_MMC_SUNXI_SLOT 0
-#define CONFIG_SYS_MMC_MAX_DEVICE 4 - /* * Miscellaneous configurable options */ diff --git a/include/configs/tegra-common.h b/include/configs/tegra-common.h index 159ba093f299..2915db7f8bf7 100644 --- a/include/configs/tegra-common.h +++ b/include/configs/tegra-common.h @@ -28,13 +28,6 @@ */ #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
-/* - * Common HW configuration. - * If this varies between SoCs later, move to tegraNN-common.h - * Note: This is number of devices, not max device ID. - */ -#define CONFIG_SYS_MMC_MAX_DEVICE 4 - #ifdef CONFIG_ARM64 #define FDTFILE "nvidia/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" #else diff --git a/include/configs/zynq-common.h b/include/configs/zynq-common.h index e194e77e5b77..6574cf92e26e 100644 --- a/include/configs/zynq-common.h +++ b/include/configs/zynq-common.h @@ -195,9 +195,6 @@
/* Extend size of kernel image for uncompression */
-/* Boot FreeBSD/vxWorks from an ELF image */ -#define CONFIG_SYS_MMC_MAX_DEVICE 1 - /* Address in RAM where the parameters must be copied by SPL. */
/* Not using MMC raw mode - just for compilation purpose */
Hi Tom,
On Fri, 28 Oct 2022 at 18:29, Tom Rini trini@konsulko.com wrote:
This converts the following to Kconfig: CONFIG_SYS_MMC_MAX_DEVICE
Signed-off-by: Tom Rini trini@konsulko.com
api/Kconfig | 5 +++++ api/api_storage.c | 4 ---- include/configs/am335x_evm.h | 18 ------------------ include/configs/stm32mp13_common.h | 3 --- include/configs/stm32mp15_common.h | 3 --- include/configs/sunxi-common.h | 2 -- include/configs/tegra-common.h | 7 ------- include/configs/zynq-common.h | 3 --- 8 files changed, 5 insertions(+), 40 deletions(-)
It seems odd that none of the boards end up with a defconfig setting it to 2 or 3.
Regards, Simon
On Sat, Oct 29, 2022 at 07:43:36PM -0600, Simon Glass wrote:
Hi Tom,
On Fri, 28 Oct 2022 at 18:29, Tom Rini trini@konsulko.com wrote:
This converts the following to Kconfig: CONFIG_SYS_MMC_MAX_DEVICE
Signed-off-by: Tom Rini trini@konsulko.com
api/Kconfig | 5 +++++ api/api_storage.c | 4 ---- include/configs/am335x_evm.h | 18 ------------------ include/configs/stm32mp13_common.h | 3 --- include/configs/stm32mp15_common.h | 3 --- include/configs/sunxi-common.h | 2 -- include/configs/tegra-common.h | 7 ------- include/configs/zynq-common.h | 3 --- 8 files changed, 5 insertions(+), 40 deletions(-)
It seems odd that none of the boards end up with a defconfig setting it to 2 or 3.
What happened here is that boards were setting the value to something else, but never using it.
On Sun, 30 Oct 2022 at 10:37, Tom Rini trini@konsulko.com wrote:
On Sat, Oct 29, 2022 at 07:43:36PM -0600, Simon Glass wrote:
Hi Tom,
On Fri, 28 Oct 2022 at 18:29, Tom Rini trini@konsulko.com wrote:
This converts the following to Kconfig: CONFIG_SYS_MMC_MAX_DEVICE
Signed-off-by: Tom Rini trini@konsulko.com
api/Kconfig | 5 +++++ api/api_storage.c | 4 ---- include/configs/am335x_evm.h | 18 ------------------ include/configs/stm32mp13_common.h | 3 --- include/configs/stm32mp15_common.h | 3 --- include/configs/sunxi-common.h | 2 -- include/configs/tegra-common.h | 7 ------- include/configs/zynq-common.h | 3 --- 8 files changed, 5 insertions(+), 40 deletions(-)
It seems odd that none of the boards end up with a defconfig setting it to 2 or 3.
What happened here is that boards were setting the value to something else, but never using it.
Ah OK, that's good to fix.
Reviewed-by: Simon Glass sjg@chromium.org
-----Original Message----- From: U-Boot [mailto:u-boot-bounces@lists.denx.de] On Behalf Of Simon Glass Sent: Tuesday, November 1, 2022 4:27 AM To: Tom Rini trini@konsulko.com Cc: u-boot@lists.denx.de Subject: Re: [PATCH 13/21] Convert CONFIG_SYS_MMC_MAX_DEVICE to Kconfig
On Sun, 30 Oct 2022 at 10:37, Tom Rini trini@konsulko.com wrote:
On Sat, Oct 29, 2022 at 07:43:36PM -0600, Simon Glass wrote:
Hi Tom,
On Fri, 28 Oct 2022 at 18:29, Tom Rini trini@konsulko.com wrote:
This converts the following to Kconfig: CONFIG_SYS_MMC_MAX_DEVICE
Signed-off-by: Tom Rini trini@konsulko.com
api/Kconfig | 5 +++++ api/api_storage.c | 4 ---- include/configs/am335x_evm.h | 18 ------------------ include/configs/stm32mp13_common.h | 3 --- include/configs/stm32mp15_common.h | 3 --- include/configs/sunxi-common.h | 2 -- include/configs/tegra-common.h | 7 ------- include/configs/zynq-common.h | 3 --- 8 files changed, 5 insertions(+), 40 deletions(-)
It seems odd that none of the boards end up with a defconfig setting it to 2 or 3.
What happened here is that boards were setting the value to something else, but never using it.
Ah OK, that's good to fix.
Reviewed-by: Simon Glass sjg@chromium.org
Reviewed-by: Jaehoon Chung jh80.chung@samsung.com
This converts the following to Kconfig: CONFIG_SYS_MONITOR_LEN
To do this, we set a default of 0 for everyone because there are a number of cases where we define CONFIG_SYS_MONITOR_LEN but the only impact is that we set TOTAL_MALLOC_LEN to be CONFIG_SYS_MALLOC_LEN + CONFIG_ENV_SIZE, so we must continue to allow all boards to set this value. Update the SPL code to use 200 KB as the default raw U-Boot size directly, if we don't have a real CONFIG_SYS_MONITOR_LEN value.
Signed-off-by: Tom Rini trini@konsulko.com --- Kconfig | 11 +++++++++++ README | 6 ------ common/spl/spl.c | 11 +++++++---- configs/10m50_defconfig | 1 + configs/3c120_defconfig | 1 + configs/A10-OLinuXino-Lime_defconfig | 1 + configs/A10s-OLinuXino-M_defconfig | 1 + configs/A13-OLinuXinoM_defconfig | 1 + configs/A13-OLinuXino_defconfig | 1 + configs/A20-OLinuXino-Lime2-eMMC_defconfig | 1 + configs/A20-OLinuXino-Lime2_defconfig | 1 + configs/A20-OLinuXino-Lime_defconfig | 1 + configs/A20-OLinuXino_MICRO-eMMC_defconfig | 1 + configs/A20-OLinuXino_MICRO_defconfig | 1 + configs/A20-Olimex-SOM-EVB_defconfig | 1 + configs/A20-Olimex-SOM204-EVB-eMMC_defconfig | 1 + configs/A20-Olimex-SOM204-EVB_defconfig | 1 + configs/A33-OLinuXino_defconfig | 1 + configs/Ainol_AW1_defconfig | 1 + configs/Ampe_A76_defconfig | 1 + configs/Auxtek-T003_defconfig | 1 + configs/Auxtek-T004_defconfig | 1 + configs/Bananapi_M2_Ultra_defconfig | 1 + configs/Bananapi_defconfig | 1 + configs/Bananapi_m2m_defconfig | 1 + configs/Bananapro_defconfig | 1 + configs/CHIP_defconfig | 1 + configs/CHIP_pro_defconfig | 1 + configs/CSQ_CS908_defconfig | 1 + configs/Chuwi_V7_CW0825_defconfig | 1 + configs/Colombus_defconfig | 1 + configs/Cubieboard2_defconfig | 1 + configs/Cubieboard4_defconfig | 1 + configs/Cubieboard_defconfig | 1 + configs/Cubietruck_defconfig | 1 + configs/Cubietruck_plus_defconfig | 1 + configs/Empire_electronix_d709_defconfig | 1 + configs/Empire_electronix_m712_defconfig | 1 + configs/Hummingbird_A31_defconfig | 1 + configs/Hyundai_A7HD_defconfig | 1 + configs/Itead_Ibox_A20_defconfig | 1 + configs/Lamobo_R1_defconfig | 1 + configs/LicheePi_Zero_defconfig | 1 + configs/Linksprite_pcDuino3_Nano_defconfig | 1 + configs/Linksprite_pcDuino3_defconfig | 1 + configs/Linksprite_pcDuino_defconfig | 1 + configs/M5208EVBE_defconfig | 1 + configs/M5235EVB_Flash32_defconfig | 1 + configs/M5235EVB_defconfig | 1 + configs/M5249EVB_defconfig | 1 + configs/M5253DEMO_defconfig | 1 + configs/M5272C3_defconfig | 1 + configs/M5275EVB_defconfig | 1 + configs/M5282EVB_defconfig | 1 + configs/M53017EVB_defconfig | 1 + configs/M5329AFEE_defconfig | 1 + configs/M5329BFEE_defconfig | 1 + configs/M5373EVB_defconfig | 1 + configs/MCR3000_defconfig | 1 + configs/MK808C_defconfig | 1 + configs/MPC837XERDB_defconfig | 1 + configs/MPC8548CDS_36BIT_defconfig | 1 + configs/MPC8548CDS_defconfig | 1 + configs/MPC8548CDS_legacy_defconfig | 1 + configs/MSI_Primo73_defconfig | 1 + configs/MSI_Primo81_defconfig | 1 + configs/Marsboard_A10_defconfig | 1 + configs/Mele_A1000G_quad_defconfig | 1 + configs/Mele_A1000_defconfig | 1 + configs/Mele_I7_defconfig | 1 + configs/Mele_M3_defconfig | 1 + configs/Mele_M5_defconfig | 1 + configs/Mele_M9_defconfig | 1 + configs/Merrii_A80_Optimus_defconfig | 1 + configs/Mini-X_defconfig | 1 + configs/Nintendo_NES_Classic_Edition_defconfig | 1 + configs/Orangepi_defconfig | 1 + configs/Orangepi_mini_defconfig | 1 + configs/P1010RDB-PA_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PA_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PA_36BIT_SDCARD_defconfig | 1 + configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PA_NAND_defconfig | 1 + configs/P1010RDB-PA_NOR_defconfig | 1 + configs/P1010RDB-PA_SDCARD_defconfig | 1 + configs/P1010RDB-PA_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_36BIT_NAND_defconfig | 1 + configs/P1010RDB-PB_36BIT_NOR_defconfig | 1 + configs/P1010RDB-PB_36BIT_SDCARD_defconfig | 1 + configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig | 1 + configs/P1010RDB-PB_NAND_defconfig | 1 + configs/P1010RDB-PB_NOR_defconfig | 1 + configs/P1010RDB-PB_SDCARD_defconfig | 1 + configs/P1010RDB-PB_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_36BIT_defconfig | 1 + configs/P1020RDB-PC_NAND_defconfig | 1 + configs/P1020RDB-PC_SDCARD_defconfig | 1 + configs/P1020RDB-PC_SPIFLASH_defconfig | 1 + configs/P1020RDB-PC_defconfig | 1 + configs/P1020RDB-PD_NAND_defconfig | 1 + configs/P1020RDB-PD_SDCARD_defconfig | 1 + configs/P1020RDB-PD_SPIFLASH_defconfig | 1 + configs/P1020RDB-PD_defconfig | 1 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 1 + configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 1 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_36BIT_defconfig | 1 + configs/P2020RDB-PC_NAND_defconfig | 1 + configs/P2020RDB-PC_SDCARD_defconfig | 1 + configs/P2020RDB-PC_SPIFLASH_defconfig | 1 + configs/P2020RDB-PC_defconfig | 1 + configs/P2041RDB_NAND_defconfig | 1 + configs/P2041RDB_SDCARD_defconfig | 1 + configs/P2041RDB_SPIFLASH_defconfig | 1 + configs/P2041RDB_defconfig | 1 + configs/SBx81LIFKW_defconfig | 1 + configs/SBx81LIFXCAT_defconfig | 1 + configs/Sinlinx_SinA31s_defconfig | 1 + configs/Sinlinx_SinA33_defconfig | 1 + configs/Sinovoip_BPI_M2_defconfig | 1 + configs/Sinovoip_BPI_M3_defconfig | 1 + configs/Sunchip_CX-A99_defconfig | 1 + configs/T1024RDB_NAND_defconfig | 1 + configs/T1024RDB_SDCARD_defconfig | 1 + configs/T1024RDB_SPIFLASH_defconfig | 1 + configs/T1024RDB_defconfig | 1 + configs/T1042D4RDB_NAND_defconfig | 1 + configs/T1042D4RDB_SDCARD_defconfig | 1 + configs/T1042D4RDB_SPIFLASH_defconfig | 1 + configs/T1042D4RDB_defconfig | 1 + configs/T2080QDS_NAND_defconfig | 1 + configs/T2080QDS_SDCARD_defconfig | 1 + configs/T2080QDS_SECURE_BOOT_defconfig | 1 + configs/T2080QDS_SPIFLASH_defconfig | 1 + configs/T2080QDS_SRIO_PCIE_BOOT_defconfig | 1 + configs/T2080QDS_defconfig | 1 + configs/T2080RDB_NAND_defconfig | 1 + configs/T2080RDB_SDCARD_defconfig | 1 + configs/T2080RDB_SPIFLASH_defconfig | 1 + configs/T2080RDB_defconfig | 1 + configs/T2080RDB_revD_NAND_defconfig | 1 + configs/T2080RDB_revD_SDCARD_defconfig | 1 + configs/T2080RDB_revD_SPIFLASH_defconfig | 1 + configs/T2080RDB_revD_defconfig | 1 + configs/T4240RDB_SDCARD_defconfig | 1 + configs/T4240RDB_defconfig | 1 + configs/UTOO_P66_defconfig | 1 + configs/Wexler_TAB7200_defconfig | 1 + configs/Wits_Pro_A20_DKT_defconfig | 1 + configs/Wobo_i5_defconfig | 1 + configs/Yones_Toptech_BD1078_defconfig | 1 + configs/Yones_Toptech_BS1078_V2_defconfig | 1 + configs/a64-olinuxino-emmc_defconfig | 1 + configs/a64-olinuxino_defconfig | 1 + configs/ae350_rv32_defconfig | 1 + configs/ae350_rv32_spl_defconfig | 1 + configs/ae350_rv32_spl_xip_defconfig | 1 + configs/ae350_rv32_xip_defconfig | 1 + configs/alt_defconfig | 1 + configs/am3517_evm_defconfig | 1 + configs/amarula_a64_relic_defconfig | 1 + configs/amcore_defconfig | 1 + configs/apalis_imx6_defconfig | 1 + configs/astro_mcf5373l_defconfig | 1 + configs/at91sam9263ek_norflash_boot_defconfig | 1 + configs/at91sam9263ek_norflash_defconfig | 1 + configs/at91sam9m10g45ek_mmc_defconfig | 1 + configs/at91sam9m10g45ek_nandflash_defconfig | 1 + configs/at91sam9n12ek_mmc_defconfig | 1 + configs/at91sam9n12ek_nandflash_defconfig | 1 + configs/at91sam9n12ek_spiflash_defconfig | 1 + configs/at91sam9x5ek_dataflash_defconfig | 1 + configs/at91sam9x5ek_mmc_defconfig | 1 + configs/at91sam9x5ek_nandflash_defconfig | 1 + configs/at91sam9x5ek_spiflash_defconfig | 1 + configs/ba10_tv_box_defconfig | 1 + configs/bananapi_m1_plus_defconfig | 1 + configs/bananapi_m2_berry_defconfig | 1 + configs/bananapi_m2_plus_h3_defconfig | 1 + configs/bananapi_m2_plus_h5_defconfig | 1 + configs/bananapi_m2_zero_defconfig | 1 + configs/bananapi_m64_defconfig | 1 + configs/beelink_gs1_defconfig | 1 + configs/beelink_x2_defconfig | 1 + configs/blanche_defconfig | 1 + configs/cherryhill_defconfig | 1 + configs/chromebit_mickey_defconfig | 1 + configs/chromebook_jerry_defconfig | 1 + configs/chromebook_minnie_defconfig | 1 + configs/chromebook_speedy_defconfig | 1 + configs/ci20_mmc_defconfig | 1 + configs/cl-som-imx7_defconfig | 1 + configs/cm_fx6_defconfig | 1 + configs/cm_t43_defconfig | 1 + configs/cobra5272_defconfig | 1 + configs/colibri_imx6_defconfig | 1 + configs/colorfly_e708_q1_defconfig | 1 + configs/cougarcanyon2_defconfig | 1 + configs/devkit3250_defconfig | 1 + configs/devkit8000_defconfig | 1 + configs/dh_imx6_defconfig | 1 + configs/difrnce_dit4350_defconfig | 1 + configs/display5_defconfig | 1 + configs/display5_factory_defconfig | 1 + configs/dserve_dsrv9703c_defconfig | 1 + configs/eb_cpu5282_defconfig | 1 + configs/eb_cpu5282_internal_defconfig | 1 + configs/edison_defconfig | 1 + configs/emlid_neutis_n5_devboard_defconfig | 1 + configs/ethernut5_defconfig | 2 +- configs/evb-rk3288_defconfig | 1 + configs/firefly-rk3288_defconfig | 1 + configs/ga10h_v1_1_defconfig | 1 + configs/gardena-smart-gateway-at91sam_defconfig | 1 + configs/gazerbeam_defconfig | 1 + configs/gose_defconfig | 1 + configs/grpeach_defconfig | 1 + configs/gt90h_v4_defconfig | 1 + configs/gwventana_emmc_defconfig | 1 + configs/gwventana_gw5904_defconfig | 1 + configs/gwventana_nand_defconfig | 1 + configs/h8_homlet_v2_defconfig | 1 + configs/hihope_rzg2_defconfig | 1 + configs/i12-tvbox_defconfig | 1 + configs/iNet_3F_defconfig | 1 + configs/iNet_3W_defconfig | 1 + configs/iNet_86VS_defconfig | 1 + configs/iNet_D978_rev2_defconfig | 1 + configs/icnova-a20-swac_defconfig | 1 + configs/igep00x0_defconfig | 1 + configs/imx6dl_mamoj_defconfig | 1 + configs/imx6q_bosch_acc_defconfig | 1 + configs/imx6q_logic_defconfig | 1 + configs/imx6qdl_icore_mipi_defconfig | 1 + configs/imx6qdl_icore_mmc_defconfig | 1 + configs/imx6qdl_icore_rqs_defconfig | 1 + configs/imx6ul_geam_mmc_defconfig | 1 + configs/imx6ul_isiot_emmc_defconfig | 1 + configs/imx7_cm_defconfig | 1 + configs/imx8mm-cl-iot-gate-optee_defconfig | 1 + configs/imx8mm-cl-iot-gate_defconfig | 1 + configs/imx8mm-icore-mx8mm-ctouch2_defconfig | 1 + configs/imx8mm-icore-mx8mm-edimm2.2_defconfig | 1 + configs/imx8mm-mx8menlo_defconfig | 1 + configs/imx8mm_beacon_defconfig | 1 + configs/imx8mm_data_modul_edm_sbc_defconfig | 1 + configs/imx8mm_evk_defconfig | 1 + configs/imx8mm_evk_fspi_defconfig | 1 + configs/imx8mm_venice_defconfig | 1 + configs/imx8mn_beacon_2g_defconfig | 1 + configs/imx8mn_beacon_defconfig | 1 + configs/imx8mn_bsh_smm_s2_defconfig | 1 + configs/imx8mn_bsh_smm_s2pro_defconfig | 1 + configs/imx8mn_ddr4_evk_defconfig | 1 + configs/imx8mn_evk_defconfig | 1 + configs/imx8mn_var_som_defconfig | 1 + configs/imx8mn_venice_defconfig | 1 + configs/imx8mp-icore-mx8mp-edimm2.2_defconfig | 1 + configs/imx8mp_dhcom_pdk2_defconfig | 1 + configs/imx8mp_evk_defconfig | 1 + configs/imx8mp_rsb3720a1_4G_defconfig | 1 + configs/imx8mp_rsb3720a1_6G_defconfig | 1 + configs/imx8mp_venice_defconfig | 1 + configs/imx8mq_cm_defconfig | 1 + configs/imx8mq_evk_defconfig | 1 + configs/imx8mq_phanbell_defconfig | 1 + configs/imx8ulp_evk_defconfig | 1 + configs/imx93_11x11_evk_defconfig | 1 + configs/inet1_defconfig | 1 + configs/inet86dz_defconfig | 1 + configs/inet97fv2_defconfig | 1 + configs/inet98v_rev2_defconfig | 1 + configs/inet9f_rev03_defconfig | 1 + configs/inet_q972_defconfig | 1 + configs/integratorcp_cm1136_defconfig | 1 + configs/integratorcp_cm920t_defconfig | 1 + configs/integratorcp_cm926ejs_defconfig | 1 + configs/integratorcp_cm946es_defconfig | 1 + configs/jesurun_q5_defconfig | 1 + configs/kmcent2_defconfig | 1 + configs/kmcoge5ne_defconfig | 1 + configs/kmeter1_defconfig | 1 + configs/kmopti2_defconfig | 1 + configs/kmsupx5_defconfig | 1 + configs/kmtepr2_defconfig | 1 + configs/koelsch_defconfig | 1 + configs/kontron_pitx_imx8m_defconfig | 1 + configs/kontron_sl28_defconfig | 1 + configs/kp_imx6q_tpc_defconfig | 1 + configs/lager_defconfig | 1 + configs/librem5_defconfig | 1 + configs/libretech_all_h3_cc_h2_plus_defconfig | 1 + configs/libretech_all_h3_cc_h3_defconfig | 1 + configs/libretech_all_h3_cc_h5_defconfig | 1 + configs/libretech_all_h3_it_h5_defconfig | 1 + configs/libretech_all_h5_cc_h5_defconfig | 1 + configs/licheepi_nano_defconfig | 1 + configs/liteboard_defconfig | 1 + configs/ls1021aiot_sdcard_defconfig | 1 + configs/ls1021aqds_nand_defconfig | 1 + configs/ls1021aqds_sdcard_ifc_defconfig | 1 + configs/ls1021aqds_sdcard_qspi_defconfig | 1 + configs/ls1021atsn_sdcard_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig | 1 + configs/ls1021atwr_sdcard_ifc_defconfig | 1 + configs/ls1021atwr_sdcard_qspi_defconfig | 1 + configs/ls1043aqds_nand_defconfig | 1 + configs/ls1043aqds_sdcard_ifc_defconfig | 1 + configs/ls1043aqds_sdcard_qspi_defconfig | 1 + configs/ls1043ardb_nand_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_nand_defconfig | 1 + configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig | 1 + configs/ls1043ardb_sdcard_defconfig | 1 + configs/ls1046aqds_nand_defconfig | 1 + configs/ls1046aqds_sdcard_ifc_defconfig | 1 + configs/ls1046aqds_sdcard_qspi_defconfig | 1 + configs/ls1046ardb_emmc_defconfig | 1 + configs/ls1046ardb_qspi_spl_defconfig | 1 + configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig | 1 + configs/ls1046ardb_sdcard_defconfig | 1 + configs/ls1088aqds_sdcard_ifc_defconfig | 1 + configs/ls1088aqds_sdcard_qspi_defconfig | 1 + configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 1 + configs/ls1088ardb_sdcard_qspi_defconfig | 1 + configs/ls2080aqds_SECURE_BOOT_defconfig | 1 + configs/ls2080aqds_defconfig | 1 + configs/ls2080aqds_nand_defconfig | 1 + configs/ls2080aqds_qspi_defconfig | 1 + configs/ls2080aqds_sdcard_defconfig | 1 + configs/ls2080ardb_SECURE_BOOT_defconfig | 1 + configs/ls2080ardb_defconfig | 1 + configs/ls2080ardb_nand_defconfig | 1 + configs/ls2081ardb_defconfig | 1 + configs/ls2088aqds_tfa_defconfig | 1 + configs/ls2088ardb_qspi_SECURE_BOOT_defconfig | 1 + configs/ls2088ardb_qspi_defconfig | 1 + configs/ls2088ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/ls2088ardb_tfa_defconfig | 1 + configs/lx2160aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160aqds_tfa_defconfig | 1 + configs/lx2160ardb_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2160ardb_tfa_defconfig | 1 + configs/lx2160ardb_tfa_stmm_defconfig | 1 + configs/lx2162aqds_tfa_SECURE_BOOT_defconfig | 1 + configs/lx2162aqds_tfa_defconfig | 1 + configs/lx2162aqds_tfa_verified_boot_defconfig | 1 + configs/mccmon6_sd_defconfig | 1 + configs/miqi-rk3288_defconfig | 1 + configs/mixtile_loftq_defconfig | 1 + configs/mk802_a10s_defconfig | 1 + configs/mk802_defconfig | 1 + configs/mk802ii_defconfig | 1 + configs/mx6cuboxi_defconfig | 1 + configs/mx6sabreauto_defconfig | 1 + configs/mx6sabresd_defconfig | 1 + configs/mx6slevk_spl_defconfig | 1 + configs/mx6ul_14x14_evk_defconfig | 1 + configs/mx6ul_9x9_evk_defconfig | 1 + configs/myir_mys_6ulx_defconfig | 1 + configs/nanopi_a64_defconfig | 1 + configs/nanopi_m1_defconfig | 1 + configs/nanopi_m1_plus_defconfig | 1 + configs/nanopi_neo2_defconfig | 1 + configs/nanopi_neo_air_defconfig | 1 + configs/nanopi_neo_defconfig | 1 + configs/nanopi_neo_plus2_defconfig | 1 + configs/nanopi_r1s_h5_defconfig | 1 + configs/novena_defconfig | 1 + configs/oceanic_5205_5inmfd_defconfig | 1 + configs/odroid_defconfig | 1 + configs/omap35_logic_defconfig | 1 + configs/omap35_logic_somlv_defconfig | 1 + configs/omap3_beagle_defconfig | 1 + configs/omap3_evm_defconfig | 1 + configs/omap3_logic_defconfig | 1 + configs/omap3_logic_somlv_defconfig | 1 + configs/opos6uldev_defconfig | 1 + configs/orangepi_2_defconfig | 1 + configs/orangepi_3_defconfig | 1 + configs/orangepi_lite2_defconfig | 1 + configs/orangepi_lite_defconfig | 1 + configs/orangepi_one_defconfig | 1 + configs/orangepi_one_plus_defconfig | 1 + configs/orangepi_pc2_defconfig | 1 + configs/orangepi_pc_defconfig | 1 + configs/orangepi_pc_plus_defconfig | 1 + configs/orangepi_plus2e_defconfig | 1 + configs/orangepi_plus_defconfig | 1 + configs/orangepi_prime_defconfig | 1 + configs/orangepi_r1_defconfig | 1 + configs/orangepi_win_defconfig | 1 + configs/orangepi_zero2_defconfig | 1 + configs/orangepi_zero_defconfig | 1 + configs/orangepi_zero_plus2_defconfig | 1 + configs/orangepi_zero_plus2_h3_defconfig | 1 + configs/orangepi_zero_plus_defconfig | 1 + configs/origen_defconfig | 1 + configs/parrot_r16_defconfig | 1 + configs/pcm058_defconfig | 1 + configs/pg_wcom_expu1_defconfig | 1 + configs/pg_wcom_expu1_update_defconfig | 1 + configs/pg_wcom_seli8_defconfig | 1 + configs/pg_wcom_seli8_update_defconfig | 1 + configs/phycore-imx8mm_defconfig | 1 + configs/phycore-imx8mp_defconfig | 1 + configs/phycore-rk3288_defconfig | 1 + configs/phycore_pcl063_defconfig | 1 + configs/phycore_pcl063_ull_defconfig | 1 + configs/pic32mzdask_defconfig | 1 + configs/pico-dwarf-imx6ul_defconfig | 1 + configs/pico-dwarf-imx7d_defconfig | 1 + configs/pico-hobbit-imx6ul_defconfig | 1 + configs/pico-hobbit-imx7d_defconfig | 1 + configs/pico-imx6_defconfig | 1 + configs/pico-imx6ul_defconfig | 1 + configs/pico-imx7d_bl33_defconfig | 1 + configs/pico-imx7d_defconfig | 1 + configs/pico-imx8mq_defconfig | 1 + configs/pico-nymph-imx7d_defconfig | 1 + configs/pico-pi-imx6ul_defconfig | 1 + configs/pico-pi-imx7d_defconfig | 1 + configs/pine64-lts_defconfig | 1 + configs/pine64_plus_defconfig | 1 + configs/pine_h64_defconfig | 1 + configs/pinebook_defconfig | 1 + configs/pinecube_defconfig | 1 + configs/pinephone_defconfig | 1 + configs/pinetab_defconfig | 1 + configs/pm9g45_defconfig | 1 + configs/polaroid_mid2407pxe03_defconfig | 1 + configs/polaroid_mid2809pxe04_defconfig | 1 + configs/popmetal-rk3288_defconfig | 1 + configs/porter_defconfig | 1 + configs/pov_protab2_ips9_defconfig | 1 + configs/q8_a13_tablet_defconfig | 1 + configs/q8_a23_tablet_800x480_defconfig | 1 + configs/q8_a33_tablet_1024x600_defconfig | 1 + configs/q8_a33_tablet_800x480_defconfig | 1 + configs/qemu-ppce500_defconfig | 1 + configs/qemu-riscv32_defconfig | 1 + configs/qemu-riscv32_smode_defconfig | 1 + configs/qemu-riscv32_spl_defconfig | 1 + configs/r2dplus_defconfig | 1 + configs/r7-tv-dongle_defconfig | 1 + configs/r8a77970_eagle_defconfig | 1 + configs/r8a77980_condor_defconfig | 1 + configs/r8a77990_ebisu_defconfig | 1 + configs/r8a77995_draak_defconfig | 1 + configs/r8a779a0_falcon_defconfig | 1 + configs/rcar3_salvator-x_defconfig | 1 + configs/rcar3_ulcb_defconfig | 1 + configs/riotboard_defconfig | 1 + configs/rock-pi-n8-rk3288_defconfig | 1 + configs/rock2_defconfig | 1 + configs/rzg2_beacon_defconfig | 1 + configs/s5p_goni_defconfig | 1 + configs/s5pc210_universal_defconfig | 1 + configs/sama5d27_giantboard_defconfig | 1 + configs/sama5d27_som1_ek_mmc1_defconfig | 1 + configs/sama5d27_som1_ek_mmc_defconfig | 1 + configs/sama5d27_som1_ek_qspiflash_defconfig | 1 + configs/sama5d27_wlsom1_ek_mmc_defconfig | 1 + configs/sama5d27_wlsom1_ek_qspiflash_defconfig | 1 + configs/sama5d2_icp_mmc_defconfig | 1 + configs/sama5d2_icp_qspiflash_defconfig | 1 + configs/sama5d2_xplained_emmc_defconfig | 1 + configs/sama5d2_xplained_mmc_defconfig | 1 + configs/sama5d2_xplained_qspiflash_defconfig | 1 + configs/sama5d2_xplained_spiflash_defconfig | 1 + configs/sama5d36ek_cmp_mmc_defconfig | 1 + configs/sama5d36ek_cmp_nandflash_defconfig | 1 + configs/sama5d36ek_cmp_spiflash_defconfig | 1 + configs/sama5d3_xplained_mmc_defconfig | 1 + configs/sama5d3_xplained_nandflash_defconfig | 1 + configs/sama5d3xek_mmc_defconfig | 1 + configs/sama5d3xek_nandflash_defconfig | 1 + configs/sama5d3xek_spiflash_defconfig | 1 + configs/sama5d4_xplained_mmc_defconfig | 1 + configs/sama5d4_xplained_nandflash_defconfig | 1 + configs/sama5d4_xplained_spiflash_defconfig | 1 + configs/sama5d4ek_mmc_defconfig | 1 + configs/sama5d4ek_nandflash_defconfig | 1 + configs/sama5d4ek_spiflash_defconfig | 1 + configs/seeed_npi_imx6ull_defconfig | 1 + configs/silinux_ek874_defconfig | 1 + configs/silk_defconfig | 1 + configs/smdkc100_defconfig | 1 + configs/smdkv310_defconfig | 1 + configs/socrates_defconfig | 1 + configs/sopine_baseboard_defconfig | 1 + configs/stm32746g-eval_defconfig | 1 + configs/stm32746g-eval_spl_defconfig | 1 + configs/stm32f746-disco_defconfig | 1 + configs/stm32f746-disco_spl_defconfig | 1 + configs/stm32f769-disco_defconfig | 1 + configs/stm32f769-disco_spl_defconfig | 1 + configs/stmark2_defconfig | 1 + configs/stout_defconfig | 1 + configs/sun8i_a23_evb_defconfig | 1 + configs/sunxi_Gemei_G9_defconfig | 1 + configs/tanix_tx6_defconfig | 1 + configs/tbs_a711_defconfig | 1 + configs/teres_i_defconfig | 1 + configs/tinker-rk3288_defconfig | 1 + configs/tinker-s-rk3288_defconfig | 1 + configs/trats2_defconfig | 1 + configs/trats_defconfig | 1 + configs/tuge1_defconfig | 1 + configs/tuxx1_defconfig | 1 + configs/udoo_defconfig | 1 + configs/udoo_neo_defconfig | 1 + configs/uniphier_ld4_sld8_defconfig | 1 + configs/uniphier_v7_defconfig | 1 + configs/uniphier_v8_defconfig | 1 + configs/variscite_dart6ul_defconfig | 1 + configs/verdin-imx8mm_defconfig | 1 + configs/verdin-imx8mp_defconfig | 1 + configs/vining_2000_defconfig | 1 + configs/vyasa-rk3288_defconfig | 1 + configs/wandboard_defconfig | 1 + configs/work_92105_defconfig | 1 + configs/x96_mate_defconfig | 1 + configs/xtfpga_defconfig | 1 + configs/zeropi_defconfig | 1 + include/configs/10m50_devboard.h | 1 - include/configs/3c120_devboard.h | 1 - include/configs/M5208EVBE.h | 2 -- include/configs/M5235EVB.h | 2 -- include/configs/M5249EVB.h | 2 -- include/configs/M5253DEMO.h | 2 -- include/configs/M5272C3.h | 2 -- include/configs/M5275EVB.h | 2 -- include/configs/M5282EVB.h | 2 -- include/configs/M53017EVB.h | 2 -- include/configs/M5329EVB.h | 2 -- include/configs/M5373EVB.h | 2 -- include/configs/MCR3000.h | 1 - include/configs/MPC837XERDB.h | 2 -- include/configs/MPC8548CDS.h | 2 -- include/configs/P1010RDB.h | 2 -- include/configs/P2041RDB.h | 2 -- include/configs/SBx81LIFKW.h | 2 -- include/configs/SBx81LIFXCAT.h | 2 -- include/configs/T102xRDB.h | 2 -- include/configs/T104xRDB.h | 2 -- include/configs/T208xQDS.h | 1 - include/configs/T208xRDB.h | 1 - include/configs/T4240RDB.h | 2 -- include/configs/am3517_evm.h | 1 - include/configs/amcore.h | 1 - include/configs/astro_mcf5373l.h | 1 - include/configs/at91sam9263ek.h | 2 -- include/configs/at91sam9m10g45ek.h | 2 -- include/configs/at91sam9n12ek.h | 2 -- include/configs/at91sam9x5ek.h | 2 -- include/configs/bayleybay.h | 2 -- include/configs/capricorn-common.h | 3 --- include/configs/cgtqmx8.h | 2 -- include/configs/cherryhill.h | 2 -- include/configs/ci20.h | 1 - include/configs/cm_t43.h | 2 -- include/configs/cobra5272.h | 2 -- include/configs/conga-qeval20-qa3-e3845.h | 2 -- include/configs/coreboot.h | 2 -- include/configs/cougarcanyon2.h | 2 -- include/configs/crownbay.h | 2 -- include/configs/devkit3250.h | 1 - include/configs/dfi-bt700.h | 2 -- include/configs/eb_cpu5282.h | 2 -- include/configs/edison.h | 2 -- include/configs/efi-x86_payload.h | 2 -- include/configs/exynos4-common.h | 2 -- include/configs/galileo.h | 2 -- include/configs/gardena-smart-gateway-at91sam.h | 2 -- include/configs/gazerbeam.h | 2 -- include/configs/grpeach.h | 2 -- include/configs/imx27lite-common.h | 1 - include/configs/imx6_spl.h | 3 --- include/configs/imx7_spl.h | 3 --- include/configs/imx8mm-cl-iot-gate.h | 1 - include/configs/imx8mm_beacon.h | 1 - include/configs/imx8mm_data_modul_edm_sbc.h | 2 -- include/configs/imx8mm_evk.h | 1 - include/configs/imx8mm_icore_mx8mm.h | 1 - include/configs/imx8mm_venice.h | 1 - include/configs/imx8mn_beacon.h | 1 - include/configs/imx8mn_bsh_smm_s2_common.h | 1 - include/configs/imx8mn_evk.h | 1 - include/configs/imx8mn_var_som.h | 1 - include/configs/imx8mn_venice.h | 1 - include/configs/imx8mp_dhcom_pdk2.h | 2 -- include/configs/imx8mp_evk.h | 1 - include/configs/imx8mp_icore_mx8mp.h | 1 - include/configs/imx8mp_rsb3720.h | 1 - include/configs/imx8mp_venice.h | 1 - include/configs/imx8mq_cm.h | 2 -- include/configs/imx8mq_evk.h | 2 -- include/configs/imx8mq_phanbell.h | 2 -- include/configs/imx8qm_mek.h | 2 -- include/configs/imx8qxp_mek.h | 2 -- include/configs/imx8ulp_evk.h | 1 - include/configs/imx93_evk.h | 1 - include/configs/integratorcp.h | 1 - include/configs/km/km-mpc83xx.h | 1 - include/configs/km/pg-wcom-ls102xa.h | 2 -- include/configs/kmcent2.h | 2 -- include/configs/kontron_pitx_imx8m.h | 2 -- include/configs/kontron_sl28.h | 2 -- include/configs/librem5.h | 2 -- include/configs/ls1021aiot.h | 4 ---- include/configs/ls1021aqds.h | 6 ------ include/configs/ls1021atsn.h | 3 --- include/configs/ls1021atwr.h | 3 --- include/configs/ls1043a_common.h | 6 ------ include/configs/ls1046a_common.h | 9 --------- include/configs/ls1088a_common.h | 3 --- include/configs/ls2080a_common.h | 1 - include/configs/lx2160a_common.h | 1 - include/configs/minnowmax.h | 2 -- include/configs/p1_p2_rdb_pc.h | 2 -- include/configs/phycore_imx8mm.h | 1 - include/configs/phycore_imx8mp.h | 1 - include/configs/pic32mzdask.h | 2 -- include/configs/pico-imx8mq.h | 2 -- include/configs/pm9g45.h | 2 -- include/configs/qemu-ppce500.h | 2 -- include/configs/qemu-x86.h | 2 -- include/configs/r2dplus.h | 1 - include/configs/rcar-gen2-common.h | 2 -- include/configs/rcar-gen3-common.h | 2 -- include/configs/rk3288_common.h | 2 -- include/configs/s5p_goni.h | 2 -- include/configs/sama5d27_som1_ek.h | 2 -- include/configs/sama5d27_wlsom1_ek.h | 2 -- include/configs/sama5d2_icp.h | 2 -- include/configs/sama5d2_xplained.h | 2 -- include/configs/sama5d3_xplained.h | 1 - include/configs/sama5d3xek.h | 2 -- include/configs/sama5d4_xplained.h | 2 -- include/configs/sama5d4ek.h | 2 -- include/configs/smdkc100.h | 2 -- include/configs/socrates.h | 2 -- include/configs/som-db5800-som-6867.h | 2 -- include/configs/stm32f746-disco.h | 1 - include/configs/stmark2.h | 1 - include/configs/sunxi-common.h | 2 -- include/configs/theadorable-x86-common.h | 2 -- include/configs/ti_omap3_common.h | 2 -- include/configs/uniphier.h | 2 -- include/configs/verdin-imx8mm.h | 1 - include/configs/verdin-imx8mp.h | 1 - include/configs/work_92105.h | 1 - include/configs/x86-chromebook.h | 2 -- include/configs/xtfpga.h | 5 ----- 657 files changed, 542 insertions(+), 257 deletions(-)
diff --git a/Kconfig b/Kconfig index d297513bac6d..3a3025ddc6cb 100644 --- a/Kconfig +++ b/Kconfig @@ -583,6 +583,17 @@ config SYS_SRAM_SIZE default 0x10000 if TARGET_TRICORDER default 0x0
+config SYS_MONITOR_LEN + int "Maximum size in bytes reserved for U-Boot in memory" + default 1048576 if X86 + default 0 + help + Size of memory reserved for monitor code, used to determine + _at_compile_time_ (!) if the environment is embedded within the + U-Boot image, or in a separate flash sector, among other uses where + we need to set a maximum size of the U-Boot binary itself that will + be loaded. + config MP bool "Support for multiprocessor" help diff --git a/README b/README index 9b672d49a68a..ee63a115fa91 100644 --- a/README +++ b/README @@ -1526,12 +1526,6 @@ Configuration Settings: - CONFIG_SYS_FLASH_BASE: Physical start address of Flash memory.
-- CONFIG_SYS_MONITOR_LEN: - Size of memory reserved for monitor code, used to - determine _at_compile_time_ (!) if the environment is - embedded within the U-Boot image, or in a separate - flash sector. - - CONFIG_SYS_MALLOC_LEN: Size of DRAM reserved for malloc() use.
diff --git a/common/spl/spl.c b/common/spl/spl.c index 752b5b247cb8..abd106cc5505 100644 --- a/common/spl/spl.c +++ b/common/spl/spl.c @@ -46,10 +46,6 @@ DECLARE_BINMAN_MAGIC_SYM; #ifndef CONFIG_SYS_UBOOT_START #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE #endif -#ifndef CONFIG_SYS_MONITOR_LEN -/* Unknown U-Boot size, let's assume it will not be more than 200 KB */ -#define CONFIG_SYS_MONITOR_LEN (200 * 1024) -#endif
u32 *boot_params_ptr = NULL;
@@ -232,11 +228,17 @@ __weak struct legacy_img_hdr *spl_get_load_buffer(ssize_t offset, size_t size) return map_sysmem(CONFIG_SYS_TEXT_BASE + offset, 0); }
+#ifdef CONFIG_SPL_RAW_IMAGE_SUPPORT void spl_set_header_raw_uboot(struct spl_image_info *spl_image) { ulong u_boot_pos = spl_get_image_pos();
+#if CONFIG_SYS_MONITOR_LEN != 0 spl_image->size = CONFIG_SYS_MONITOR_LEN; +#else + /* Unknown U-Boot size, let's assume it will not be more than 200 KB */ + spl_image->size = 200 * 1024; +#endif
/* * Binman error cases: address of the end of the previous region or the @@ -254,6 +256,7 @@ void spl_set_header_raw_uboot(struct spl_image_info *spl_image) spl_image->os = IH_OS_U_BOOT; spl_image->name = "U-Boot"; } +#endif
#if CONFIG_IS_ENABLED(LOAD_FIT_FULL) /* Parse and load full fitImage in SPL */ diff --git a/configs/10m50_defconfig b/configs/10m50_defconfig index e1f75045f08e..dd88d10274c1 100644 --- a/configs/10m50_defconfig +++ b/configs/10m50_defconfig @@ -9,6 +9,7 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="10m50_devboard" CONFIG_SYS_LOAD_ADDR=0xcc000000 CONFIG_ENV_ADDR=0xF4080000 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0xCFF80000 # CONFIG_AUTOBOOT is not set diff --git a/configs/3c120_defconfig b/configs/3c120_defconfig index b094d3dc1f08..3d62512ff9d2 100644 --- a/configs/3c120_defconfig +++ b/configs/3c120_defconfig @@ -9,6 +9,7 @@ CONFIG_DM_GPIO=y CONFIG_DEFAULT_DEVICE_TREE="3c120_devboard" CONFIG_SYS_LOAD_ADDR=0xd4000000 CONFIG_ENV_ADDR=0xE2880000 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0xD7F80000 # CONFIG_AUTOBOOT is not set diff --git a/configs/A10-OLinuXino-Lime_defconfig b/configs/A10-OLinuXino-Lime_defconfig index 6727932f7fe0..ee92ac45fbca 100644 --- a/configs/A10-OLinuXino-Lime_defconfig +++ b/configs/A10-OLinuXino-Lime_defconfig @@ -11,6 +11,7 @@ CONFIG_I2C1_ENABLE=y CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/A10s-OLinuXino-M_defconfig b/configs/A10s-OLinuXino-M_defconfig index 99f578575178..2ac68039b0e1 100644 --- a/configs/A10s-OLinuXino-M_defconfig +++ b/configs/A10s-OLinuXino-M_defconfig @@ -9,6 +9,7 @@ CONFIG_MMC1_CD_PIN="PG13" CONFIG_MMC_SUNXI_SLOT_EXTRA=1 CONFIG_USB1_VBUS_PIN="PB10" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/A13-OLinuXinoM_defconfig b/configs/A13-OLinuXinoM_defconfig index f9d17b19500f..8f390cb83f8a 100644 --- a/configs/A13-OLinuXinoM_defconfig +++ b/configs/A13-OLinuXinoM_defconfig @@ -13,6 +13,7 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y CONFIG_VIDEO_LCD_POWER="PB10" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/A13-OLinuXino_defconfig b/configs/A13-OLinuXino_defconfig index 8c9043559bdb..ec11da5f061e 100644 --- a/configs/A13-OLinuXino_defconfig +++ b/configs/A13-OLinuXino_defconfig @@ -15,6 +15,7 @@ CONFIG_VIDEO_VGA_VIA_LCD_FORCE_SYNC_ACTIVE_HIGH=y CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/A20-OLinuXino-Lime2-eMMC_defconfig b/configs/A20-OLinuXino-Lime2-eMMC_defconfig index bccadcc7b4ae..8ce10d6f75b7 100644 --- a/configs/A20-OLinuXino-Lime2-eMMC_defconfig +++ b/configs/A20-OLinuXino-Lime2-eMMC_defconfig @@ -13,6 +13,7 @@ CONFIG_SATAPWR="PC3" CONFIG_SPL_SPI_SUNXI=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/A20-OLinuXino-Lime2_defconfig b/configs/A20-OLinuXino-Lime2_defconfig index 0a9de5ee6712..e38110b030be 100644 --- a/configs/A20-OLinuXino-Lime2_defconfig +++ b/configs/A20-OLinuXino-Lime2_defconfig @@ -11,6 +11,7 @@ CONFIG_I2C1_ENABLE=y CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/A20-OLinuXino-Lime_defconfig b/configs/A20-OLinuXino-Lime_defconfig index 38daf33b95b0..4e4804748ef6 100644 --- a/configs/A20-OLinuXino-Lime_defconfig +++ b/configs/A20-OLinuXino-Lime_defconfig @@ -9,6 +9,7 @@ CONFIG_I2C1_ENABLE=y CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/A20-OLinuXino_MICRO-eMMC_defconfig b/configs/A20-OLinuXino_MICRO-eMMC_defconfig index d73e64c46052..113d54dc0b91 100644 --- a/configs/A20-OLinuXino_MICRO-eMMC_defconfig +++ b/configs/A20-OLinuXino_MICRO-eMMC_defconfig @@ -11,6 +11,7 @@ CONFIG_VIDEO_VGA=y CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/A20-OLinuXino_MICRO_defconfig b/configs/A20-OLinuXino_MICRO_defconfig index 8a6bb885e9c5..1e1c30ef303a 100644 --- a/configs/A20-OLinuXino_MICRO_defconfig +++ b/configs/A20-OLinuXino_MICRO_defconfig @@ -12,6 +12,7 @@ CONFIG_VIDEO_VGA=y CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/A20-Olimex-SOM-EVB_defconfig b/configs/A20-Olimex-SOM-EVB_defconfig index 5de6c2d9a9ec..e76e6dd09327 100644 --- a/configs/A20-Olimex-SOM-EVB_defconfig +++ b/configs/A20-Olimex-SOM-EVB_defconfig @@ -12,6 +12,7 @@ CONFIG_USB0_VBUS_DET="PH5" CONFIG_SATAPWR="PC3" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig index 6e9bdc27d98a..1d3cf3119520 100644 --- a/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig +++ b/configs/A20-Olimex-SOM204-EVB-eMMC_defconfig @@ -13,6 +13,7 @@ CONFIG_SATAPWR="PC3" CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/A20-Olimex-SOM204-EVB_defconfig b/configs/A20-Olimex-SOM204-EVB_defconfig index e0517459ee68..97d0b9cee754 100644 --- a/configs/A20-Olimex-SOM204-EVB_defconfig +++ b/configs/A20-Olimex-SOM204-EVB_defconfig @@ -12,6 +12,7 @@ CONFIG_SATAPWR="PC3" CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/A33-OLinuXino_defconfig b/configs/A33-OLinuXino_defconfig index 351a454339be..49c9250092e2 100644 --- a/configs/A33-OLinuXino_defconfig +++ b/configs/A33-OLinuXino_defconfig @@ -16,5 +16,6 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PB2" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DCDC1_VOLT=3300 CONFIG_USB_MUSB_HOST=y diff --git a/configs/Ainol_AW1_defconfig b/configs/Ainol_AW1_defconfig index 9a18af8c6e11..4f01188fcf84 100644 --- a/configs/Ainol_AW1_defconfig +++ b/configs/Ainol_AW1_defconfig @@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Ampe_A76_defconfig b/configs/Ampe_A76_defconfig index 7bf3dfcd8a5e..d5cf1f42e5d2 100644 --- a/configs/Ampe_A76_defconfig +++ b/configs/Ampe_A76_defconfig @@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Auxtek-T003_defconfig b/configs/Auxtek-T003_defconfig index 7d81f12f766d..2b9d3a88ab61 100644 --- a/configs/Auxtek-T003_defconfig +++ b/configs/Auxtek-T003_defconfig @@ -8,6 +8,7 @@ CONFIG_DRAM_EMR1=0 CONFIG_USB1_VBUS_PIN="PB10" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Auxtek-T004_defconfig b/configs/Auxtek-T004_defconfig index 4c7154b04c49..f3e6944b14ec 100644 --- a/configs/Auxtek-T004_defconfig +++ b/configs/Auxtek-T004_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Bananapi_M2_Ultra_defconfig b/configs/Bananapi_M2_Ultra_defconfig index 18ee81b63786..0bd163afdd7c 100644 --- a/configs/Bananapi_M2_Ultra_defconfig +++ b/configs/Bananapi_M2_Ultra_defconfig @@ -12,6 +12,7 @@ CONFIG_USB2_VBUS_PIN="PH23" # CONFIG_HAS_ARMV7_SECURE_BASE is not set CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/Bananapi_defconfig b/configs/Bananapi_defconfig index 6c2a1f630e84..2814d77c1872 100644 --- a/configs/Bananapi_defconfig +++ b/configs/Bananapi_defconfig @@ -9,6 +9,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y diff --git a/configs/Bananapi_m2m_defconfig b/configs/Bananapi_m2m_defconfig index bad38a66568e..0e73265abb5c 100644 --- a/configs/Bananapi_m2m_defconfig +++ b/configs/Bananapi_m2m_defconfig @@ -10,6 +10,7 @@ CONFIG_MMC0_CD_PIN="PB4" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB0_ID_DET="PH8" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/Bananapro_defconfig b/configs/Bananapro_defconfig index 94fd74754ea3..11375991c812 100644 --- a/configs/Bananapro_defconfig +++ b/configs/Bananapro_defconfig @@ -11,6 +11,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y diff --git a/configs/CHIP_defconfig b/configs/CHIP_defconfig index cd9bdbfd36f7..03b2e03963e8 100644 --- a/configs/CHIP_defconfig +++ b/configs/CHIP_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y CONFIG_USB0_VBUS_PIN="PB10" CONFIG_VIDEO_COMPOSITE=y CONFIG_CHIP_DIP_SCAN=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_CMD_DFU=y CONFIG_DFU_RAM=y diff --git a/configs/CHIP_pro_defconfig b/configs/CHIP_pro_defconfig index 5a12fbb8cdaa..0e7d5e7c96f2 100644 --- a/configs/CHIP_pro_defconfig +++ b/configs/CHIP_pro_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN5I=y CONFIG_DRAM_TIMINGS_DDR3_800E_1066G_1333J=y CONFIG_USB0_VBUS_PIN="PB10" +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTDPARTS=y diff --git a/configs/CSQ_CS908_defconfig b/configs/CSQ_CS908_defconfig index 1cd39d498f23..73983b1f97d1 100644 --- a/configs/CSQ_CS908_defconfig +++ b/configs/CSQ_CS908_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Chuwi_V7_CW0825_defconfig b/configs/Chuwi_V7_CW0825_defconfig index 02b3e69584f1..4f964f19f072 100644 --- a/configs/Chuwi_V7_CW0825_defconfig +++ b/configs/Chuwi_V7_CW0825_defconfig @@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_HITACHI_TX18D42VM=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Colombus_defconfig b/configs/Colombus_defconfig index 270bd7d351a9..470d3f3ea01e 100644 --- a/configs/Colombus_defconfig +++ b/configs/Colombus_defconfig @@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_BL_EN="PM1" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_EDP_4_LANE_1620M_VIA_ANX9804=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Cubieboard2_defconfig b/configs/Cubieboard2_defconfig index ab5e53fb62ed..2c1b3d27aa05 100644 --- a/configs/Cubieboard2_defconfig +++ b/configs/Cubieboard2_defconfig @@ -8,6 +8,7 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/Cubieboard4_defconfig b/configs/Cubieboard4_defconfig index 04ed79afb6d5..c17edba90e02 100644 --- a/configs/Cubieboard4_defconfig +++ b/configs/Cubieboard4_defconfig @@ -12,5 +12,6 @@ CONFIG_USB0_ID_DET="PH16" CONFIG_USB1_VBUS_PIN="PH14" CONFIG_USB3_VBUS_PIN="PH15" CONFIG_AXP_GPIO=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SYS_I2C_SUN8I_RSB=y CONFIG_AXP809_POWER=y diff --git a/configs/Cubieboard_defconfig b/configs/Cubieboard_defconfig index c017b126b8c1..008167509d3b 100644 --- a/configs/Cubieboard_defconfig +++ b/configs/Cubieboard_defconfig @@ -8,6 +8,7 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/Cubietruck_defconfig b/configs/Cubietruck_defconfig index c85468e5827c..a42463437066 100644 --- a/configs/Cubietruck_defconfig +++ b/configs/Cubietruck_defconfig @@ -13,6 +13,7 @@ CONFIG_SATAPWR="PH12" CONFIG_GMAC_TX_DELAY=1 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_CMD_DFU=y CONFIG_CMD_USB_MASS_STORAGE=y diff --git a/configs/Cubietruck_plus_defconfig b/configs/Cubietruck_plus_defconfig index 13f958977be2..b44b9a71ac23 100644 --- a/configs/Cubietruck_plus_defconfig +++ b/configs/Cubietruck_plus_defconfig @@ -15,6 +15,7 @@ CONFIG_USB2_VBUS_PIN="PL6" CONFIG_I2C0_ENABLE=y CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_CONSOLE_MUX=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/Empire_electronix_d709_defconfig b/configs/Empire_electronix_d709_defconfig index a9bbe8bcffac..d31e867be305 100644 --- a/configs/Empire_electronix_d709_defconfig +++ b/configs/Empire_electronix_d709_defconfig @@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Empire_electronix_m712_defconfig b/configs/Empire_electronix_m712_defconfig index fc1f26b7a998..3e15d774336b 100644 --- a/configs/Empire_electronix_m712_defconfig +++ b/configs/Empire_electronix_m712_defconfig @@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Hummingbird_A31_defconfig b/configs/Hummingbird_A31_defconfig index 24e8b5be1b5b..0617192632a8 100644 --- a/configs/Hummingbird_A31_defconfig +++ b/configs/Hummingbird_A31_defconfig @@ -9,6 +9,7 @@ CONFIG_USB2_VBUS_PIN="" CONFIG_VIDEO_VGA_VIA_LCD=y CONFIG_VIDEO_VGA_EXTERNAL_DAC_EN="PH25" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/Hyundai_A7HD_defconfig b/configs/Hyundai_A7HD_defconfig index 482e0fb7a83d..d745a680289d 100644 --- a/configs/Hyundai_A7HD_defconfig +++ b/configs/Hyundai_A7HD_defconfig @@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Itead_Ibox_A20_defconfig b/configs/Itead_Ibox_A20_defconfig index 99df9cff24f9..6474c9e90a79 100644 --- a/configs/Itead_Ibox_A20_defconfig +++ b/configs/Itead_Ibox_A20_defconfig @@ -8,6 +8,7 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_SATAPWR="PB8" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/Lamobo_R1_defconfig b/configs/Lamobo_R1_defconfig index f97dc131f282..c943fd3c06e1 100644 --- a/configs/Lamobo_R1_defconfig +++ b/configs/Lamobo_R1_defconfig @@ -10,6 +10,7 @@ CONFIG_SATAPWR="PB3" CONFIG_GMAC_TX_DELAY=4 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/LicheePi_Zero_defconfig b/configs/LicheePi_Zero_defconfig index 9815348badd1..5e9732e62e66 100644 --- a/configs/LicheePi_Zero_defconfig +++ b/configs/LicheePi_Zero_defconfig @@ -5,4 +5,5 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_V3S=y CONFIG_DRAM_CLK=360 # CONFIG_HAS_ARMV7_SECURE_BASE is not set +CONFIG_SYS_MONITOR_LEN=786432 # CONFIG_NETDEVICES is not set diff --git a/configs/Linksprite_pcDuino3_Nano_defconfig b/configs/Linksprite_pcDuino3_Nano_defconfig index e3e30a49490a..469dcc11f12c 100644 --- a/configs/Linksprite_pcDuino3_Nano_defconfig +++ b/configs/Linksprite_pcDuino3_Nano_defconfig @@ -10,6 +10,7 @@ CONFIG_SATAPWR="PH2" CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/Linksprite_pcDuino3_defconfig b/configs/Linksprite_pcDuino3_defconfig index 1fda0db4c9df..c4a3f2db963f 100644 --- a/configs/Linksprite_pcDuino3_defconfig +++ b/configs/Linksprite_pcDuino3_defconfig @@ -8,6 +8,7 @@ CONFIG_DRAM_ZQ=122 CONFIG_SATAPWR="PH2" CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/Linksprite_pcDuino_defconfig b/configs/Linksprite_pcDuino_defconfig index 49dcfa098ee2..80eb661e7796 100644 --- a/configs/Linksprite_pcDuino_defconfig +++ b/configs/Linksprite_pcDuino_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN4I=y CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/M5208EVBE_defconfig b/configs/M5208EVBE_defconfig index 9513b02d8747..bff2e5aae102 100644 --- a/configs/M5208EVBE_defconfig +++ b/configs/M5208EVBE_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_LOAD_ADDR=0x40010000 CONFIG_ENV_ADDR=0x2000 CONFIG_TARGET_M5208EVBE=y CONFIG_MCFTMR=y +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_BASE=0x00000400 CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/M5235EVB_Flash32_defconfig b/configs/M5235EVB_Flash32_defconfig index 6a2b700fc78c..7653eb33cb73 100644 --- a/configs/M5235EVB_Flash32_defconfig +++ b/configs/M5235EVB_Flash32_defconfig @@ -9,6 +9,7 @@ CONFIG_ENV_ADDR=0xFFE04000 CONFIG_TARGET_M5235EVB=y CONFIG_NORFLASH_PS32BIT=y CONFIG_MCFTMR=y +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_BASE=0xFFC00400 CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/M5235EVB_defconfig b/configs/M5235EVB_defconfig index 09f3602611b2..49eca3b6ea9a 100644 --- a/configs/M5235EVB_defconfig +++ b/configs/M5235EVB_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_ENV_ADDR=0xFFE04000 CONFIG_TARGET_M5235EVB=y CONFIG_MCFTMR=y +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_BASE=0xFFE00400 CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/M5249EVB_defconfig b/configs/M5249EVB_defconfig index e4fb7ab96a83..42e6491b8eec 100644 --- a/configs/M5249EVB_defconfig +++ b/configs/M5249EVB_defconfig @@ -8,6 +8,7 @@ CONFIG_SYS_LOAD_ADDR=0x200000 CONFIG_ENV_ADDR=0xFFE04000 CONFIG_TARGET_M5249EVB=y CONFIG_MCFTMR=y +CONFIG_SYS_MONITOR_LEN=131072 CONFIG_SYS_MONITOR_BASE=0xFFE00400 # CONFIG_AUTOBOOT is not set CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/M5253DEMO_defconfig b/configs/M5253DEMO_defconfig index a73aca082c33..8f7c9d5d8438 100644 --- a/configs/M5253DEMO_defconfig +++ b/configs/M5253DEMO_defconfig @@ -8,6 +8,7 @@ CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_ENV_ADDR=0xFF804000 CONFIG_TARGET_M5253DEMO=y CONFIG_MCFTMR=y +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_BASE=0xFF800400 CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig index 3be9296cd24f..4c29e01c8d3d 100644 --- a/configs/M5272C3_defconfig +++ b/configs/M5272C3_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_ENV_ADDR=0xFFE04000 CONFIG_TARGET_M5272C3=y CONFIG_MCFTMR=y +CONFIG_SYS_MONITOR_LEN=131072 CONFIG_SYS_MONITOR_BASE=0xFFE00400 CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/M5275EVB_defconfig b/configs/M5275EVB_defconfig index 977d38ab64de..81c0fb1970d6 100644 --- a/configs/M5275EVB_defconfig +++ b/configs/M5275EVB_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_LOAD_ADDR=0x800000 CONFIG_ENV_ADDR=0xFFE04000 CONFIG_TARGET_M5275EVB=y CONFIG_MCFTMR=y +CONFIG_SYS_MONITOR_LEN=131072 CONFIG_SYS_MONITOR_BASE=0xFFE00400 CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTCOMMAND=y diff --git a/configs/M5282EVB_defconfig b/configs/M5282EVB_defconfig index 4b393abe1128..0fda35e84f68 100644 --- a/configs/M5282EVB_defconfig +++ b/configs/M5282EVB_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_ENV_ADDR=0xFFE04000 CONFIG_TARGET_M5282EVB=y CONFIG_MCFTMR=y +CONFIG_SYS_MONITOR_LEN=131072 CONFIG_SYS_MONITOR_BASE=0xFFE00400 CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/M53017EVB_defconfig b/configs/M53017EVB_defconfig index 986a9322ea99..3b3ce765905a 100644 --- a/configs/M53017EVB_defconfig +++ b/configs/M53017EVB_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_LOAD_ADDR=0x40010000 CONFIG_ENV_ADDR=0x40000 CONFIG_TARGET_M53017EVB=y CONFIG_MCFTMR=y +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_BASE=0x00000400 CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y diff --git a/configs/M5329AFEE_defconfig b/configs/M5329AFEE_defconfig index 0d513b75917e..7e463b9f9d66 100644 --- a/configs/M5329AFEE_defconfig +++ b/configs/M5329AFEE_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_LOAD_ADDR=0x40010000 CONFIG_ENV_ADDR=0x4000 CONFIG_TARGET_M5329EVB=y CONFIG_MCFTMR=y +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_BASE=0x00000400 CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/M5329BFEE_defconfig b/configs/M5329BFEE_defconfig index f3c2d9f179c3..623ffcdc38e1 100644 --- a/configs/M5329BFEE_defconfig +++ b/configs/M5329BFEE_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_LOAD_ADDR=0x40010000 CONFIG_ENV_ADDR=0x4000 CONFIG_TARGET_M5329EVB=y CONFIG_MCFTMR=y +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_BASE=0x00000400 CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/M5373EVB_defconfig b/configs/M5373EVB_defconfig index f462b1bb28c0..d3f8588cff91 100644 --- a/configs/M5373EVB_defconfig +++ b/configs/M5373EVB_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_LOAD_ADDR=0x40010000 CONFIG_ENV_ADDR=0x4000 CONFIG_TARGET_M5373EVB=y CONFIG_MCFTMR=y +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_BASE=0x00000400 CONFIG_BOOTDELAY=1 # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig index d34163515a1f..4d01f882c6db 100644 --- a/configs/MCR3000_defconfig +++ b/configs/MCR3000_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_PLPRCR=0x00460004 CONFIG_SYS_SCCR=0x00C20000 CONFIG_SYS_SCCR_MASK=0x60000000 CONFIG_SYS_DER=0x2002000F +CONFIG_SYS_MONITOR_LEN=327680 CONFIG_OF_BOARD_SETUP=y CONFIG_SYS_MONITOR_BASE=0x04000000 CONFIG_BOOTDELAY=5 diff --git a/configs/MK808C_defconfig b/configs/MK808C_defconfig index 3ed962d7cd94..0a4681b55787 100644 --- a/configs/MK808C_defconfig +++ b/configs/MK808C_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN7I=y CONFIG_DRAM_CLK=384 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig index 50abb797d287..b76e69245b05 100644 --- a/configs/MPC837XERDB_defconfig +++ b/configs/MPC837XERDB_defconfig @@ -147,6 +147,7 @@ CONFIG_ACR_RPTCNT_4=y CONFIG_SPCR_TSECEP_3=y CONFIG_LCRR_DBYP_PLL_BYPASSED=y CONFIG_LCRR_CLKDIV_8=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_BOOTDELAY=6 diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index b4475799c7ba..8ed38b8381ff 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -14,6 +14,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_PCIE1=y CONFIG_PHYS_64BIT=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DYNAMIC_SYS_CLK_FREQ=y diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 7d096dcddffe..3d55e5689589 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -13,6 +13,7 @@ CONFIG_TARGET_MPC8548CDS=y CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_PCIE1=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DYNAMIC_SYS_CLK_FREQ=y diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index 159028a84e6a..2c4a8c86669d 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -14,6 +14,7 @@ CONFIG_MPC85XX_HAVE_RESET_VECTOR=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_TARGET_MPC8548CDS_LEGACY=y CONFIG_PCIE1=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_DYNAMIC_SYS_CLK_FREQ=y diff --git a/configs/MSI_Primo73_defconfig b/configs/MSI_Primo73_defconfig index 071169fd2989..915a74d92a52 100644 --- a/configs/MSI_Primo73_defconfig +++ b/configs/MSI_Primo73_defconfig @@ -10,6 +10,7 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/MSI_Primo81_defconfig b/configs/MSI_Primo81_defconfig index e77b0072923e..d01532fe7534 100644 --- a/configs/MSI_Primo81_defconfig +++ b/configs/MSI_Primo81_defconfig @@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_MIPI_4_LANE_513_MBPS_VIA_SSD2828=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_USB_MUSB_HOST=y diff --git a/configs/Marsboard_A10_defconfig b/configs/Marsboard_A10_defconfig index 3c5312d88249..e3ada32b2ffc 100644 --- a/configs/Marsboard_A10_defconfig +++ b/configs/Marsboard_A10_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/Mele_A1000G_quad_defconfig b/configs/Mele_A1000G_quad_defconfig index c697d286dc19..d1bc200ab8e7 100644 --- a/configs/Mele_A1000G_quad_defconfig +++ b/configs/Mele_A1000G_quad_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_ZQ=120 CONFIG_USB1_VBUS_PIN="PC27" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Mele_A1000_defconfig b/configs/Mele_A1000_defconfig index f5b6d908cdc0..3424b976772f 100644 --- a/configs/Mele_A1000_defconfig +++ b/configs/Mele_A1000_defconfig @@ -8,6 +8,7 @@ CONFIG_VIDEO_VGA=y CONFIG_VIDEO_COMPOSITE=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/Mele_I7_defconfig b/configs/Mele_I7_defconfig index 2b9bca13d08e..11ba7862382c 100644 --- a/configs/Mele_I7_defconfig +++ b/configs/Mele_I7_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_ZQ=120 CONFIG_USB1_VBUS_PIN="PC27" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Mele_M3_defconfig b/configs/Mele_M3_defconfig index 77cb464c9326..1b04ebc22a65 100644 --- a/configs/Mele_M3_defconfig +++ b/configs/Mele_M3_defconfig @@ -9,6 +9,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_VIDEO_VGA=y CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Mele_M5_defconfig b/configs/Mele_M5_defconfig index b07dbbde2e4b..114c2fe827f3 100644 --- a/configs/Mele_M5_defconfig +++ b/configs/Mele_M5_defconfig @@ -9,6 +9,7 @@ CONFIG_MMC0_CD_PIN="PH1" CONFIG_VIDEO_COMPOSITE=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/Mele_M9_defconfig b/configs/Mele_M9_defconfig index be6dd417545c..b24ef02f8a27 100644 --- a/configs/Mele_M9_defconfig +++ b/configs/Mele_M9_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_ZQ=120 CONFIG_USB1_VBUS_PIN="PC27" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Merrii_A80_Optimus_defconfig b/configs/Merrii_A80_Optimus_defconfig index c5d1f40df398..2b96f6be1200 100644 --- a/configs/Merrii_A80_Optimus_defconfig +++ b/configs/Merrii_A80_Optimus_defconfig @@ -12,5 +12,6 @@ CONFIG_USB0_ID_DET="PH3" CONFIG_USB1_VBUS_PIN="PH4" CONFIG_USB3_VBUS_PIN="PH5" CONFIG_AXP_GPIO=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SYS_I2C_SUN8I_RSB=y CONFIG_AXP809_POWER=y diff --git a/configs/Mini-X_defconfig b/configs/Mini-X_defconfig index e8bc14857663..72745f2b5323 100644 --- a/configs/Mini-X_defconfig +++ b/configs/Mini-X_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN4I=y CONFIG_USB0_VBUS_PIN="PB9" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Nintendo_NES_Classic_Edition_defconfig b/configs/Nintendo_NES_Classic_Edition_defconfig index 89fb441cc738..94060ab107ab 100644 --- a/configs/Nintendo_NES_Classic_Edition_defconfig +++ b/configs/Nintendo_NES_Classic_Edition_defconfig @@ -9,6 +9,7 @@ CONFIG_DRAM_ODT_EN=y CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 # CONFIG_CMD_FLASH is not set CONFIG_CMD_MTDPARTS=y # CONFIG_MMC is not set diff --git a/configs/Orangepi_defconfig b/configs/Orangepi_defconfig index c89a9a1f9dd5..b4d5feff3092 100644 --- a/configs/Orangepi_defconfig +++ b/configs/Orangepi_defconfig @@ -12,6 +12,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/Orangepi_mini_defconfig b/configs/Orangepi_mini_defconfig index 8757dcb461c3..431973811145 100644 --- a/configs/Orangepi_mini_defconfig +++ b/configs/Orangepi_mini_defconfig @@ -14,6 +14,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/P1010RDB-PA_36BIT_NAND_defconfig b/configs/P1010RDB-PA_36BIT_NAND_defconfig index 2808763cc2bc..4afd16d44c2f 100644 --- a/configs/P1010RDB-PA_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PA_36BIT_NAND_defconfig @@ -22,6 +22,7 @@ CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1010RDB-PA_36BIT_NOR_defconfig b/configs/P1010RDB-PA_36BIT_NOR_defconfig index c857d0693899..1057a8f4701d 100644 --- a/configs/P1010RDB-PA_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PA_36BIT_NOR_defconfig @@ -14,6 +14,7 @@ CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig index c3432bac6926..873f383b5ff7 100644 --- a/configs/P1010RDB-PA_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PA_36BIT_SDCARD_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig index 9c272991008b..b0f6cfee4ed5 100644 --- a/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_36BIT_SPIFLASH_defconfig @@ -22,6 +22,7 @@ CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1010RDB-PA_NAND_defconfig b/configs/P1010RDB-PA_NAND_defconfig index 24efd95dac6c..97546aebedec 100644 --- a/configs/P1010RDB-PA_NAND_defconfig +++ b/configs/P1010RDB-PA_NAND_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1010RDB-PA_NOR_defconfig b/configs/P1010RDB-PA_NOR_defconfig index 0cf331645b36..3e28a18e4962 100644 --- a/configs/P1010RDB-PA_NOR_defconfig +++ b/configs/P1010RDB-PA_NOR_defconfig @@ -13,6 +13,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1010RDB-PA_SDCARD_defconfig b/configs/P1010RDB-PA_SDCARD_defconfig index cda3bcff5104..be085e5092b4 100644 --- a/configs/P1010RDB-PA_SDCARD_defconfig +++ b/configs/P1010RDB-PA_SDCARD_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1010RDB-PA_SPIFLASH_defconfig b/configs/P1010RDB-PA_SPIFLASH_defconfig index f55eec2c6f19..20f5d8be23d5 100644 --- a/configs/P1010RDB-PA_SPIFLASH_defconfig +++ b/configs/P1010RDB-PA_SPIFLASH_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1010RDB-PB_36BIT_NAND_defconfig b/configs/P1010RDB-PB_36BIT_NAND_defconfig index d04cae88baa3..b939b325efed 100644 --- a/configs/P1010RDB-PB_36BIT_NAND_defconfig +++ b/configs/P1010RDB-PB_36BIT_NAND_defconfig @@ -22,6 +22,7 @@ CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1010RDB-PB_36BIT_NOR_defconfig b/configs/P1010RDB-PB_36BIT_NOR_defconfig index 2b45dd00c3a5..e048db81735c 100644 --- a/configs/P1010RDB-PB_36BIT_NOR_defconfig +++ b/configs/P1010RDB-PB_36BIT_NOR_defconfig @@ -14,6 +14,7 @@ CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig index cf3ffdd8544b..2a81539dfe25 100644 --- a/configs/P1010RDB-PB_36BIT_SDCARD_defconfig +++ b/configs/P1010RDB-PB_36BIT_SDCARD_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig index 8c0e996f9137..89a5ab1e449f 100644 --- a/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_36BIT_SPIFLASH_defconfig @@ -22,6 +22,7 @@ CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1010RDB-PB_NAND_defconfig b/configs/P1010RDB-PB_NAND_defconfig index e68276530b29..eb21534282e3 100644 --- a/configs/P1010RDB-PB_NAND_defconfig +++ b/configs/P1010RDB-PB_NAND_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1010RDB-PB_NOR_defconfig b/configs/P1010RDB-PB_NOR_defconfig index 6918a906047c..901919478347 100644 --- a/configs/P1010RDB-PB_NOR_defconfig +++ b/configs/P1010RDB-PB_NOR_defconfig @@ -13,6 +13,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1010RDB-PB_SDCARD_defconfig b/configs/P1010RDB-PB_SDCARD_defconfig index 9913cd2c4cf1..9915deeb79b3 100644 --- a/configs/P1010RDB-PB_SDCARD_defconfig +++ b/configs/P1010RDB-PB_SDCARD_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1010RDB-PB_SPIFLASH_defconfig b/configs/P1010RDB-PB_SPIFLASH_defconfig index 2832e58eddd4..768d40ad86d5 100644 --- a/configs/P1010RDB-PB_SPIFLASH_defconfig +++ b/configs/P1010RDB-PB_SPIFLASH_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index c3672d1760bc..824173a4b5e0 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -22,6 +22,7 @@ CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 5ea1cb5245cf..1293c7252ecc 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index 0177ae5eb58a..82eb371a8460 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -22,6 +22,7 @@ CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 82e11dabffe1..33babe72ee9f 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -15,6 +15,7 @@ CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 887a0d90a70b..3c43800d627f 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index 76d1b8c3cb60..fb7338bcce75 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index 996fa5dcc085..37ccd1876992 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 1519cf6d9014..942248819ee4 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -14,6 +14,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 00f9df246bd3..7051e90bd090 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index f8cc037a4e61..0661c2ca0165 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index ab1d3f1355e4..48150a7ec510 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index a5008a5bc3ed..eb5645406055 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -14,6 +14,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index 6f51ab625437..7c44e7d25490 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -22,6 +22,7 @@ CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 7ccdc1f5c948..45673818c9f5 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index bbdc5452debc..8e89cd66b946 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -22,6 +22,7 @@ CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index c97eb4b96b4f..b11098ce194d 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -15,6 +15,7 @@ CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PHYS_64BIT=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 58e461ba4467..ec105814d9f5 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_TPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index 60a295933869..6a1e62f92a75 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index 188a22b76dcd..f30bff99fc24 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_SPL_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 4e414d45958f..0d96fb5d2eac 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -14,6 +14,7 @@ CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y CONFIG_PCIE1=y CONFIG_PCIE2=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index e48d9fba6399..3ded80066fe1 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -15,6 +15,7 @@ CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index 6c589b464b77..c40d0cf552dc 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -15,6 +15,7 @@ CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index d8017c3c6cc9..a554ff253fd7 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -16,6 +16,7 @@ CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index bca9e3794d2d..099c035a6f0b 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -16,6 +16,7 @@ CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_PCIE3=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/SBx81LIFKW_defconfig b/configs/SBx81LIFKW_defconfig index 69899760f19f..4196d339b3b0 100644 --- a/configs/SBx81LIFKW_defconfig +++ b/configs/SBx81LIFKW_defconfig @@ -16,6 +16,7 @@ CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y CONFIG_SILENT_U_BOOT_ONLY=y diff --git a/configs/SBx81LIFXCAT_defconfig b/configs/SBx81LIFXCAT_defconfig index 84ac69dcc978..62ec1711204f 100644 --- a/configs/SBx81LIFXCAT_defconfig +++ b/configs/SBx81LIFXCAT_defconfig @@ -16,6 +16,7 @@ CONFIG_SYS_LOAD_ADDR=0x1000000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xc8012000 # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_BOOTDELAY=3 CONFIG_SILENT_CONSOLE=y CONFIG_SILENT_U_BOOT_ONLY=y diff --git a/configs/Sinlinx_SinA31s_defconfig b/configs/Sinlinx_SinA31s_defconfig index 238b0073e794..a1d62fce7c1c 100644 --- a/configs/Sinlinx_SinA31s_defconfig +++ b/configs/Sinlinx_SinA31s_defconfig @@ -10,6 +10,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=3 CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_MII=y diff --git a/configs/Sinlinx_SinA33_defconfig b/configs/Sinlinx_SinA33_defconfig index 4eb5300b0468..eb172c70de88 100644 --- a/configs/Sinlinx_SinA33_defconfig +++ b/configs/Sinlinx_SinA33_defconfig @@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_CMD_DFU=y CONFIG_DFU_RAM=y CONFIG_FASTBOOT_CMD_OEM_FORMAT=y diff --git a/configs/Sinovoip_BPI_M2_defconfig b/configs/Sinovoip_BPI_M2_defconfig index aba95270eb2f..fa967bcc0c13 100644 --- a/configs/Sinovoip_BPI_M2_defconfig +++ b/configs/Sinovoip_BPI_M2_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=432 CONFIG_USB1_VBUS_PIN="" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/Sinovoip_BPI_M3_defconfig b/configs/Sinovoip_BPI_M3_defconfig index 5116fab52d7f..ab70eff68ebd 100644 --- a/configs/Sinovoip_BPI_M3_defconfig +++ b/configs/Sinovoip_BPI_M3_defconfig @@ -15,6 +15,7 @@ CONFIG_USB1_VBUS_PIN="PD24" CONFIG_AXP_GPIO=y CONFIG_SATAPWR="PD25" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_CONSOLE_MUX=y CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y diff --git a/configs/Sunchip_CX-A99_defconfig b/configs/Sunchip_CX-A99_defconfig index bb62ae9a7a99..53cead297622 100644 --- a/configs/Sunchip_CX-A99_defconfig +++ b/configs/Sunchip_CX-A99_defconfig @@ -12,3 +12,4 @@ CONFIG_USB0_VBUS_PIN="PH15" CONFIG_USB1_VBUS_PIN="PL7" CONFIG_USB3_VBUS_PIN="PL8" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index eb5e70b88112..8f088524d8d0 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -23,6 +23,7 @@ CONFIG_PCIE2=y CONFIG_PCIE3=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index 4c8fb8252653..62618491164f 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -23,6 +23,7 @@ CONFIG_PCIE2=y CONFIG_PCIE3=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 8405d25f10e1..014c68303ae8 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -25,6 +25,7 @@ CONFIG_PCIE2=y CONFIG_PCIE3=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 44ef30577c70..441982fac605 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -17,6 +17,7 @@ CONFIG_PCIE2=y CONFIG_PCIE3=y CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index d7e0a9f57516..130ae9efd2eb 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -22,6 +22,7 @@ CONFIG_PCIE2=y CONFIG_PCIE3=y CONFIG_PCIE4=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index c3c3303d82c0..c39e6edd9b0b 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -22,6 +22,7 @@ CONFIG_PCIE2=y CONFIG_PCIE3=y CONFIG_PCIE4=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index c9bf6db4407a..9eb4f8ea4d1e 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -24,6 +24,7 @@ CONFIG_PCIE2=y CONFIG_PCIE3=y CONFIG_PCIE4=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index 3ce7270cc315..82a4abce9e4f 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -16,6 +16,7 @@ CONFIG_PCIE2=y CONFIG_PCIE3=y CONFIG_PCIE4=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T2080QDS_NAND_defconfig b/configs/T2080QDS_NAND_defconfig index ff72ec9452ba..f093d2690672 100644 --- a/configs/T2080QDS_NAND_defconfig +++ b/configs/T2080QDS_NAND_defconfig @@ -29,6 +29,7 @@ CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T2080QDS_SDCARD_defconfig b/configs/T2080QDS_SDCARD_defconfig index 2f209166263d..5a9cac7e6e50 100644 --- a/configs/T2080QDS_SDCARD_defconfig +++ b/configs/T2080QDS_SDCARD_defconfig @@ -29,6 +29,7 @@ CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T2080QDS_SECURE_BOOT_defconfig b/configs/T2080QDS_SECURE_BOOT_defconfig index 10757091b4e3..baf630308557 100644 --- a/configs/T2080QDS_SECURE_BOOT_defconfig +++ b/configs/T2080QDS_SECURE_BOOT_defconfig @@ -24,6 +24,7 @@ CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set # CONFIG_SYS_MALLOC_F is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T2080QDS_SPIFLASH_defconfig b/configs/T2080QDS_SPIFLASH_defconfig index edef62e00878..bf348c6b73df 100644 --- a/configs/T2080QDS_SPIFLASH_defconfig +++ b/configs/T2080QDS_SPIFLASH_defconfig @@ -31,6 +31,7 @@ CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig index 612bb6a444c8..cefbfd21a787 100644 --- a/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig +++ b/configs/T2080QDS_SRIO_PCIE_BOOT_defconfig @@ -23,6 +23,7 @@ CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T2080QDS_defconfig b/configs/T2080QDS_defconfig index d2dc24fb036b..27826ebd2708 100644 --- a/configs/T2080QDS_defconfig +++ b/configs/T2080QDS_defconfig @@ -23,6 +23,7 @@ CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index df4deafc1ab1..1760dbbb103e 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -28,6 +28,7 @@ CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index 534770b43ec5..543002c2fd3b 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -28,6 +28,7 @@ CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index 278acb87719e..f0ecbd524f37 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -30,6 +30,7 @@ CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index 5422214f198a..708314eeb40d 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -22,6 +22,7 @@ CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T2080RDB_revD_NAND_defconfig b/configs/T2080RDB_revD_NAND_defconfig index 75dce6042f22..903d8cdfa010 100644 --- a/configs/T2080RDB_revD_NAND_defconfig +++ b/configs/T2080RDB_revD_NAND_defconfig @@ -29,6 +29,7 @@ CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T2080RDB_revD_SDCARD_defconfig b/configs/T2080RDB_revD_SDCARD_defconfig index 7d67f728b4c8..efceef7c656d 100644 --- a/configs/T2080RDB_revD_SDCARD_defconfig +++ b/configs/T2080RDB_revD_SDCARD_defconfig @@ -29,6 +29,7 @@ CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T2080RDB_revD_SPIFLASH_defconfig b/configs/T2080RDB_revD_SPIFLASH_defconfig index 0f7658b88890..6934e3a502ac 100644 --- a/configs/T2080RDB_revD_SPIFLASH_defconfig +++ b/configs/T2080RDB_revD_SPIFLASH_defconfig @@ -31,6 +31,7 @@ CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T2080RDB_revD_defconfig b/configs/T2080RDB_revD_defconfig index f9c85dfccfdd..7689df244d33 100644 --- a/configs/T2080RDB_revD_defconfig +++ b/configs/T2080RDB_revD_defconfig @@ -23,6 +23,7 @@ CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_SYS_MEMTEST_START=0x00200000 CONFIG_SYS_MEMTEST_END=0x00400000 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index de25f325990c..a404a8021d4d 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -26,6 +26,7 @@ CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=5 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index bd125980d051..b0a4eaac4a80 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -20,6 +20,7 @@ CONFIG_VID_FLS_ENV="t4240rdb_vdd_mv" CONFIG_VOL_MONITOR_IR36021_READ=y CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=5 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/UTOO_P66_defconfig b/configs/UTOO_P66_defconfig index b021b0a8865c..d7912e18eaec 100644 --- a/configs/UTOO_P66_defconfig +++ b/configs/UTOO_P66_defconfig @@ -20,6 +20,7 @@ CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_TL059WV5C0=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Wexler_TAB7200_defconfig b/configs/Wexler_TAB7200_defconfig index 101ce57aa44d..8e729b8dc9c1 100644 --- a/configs/Wexler_TAB7200_defconfig +++ b/configs/Wexler_TAB7200_defconfig @@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Wits_Pro_A20_DKT_defconfig b/configs/Wits_Pro_A20_DKT_defconfig index f401ac74ef47..2eb1331e4d36 100644 --- a/configs/Wits_Pro_A20_DKT_defconfig +++ b/configs/Wits_Pro_A20_DKT_defconfig @@ -12,6 +12,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/Wobo_i5_defconfig b/configs/Wobo_i5_defconfig index e0687bf887db..fb8774786ecc 100644 --- a/configs/Wobo_i5_defconfig +++ b/configs/Wobo_i5_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=432 CONFIG_MMC0_CD_PIN="PB3" CONFIG_USB1_VBUS_PIN="PG12" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Yones_Toptech_BD1078_defconfig b/configs/Yones_Toptech_BD1078_defconfig index f1ceb8b55275..31e79ac6e340 100644 --- a/configs/Yones_Toptech_BD1078_defconfig +++ b/configs/Yones_Toptech_BD1078_defconfig @@ -19,6 +19,7 @@ CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_VIDEO_LCD_BL_PWM_ACTIVE_LOW is not set CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/Yones_Toptech_BS1078_V2_defconfig b/configs/Yones_Toptech_BS1078_V2_defconfig index 6701ecce2fef..625f72903a33 100644 --- a/configs/Yones_Toptech_BS1078_V2_defconfig +++ b/configs/Yones_Toptech_BS1078_V2_defconfig @@ -16,5 +16,6 @@ CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_USB_MUSB_HOST=y diff --git a/configs/a64-olinuxino-emmc_defconfig b/configs/a64-olinuxino-emmc_defconfig index 8ec9eb3e9c2d..c3eaaa758586 100644 --- a/configs/a64-olinuxino-emmc_defconfig +++ b/configs/a64-olinuxino-emmc_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/a64-olinuxino_defconfig b/configs/a64-olinuxino_defconfig index 16cef18beefe..763230245236 100644 --- a/configs/a64-olinuxino_defconfig +++ b/configs/a64-olinuxino_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/ae350_rv32_defconfig b/configs/ae350_rv32_defconfig index b73755d9d1e9..9e97afc8e538 100644 --- a/configs/ae350_rv32_defconfig +++ b/configs/ae350_rv32_defconfig @@ -10,6 +10,7 @@ CONFIG_TARGET_AX25_AE350=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe80 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 diff --git a/configs/ae350_rv32_spl_defconfig b/configs/ae350_rv32_spl_defconfig index 98d39eea09a0..6862c1883370 100644 --- a/configs/ae350_rv32_spl_defconfig +++ b/configs/ae350_rv32_spl_defconfig @@ -14,6 +14,7 @@ CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffff00 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x00200000 CONFIG_SYS_MONITOR_BASE=0x88000000 diff --git a/configs/ae350_rv32_spl_xip_defconfig b/configs/ae350_rv32_spl_xip_defconfig index 67c1e35c557c..a5c93f85087a 100644 --- a/configs/ae350_rv32_spl_xip_defconfig +++ b/configs/ae350_rv32_spl_xip_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL_XIP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xffff00 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80010000 CONFIG_SYS_MONITOR_BASE=0x88000000 diff --git a/configs/ae350_rv32_xip_defconfig b/configs/ae350_rv32_xip_defconfig index f5bbece8eba7..c8a834ff1b57 100644 --- a/configs/ae350_rv32_xip_defconfig +++ b/configs/ae350_rv32_xip_defconfig @@ -11,6 +11,7 @@ CONFIG_XIP=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0xfffe80 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_SYS_MONITOR_BASE=0x88000000 CONFIG_BOOTDELAY=3 diff --git a/configs/alt_defconfig b/configs/alt_defconfig index 4549cd5d0d7d..2f052ea329fa 100644 --- a/configs/alt_defconfig +++ b/configs/alt_defconfig @@ -28,6 +28,7 @@ CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_ENV_ADDR=0xC0000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_SPL_MAX_SIZE=0x4000 diff --git a/configs/am3517_evm_defconfig b/configs/am3517_evm_defconfig index c6accc66ed87..d7709d5de08c 100644 --- a/configs/am3517_evm_defconfig +++ b/configs/am3517_evm_defconfig @@ -17,6 +17,7 @@ CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_BOOTDELAY=10 CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then echo SD/MMC found on device $mmcdev; if run loadbootenv; then run importbootenv; fi; echo Checking if uenvcmd is set ...; if test -n $uenvcmd; then echo Running uenvcmd ...; run uenvcmd; fi; echo Running default loadimage ...; setenv bootfile zImage; if run loadimage; then run loadfdt; run mmcboot; fi; else run nandboot; fi" CONFIG_SPL_MAX_SIZE=0xec00 diff --git a/configs/amarula_a64_relic_defconfig b/configs/amarula_a64_relic_defconfig index ae44b66d1092..66c245ff0ae7 100644 --- a/configs/amarula_a64_relic_defconfig +++ b/configs/amarula_a64_relic_defconfig @@ -7,6 +7,7 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y CONFIG_USB_MUSB_GADGET=y diff --git a/configs/amcore_defconfig b/configs/amcore_defconfig index 6054e8086386..78ac65dca8c1 100644 --- a/configs/amcore_defconfig +++ b/configs/amcore_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_ENV_ADDR=0xFFC1F000 CONFIG_TARGET_AMCORE=y CONFIG_MCFTMR=y +CONFIG_SYS_MONITOR_LEN=126976 CONFIG_SYS_MONITOR_BASE=0xFFC00400 CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTCOMMAND=y diff --git a/configs/apalis_imx6_defconfig b/configs/apalis_imx6_defconfig index 2689e8d9846a..44fd5f095221 100644 --- a/configs/apalis_imx6_defconfig +++ b/configs/apalis_imx6_defconfig @@ -27,6 +27,7 @@ CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x10000000 CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=1 diff --git a/configs/astro_mcf5373l_defconfig b/configs/astro_mcf5373l_defconfig index f0c91d4ca455..da2649f1da51 100644 --- a/configs/astro_mcf5373l_defconfig +++ b/configs/astro_mcf5373l_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_ENV_ADDR=0x1FF8000 CONFIG_TARGET_ASTRO_MCF5373L=y CONFIG_MCFTMR=y +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_BASE=0x00000400 CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9263ek_norflash_boot_defconfig b/configs/at91sam9263ek_norflash_boot_defconfig index b0a01c2c689d..1542a74aac93 100644 --- a/configs/at91sam9263ek_norflash_boot_defconfig +++ b/configs/at91sam9263ek_norflash_boot_defconfig @@ -18,6 +18,7 @@ CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_ENV_ADDR=0x107E0000 CONFIG_DEBUG_UART=y +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_BASE=0x10000000 CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/at91sam9263ek_norflash_defconfig b/configs/at91sam9263ek_norflash_defconfig index fbf40ef52400..5bb865ad607d 100644 --- a/configs/at91sam9263ek_norflash_defconfig +++ b/configs/at91sam9263ek_norflash_defconfig @@ -19,6 +19,7 @@ CONFIG_DEBUG_UART_BOARD_INIT=y CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_ENV_ADDR=0x107E0000 CONFIG_DEBUG_UART=y +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_BASE=0x10000000 CONFIG_BOOTDELAY=3 CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/at91sam9m10g45ek_mmc_defconfig b/configs/at91sam9m10g45ek_mmc_defconfig index dd088ed8c89a..8c123e07f3e5 100644 --- a/configs/at91sam9m10g45ek_mmc_defconfig +++ b/configs/at91sam9m10g45ek_mmc_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x70003f00 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9m10g45ek_nandflash_defconfig b/configs/at91sam9m10g45ek_nandflash_defconfig index 64a2490857b5..97ef4ccd9c53 100644 --- a/configs/at91sam9m10g45ek_nandflash_defconfig +++ b/configs/at91sam9m10g45ek_nandflash_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x70003f00 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9n12ek_mmc_defconfig b/configs/at91sam9n12ek_mmc_defconfig index 1902844803f2..cf181688c003 100644 --- a/configs/at91sam9n12ek_mmc_defconfig +++ b/configs/at91sam9n12ek_mmc_defconfig @@ -15,6 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x303f00 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y diff --git a/configs/at91sam9n12ek_nandflash_defconfig b/configs/at91sam9n12ek_nandflash_defconfig index 5e727cfab831..30c6927e88df 100644 --- a/configs/at91sam9n12ek_nandflash_defconfig +++ b/configs/at91sam9n12ek_nandflash_defconfig @@ -15,6 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x303f00 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y diff --git a/configs/at91sam9n12ek_spiflash_defconfig b/configs/at91sam9n12ek_spiflash_defconfig index faa7eece3e7d..46fdddf41c37 100644 --- a/configs/at91sam9n12ek_spiflash_defconfig +++ b/configs/at91sam9n12ek_spiflash_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x303f00 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y diff --git a/configs/at91sam9x5ek_dataflash_defconfig b/configs/at91sam9x5ek_dataflash_defconfig index da2f263a9d36..433da7e7bc40 100644 --- a/configs/at91sam9x5ek_dataflash_defconfig +++ b/configs/at91sam9x5ek_dataflash_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/at91sam9x5ek_mmc_defconfig b/configs/at91sam9x5ek_mmc_defconfig index 017afc2275b2..38562429a091 100644 --- a/configs/at91sam9x5ek_mmc_defconfig +++ b/configs/at91sam9x5ek_mmc_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/at91sam9x5ek_nandflash_defconfig b/configs/at91sam9x5ek_nandflash_defconfig index 84a6024826b6..b6c1b76930ae 100644 --- a/configs/at91sam9x5ek_nandflash_defconfig +++ b/configs/at91sam9x5ek_nandflash_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/at91sam9x5ek_spiflash_defconfig b/configs/at91sam9x5ek_spiflash_defconfig index 145a989beda5..6bfaca385ed8 100644 --- a/configs/at91sam9x5ek_spiflash_defconfig +++ b/configs/at91sam9x5ek_spiflash_defconfig @@ -19,6 +19,7 @@ CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/ba10_tv_box_defconfig b/configs/ba10_tv_box_defconfig index b89dd8ea62b4..9268cebed64b 100644 --- a/configs/ba10_tv_box_defconfig +++ b/configs/ba10_tv_box_defconfig @@ -9,6 +9,7 @@ CONFIG_USB0_VBUS_PIN="PB9" CONFIG_USB2_VBUS_PIN="PH12" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/bananapi_m1_plus_defconfig b/configs/bananapi_m1_plus_defconfig index 0fbb619d6231..12ea6a3236a5 100644 --- a/configs/bananapi_m1_plus_defconfig +++ b/configs/bananapi_m1_plus_defconfig @@ -9,6 +9,7 @@ CONFIG_VIDEO_COMPOSITE=y CONFIG_GMAC_TX_DELAY=3 CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_NETCONSOLE=y CONFIG_SCSI_AHCI=y diff --git a/configs/bananapi_m2_berry_defconfig b/configs/bananapi_m2_berry_defconfig index 588eea2a27d1..63f9c1498270 100644 --- a/configs/bananapi_m2_berry_defconfig +++ b/configs/bananapi_m2_berry_defconfig @@ -9,6 +9,7 @@ CONFIG_USB1_VBUS_PIN="PH23" # CONFIG_HAS_ARMV7_SECURE_BASE is not set CONFIG_AHCI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SCSI_AHCI=y CONFIG_SYS_64BIT_LBA=y diff --git a/configs/bananapi_m2_plus_h3_defconfig b/configs/bananapi_m2_plus_h3_defconfig index 26ced59fb02b..2bd5a70a2d06 100644 --- a/configs/bananapi_m2_plus_h3_defconfig +++ b/configs/bananapi_m2_plus_h3_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=672 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/bananapi_m2_plus_h5_defconfig b/configs/bananapi_m2_plus_h5_defconfig index fb6c945919a0..926cf6f5a4d6 100644 --- a/configs/bananapi_m2_plus_h5_defconfig +++ b/configs/bananapi_m2_plus_h5_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=672 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/bananapi_m2_zero_defconfig b/configs/bananapi_m2_zero_defconfig index ac3f8f5ab8bc..b351d505a410 100644 --- a/configs/bananapi_m2_zero_defconfig +++ b/configs/bananapi_m2_zero_defconfig @@ -6,3 +6,4 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 CONFIG_MMC0_CD_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 diff --git a/configs/bananapi_m64_defconfig b/configs/bananapi_m64_defconfig index 5463b046fdb2..74fa637fd3cf 100644 --- a/configs/bananapi_m64_defconfig +++ b/configs/bananapi_m64_defconfig @@ -7,6 +7,7 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/beelink_gs1_defconfig b/configs/beelink_gs1_defconfig index 42925eabcb0a..7d8f2160c855 100644 --- a/configs/beelink_gs1_defconfig +++ b/configs/beelink_gs1_defconfig @@ -8,6 +8,7 @@ CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/beelink_x2_defconfig b/configs/beelink_x2_defconfig index 6206d9090031..68acb6b26335 100644 --- a/configs/beelink_x2_defconfig +++ b/configs/beelink_x2_defconfig @@ -6,5 +6,6 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=567 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/blanche_defconfig b/configs/blanche_defconfig index 3cbec64a8f26..94e15201a35a 100644 --- a/configs/blanche_defconfig +++ b/configs/blanche_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_ENV_ADDR=0x40000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_HUSH_PARSER=y diff --git a/configs/cherryhill_defconfig b/configs/cherryhill_defconfig index 9c3d26a36e13..87a86b451de4 100644 --- a/configs/cherryhill_defconfig +++ b/configs/cherryhill_defconfig @@ -12,6 +12,7 @@ CONFIG_TARGET_CHERRYHILL=y CONFIG_DEBUG_UART=y CONFIG_SMP=y CONFIG_GENERATE_MP_TABLE=y +CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="ext2load scsi 0:3 01000000 /boot/vmlinuz; zboot 01000000" diff --git a/configs/chromebit_mickey_defconfig b/configs/chromebit_mickey_defconfig index 657db6626506..887a183777f4 100644 --- a/configs/chromebit_mickey_defconfig +++ b/configs/chromebit_mickey_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 +CONFIG_SYS_MONITOR_LEN=614400 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-mickey.dtb" # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/chromebook_jerry_defconfig b/configs/chromebook_jerry_defconfig index 13ffafceec35..faa30771bdc4 100644 --- a/configs/chromebook_jerry_defconfig +++ b/configs/chromebook_jerry_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 +CONFIG_SYS_MONITOR_LEN=614400 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-jerry.dtb" CONFIG_SILENT_CONSOLE=y diff --git a/configs/chromebook_minnie_defconfig b/configs/chromebook_minnie_defconfig index d80dd8e56c94..a3b0d1a776b7 100644 --- a/configs/chromebook_minnie_defconfig +++ b/configs/chromebook_minnie_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 +CONFIG_SYS_MONITOR_LEN=614400 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-minnie.dtb" CONFIG_SILENT_CONSOLE=y diff --git a/configs/chromebook_speedy_defconfig b/configs/chromebook_speedy_defconfig index 8e0214d21e22..cb90880f9762 100644 --- a/configs/chromebook_speedy_defconfig +++ b/configs/chromebook_speedy_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 +CONFIG_SYS_MONITOR_LEN=614400 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-veyron-speedy.dtb" CONFIG_SILENT_CONSOLE=y diff --git a/configs/ci20_mmc_defconfig b/configs/ci20_mmc_defconfig index 07848a5933eb..02dcf613d29b 100644 --- a/configs/ci20_mmc_defconfig +++ b/configs/ci20_mmc_defconfig @@ -13,6 +13,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x81000000 CONFIG_ARCH_JZ47XX=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS4,115200 rw rootwait root=/dev/mmcblk0p1" diff --git a/configs/cl-som-imx7_defconfig b/configs/cl-som-imx7_defconfig index c55c6c56e50e..f3ee559d21fc 100644 --- a/configs/cl-som-imx7_defconfig +++ b/configs/cl-som-imx7_defconfig @@ -21,6 +21,7 @@ CONFIG_SPL_SPI=y CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTCOMMAND=y diff --git a/configs/cm_fx6_defconfig b/configs/cm_fx6_defconfig index e323438506fe..df327a7229c0 100644 --- a/configs/cm_fx6_defconfig +++ b/configs/cm_fx6_defconfig @@ -25,6 +25,7 @@ CONFIG_SPL_SPI=y # CONFIG_CMD_BMODE is not set CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd; run legacy_bootcmd" diff --git a/configs/cm_t43_defconfig b/configs/cm_t43_defconfig index eaeddc8c96ab..0a5ce2046f1c 100644 --- a/configs/cm_t43_defconfig +++ b/configs/cm_t43_defconfig @@ -25,6 +25,7 @@ CONFIG_SPL_SPI=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4033ff00 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_BOOTCOMMAND="mmc dev 0; if mmc rescan; then if run loadbootscript; then run bootscript; fi; fi; mmc dev 1; if mmc rescan; then run emmcboot; fi;" CONFIG_SYS_CONSOLE_INFO_QUIET=y # CONFIG_DISPLAY_CPUINFO is not set diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig index e8c91b8beff3..68f0b3a59098 100644 --- a/configs/cobra5272_defconfig +++ b/configs/cobra5272_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_LOAD_ADDR=0x20000 CONFIG_ENV_ADDR=0xFFE04000 CONFIG_TARGET_COBRA5272=y CONFIG_MCFTMR=y +CONFIG_SYS_MONITOR_LEN=131072 CONFIG_SYS_MONITOR_BASE=0xFFE00400 CONFIG_BOOTDELAY=5 # CONFIG_DISPLAY_BOARDINFO is not set diff --git a/configs/colibri_imx6_defconfig b/configs/colibri_imx6_defconfig index 135095b275db..1f879447ca17 100644 --- a/configs/colibri_imx6_defconfig +++ b/configs/colibri_imx6_defconfig @@ -26,6 +26,7 @@ CONFIG_SYS_LOAD_ADDR=0x14200000 CONFIG_SYS_MEMTEST_START=0x10000000 CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=1 diff --git a/configs/colorfly_e708_q1_defconfig b/configs/colorfly_e708_q1_defconfig index 5d3636e34e8c..a7496c8a0b94 100644 --- a/configs/colorfly_e708_q1_defconfig +++ b/configs/colorfly_e708_q1_defconfig @@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_AXP_DLDO2_VOLT=1800 CONFIG_USB_MUSB_HOST=y diff --git a/configs/cougarcanyon2_defconfig b/configs/cougarcanyon2_defconfig index 7ee0cb746e40..55db01d210a7 100644 --- a/configs/cougarcanyon2_defconfig +++ b/configs/cougarcanyon2_defconfig @@ -12,6 +12,7 @@ CONFIG_TARGET_COUGARCANYON2=y CONFIG_SMP=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y +CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_SHOW_BOOT_PROGRESS=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/sdb3 init=/sbin/init rootwait ro" diff --git a/configs/devkit3250_defconfig b/configs/devkit3250_defconfig index 744ffbd94333..41e458560985 100644 --- a/configs/devkit3250_defconfig +++ b/configs/devkit3250_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x80008000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80000f20 +CONFIG_SYS_MONITOR_LEN=393216 CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS0,115200n8" diff --git a/configs/devkit8000_defconfig b/configs/devkit8000_defconfig index 9244787fb7d2..372c1046465f 100644 --- a/configs/devkit8000_defconfig +++ b/configs/devkit8000_defconfig @@ -12,6 +12,7 @@ CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_BOOTCOMMAND="run autoboot" CONFIG_USE_PREBOOT=y CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/dh_imx6_defconfig b/configs/dh_imx6_defconfig index 463c6d4477dc..63aabe96b88b 100644 --- a/configs/dh_imx6_defconfig +++ b/configs/dh_imx6_defconfig @@ -29,6 +29,7 @@ CONFIG_AHCI=y CONFIG_SYS_MEMTEST_START=0x10000000 CONFIG_SYS_MEMTEST_END=0x20000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT=y diff --git a/configs/difrnce_dit4350_defconfig b/configs/difrnce_dit4350_defconfig index e1067b66eec2..1b292644d170 100644 --- a/configs/difrnce_dit4350_defconfig +++ b/configs/difrnce_dit4350_defconfig @@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/display5_defconfig b/configs/display5_defconfig index 29397cb3fbd4..64ceb77eb7d2 100644 --- a/configs/display5_defconfig +++ b/configs/display5_defconfig @@ -29,6 +29,7 @@ CONFIG_SYS_BOOTCOUNT_SINGLEWORD=y CONFIG_ENV_OFFSET_REDUND=0x130000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set diff --git a/configs/display5_factory_defconfig b/configs/display5_factory_defconfig index 7ae636738de8..05686af8bb54 100644 --- a/configs/display5_factory_defconfig +++ b/configs/display5_factory_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x130000 CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set diff --git a/configs/dserve_dsrv9703c_defconfig b/configs/dserve_dsrv9703c_defconfig index 60910c3ce354..d81782f727d2 100644 --- a/configs/dserve_dsrv9703c_defconfig +++ b/configs/dserve_dsrv9703c_defconfig @@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/eb_cpu5282_defconfig b/configs/eb_cpu5282_defconfig index b46d16377168..f36ba771e1ed 100644 --- a/configs/eb_cpu5282_defconfig +++ b/configs/eb_cpu5282_defconfig @@ -9,6 +9,7 @@ CONFIG_ENV_ADDR=0xFF040000 CONFIG_TARGET_EB_CPU5282=y CONFIG_MCFTMR=y CONFIG_SYS_BARGSIZE=1024 +CONFIG_SYS_MONITOR_LEN=131072 CONFIG_SYS_MONITOR_BASE=0xFF000400 CONFIG_BOOTDELAY=5 CONFIG_BOOT_RETRY=y diff --git a/configs/eb_cpu5282_internal_defconfig b/configs/eb_cpu5282_internal_defconfig index cd0fe911108d..95b5e5987f5c 100644 --- a/configs/eb_cpu5282_internal_defconfig +++ b/configs/eb_cpu5282_internal_defconfig @@ -8,6 +8,7 @@ CONFIG_ENV_ADDR=0xFF040000 CONFIG_TARGET_EB_CPU5282=y CONFIG_MCFTMR=y CONFIG_SYS_BARGSIZE=1024 +CONFIG_SYS_MONITOR_LEN=131072 CONFIG_SYS_MONITOR_BASE=0xF0000418 CONFIG_BOOTDELAY=5 CONFIG_BOOT_RETRY=y diff --git a/configs/edison_defconfig b/configs/edison_defconfig index dbca94525ed4..2c1c5ef8ca35 100644 --- a/configs/edison_defconfig +++ b/configs/edison_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_LOAD_ADDR=0x100000 CONFIG_VENDOR_INTEL=y CONFIG_TARGET_EDISON=y CONFIG_SMP=y +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_BASE=0x01101000 CONFIG_BOARD_EARLY_INIT_R=y CONFIG_LAST_STAGE_INIT=y diff --git a/configs/emlid_neutis_n5_devboard_defconfig b/configs/emlid_neutis_n5_devboard_defconfig index a3b43dffc63c..e482f3cb19e6 100644 --- a/configs/emlid_neutis_n5_devboard_defconfig +++ b/configs/emlid_neutis_n5_devboard_defconfig @@ -8,4 +8,5 @@ CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUPPORT_EMMC_BOOT=y diff --git a/configs/ethernut5_defconfig b/configs/ethernut5_defconfig index b8542ecbf7dd..05727e04ff9f 100644 --- a/configs/ethernut5_defconfig +++ b/configs/ethernut5_defconfig @@ -31,9 +31,9 @@ CONFIG_CMD_ASKENV=y CONFIG_CMD_UNZIP=y CONFIG_CMD_I2C=y # CONFIG_CMD_LOADS is not set +CONFIG_CMD_SAVES=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND=y -CONFIG_CMD_SAVES=y CONFIG_CMD_SPI=y CONFIG_CMD_DHCP=y CONFIG_BOOTP_BOOTFILESIZE=y diff --git a/configs/evb-rk3288_defconfig b/configs/evb-rk3288_defconfig index 40e235b1ca7c..b0f68731eeb2 100644 --- a/configs/evb-rk3288_defconfig +++ b/configs/evb-rk3288_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 +CONFIG_SYS_MONITOR_LEN=614400 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/firefly-rk3288_defconfig b/configs/firefly-rk3288_defconfig index 1349d6464d11..3d964c0fded8 100644 --- a/configs/firefly-rk3288_defconfig +++ b/configs/firefly-rk3288_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 +CONFIG_SYS_MONITOR_LEN=614400 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-firefly.dtb" diff --git a/configs/ga10h_v1_1_defconfig b/configs/ga10h_v1_1_defconfig index 599eeb96b4f2..03ba9dd26bf7 100644 --- a/configs/ga10h_v1_1_defconfig +++ b/configs/ga10h_v1_1_defconfig @@ -17,6 +17,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_EHCI_HCD=y diff --git a/configs/gardena-smart-gateway-at91sam_defconfig b/configs/gardena-smart-gateway-at91sam_defconfig index e889befcca6b..ef690f8c9f7b 100644 --- a/configs/gardena-smart-gateway-at91sam_defconfig +++ b/configs/gardena-smart-gateway-at91sam_defconfig @@ -25,6 +25,7 @@ CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003f00 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=0 diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig index a184e81fb9dc..a89908b1003f 100644 --- a/configs/gazerbeam_defconfig +++ b/configs/gazerbeam_defconfig @@ -114,6 +114,7 @@ CONFIG_CMD_IOLOOP=y CONFIG_SYS_MEMTEST_START=0x00001000 CONFIG_SYS_MEMTEST_END=0x07e00000 CONFIG_SYS_BARGSIZE=1024 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y diff --git a/configs/gose_defconfig b/configs/gose_defconfig index 930755c668fd..b22842ca5fb6 100644 --- a/configs/gose_defconfig +++ b/configs/gose_defconfig @@ -28,6 +28,7 @@ CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_ENV_ADDR=0xC0000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_SPL_MAX_SIZE=0x4000 diff --git a/configs/grpeach_defconfig b/configs/grpeach_defconfig index 946d81cc04cd..1ea4ede094fa 100644 --- a/configs/grpeach_defconfig +++ b/configs/grpeach_defconfig @@ -15,6 +15,7 @@ CONFIG_SYS_CLK_FREQ=66666666 CONFIG_SYS_LOAD_ADDR=0x20400000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20900000 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="ignore_loglevel" diff --git a/configs/gt90h_v4_defconfig b/configs/gt90h_v4_defconfig index 1a5fe06bbe11..4069cf14b082 100644 --- a/configs/gt90h_v4_defconfig +++ b/configs/gt90h_v4_defconfig @@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/gwventana_emmc_defconfig b/configs/gwventana_emmc_defconfig index decbf5fbd603..ac120480ccc8 100644 --- a/configs/gwventana_emmc_defconfig +++ b/configs/gwventana_emmc_defconfig @@ -25,6 +25,7 @@ CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0xD1400 CONFIG_CMD_HDMIDETECT=y CONFIG_AHCI=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y diff --git a/configs/gwventana_gw5904_defconfig b/configs/gwventana_gw5904_defconfig index a5b31514ff12..a4ed7bef7fba 100644 --- a/configs/gwventana_gw5904_defconfig +++ b/configs/gwventana_gw5904_defconfig @@ -25,6 +25,7 @@ CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0xD1400 CONFIG_CMD_HDMIDETECT=y CONFIG_AHCI=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y diff --git a/configs/gwventana_nand_defconfig b/configs/gwventana_nand_defconfig index ff826deb73e1..16f7c602d6c4 100644 --- a/configs/gwventana_nand_defconfig +++ b/configs/gwventana_nand_defconfig @@ -25,6 +25,7 @@ CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x1080000 CONFIG_CMD_HDMIDETECT=y CONFIG_AHCI=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y diff --git a/configs/h8_homlet_v2_defconfig b/configs/h8_homlet_v2_defconfig index 29f965200e1a..cf3e7ce73aae 100644 --- a/configs/h8_homlet_v2_defconfig +++ b/configs/h8_homlet_v2_defconfig @@ -10,6 +10,7 @@ CONFIG_USB0_VBUS_PIN="PL5" CONFIG_USB1_VBUS_PIN="PL6" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_CONSOLE_MUX=y CONFIG_AXP_DLDO4_VOLT=3300 CONFIG_USB_EHCI_HCD=y diff --git a/configs/hihope_rzg2_defconfig b/configs/hihope_rzg2_defconfig index f9a2e73b11e6..f8d5b035def9 100644 --- a/configs/hihope_rzg2_defconfig +++ b/configs/hihope_rzg2_defconfig @@ -13,6 +13,7 @@ CONFIG_TARGET_HIHOPE_RZG2=y # CONFIG_SPL is not set CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y diff --git a/configs/i12-tvbox_defconfig b/configs/i12-tvbox_defconfig index 257dd89af45b..d75a7992a82e 100644 --- a/configs/i12-tvbox_defconfig +++ b/configs/i12-tvbox_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=384 CONFIG_MACPWR="PH21" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/iNet_3F_defconfig b/configs/iNet_3F_defconfig index 436e3a8c209f..67474a8e62b0 100644 --- a/configs/iNet_3F_defconfig +++ b/configs/iNet_3F_defconfig @@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/iNet_3W_defconfig b/configs/iNet_3W_defconfig index 6978f8b0aabd..23d41b796dc3 100644 --- a/configs/iNet_3W_defconfig +++ b/configs/iNet_3W_defconfig @@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/iNet_86VS_defconfig b/configs/iNet_86VS_defconfig index 2c8ecb51de05..d51561eacc6b 100644 --- a/configs/iNet_86VS_defconfig +++ b/configs/iNet_86VS_defconfig @@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/iNet_D978_rev2_defconfig b/configs/iNet_D978_rev2_defconfig index 9a90252dbd7a..8057df5ef11d 100644 --- a/configs/iNet_D978_rev2_defconfig +++ b/configs/iNet_D978_rev2_defconfig @@ -17,6 +17,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 # CONFIG_REQUIRE_SERIAL_CONSOLE is not set CONFIG_CONS_INDEX=5 diff --git a/configs/icnova-a20-swac_defconfig b/configs/icnova-a20-swac_defconfig index c759d7e2357f..80441b32baa5 100644 --- a/configs/icnova-a20-swac_defconfig +++ b/configs/icnova-a20-swac_defconfig @@ -17,6 +17,7 @@ CONFIG_VIDEO_LCD_MODE="x:800,y:480,depth:24,pclk_khz:33000,le:45,ri:209,up:22,lo CONFIG_VIDEO_LCD_POWER="PH22" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_CMD_UNZIP=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/igep00x0_defconfig b/configs/igep00x0_defconfig index 25eda11dd45e..997c2df9753f 100644 --- a/configs/igep00x0_defconfig +++ b/configs/igep00x0_defconfig @@ -11,6 +11,7 @@ CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" diff --git a/configs/imx6dl_mamoj_defconfig b/configs/imx6dl_mamoj_defconfig index 067498d80e32..ac6f622c2159 100644 --- a/configs/imx6dl_mamoj_defconfig +++ b/configs/imx6dl_mamoj_defconfig @@ -16,6 +16,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_BOOTDELAY=3 CONFIG_SYS_SPL_MALLOC=y CONFIG_SPL_OS_BOOT=y diff --git a/configs/imx6q_bosch_acc_defconfig b/configs/imx6q_bosch_acc_defconfig index 7ed31d6b8822..301b32b13438 100644 --- a/configs/imx6q_bosch_acc_defconfig +++ b/configs/imx6q_bosch_acc_defconfig @@ -26,6 +26,7 @@ CONFIG_IMX_HAB=y # CONFIG_CMD_DEKBLOB is not set CONFIG_BUILD_TARGET="" # CONFIG_LOCALVERSION_AUTO is not set +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y diff --git a/configs/imx6q_logic_defconfig b/configs/imx6q_logic_defconfig index 98c54c7b3473..b76b99b02b73 100644 --- a/configs/imx6q_logic_defconfig +++ b/configs/imx6q_logic_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_MEMTEST_START=0x10000000 CONFIG_SYS_MEMTEST_END=0x10010000 CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run autoboot" CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/imx6qdl_icore_mipi_defconfig b/configs/imx6qdl_icore_mipi_defconfig index e4b1866a0d09..e6dea95c7c9f 100644 --- a/configs/imx6qdl_icore_mipi_defconfig +++ b/configs/imx6qdl_icore_mipi_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y diff --git a/configs/imx6qdl_icore_mmc_defconfig b/configs/imx6qdl_icore_mmc_defconfig index 0ace5d93713d..28083212e9f6 100644 --- a/configs/imx6qdl_icore_mmc_defconfig +++ b/configs/imx6qdl_icore_mmc_defconfig @@ -26,6 +26,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DEBUG_UART=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y diff --git a/configs/imx6qdl_icore_rqs_defconfig b/configs/imx6qdl_icore_rqs_defconfig index d3592a0744c1..aee8ace2396d 100644 --- a/configs/imx6qdl_icore_rqs_defconfig +++ b/configs/imx6qdl_icore_rqs_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_CMD_BMODE is not set CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y diff --git a/configs/imx6ul_geam_mmc_defconfig b/configs/imx6ul_geam_mmc_defconfig index e5dd7c0f394d..3b3110f81d54 100644 --- a/configs/imx6ul_geam_mmc_defconfig +++ b/configs/imx6ul_geam_mmc_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_CMD_BMODE is not set CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y diff --git a/configs/imx6ul_isiot_emmc_defconfig b/configs/imx6ul_isiot_emmc_defconfig index 3bca92c5b9e4..06fd2986a1cf 100644 --- a/configs/imx6ul_isiot_emmc_defconfig +++ b/configs/imx6ul_isiot_emmc_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_CMD_BMODE is not set CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y diff --git a/configs/imx7_cm_defconfig b/configs/imx7_cm_defconfig index 4dfb46905954..b297e3373318 100644 --- a/configs/imx7_cm_defconfig +++ b/configs/imx7_cm_defconfig @@ -21,6 +21,7 @@ CONFIG_ARMV7_BOOT_SEC_DEFAULT=y CONFIG_IMX_RDC=y CONFIG_IMX_BOOTAUX=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_BOOTCOMMAND="run boot${boot-mode}" CONFIG_DEFAULT_FDT_FILE="ask" # CONFIG_BOARD_EARLY_INIT_F is not set diff --git a/configs/imx8mm-cl-iot-gate-optee_defconfig b/configs/imx8mm-cl-iot-gate-optee_defconfig index 9ab217354b6d..0774addc8f66 100644 --- a/configs/imx8mm-cl-iot-gate-optee_defconfig +++ b/configs/imx8mm-cl-iot-gate-optee_defconfig @@ -17,6 +17,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_FIT_SIGNATURE=y diff --git a/configs/imx8mm-cl-iot-gate_defconfig b/configs/imx8mm-cl-iot-gate_defconfig index 73d938834a13..039f3676f576 100644 --- a/configs/imx8mm-cl-iot-gate_defconfig +++ b/configs/imx8mm-cl-iot-gate_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x204000 CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_FIT_SIGNATURE=y diff --git a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig index d3e0b0541811..adb9c5ebff37 100644 --- a/configs/imx8mm-icore-mx8mm-ctouch2_defconfig +++ b/configs/imx8mm-icore-mx8mm-ctouch2_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig index 29addb5356a3..a8daedfbb95f 100644 --- a/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig +++ b/configs/imx8mm-icore-mx8mm-edimm2.2_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mm-mx8menlo_defconfig b/configs/imx8mm-mx8menlo_defconfig index ad6885942d3f..73d1f9c87e92 100644 --- a/configs/imx8mm-mx8menlo_defconfig +++ b/configs/imx8mm-mx8menlo_defconfig @@ -24,6 +24,7 @@ CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mm_beacon_defconfig b/configs/imx8mm_beacon_defconfig index e37ce01c1924..a9c0da50c66e 100644 --- a/configs/imx8mm_beacon_defconfig +++ b/configs/imx8mm_beacon_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_LTO=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mm_data_modul_edm_sbc_defconfig b/configs/imx8mm_data_modul_edm_sbc_defconfig index b246fbdc9e88..d3ce42a374fc 100644 --- a/configs/imx8mm_data_modul_edm_sbc_defconfig +++ b/configs/imx8mm_data_modul_edm_sbc_defconfig @@ -25,6 +25,7 @@ CONFIG_ENV_OFFSET_REDUND=0xFFFC0000 CONFIG_IMX_BOOTAUX=y CONFIG_SYS_LOAD_ADDR=0x60000000 CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mm_evk_defconfig b/configs/imx8mm_evk_defconfig index 2dff26b3eb87..63d9db356216 100644 --- a/configs/imx8mm_evk_defconfig +++ b/configs/imx8mm_evk_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mm_evk_fspi_defconfig b/configs/imx8mm_evk_fspi_defconfig index 21fd7e08db1c..2a93a1fccd76 100644 --- a/configs/imx8mm_evk_fspi_defconfig +++ b/configs/imx8mm_evk_fspi_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mm_venice_defconfig b/configs/imx8mm_venice_defconfig index cf8809291825..ad620ffe5edd 100644 --- a/configs/imx8mm_venice_defconfig +++ b/configs/imx8mm_venice_defconfig @@ -22,6 +22,7 @@ CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mn_beacon_2g_defconfig b/configs/imx8mn_beacon_2g_defconfig index 613945a9ec6c..c1ec56735688 100644 --- a/configs/imx8mn_beacon_2g_defconfig +++ b/configs/imx8mn_beacon_2g_defconfig @@ -24,6 +24,7 @@ CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x44000000 CONFIG_LTO=y CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mn_beacon_defconfig b/configs/imx8mn_beacon_defconfig index cc1583524ba3..5be30d4e74dc 100644 --- a/configs/imx8mn_beacon_defconfig +++ b/configs/imx8mn_beacon_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x44000000 CONFIG_LTO=y CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mn_bsh_smm_s2_defconfig b/configs/imx8mn_bsh_smm_s2_defconfig index 588597f92b96..f3dd1e5e9f96 100644 --- a/configs/imx8mn_bsh_smm_s2_defconfig +++ b/configs/imx8mn_bsh_smm_s2_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mn_bsh_smm_s2pro_defconfig b/configs/imx8mn_bsh_smm_s2pro_defconfig index 5763948feea3..07a0aba435f3 100644 --- a/configs/imx8mn_bsh_smm_s2pro_defconfig +++ b/configs/imx8mn_bsh_smm_s2pro_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mn_ddr4_evk_defconfig b/configs/imx8mn_ddr4_evk_defconfig index 169e85ac4873..ab015f97efc8 100644 --- a/configs/imx8mn_ddr4_evk_defconfig +++ b/configs/imx8mn_ddr4_evk_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mn_evk_defconfig b/configs/imx8mn_evk_defconfig index 4bf40eb97d76..297b77f5fe12 100644 --- a/configs/imx8mn_evk_defconfig +++ b/configs/imx8mn_evk_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mn_var_som_defconfig b/configs/imx8mn_var_som_defconfig index 8e4f6a419c9d..3449f2b66071 100644 --- a/configs/imx8mn_var_som_defconfig +++ b/configs/imx8mn_var_som_defconfig @@ -21,6 +21,7 @@ CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mn_venice_defconfig b/configs/imx8mn_venice_defconfig index b40d93c6bb32..eb196a3366e8 100644 --- a/configs/imx8mn_venice_defconfig +++ b/configs/imx8mn_venice_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig index 595d7893a4ab..1e1935a5f0c2 100644 --- a/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig +++ b/configs/imx8mp-icore-mx8mp-edimm2.2_defconfig @@ -22,6 +22,7 @@ CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mp_dhcom_pdk2_defconfig b/configs/imx8mp_dhcom_pdk2_defconfig index e78b9a1569e1..40b06e7d1678 100644 --- a/configs/imx8mp_dhcom_pdk2_defconfig +++ b/configs/imx8mp_dhcom_pdk2_defconfig @@ -30,6 +30,7 @@ CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mp_evk_defconfig b/configs/imx8mp_evk_defconfig index 0be1951e740f..a6c317483706 100644 --- a/configs/imx8mp_evk_defconfig +++ b/configs/imx8mp_evk_defconfig @@ -22,6 +22,7 @@ CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig index 378489072f3f..1f4ba696a516 100644 --- a/configs/imx8mp_rsb3720a1_4G_defconfig +++ b/configs/imx8mp_rsb3720a1_4G_defconfig @@ -24,6 +24,7 @@ CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_FIT_SIGNATURE=y diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig index 469ba34de0c5..93373db92800 100644 --- a/configs/imx8mp_rsb3720a1_6G_defconfig +++ b/configs/imx8mp_rsb3720a1_6G_defconfig @@ -24,6 +24,7 @@ CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_FIT_SIGNATURE=y diff --git a/configs/imx8mp_venice_defconfig b/configs/imx8mp_venice_defconfig index 84e708a704c4..94cd7ea7fa65 100644 --- a/configs/imx8mp_venice_defconfig +++ b/configs/imx8mp_venice_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mq_cm_defconfig b/configs/imx8mq_cm_defconfig index 74123b257ad0..16c0b6a47f28 100644 --- a/configs/imx8mq_cm_defconfig +++ b/configs/imx8mq_cm_defconfig @@ -22,6 +22,7 @@ CONFIG_IMX_BOOTAUX=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_SPL_FIT_PRINT=y CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mq_evk_defconfig b/configs/imx8mq_evk_defconfig index cf207295e547..fcdb5e24c2a3 100644 --- a/configs/imx8mq_evk_defconfig +++ b/configs/imx8mq_evk_defconfig @@ -23,6 +23,7 @@ CONFIG_IMX_BOOTAUX=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8mq_phanbell_defconfig b/configs/imx8mq_phanbell_defconfig index 372cd03ed0d9..7207ac88e4be 100644 --- a/configs/imx8mq_phanbell_defconfig +++ b/configs/imx8mq_phanbell_defconfig @@ -21,6 +21,7 @@ CONFIG_SPL=y CONFIG_IMX_BOOTAUX=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/imx8ulp_evk_defconfig b/configs/imx8ulp_evk_defconfig index f9198cf7247e..a6c75ccf0c27 100644 --- a/configs/imx8ulp_evk_defconfig +++ b/configs/imx8ulp_evk_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_LOAD_IMX_CONTAINER=y CONFIG_SYS_LOAD_ADDR=0x80480000 CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_BOOTDELAY=0 diff --git a/configs/imx93_11x11_evk_defconfig b/configs/imx93_11x11_evk_defconfig index 72ec466b7f23..d2ace6f34c29 100644 --- a/configs/imx93_11x11_evk_defconfig +++ b/configs/imx93_11x11_evk_defconfig @@ -23,6 +23,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_DEFAULT_FDT_FILE="imx93-11x11-evk.dtb" CONFIG_ARCH_MISC_INIT=y CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/inet1_defconfig b/configs/inet1_defconfig index f81120b11975..64f778734410 100644 --- a/configs/inet1_defconfig +++ b/configs/inet1_defconfig @@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/inet86dz_defconfig b/configs/inet86dz_defconfig index 3ade9fea8246..086098e5f4ca 100644 --- a/configs/inet86dz_defconfig +++ b/configs/inet86dz_defconfig @@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/inet97fv2_defconfig b/configs/inet97fv2_defconfig index d5d2dc32c935..0f70e95233e0 100644 --- a/configs/inet97fv2_defconfig +++ b/configs/inet97fv2_defconfig @@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/inet98v_rev2_defconfig b/configs/inet98v_rev2_defconfig index bd6c45bd661a..5c61766fe94d 100644 --- a/configs/inet98v_rev2_defconfig +++ b/configs/inet98v_rev2_defconfig @@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/inet9f_rev03_defconfig b/configs/inet9f_rev03_defconfig index 4485f9302364..d21d17fb984a 100644 --- a/configs/inet9f_rev03_defconfig +++ b/configs/inet9f_rev03_defconfig @@ -13,6 +13,7 @@ CONFIG_VIDEO_LCD_POWER="PH8" CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/inet_q972_defconfig b/configs/inet_q972_defconfig index 1769256b7d1e..a6148219253a 100644 --- a/configs/inet_q972_defconfig +++ b/configs/inet_q972_defconfig @@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_DCLK_PHASE=0 CONFIG_VIDEO_LCD_BL_EN="PA25" CONFIG_VIDEO_LCD_BL_PWM="PH13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/integratorcp_cm1136_defconfig b/configs/integratorcp_cm1136_defconfig index c9623cc6a181..ed64571b3fa6 100644 --- a/configs/integratorcp_cm1136_defconfig +++ b/configs/integratorcp_cm1136_defconfig @@ -12,6 +12,7 @@ CONFIG_SYS_LOAD_ADDR=0x7fc0 CONFIG_ENV_ADDR=0x24F00000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7ffff20 +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SYS_MONITOR_BASE=0x27F40000 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" diff --git a/configs/integratorcp_cm920t_defconfig b/configs/integratorcp_cm920t_defconfig index 64a4b81496c0..10d664ae7c77 100644 --- a/configs/integratorcp_cm920t_defconfig +++ b/configs/integratorcp_cm920t_defconfig @@ -12,6 +12,7 @@ CONFIG_SYS_LOAD_ADDR=0x7fc0 CONFIG_ENV_ADDR=0x24F00000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7ffff20 +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SYS_MONITOR_BASE=0x27F40000 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" diff --git a/configs/integratorcp_cm926ejs_defconfig b/configs/integratorcp_cm926ejs_defconfig index 4a72befd5ae2..1908d74160e4 100644 --- a/configs/integratorcp_cm926ejs_defconfig +++ b/configs/integratorcp_cm926ejs_defconfig @@ -12,6 +12,7 @@ CONFIG_SYS_LOAD_ADDR=0x7fc0 CONFIG_ENV_ADDR=0x24F00000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7ffff20 +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SYS_MONITOR_BASE=0x27F40000 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" diff --git a/configs/integratorcp_cm946es_defconfig b/configs/integratorcp_cm946es_defconfig index 9b3fda0b2492..16892809a56d 100644 --- a/configs/integratorcp_cm946es_defconfig +++ b/configs/integratorcp_cm946es_defconfig @@ -12,6 +12,7 @@ CONFIG_SYS_LOAD_ADDR=0x7fc0 CONFIG_ENV_ADDR=0x24F00000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x7ffff20 +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_SYS_MONITOR_BASE=0x27F40000 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock0 console=ttyAMA0 console=tty ip=dhcp netdev=27,0,0xfc800000,0xfc800010,eth0 video=clcdfb:0" diff --git a/configs/jesurun_q5_defconfig b/configs/jesurun_q5_defconfig index 0ff666b2ee5c..2e6b045b5494 100644 --- a/configs/jesurun_q5_defconfig +++ b/configs/jesurun_q5_defconfig @@ -8,6 +8,7 @@ CONFIG_MACPWR="PH19" CONFIG_USB0_VBUS_PIN="PB9" CONFIG_VIDEO_COMPOSITE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/kmcent2_defconfig b/configs/kmcent2_defconfig index 144edd4da508..63b8f71643f9 100644 --- a/configs/kmcent2_defconfig +++ b/configs/kmcent2_defconfig @@ -19,6 +19,7 @@ CONFIG_PCIE1=y CONFIG_SYS_FSL_NUM_CC_PLLS=2 CONFIG_KM_DEF_NETDEV="eth2" CONFIG_KM_IVM_BUS=2 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig index 686644393204..8526f3476526 100644 --- a/configs/kmcoge5ne_defconfig +++ b/configs/kmcoge5ne_defconfig @@ -160,6 +160,7 @@ CONFIG_LCRR_EADC_2=y CONFIG_LCRR_CLKDIV_4=y CONFIG_83XX_PCICLK=0x3ef1480 CONFIG_KM_DEF_NETDEV="eth1" +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig index 79567261f9b1..8602386e305a 100644 --- a/configs/kmeter1_defconfig +++ b/configs/kmeter1_defconfig @@ -130,6 +130,7 @@ CONFIG_LCRR_DBYP_PLL_BYPASSED=y CONFIG_LCRR_EADC_2=y CONFIG_LCRR_CLKDIV_4=y CONFIG_KM_DEF_NETDEV="eth2" +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig index af8ec9da9a9d..d7dab8b86e8c 100644 --- a/configs/kmopti2_defconfig +++ b/configs/kmopti2_defconfig @@ -143,6 +143,7 @@ CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_LCRR_EADC_1=y CONFIG_LCRR_CLKDIV_2=y CONFIG_83XX_PCICLK=0x3ef1480 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig index 945593df5391..86d4f47e3373 100644 --- a/configs/kmsupx5_defconfig +++ b/configs/kmsupx5_defconfig @@ -123,6 +123,7 @@ CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_LCRR_EADC_1=y CONFIG_LCRR_CLKDIV_2=y CONFIG_83XX_PCICLK=0x3ef1480 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig index be0f858dffd5..1001d18d98c9 100644 --- a/configs/kmtepr2_defconfig +++ b/configs/kmtepr2_defconfig @@ -143,6 +143,7 @@ CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_LCRR_EADC_1=y CONFIG_LCRR_CLKDIV_2=y CONFIG_83XX_PCICLK=0x3ef1480 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/koelsch_defconfig b/configs/koelsch_defconfig index ee4bb102a798..9aa683e60da7 100644 --- a/configs/koelsch_defconfig +++ b/configs/koelsch_defconfig @@ -28,6 +28,7 @@ CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_ENV_ADDR=0xC0000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_SPL_MAX_SIZE=0x4000 diff --git a/configs/kontron_pitx_imx8m_defconfig b/configs/kontron_pitx_imx8m_defconfig index 284aa6d6b8b7..2da3904a2a04 100644 --- a/configs/kontron_pitx_imx8m_defconfig +++ b/configs/kontron_pitx_imx8m_defconfig @@ -22,6 +22,7 @@ CONFIG_IMX_BOOTAUX=y CONFIG_SYS_LOAD_ADDR=0x42000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_SPL_FIT_PRINT=y CONFIG_SPL_LOAD_FIT=y diff --git a/configs/kontron_sl28_defconfig b/configs/kontron_sl28_defconfig index 9112956e0709..f044334e80e6 100644 --- a/configs/kontron_sl28_defconfig +++ b/configs/kontron_sl28_defconfig @@ -29,6 +29,7 @@ CONFIG_SYS_FSL_NUM_CC_PLLS=3 CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800eff0 +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y diff --git a/configs/kp_imx6q_tpc_defconfig b/configs/kp_imx6q_tpc_defconfig index 8c5010d60523..2ccd6e0946f8 100644 --- a/configs/kp_imx6q_tpc_defconfig +++ b/configs/kp_imx6q_tpc_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x102000 CONFIG_SPL_PAYLOAD="u-boot.img" CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/lager_defconfig b/configs/lager_defconfig index b8946437cf6d..f6e190319105 100644 --- a/configs/lager_defconfig +++ b/configs/lager_defconfig @@ -28,6 +28,7 @@ CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_ENV_ADDR=0xC0000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_SPL_MAX_SIZE=0x4000 diff --git a/configs/librem5_defconfig b/configs/librem5_defconfig index b022ae363789..c34d9b4fb870 100644 --- a/configs/librem5_defconfig +++ b/configs/librem5_defconfig @@ -23,6 +23,7 @@ CONFIG_IMX_BOOTAUX=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/libretech_all_h3_cc_h2_plus_defconfig b/configs/libretech_all_h3_cc_h2_plus_defconfig index 8725fe64cdcf..d19e3371410e 100644 --- a/configs/libretech_all_h3_cc_h2_plus_defconfig +++ b/configs/libretech_all_h3_cc_h2_plus_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/libretech_all_h3_cc_h3_defconfig b/configs/libretech_all_h3_cc_h3_defconfig index 5275fdc36da3..4f3ab902d1e9 100644 --- a/configs/libretech_all_h3_cc_h3_defconfig +++ b/configs/libretech_all_h3_cc_h3_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/libretech_all_h3_cc_h5_defconfig b/configs/libretech_all_h3_cc_h5_defconfig index 96274019499a..a912829be5c1 100644 --- a/configs/libretech_all_h3_cc_h5_defconfig +++ b/configs/libretech_all_h3_cc_h5_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN50I_H5=y CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/libretech_all_h3_it_h5_defconfig b/configs/libretech_all_h3_it_h5_defconfig index cb7ffb4d7daa..f1f177c6815f 100644 --- a/configs/libretech_all_h3_it_h5_defconfig +++ b/configs/libretech_all_h3_it_h5_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPI_FLASH_XMC=y CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/libretech_all_h5_cc_h5_defconfig b/configs/libretech_all_h5_cc_h5_defconfig index c3aa4b10617f..1dbcaa8c75f1 100644 --- a/configs/libretech_all_h5_cc_h5_defconfig +++ b/configs/libretech_all_h5_cc_h5_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=672 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPI_FLASH_XMC=y CONFIG_SUN8I_EMAC=y CONFIG_SPI=y diff --git a/configs/licheepi_nano_defconfig b/configs/licheepi_nano_defconfig index 12a43c1ec10a..e7663e1d1ba7 100644 --- a/configs/licheepi_nano_defconfig +++ b/configs/licheepi_nano_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=156 CONFIG_DRAM_ZQ=0 # CONFIG_VIDEO_SUNXI is not set CONFIG_SPL_SPI_SUNXI=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPI_FLASH_WINBOND=y CONFIG_SPI_FLASH_XTX=y CONFIG_SPI=y diff --git a/configs/liteboard_defconfig b/configs/liteboard_defconfig index c96ea617cf18..0875f85a0ea7 100644 --- a/configs/liteboard_defconfig +++ b/configs/liteboard_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOOTDELAY=1 CONFIG_USE_BOOTCOMMAND=y diff --git a/configs/ls1021aiot_sdcard_defconfig b/configs/ls1021aiot_sdcard_defconfig index 64ae1dfd1895..2aa25a58e82c 100644 --- a/configs/ls1021aiot_sdcard_defconfig +++ b/configs/ls1021aiot_sdcard_defconfig @@ -23,6 +23,7 @@ CONFIG_AHCI=y CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_PCIE1=y CONFIG_PCIE2=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_RAMBOOT_PBL=y diff --git a/configs/ls1021aqds_nand_defconfig b/configs/ls1021aqds_nand_defconfig index 3b7ad02e8b0b..106a0fed0491 100644 --- a/configs/ls1021aqds_nand_defconfig +++ b/configs/ls1021aqds_nand_defconfig @@ -29,6 +29,7 @@ CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls1021aqds_sdcard_ifc_defconfig b/configs/ls1021aqds_sdcard_ifc_defconfig index 54e82250b59d..784b892095b5 100644 --- a/configs/ls1021aqds_sdcard_ifc_defconfig +++ b/configs/ls1021aqds_sdcard_ifc_defconfig @@ -30,6 +30,7 @@ CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_DYNAMIC_SYS_CLK_FREQ=y diff --git a/configs/ls1021aqds_sdcard_qspi_defconfig b/configs/ls1021aqds_sdcard_qspi_defconfig index b528671b63ff..aa24308069fa 100644 --- a/configs/ls1021aqds_sdcard_qspi_defconfig +++ b/configs/ls1021aqds_sdcard_qspi_defconfig @@ -29,6 +29,7 @@ CONFIG_FSL_USE_PCA9547_MUX=y CONFIG_FSL_QIXIS=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_RAMBOOT_PBL=y diff --git a/configs/ls1021atsn_sdcard_defconfig b/configs/ls1021atsn_sdcard_defconfig index 63631f694342..10d341cd06db 100644 --- a/configs/ls1021atsn_sdcard_defconfig +++ b/configs/ls1021atsn_sdcard_defconfig @@ -23,6 +23,7 @@ CONFIG_LAYERSCAPE_NS_ACCESS=y CONFIG_PCIE1=y CONFIG_PCIE2=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig index 24d48b9ab6a8..2b131df615e6 100644 --- a/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_SECURE_BOOT_defconfig @@ -27,6 +27,7 @@ CONFIG_PCIE2=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=1064960 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls1021atwr_sdcard_ifc_defconfig b/configs/ls1021atwr_sdcard_ifc_defconfig index ffe377cda1ed..3e7ce1ff4a43 100644 --- a/configs/ls1021atwr_sdcard_ifc_defconfig +++ b/configs/ls1021atwr_sdcard_ifc_defconfig @@ -27,6 +27,7 @@ CONFIG_PCIE2=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls1021atwr_sdcard_qspi_defconfig b/configs/ls1021atwr_sdcard_qspi_defconfig index fb81e471df40..125791d9491d 100644 --- a/configs/ls1021atwr_sdcard_qspi_defconfig +++ b/configs/ls1021atwr_sdcard_qspi_defconfig @@ -27,6 +27,7 @@ CONFIG_PCIE2=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls1043aqds_nand_defconfig b/configs/ls1043aqds_nand_defconfig index d3808979019c..177d93477aea 100644 --- a/configs/ls1043aqds_nand_defconfig +++ b/configs/ls1043aqds_nand_defconfig @@ -37,6 +37,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls1043aqds_sdcard_ifc_defconfig b/configs/ls1043aqds_sdcard_ifc_defconfig index 565970dbb848..02ab31e61309 100644 --- a/configs/ls1043aqds_sdcard_ifc_defconfig +++ b/configs/ls1043aqds_sdcard_ifc_defconfig @@ -38,6 +38,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls1043aqds_sdcard_qspi_defconfig b/configs/ls1043aqds_sdcard_qspi_defconfig index ba1b7fe624dd..cfc78b171c71 100644 --- a/configs/ls1043aqds_sdcard_qspi_defconfig +++ b/configs/ls1043aqds_sdcard_qspi_defconfig @@ -37,6 +37,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig index 3a5b61b133a2..57eef4eedc69 100644 --- a/configs/ls1043ardb_nand_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_nand_SECURE_BOOT_defconfig @@ -24,6 +24,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1064960 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls1043ardb_nand_defconfig b/configs/ls1043ardb_nand_defconfig index 6100ba2c8b8c..c9a600bde6b2 100644 --- a/configs/ls1043ardb_nand_defconfig +++ b/configs/ls1043ardb_nand_defconfig @@ -28,6 +28,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig index 33678c122eb9..9891af437cc4 100644 --- a/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1043ardb_sdcard_SECURE_BOOT_defconfig @@ -25,6 +25,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1064960 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls1043ardb_sdcard_defconfig b/configs/ls1043ardb_sdcard_defconfig index ad221a33294d..9ab8d9cef061 100644 --- a/configs/ls1043ardb_sdcard_defconfig +++ b/configs/ls1043ardb_sdcard_defconfig @@ -29,6 +29,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls1046aqds_nand_defconfig b/configs/ls1046aqds_nand_defconfig index 753e7b545243..770b923d6edb 100644 --- a/configs/ls1046aqds_nand_defconfig +++ b/configs/ls1046aqds_nand_defconfig @@ -37,6 +37,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=655360 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls1046aqds_sdcard_ifc_defconfig b/configs/ls1046aqds_sdcard_ifc_defconfig index 7e12a9006a70..850e304ff1ac 100644 --- a/configs/ls1046aqds_sdcard_ifc_defconfig +++ b/configs/ls1046aqds_sdcard_ifc_defconfig @@ -38,6 +38,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls1046aqds_sdcard_qspi_defconfig b/configs/ls1046aqds_sdcard_qspi_defconfig index 47c0ae80631b..1cbb9613ff86 100644 --- a/configs/ls1046aqds_sdcard_qspi_defconfig +++ b/configs/ls1046aqds_sdcard_qspi_defconfig @@ -37,6 +37,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls1046ardb_emmc_defconfig b/configs/ls1046ardb_emmc_defconfig index 54c48f2ea641..1ccfbb1235c4 100644 --- a/configs/ls1046ardb_emmc_defconfig +++ b/configs/ls1046ardb_emmc_defconfig @@ -29,6 +29,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls1046ardb_qspi_spl_defconfig b/configs/ls1046ardb_qspi_spl_defconfig index ae110b6ac8e4..ad14f92c3007 100644 --- a/configs/ls1046ardb_qspi_spl_defconfig +++ b/configs/ls1046ardb_qspi_spl_defconfig @@ -31,6 +31,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_LOAD_FIT=y diff --git a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig index a4efdd5ce4f4..cc4882183116 100644 --- a/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig +++ b/configs/ls1046ardb_sdcard_SECURE_BOOT_defconfig @@ -28,6 +28,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1064960 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls1046ardb_sdcard_defconfig b/configs/ls1046ardb_sdcard_defconfig index dc388051c725..0822b34c9015 100644 --- a/configs/ls1046ardb_sdcard_defconfig +++ b/configs/ls1046ardb_sdcard_defconfig @@ -29,6 +29,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1000fff0 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls1088aqds_sdcard_ifc_defconfig b/configs/ls1088aqds_sdcard_ifc_defconfig index 6a1ceb3b73c8..829bab9ff866 100644 --- a/configs/ls1088aqds_sdcard_ifc_defconfig +++ b/configs/ls1088aqds_sdcard_ifc_defconfig @@ -31,6 +31,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_OF_BOARD_SETUP=y CONFIG_DYNAMIC_SYS_CLK_FREQ=y diff --git a/configs/ls1088aqds_sdcard_qspi_defconfig b/configs/ls1088aqds_sdcard_qspi_defconfig index b6cc4fd89921..725680681c56 100644 --- a/configs/ls1088aqds_sdcard_qspi_defconfig +++ b/configs/ls1088aqds_sdcard_qspi_defconfig @@ -32,6 +32,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig index e62892c4d5e2..88c5106d69ea 100644 --- a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -31,6 +31,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1064960 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls1088ardb_sdcard_qspi_defconfig b/configs/ls1088ardb_sdcard_qspi_defconfig index b978b6605199..552618c0dc72 100644 --- a/configs/ls1088ardb_sdcard_qspi_defconfig +++ b/configs/ls1088ardb_sdcard_qspi_defconfig @@ -32,6 +32,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls2080aqds_SECURE_BOOT_defconfig b/configs/ls2080aqds_SECURE_BOOT_defconfig index 6dcec8e8bf9e..8d9fba21b3ee 100644 --- a/configs/ls2080aqds_SECURE_BOOT_defconfig +++ b/configs/ls2080aqds_SECURE_BOOT_defconfig @@ -17,6 +17,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls2080aqds_defconfig b/configs/ls2080aqds_defconfig index 2aff79826825..d4981a7a00bc 100644 --- a/configs/ls2080aqds_defconfig +++ b/configs/ls2080aqds_defconfig @@ -18,6 +18,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls2080aqds_nand_defconfig b/configs/ls2080aqds_nand_defconfig index 6efe9426b354..22ea939f12ea 100644 --- a/configs/ls2080aqds_nand_defconfig +++ b/configs/ls2080aqds_nand_defconfig @@ -21,6 +21,7 @@ CONFIG_FSL_QIXIS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/ls2080aqds_qspi_defconfig b/configs/ls2080aqds_qspi_defconfig index 3667c213e96c..6c1194385609 100644 --- a/configs/ls2080aqds_qspi_defconfig +++ b/configs/ls2080aqds_qspi_defconfig @@ -16,6 +16,7 @@ CONFIG_FSL_QIXIS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/ls2080aqds_sdcard_defconfig b/configs/ls2080aqds_sdcard_defconfig index 360d13bc8261..53cb76e58aad 100644 --- a/configs/ls2080aqds_sdcard_defconfig +++ b/configs/ls2080aqds_sdcard_defconfig @@ -23,6 +23,7 @@ CONFIG_FSL_QIXIS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls2080ardb_SECURE_BOOT_defconfig b/configs/ls2080ardb_SECURE_BOOT_defconfig index e279a387ce1f..7d7beb6f1cb3 100644 --- a/configs/ls2080ardb_SECURE_BOOT_defconfig +++ b/configs/ls2080ardb_SECURE_BOOT_defconfig @@ -21,6 +21,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls2080ardb_defconfig b/configs/ls2080ardb_defconfig index e9818d62de35..b96bca88ee48 100644 --- a/configs/ls2080ardb_defconfig +++ b/configs/ls2080ardb_defconfig @@ -22,6 +22,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls2080ardb_nand_defconfig b/configs/ls2080ardb_nand_defconfig index b6ae3c8df314..bbd24cf74ccb 100644 --- a/configs/ls2080ardb_nand_defconfig +++ b/configs/ls2080ardb_nand_defconfig @@ -26,6 +26,7 @@ CONFIG_FSL_QIXIS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT=y CONFIG_FIT_VERBOSE=y diff --git a/configs/ls2081ardb_defconfig b/configs/ls2081ardb_defconfig index a3d29e86551a..db2ab2955ecb 100644 --- a/configs/ls2081ardb_defconfig +++ b/configs/ls2081ardb_defconfig @@ -22,6 +22,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls2088aqds_tfa_defconfig b/configs/ls2088aqds_tfa_defconfig index 639a16b5bbaa..8f531a43499f 100644 --- a/configs/ls2088aqds_tfa_defconfig +++ b/configs/ls2088aqds_tfa_defconfig @@ -20,6 +20,7 @@ CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig index d621eb6c9ee3..dd3737f6d9dd 100644 --- a/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_qspi_SECURE_BOOT_defconfig @@ -21,6 +21,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls2088ardb_qspi_defconfig b/configs/ls2088ardb_qspi_defconfig index 6d7378127219..5c9689a1c52b 100644 --- a/configs/ls2088ardb_qspi_defconfig +++ b/configs/ls2088ardb_qspi_defconfig @@ -23,6 +23,7 @@ CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x1800fff0 # CONFIG_SYS_MALLOC_F is not set CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig index bedf588e1f35..4907b20536e2 100644 --- a/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/ls2088ardb_tfa_SECURE_BOOT_defconfig @@ -23,6 +23,7 @@ CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/ls2088ardb_tfa_defconfig b/configs/ls2088ardb_tfa_defconfig index c0567964fb6d..cfb0dfef0b31 100644 --- a/configs/ls2088ardb_tfa_defconfig +++ b/configs/ls2088ardb_tfa_defconfig @@ -25,6 +25,7 @@ CONFIG_VOL_MONITOR_IR36021_SET=y CONFIG_FSL_QIXIS=y # CONFIG_QIXIS_I2C_ACCESS is not set CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig index 99c861ea8bdb..dbceac1d63fa 100644 --- a/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160aqds_tfa_SECURE_BOOT_defconfig @@ -24,6 +24,7 @@ CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=4 CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=958464 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig index 3610d259dbfe..4ed37c37210c 100644 --- a/configs/lx2160aqds_tfa_defconfig +++ b/configs/lx2160aqds_tfa_defconfig @@ -26,6 +26,7 @@ CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=4 CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=958464 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig index 13e46adecd06..2be379b77138 100644 --- a/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2160ardb_tfa_SECURE_BOOT_defconfig @@ -25,6 +25,7 @@ CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=4 CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=958464 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/lx2160ardb_tfa_defconfig b/configs/lx2160ardb_tfa_defconfig index 03c3a57bee94..0be64221836b 100644 --- a/configs/lx2160ardb_tfa_defconfig +++ b/configs/lx2160ardb_tfa_defconfig @@ -27,6 +27,7 @@ CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=4 CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=958464 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/lx2160ardb_tfa_stmm_defconfig b/configs/lx2160ardb_tfa_stmm_defconfig index 79b0e477a9ef..f25a98aca60a 100644 --- a/configs/lx2160ardb_tfa_stmm_defconfig +++ b/configs/lx2160ardb_tfa_stmm_defconfig @@ -27,6 +27,7 @@ CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=4 CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=958464 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig index 4509d448039e..925abe102467 100644 --- a/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig +++ b/configs/lx2162aqds_tfa_SECURE_BOOT_defconfig @@ -24,6 +24,7 @@ CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=4 CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=958464 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/lx2162aqds_tfa_defconfig b/configs/lx2162aqds_tfa_defconfig index 81511d31db66..c03e3002cd3a 100644 --- a/configs/lx2162aqds_tfa_defconfig +++ b/configs/lx2162aqds_tfa_defconfig @@ -26,6 +26,7 @@ CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=4 CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=958464 CONFIG_MP=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/lx2162aqds_tfa_verified_boot_defconfig b/configs/lx2162aqds_tfa_verified_boot_defconfig index 72611eb8eee7..fbf5b8c513e4 100644 --- a/configs/lx2162aqds_tfa_verified_boot_defconfig +++ b/configs/lx2162aqds_tfa_verified_boot_defconfig @@ -26,6 +26,7 @@ CONFIG_VOL_MONITOR_LTC3882_SET=y CONFIG_SYS_FSL_NUM_CC_PLLS=4 CONFIG_FSL_QIXIS=y CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=958464 CONFIG_MP=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y diff --git a/configs/mccmon6_sd_defconfig b/configs/mccmon6_sd_defconfig index 111c0f07c7c0..0a699fa26621 100644 --- a/configs/mccmon6_sd_defconfig +++ b/configs/mccmon6_sd_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL=y # CONFIG_CMD_BMODE is not set CONFIG_ENV_ADDR=0x8040000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT=y # CONFIG_USE_SPL_FIT_GENERATOR is not set diff --git a/configs/miqi-rk3288_defconfig b/configs/miqi-rk3288_defconfig index 75675e6095fd..7d74065d806e 100644 --- a/configs/miqi-rk3288_defconfig +++ b/configs/miqi-rk3288_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 +CONFIG_SYS_MONITOR_LEN=614400 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-miqi.dtb" diff --git a/configs/mixtile_loftq_defconfig b/configs/mixtile_loftq_defconfig index 0e4cdc446701..646594b6e07d 100644 --- a/configs/mixtile_loftq_defconfig +++ b/configs/mixtile_loftq_defconfig @@ -9,6 +9,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PH24" CONFIG_USB2_VBUS_PIN="" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_PHY_REALTEK=y CONFIG_ETH_DESIGNWARE=y CONFIG_RGMII=y diff --git a/configs/mk802_a10s_defconfig b/configs/mk802_a10s_defconfig index 21f7a6e535d2..ffcb93297421 100644 --- a/configs/mk802_a10s_defconfig +++ b/configs/mk802_a10s_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=432 CONFIG_DRAM_EMR1=0 CONFIG_USB1_VBUS_PIN="PB10" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/mk802_defconfig b/configs/mk802_defconfig index 416565e5af2b..1186a5361e98 100644 --- a/configs/mk802_defconfig +++ b/configs/mk802_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN4I=y CONFIG_USB2_VBUS_PIN="PH12" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f CONFIG_SYS_I2C_SPEED=400000 diff --git a/configs/mk802ii_defconfig b/configs/mk802ii_defconfig index 965a9cd5c4b0..9c31b33c43c7 100644 --- a/configs/mk802ii_defconfig +++ b/configs/mk802ii_defconfig @@ -4,6 +4,7 @@ CONFIG_DEFAULT_DEVICE_TREE="sun4i-a10-mk802ii" CONFIG_SPL=y CONFIG_MACH_SUN4I=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/mx6cuboxi_defconfig b/configs/mx6cuboxi_defconfig index 9de5e77c75ad..0269b059adbd 100644 --- a/configs/mx6cuboxi_defconfig +++ b/configs/mx6cuboxi_defconfig @@ -21,6 +21,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_CMD_HDMIDETECT=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_OF_BOARD_SETUP=y CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" diff --git a/configs/mx6sabreauto_defconfig b/configs/mx6sabreauto_defconfig index 093bb85c201f..74fca470920e 100644 --- a/configs/mx6sabreauto_defconfig +++ b/configs/mx6sabreauto_defconfig @@ -22,6 +22,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_NXP_BOARD_REVISION=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_SPL_FIT_PRINT=y CONFIG_SPL_LOAD_FIT=y diff --git a/configs/mx6sabresd_defconfig b/configs/mx6sabresd_defconfig index 5db818214241..655eb8bad11b 100644 --- a/configs/mx6sabresd_defconfig +++ b/configs/mx6sabresd_defconfig @@ -21,6 +21,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_SPL_FIT_PRINT=y CONFIG_SPL_LOAD_FIT=y diff --git a/configs/mx6slevk_spl_defconfig b/configs/mx6slevk_spl_defconfig index b6b15c064e14..cd13e3883f97 100644 --- a/configs/mx6slevk_spl_defconfig +++ b/configs/mx6slevk_spl_defconfig @@ -21,6 +21,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_CMD_BMODE is not set +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" diff --git a/configs/mx6ul_14x14_evk_defconfig b/configs/mx6ul_14x14_evk_defconfig index b87973fa0b9a..c53e5754acb8 100644 --- a/configs/mx6ul_14x14_evk_defconfig +++ b/configs/mx6ul_14x14_evk_defconfig @@ -21,6 +21,7 @@ CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" diff --git a/configs/mx6ul_9x9_evk_defconfig b/configs/mx6ul_9x9_evk_defconfig index 8062095dd478..bdd026e10ac8 100644 --- a/configs/mx6ul_9x9_evk_defconfig +++ b/configs/mx6ul_9x9_evk_defconfig @@ -21,6 +21,7 @@ CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTCOMMAND=y CONFIG_BOOTCOMMAND="run findfdt;mmc dev ${mmcdev};mmc dev ${mmcdev}; if mmc rescan; then if run loadbootscript; then run bootscript; else if run loadimage; then run mmcboot; else run netboot; fi; fi; else run netboot; fi" diff --git a/configs/myir_mys_6ulx_defconfig b/configs/myir_mys_6ulx_defconfig index f748b4dd66ba..6dddedd7e508 100644 --- a/configs/myir_mys_6ulx_defconfig +++ b/configs/myir_mys_6ulx_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/nanopi_a64_defconfig b/configs/nanopi_a64_defconfig index 70fc257eebd9..ed11e0a6308a 100644 --- a/configs/nanopi_a64_defconfig +++ b/configs/nanopi_a64_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_m1_defconfig b/configs/nanopi_m1_defconfig index dc2dbd629003..9419eaf5511d 100644 --- a/configs/nanopi_m1_defconfig +++ b/configs/nanopi_m1_defconfig @@ -5,5 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_m1_plus_defconfig b/configs/nanopi_m1_plus_defconfig index 37b7817d869c..89065f0411ac 100644 --- a/configs/nanopi_m1_plus_defconfig +++ b/configs/nanopi_m1_plus_defconfig @@ -8,6 +8,7 @@ CONFIG_MACPWR="PD6" CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_neo2_defconfig b/configs/nanopi_neo2_defconfig index 95dd56aa04c7..d76d37f271ea 100644 --- a/configs/nanopi_neo2_defconfig +++ b/configs/nanopi_neo2_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_neo_air_defconfig b/configs/nanopi_neo_air_defconfig index 806d95c1cc75..09a6bfa2e06b 100644 --- a/configs/nanopi_neo_air_defconfig +++ b/configs/nanopi_neo_air_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_CONSOLE_MUX=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_neo_defconfig b/configs/nanopi_neo_defconfig index c0255196384f..6110cfd49532 100644 --- a/configs/nanopi_neo_defconfig +++ b/configs/nanopi_neo_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=408 # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_CONSOLE_MUX=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/nanopi_neo_plus2_defconfig b/configs/nanopi_neo_plus2_defconfig index 924ff38f17ca..d462b63e9443 100644 --- a/configs/nanopi_neo_plus2_defconfig +++ b/configs/nanopi_neo_plus2_defconfig @@ -9,6 +9,7 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/nanopi_r1s_h5_defconfig b/configs/nanopi_r1s_h5_defconfig index 27cf172d72af..5c332ca5261f 100644 --- a/configs/nanopi_r1s_h5_defconfig +++ b/configs/nanopi_r1s_h5_defconfig @@ -9,6 +9,7 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/novena_defconfig b/configs/novena_defconfig index 7e336147f8eb..6eabb7de90f8 100644 --- a/configs/novena_defconfig +++ b/configs/novena_defconfig @@ -25,6 +25,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_CMD_HDMIDETECT=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttymxc1,115200 " diff --git a/configs/oceanic_5205_5inmfd_defconfig b/configs/oceanic_5205_5inmfd_defconfig index 7ce63ba665d6..ca3139431fee 100644 --- a/configs/oceanic_5205_5inmfd_defconfig +++ b/configs/oceanic_5205_5inmfd_defconfig @@ -10,6 +10,7 @@ CONFIG_DRAM_ZQ=3881949 CONFIG_MMC0_CD_PIN="" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_SPI=y CONFIG_USB_EHCI_HCD=y diff --git a/configs/odroid_defconfig b/configs/odroid_defconfig index bd4877198154..c82448d6d410 100644 --- a/configs/odroid_defconfig +++ b/configs/odroid_defconfig @@ -20,6 +20,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43dfff10 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_USE_BOOTARGS=y diff --git a/configs/omap35_logic_defconfig b/configs/omap35_logic_defconfig index 945d7b6e7d85..14397c1e31dd 100644 --- a/configs/omap35_logic_defconfig +++ b/configs/omap35_logic_defconfig @@ -17,6 +17,7 @@ CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_BOOTCOMMAND="run autoboot" CONFIG_USE_PREBOOT=y diff --git a/configs/omap35_logic_somlv_defconfig b/configs/omap35_logic_somlv_defconfig index e7d1c4ee37fd..20062d118923 100644 --- a/configs/omap35_logic_somlv_defconfig +++ b/configs/omap35_logic_somlv_defconfig @@ -17,6 +17,7 @@ CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_SYS_MONITOR_BASE=0x10000000 CONFIG_BOOTCOMMAND="run autoboot" diff --git a/configs/omap3_beagle_defconfig b/configs/omap3_beagle_defconfig index 9ead47f09bbb..125372dc552b 100644 --- a/configs/omap3_beagle_defconfig +++ b/configs/omap3_beagle_defconfig @@ -13,6 +13,7 @@ CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="omap3-beagle.dtb" diff --git a/configs/omap3_evm_defconfig b/configs/omap3_evm_defconfig index e67b71741843..51706b8e5089 100644 --- a/configs/omap3_evm_defconfig +++ b/configs/omap3_evm_defconfig @@ -13,6 +13,7 @@ CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_BOOTCOMMAND="if test ${boot_fit} -eq 1; then setenv boot mmc; setenv addr_fit 0x8b000000; run update_to_fit; run mmcboot; fi; run envboot; run distro_bootcmd" CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="omap3-evm.dtb" diff --git a/configs/omap3_logic_defconfig b/configs/omap3_logic_defconfig index bca52bb27cbd..dd601ba030a2 100644 --- a/configs/omap3_logic_defconfig +++ b/configs/omap3_logic_defconfig @@ -17,6 +17,7 @@ CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_BOOTCOMMAND="run autoboot" CONFIG_USE_PREBOOT=y diff --git a/configs/omap3_logic_somlv_defconfig b/configs/omap3_logic_somlv_defconfig index 6b5ddb9d6f0e..3770d0d4f6f4 100644 --- a/configs/omap3_logic_somlv_defconfig +++ b/configs/omap3_logic_somlv_defconfig @@ -17,6 +17,7 @@ CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4020ff00 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_ANDROID_BOOT_IMAGE=y CONFIG_SYS_MONITOR_BASE=0x10000000 CONFIG_BOOTCOMMAND="run autoboot" diff --git a/configs/opos6uldev_defconfig b/configs/opos6uldev_defconfig index e508b63b7693..0d028e861d8c 100644 --- a/configs/opos6uldev_defconfig +++ b/configs/opos6uldev_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x180000 CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_CMD_BMODE is not set +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOOTDELAY=5 CONFIG_USE_BOOTARGS=y diff --git a/configs/orangepi_2_defconfig b/configs/orangepi_2_defconfig index 7aaa5190b3a3..000ab3e672ce 100644 --- a/configs/orangepi_2_defconfig +++ b/configs/orangepi_2_defconfig @@ -7,6 +7,7 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/orangepi_3_defconfig b/configs/orangepi_3_defconfig index ebecf49ebdaa..3debe90cb665 100644 --- a/configs/orangepi_3_defconfig +++ b/configs/orangepi_3_defconfig @@ -8,6 +8,7 @@ CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_BLUETOOTH_DT_DEVICE_FIXUP="brcm,bcm4345c5" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_PHY_SUN50I_USB3=y CONFIG_USB_XHCI_HCD=y CONFIG_USB_XHCI_DWC3=y diff --git a/configs/orangepi_lite2_defconfig b/configs/orangepi_lite2_defconfig index 75c97d6b897c..37d3cf7d7dc8 100644 --- a/configs/orangepi_lite2_defconfig +++ b/configs/orangepi_lite2_defconfig @@ -7,5 +7,6 @@ CONFIG_SUNXI_DRAM_H6_LPDDR3=y CONFIG_MMC0_CD_PIN="PF6" # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_lite_defconfig b/configs/orangepi_lite_defconfig index 96bbd1bab6fe..25f5a4fe6f08 100644 --- a/configs/orangepi_lite_defconfig +++ b/configs/orangepi_lite_defconfig @@ -5,5 +5,6 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_one_defconfig b/configs/orangepi_one_defconfig index 1064b4a39de6..094f8d1dfa26 100644 --- a/configs/orangepi_one_defconfig +++ b/configs/orangepi_one_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=672 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_one_plus_defconfig b/configs/orangepi_one_plus_defconfig index 55a8b003fb5b..9a2abfa10287 100644 --- a/configs/orangepi_one_plus_defconfig +++ b/configs/orangepi_one_plus_defconfig @@ -7,5 +7,6 @@ CONFIG_SUNXI_DRAM_H6_LPDDR3=y CONFIG_MMC0_CD_PIN="PF6" # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_pc2_defconfig b/configs/orangepi_pc2_defconfig index 777af8c60ea7..356ae7ce4762 100644 --- a/configs/orangepi_pc2_defconfig +++ b/configs/orangepi_pc2_defconfig @@ -8,6 +8,7 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MACPWR="PD6" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/orangepi_pc_defconfig b/configs/orangepi_pc_defconfig index 905ff7b1271d..4d3fa7799c00 100644 --- a/configs/orangepi_pc_defconfig +++ b/configs/orangepi_pc_defconfig @@ -5,6 +5,7 @@ CONFIG_SPL=y CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=624 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/orangepi_pc_plus_defconfig b/configs/orangepi_pc_plus_defconfig index f845138153db..dcdec8d08835 100644 --- a/configs/orangepi_pc_plus_defconfig +++ b/configs/orangepi_pc_plus_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN8I_H3=y CONFIG_DRAM_CLK=624 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/orangepi_plus2e_defconfig b/configs/orangepi_plus2e_defconfig index 138a6a72b8ce..e27b329b0a9c 100644 --- a/configs/orangepi_plus2e_defconfig +++ b/configs/orangepi_plus2e_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=672 CONFIG_MACPWR="PD6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/orangepi_plus_defconfig b/configs/orangepi_plus_defconfig index 76de72aa2287..5c7f0731d90b 100644 --- a/configs/orangepi_plus_defconfig +++ b/configs/orangepi_plus_defconfig @@ -9,6 +9,7 @@ CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PG13" CONFIG_SATAPWR="PG11" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/orangepi_prime_defconfig b/configs/orangepi_prime_defconfig index 95a82e20f3ec..80de7da021fb 100644 --- a/configs/orangepi_prime_defconfig +++ b/configs/orangepi_prime_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=672 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_r1_defconfig b/configs/orangepi_r1_defconfig index 4496aa4a45c7..d645168d7c49 100644 --- a/configs/orangepi_r1_defconfig +++ b/configs/orangepi_r1_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=624 # CONFIG_VIDEO_DE2 is not set CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_CONSOLE_MUX=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y diff --git a/configs/orangepi_win_defconfig b/configs/orangepi_win_defconfig index 3b78ad7e52d4..1e26970230f7 100644 --- a/configs/orangepi_win_defconfig +++ b/configs/orangepi_win_defconfig @@ -7,6 +7,7 @@ CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_MACPWR="PD14" CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPI_FLASH_WINBOND=y CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y diff --git a/configs/orangepi_zero2_defconfig b/configs/orangepi_zero2_defconfig index ceef51b3db65..877eccf31bd6 100644 --- a/configs/orangepi_zero2_defconfig +++ b/configs/orangepi_zero2_defconfig @@ -11,6 +11,7 @@ CONFIG_MMC0_CD_PIN="PF6" CONFIG_R_I2C_ENABLE=y CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/orangepi_zero_defconfig b/configs/orangepi_zero_defconfig index f7f3bfbcc410..5700c1bd0065 100644 --- a/configs/orangepi_zero_defconfig +++ b/configs/orangepi_zero_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=624 # CONFIG_VIDEO_DE2 is not set CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_CONSOLE_MUX=y CONFIG_SPI_FLASH_MACRONIX=y CONFIG_SPI_FLASH_WINBOND=y diff --git a/configs/orangepi_zero_plus2_defconfig b/configs/orangepi_zero_plus2_defconfig index 9583d24c8d62..6a02624cd05b 100644 --- a/configs/orangepi_zero_plus2_defconfig +++ b/configs/orangepi_zero_plus2_defconfig @@ -9,6 +9,7 @@ CONFIG_DRAM_ZQ=3881977 CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_zero_plus2_h3_defconfig b/configs/orangepi_zero_plus2_h3_defconfig index 55a251374a1e..d003612d50dc 100644 --- a/configs/orangepi_zero_plus2_h3_defconfig +++ b/configs/orangepi_zero_plus2_h3_defconfig @@ -8,6 +8,7 @@ CONFIG_DRAM_CLK=672 CONFIG_MMC0_CD_PIN="PH13" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/orangepi_zero_plus_defconfig b/configs/orangepi_zero_plus_defconfig index f3ecf35eee1d..16280994489d 100644 --- a/configs/orangepi_zero_plus_defconfig +++ b/configs/orangepi_zero_plus_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=624 CONFIG_DRAM_ZQ=3881977 # CONFIG_DRAM_ODT_EN is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/origen_defconfig b/configs/origen_defconfig index 79e3af950eca..ae33e76b25a1 100644 --- a/configs/origen_defconfig +++ b/configs/origen_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_LOAD_ADDR=0x43e00000 CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2040000 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_BOOTCOMMAND="if mmc rescan; then echo SD/MMC found on device ${mmcdev};if run loadbootenv; then echo Loaded environment from ${bootenv};run importbootenv;fi;if test -n $uenvcmd; then echo Running uenvcmd ...;run uenvcmd;fi;if run loadbootscript; then run bootscript; fi; fi;load mmc ${mmcdev} ${loadaddr} uImage; bootm ${loadaddr} " CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_INFO_QUIET=y diff --git a/configs/parrot_r16_defconfig b/configs/parrot_r16_defconfig index d56c4504b6a8..b5c60da9f10f 100644 --- a/configs/parrot_r16_defconfig +++ b/configs/parrot_r16_defconfig @@ -11,6 +11,7 @@ CONFIG_USB0_ID_DET="PD10" CONFIG_USB1_VBUS_PIN="PD12" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_CONS_INDEX=5 CONFIG_USB_EHCI_HCD=y diff --git a/configs/pcm058_defconfig b/configs/pcm058_defconfig index 8d9ee88b4771..0f5cbdbe1f95 100644 --- a/configs/pcm058_defconfig +++ b/configs/pcm058_defconfig @@ -25,6 +25,7 @@ CONFIG_SPL_SPI_FLASH_SUPPORT=y CONFIG_SPL_SPI=y CONFIG_CMD_HDMIDETECT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run mmcboot;run nandboot" diff --git a/configs/pg_wcom_expu1_defconfig b/configs/pg_wcom_expu1_defconfig index d972c29c03ca..3da3885a0e98 100644 --- a/configs/pg_wcom_expu1_defconfig +++ b/configs/pg_wcom_expu1_defconfig @@ -29,6 +29,7 @@ CONFIG_PG_WCOM_UBOOT_UPDATE_TEXT_BASE=0x60240000 CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/pg_wcom_expu1_update_defconfig b/configs/pg_wcom_expu1_update_defconfig index 66e21ddf2330..39db7ed1d3f4 100644 --- a/configs/pg_wcom_expu1_update_defconfig +++ b/configs/pg_wcom_expu1_update_defconfig @@ -27,6 +27,7 @@ CONFIG_PG_WCOM_UBOOT_UPDATE=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/pg_wcom_seli8_defconfig b/configs/pg_wcom_seli8_defconfig index fecb62e679bd..11f62d735e3b 100644 --- a/configs/pg_wcom_seli8_defconfig +++ b/configs/pg_wcom_seli8_defconfig @@ -29,6 +29,7 @@ CONFIG_PG_WCOM_UBOOT_UPDATE_TEXT_BASE=0x60240000 CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/pg_wcom_seli8_update_defconfig b/configs/pg_wcom_seli8_update_defconfig index 828a961b4625..0875f02fa777 100644 --- a/configs/pg_wcom_seli8_update_defconfig +++ b/configs/pg_wcom_seli8_update_defconfig @@ -27,6 +27,7 @@ CONFIG_PG_WCOM_UBOOT_UPDATE=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x9fffffff CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/phycore-imx8mm_defconfig b/configs/phycore-imx8mm_defconfig index e8d7905bb4ac..f03d73d6d47b 100644 --- a/configs/phycore-imx8mm_defconfig +++ b/configs/phycore-imx8mm_defconfig @@ -18,6 +18,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x3E0000 CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/phycore-imx8mp_defconfig b/configs/phycore-imx8mp_defconfig index ac8c4e6836e8..734c05a49c3f 100644 --- a/configs/phycore-imx8mp_defconfig +++ b/configs/phycore-imx8mp_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL_DRIVERS_MISC=y CONFIG_SPL=y CONFIG_SPL_IMX_ROMAPI_LOADADDR=0x48000000 CONFIG_SYS_LOAD_ADDR=0x40480000 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/phycore-rk3288_defconfig b/configs/phycore-rk3288_defconfig index cfe02dfe216c..bd41935d8e9d 100644 --- a/configs/phycore-rk3288_defconfig +++ b/configs/phycore-rk3288_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 +CONFIG_SYS_MONITOR_LEN=614400 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-phycore-rdk.dtb" diff --git a/configs/phycore_pcl063_defconfig b/configs/phycore_pcl063_defconfig index b9d2a976636c..2e74025338ed 100644 --- a/configs/phycore_pcl063_defconfig +++ b/configs/phycore_pcl063_defconfig @@ -16,6 +16,7 @@ CONFIG_SPL=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_SPL_MALLOC=y diff --git a/configs/phycore_pcl063_ull_defconfig b/configs/phycore_pcl063_ull_defconfig index f172b065bfcf..819bfce470eb 100644 --- a/configs/phycore_pcl063_ull_defconfig +++ b/configs/phycore_pcl063_ull_defconfig @@ -14,6 +14,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run mmc_mmc_fit" diff --git a/configs/pic32mzdask_defconfig b/configs/pic32mzdask_defconfig index 19303f8c9d1c..b6e10947c4d9 100644 --- a/configs/pic32mzdask_defconfig +++ b/configs/pic32mzdask_defconfig @@ -15,6 +15,7 @@ CONFIG_SYS_MEMTEST_END=0x88080000 CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007ffff +CONFIG_SYS_MONITOR_LEN=196608 CONFIG_TIMESTAMP=y CONFIG_BOOTDELAY=5 CONFIG_BOOTCOMMAND="run distro_bootcmd || run legacy_bootcmd" diff --git a/configs/pico-dwarf-imx6ul_defconfig b/configs/pico-dwarf-imx6ul_defconfig index d6ca9e658ef2..c3530d24107b 100644 --- a/configs/pico-dwarf-imx6ul_defconfig +++ b/configs/pico-dwarf-imx6ul_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=715776 +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-dwarf.dtb" diff --git a/configs/pico-dwarf-imx7d_defconfig b/configs/pico-dwarf-imx7d_defconfig index 57a54fd35382..aaa3edd2a66f 100644 --- a/configs/pico-dwarf-imx7d_defconfig +++ b/configs/pico-dwarf-imx7d_defconfig @@ -23,6 +23,7 @@ CONFIG_IMX_BOOTAUX=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=715776 +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb" CONFIG_SPL_MAX_SIZE=0xe000 diff --git a/configs/pico-hobbit-imx6ul_defconfig b/configs/pico-hobbit-imx6ul_defconfig index 6dc375402934..b8fbeeb7cfed 100644 --- a/configs/pico-hobbit-imx6ul_defconfig +++ b/configs/pico-hobbit-imx6ul_defconfig @@ -22,6 +22,7 @@ CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=715776 +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-hobbit.dtb" diff --git a/configs/pico-hobbit-imx7d_defconfig b/configs/pico-hobbit-imx7d_defconfig index 61ceb890201d..864ebc9466ba 100644 --- a/configs/pico-hobbit-imx7d_defconfig +++ b/configs/pico-hobbit-imx7d_defconfig @@ -23,6 +23,7 @@ CONFIG_IMX_BOOTAUX=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=715776 +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx7d-pico-hobbit.dtb" CONFIG_SPL_MAX_SIZE=0xe000 diff --git a/configs/pico-imx6_defconfig b/configs/pico-imx6_defconfig index ef724618ed9e..bc479f5bf918 100644 --- a/configs/pico-imx6_defconfig +++ b/configs/pico-imx6_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=715776 +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_SPL_FIT_PRINT=y CONFIG_SPL_LOAD_FIT=y diff --git a/configs/pico-imx6ul_defconfig b/configs/pico-imx6ul_defconfig index 7384b9b6eac2..a1da0c766a3c 100644 --- a/configs/pico-imx6ul_defconfig +++ b/configs/pico-imx6ul_defconfig @@ -22,6 +22,7 @@ CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=715776 +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="ask" diff --git a/configs/pico-imx7d_bl33_defconfig b/configs/pico-imx7d_bl33_defconfig index 49a8051d46a5..c5a984396583 100644 --- a/configs/pico-imx7d_bl33_defconfig +++ b/configs/pico-imx7d_bl33_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0xa0000000 CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=715776 +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_FIT_VERBOSE=y diff --git a/configs/pico-imx7d_defconfig b/configs/pico-imx7d_defconfig index 62658bfa4f21..56949d39cf91 100644 --- a/configs/pico-imx7d_defconfig +++ b/configs/pico-imx7d_defconfig @@ -23,6 +23,7 @@ CONFIG_IMX_BOOTAUX=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=715776 +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="ask" CONFIG_SPL_MAX_SIZE=0xe000 diff --git a/configs/pico-imx8mq_defconfig b/configs/pico-imx8mq_defconfig index 39136e1c8b9f..fedf43219f8a 100644 --- a/configs/pico-imx8mq_defconfig +++ b/configs/pico-imx8mq_defconfig @@ -21,6 +21,7 @@ CONFIG_SPL=y CONFIG_IMX_BOOTAUX=y CONFIG_SYS_LOAD_ADDR=0x40480000 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_SPL_LOAD_FIT=y diff --git a/configs/pico-nymph-imx7d_defconfig b/configs/pico-nymph-imx7d_defconfig index 57a54fd35382..aaa3edd2a66f 100644 --- a/configs/pico-nymph-imx7d_defconfig +++ b/configs/pico-nymph-imx7d_defconfig @@ -23,6 +23,7 @@ CONFIG_IMX_BOOTAUX=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=715776 +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx7d-pico-dwarf.dtb" CONFIG_SPL_MAX_SIZE=0xe000 diff --git a/configs/pico-pi-imx6ul_defconfig b/configs/pico-pi-imx6ul_defconfig index faf3c8421349..06c3866a0d86 100644 --- a/configs/pico-pi-imx6ul_defconfig +++ b/configs/pico-pi-imx6ul_defconfig @@ -22,6 +22,7 @@ CONFIG_SYS_MEMTEST_END=0x88000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=715776 +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx6ul-pico-pi.dtb" diff --git a/configs/pico-pi-imx7d_defconfig b/configs/pico-pi-imx7d_defconfig index 4853ab3527b9..7ba4baac474d 100644 --- a/configs/pico-pi-imx7d_defconfig +++ b/configs/pico-pi-imx7d_defconfig @@ -23,6 +23,7 @@ CONFIG_IMX_BOOTAUX=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_BOARD_SIZE_LIMIT=y CONFIG_BOARD_SIZE_LIMIT=715776 +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_BOOTCOMMAND="run findfdt; run finduuid; run distro_bootcmd" CONFIG_DEFAULT_FDT_FILE="imx7d-pico-pi.dtb" CONFIG_SPL_MAX_SIZE=0xe000 diff --git a/configs/pine64-lts_defconfig b/configs/pine64-lts_defconfig index 7e7c2d79104a..d8f718809b05 100644 --- a/configs/pine64-lts_defconfig +++ b/configs/pine64-lts_defconfig @@ -10,6 +10,7 @@ CONFIG_MMC0_CD_PIN="" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y diff --git a/configs/pine64_plus_defconfig b/configs/pine64_plus_defconfig index f42f4e5923ab..0fd24b5c5b38 100644 --- a/configs/pine64_plus_defconfig +++ b/configs/pine64_plus_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN50I=y CONFIG_RESERVE_ALLWINNER_BOOT0_HEADER=y CONFIG_PINE64_DT_SELECTION=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_OF_LIST="sun50i-a64-pine64 sun50i-a64-pine64-plus" CONFIG_PHY_REALTEK=y CONFIG_SUN8I_EMAC=y diff --git a/configs/pine_h64_defconfig b/configs/pine_h64_defconfig index 09a4275f0e79..578bd92f6a35 100644 --- a/configs/pine_h64_defconfig +++ b/configs/pine_h64_defconfig @@ -11,6 +11,7 @@ CONFIG_USB3_VBUS_PIN="PL5" CONFIG_SPL_SPI_SUNXI=y # CONFIG_PSCI_RESET is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y diff --git a/configs/pinebook_defconfig b/configs/pinebook_defconfig index 26918dd38753..75999b2fdccf 100644 --- a/configs/pinebook_defconfig +++ b/configs/pinebook_defconfig @@ -8,6 +8,7 @@ CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_R_I2C_ENABLE=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_DM_REGULATOR_FIXED=y diff --git a/configs/pinecube_defconfig b/configs/pinecube_defconfig index 28e347b4d952..3386eda88624 100644 --- a/configs/pinecube_defconfig +++ b/configs/pinecube_defconfig @@ -8,6 +8,7 @@ CONFIG_DRAM_CLK=504 CONFIG_DRAM_ODT_EN=y CONFIG_I2C0_ENABLE=y # CONFIG_HAS_ARMV7_SECURE_BASE is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/pinephone_defconfig b/configs/pinephone_defconfig index 9d39204a439a..373c8c8d14c0 100644 --- a/configs/pinephone_defconfig +++ b/configs/pinephone_defconfig @@ -10,6 +10,7 @@ CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_PINEPHONE_DT_SELECTION=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_OF_LIST="sun50i-a64-pinephone-1.1 sun50i-a64-pinephone-1.2" CONFIG_LED_STATUS=y CONFIG_LED_STATUS_GPIO=y diff --git a/configs/pinetab_defconfig b/configs/pinetab_defconfig index 0cc24146b394..f57901082415 100644 --- a/configs/pinetab_defconfig +++ b/configs/pinetab_defconfig @@ -8,3 +8,4 @@ CONFIG_DRAM_CLK=552 CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 diff --git a/configs/pm9g45_defconfig b/configs/pm9g45_defconfig index 436bfc6109f8..b66083ddc818 100644 --- a/configs/pm9g45_defconfig +++ b/configs/pm9g45_defconfig @@ -16,6 +16,7 @@ CONFIG_SYS_LOAD_ADDR=0x22000000 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x70003f00 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y diff --git a/configs/polaroid_mid2407pxe03_defconfig b/configs/polaroid_mid2407pxe03_defconfig index 17fffeb1e26a..9b7ee4c9c6fe 100644 --- a/configs/polaroid_mid2407pxe03_defconfig +++ b/configs/polaroid_mid2407pxe03_defconfig @@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/polaroid_mid2809pxe04_defconfig b/configs/polaroid_mid2809pxe04_defconfig index e542b7111325..e4b2797304e8 100644 --- a/configs/polaroid_mid2809pxe04_defconfig +++ b/configs/polaroid_mid2809pxe04_defconfig @@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/popmetal-rk3288_defconfig b/configs/popmetal-rk3288_defconfig index c010a8d7fa3b..05e97f2ea66d 100644 --- a/configs/popmetal-rk3288_defconfig +++ b/configs/popmetal-rk3288_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 +CONFIG_SYS_MONITOR_LEN=614400 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-popmetal.dtb" diff --git a/configs/porter_defconfig b/configs/porter_defconfig index 302291285f9a..531fe65bbb89 100644 --- a/configs/porter_defconfig +++ b/configs/porter_defconfig @@ -28,6 +28,7 @@ CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_ENV_ADDR=0xC0000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_SPL_MAX_SIZE=0x4000 diff --git a/configs/pov_protab2_ips9_defconfig b/configs/pov_protab2_ips9_defconfig index a62c9f8fa37f..e2ebf2ba0b12 100644 --- a/configs/pov_protab2_ips9_defconfig +++ b/configs/pov_protab2_ips9_defconfig @@ -14,6 +14,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/q8_a13_tablet_defconfig b/configs/q8_a13_tablet_defconfig index f269b8a58895..2505822b6684 100644 --- a/configs/q8_a13_tablet_defconfig +++ b/configs/q8_a13_tablet_defconfig @@ -15,6 +15,7 @@ CONFIG_VIDEO_LCD_POWER="AXP0-0" CONFIG_VIDEO_LCD_BL_EN="AXP0-1" CONFIG_VIDEO_LCD_BL_PWM="PB2" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/q8_a23_tablet_800x480_defconfig b/configs/q8_a23_tablet_800x480_defconfig index dda1a0c51f6e..dfa220b7c7c8 100644 --- a/configs/q8_a23_tablet_800x480_defconfig +++ b/configs/q8_a23_tablet_800x480_defconfig @@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/q8_a33_tablet_1024x600_defconfig b/configs/q8_a33_tablet_1024x600_defconfig index 7925677d30e2..79a0fc52e1a4 100644 --- a/configs/q8_a33_tablet_1024x600_defconfig +++ b/configs/q8_a33_tablet_1024x600_defconfig @@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/q8_a33_tablet_800x480_defconfig b/configs/q8_a33_tablet_800x480_defconfig index f3335f9d233e..b2d37122fc51 100644 --- a/configs/q8_a33_tablet_800x480_defconfig +++ b/configs/q8_a33_tablet_800x480_defconfig @@ -16,6 +16,7 @@ CONFIG_VIDEO_LCD_POWER="PH7" CONFIG_VIDEO_LCD_BL_EN="PH6" CONFIG_VIDEO_LCD_BL_PWM="PH0" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_AXP_DLDO1_VOLT=3300 CONFIG_CONS_INDEX=5 CONFIG_USB_MUSB_HOST=y diff --git a/configs/qemu-ppce500_defconfig b/configs/qemu-ppce500_defconfig index 70807bf00b04..6a123e4889af 100644 --- a/configs/qemu-ppce500_defconfig +++ b/configs/qemu-ppce500_defconfig @@ -8,6 +8,7 @@ CONFIG_MPC85xx=y CONFIG_TARGET_QEMU_PPCE500=y CONFIG_ENABLE_36BIT_PHYS=y CONFIG_SYS_MPC85XX_NO_RESETVEC=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_STDOUT_VIA_ALIAS=y diff --git a/configs/qemu-riscv32_defconfig b/configs/qemu-riscv32_defconfig index 9634d7f77f11..40ba25297f6c 100644 --- a/configs/qemu-riscv32_defconfig +++ b/configs/qemu-riscv32_defconfig @@ -8,6 +8,7 @@ CONFIG_TARGET_QEMU_VIRT=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y diff --git a/configs/qemu-riscv32_smode_defconfig b/configs/qemu-riscv32_smode_defconfig index c3d13a5b8cad..eb9bf9b918a8 100644 --- a/configs/qemu-riscv32_smode_defconfig +++ b/configs/qemu-riscv32_smode_defconfig @@ -9,6 +9,7 @@ CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_DISPLAY_CPUINFO=y CONFIG_DISPLAY_BOARDINFO=y diff --git a/configs/qemu-riscv32_spl_defconfig b/configs/qemu-riscv32_spl_defconfig index a3a899efc8c0..756e7f35f68b 100644 --- a/configs/qemu-riscv32_spl_defconfig +++ b/configs/qemu-riscv32_spl_defconfig @@ -11,6 +11,7 @@ CONFIG_RISCV_SMODE=y CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x80200000 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FIT=y CONFIG_SPL_LOAD_FIT_ADDRESS=0x80200000 CONFIG_DISPLAY_CPUINFO=y diff --git a/configs/r2dplus_defconfig b/configs/r2dplus_defconfig index a89a07db2a2c..261612d19b85 100644 --- a/configs/r2dplus_defconfig +++ b/configs/r2dplus_defconfig @@ -9,6 +9,7 @@ CONFIG_SYS_CLK_FREQ=60000000 CONFIG_SYS_LOAD_ADDR=0x8e000000 CONFIG_ENV_ADDR=0xA0040000 CONFIG_TARGET_R2DPLUS=y +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_BASE=0xA0000000 CONFIG_BOOTDELAY=-1 CONFIG_USE_BOOTARGS=y diff --git a/configs/r7-tv-dongle_defconfig b/configs/r7-tv-dongle_defconfig index 8875a09b2c98..60d8d7d3739d 100644 --- a/configs/r7-tv-dongle_defconfig +++ b/configs/r7-tv-dongle_defconfig @@ -6,6 +6,7 @@ CONFIG_MACH_SUN5I=y CONFIG_DRAM_CLK=384 CONFIG_USB1_VBUS_PIN="PG13" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/r8a77970_eagle_defconfig b/configs/r8a77970_eagle_defconfig index 5f524ae4ad36..394887f5b9d5 100644 --- a/configs/r8a77970_eagle_defconfig +++ b/configs/r8a77970_eagle_defconfig @@ -15,6 +15,7 @@ CONFIG_RCAR_GEN3=y CONFIG_TARGET_EAGLE=y CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y diff --git a/configs/r8a77980_condor_defconfig b/configs/r8a77980_condor_defconfig index 9e1b17addad8..c934b590d1c9 100644 --- a/configs/r8a77980_condor_defconfig +++ b/configs/r8a77980_condor_defconfig @@ -15,6 +15,7 @@ CONFIG_RCAR_GEN3=y CONFIG_TARGET_CONDOR=y CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y diff --git a/configs/r8a77990_ebisu_defconfig b/configs/r8a77990_ebisu_defconfig index ff7a8fb99a4a..f1e163502dcb 100644 --- a/configs/r8a77990_ebisu_defconfig +++ b/configs/r8a77990_ebisu_defconfig @@ -14,6 +14,7 @@ CONFIG_RCAR_GEN3=y CONFIG_TARGET_EBISU=y CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_MONITOR_BASE=0x00000000 diff --git a/configs/r8a77995_draak_defconfig b/configs/r8a77995_draak_defconfig index 64f9583b9f5f..04808866f1d3 100644 --- a/configs/r8a77995_draak_defconfig +++ b/configs/r8a77995_draak_defconfig @@ -14,6 +14,7 @@ CONFIG_RCAR_GEN3=y CONFIG_TARGET_DRAAK=y CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_MONITOR_BASE=0x00000000 diff --git a/configs/r8a779a0_falcon_defconfig b/configs/r8a779a0_falcon_defconfig index 7375973d0fa9..842a5dd1c67d 100644 --- a/configs/r8a779a0_falcon_defconfig +++ b/configs/r8a779a0_falcon_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_CLK_FREQ=16666666 CONFIG_ARMV8_PSCI=y CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y diff --git a/configs/rcar3_salvator-x_defconfig b/configs/rcar3_salvator-x_defconfig index 6749f816bd11..cba0ce5dea76 100644 --- a/configs/rcar3_salvator-x_defconfig +++ b/configs/rcar3_salvator-x_defconfig @@ -13,6 +13,7 @@ CONFIG_TARGET_SALVATOR_X=y CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_LTO=y CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_FIT=y # CONFIG_BOOTSTD is not set CONFIG_SUPPORT_RAW_INITRD=y diff --git a/configs/rcar3_ulcb_defconfig b/configs/rcar3_ulcb_defconfig index b00e9f4e2bf3..6d90a9065e04 100644 --- a/configs/rcar3_ulcb_defconfig +++ b/configs/rcar3_ulcb_defconfig @@ -14,6 +14,7 @@ CONFIG_RCAR_GEN3=y CONFIG_TARGET_ULCB=y CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_SYS_MONITOR_BASE=0x00000000 diff --git a/configs/riotboard_defconfig b/configs/riotboard_defconfig index bd17c02b24a1..1f7a9ab67a71 100644 --- a/configs/riotboard_defconfig +++ b/configs/riotboard_defconfig @@ -22,6 +22,7 @@ CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_BOOTCOMMAND="run finduuid; run distro_bootcmd" # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/configs/rock-pi-n8-rk3288_defconfig b/configs/rock-pi-n8-rk3288_defconfig index 6227ad39c130..e14d84944090 100644 --- a/configs/rock-pi-n8-rk3288_defconfig +++ b/configs/rock-pi-n8-rk3288_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 +CONFIG_SYS_MONITOR_LEN=614400 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_SILENT_CONSOLE=y diff --git a/configs/rock2_defconfig b/configs/rock2_defconfig index d639ed233857..72c8bfc177aa 100644 --- a/configs/rock2_defconfig +++ b/configs/rock2_defconfig @@ -17,6 +17,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 +CONFIG_SYS_MONITOR_LEN=614400 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-rock2-square.dtb" diff --git a/configs/rzg2_beacon_defconfig b/configs/rzg2_beacon_defconfig index ffcaaccc3370..a409d4e69850 100644 --- a/configs/rzg2_beacon_defconfig +++ b/configs/rzg2_beacon_defconfig @@ -12,6 +12,7 @@ CONFIG_TARGET_BEACON_RZG2M=y CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_LTO=y CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set diff --git a/configs/s5p_goni_defconfig b/configs/s5p_goni_defconfig index d5a1219646f5..d592768921e8 100644 --- a/configs/s5p_goni_defconfig +++ b/configs/s5p_goni_defconfig @@ -14,6 +14,7 @@ CONFIG_SYS_LOAD_ADDR=0x34000000 CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x33000000 +CONFIG_SYS_MONITOR_LEN=262144 # CONFIG_AUTOBOOT is not set CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock8 rootfstype=ext4 ${console} ${meminfo} ${mtdparts}" diff --git a/configs/s5pc210_universal_defconfig b/configs/s5pc210_universal_defconfig index c2e1b67ce6f4..38f63bebd9f2 100644 --- a/configs/s5pc210_universal_defconfig +++ b/configs/s5pc210_universal_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_LOAD_ADDR=0x44800000 CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x447fff10 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="Please use defined boot" CONFIG_BOOTCOMMAND="run mmcboot" diff --git a/configs/sama5d27_giantboard_defconfig b/configs/sama5d27_giantboard_defconfig index 71187df16e62..ef17534d776c 100644 --- a/configs/sama5d27_giantboard_defconfig +++ b/configs/sama5d27_giantboard_defconfig @@ -26,6 +26,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ef0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d27_som1_ek_mmc1_defconfig b/configs/sama5d27_som1_ek_mmc1_defconfig index 8b99f215fb13..759660a48096 100644 --- a/configs/sama5d27_som1_ek_mmc1_defconfig +++ b/configs/sama5d27_som1_ek_mmc1_defconfig @@ -25,6 +25,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d27_som1_ek_mmc_defconfig b/configs/sama5d27_som1_ek_mmc_defconfig index 55a26b5a2f92..a9abc48f07a9 100644 --- a/configs/sama5d27_som1_ek_mmc_defconfig +++ b/configs/sama5d27_som1_ek_mmc_defconfig @@ -26,6 +26,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d27_som1_ek_qspiflash_defconfig b/configs/sama5d27_som1_ek_qspiflash_defconfig index f86a9cca5748..4e5f934d2aa6 100644 --- a/configs/sama5d27_som1_ek_qspiflash_defconfig +++ b/configs/sama5d27_som1_ek_qspiflash_defconfig @@ -26,6 +26,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_QSPI_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d27_wlsom1_ek_mmc_defconfig b/configs/sama5d27_wlsom1_ek_mmc_defconfig index 3bb3cf43a953..3d2e7ad4b95a 100644 --- a/configs/sama5d27_wlsom1_ek_mmc_defconfig +++ b/configs/sama5d27_wlsom1_ek_mmc_defconfig @@ -24,6 +24,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig index d2bb74811ab7..25678a02e481 100644 --- a/configs/sama5d27_wlsom1_ek_qspiflash_defconfig +++ b/configs/sama5d27_wlsom1_ek_qspiflash_defconfig @@ -24,6 +24,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_QSPI_BOOT=y CONFIG_SPI_BOOT=y diff --git a/configs/sama5d2_icp_mmc_defconfig b/configs/sama5d2_icp_mmc_defconfig index 77bdb6d67f28..ae0d50e7d9f8 100644 --- a/configs/sama5d2_icp_mmc_defconfig +++ b/configs/sama5d2_icp_mmc_defconfig @@ -24,6 +24,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d2_icp_qspiflash_defconfig b/configs/sama5d2_icp_qspiflash_defconfig index a8884b0b5d95..0a6d372c2987 100644 --- a/configs/sama5d2_icp_qspiflash_defconfig +++ b/configs/sama5d2_icp_qspiflash_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_BOOT_GET_CMDLINE=y CONFIG_SYS_BOOT_GET_KBD=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_QSPI_BOOT=y CONFIG_SD_BOOT=y diff --git a/configs/sama5d2_xplained_emmc_defconfig b/configs/sama5d2_xplained_emmc_defconfig index b27379c8f703..5763498d971e 100644 --- a/configs/sama5d2_xplained_emmc_defconfig +++ b/configs/sama5d2_xplained_emmc_defconfig @@ -25,6 +25,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d2_xplained_mmc_defconfig b/configs/sama5d2_xplained_mmc_defconfig index f63156d909c2..c2f1c2c31b77 100644 --- a/configs/sama5d2_xplained_mmc_defconfig +++ b/configs/sama5d2_xplained_mmc_defconfig @@ -26,6 +26,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d2_xplained_qspiflash_defconfig b/configs/sama5d2_xplained_qspiflash_defconfig index 9526465bf90f..1cfd3c653c15 100644 --- a/configs/sama5d2_xplained_qspiflash_defconfig +++ b/configs/sama5d2_xplained_qspiflash_defconfig @@ -26,6 +26,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_QSPI_BOOT=y CONFIG_SD_BOOT=y diff --git a/configs/sama5d2_xplained_spiflash_defconfig b/configs/sama5d2_xplained_spiflash_defconfig index fabd4ecea7c1..6401710a5491 100644 --- a/configs/sama5d2_xplained_spiflash_defconfig +++ b/configs/sama5d2_xplained_spiflash_defconfig @@ -28,6 +28,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x22003ee0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d36ek_cmp_mmc_defconfig b/configs/sama5d36ek_cmp_mmc_defconfig index b3e6b5390383..9445fa467d68 100644 --- a/configs/sama5d36ek_cmp_mmc_defconfig +++ b/configs/sama5d36ek_cmp_mmc_defconfig @@ -16,6 +16,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d36ek_cmp_nandflash_defconfig b/configs/sama5d36ek_cmp_nandflash_defconfig index a9632a198fbf..8be34ac62aa1 100644 --- a/configs/sama5d36ek_cmp_nandflash_defconfig +++ b/configs/sama5d36ek_cmp_nandflash_defconfig @@ -16,6 +16,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d36ek_cmp_spiflash_defconfig b/configs/sama5d36ek_cmp_spiflash_defconfig index 5f5caf932a48..9f2cf9d5353d 100644 --- a/configs/sama5d36ek_cmp_spiflash_defconfig +++ b/configs/sama5d36ek_cmp_spiflash_defconfig @@ -18,6 +18,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d3_xplained_mmc_defconfig b/configs/sama5d3_xplained_mmc_defconfig index 834dcc1b8246..f90935ab714a 100644 --- a/configs/sama5d3_xplained_mmc_defconfig +++ b/configs/sama5d3_xplained_mmc_defconfig @@ -26,6 +26,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0 +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d3_xplained_nandflash_defconfig b/configs/sama5d3_xplained_nandflash_defconfig index 93497500bd25..ad3d073a89dc 100644 --- a/configs/sama5d3_xplained_nandflash_defconfig +++ b/configs/sama5d3_xplained_nandflash_defconfig @@ -23,6 +23,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ef0 +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d3xek_mmc_defconfig b/configs/sama5d3xek_mmc_defconfig index fce358c6c33c..c768cd72fabc 100644 --- a/configs/sama5d3xek_mmc_defconfig +++ b/configs/sama5d3xek_mmc_defconfig @@ -26,6 +26,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d3xek_nandflash_defconfig b/configs/sama5d3xek_nandflash_defconfig index 9a4c1d846d5f..3a4be37f698e 100644 --- a/configs/sama5d3xek_nandflash_defconfig +++ b/configs/sama5d3xek_nandflash_defconfig @@ -23,6 +23,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d3xek_spiflash_defconfig b/configs/sama5d3xek_spiflash_defconfig index 9595c06b79c4..b2c8d2d9b1a7 100644 --- a/configs/sama5d3xek_spiflash_defconfig +++ b/configs/sama5d3xek_spiflash_defconfig @@ -28,6 +28,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d4_xplained_mmc_defconfig b/configs/sama5d4_xplained_mmc_defconfig index 0cbdfb9939d0..053047842b6a 100644 --- a/configs/sama5d4_xplained_mmc_defconfig +++ b/configs/sama5d4_xplained_mmc_defconfig @@ -26,6 +26,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d4_xplained_nandflash_defconfig b/configs/sama5d4_xplained_nandflash_defconfig index 2e0e06c5f2db..823373e2780f 100644 --- a/configs/sama5d4_xplained_nandflash_defconfig +++ b/configs/sama5d4_xplained_nandflash_defconfig @@ -23,6 +23,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d4_xplained_spiflash_defconfig b/configs/sama5d4_xplained_spiflash_defconfig index 3c2c9d69d715..76c7bf2120a3 100644 --- a/configs/sama5d4_xplained_spiflash_defconfig +++ b/configs/sama5d4_xplained_spiflash_defconfig @@ -28,6 +28,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d4ek_mmc_defconfig b/configs/sama5d4ek_mmc_defconfig index 23336c56547b..cc701481a994 100644 --- a/configs/sama5d4ek_mmc_defconfig +++ b/configs/sama5d4ek_mmc_defconfig @@ -26,6 +26,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_SD_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d4ek_nandflash_defconfig b/configs/sama5d4ek_nandflash_defconfig index 0b4a2c6baade..a3ee28d79a7e 100644 --- a/configs/sama5d4ek_nandflash_defconfig +++ b/configs/sama5d4ek_nandflash_defconfig @@ -23,6 +23,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_NAND_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/sama5d4ek_spiflash_defconfig b/configs/sama5d4ek_spiflash_defconfig index cca6c471c7be..88e36d033c47 100644 --- a/configs/sama5d4ek_spiflash_defconfig +++ b/configs/sama5d4ek_spiflash_defconfig @@ -28,6 +28,7 @@ CONFIG_DEBUG_UART=y CONFIG_ENV_VARS_UBOOT_CONFIG=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20003ee0 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_SPI_BOOT=y CONFIG_BOOTDELAY=3 diff --git a/configs/seeed_npi_imx6ull_defconfig b/configs/seeed_npi_imx6ull_defconfig index e12a7d850606..541f14f0ab72 100644 --- a/configs/seeed_npi_imx6ull_defconfig +++ b/configs/seeed_npi_imx6ull_defconfig @@ -17,6 +17,7 @@ CONFIG_SPL=y CONFIG_SYS_MEMTEST_START=0x80000000 CONFIG_SYS_MEMTEST_END=0x90000000 CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/silinux_ek874_defconfig b/configs/silinux_ek874_defconfig index b29540a57782..c5ae8202acd3 100644 --- a/configs/silinux_ek874_defconfig +++ b/configs/silinux_ek874_defconfig @@ -15,6 +15,7 @@ CONFIG_RCAR_GEN3=y CONFIG_TARGET_SILINUX_EK874=y CONFIG_SYS_LOAD_ADDR=0x58000000 CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=1048576 CONFIG_FIT=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_USE_BOOTARGS=y diff --git a/configs/silk_defconfig b/configs/silk_defconfig index 84985008fe2d..212e4c16160f 100644 --- a/configs/silk_defconfig +++ b/configs/silk_defconfig @@ -28,6 +28,7 @@ CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_ENV_ADDR=0xC0000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_SPL_MAX_SIZE=0x4000 diff --git a/configs/smdkc100_defconfig b/configs/smdkc100_defconfig index b0048545b554..662b73e41a6c 100644 --- a/configs/smdkc100_defconfig +++ b/configs/smdkc100_defconfig @@ -15,6 +15,7 @@ CONFIG_SYS_LOAD_ADDR=0x30000000 CONFIG_ENV_ADDR=0x40000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2f000000 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="root=/dev/mtdblock5 ubi.mtd=4 rootfstype=cramfs console=ttySAC0,115200n8 mem=128M mtdparts=s3c-onenand:256k(bootloader),128k@0x40000(params),3m@0x60000(kernel),16m@0x360000(test),-(UBI)" diff --git a/configs/smdkv310_defconfig b/configs/smdkv310_defconfig index 92d315ccc069..bfe052323e97 100644 --- a/configs/smdkv310_defconfig +++ b/configs/smdkv310_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_LOAD_ADDR=0x43e00000 CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x2040000 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_BOOTCOMMAND="fatload mmc 0 40007000 uImage; bootm 40007000" # CONFIG_SPL_FRAMEWORK is not set CONFIG_SPL_FOOTPRINT_LIMIT=y diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig index dd6bf60af317..e5daf2f4cce9 100644 --- a/configs/socrates_defconfig +++ b/configs/socrates_defconfig @@ -11,6 +11,7 @@ CONFIG_SYS_INIT_RAM_LOCK=y # CONFIG_CMD_ERRATA is not set CONFIG_TARGET_SOCRATES=y CONFIG_ENABLE_36BIT_PHYS=y +CONFIG_SYS_MONITOR_LEN=393216 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_OF_BOARD_SETUP=y diff --git a/configs/sopine_baseboard_defconfig b/configs/sopine_baseboard_defconfig index fbbef7a9f9ad..84890d8f5ac0 100644 --- a/configs/sopine_baseboard_defconfig +++ b/configs/sopine_baseboard_defconfig @@ -11,6 +11,7 @@ CONFIG_MMC0_CD_PIN="" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_SPL_SPI_SUNXI=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SUPPORT_EMMC_BOOT=y CONFIG_SPI_FLASH_WINBOND=y CONFIG_SUN8I_EMAC=y diff --git a/configs/stm32746g-eval_defconfig b/configs/stm32746g-eval_defconfig index 7200446d287d..5f5a687e77ed 100644 --- a/configs/stm32746g-eval_defconfig +++ b/configs/stm32746g-eval_defconfig @@ -12,6 +12,7 @@ CONFIG_SYS_LOAD_ADDR=0x8008000 CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" diff --git a/configs/stm32746g-eval_spl_defconfig b/configs/stm32746g-eval_spl_defconfig index ff42952a762a..122875349fbc 100644 --- a/configs/stm32746g-eval_spl_defconfig +++ b/configs/stm32746g-eval_spl_defconfig @@ -21,6 +21,7 @@ CONFIG_BUILD_TARGET="u-boot-with-spl.bin" CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" diff --git a/configs/stm32f746-disco_defconfig b/configs/stm32f746-disco_defconfig index a8edf11b4003..c7b6a08dd41a 100644 --- a/configs/stm32f746-disco_defconfig +++ b/configs/stm32f746-disco_defconfig @@ -12,6 +12,7 @@ CONFIG_SYS_LOAD_ADDR=0x8008000 CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" diff --git a/configs/stm32f746-disco_spl_defconfig b/configs/stm32f746-disco_spl_defconfig index 0e358e86ff58..24a981b6069f 100644 --- a/configs/stm32f746-disco_spl_defconfig +++ b/configs/stm32f746-disco_spl_defconfig @@ -21,6 +21,7 @@ CONFIG_BUILD_TARGET="u-boot-with-spl.bin" CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" diff --git a/configs/stm32f769-disco_defconfig b/configs/stm32f769-disco_defconfig index 3e7b5bd06edc..1e002039c7c4 100644 --- a/configs/stm32f769-disco_defconfig +++ b/configs/stm32f769-disco_defconfig @@ -12,6 +12,7 @@ CONFIG_SYS_LOAD_ADDR=0x8008000 CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" diff --git a/configs/stm32f769-disco_spl_defconfig b/configs/stm32f769-disco_spl_defconfig index f0a1b667b89f..124e7cc88233 100644 --- a/configs/stm32f769-disco_spl_defconfig +++ b/configs/stm32f769-disco_spl_defconfig @@ -21,6 +21,7 @@ CONFIG_BUILD_TARGET="u-boot-with-spl.bin" CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x20050000 +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_BOOTDELAY=3 CONFIG_AUTOBOOT_KEYED=y CONFIG_AUTOBOOT_PROMPT="Hit SPACE in %d seconds to stop autoboot.\n" diff --git a/configs/stmark2_defconfig b/configs/stmark2_defconfig index 03fa066d5494..8f348fe4b0f9 100644 --- a/configs/stmark2_defconfig +++ b/configs/stmark2_defconfig @@ -10,6 +10,7 @@ CONFIG_SYS_LOAD_ADDR=0x40010000 CONFIG_TARGET_STMARK2=y CONFIG_MCFTMR=y CONFIG_SYS_BARGSIZE=256 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_TIMESTAMP=y CONFIG_SYS_MONITOR_BASE=0x47E00400 CONFIG_USE_BOOTARGS=y diff --git a/configs/stout_defconfig b/configs/stout_defconfig index b0df55558c7f..5503ec45aa5c 100644 --- a/configs/stout_defconfig +++ b/configs/stout_defconfig @@ -28,6 +28,7 @@ CONFIG_SYS_LOAD_ADDR=0x50000000 CONFIG_ENV_ADDR=0xC0000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x4f000000 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_SPL_MAX_SIZE=0x4000 diff --git a/configs/sun8i_a23_evb_defconfig b/configs/sun8i_a23_evb_defconfig index a3b1d76d8bb1..148015813b29 100644 --- a/configs/sun8i_a23_evb_defconfig +++ b/configs/sun8i_a23_evb_defconfig @@ -9,6 +9,7 @@ CONFIG_USB0_VBUS_PIN="axp_drivebus" CONFIG_USB0_VBUS_DET="axp_vbus_detect" CONFIG_USB1_VBUS_PIN="PH7" # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_CONS_INDEX=5 CONFIG_USB_EHCI_HCD=y CONFIG_USB_OHCI_HCD=y diff --git a/configs/sunxi_Gemei_G9_defconfig b/configs/sunxi_Gemei_G9_defconfig index 3fee7c2e50c0..b67d1fb114d4 100644 --- a/configs/sunxi_Gemei_G9_defconfig +++ b/configs/sunxi_Gemei_G9_defconfig @@ -11,6 +11,7 @@ CONFIG_VIDEO_LCD_BL_EN="PH7" CONFIG_VIDEO_LCD_BL_PWM="PB2" CONFIG_VIDEO_LCD_PANEL_LVDS=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SYS_I2C_MVTWSI=y CONFIG_SYS_I2C_SLAVE=0x7f diff --git a/configs/tanix_tx6_defconfig b/configs/tanix_tx6_defconfig index 0390347415cd..d8095d0d423b 100644 --- a/configs/tanix_tx6_defconfig +++ b/configs/tanix_tx6_defconfig @@ -8,3 +8,4 @@ CONFIG_DRAM_CLK=648 CONFIG_MMC0_CD_PIN="PF6" CONFIG_MMC_SUNXI_SLOT_EXTRA=2 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 diff --git a/configs/tbs_a711_defconfig b/configs/tbs_a711_defconfig index b3c2e69d6cdb..6c3d5d49cda4 100644 --- a/configs/tbs_a711_defconfig +++ b/configs/tbs_a711_defconfig @@ -13,6 +13,7 @@ CONFIG_USB0_VBUS_DET="AXP0-VBUS-DETECT" CONFIG_USB0_ID_DET="PH11" CONFIG_AXP_GPIO=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_FASTBOOT_CMD_OEM_FORMAT=y CONFIG_AXP_DCDC5_VOLT=1200 CONFIG_USB_EHCI_HCD=y diff --git a/configs/teres_i_defconfig b/configs/teres_i_defconfig index e7de85eb506c..64fa2a9761fc 100644 --- a/configs/teres_i_defconfig +++ b/configs/teres_i_defconfig @@ -8,6 +8,7 @@ CONFIG_DRAM_ZQ=3881949 CONFIG_MMC_SUNXI_SLOT_EXTRA=2 CONFIG_USB1_VBUS_PIN="PL7" CONFIG_I2C0_ENABLE=y +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_PREBOOT="setenv usb_pgood_delay 2000; usb start" CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/tinker-rk3288_defconfig b/configs/tinker-rk3288_defconfig index 27ff352fba3b..8fc77bd5bc30 100644 --- a/configs/tinker-rk3288_defconfig +++ b/configs/tinker-rk3288_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 +CONFIG_SYS_MONITOR_LEN=614400 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-tinker.dtb" diff --git a/configs/tinker-s-rk3288_defconfig b/configs/tinker-s-rk3288_defconfig index 28ae79bc0154..ec623465931e 100644 --- a/configs/tinker-s-rk3288_defconfig +++ b/configs/tinker-s-rk3288_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 +CONFIG_SYS_MONITOR_LEN=614400 # CONFIG_ANDROID_BOOT_IMAGE is not set CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-tinker-s.dtb" diff --git a/configs/trats2_defconfig b/configs/trats2_defconfig index c86c3975ff46..84d8704d7f15 100644 --- a/configs/trats2_defconfig +++ b/configs/trats2_defconfig @@ -19,6 +19,7 @@ CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x43dfff10 # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_USE_BOOTARGS=y diff --git a/configs/trats_defconfig b/configs/trats_defconfig index 9bded4cb57f5..6fe046589b9d 100644 --- a/configs/trats_defconfig +++ b/configs/trats_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_LOAD_ADDR=0x44800000 CONFIG_DISTRO_DEFAULTS=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x447fff10 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_USE_BOOTARGS=y diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig index 9237ff04fc22..3ee78a639cd4 100644 --- a/configs/tuge1_defconfig +++ b/configs/tuge1_defconfig @@ -123,6 +123,7 @@ CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_LCRR_EADC_1=y CONFIG_LCRR_CLKDIV_2=y CONFIG_83XX_PCICLK=0x3ef1480 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig index 9fd6cc55e8be..8b704fc43988 100644 --- a/configs/tuxx1_defconfig +++ b/configs/tuxx1_defconfig @@ -145,6 +145,7 @@ CONFIG_ACR_PARKM_USB_I2C1_BOOT=y CONFIG_LCRR_EADC_1=y CONFIG_LCRR_CLKDIV_2=y CONFIG_83XX_PCICLK=0x3ef1480 +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_OF_BOARD_SETUP=y CONFIG_OF_STDOUT_VIA_ALIAS=y CONFIG_AUTOBOOT_KEYED=y diff --git a/configs/udoo_defconfig b/configs/udoo_defconfig index eadc9b600a01..334fcf37de99 100644 --- a/configs/udoo_defconfig +++ b/configs/udoo_defconfig @@ -19,6 +19,7 @@ CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" CONFIG_BOARD_EARLY_INIT_F=y diff --git a/configs/udoo_neo_defconfig b/configs/udoo_neo_defconfig index 4ff449ceece5..ddb855ec81ad 100644 --- a/configs/udoo_neo_defconfig +++ b/configs/udoo_neo_defconfig @@ -20,6 +20,7 @@ CONFIG_SPL=y CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_CMD_BMODE is not set CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_BOOTCOMMAND="run findfdt; run distro_bootcmd" CONFIG_BOARD_EARLY_INIT_F=y CONFIG_SYS_SPL_MALLOC=y diff --git a/configs/uniphier_ld4_sld8_defconfig b/configs/uniphier_ld4_sld8_defconfig index 5de9a6883432..1fa321349643 100644 --- a/configs/uniphier_ld4_sld8_defconfig +++ b/configs/uniphier_ld4_sld8_defconfig @@ -12,6 +12,7 @@ CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_LOAD_ADDR=0x85000000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x84000000 +CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_TIMESTAMP=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot" diff --git a/configs/uniphier_v7_defconfig b/configs/uniphier_v7_defconfig index b6b5ca58c272..b579319b830a 100644 --- a/configs/uniphier_v7_defconfig +++ b/configs/uniphier_v7_defconfig @@ -12,6 +12,7 @@ CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_LOAD_ADDR=0x85000000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x84000000 +CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_TIMESTAMP=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot" diff --git a/configs/uniphier_v8_defconfig b/configs/uniphier_v8_defconfig index eccfb0dbb167..d5bbc3f989a1 100644 --- a/configs/uniphier_v8_defconfig +++ b/configs/uniphier_v8_defconfig @@ -9,6 +9,7 @@ CONFIG_DEFAULT_DEVICE_TREE="uniphier-ld20-ref" CONFIG_ARCH_UNIPHIER_V8_MULTI=y CONFIG_MICRO_SUPPORT_CARD=y CONFIG_SYS_LOAD_ADDR=0x85000000 +CONFIG_SYS_MONITOR_LEN=2097152 CONFIG_TIMESTAMP=y # CONFIG_ARCH_FIXUP_FDT_MEMORY is not set CONFIG_BOOTCOMMAND="run ${bootdev}script; run ${bootdev}boot" diff --git a/configs/variscite_dart6ul_defconfig b/configs/variscite_dart6ul_defconfig index 0f9cc8d82d3b..06bd9b2c4bae 100644 --- a/configs/variscite_dart6ul_defconfig +++ b/configs/variscite_dart6ul_defconfig @@ -15,6 +15,7 @@ CONFIG_SPL_MMC=y CONFIG_SPL_SERIAL=y CONFIG_SPL=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_BOOTDELAY=3 CONFIG_BOOTCOMMAND="run mmc_mmc_fit" diff --git a/configs/verdin-imx8mm_defconfig b/configs/verdin-imx8mm_defconfig index 168b7a5a4b28..21187687960a 100644 --- a/configs/verdin-imx8mm_defconfig +++ b/configs/verdin-imx8mm_defconfig @@ -21,6 +21,7 @@ CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_LTO=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_FIT_VERBOSE=y diff --git a/configs/verdin-imx8mp_defconfig b/configs/verdin-imx8mp_defconfig index d74f594edf09..0b439834fc10 100644 --- a/configs/verdin-imx8mp_defconfig +++ b/configs/verdin-imx8mp_defconfig @@ -27,6 +27,7 @@ CONFIG_SYS_MEMTEST_START=0x40000000 CONFIG_SYS_MEMTEST_END=0x80000000 CONFIG_DISTRO_DEFAULTS=y CONFIG_REMAKE_ELF=y +CONFIG_SYS_MONITOR_LEN=524288 CONFIG_FIT=y CONFIG_FIT_EXTERNAL_OFFSET=0x3000 CONFIG_FIT_VERBOSE=y diff --git a/configs/vining_2000_defconfig b/configs/vining_2000_defconfig index 8445d9439f72..62e6c798a894 100644 --- a/configs/vining_2000_defconfig +++ b/configs/vining_2000_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL=y CONFIG_ENV_OFFSET_REDUND=0x90000 CONFIG_SPL_LIBDISK_SUPPORT=y # CONFIG_CMD_BMODE is not set +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SUPPORT_RAW_INITRD=y diff --git a/configs/vyasa-rk3288_defconfig b/configs/vyasa-rk3288_defconfig index 4b5b1db0ff05..1055bc027b17 100644 --- a/configs/vyasa-rk3288_defconfig +++ b/configs/vyasa-rk3288_defconfig @@ -18,6 +18,7 @@ CONFIG_SYS_LOAD_ADDR=0x800800 CONFIG_DEBUG_UART=y CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x100000 +CONFIG_SYS_MONITOR_LEN=614400 CONFIG_USE_PREBOOT=y CONFIG_DEFAULT_FDT_FILE="rk3288-vyasa.dtb" CONFIG_SILENT_CONSOLE=y diff --git a/configs/wandboard_defconfig b/configs/wandboard_defconfig index 6b49b40fb7e6..3dabfd6b8752 100644 --- a/configs/wandboard_defconfig +++ b/configs/wandboard_defconfig @@ -23,6 +23,7 @@ CONFIG_SPL_LIBDISK_SUPPORT=y CONFIG_CMD_HDMIDETECT=y CONFIG_AHCI=y CONFIG_DISTRO_DEFAULTS=y +CONFIG_SYS_MONITOR_LEN=409600 CONFIG_FIT=y CONFIG_SPL_FIT_PRINT=y CONFIG_SPL_LOAD_FIT=y diff --git a/configs/work_92105_defconfig b/configs/work_92105_defconfig index 7eb23907ebcd..d382f3b33d2e 100644 --- a/configs/work_92105_defconfig +++ b/configs/work_92105_defconfig @@ -22,6 +22,7 @@ CONFIG_ENV_OFFSET_REDUND=0x120000 CONFIG_SYS_LOAD_ADDR=0x80008000 CONFIG_HAS_CUSTOM_SYS_INIT_SP_ADDR=y CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x8007ff20 +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_BOOTDELAY=3 CONFIG_USE_BOOTARGS=y CONFIG_BOOTARGS="console=ttyS2,115200n8" diff --git a/configs/x96_mate_defconfig b/configs/x96_mate_defconfig index 4276f4f543be..41a1c47bd7d4 100644 --- a/configs/x96_mate_defconfig +++ b/configs/x96_mate_defconfig @@ -7,6 +7,7 @@ CONFIG_MACH_SUN50I_H616=y CONFIG_MMC0_CD_PIN="PF6" CONFIG_R_I2C_ENABLE=y # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_SPL_I2C=y CONFIG_SPL_SYS_I2C_LEGACY=y CONFIG_SYS_I2C_MVTWSI=y diff --git a/configs/xtfpga_defconfig b/configs/xtfpga_defconfig index 1242e3508259..31483296802c 100644 --- a/configs/xtfpga_defconfig +++ b/configs/xtfpga_defconfig @@ -8,6 +8,7 @@ CONFIG_SYS_PROMPT="U-Boot> " CONFIG_SYS_LOAD_ADDR=0x02000000 CONFIG_ENV_ADDR=0xF7FE0000 CONFIG_XTFPGA_KC705=y +CONFIG_SYS_MONITOR_LEN=262144 CONFIG_SYS_MONITOR_BASE=0xF6000000 CONFIG_DYNAMIC_SYS_CLK_FREQ=y CONFIG_SHOW_BOOT_PROGRESS=y diff --git a/configs/zeropi_defconfig b/configs/zeropi_defconfig index 11f3715e6dcc..8365da2c4723 100644 --- a/configs/zeropi_defconfig +++ b/configs/zeropi_defconfig @@ -7,6 +7,7 @@ CONFIG_DRAM_CLK=408 CONFIG_MACPWR="PD6" # CONFIG_VIDEO_DE2 is not set # CONFIG_SYS_MALLOC_CLEAR_ON_INIT is not set +CONFIG_SYS_MONITOR_LEN=786432 CONFIG_CONSOLE_MUX=y CONFIG_SUN8I_EMAC=y CONFIG_USB_EHCI_HCD=y diff --git a/include/configs/10m50_devboard.h b/include/configs/10m50_devboard.h index 35560ab68351..afd7cc89bf8e 100644 --- a/include/configs/10m50_devboard.h +++ b/include/configs/10m50_devboard.h @@ -34,6 +34,5 @@ #define CONFIG_SYS_SDRAM_BASE 0xc8000000 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 #define CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_SYS_MONITOR_LEN 0x80000 /* Reserve 512k */
#endif /* __CONFIG_H */ diff --git a/include/configs/3c120_devboard.h b/include/configs/3c120_devboard.h index 69fa1c1b7681..ad7bd133200f 100644 --- a/include/configs/3c120_devboard.h +++ b/include/configs/3c120_devboard.h @@ -29,6 +29,5 @@ #define CONFIG_SYS_SDRAM_BASE 0xD0000000 #define CONFIG_SYS_SDRAM_SIZE 0x08000000 #define CONFIG_MONITOR_IS_IN_RAM -#define CONFIG_SYS_MONITOR_LEN 0x80000 /* Reserve 512k */
#endif /* __CONFIG_H */ diff --git a/include/configs/M5208EVBE.h b/include/configs/M5208EVBE.h index 6c6469b0d4b8..25c3f22bea13 100644 --- a/include/configs/M5208EVBE.h +++ b/include/configs/M5208EVBE.h @@ -70,8 +70,6 @@ #define CONFIG_SYS_SDRAM_EMOD 0x80010000 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 54116413230b..f200d706a92a 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -75,8 +75,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/M5249EVB.h b/include/configs/M5249EVB.h index 42c62b4d684a..9ff66d751c66 100644 --- a/include/configs/M5249EVB.h +++ b/include/configs/M5249EVB.h @@ -62,8 +62,6 @@ #define CONFIG_PRAM 512 /* test-only for SDRAM problem!!!!!!!!!!!!!!!!!!!! */ #endif
-#define CONFIG_SYS_MONITOR_LEN 0x20000 - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/M5253DEMO.h b/include/configs/M5253DEMO.h index 75278f4dab71..f7bfe598a80a 100644 --- a/include/configs/M5253DEMO.h +++ b/include/configs/M5253DEMO.h @@ -82,8 +82,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x00000000 #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */
-#define CONFIG_SYS_MONITOR_LEN 0x40000 - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h index 356ad3e9da1e..dcd83650f22e 100644 --- a/include/configs/M5272C3.h +++ b/include/configs/M5272C3.h @@ -77,8 +77,6 @@ #define CONFIG_SYS_SDRAM_SIZE 4 /* SDRAM size in MB */ #define CONFIG_SYS_FLASH_BASE 0xffe00000
-#define CONFIG_SYS_MONITOR_LEN 0x20000 - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 35ff267371c2..9012794501a8 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -79,8 +79,6 @@ #define CONFIG_SYS_SDRAM_SIZE 16 /* SDRAM size in MB */ #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_CS0_BASE
-#define CONFIG_SYS_MONITOR_LEN 0x20000 - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index 900b0b53434b..e191dc615bc2 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -80,8 +80,6 @@ #define CONFIG_SYS_INT_FLASH_BASE 0xf0000000 #define CONFIG_SYS_INT_FLASH_ENABLE 0x21
-#define CONFIG_SYS_MONITOR_LEN 0x20000 - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/M53017EVB.h b/include/configs/M53017EVB.h index 4f82389cedfa..79a4e6171d23 100644 --- a/include/configs/M53017EVB.h +++ b/include/configs/M53017EVB.h @@ -84,8 +84,6 @@ #define CONFIG_SYS_SDRAM_EMOD 0x80010000 #define CONFIG_SYS_SDRAM_MODE 0x00CD0000
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 474480cc1c24..47ea51c50724 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -78,8 +78,6 @@ #define CONFIG_SYS_SDRAM_EMOD 0x40010000 #define CONFIG_SYS_SDRAM_MODE 0x018D0000
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index 2e1c8579e909..a2e36cc86736 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -80,8 +80,6 @@ #define CONFIG_SYS_SDRAM_EMOD 0x40010000 #define CONFIG_SYS_SDRAM_MODE 0x018D0000
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/MCR3000.h b/include/configs/MCR3000.h index a861ddb5bdd1..7c338b1a6702 100644 --- a/include/configs/MCR3000.h +++ b/include/configs/MCR3000.h @@ -74,7 +74,6 @@ * the maximum mapped by the Linux kernel during initialization. */ #define CONFIG_SYS_BOOTMAPSZ (8 << 20) -#define CONFIG_SYS_MONITOR_LEN (320 << 10)
/* Environment Configuration */
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 476b7dfc0651..eb7e94ec1882 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -126,8 +126,6 @@ * The reserved memory */
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ - /* * Initial RAM Base Address Setup */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index a9486c421a6c..5c9ae85d7ca0 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -234,8 +234,6 @@
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 88d9bec9d927..2c49326484ff 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -301,8 +301,6 @@ extern unsigned long get_sdram_size(void);
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - /* * Config the L2 Cache as L2 SRAM */ diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 4a2546213d0b..135b9907fcd6 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -159,8 +159,6 @@
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - /* Serial Port - controlled on board with jumper J8 * open - index 2 * shorted - index 1 diff --git a/include/configs/SBx81LIFKW.h b/include/configs/SBx81LIFKW.h index e42e6d56532f..9629d735a271 100644 --- a/include/configs/SBx81LIFKW.h +++ b/include/configs/SBx81LIFKW.h @@ -34,8 +34,6 @@ * U-Boot bootcode configuration */
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */ - #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Mem map for Linux*/
/* size in bytes reserved for initial data */ diff --git a/include/configs/SBx81LIFXCAT.h b/include/configs/SBx81LIFXCAT.h index 8926c26b0bdf..67e42b94c117 100644 --- a/include/configs/SBx81LIFXCAT.h +++ b/include/configs/SBx81LIFXCAT.h @@ -34,8 +34,6 @@ * U-Boot bootcode configuration */
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for monitor */ - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index cbe572153468..b730d176ab66 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -294,8 +294,6 @@
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - /* Serial Port */ #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 269c55405695..5a2ae8798f3f 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -264,8 +264,6 @@
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - /* Serial Port - controlled on board with jumper J8 * open - index 2 * shorted - index 1 diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index d3b2c448abd9..75ef2894faa3 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -266,7 +266,6 @@ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
/* * Serial Port diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index b3abe56410a2..b61b40b6271a 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -226,7 +226,6 @@ CONFIG_SYS_INIT_RAM_ADDR_PHYS_LOW) #define CONFIG_SYS_INIT_RAM_SIZE 0x00004000 #define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
/* * Serial Port diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 4b20705db0ff..836a93219ee6 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -85,8 +85,6 @@
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - /* Serial Port - controlled on board with jumper J8 * open - index 2 * shorted - index 1 diff --git a/include/configs/am3517_evm.h b/include/configs/am3517_evm.h index 2dc6bd2f2cdd..27789163e367 100644 --- a/include/configs/am3517_evm.h +++ b/include/configs/am3517_evm.h @@ -89,7 +89,6 @@
/* **** PISMO SUPPORT *** */ /* on one chip */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
#if defined(CONFIG_MTD_RAW_NAND) #define CONFIG_SYS_FLASH_BASE NAND_BASE diff --git a/include/configs/amcore.h b/include/configs/amcore.h index 3f3b399ed7d9..2bda66fe033b 100644 --- a/include/configs/amcore.h +++ b/include/configs/amcore.h @@ -40,7 +40,6 @@ /* amcore design has flash data bytes wired swapped */ #define CONFIG_SYS_WRITE_SWAPPED_DATA /* reserve 128-4KB */ -#define CONFIG_SYS_MONITOR_LEN ((128 - 4) * 1024)
#define LDS_BOARD_TEXT \ . = DEFINED(env_offset) ? env_offset : .; \ diff --git a/include/configs/astro_mcf5373l.h b/include/configs/astro_mcf5373l.h index c79f9ca8f0f4..58635df149b7 100644 --- a/include/configs/astro_mcf5373l.h +++ b/include/configs/astro_mcf5373l.h @@ -189,7 +189,6 @@ #define CONFIG_SYS_FLASH_BASE 0x00000000
/* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10)
/* * For booting Linux, the board info and command line data diff --git a/include/configs/at91sam9263ek.h b/include/configs/at91sam9263ek.h index 3bbc37ec5921..5b0a170daaaa 100644 --- a/include/configs/at91sam9263ek.h +++ b/include/configs/at91sam9263ek.h @@ -41,8 +41,6 @@ #define PHYS_FLASH_1 0x10000000 #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) - /* Address and size of Primary Environment Sector */
#define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/at91sam9m10g45ek.h b/include/configs/at91sam9m10g45ek.h index 4409179e123f..f13c28e3e485 100644 --- a/include/configs/at91sam9m10g45ek.h +++ b/include/configs/at91sam9m10g45ek.h @@ -36,8 +36,6 @@
#endif
-#define CONFIG_SYS_MONITOR_LEN 0x80000 - #ifdef CONFIG_SD_BOOT #elif CONFIG_NAND_BOOT #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 diff --git a/include/configs/at91sam9n12ek.h b/include/configs/at91sam9n12ek.h index 0a0074c5a057..ec9a5c453a60 100644 --- a/include/configs/at91sam9n12ek.h +++ b/include/configs/at91sam9n12ek.h @@ -40,8 +40,6 @@
/* SPL */
-#define CONFIG_SYS_MONITOR_LEN (512 << 10) - #define CONFIG_SYS_MASTER_CLOCK 132096000 #define CONFIG_SYS_AT91_PLLA 0x20953f03 #define CONFIG_SYS_MCKR 0x1301 diff --git a/include/configs/at91sam9x5ek.h b/include/configs/at91sam9x5ek.h index 71246ce0e2bc..71a2863bfc2b 100644 --- a/include/configs/at91sam9x5ek.h +++ b/include/configs/at91sam9x5ek.h @@ -39,8 +39,6 @@
/* SPL */
-#define CONFIG_SYS_MONITOR_LEN (512 << 10) - #define CONFIG_SYS_MASTER_CLOCK 132096000 #define CONFIG_SYS_AT91_PLLA 0x20c73f03 #define CONFIG_SYS_MCKR 0x1301 diff --git a/include/configs/bayleybay.h b/include/configs/bayleybay.h index 0198051bcf26..b347125f2fa0 100644 --- a/include/configs/bayleybay.h +++ b/include/configs/bayleybay.h @@ -12,8 +12,6 @@
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (1 << 20) - #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" diff --git a/include/configs/capricorn-common.h b/include/configs/capricorn-common.h index 6b1e82ad3b17..c4110f84c0bc 100644 --- a/include/configs/capricorn-common.h +++ b/include/configs/capricorn-common.h @@ -14,9 +14,6 @@
/* SPL config */ #ifdef CONFIG_SPL_BUILD - -#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) - #define CONFIG_MALLOC_F_ADDR 0x00120000
#endif /* CONFIG_SPL_BUILD */ diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index 6ac848785195..2c0bf877e86b 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -12,8 +12,6 @@ #include <asm/arch/imx-regs.h>
#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) - #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 #define CONFIG_MALLOC_F_ADDR 0x00120000
diff --git a/include/configs/cherryhill.h b/include/configs/cherryhill.h index 6c7f9ea83bae..726c43d35ea0 100644 --- a/include/configs/cherryhill.h +++ b/include/configs/cherryhill.h @@ -8,8 +8,6 @@
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (2 << 20) - #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \ "stdout=vidconsole,serial\0" \ "stderr=vidconsole,serial\0" diff --git a/include/configs/ci20.h b/include/configs/ci20.h index 192da015e188..f570b34ea02a 100644 --- a/include/configs/ci20.h +++ b/include/configs/ci20.h @@ -14,7 +14,6 @@ #define CONFIG_SYS_MIPS_TIMER_FREQ (CONFIG_SYS_MHZ * 1000000)
/* Memory configuration */ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
#define CONFIG_SYS_SDRAM_BASE 0x80000000 /* cached (KSEG0) address */ #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 diff --git a/include/configs/cm_t43.h b/include/configs/cm_t43.h index 50cb2a47187f..f0fbbe2870bc 100644 --- a/include/configs/cm_t43.h +++ b/include/configs/cm_t43.h @@ -46,7 +46,6 @@ #define CONFIG_HSMMC2_8BIT
#include <configs/ti_armv7_omap.h> -#undef CONFIG_SYS_MONITOR_LEN
#define V_OSCK 24000000 /* Clock output from T2 */ #define V_SCLK (V_OSCK) @@ -74,7 +73,6 @@ "bootz ${loadaddr} - ${fdtaddr}\0"
/* SPL defines. */ -#define CONFIG_SYS_MONITOR_LEN (512 * 1024)
/* EEPROM */
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index ba0662f1f40e..735b2460e915 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -170,8 +170,6 @@ enter a valid image address in flash */
#define CONFIG_SYS_FLASH_BASE 0xffe00000
-#define CONFIG_SYS_MONITOR_LEN 0x20000 - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/conga-qeval20-qa3-e3845.h b/include/configs/conga-qeval20-qa3-e3845.h index 6e819ad25538..823d37fc38ca 100644 --- a/include/configs/conga-qeval20-qa3-e3845.h +++ b/include/configs/conga-qeval20-qa3-e3845.h @@ -12,8 +12,6 @@
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (1 << 20) - #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=serial\0" \ "stderr=serial\0" diff --git a/include/configs/coreboot.h b/include/configs/coreboot.h index 23c493b25820..f73004386fda 100644 --- a/include/configs/coreboot.h +++ b/include/configs/coreboot.h @@ -15,8 +15,6 @@
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (1 << 20) - #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" diff --git a/include/configs/cougarcanyon2.h b/include/configs/cougarcanyon2.h index 353756193eee..efd0b7784350 100644 --- a/include/configs/cougarcanyon2.h +++ b/include/configs/cougarcanyon2.h @@ -8,8 +8,6 @@
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (2 << 20) - #define CONFIG_SMSC_SIO1007
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ diff --git a/include/configs/crownbay.h b/include/configs/crownbay.h index 4c118080cb5c..e8a8af7e6492 100644 --- a/include/configs/crownbay.h +++ b/include/configs/crownbay.h @@ -12,8 +12,6 @@
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (1 << 20) - #define CONFIG_SMSC_LPC47M
#define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ diff --git a/include/configs/devkit3250.h b/include/configs/devkit3250.h index 03adae8e18f9..8561a4583928 100644 --- a/include/configs/devkit3250.h +++ b/include/configs/devkit3250.h @@ -85,7 +85,6 @@ #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
/* See common/spl/spl.c spl_set_header_raw_uboot() */ -#define CONFIG_SYS_MONITOR_LEN CONFIG_SYS_NAND_U_BOOT_SIZE
/* * Include SoC specific configuration diff --git a/include/configs/dfi-bt700.h b/include/configs/dfi-bt700.h index 53ed7de07201..4297047e8ce2 100644 --- a/include/configs/dfi-bt700.h +++ b/include/configs/dfi-bt700.h @@ -12,8 +12,6 @@
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (1 << 20) - #ifndef CONFIG_INTERNAL_UART /* Use BayTrail internal HS UART which is memory-mapped */ #undef CONFIG_SYS_NS16550_PORT_MAPPED diff --git a/include/configs/eb_cpu5282.h b/include/configs/eb_cpu5282.h index 79cacd7dacc6..aaa2ef039d94 100644 --- a/include/configs/eb_cpu5282.h +++ b/include/configs/eb_cpu5282.h @@ -74,8 +74,6 @@ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_SDRAM_BASE0 #define CONFIG_SYS_SDRAM_SIZE CONFIG_SYS_SDRAM_SIZE0
-#define CONFIG_SYS_MONITOR_LEN 0x20000 - /* * For booting Linux, the board info and command line data * have to be in the first 8 MB of memory, since this is diff --git a/include/configs/edison.h b/include/configs/edison.h index c71ef25233bd..b05141ad6450 100644 --- a/include/configs/edison.h +++ b/include/configs/edison.h @@ -12,6 +12,4 @@
#define CONFIG_SYS_STACK_SIZE (32 * 1024)
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) - #endif diff --git a/include/configs/efi-x86_payload.h b/include/configs/efi-x86_payload.h index 59fad4c15dba..f50c2ce4dd07 100644 --- a/include/configs/efi-x86_payload.h +++ b/include/configs/efi-x86_payload.h @@ -12,8 +12,6 @@
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (1 << 20) - #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd,usbkbd\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" diff --git a/include/configs/exynos4-common.h b/include/configs/exynos4-common.h index 054cb5309e70..81f450cde6c4 100644 --- a/include/configs/exynos4-common.h +++ b/include/configs/exynos4-common.h @@ -21,8 +21,6 @@ #define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525 #define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ - /* Common environment variables */ #define ENV_ITB \ "loadkernel=load mmc ${mmcbootdev}:${mmcbootpart} ${kerneladdr} " \ diff --git a/include/configs/galileo.h b/include/configs/galileo.h index 49f57dda58fb..545408a4baa5 100644 --- a/include/configs/galileo.h +++ b/include/configs/galileo.h @@ -12,8 +12,6 @@
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (1 << 20) - /* ns16550 UART is memory-mapped in Quark SoC */ #undef CONFIG_SYS_NS16550_PORT_MAPPED
diff --git a/include/configs/gardena-smart-gateway-at91sam.h b/include/configs/gardena-smart-gateway-at91sam.h index 39fc7b36663c..30d8a0f7c6c9 100644 --- a/include/configs/gardena-smart-gateway-at91sam.h +++ b/include/configs/gardena-smart-gateway-at91sam.h @@ -33,8 +33,6 @@
/* SPL */
-#define CONFIG_SYS_MONITOR_LEN (512 << 10) - #define CONFIG_SYS_MASTER_CLOCK 132096000 #define CONFIG_SYS_AT91_PLLA 0x20c73f03 #define CONFIG_SYS_MCKR 0x1301 diff --git a/include/configs/gazerbeam.h b/include/configs/gazerbeam.h index 8bab723e5699..fa6f0e63ac50 100644 --- a/include/configs/gazerbeam.h +++ b/include/configs/gazerbeam.h @@ -25,8 +25,6 @@ * The reserved memory */
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) /* Reserve 512 kB for Mon */ - /* * Initial RAM Base Address Setup */ diff --git a/include/configs/grpeach.h b/include/configs/grpeach.h index fb69716bcbf4..d2138c220f0a 100644 --- a/include/configs/grpeach.h +++ b/include/configs/grpeach.h @@ -16,8 +16,6 @@ #define CONFIG_SYS_SDRAM_BASE 0x20000000 #define CONFIG_SYS_SDRAM_SIZE (10 * 1024 * 1024)
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - /* Network interface */ #define CONFIG_SH_ETHER_USE_PORT 0 #define CONFIG_SH_ETHER_PHY_ADDR 0 diff --git a/include/configs/imx27lite-common.h b/include/configs/imx27lite-common.h index 40428452954a..232f7868cc25 100644 --- a/include/configs/imx27lite-common.h +++ b/include/configs/imx27lite-common.h @@ -81,7 +81,6 @@ #define PHYS_FLASH_1 0xc0000000 /* Flash Base for U-Boot */ #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* Reserve 256KiB */ /* Address and size of Redundant Environment Sector */
/* diff --git a/include/configs/imx6_spl.h b/include/configs/imx6_spl.h index 488b2f1696a9..3afe418b67dc 100644 --- a/include/configs/imx6_spl.h +++ b/include/configs/imx6_spl.h @@ -9,9 +9,6 @@ #ifdef CONFIG_SPL
/* MMC support */ -#if defined(CONFIG_SPL_MMC) -#define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */ -#endif
/* SATA support */ #if defined(CONFIG_SPL_SATA) diff --git a/include/configs/imx7_spl.h b/include/configs/imx7_spl.h index 5900c05db1fb..362b98075f05 100644 --- a/include/configs/imx7_spl.h +++ b/include/configs/imx7_spl.h @@ -13,9 +13,6 @@ #ifdef CONFIG_SPL
/* MMC support */ -#if defined(CONFIG_SPL_MMC) -#define CONFIG_SYS_MONITOR_LEN 409600 /* 400 KB */ -#endif
#endif /* CONFIG_SPL */
diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index c69f2fa19f30..8046a13e8003 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -11,7 +11,6 @@ #include <asm/arch/imx-regs.h> #include <config_distro_bootcmd.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/imx8mm_beacon.h b/include/configs/imx8mm_beacon.h index 79ed39712250..8e0889945805 100644 --- a/include/configs/imx8mm_beacon.h +++ b/include/configs/imx8mm_beacon.h @@ -9,7 +9,6 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index a5b7e9f5b645..363378b574c7 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -10,8 +10,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_1M - #ifdef CONFIG_SPL_BUILD #define CONFIG_MALLOC_F_ADDR 0x930000
diff --git a/include/configs/imx8mm_evk.h b/include/configs/imx8mm_evk.h index dac642ed0700..f1d1c1c9c3d1 100644 --- a/include/configs/imx8mm_evk.h +++ b/include/configs/imx8mm_evk.h @@ -10,7 +10,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K #define UBOOT_ITB_OFFSET 0x57C00 #define FSPI_CONF_BLOCK_SIZE 0x1000 #define UBOOT_ITB_OFFSET_FSPI \ diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index 6b7f3af53a21..66bc8eef8d96 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -10,7 +10,6 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/imx8mm_venice.h b/include/configs/imx8mm_venice.h index 130156045091..dadc829e4eb1 100644 --- a/include/configs/imx8mm_venice.h +++ b/include/configs/imx8mm_venice.h @@ -9,7 +9,6 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/imx8mn_beacon.h b/include/configs/imx8mn_beacon.h index 6faecbde776d..f6634c85a9b5 100644 --- a/include/configs/imx8mn_beacon.h +++ b/include/configs/imx8mn_beacon.h @@ -9,7 +9,6 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/imx8mn_bsh_smm_s2_common.h b/include/configs/imx8mn_bsh_smm_s2_common.h index a371c5b3832c..d6959ac95a13 100644 --- a/include/configs/imx8mn_bsh_smm_s2_common.h +++ b/include/configs/imx8mn_bsh_smm_s2_common.h @@ -10,7 +10,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/imx8mn_evk.h b/include/configs/imx8mn_evk.h index ae7fcb1027a0..9c75e3eec152 100644 --- a/include/configs/imx8mn_evk.h +++ b/include/configs/imx8mn_evk.h @@ -10,7 +10,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h index c8604e0de592..a1a93e6bee57 100644 --- a/include/configs/imx8mn_var_som.h +++ b/include/configs/imx8mn_var_som.h @@ -10,7 +10,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/imx8mn_venice.h b/include/configs/imx8mn_venice.h index c43c4da6fbf8..940e32ce5b4c 100644 --- a/include/configs/imx8mn_venice.h +++ b/include/configs/imx8mn_venice.h @@ -9,7 +9,6 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h index 4b4731c3035b..124119edc98b 100644 --- a/include/configs/imx8mp_dhcom_pdk2.h +++ b/include/configs/imx8mp_dhcom_pdk2.h @@ -10,8 +10,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_1M - /* Link Definitions */ #define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 #define CONFIG_SYS_INIT_RAM_SIZE 0x200000 diff --git a/include/configs/imx8mp_evk.h b/include/configs/imx8mp_evk.h index 140eba3d1cb0..1b533e2c142e 100644 --- a/include/configs/imx8mp_evk.h +++ b/include/configs/imx8mp_evk.h @@ -10,7 +10,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD diff --git a/include/configs/imx8mp_icore_mx8mp.h b/include/configs/imx8mp_icore_mx8mp.h index 28d44163e4f5..7986d20eed1a 100644 --- a/include/configs/imx8mp_icore_mx8mp.h +++ b/include/configs/imx8mp_icore_mx8mp.h @@ -11,7 +11,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 8eb7456f94ed..b8abdb076340 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -12,7 +12,6 @@ #include <asm/arch/imx-regs.h> #include <config_distro_bootcmd.h>
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
/* GUIDs for capsule updatable firmware images */ diff --git a/include/configs/imx8mp_venice.h b/include/configs/imx8mp_venice.h index 455f5a89dcbd..ef507c339120 100644 --- a/include/configs/imx8mp_venice.h +++ b/include/configs/imx8mp_venice.h @@ -9,7 +9,6 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index ab74d5b26b6f..6aad04e9e97e 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -10,8 +10,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - #ifdef CONFIG_SPL_BUILD #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000
diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index ea4305667f24..8ecd3b7c2717 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -10,8 +10,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index 97bd5044501f..df5af640d45e 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -9,8 +9,6 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 diff --git a/include/configs/imx8qm_mek.h b/include/configs/imx8qm_mek.h index 5f9d06e0f6f4..7f6d59db3aa2 100644 --- a/include/configs/imx8qm_mek.h +++ b/include/configs/imx8qm_mek.h @@ -11,8 +11,6 @@ #include <asm/arch/imx-regs.h>
#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) - #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 #define CONFIG_MALLOC_F_ADDR 0x00120000
diff --git a/include/configs/imx8qxp_mek.h b/include/configs/imx8qxp_mek.h index f8ec16ebb197..567351fcad64 100644 --- a/include/configs/imx8qxp_mek.h +++ b/include/configs/imx8qxp_mek.h @@ -11,8 +11,6 @@ #include <asm/arch/imx-regs.h>
#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) - #define CONFIG_SERIAL_LPUART_BASE 0x5a060000 #define CONFIG_MALLOC_F_ADDR 0x00120000
diff --git a/include/configs/imx8ulp_evk.h b/include/configs/imx8ulp_evk.h index ebfc166b4d46..7bf0ce784c5e 100644 --- a/include/configs/imx8ulp_evk.h +++ b/include/configs/imx8ulp_evk.h @@ -9,7 +9,6 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_UBOOT_BASE (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
#ifdef CONFIG_SPL_BUILD diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index f9750da58055..a9749a1bcaa2 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -10,7 +10,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/integratorcp.h b/include/configs/integratorcp.h index 7b9a5b1c5415..bf09510d02f6 100644 --- a/include/configs/integratorcp.h +++ b/include/configs/integratorcp.h @@ -26,6 +26,5 @@ * Miscellaneous configurable options */ #define PHYS_FLASH_SIZE 0x01000000 /* 16MB */ -#define CONFIG_SYS_MONITOR_LEN 0x00100000
#endif /* __CONFIG_H */ diff --git a/include/configs/km/km-mpc83xx.h b/include/configs/km/km-mpc83xx.h index f05aeaca24fb..181ed1b8fae1 100644 --- a/include/configs/km/km-mpc83xx.h +++ b/include/configs/km/km-mpc83xx.h @@ -26,7 +26,6 @@ #define CONFIG_SYS_FLASH_BASE 0xF0000000
/* Reserve 768 kB for Mon */ -#define CONFIG_SYS_MONITOR_LEN (768 * 1024)
/* * Initial RAM Base Address Setup diff --git a/include/configs/km/pg-wcom-ls102xa.h b/include/configs/km/pg-wcom-ls102xa.h index 1f5a025017d5..0613b77e966f 100644 --- a/include/configs/km/pg-wcom-ls102xa.h +++ b/include/configs/km/pg-wcom-ls102xa.h @@ -177,8 +177,6 @@
#define CONFIG_LS102XA_STREAM_ID
-#define CONFIG_SYS_MONITOR_LEN 0x100000 /* 1Mbyte */ - /* * Environment */ diff --git a/include/configs/kmcent2.h b/include/configs/kmcent2.h index 6032f3913cc7..2e1459e3e4f2 100644 --- a/include/configs/kmcent2.h +++ b/include/configs/kmcent2.h @@ -323,8 +323,6 @@
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN 0xc0000 /* 768k */ - /* * Serial Port - controlled on board with jumper J8 * open - index 2 diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index d77e4b4e1009..5b461d290b70 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -7,8 +7,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN (512 * SZ_1K) - /* GUID for capsule updatable firmware image */ #define KONTRON_PITX_IMX8M_FIT_IMAGE_GUID \ EFI_GUID(0xc898e959, 0x5b1f, 0x4e6d, 0x88, 0xe0, \ diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index df46e586f35f..de20f9b2e002 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -39,8 +39,6 @@
/* SPL */
-#define CONFIG_SYS_MONITOR_LEN (1024 * 1024) - /* GUID for capsule updatable firmware image */ #define KONTRON_SL28_FIT_IMAGE_GUID \ EFI_GUID(0x86ebd44f, 0xfeb8, 0x466f, 0x8b, 0xb8, \ diff --git a/include/configs/librem5.h b/include/configs/librem5.h index 389469aec545..a83363ec869a 100644 --- a/include/configs/librem5.h +++ b/include/configs/librem5.h @@ -15,8 +15,6 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - #ifdef CONFIG_SPL_BUILD
#define CONFIG_SPL_ABORT_ON_RAW_IMAGE /* For RAW image gives a error info not panic */ diff --git a/include/configs/ls1021aiot.h b/include/configs/ls1021aiot.h index f418c8ccf714..885774f63d47 100644 --- a/include/configs/ls1021aiot.h +++ b/include/configs/ls1021aiot.h @@ -41,10 +41,6 @@ #define SDRAM_CFG2_FRC_SR 0x80000000 #define SDRAM_CFG_BI 0x00000001
-#ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_MONITOR_LEN 0x80000 -#endif - #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index 4281a2637287..45f9e4233964 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -10,16 +10,10 @@ #define CONFIG_SYS_INIT_RAM_ADDR OCRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE OCRAM_SIZE
-#ifdef CONFIG_SD_BOOT -#define CONFIG_SYS_MONITOR_LEN 0xc0000 -#endif - #ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_NAND_U_BOOT_SIZE (400 << 10) #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MONITOR_LEN 0x80000 #endif
#define SPD_EEPROM_ADDRESS 0x51 diff --git a/include/configs/ls1021atsn.h b/include/configs/ls1021atsn.h index 157f218a8ec1..fce91192dff7 100644 --- a/include/configs/ls1021atsn.h +++ b/include/configs/ls1021atsn.h @@ -50,9 +50,6 @@ * size increases then increase this size in case of secure boot as * it uses raw U-Boot image instead of FIT image. */ -#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) -#else -#define CONFIG_SYS_MONITOR_LEN 0x100000 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ #endif
diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 83c74b66d3a0..2c96b6f77895 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -53,9 +53,6 @@ * size increases then increase this size in case of secure boot as * it uses raw u-boot image instead of fit image. */ -#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) -#else -#define CONFIG_SYS_MONITOR_LEN 0x100000 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */ #endif
diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index 1fb1d05eba36..c43eb232fb27 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -54,9 +54,6 @@ * size increases then increase this size in case of secure boot as * it uses raw u-boot image instead of fit image. */ -#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) -#else -#define CONFIG_SYS_MONITOR_LEN 0x100000 #endif /* ifdef CONFIG_NXP_ESBC */ #endif
@@ -76,9 +73,6 @@ * size increases then increase this size in case of secure boot as * it uses raw u-boot image instead of fit image. */ -#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) -#else -#define CONFIG_SYS_MONITOR_LEN 0x100000 #endif /* ifdef CONFIG_U_BOOT_HDR_SIZE */
#endif diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index e5fb111f1b88..e94ed26337c9 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -54,22 +54,13 @@ * size increases then increase this size in case of secure boot as * it uses raw u-boot image instead of fit image. */ -#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) -#else -#define CONFIG_SYS_MONITOR_LEN 0x100000 #endif /* ifdef CONFIG_NXP_ESBC */ #endif
-#if defined(CONFIG_QSPI_BOOT) && defined(CONFIG_SPL) -#define CONFIG_SYS_MONITOR_LEN 0x100000 -#endif - /* NAND SPL */ #ifdef CONFIG_NAND_BOOT #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE - -#define CONFIG_SYS_MONITOR_LEN 0xa0000 #endif
/* GPIO */ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 21afe80e70de..bbe52824ccd9 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -146,9 +146,6 @@ unsigned long long get_qixis_addr(void); * size increases then increase this size in case of secure boot as * it uses raw u-boot image instead of fit image. */ -#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) -#else -#define CONFIG_SYS_MONITOR_LEN 0x100000 #endif /* ifdef CONFIG_NXP_ESBC */
#endif diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index e170b5aa2c70..b0f686084f48 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -132,7 +132,6 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_NAND_U_BOOT_DST 0x80400000 #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_NAND_U_BOOT_DST #endif -#define CONFIG_SYS_MONITOR_LEN (1024 * 1024)
#include <asm/arch/soc.h>
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index ed69b8575826..59e54bf6f074 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -27,7 +27,6 @@ #define SPD_EEPROM_ADDRESS5 0x55 #define SPD_EEPROM_ADDRESS6 0x56 #define SPD_EEPROM_ADDRESS SPD_EEPROM_ADDRESS1 -#define CONFIG_SYS_MONITOR_LEN (936 * 1024)
/* Miscellaneous configurable options */
diff --git a/include/configs/minnowmax.h b/include/configs/minnowmax.h index 6bcae31cb61b..50c52f8839b1 100644 --- a/include/configs/minnowmax.h +++ b/include/configs/minnowmax.h @@ -12,8 +12,6 @@
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (1 << 20) - #define CONFIG_STD_DEVICES_SETTINGS "stdin=usbkbd,serial\0" \ "stdout=vidconsole,serial\0" \ "stderr=vidconsole,serial\0" \ diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index da3b18e99889..428b8483e738 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -260,8 +260,6 @@
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (768 * 1024) - #define CONFIG_SYS_CPLD_BASE 0xffa00000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_CPLD_BASE_PHYS 0xfffa00000ull diff --git a/include/configs/phycore_imx8mm.h b/include/configs/phycore_imx8mm.h index 049d1d74345d..c98393b7c757 100644 --- a/include/configs/phycore_imx8mm.h +++ b/include/configs/phycore_imx8mm.h @@ -11,7 +11,6 @@ #include <linux/stringify.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/phycore_imx8mp.h b/include/configs/phycore_imx8mp.h index df1716106fe1..49cd9d4b3c69 100644 --- a/include/configs/phycore_imx8mp.h +++ b/include/configs/phycore_imx8mp.h @@ -10,7 +10,6 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/pic32mzdask.h b/include/configs/pic32mzdask.h index 0a07c9c29c18..af8f8d9a52f9 100644 --- a/include/configs/pic32mzdask.h +++ b/include/configs/pic32mzdask.h @@ -27,8 +27,6 @@ /* SDRAM Configuration (for final code, data, stack, heap) */ #define CONFIG_SYS_SDRAM_BASE 0x88000000
-#define CONFIG_SYS_MONITOR_LEN (192 << 10) - /* Memory Test */
/*---------------------------------------------------------------------- diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index d1cc1b9d63fb..1ee1edbdfffa 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -9,8 +9,6 @@ #include <linux/sizes.h> #include <asm/arch/imx-regs.h>
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - #ifdef CONFIG_SPL_BUILD /*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ #define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 diff --git a/include/configs/pm9g45.h b/include/configs/pm9g45.h index fa47a3ed7935..35fd52568363 100644 --- a/include/configs/pm9g45.h +++ b/include/configs/pm9g45.h @@ -43,8 +43,6 @@
/* Defines for SPL */
-#define CONFIG_SYS_MONITOR_LEN 0x80000 - #ifdef CONFIG_SD_BOOT #elif CONFIG_NAND_BOOT #define CONFIG_SYS_NAND_U_BOOT_SIZE 0x80000 diff --git a/include/configs/qemu-ppce500.h b/include/configs/qemu-ppce500.h index 621135fe1012..9fc51fdfd763 100644 --- a/include/configs/qemu-ppce500.h +++ b/include/configs/qemu-ppce500.h @@ -46,8 +46,6 @@ extern unsigned long long get_phys_ccsrbar_addr_early(void);
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) - /* RTC */ #define CONFIG_RTC_PT7C4338
diff --git a/include/configs/qemu-x86.h b/include/configs/qemu-x86.h index ba843e35a408..5cd13887084c 100644 --- a/include/configs/qemu-x86.h +++ b/include/configs/qemu-x86.h @@ -22,8 +22,6 @@ #include <config_distro_bootcmd.h> #include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (1 << 20) - #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,i8042-kbd\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" diff --git a/include/configs/r2dplus.h b/include/configs/r2dplus.h index f0dfba3fd49f..ac39e11a99e1 100644 --- a/include/configs/r2dplus.h +++ b/include/configs/r2dplus.h @@ -10,7 +10,6 @@ #define CONFIG_SYS_SDRAM_SIZE 0x04000000
/* Address of u-boot image in Flash */ -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
/* diff --git a/include/configs/rcar-gen2-common.h b/include/configs/rcar-gen2-common.h index 2e5421169046..3a38e0656de1 100644 --- a/include/configs/rcar-gen2-common.h +++ b/include/configs/rcar-gen2-common.h @@ -20,8 +20,6 @@ #define CONFIG_SYS_SDRAM_BASE (RCAR_GEN2_SDRAM_BASE) #define CONFIG_SYS_SDRAM_SIZE (RCAR_GEN2_UBOOT_SDRAM_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (256 * 1024) - /* Timer */ #define CONFIG_TMU_TIMER #define CONFIG_SYS_TIMER_COUNTS_DOWN diff --git a/include/configs/rcar-gen3-common.h b/include/configs/rcar-gen3-common.h index 9efda3eeea93..7432cffb5a56 100644 --- a/include/configs/rcar-gen3-common.h +++ b/include/configs/rcar-gen3-common.h @@ -31,8 +31,6 @@ #define CONFIG_VERY_BIG_RAM #define CONFIG_MAX_MEM_MAPPED (0x80000000u - DRAM_RSV_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (1 * 1024 * 1024) - /* ENV setting */
#define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/rk3288_common.h b/include/configs/rk3288_common.h index f4b3481115b3..81f16edbad64 100644 --- a/include/configs/rk3288_common.h +++ b/include/configs/rk3288_common.h @@ -19,8 +19,6 @@ #define SDRAM_BANK_SIZE (2UL << 30) #define SDRAM_MAX_SIZE 0xfe000000
-#define CONFIG_SYS_MONITOR_LEN (600 * 1024) - #define ENV_MEM_LAYOUT_SETTINGS \ "scriptaddr=0x00000000\0" \ "pxefile_addr_r=0x00100000\0" \ diff --git a/include/configs/s5p_goni.h b/include/configs/s5p_goni.h index 712a47a49569..de4510aa4348 100644 --- a/include/configs/s5p_goni.h +++ b/include/configs/s5p_goni.h @@ -121,8 +121,6 @@ #define PHYS_SDRAM_3 0x50000000 /* mDDR DMC2 Bank #2 */ #define PHYS_SDRAM_3_SIZE (128 << 20) /* 128 MB in Bank #2 */
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */ - /* FLASH and environment organization */ #define CONFIG_MMC_DEFAULT_DEV 0
diff --git a/include/configs/sama5d27_som1_ek.h b/include/configs/sama5d27_som1_ek.h index 0eecb561508e..79f354d2e6cc 100644 --- a/include/configs/sama5d27_som1_ek.h +++ b/include/configs/sama5d27_som1_ek.h @@ -16,6 +16,4 @@
/* SPL */
-#define CONFIG_SYS_MONITOR_LEN (512 << 10) - #endif diff --git a/include/configs/sama5d27_wlsom1_ek.h b/include/configs/sama5d27_wlsom1_ek.h index 178a6ad4eed5..de6c92ed7d43 100644 --- a/include/configs/sama5d27_wlsom1_ek.h +++ b/include/configs/sama5d27_wlsom1_ek.h @@ -21,6 +21,4 @@
/* SPL */
-#define CONFIG_SYS_MONITOR_LEN (512 << 10) - #endif diff --git a/include/configs/sama5d2_icp.h b/include/configs/sama5d2_icp.h index b18377be66bf..ebdb39273ef5 100644 --- a/include/configs/sama5d2_icp.h +++ b/include/configs/sama5d2_icp.h @@ -28,6 +28,4 @@
/* SPL */
-#define CONFIG_SYS_MONITOR_LEN (512 << 10) - #endif diff --git a/include/configs/sama5d2_xplained.h b/include/configs/sama5d2_xplained.h index bbd72979b56e..da2ae964f928 100644 --- a/include/configs/sama5d2_xplained.h +++ b/include/configs/sama5d2_xplained.h @@ -13,6 +13,4 @@
/* SPL */
-#define CONFIG_SYS_MONITOR_LEN (512 << 10) - #endif diff --git a/include/configs/sama5d3_xplained.h b/include/configs/sama5d3_xplained.h index 301e8c900c4b..eed688d6b3e4 100644 --- a/include/configs/sama5d3_xplained.h +++ b/include/configs/sama5d3_xplained.h @@ -39,7 +39,6 @@ /* SPL */
/* size of u-boot.bin to load */ -#define CONFIG_SYS_MONITOR_LEN (2 * SZ_512K)
/* Falcon boot support on raw MMC */ /* U-Boot proper stored by default at 0x200 (256 KiB) */ diff --git a/include/configs/sama5d3xek.h b/include/configs/sama5d3xek.h index e211aa52ed0e..a576b8a8ca2b 100644 --- a/include/configs/sama5d3xek.h +++ b/include/configs/sama5d3xek.h @@ -50,6 +50,4 @@
/* SPL */
-#define CONFIG_SYS_MONITOR_LEN (512 << 10) - #endif diff --git a/include/configs/sama5d4_xplained.h b/include/configs/sama5d4_xplained.h index eac41449cb00..c4552c269752 100644 --- a/include/configs/sama5d4_xplained.h +++ b/include/configs/sama5d4_xplained.h @@ -26,6 +26,4 @@
/* SPL */
-#define CONFIG_SYS_MONITOR_LEN (512 << 10) - #endif diff --git a/include/configs/sama5d4ek.h b/include/configs/sama5d4ek.h index bc5312d32c6b..d7199921ba3c 100644 --- a/include/configs/sama5d4ek.h +++ b/include/configs/sama5d4ek.h @@ -26,6 +26,4 @@
/* SPL */
-#define CONFIG_SYS_MONITOR_LEN (512 << 10) - #endif diff --git a/include/configs/smdkc100.h b/include/configs/smdkc100.h index 1395b8dfe38b..ba562b237803 100644 --- a/include/configs/smdkc100.h +++ b/include/configs/smdkc100.h @@ -84,8 +84,6 @@ * FLASH and environment organization */
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* 256 KiB */ - /*----------------------------------------------------------------------- * Boot configuration */ diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 122aec2287f4..3c978f5ee4ec 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -95,8 +95,6 @@
#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
-#define CONFIG_SYS_MONITOR_LEN (384 * 1024) /* Reserve 384KiB for Mon */ - /* FPGA and NAND */ #define CONFIG_SYS_FPGA_BASE 0xc0000000 #define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */ diff --git a/include/configs/som-db5800-som-6867.h b/include/configs/som-db5800-som-6867.h index 201f2c2ece57..ee038d83bc05 100644 --- a/include/configs/som-db5800-som-6867.h +++ b/include/configs/som-db5800-som-6867.h @@ -12,8 +12,6 @@
#include <configs/x86-common.h>
-#define CONFIG_SYS_MONITOR_LEN (1 << 20) - #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial,usbkbd\0" \ "stdout=serial,vidconsole\0" \ "stderr=serial,vidconsole\0" diff --git a/include/configs/stm32f746-disco.h b/include/configs/stm32f746-disco.h index b0ec2261141a..c7d6d9368a2e 100644 --- a/include/configs/stm32f746-disco.h +++ b/include/configs/stm32f746-disco.h @@ -33,7 +33,6 @@ "ramdisk_addr_r=0xC0438000\0" \ BOOTENV
-#define CONFIG_SYS_MONITOR_LEN (512 * 1024) #define CONFIG_SYS_UBOOT_BASE (CONFIG_SYS_FLASH_BASE + \ CONFIG_SPL_PAD_TO)
diff --git a/include/configs/stmark2.h b/include/configs/stmark2.h index 8167d250f27f..ba49075ce068 100644 --- a/include/configs/stmark2.h +++ b/include/configs/stmark2.h @@ -68,7 +68,6 @@ #endif
/* Reserve 256 kB for Monitor */ -#define CONFIG_SYS_MONITOR_LEN (256 << 10)
/* * For booting Linux, the board info and command line data diff --git a/include/configs/sunxi-common.h b/include/configs/sunxi-common.h index 183af45f556f..ed9facf122e2 100644 --- a/include/configs/sunxi-common.h +++ b/include/configs/sunxi-common.h @@ -87,8 +87,6 @@
/* FLASH and environment organization */
-#define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 KiB */ - /* * We cannot use expressions here, because expressions won't be evaluated in * autoconf.mk. diff --git a/include/configs/theadorable-x86-common.h b/include/configs/theadorable-x86-common.h index eaa19ee9b2db..af0a095dfc8c 100644 --- a/include/configs/theadorable-x86-common.h +++ b/include/configs/theadorable-x86-common.h @@ -11,8 +11,6 @@ #ifndef __THEADORABLE_X86_COMMON_H #define __THEADORABLE_X86_COMMON_H
-#define CONFIG_SYS_MONITOR_LEN (1 << 20) - #define CONFIG_STD_DEVICES_SETTINGS "stdin=serial\0" \ "stdout=serial\0" \ "stderr=serial\0" diff --git a/include/configs/ti_omap3_common.h b/include/configs/ti_omap3_common.h index 725a5a62f525..47f3c813b333 100644 --- a/include/configs/ti_omap3_common.h +++ b/include/configs/ti_omap3_common.h @@ -52,8 +52,6 @@ */ #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2)
-#define CONFIG_SYS_MONITOR_LEN (256 << 10) - /* SPL */
#ifdef CONFIG_MTD_RAW_NAND diff --git a/include/configs/uniphier.h b/include/configs/uniphier.h index b92fe3894214..32b47db346f7 100644 --- a/include/configs/uniphier.h +++ b/include/configs/uniphier.h @@ -35,8 +35,6 @@ BOOT_TARGET_DEVICE_UBIFS(func) \ BOOT_TARGET_DEVICE_USB(func)
-#define CONFIG_SYS_MONITOR_LEN 0x00200000 /* 2MB */ - #if !defined(CONFIG_ARM64) /* Time clock 1MHz */ #define CONFIG_SYS_TIMER_RATE 1000000 diff --git a/include/configs/verdin-imx8mm.h b/include/configs/verdin-imx8mm.h index 1de00234f0a0..f513dade6aa6 100644 --- a/include/configs/verdin-imx8mm.h +++ b/include/configs/verdin-imx8mm.h @@ -9,7 +9,6 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/verdin-imx8mp.h b/include/configs/verdin-imx8mp.h index ce7279851480..fea4329d23cc 100644 --- a/include/configs/verdin-imx8mp.h +++ b/include/configs/verdin-imx8mp.h @@ -9,7 +9,6 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h>
-#define CONFIG_SYS_MONITOR_LEN SZ_512K #define CONFIG_SYS_UBOOT_BASE \ (QSPI0_AMBA_BASE + CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)
diff --git a/include/configs/work_92105.h b/include/configs/work_92105.h index 9164f818e9a9..fe6a1c55ce03 100644 --- a/include/configs/work_92105.h +++ b/include/configs/work_92105.h @@ -63,7 +63,6 @@ /* SPL will use serial */ /* SPL will load U-Boot from NAND offset 0x40000 */ /* U-Boot will be 0x40000 bytes, loaded and run at CONFIG_SYS_TEXT_BASE */ -#define CONFIG_SYS_MONITOR_LEN 0x40000 /* actually, MAX size */ #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/x86-chromebook.h b/include/configs/x86-chromebook.h index 4109af7d8511..ec87eddd4c72 100644 --- a/include/configs/x86-chromebook.h +++ b/include/configs/x86-chromebook.h @@ -6,8 +6,6 @@ #ifndef _X86_CHROMEBOOK_H #define _X86_CHROMEBOOK_H
-#define CONFIG_SYS_MONITOR_LEN (1 << 20) - #define CONFIG_X86_MRC_ADDR 0xfffa0000 #define CONFIG_X86_REFCODE_ADDR 0xffea0000 #define CONFIG_X86_REFCODE_RUN_ADDR 0 diff --git a/include/configs/xtfpga.h b/include/configs/xtfpga.h index ad8ea6538c20..58d01f4bb428 100644 --- a/include/configs/xtfpga.h +++ b/include/configs/xtfpga.h @@ -50,11 +50,6 @@ #define CONFIG_SYS_SDRAM_BASE MEMADDR(0x00000000)
/* Lx60 can only map 128kb memory (instead of 256kb) when running under OCD */ -#ifdef CONFIG_XTFPGA_LX60 -# define CONFIG_SYS_MONITOR_LEN 0x00020000 /* 128KB */ -#else -# define CONFIG_SYS_MONITOR_LEN 0x00040000 /* 256KB */ -#endif
/* Memory test is destructive so default must not overlap vectors or U-Boot*/
On Fri, 28 Oct 2022 at 18:31, Tom Rini trini@konsulko.com wrote:
This converts the following to Kconfig: CONFIG_SYS_MONITOR_LEN
To do this, we set a default of 0 for everyone because there are a number of cases where we define CONFIG_SYS_MONITOR_LEN but the only impact is that we set TOTAL_MALLOC_LEN to be CONFIG_SYS_MALLOC_LEN + CONFIG_ENV_SIZE, so we must continue to allow all boards to set this value. Update the SPL code to use 200 KB as the default raw U-Boot size directly, if we don't have a real CONFIG_SYS_MONITOR_LEN value.
Signed-off-by: Tom Rini trini@konsulko.com
Kconfig | 11 +++++++++++ README | 6 ------ common/spl/spl.c | 11 +++++++---- configs/10m50_defconfig | 1 + configs/3c120_defconfig | 1 +
yay!
Reviewed-by: Simon Glass sjg@chromium.org
These files reference SZ_ macros without including <linux/sizes.h>, correct this.
Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-mediatek/mt7981/init.c | 1 + arch/arm/mach-mediatek/mt7986/init.c | 1 + arch/arm/mach-mediatek/mt8512/init.c | 1 + drivers/spi/mtk_spim.c | 1 + 4 files changed, 4 insertions(+)
diff --git a/arch/arm/mach-mediatek/mt7981/init.c b/arch/arm/mach-mediatek/mt7981/init.c index 4f77a3defb02..a8955064e031 100644 --- a/arch/arm/mach-mediatek/mt7981/init.c +++ b/arch/arm/mach-mediatek/mt7981/init.c @@ -8,6 +8,7 @@ #include <asm/armv8/mmu.h> #include <asm/system.h> #include <asm/global_data.h> +#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-mediatek/mt7986/init.c b/arch/arm/mach-mediatek/mt7986/init.c index 0fd459657d99..cf89e63e80ad 100644 --- a/arch/arm/mach-mediatek/mt7986/init.c +++ b/arch/arm/mach-mediatek/mt7986/init.c @@ -8,6 +8,7 @@ #include <asm/armv8/mmu.h> #include <asm/system.h> #include <asm/global_data.h> +#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/arch/arm/mach-mediatek/mt8512/init.c b/arch/arm/mach-mediatek/mt8512/init.c index b7050dfc3922..5a21e9a4485c 100644 --- a/arch/arm/mach-mediatek/mt8512/init.c +++ b/arch/arm/mach-mediatek/mt8512/init.c @@ -21,6 +21,7 @@ #include <asm/sections.h> #include <dm/uclass.h> #include <dt-bindings/clock/mt8512-clk.h> +#include <linux/sizes.h>
DECLARE_GLOBAL_DATA_PTR;
diff --git a/drivers/spi/mtk_spim.c b/drivers/spi/mtk_spim.c index b45ef529a505..a7c0fc593fb1 100644 --- a/drivers/spi/mtk_spim.c +++ b/drivers/spi/mtk_spim.c @@ -22,6 +22,7 @@ #include <linux/dma-mapping.h> #include <linux/io.h> #include <linux/iopoll.h> +#include <linux/sizes.h>
#define SPI_CFG0_REG 0x0000 #define SPI_CFG1_REG 0x0004
On Fri, 28 Oct 2022 at 18:29, Tom Rini trini@konsulko.com wrote:
These files reference SZ_ macros without including <linux/sizes.h>, correct this.
Signed-off-by: Tom Rini trini@konsulko.com
arch/arm/mach-mediatek/mt7981/init.c | 1 + arch/arm/mach-mediatek/mt7986/init.c | 1 + arch/arm/mach-mediatek/mt8512/init.c | 1 + drivers/spi/mtk_spim.c | 1 + 4 files changed, 4 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
The comment block in reserve_noncached has a typo in one filename and an incorrect filename in another function reference. Correct both of these.
Signed-off-by: Tom Rini trini@konsulko.com --- common/board_f.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/common/board_f.c b/common/board_f.c index 4355d1c82d4b..3cbf675e63c8 100644 --- a/common/board_f.c +++ b/common/board_f.c @@ -480,8 +480,8 @@ static int reserve_noncached(void) { /* * The value of gd->start_addr_sp must match the value of malloc_start - * calculated in boatrd_f.c:initr_malloc(), which is passed to - * board_r.c:mem_malloc_init() and then used by + * calculated in board_r.c:initr_malloc(), which is passed to + * dlmalloc.c:mem_malloc_init() and then used by * cache.c:noncached_init() * * These calculations must match the code in cache.c:noncached_init()
On Fri, 28 Oct 2022 at 18:30, Tom Rini trini@konsulko.com wrote:
The comment block in reserve_noncached has a typo in one filename and an incorrect filename in another function reference. Correct both of these.
Signed-off-by: Tom Rini trini@konsulko.com
common/board_f.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
This converts the following to Kconfig: CONFIG_SYS_NONCACHED_MEMORY
To do this we introduce CONFIG_SYS_HAS_NONCACHED_MEMORY as a bool to gate if we are going to have noncached_... functions available and then continue to use CONFIG_SYS_NONCACHED_MEMORY to store the size of said cache. We make this new option depend on both the architectures which implement support and the drivers which make use of it.
Cc: Tom Warren twarren@nvidia.com Cc: Mingming lee mingming.lee@mediatek.com Cc: "Ying-Chun Liu (PaulLiu)" paul.liu@linaro.org Cc: Alban Bedel alban.bedel@avionic-design.de Cc: Stephen Warren swarren@nvidia.com Cc: Marcel Ziswiler marcel.ziswiler@toradex.com Cc: Allen Martin amartin@nvidia.com Signed-off-by: Tom Rini trini@konsulko.com --- I'm cc'ing a bunch of board maintainers here because restricting the noncached support to these drivers results in the noncached framework not being used, but also doesn't change anything else about the binary. Is there some other use case here I'm missing? --- README | 19 ----------------- arch/Kconfig | 24 ++++++++++++++++++++++ configs/apalis-tk1_defconfig | 1 + configs/apalis_t30_defconfig | 1 + configs/beaver_defconfig | 1 + configs/cardhu_defconfig | 1 + configs/cei-tk1-som_defconfig | 1 + configs/colibri_t20_defconfig | 1 + configs/colibri_t30_defconfig | 1 + configs/dalmore_defconfig | 1 + configs/harmony_defconfig | 1 + configs/imx8mp_rsb3720a1_4G_defconfig | 1 + configs/imx8mp_rsb3720a1_6G_defconfig | 1 + configs/jetson-tk1_defconfig | 1 + configs/medcom-wide_defconfig | 1 + configs/mt7621_nand_rfb_defconfig | 1 + configs/mt7621_rfb_defconfig | 1 + configs/mt7622_rfb_defconfig | 1 + configs/mt7623a_unielec_u7623_02_defconfig | 1 + configs/mt7623n_bpir2_defconfig | 1 + configs/mt7629_rfb_defconfig | 1 + configs/mt7981_emmc_rfb_defconfig | 1 + configs/mt7981_rfb_defconfig | 1 + configs/mt7981_sd_rfb_defconfig | 1 + configs/mt7986_rfb_defconfig | 1 + configs/mt7986a_bpir3_emmc_defconfig | 1 + configs/mt7986a_bpir3_sd_defconfig | 1 + configs/mt8512_bm1_emmc_defconfig | 1 + configs/mt8518_ap1_emmc_defconfig | 1 + configs/nyan-big_defconfig | 1 + configs/p2371-0000_defconfig | 1 + configs/p2371-2180_defconfig | 1 + configs/p2571_defconfig | 1 + configs/p2771-0000-000_defconfig | 1 + configs/p2771-0000-500_defconfig | 1 + configs/p3450-0000_defconfig | 1 + configs/paz00_defconfig | 1 + configs/plutux_defconfig | 1 + configs/seaboard_defconfig | 1 + configs/tec-ng_defconfig | 1 + configs/tec_defconfig | 1 + configs/trimslice_defconfig | 1 + configs/venice2_defconfig | 1 + configs/ventana_defconfig | 1 + include/configs/imx8mp_rsb3720.h | 4 ---- include/configs/mt7621.h | 2 -- include/configs/mt7622.h | 4 ---- include/configs/mt7623.h | 2 -- include/configs/mt7629.h | 2 -- include/configs/mt7981.h | 4 ---- include/configs/mt7986.h | 4 ---- include/configs/mt8512.h | 4 ---- include/configs/mt8518.h | 5 ----- include/configs/tegra-common-post.h | 2 -- 54 files changed, 66 insertions(+), 52 deletions(-)
diff --git a/README b/README index ee63a115fa91..edbcc02444a9 100644 --- a/README +++ b/README @@ -1547,25 +1547,6 @@ Configuration Settings: boards which do not use the full malloc in SPL (which is enabled with CONFIG_SYS_SPL_MALLOC).
-- CONFIG_SYS_NONCACHED_MEMORY: - Size of non-cached memory area. This area of memory will be - typically located right below the malloc() area and mapped - uncached in the MMU. This is useful for drivers that would - otherwise require a lot of explicit cache maintenance. For - some drivers it's also impossible to properly maintain the - cache. For example if the regions that need to be flushed - are not a multiple of the cache-line size, *and* padding - cannot be allocated between the regions to align them (i.e. - if the HW requires a contiguous array of regions, and the - size of each region is not cache-aligned), then a flush of - one region may result in overwriting data that hardware has - written to another region in the same cache-line. This can - happen for example in network drivers where descriptors for - buffers are typically smaller than the CPU cache-line (e.g. - 16 bytes vs. 32 or 64 bytes). - - Non-cached memory is only supported on 32-bit ARM at present. - - CONFIG_SYS_BOOTMAPSZ: Maximum size of memory mapped by the startup code of the Linux kernel; all data that must be processed by diff --git a/arch/Kconfig b/arch/Kconfig index 1ffd77c0f4f8..ee5f8d801d7e 100644 --- a/arch/Kconfig +++ b/arch/Kconfig @@ -438,6 +438,30 @@ config TPL_SKIP_LOWLEVEL_INIT_ONLY normal CP15 init (such as enabling the instruction cache) is still performed.
+config SYS_HAS_NONCACHED_MEMORY + bool "Enable reserving a non-cached memory area for drivers" + depends on (ARM || MIPS) && (RTL8169 || MEDIATEK_ETH) + help + This is useful for drivers that would otherwise require a lot of + explicit cache maintenance. For some drivers it's also impossible to + properly maintain the cache. For example if the regions that need to + be flushed are not a multiple of the cache-line size, *and* padding + cannot be allocated between the regions to align them (i.e. if the + HW requires a contiguous array of regions, and the size of each + region is not cache-aligned), then a flush of one region may result + in overwriting data that hardware has written to another region in + the same cache-line. This can happen for example in network drivers + where descriptors for buffers are typically smaller than the CPU + cache-line (e.g. 16 bytes vs. 32 or 64 bytes). + +config SYS_NONCACHED_MEMORY + hex "Size in bytes of the non-cached memory area" + depends on SYS_HAS_NONCACHED_MEMORY + default 0x100000 + help + Size of non-cached memory area. This area of memory will be typically + located right below the malloc() area and mapped uncached in the MMU. + source "arch/arc/Kconfig" source "arch/arm/Kconfig" source "arch/m68k/Kconfig" diff --git a/configs/apalis-tk1_defconfig b/configs/apalis-tk1_defconfig index 47ac0ef2720d..6ae838e8367a 100644 --- a/configs/apalis-tk1_defconfig +++ b/configs/apalis-tk1_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SYS_TEXT_BASE=0x80110000 diff --git a/configs/apalis_t30_defconfig b/configs/apalis_t30_defconfig index d1d2c9047b85..c7561fea6c28 100644 --- a/configs/apalis_t30_defconfig +++ b/configs/apalis_t30_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SYS_TEXT_BASE=0x80110000 diff --git a/configs/beaver_defconfig b/configs/beaver_defconfig index 088ce8eee029..1f7774b1c80b 100644 --- a/configs/beaver_defconfig +++ b/configs/beaver_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SYS_TEXT_BASE=0x80110000 diff --git a/configs/cardhu_defconfig b/configs/cardhu_defconfig index c2960eb6d0d7..bf7bddd047e1 100644 --- a/configs/cardhu_defconfig +++ b/configs/cardhu_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SYS_TEXT_BASE=0x80110000 diff --git a/configs/cei-tk1-som_defconfig b/configs/cei-tk1-som_defconfig index 424657d71015..6c9fca03e29e 100644 --- a/configs/cei-tk1-som_defconfig +++ b/configs/cei-tk1-som_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SYS_TEXT_BASE=0x80110000 diff --git a/configs/colibri_t20_defconfig b/configs/colibri_t20_defconfig index 02e4a7c0b470..f30c644ddfc1 100644 --- a/configs/colibri_t20_defconfig +++ b/configs/colibri_t20_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SYS_TEXT_BASE=0x00110000 diff --git a/configs/colibri_t30_defconfig b/configs/colibri_t30_defconfig index 86e421c1d4fb..39fce7391e12 100644 --- a/configs/colibri_t30_defconfig +++ b/configs/colibri_t30_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SYS_TEXT_BASE=0x80110000 diff --git a/configs/dalmore_defconfig b/configs/dalmore_defconfig index 2fef3a4daa2a..7ada40398a59 100644 --- a/configs/dalmore_defconfig +++ b/configs/dalmore_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SYS_TEXT_BASE=0x80110000 diff --git a/configs/harmony_defconfig b/configs/harmony_defconfig index 0dc0485c6cb4..a2c0b7a2124d 100644 --- a/configs/harmony_defconfig +++ b/configs/harmony_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SYS_TEXT_BASE=0x00110000 diff --git a/configs/imx8mp_rsb3720a1_4G_defconfig b/configs/imx8mp_rsb3720a1_4G_defconfig index 1f4ba696a516..9a44ae0a71c2 100644 --- a/configs/imx8mp_rsb3720a1_4G_defconfig +++ b/configs/imx8mp_rsb3720a1_4G_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_ARCH_IMX8M=y CONFIG_SYS_TEXT_BASE=0x40200000 CONFIG_SYS_MALLOC_LEN=0x2000000 diff --git a/configs/imx8mp_rsb3720a1_6G_defconfig b/configs/imx8mp_rsb3720a1_6G_defconfig index 93373db92800..a0f72b3602f9 100644 --- a/configs/imx8mp_rsb3720a1_6G_defconfig +++ b/configs/imx8mp_rsb3720a1_6G_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_ARCH_IMX8M=y CONFIG_SYS_TEXT_BASE=0x40200000 CONFIG_SYS_MALLOC_LEN=0x2000000 diff --git a/configs/jetson-tk1_defconfig b/configs/jetson-tk1_defconfig index f4f0063abcf8..67b7d1c27c4f 100644 --- a/configs/jetson-tk1_defconfig +++ b/configs/jetson-tk1_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SYS_TEXT_BASE=0x80110000 diff --git a/configs/medcom-wide_defconfig b/configs/medcom-wide_defconfig index d51a124ed49a..2f4212ee9e66 100644 --- a/configs/medcom-wide_defconfig +++ b/configs/medcom-wide_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SYS_TEXT_BASE=0x00110000 diff --git a/configs/mt7621_nand_rfb_defconfig b/configs/mt7621_nand_rfb_defconfig index 0ad4849eb2ae..16411bbb1d78 100644 --- a/configs/mt7621_nand_rfb_defconfig +++ b/configs/mt7621_nand_rfb_defconfig @@ -1,4 +1,5 @@ CONFIG_MIPS=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y diff --git a/configs/mt7621_rfb_defconfig b/configs/mt7621_rfb_defconfig index fa663648173d..17043d9f3cb8 100644 --- a/configs/mt7621_rfb_defconfig +++ b/configs/mt7621_rfb_defconfig @@ -1,4 +1,5 @@ CONFIG_MIPS=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_MALLOC_LEN=0x100000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y diff --git a/configs/mt7622_rfb_defconfig b/configs/mt7622_rfb_defconfig index 82660d83410c..bb8e14eaee09 100644 --- a/configs/mt7622_rfb_defconfig +++ b/configs/mt7622_rfb_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_MEDIATEK=y CONFIG_SYS_TEXT_BASE=0x41e00000 diff --git a/configs/mt7623a_unielec_u7623_02_defconfig b/configs/mt7623a_unielec_u7623_02_defconfig index f052d5e9a1c5..047382da2c4a 100644 --- a/configs/mt7623a_unielec_u7623_02_defconfig +++ b/configs/mt7623a_unielec_u7623_02_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MEDIATEK=y CONFIG_SYS_TEXT_BASE=0x81e00000 diff --git a/configs/mt7623n_bpir2_defconfig b/configs/mt7623n_bpir2_defconfig index 8e101a5258e1..3baef4ccff16 100644 --- a/configs/mt7623n_bpir2_defconfig +++ b/configs/mt7623n_bpir2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MEDIATEK=y CONFIG_SYS_TEXT_BASE=0x81e00000 diff --git a/configs/mt7629_rfb_defconfig b/configs/mt7629_rfb_defconfig index 314a07d554ad..74c7ef48aae0 100644 --- a/configs/mt7629_rfb_defconfig +++ b/configs/mt7629_rfb_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_ARCH_TIMER=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MEDIATEK=y diff --git a/configs/mt7981_emmc_rfb_defconfig b/configs/mt7981_emmc_rfb_defconfig index e7809e691c6e..5df02c58c873 100644 --- a/configs/mt7981_emmc_rfb_defconfig +++ b/configs/mt7981_emmc_rfb_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_MEDIATEK=y CONFIG_SYS_TEXT_BASE=0x41e00000 diff --git a/configs/mt7981_rfb_defconfig b/configs/mt7981_rfb_defconfig index 4f429006d146..0d98fbfa2989 100644 --- a/configs/mt7981_rfb_defconfig +++ b/configs/mt7981_rfb_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_MEDIATEK=y CONFIG_SYS_TEXT_BASE=0x41e00000 diff --git a/configs/mt7981_sd_rfb_defconfig b/configs/mt7981_sd_rfb_defconfig index 2a66a280caf9..c7c4933b62e7 100644 --- a/configs/mt7981_sd_rfb_defconfig +++ b/configs/mt7981_sd_rfb_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_MEDIATEK=y CONFIG_SYS_TEXT_BASE=0x41e00000 diff --git a/configs/mt7986_rfb_defconfig b/configs/mt7986_rfb_defconfig index 0c7411332ca0..ef7a9c833b45 100644 --- a/configs/mt7986_rfb_defconfig +++ b/configs/mt7986_rfb_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_MEDIATEK=y CONFIG_SYS_TEXT_BASE=0x41e00000 diff --git a/configs/mt7986a_bpir3_emmc_defconfig b/configs/mt7986a_bpir3_emmc_defconfig index 11ab8d13fd63..35f79b9c4f0e 100644 --- a/configs/mt7986a_bpir3_emmc_defconfig +++ b/configs/mt7986a_bpir3_emmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_MEDIATEK=y CONFIG_SYS_TEXT_BASE=0x41e00000 diff --git a/configs/mt7986a_bpir3_sd_defconfig b/configs/mt7986a_bpir3_sd_defconfig index 9420a5ac666f..7346377eeab6 100644 --- a/configs/mt7986a_bpir3_sd_defconfig +++ b/configs/mt7986a_bpir3_sd_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_MEDIATEK=y CONFIG_SYS_TEXT_BASE=0x41e00000 diff --git a/configs/mt8512_bm1_emmc_defconfig b/configs/mt8512_bm1_emmc_defconfig index cea990860bdf..27c34c4b10f3 100644 --- a/configs/mt8512_bm1_emmc_defconfig +++ b/configs/mt8512_bm1_emmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=13000000 CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_MEDIATEK=y diff --git a/configs/mt8518_ap1_emmc_defconfig b/configs/mt8518_ap1_emmc_defconfig index 2072eb6d73c3..d9ba9ab14b84 100644 --- a/configs/mt8518_ap1_emmc_defconfig +++ b/configs/mt8518_ap1_emmc_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=13000000 CONFIG_POSITION_INDEPENDENT=y CONFIG_ARCH_MEDIATEK=y diff --git a/configs/nyan-big_defconfig b/configs/nyan-big_defconfig index 6607edde8db5..a64a697fa170 100644 --- a/configs/nyan-big_defconfig +++ b/configs/nyan-big_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SYS_TEXT_BASE=0x81000100 diff --git a/configs/p2371-0000_defconfig b/configs/p2371-0000_defconfig index a33a7fcccd8d..50fa0eb463ea 100644 --- a/configs/p2371-0000_defconfig +++ b/configs/p2371-0000_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SYS_TEXT_BASE=0x80080000 diff --git a/configs/p2371-2180_defconfig b/configs/p2371-2180_defconfig index b95a8f68528e..89b32bde9352 100644 --- a/configs/p2371-2180_defconfig +++ b/configs/p2371-2180_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=19200000 CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y diff --git a/configs/p2571_defconfig b/configs/p2571_defconfig index 0dfd36e553b7..c15550375c28 100644 --- a/configs/p2571_defconfig +++ b/configs/p2571_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SYS_TEXT_BASE=0x80080000 diff --git a/configs/p2771-0000-000_defconfig b/configs/p2771-0000-000_defconfig index e291c3780898..45330fa9ace1 100644 --- a/configs/p2771-0000-000_defconfig +++ b/configs/p2771-0000-000_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=19200000 CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y diff --git a/configs/p2771-0000-500_defconfig b/configs/p2771-0000-500_defconfig index 12282f378489..340616696d71 100644 --- a/configs/p2771-0000-500_defconfig +++ b/configs/p2771-0000-500_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=19200000 CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y diff --git a/configs/p3450-0000_defconfig b/configs/p3450-0000_defconfig index b199fbeaf403..7f846c2441b4 100644 --- a/configs/p3450-0000_defconfig +++ b/configs/p3450-0000_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=19200000 CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y diff --git a/configs/paz00_defconfig b/configs/paz00_defconfig index bb115221f6ca..d1c10584732a 100644 --- a/configs/paz00_defconfig +++ b/configs/paz00_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SYS_TEXT_BASE=0x00110000 diff --git a/configs/plutux_defconfig b/configs/plutux_defconfig index 958392fd6c3f..718a7a7e55ea 100644 --- a/configs/plutux_defconfig +++ b/configs/plutux_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SYS_TEXT_BASE=0x00110000 diff --git a/configs/seaboard_defconfig b/configs/seaboard_defconfig index e3895f520e72..60d25b4003e6 100644 --- a/configs/seaboard_defconfig +++ b/configs/seaboard_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SYS_TEXT_BASE=0x00110000 diff --git a/configs/tec-ng_defconfig b/configs/tec-ng_defconfig index 8745eed2aa30..a089bb9004b9 100644 --- a/configs/tec-ng_defconfig +++ b/configs/tec-ng_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SYS_TEXT_BASE=0x80110000 diff --git a/configs/tec_defconfig b/configs/tec_defconfig index 99d34901d70f..226a86658bf9 100644 --- a/configs/tec_defconfig +++ b/configs/tec_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SYS_TEXT_BASE=0x00110000 diff --git a/configs/trimslice_defconfig b/configs/trimslice_defconfig index 8d94eedbe80c..91d7c2f8e50c 100644 --- a/configs/trimslice_defconfig +++ b/configs/trimslice_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SYS_TEXT_BASE=0x00110000 diff --git a/configs/venice2_defconfig b/configs/venice2_defconfig index 0ac9c4710aa2..478485e10798 100644 --- a/configs/venice2_defconfig +++ b/configs/venice2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SYS_TEXT_BASE=0x80110000 diff --git a/configs/ventana_defconfig b/configs/ventana_defconfig index aac59831ea59..d25951b8df94 100644 --- a/configs/ventana_defconfig +++ b/configs/ventana_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_SYS_L2CACHE_OFF=y CONFIG_ARCH_TEGRA=y CONFIG_SYS_TEXT_BASE=0x00110000 diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index b8abdb076340..5caabf21a646 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -41,10 +41,6 @@ #if defined(CONFIG_CMD_NET) #define CONFIG_FEC_MXC_PHYADDR 4
-#ifdef CONFIG_DWC_ETH_QOS -#define CONFIG_SYS_NONCACHED_MEMORY (1 * SZ_1M) /* 1M */ -#endif - #define PHY_ANEG_TIMEOUT 20000
#endif diff --git a/include/configs/mt7621.h b/include/configs/mt7621.h index 86e48f93349d..517b9b53b134 100644 --- a/include/configs/mt7621.h +++ b/include/configs/mt7621.h @@ -17,8 +17,6 @@
#define CONFIG_SYS_INIT_SP_OFFSET 0x800000
-#define CONFIG_SYS_NONCACHED_MEMORY 0x100000 - /* MMC */ #define MMC_SUPPORTS_TUNING
diff --git a/include/configs/mt7622.h b/include/configs/mt7622.h index 78d79b7780bc..365b65973a81 100644 --- a/include/configs/mt7622.h +++ b/include/configs/mt7622.h @@ -9,10 +9,6 @@ #ifndef __MT7622_H #define __MT7622_H
-#include <linux/sizes.h> - -#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M - /* Uboot definition */ #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/mt7623.h b/include/configs/mt7623.h index 0cd8b08552cf..73093f94d2b6 100644 --- a/include/configs/mt7623.h +++ b/include/configs/mt7623.h @@ -13,8 +13,6 @@
/* Miscellaneous configurable options */
-#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M - /* Environment */
/* Preloader -> Uboot */ diff --git a/include/configs/mt7629.h b/include/configs/mt7629.h index 22d11d014761..668dc3c4f741 100644 --- a/include/configs/mt7629.h +++ b/include/configs/mt7629.h @@ -13,8 +13,6 @@
/* Miscellaneous configurable options */
-#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M - /* Environment */
/* Defines for SPL */ diff --git a/include/configs/mt7981.h b/include/configs/mt7981.h index 01ad30960885..6e2a0b3706d6 100644 --- a/include/configs/mt7981.h +++ b/include/configs/mt7981.h @@ -9,10 +9,6 @@ #ifndef __MT7981_H #define __MT7981_H
-#include <linux/sizes.h> - -#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M - /* Uboot definition */ #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/mt7986.h b/include/configs/mt7986.h index ccdd6abdb180..4c1575992068 100644 --- a/include/configs/mt7986.h +++ b/include/configs/mt7986.h @@ -9,10 +9,6 @@ #ifndef __MT7986_H #define __MT7986_H
-#include <linux/sizes.h> - -#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M - /* Uboot definition */ #define CONFIG_SYS_UBOOT_BASE CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/mt8512.h b/include/configs/mt8512.h index 964c95781338..5bf667aaba12 100644 --- a/include/configs/mt8512.h +++ b/include/configs/mt8512.h @@ -9,10 +9,6 @@ #ifndef __MT8512_H #define __MT8512_H
-#include <linux/sizes.h> - -#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M - /* Uboot definition */ #define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
diff --git a/include/configs/mt8518.h b/include/configs/mt8518.h index 6d4704644e4f..7cabbef92889 100644 --- a/include/configs/mt8518.h +++ b/include/configs/mt8518.h @@ -9,11 +9,6 @@ #ifndef __MT8518_H #define __MT8518_H
-#include <linux/sizes.h> - -#define CONFIG_SYS_NONCACHED_MEMORY SZ_1M - - /* DRAM definition */ #define CONFIG_SYS_SDRAM_BASE 0x40000000 #define CONFIG_SYS_SDRAM_SIZE 0x20000000 diff --git a/include/configs/tegra-common-post.h b/include/configs/tegra-common-post.h index c8f9d7cb175c..db3b3b38f156 100644 --- a/include/configs/tegra-common-post.h +++ b/include/configs/tegra-common-post.h @@ -7,8 +7,6 @@ #ifndef __TEGRA_COMMON_POST_H #define __TEGRA_COMMON_POST_H
-#define CONFIG_SYS_NONCACHED_MEMORY (1 << 20) /* 1 MiB */ - #if CONFIG_IS_ENABLED(CMD_USB) # define BOOT_TARGET_USB(func) func(USB, usb, 0) #else
On Fri, 28 Oct 2022 at 18:30, Tom Rini trini@konsulko.com wrote:
This converts the following to Kconfig: CONFIG_SYS_NONCACHED_MEMORY
To do this we introduce CONFIG_SYS_HAS_NONCACHED_MEMORY as a bool to gate if we are going to have noncached_... functions available and then continue to use CONFIG_SYS_NONCACHED_MEMORY to store the size of said cache. We make this new option depend on both the architectures which implement support and the drivers which make use of it.
Cc: Tom Warren twarren@nvidia.com Cc: Mingming lee mingming.lee@mediatek.com Cc: "Ying-Chun Liu (PaulLiu)" paul.liu@linaro.org Cc: Alban Bedel alban.bedel@avionic-design.de Cc: Stephen Warren swarren@nvidia.com Cc: Marcel Ziswiler marcel.ziswiler@toradex.com Cc: Allen Martin amartin@nvidia.com Signed-off-by: Tom Rini trini@konsulko.com
I'm cc'ing a bunch of board maintainers here because restricting the noncached support to these drivers results in the noncached framework not being used, but also doesn't change anything else about the binary. Is there some other use case here I'm missing?
README | 19 ----------------- arch/Kconfig | 24 ++++++++++++++++++++++
Reviewed-by: Simon Glass sjg@chromium.org
This converts the following to Kconfig: CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
Signed-off-by: Tom Rini trini@konsulko.com --- configs/da850evm_nand_defconfig | 1 + configs/k2e_evm_defconfig | 1 + configs/k2e_hs_evm_defconfig | 1 + configs/k2hk_evm_defconfig | 1 + configs/k2hk_hs_evm_defconfig | 1 + configs/k2l_evm_defconfig | 1 + configs/k2l_hs_evm_defconfig | 1 + configs/omapl138_lcdk_defconfig | 1 + drivers/mtd/nand/raw/Kconfig | 4 ++++ include/configs/da850evm.h | 1 - include/configs/omapl138_lcdk.h | 1 - include/configs/ti_armv7_keystone2.h | 1 - 12 files changed, 12 insertions(+), 3 deletions(-)
diff --git a/configs/da850evm_nand_defconfig b/configs/da850evm_nand_defconfig index f3ae5a77ccc5..dfa0399f3cf1 100644 --- a/configs/da850evm_nand_defconfig +++ b/configs/da850evm_nand_defconfig @@ -86,6 +86,7 @@ CONFIG_DM_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y +CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 diff --git a/configs/k2e_evm_defconfig b/configs/k2e_evm_defconfig index ed2affd8f7f0..4184d280b30e 100644 --- a/configs/k2e_evm_defconfig +++ b/configs/k2e_evm_defconfig @@ -79,6 +79,7 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y +CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/k2e_hs_evm_defconfig b/configs/k2e_hs_evm_defconfig index c19c69903b1b..9958cf7a265f 100644 --- a/configs/k2e_hs_evm_defconfig +++ b/configs/k2e_hs_evm_defconfig @@ -54,6 +54,7 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y +CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/k2hk_evm_defconfig b/configs/k2hk_evm_defconfig index 973d812385b5..9c3e92c11c8a 100644 --- a/configs/k2hk_evm_defconfig +++ b/configs/k2hk_evm_defconfig @@ -79,6 +79,7 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y +CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/k2hk_hs_evm_defconfig b/configs/k2hk_hs_evm_defconfig index fe25c090bbf7..b37e5c829375 100644 --- a/configs/k2hk_hs_evm_defconfig +++ b/configs/k2hk_hs_evm_defconfig @@ -54,6 +54,7 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y +CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/k2l_evm_defconfig b/configs/k2l_evm_defconfig index 437cf4b06d94..e0976312c129 100644 --- a/configs/k2l_evm_defconfig +++ b/configs/k2l_evm_defconfig @@ -79,6 +79,7 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y +CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/k2l_hs_evm_defconfig b/configs/k2l_hs_evm_defconfig index 9b98bc9f2abe..090e16be3128 100644 --- a/configs/k2l_hs_evm_defconfig +++ b/configs/k2l_hs_evm_defconfig @@ -57,6 +57,7 @@ CONFIG_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y +CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_SPEED=30000000 CONFIG_SPI_FLASH_STMICRO=y diff --git a/configs/omapl138_lcdk_defconfig b/configs/omapl138_lcdk_defconfig index a7918aaa0b0a..bc3af8a851c6 100644 --- a/configs/omapl138_lcdk_defconfig +++ b/configs/omapl138_lcdk_defconfig @@ -83,6 +83,7 @@ CONFIG_DM_MTD=y CONFIG_MTD_RAW_NAND=y CONFIG_SYS_NAND_USE_FLASH_BBT=y CONFIG_NAND_DAVINCI=y +CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST=y CONFIG_SYS_NAND_BLOCK_SIZE=0x20000 CONFIG_SYS_NAND_PAGE_COUNT=0x40 CONFIG_SYS_NAND_PAGE_SIZE=0x800 diff --git a/drivers/mtd/nand/raw/Kconfig b/drivers/mtd/nand/raw/Kconfig index 2c03676bf78b..1686f8b94d66 100644 --- a/drivers/mtd/nand/raw/Kconfig +++ b/drivers/mtd/nand/raw/Kconfig @@ -136,6 +136,10 @@ config NAND_DAVINCI Enable this driver for NAND flash controllers available in TI Davinci and Keystone2 platforms
+config SYS_NAND_4BIT_HW_ECC_OOBFIRST + bool "Use 4-bit HW ECC with OOB at the front" + depends on NAND_DAVINCI + config KEYSTONE_RBL_NAND depends on ARCH_KEYSTONE def_bool y diff --git a/include/configs/da850evm.h b/include/configs/da850evm.h index 3625f923a5c1..281cbe37f9d9 100644 --- a/include/configs/da850evm.h +++ b/include/configs/da850evm.h @@ -107,7 +107,6 @@ * Flash & Environment */ #ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_PAGE_2K #define CONFIG_SYS_NAND_CS 3 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE diff --git a/include/configs/omapl138_lcdk.h b/include/configs/omapl138_lcdk.h index df4a16fd0815..410393024158 100644 --- a/include/configs/omapl138_lcdk.h +++ b/include/configs/omapl138_lcdk.h @@ -105,7 +105,6 @@ * Flash & Environment */ #ifdef CONFIG_MTD_RAW_NAND -#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST #define CONFIG_SYS_NAND_PAGE_2K #define CONFIG_SYS_NAND_CS 3 #define CONFIG_SYS_NAND_BASE DAVINCI_ASYNC_EMIF_DATA_CE3_BASE diff --git a/include/configs/ti_armv7_keystone2.h b/include/configs/ti_armv7_keystone2.h index 4078413d0f51..6c01ab813e5a 100644 --- a/include/configs/ti_armv7_keystone2.h +++ b/include/configs/ti_armv7_keystone2.h @@ -65,7 +65,6 @@ #define CONFIG_SYS_NAND_MASK_CLE 0x4000 #define CONFIG_SYS_NAND_MASK_ALE 0x2000 #define CONFIG_SYS_NAND_CS 2 -#define CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
#define CONFIG_SYS_NAND_LARGEPAGE #define CONFIG_SYS_NAND_BASE_LIST { 0x30000000, }
On Fri, 28 Oct 2022 at 18:34, Tom Rini trini@konsulko.com wrote:
This converts the following to Kconfig: CONFIG_SYS_NAND_4BIT_HW_ECC_OOBFIRST
Signed-off-by: Tom Rini trini@konsulko.com
configs/da850evm_nand_defconfig | 1 + configs/k2e_evm_defconfig | 1 + configs/k2e_hs_evm_defconfig | 1 + configs/k2hk_evm_defconfig | 1 + configs/k2hk_hs_evm_defconfig | 1 + configs/k2l_evm_defconfig | 1 + configs/k2l_hs_evm_defconfig | 1 + configs/omapl138_lcdk_defconfig | 1 + drivers/mtd/nand/raw/Kconfig | 4 ++++ include/configs/da850evm.h | 1 - include/configs/omapl138_lcdk.h | 1 - include/configs/ti_armv7_keystone2.h | 1 - 12 files changed, 12 insertions(+), 3 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
Migrate all of COFIG_SYS_MPC* to the CFG_SYS namespace.
Signed-off-by: Tom Rini trini@konsulko.com --- arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c | 2 +- arch/powerpc/cpu/mpc85xx/c29x_serdes.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu.c | 8 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 22 +- arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 4 +- arch/powerpc/cpu/mpc85xx/fdt.c | 6 +- .../powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 4 +- arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 10 +- arch/powerpc/cpu/mpc85xx/interrupts.c | 2 +- arch/powerpc/cpu/mpc85xx/mp.c | 20 +- arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c | 4 +- arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c | 2 +- arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c | 2 +- arch/powerpc/cpu/mpc85xx/p1010_serdes.c | 2 +- arch/powerpc/cpu/mpc85xx/p1021_serdes.c | 4 +- arch/powerpc/cpu/mpc85xx/p1023_serdes.c | 2 +- arch/powerpc/cpu/mpc85xx/p2020_serdes.c | 2 +- arch/powerpc/cpu/mpc85xx/qe_io.c | 2 +- arch/powerpc/cpu/mpc85xx/speed.c | 4 +- arch/powerpc/cpu/mpc85xx/spl_minimal.c | 2 +- arch/powerpc/cpu/mpc85xx/start.S | 8 +- arch/powerpc/cpu/mpc85xx/traps.c | 2 +- arch/powerpc/cpu/mpc8xxx/cpu.c | 14 +- arch/powerpc/cpu/mpc8xxx/law.c | 2 +- arch/powerpc/cpu/mpc8xxx/srio.c | 4 +- arch/powerpc/include/asm/fsl_liodn.h | 26 +-- arch/powerpc/include/asm/immap_83xx.h | 16 +- arch/powerpc/include/asm/immap_85xx.h | 212 +++++++++--------- arch/powerpc/include/asm/mpc85xx_gpio.h | 4 +- board/freescale/common/fsl_chain_of_trust.c | 2 +- board/freescale/common/fsl_validate.c | 2 +- board/freescale/common/mpc85xx_sleep.c | 6 +- board/freescale/common/vid.c | 2 +- board/freescale/mpc8548cds/mpc8548cds.c | 6 +- board/freescale/p1010rdb/p1010rdb.c | 6 +- board/freescale/p1010rdb/spl.c | 2 +- board/freescale/p1010rdb/spl_minimal.c | 2 +- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 12 +- board/freescale/p1_p2_rdb_pc/spl.c | 2 +- board/freescale/p1_p2_rdb_pc/spl_minimal.c | 2 +- board/freescale/p2041rdb/p2041rdb.c | 4 +- board/freescale/t102xrdb/eth_t102xrdb.c | 2 +- board/freescale/t102xrdb/spl.c | 6 +- board/freescale/t102xrdb/t102xrdb.c | 16 +- board/freescale/t104xrdb/eth.c | 2 +- board/freescale/t104xrdb/spl.c | 2 +- board/freescale/t104xrdb/t104xrdb.c | 2 +- board/freescale/t208xqds/eth_t208xqds.c | 6 +- board/freescale/t208xqds/spl.c | 2 +- board/freescale/t208xqds/t208xqds.c | 2 +- board/freescale/t208xrdb/spl.c | 2 +- board/freescale/t4rdb/eth.c | 2 +- board/freescale/t4rdb/spl.c | 2 +- board/keymile/kmcent2/kmcent2.c | 6 +- board/socrates/socrates.c | 6 +- board/xes/common/fsl_8xxx_clk.c | 4 +- board/xes/common/fsl_8xxx_misc.c | 2 +- drivers/ddr/fsl/mpc85xx_ddr_gen2.c | 2 +- drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 2 +- drivers/dma/fsl_dma.c | 4 +- drivers/net/fm/b4860.c | 8 +- drivers/net/fm/p1023.c | 8 +- drivers/net/fm/p4080.c | 8 +- drivers/net/fm/p5020.c | 8 +- drivers/net/fm/p5040.c | 8 +- drivers/net/fm/t1024.c | 6 +- drivers/net/fm/t1040.c | 2 +- drivers/net/fm/t2080.c | 6 +- drivers/net/fm/t4240.c | 8 +- drivers/qe/qe.c | 6 +- drivers/qe/uec.c | 4 +- drivers/spi/fsl_espi.c | 2 +- include/configs/MPC837XERDB.h | 2 +- include/configs/P1010RDB.h | 2 +- include/configs/P2041RDB.h | 2 +- include/configs/T102xRDB.h | 2 +- include/configs/T104xRDB.h | 2 +- include/configs/T208xQDS.h | 2 +- include/configs/T208xRDB.h | 2 +- include/configs/T4240RDB.h | 2 +- include/configs/p1_p2_rdb_pc.h | 2 +- include/post.h | 2 +- 82 files changed, 304 insertions(+), 304 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c index b972cf3b5e45..792133482740 100644 --- a/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c @@ -76,7 +76,7 @@ int is_serdes_configured(enum srds_prtcl prtcl)
void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 pordevsr = in_be32(&gur->pordevsr); u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> MPC85xx_PORDEVSR_IO_SEL_SHIFT; diff --git a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c index 34b58bb7f9e4..e53dd43f31fe 100644 --- a/arch/powerpc/cpu/mpc85xx/c29x_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/c29x_serdes.c @@ -40,7 +40,7 @@ int is_serdes_configured(enum srds_prtcl device)
void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; u32 pordevsr = in_be32(&gur->pordevsr); u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> MPC85xx_PORDEVSR_IO_SEL_SHIFT; diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 14d5c560bf83..432d4b11dcf3 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -59,7 +59,7 @@ int checkcpu (void) #if defined(CONFIG_DYNAMIC_DDR_CLK_FREQ) || \ defined(CONFIG_STATIC_DDR_CLK_FREQ) || defined(CONFIG_FSL_CORENET) ccsr_gur_t __iomem *gur = - (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); #endif
/* @@ -124,7 +124,7 @@ int checkcpu (void) puts("Unicore software on multiprocessor system!!\n" "To enable mutlticore build define CONFIG_MP\n"); #endif - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR); printf("CPU%d: ", pic->whoami); } else { puts("CPU: "); @@ -319,7 +319,7 @@ int do_reset(struct cmd_tbl *cmdtp, int flag, int argc, char *const argv[]) val |= 0x70000000; mtspr(DBCR0,val); #else - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* Call board-specific preparation for reset */ board_reset_prepare(); @@ -436,7 +436,7 @@ int dram_init(void)
#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); unsigned int x = 10; unsigned int i;
diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 92a7e608ceb8..46b44c51961c 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -302,7 +302,7 @@ static void corenet_tb_init(void) volatile ccsr_rcpm_t *rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); volatile ccsr_pic_t *pic = - (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); + (void *)(CFG_SYS_MPC8xxx_PIC_ADDR); u32 whoami = in_be32(&pic->whoami);
/* Enable the timebase register for this core */ @@ -313,7 +313,7 @@ static void corenet_tb_init(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A007212 void fsl_erratum_a007212_workaround(void) { - ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 ddr_pll_ratio; u32 __iomem *plldgdcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c20); u32 __iomem *plldadcr1 = (void *)(CONFIG_SYS_DCSRBAR + 0x21c28); @@ -379,13 +379,13 @@ ulong cpu_init_f(void) { extern void m8560_cpm_reset (void); #ifdef CONFIG_SYS_DCSRBAR_PHYS - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); #endif #if defined(CONFIG_NXP_ESBC) && !defined(CONFIG_SYS_RAMBOOT) struct law_entry law; #endif #ifdef CONFIG_ARCH_MPC8548 - ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); + ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR); uint svr = get_svr();
/* @@ -455,7 +455,7 @@ int enable_cluster_l2(void) { int i = 0; u32 cluster, svr = get_svr(); - ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); struct ccsr_cluster_l2 __iomem *l2cache;
/* only the L2 of first cluster should be enabled as expected on T4080, @@ -516,7 +516,7 @@ int l2cache_init(void) { __maybe_unused u32 svr = get_svr(); #ifdef CONFIG_L2_CACHE - ccsr_l2cache_t *l2cache = (void __iomem *)CONFIG_SYS_MPC85xx_L2_ADDR; + ccsr_l2cache_t *l2cache = (void __iomem *)CFG_SYS_MPC85xx_L2_ADDR; #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; #endif @@ -821,7 +821,7 @@ int cpu_init_r(void) #ifdef CONFIG_SYS_FSL_USB1_PHY_ENABLE { struct ccsr_usb_phy __iomem *usb_phy1 = - (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; + (void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR; #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 if (has_erratum_a006261()) fsl_erratum_a006261_workaround(usb_phy1); @@ -833,7 +833,7 @@ int cpu_init_r(void) #ifdef CONFIG_SYS_FSL_USB2_PHY_ENABLE { struct ccsr_usb_phy __iomem *usb_phy2 = - (void *)CONFIG_SYS_MPC85xx_USB2_PHY_ADDR; + (void *)CFG_SYS_MPC85xx_USB2_PHY_ADDR; #ifdef CONFIG_SYS_FSL_ERRATUM_A006261 if (has_erratum_a006261()) fsl_erratum_a006261_workaround(usb_phy2); @@ -859,7 +859,7 @@ int cpu_init_r(void)
#if defined(CONFIG_SYS_FSL_USB_DUAL_PHY_ENABLE) struct ccsr_usb_phy __iomem *usb_phy = - (void *)CONFIG_SYS_MPC85xx_USB1_PHY_ADDR; + (void *)CFG_SYS_MPC85xx_USB1_PHY_ADDR; setbits_be32(&usb_phy->pllprg[1], CONFIG_SYS_FSL_USB_PLLPRG2_PHY2_CLK_EN | CONFIG_SYS_FSL_USB_PLLPRG2_PHY1_CLK_EN | @@ -928,11 +928,11 @@ int cpu_init_r(void) fsl_sata_reg_t *reg;
/* first SATA controller */ - reg = (void *)CONFIG_SYS_MPC85xx_SATA1_ADDR; + reg = (void *)CFG_SYS_MPC85xx_SATA1_ADDR; clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN);
/* second SATA controller */ - reg = (void *)CONFIG_SYS_MPC85xx_SATA2_ADDR; + reg = (void *)CFG_SYS_MPC85xx_SATA2_ADDR; clrbits_le32(®->hcontrol, HCONTROL_ENTERPRISE_EN); } #endif diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c index 1bba216371b8..59147222d5cd 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init_early.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init_early.c @@ -85,10 +85,10 @@ void cpu_init_early_f(void *fdt) { u32 mas0, mas1, mas2, mas3, mas7; #ifdef CONFIG_SYS_FSL_ERRATUM_P1010_A003549 - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); #endif #ifdef CONFIG_A003399_NOR_WORKAROUND - ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; + ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR; u32 *dst, *src; void (*setup_ifc_sram)(void); int i; diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index c8ad6a1b01ce..266a61163f50 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -222,7 +222,7 @@ static inline void ft_fixup_l2cache_compatible(void *blob, int off) /* return size in kilobytes */ static inline u32 l2cache_size(void) { - volatile ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; + volatile ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR; volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3; u32 ver = SVR_SOC_VER(get_svr());
@@ -509,7 +509,7 @@ static void ft_fixup_qe_snum(void *blob) #if defined(CONFIG_ARCH_P4080) static void fdt_fixup_usb(void *fdt) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 rcwsr11 = in_be32(&gur->rcwsr[11]); int off;
@@ -532,7 +532,7 @@ void fdt_fixup_dma3(void *blob) { /* the 3rd DMA is not functional if SRIO2 is chosen */ int nodeoff; - ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
#define CONFIG_SYS_ELO3_DMA3 (0xffe000000 + 0x102300) #if defined(CONFIG_ARCH_T2080) diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index da8e0b655544..1a30395256b9 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -122,7 +122,7 @@ int is_serdes_configured(enum srds_prtcl device)
int serdes_get_first_lane(u32 sd, enum srds_prtcl device) { - const ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + const ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 cfg = in_be32(&gur->rcwsr[4]); int i;
@@ -193,7 +193,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device) void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) { - ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 cfg; int lane;
diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 2b4912bea0a3..1d35733c013d 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -108,7 +108,7 @@ int serdes_get_bank_by_lane(int lane)
int serdes_lane_enabled(int lane) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR;
int bank = lanes[lane].bank; @@ -133,7 +133,7 @@ int serdes_lane_enabled(int lane)
int is_serdes_configured(enum srds_prtcl device) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* Is serdes enabled at all? */ if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) @@ -169,7 +169,7 @@ int serdes_get_first_lane(enum srds_prtcl device) u32 prtcl; const ccsr_gur_t *gur;
- gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR; + gur = (typeof(gur))CFG_SYS_MPC85xx_GUTS_ADDR;
/* Is serdes enabled at all? */ if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) @@ -251,7 +251,7 @@ void serdes_reset_rx(enum srds_prtcl device) if (unlikely(device == NONE)) return;
- gur = (typeof(gur))CONFIG_SYS_MPC85xx_GUTS_ADDR; + gur = (typeof(gur))CFG_SYS_MPC85xx_GUTS_ADDR;
/* Is serdes enabled at all? */ if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) @@ -491,7 +491,7 @@ void soc_serdes_init(void) __attribute__((weak, alias("__soc_serdes_init")));
void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); int cfg; serdes_corenet_t *srds_regs; #ifdef CONFIG_ARCH_P5040 diff --git a/arch/powerpc/cpu/mpc85xx/interrupts.c b/arch/powerpc/cpu/mpc85xx/interrupts.c index 4ad762683fb9..bcbdfac02792 100644 --- a/arch/powerpc/cpu/mpc85xx/interrupts.c +++ b/arch/powerpc/cpu/mpc85xx/interrupts.c @@ -25,7 +25,7 @@
void interrupt_init_cpu(unsigned *decrementer_count) { - ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; + ccsr_pic_t __iomem *pic = (void *)CFG_SYS_MPC8xxx_PIC_ADDR;
#ifdef CONFIG_POST /* diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index 84eb8b466b71..e1469eb296a0 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -50,7 +50,7 @@ int hold_cores_in_reset(int verbose)
int cpu_reset(u32 nr) { - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR); out_be32(&pic->pir, 1 << nr); /* the dummy read works around an errata on early 85xx MP PICs */ (void)in_be32(&pic->pir); @@ -87,7 +87,7 @@ int cpu_status(u32 nr) #ifdef CONFIG_FSL_CORENET int cpu_disable(u32 nr) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->coredisrl, 1 << nr);
@@ -95,7 +95,7 @@ int cpu_disable(u32 nr) }
int is_core_disabled(int nr) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 coredisrl = in_be32(&gur->coredisrl);
return (coredisrl & (1 << nr)); @@ -103,7 +103,7 @@ int is_core_disabled(int nr) { #else int cpu_disable(u32 nr) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
switch (nr) { case 0: @@ -121,7 +121,7 @@ int cpu_disable(u32 nr) }
int is_core_disabled(int nr) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 devdisr = in_be32(&gur->devdisr);
switch (nr) { @@ -264,10 +264,10 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) u32 mask = cpu_mask(); struct law_entry e;
- gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); - pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); + pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
whoami = in_be32(&pic->whoami); cpu_up_mask = 1 << whoami; @@ -336,9 +336,9 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) u32 up, cpu_up_mask, whoami; u32 *table = (u32 *)&__spin_table; volatile u32 bpcr; - volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR); u32 devdisr; int timeout = 10;
diff --git a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c index 111692f15d18..cbcb57fe3a54 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8536_serdes.c @@ -89,8 +89,8 @@ int is_serdes_configured(enum srds_prtcl device)
void fsl_serdes_init(void) { - void *guts = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - void *sd = (void *)CONFIG_SYS_MPC85xx_SERDES2_ADDR; + void *guts = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + void *sd = (void *)CFG_SYS_MPC85xx_SERDES2_ADDR; u32 pordevsr = in_be32(guts + GUTS_PORDEVSR_OFFS); u32 srds1_io_sel, srds2_io_sel; u32 tmp; diff --git a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c index f3b5450ad55c..a48f3c151285 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8544_serdes.c @@ -52,7 +52,7 @@ int is_serdes_configured(enum srds_prtcl device)
void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; u32 pordevsr = in_be32(&gur->pordevsr); u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> MPC85xx_PORDEVSR_IO_SEL_SHIFT; diff --git a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c index 2a5c3e32002a..bf3c458565a6 100644 --- a/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/mpc8548_serdes.c @@ -32,7 +32,7 @@ int is_serdes_configured(enum srds_prtcl prtcl)
void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 pordevsr = in_be32(&gur->pordevsr); u32 srds1_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> MPC85xx_PORDEVSR_IO_SEL_SHIFT; diff --git a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c index 8cba4222c4fc..56e5ef6468c1 100644 --- a/arch/powerpc/cpu/mpc85xx/p1010_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1010_serdes.c @@ -51,7 +51,7 @@ int is_serdes_configured(enum srds_prtcl device)
void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; u32 pordevsr = in_be32(&gur->pordevsr); u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> MPC85xx_PORDEVSR_IO_SEL_SHIFT; diff --git a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c index 6b8e447e94a4..47f13e3c1cd7 100644 --- a/arch/powerpc/cpu/mpc85xx/p1021_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1021_serdes.c @@ -50,8 +50,8 @@ int is_serdes_configured(enum srds_prtcl prtcl)
void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - serdes_85xx_t *serdes = (void *)CONFIG_SYS_MPC85xx_SERDES1_ADDR; + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + serdes_85xx_t *serdes = (void *)CFG_SYS_MPC85xx_SERDES1_ADDR;
u32 pordevsr = in_be32(&gur->pordevsr); u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> diff --git a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c index bf5cac619920..7a8f653727ef 100644 --- a/arch/powerpc/cpu/mpc85xx/p1023_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p1023_serdes.c @@ -35,7 +35,7 @@ int is_serdes_configured(enum srds_prtcl device)
void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; u32 pordevsr = in_be32(&gur->pordevsr); u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> MPC85xx_PORDEVSR_IO_SEL_SHIFT; diff --git a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c index f36b1b64ede7..8c5d82ae8ade 100644 --- a/arch/powerpc/cpu/mpc85xx/p2020_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/p2020_serdes.c @@ -40,7 +40,7 @@ int is_serdes_configured(enum srds_prtcl prtcl)
void fsl_serdes_init(void) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 pordevsr = in_be32(&gur->pordevsr); u32 srds_cfg = (pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> MPC85xx_PORDEVSR_IO_SEL_SHIFT; diff --git a/arch/powerpc/cpu/mpc85xx/qe_io.c b/arch/powerpc/cpu/mpc85xx/qe_io.c index c5b1443058e2..3cf41ca76d5b 100644 --- a/arch/powerpc/cpu/mpc85xx/qe_io.c +++ b/arch/powerpc/cpu/mpc85xx/qe_io.c @@ -20,7 +20,7 @@ void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) u32 pin_2bit_assign; u32 pin_1bit_mask; u32 tmp_val; - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); volatile par_io_t *par_io = (volatile par_io_t *) &(gur->qe_par_io);
diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index 6686b7c93cb5..a7004a670bbc 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -24,7 +24,7 @@ DECLARE_GLOBAL_DATA_PTR;
void get_sys_info(sys_info_t *sys_info) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_FSL_CORENET volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); unsigned int cpu; @@ -575,7 +575,7 @@ int get_clocks(void) { sys_info_t sys_info; #ifdef CONFIG_ARCH_MPC8544 - volatile ccsr_gur_t *gur = (void *) CONFIG_SYS_MPC85xx_GUTS_ADDR; + volatile ccsr_gur_t *gur = (void *) CFG_SYS_MPC85xx_GUTS_ADDR; #endif get_sys_info (&sys_info); gd->cpu_clk = sys_info.freq_processor[0]; diff --git a/arch/powerpc/cpu/mpc85xx/spl_minimal.c b/arch/powerpc/cpu/mpc85xx/spl_minimal.c index bdd73389d902..47df3c2ce19f 100644 --- a/arch/powerpc/cpu/mpc85xx/spl_minimal.c +++ b/arch/powerpc/cpu/mpc85xx/spl_minimal.c @@ -15,7 +15,7 @@ DECLARE_GLOBAL_DATA_PTR; ulong cpu_init_f(void) { #ifdef CONFIG_SYS_INIT_L2_ADDR - ccsr_l2cache_t *l2cache = (void *)CONFIG_SYS_MPC85xx_L2_ADDR; + ccsr_l2cache_t *l2cache = (void *)CFG_SYS_MPC85xx_L2_ADDR;
out_be32(&l2cache->l2srbar0, CONFIG_SYS_INIT_L2_ADDR);
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 9d44fa415890..024414e9ff96 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -80,7 +80,7 @@
/* Definitions from C header file asm/immap_85xx.h */
-#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 +#define CFG_SYS_MPC85xx_L2_OFFSET 0x20000
#define MPC85xx_L2CTL 0x000 #define MPC85xx_L2CTL_L2E 0x80000000 @@ -127,13 +127,13 @@ bootsect: .org 0x80 /* Start of configuration */ .Lconf_pair_start:
- .long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */ + .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2SRBAR0 /* Address: L2 memory-mapped SRAM base addr 0 */ .long CONFIG_SYS_INIT_L2_ADDR
- .long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */ + .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2ERRDIS /* Address: L2 cache error disable */ .long MPC85xx_L2ERRDIS_MBECC | MPC85xx_L2ERRDIS_SBECC
- .long CONFIG_SYS_CCSRBAR_DEFAULT + CONFIG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2CTL /* Address: L2 configuration 0 */ + .long CONFIG_SYS_CCSRBAR_DEFAULT + CFG_SYS_MPC85xx_L2_OFFSET + MPC85xx_L2CTL /* Address: L2 configuration 0 */ .long MPC85xx_L2CTL_L2E | MPC85xx_L2CTL_L2SRAM_ENTIRE
.long CONFIG_SYS_CCSRBAR_DEFAULT + ESDHCCTL /* Address: eSDHC DMA control */ diff --git a/arch/powerpc/cpu/mpc85xx/traps.c b/arch/powerpc/cpu/mpc85xx/traps.c index 97ed24a6eb4d..8f451b486248 100644 --- a/arch/powerpc/cpu/mpc85xx/traps.c +++ b/arch/powerpc/cpu/mpc85xx/traps.c @@ -260,7 +260,7 @@ void UnknownException(struct pt_regs *regs)
void ExtIntException(struct pt_regs *regs) { - volatile ccsr_pic_t *pic = (void *)(CONFIG_SYS_MPC8xxx_PIC_ADDR); + volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
uint vect;
diff --git a/arch/powerpc/cpu/mpc8xxx/cpu.c b/arch/powerpc/cpu/mpc8xxx/cpu.c index 0985fb2d0577..7f2019092296 100644 --- a/arch/powerpc/cpu/mpc8xxx/cpu.c +++ b/arch/powerpc/cpu/mpc8xxx/cpu.c @@ -104,7 +104,7 @@ static struct cpu_type cpu_type_list[] = { #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 static inline u32 init_type(u32 cluster, int init_id) { - ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; u32 type = in_be32(&gur->tp_ityp[idx]);
@@ -116,7 +116,7 @@ static inline u32 init_type(u32 cluster, int init_id)
u32 compute_ppc_cpumask(void) { - ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); int i = 0, count = 0; u32 cluster, type, mask = 0;
@@ -140,7 +140,7 @@ u32 compute_ppc_cpumask(void) #ifdef CONFIG_HETROGENOUS_CLUSTERS u32 compute_dsp_cpumask(void) { - ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); int i = CONFIG_DSP_CLUSTER_START, count = 0; u32 cluster, type, dsp_mask = 0;
@@ -163,7 +163,7 @@ u32 compute_dsp_cpumask(void)
int fsl_qoriq_dsp_core_to_cluster(unsigned int core) { - ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); int count = 0, i = CONFIG_DSP_CLUSTER_START; u32 cluster;
@@ -186,7 +186,7 @@ int fsl_qoriq_dsp_core_to_cluster(unsigned int core)
int fsl_qoriq_core_to_cluster(unsigned int core) { - ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); int i = 0, count = 0; u32 cluster;
@@ -235,7 +235,7 @@ struct cpu_type *identify_cpu(u32 ver) */ __weak u32 cpu_mask(void) { - ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; + ccsr_pic_t __iomem *pic = (void *)CFG_SYS_MPC8xxx_PIC_ADDR; struct cpu_type *cpu = gd->arch.cpu;
/* better to query feature reporting register than just assume 1 */ @@ -252,7 +252,7 @@ __weak u32 cpu_mask(void) #ifdef CONFIG_HETROGENOUS_CLUSTERS __weak u32 cpu_dsp_mask(void) { - ccsr_pic_t __iomem *pic = (void *)CONFIG_SYS_MPC8xxx_PIC_ADDR; + ccsr_pic_t __iomem *pic = (void *)CFG_SYS_MPC8xxx_PIC_ADDR; struct cpu_type *cpu = gd->arch.cpu;
/* better to query feature reporting register than just assume 1 */ diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index 198b5b10a52c..38ceb8a93749 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -301,7 +301,7 @@ void init_laws(void)
#ifdef CONFIG_SRIO_PCIE_BOOT_SLAVE /* check RCW to get which port is used for boot */ - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; u32 bootloc = in_be32(&gur->rcwsr[6]); /* * in SRIO or PCIE boot we need to set specail LAWs for diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index c73cf9319c87..62524a243365 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -33,12 +33,12 @@ #define _DEVDISR_SRIO2 FSL_CORENET_DEVDISR_SRIO2 #endif #define _DEVDISR_RMU FSL_CORENET_DEVDISR_RMU - #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR #elif defined(CONFIG_MPC85xx) #define _DEVDISR_SRIO1 MPC85xx_DEVDISR_SRIO #define _DEVDISR_SRIO2 MPC85xx_DEVDISR_SRIO #define _DEVDISR_RMU MPC85xx_DEVDISR_RMSG - #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR + #define CONFIG_SYS_MPC8xxx_GUTS_ADDR CFG_SYS_MPC85xx_GUTS_ADDR #elif defined(CONFIG_MPC86xx) #define _DEVDISR_SRIO1 MPC86xx_DEVDISR_SRIO #define _DEVDISR_SRIO2 MPC86xx_DEVDISR_SRIO diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index 7ced50c1d422..be55f99030e8 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -18,15 +18,15 @@ struct srio_liodn_id_table { #define SET_SRIO_LIODN_1(port, idA) \ { .id = { idA }, .num_ids = 1, .portid = port, \ .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \ - + CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ + + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ }
#define SET_SRIO_LIODN_2(port, idA, idB) \ { .id = { idA, idB }, .num_ids = 2, .portid = port, \ .reg_offset[0] = offsetof(ccsr_gur_t, rio##port##liodnr) \ - + CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ + + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ .reg_offset[1] = offsetof(ccsr_gur_t, rio##port##maintliodnr) \ - + CONFIG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ + + CFG_SYS_MPC85xx_GUTS_OFFSET + CONFIG_SYS_CCSRBAR, \ }
#define SET_SRIO_LIODN_BASE(port, id_a) \ @@ -90,42 +90,42 @@ extern void fdt_fixup_liodn(void *blob);
#define SET_GUTS_LIODN(compat, liodn, name, compatoff) \ SET_LIODN_ENTRY_1(compat, liodn, \ - offsetof(ccsr_gur_t, name) + CONFIG_SYS_MPC85xx_GUTS_OFFSET, \ + offsetof(ccsr_gur_t, name) + CFG_SYS_MPC85xx_GUTS_OFFSET, \ compatoff)
#define SET_USB_LIODN(usbNum, compat, liodn) \ SET_GUTS_LIODN(compat, liodn, usb##usbNum##liodnr,\ - CONFIG_SYS_MPC85xx_USB##usbNum##_OFFSET) + CFG_SYS_MPC85xx_USB##usbNum##_OFFSET)
#define SET_SATA_LIODN(sataNum, liodn) \ SET_GUTS_LIODN("fsl,pq-sata-v2", liodn, sata##sataNum##liodnr,\ - CONFIG_SYS_MPC85xx_SATA##sataNum##_OFFSET) + CFG_SYS_MPC85xx_SATA##sataNum##_OFFSET)
#define SET_PCI_LIODN(compat, pciNum, liodn) \ SET_GUTS_LIODN(compat, liodn, pex##pciNum##liodnr,\ - CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET) + CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
#define SET_PCI_LIODN_BASE(compat, pciNum, liodn) \ SET_LIODN_ENTRY_1(compat, liodn,\ - offsetof(ccsr_pcix_t, liodn_base) + CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\ - CONFIG_SYS_MPC85xx_PCIE##pciNum##_OFFSET) + offsetof(ccsr_pcix_t, liodn_base) + CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET,\ + CFG_SYS_MPC85xx_PCIE##pciNum##_OFFSET)
/* reg nodes for DMA start @ 0x300 */ #define SET_DMA_LIODN(dmaNum, compat, liodn) \ SET_GUTS_LIODN(compat, liodn, dma##dmaNum##liodnr,\ - CONFIG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300) + CFG_SYS_MPC85xx_DMA##dmaNum##_OFFSET + 0x300)
#define SET_SDHC_LIODN(sdhcNum, liodn) \ SET_GUTS_LIODN("fsl,esdhc", liodn, sdmmc##sdhcNum##liodnr,\ - CONFIG_SYS_MPC85xx_ESDHC_OFFSET) + CFG_SYS_MPC85xx_ESDHC_OFFSET)
#define SET_QE_LIODN(liodn) \ SET_GUTS_LIODN("fsl,qe", liodn, qeliodnr,\ - CONFIG_SYS_MPC85xx_QE_OFFSET) + CFG_SYS_MPC85xx_QE_OFFSET)
#define SET_TDM_LIODN(liodn) \ SET_GUTS_LIODN("fsl,tdm1.0", liodn, tdmliodnr,\ - CONFIG_SYS_MPC85xx_TDM_OFFSET) + CFG_SYS_MPC85xx_TDM_OFFSET)
#define SET_QMAN_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,qman", liodn, \ diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index c7313472de14..0bf5b9c2ba57 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -861,15 +861,15 @@ struct ccsr_gpio { }; };
-#define CONFIG_SYS_MPC8xxx_DDR_OFFSET (0x2000) +#define CFG_SYS_MPC8xxx_DDR_OFFSET (0x2000) #define CONFIG_SYS_FSL_DDR_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) -#define CONFIG_SYS_MPC83xx_DMA_OFFSET (0x8000) -#define CONFIG_SYS_MPC83xx_DMA_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_DMA_OFFSET) -#define CONFIG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000) -#define CONFIG_SYS_MPC83xx_ESDHC_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC83xx_ESDHC_OFFSET) + (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET) +#define CFG_SYS_MPC83xx_DMA_OFFSET (0x8000) +#define CFG_SYS_MPC83xx_DMA_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_DMA_OFFSET) +#define CFG_SYS_MPC83xx_ESDHC_OFFSET (0x2e000) +#define CFG_SYS_MPC83xx_ESDHC_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC83xx_ESDHC_OFFSET)
#define CONFIG_SYS_LBC_ADDR (&((immap_t *)CONFIG_SYS_IMMR)->im_lbc)
diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 7e88779227a4..7a7a7f2113c6 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -2437,9 +2437,9 @@ struct ccsr_pman { #define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000 #define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000 #endif -#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x8000 -#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x9000 -#define CONFIG_SYS_MPC8xxx_DDR3_OFFSET 0xA000 +#define CFG_SYS_MPC8xxx_DDR_OFFSET 0x8000 +#define CFG_SYS_MPC8xxx_DDR2_OFFSET 0x9000 +#define CFG_SYS_MPC8xxx_DDR3_OFFSET 0xA000 #define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 #define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 #ifdef CONFIG_SYS_FSL_SFP_VER_3_0 @@ -2457,36 +2457,36 @@ struct ccsr_pman { #define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 #define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000 #define CONFIG_SYS_FSL_PAMU_OFFSET 0x20000 -#define CONFIG_SYS_MPC85xx_DMA1_OFFSET 0x100000 -#define CONFIG_SYS_MPC85xx_DMA2_OFFSET 0x101000 -#define CONFIG_SYS_MPC85xx_DMA3_OFFSET 0x102000 -#define CONFIG_SYS_MPC85xx_DMA_OFFSET CONFIG_SYS_MPC85xx_DMA1_OFFSET -#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x110000 -#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 -#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x124000 -#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x124000 -#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0x130000 -#define CONFIG_SYS_MPC85xx_TDM_OFFSET 0x185000 -#define CONFIG_SYS_MPC85xx_QE_OFFSET 0x140000 +#define CFG_SYS_MPC85xx_DMA1_OFFSET 0x100000 +#define CFG_SYS_MPC85xx_DMA2_OFFSET 0x101000 +#define CFG_SYS_MPC85xx_DMA3_OFFSET 0x102000 +#define CFG_SYS_MPC85xx_DMA_OFFSET CFG_SYS_MPC85xx_DMA1_OFFSET +#define CFG_SYS_MPC85xx_ESPI_OFFSET 0x110000 +#define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x114000 +#define CFG_SYS_MPC85xx_LBC_OFFSET 0x124000 +#define CFG_SYS_MPC85xx_IFC_OFFSET 0x124000 +#define CFG_SYS_MPC85xx_GPIO_OFFSET 0x130000 +#define CFG_SYS_MPC85xx_TDM_OFFSET 0x185000 +#define CFG_SYS_MPC85xx_QE_OFFSET 0x140000 #define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \ !defined(CONFIG_ARCH_B4420) -#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x240000 -#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x250000 -#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x260000 -#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x270000 +#define CFG_SYS_MPC85xx_PCIE1_OFFSET 0x240000 +#define CFG_SYS_MPC85xx_PCIE2_OFFSET 0x250000 +#define CFG_SYS_MPC85xx_PCIE3_OFFSET 0x260000 +#define CFG_SYS_MPC85xx_PCIE4_OFFSET 0x270000 #else -#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 -#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x201000 -#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x202000 -#define CONFIG_SYS_MPC85xx_PCIE4_OFFSET 0x203000 +#define CFG_SYS_MPC85xx_PCIE1_OFFSET 0x200000 +#define CFG_SYS_MPC85xx_PCIE2_OFFSET 0x201000 +#define CFG_SYS_MPC85xx_PCIE3_OFFSET 0x202000 +#define CFG_SYS_MPC85xx_PCIE4_OFFSET 0x203000 #endif -#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x210000 -#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x211000 -#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000 -#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100 -#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x220000 -#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x221000 +#define CFG_SYS_MPC85xx_USB1_OFFSET 0x210000 +#define CFG_SYS_MPC85xx_USB2_OFFSET 0x211000 +#define CFG_SYS_MPC85xx_USB1_PHY_OFFSET 0x214000 +#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100 +#define CFG_SYS_MPC85xx_SATA1_OFFSET 0x220000 +#define CFG_SYS_MPC85xx_SATA2_OFFSET 0x221000 #define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 #define CONFIG_SYS_FSL_JR0_OFFSET 0x301000 #define CONFIG_SYS_SEC_MON_OFFSET 0x314000 @@ -2515,32 +2515,32 @@ struct ccsr_pman { #define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000 #define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000 #else -#define CONFIG_SYS_MPC85xx_ECM_OFFSET 0x0000 -#define CONFIG_SYS_MPC8xxx_DDR_OFFSET 0x2000 -#define CONFIG_SYS_MPC85xx_LBC_OFFSET 0x5000 -#define CONFIG_SYS_MPC8xxx_DDR2_OFFSET 0x6000 -#define CONFIG_SYS_MPC85xx_ESPI_OFFSET 0x7000 -#define CONFIG_SYS_MPC85xx_PCI1_OFFSET 0x8000 -#define CONFIG_SYS_MPC85xx_PCIX_OFFSET 0x8000 -#define CONFIG_SYS_MPC85xx_PCI2_OFFSET 0x9000 -#define CONFIG_SYS_MPC85xx_PCIX2_OFFSET 0x9000 -#define CONFIG_SYS_MPC85xx_PCIE1_OFFSET 0xa000 -#define CONFIG_SYS_MPC85xx_PCIE2_OFFSET 0x9000 +#define CFG_SYS_MPC85xx_ECM_OFFSET 0x0000 +#define CFG_SYS_MPC8xxx_DDR_OFFSET 0x2000 +#define CFG_SYS_MPC85xx_LBC_OFFSET 0x5000 +#define CFG_SYS_MPC8xxx_DDR2_OFFSET 0x6000 +#define CFG_SYS_MPC85xx_ESPI_OFFSET 0x7000 +#define CFG_SYS_MPC85xx_PCI1_OFFSET 0x8000 +#define CFG_SYS_MPC85xx_PCIX_OFFSET 0x8000 +#define CFG_SYS_MPC85xx_PCI2_OFFSET 0x9000 +#define CFG_SYS_MPC85xx_PCIX2_OFFSET 0x9000 +#define CFG_SYS_MPC85xx_PCIE1_OFFSET 0xa000 +#define CFG_SYS_MPC85xx_PCIE2_OFFSET 0x9000 #if defined(CONFIG_ARCH_P2020) -#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0x8000 +#define CFG_SYS_MPC85xx_PCIE3_OFFSET 0x8000 #else -#define CONFIG_SYS_MPC85xx_PCIE3_OFFSET 0xb000 +#define CFG_SYS_MPC85xx_PCIE3_OFFSET 0xb000 #endif -#define CONFIG_SYS_MPC85xx_GPIO_OFFSET 0xF000 -#define CONFIG_SYS_MPC85xx_SATA1_OFFSET 0x18000 -#define CONFIG_SYS_MPC85xx_SATA2_OFFSET 0x19000 -#define CONFIG_SYS_MPC85xx_IFC_OFFSET 0x1e000 -#define CONFIG_SYS_MPC85xx_L2_OFFSET 0x20000 -#define CONFIG_SYS_MPC85xx_DMA_OFFSET 0x21000 -#define CONFIG_SYS_MPC85xx_USB1_OFFSET 0x22000 -#define CONFIG_SYS_MPC85xx_USB2_OFFSET 0x23000 -#define CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000 -#define CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100 +#define CFG_SYS_MPC85xx_GPIO_OFFSET 0xF000 +#define CFG_SYS_MPC85xx_SATA1_OFFSET 0x18000 +#define CFG_SYS_MPC85xx_SATA2_OFFSET 0x19000 +#define CFG_SYS_MPC85xx_IFC_OFFSET 0x1e000 +#define CFG_SYS_MPC85xx_L2_OFFSET 0x20000 +#define CFG_SYS_MPC85xx_DMA_OFFSET 0x21000 +#define CFG_SYS_MPC85xx_USB1_OFFSET 0x22000 +#define CFG_SYS_MPC85xx_USB2_OFFSET 0x23000 +#define CFG_SYS_MPC85xx_USB1_PHY_OFFSET 0xE5000 +#define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0xE5100 #ifdef CONFIG_TSECV2 #define CONFIG_SYS_TSEC1_OFFSET 0xB0000 #elif defined(CONFIG_TSECV2_1) @@ -2549,7 +2549,7 @@ struct ccsr_pman { #define CONFIG_SYS_TSEC1_OFFSET 0x24000 #endif #define CONFIG_SYS_MDIO1_OFFSET 0x24000 -#define CONFIG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 +#define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 #if defined(CONFIG_ARCH_C29X) #define CONFIG_SYS_FSL_SEC_OFFSET 0x80000 #define CONFIG_SYS_FSL_JR0_OFFSET 0x81000 @@ -2557,8 +2557,8 @@ struct ccsr_pman { #define CONFIG_SYS_FSL_SEC_OFFSET 0x30000 #define CONFIG_SYS_FSL_JR0_OFFSET 0x31000 #endif -#define CONFIG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 -#define CONFIG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 +#define CFG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 +#define CFG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 #define CONFIG_SYS_SEC_MON_OFFSET 0xE6000 #define CONFIG_SYS_SFP_OFFSET 0xE7000 #define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000 @@ -2569,8 +2569,8 @@ struct ccsr_pman { #define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000 #endif
-#define CONFIG_SYS_MPC85xx_PIC_OFFSET 0x40000 -#define CONFIG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 +#define CFG_SYS_MPC85xx_PIC_OFFSET 0x40000 +#define CFG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 #define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000
#define CONFIG_SYS_FSL_CPC_ADDR \ @@ -2587,50 +2587,50 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET) #define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET) -#define CONFIG_SYS_MPC85xx_GUTS_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GUTS_OFFSET) +#define CFG_SYS_MPC85xx_GUTS_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GUTS_OFFSET) #define CONFIG_SYS_FSL_CORENET_CCM_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET) #define CONFIG_SYS_FSL_CORENET_CLK_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET) #define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET) -#define CONFIG_SYS_MPC85xx_ECM_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ECM_OFFSET) +#define CFG_SYS_MPC85xx_ECM_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ECM_OFFSET) #define CONFIG_SYS_FSL_DDR_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR_OFFSET) + (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET) #define CONFIG_SYS_FSL_DDR2_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR2_OFFSET) + (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR2_OFFSET) #define CONFIG_SYS_FSL_DDR3_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC8xxx_DDR3_OFFSET) + (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR3_OFFSET) #define CONFIG_SYS_LBC_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_LBC_OFFSET) + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_LBC_OFFSET) #define CONFIG_SYS_IFC_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_IFC_OFFSET) -#define CONFIG_SYS_MPC85xx_ESPI_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESPI_OFFSET) -#define CONFIG_SYS_MPC85xx_PCIX_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX_OFFSET) -#define CONFIG_SYS_MPC85xx_PCIX2_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIX2_OFFSET) -#define CONFIG_SYS_MPC85xx_GPIO_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_GPIO_OFFSET) -#define CONFIG_SYS_MPC85xx_SATA1_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA1_OFFSET) -#define CONFIG_SYS_MPC85xx_SATA2_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SATA2_OFFSET) -#define CONFIG_SYS_MPC85xx_L2_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_L2_OFFSET) -#define CONFIG_SYS_MPC85xx_DMA_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_DMA_OFFSET) -#define CONFIG_SYS_MPC85xx_ESDHC_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_ESDHC_OFFSET) -#define CONFIG_SYS_MPC8xxx_PIC_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET) -#define CONFIG_SYS_MPC85xx_SERDES1_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES1_OFFSET) -#define CONFIG_SYS_MPC85xx_SERDES2_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SERDES2_OFFSET) + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_IFC_OFFSET) +#define CFG_SYS_MPC85xx_ESPI_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESPI_OFFSET) +#define CFG_SYS_MPC85xx_PCIX_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIX_OFFSET) +#define CFG_SYS_MPC85xx_PCIX2_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIX2_OFFSET) +#define CFG_SYS_MPC85xx_GPIO_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GPIO_OFFSET) +#define CFG_SYS_MPC85xx_SATA1_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SATA1_OFFSET) +#define CFG_SYS_MPC85xx_SATA2_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SATA2_OFFSET) +#define CFG_SYS_MPC85xx_L2_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_L2_OFFSET) +#define CFG_SYS_MPC85xx_DMA_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_DMA_OFFSET) +#define CFG_SYS_MPC85xx_ESDHC_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ESDHC_OFFSET) +#define CFG_SYS_MPC8xxx_PIC_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PIC_OFFSET) +#define CFG_SYS_MPC85xx_SERDES1_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES1_OFFSET) +#define CFG_SYS_MPC85xx_SERDES2_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES2_OFFSET) #define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) #define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \ @@ -2639,14 +2639,14 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET) #define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET) -#define CONFIG_SYS_MPC85xx_USB1_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_OFFSET) -#define CONFIG_SYS_MPC85xx_USB2_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_OFFSET) -#define CONFIG_SYS_MPC85xx_USB1_PHY_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB1_PHY_OFFSET) -#define CONFIG_SYS_MPC85xx_USB2_PHY_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_USB2_PHY_OFFSET) +#define CFG_SYS_MPC85xx_USB1_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_OFFSET) +#define CFG_SYS_MPC85xx_USB2_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_OFFSET) +#define CFG_SYS_MPC85xx_USB1_PHY_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_PHY_OFFSET) +#define CFG_SYS_MPC85xx_USB2_PHY_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_PHY_OFFSET) #define CONFIG_SYS_FSL_SEC_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) #define CONFIG_SYS_FSL_JR0_ADDR \ @@ -2663,17 +2663,17 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET)
#define CONFIG_SYS_PCI1_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI1_OFFSET) + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI1_OFFSET) #define CONFIG_SYS_PCI2_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCI2_OFFSET) + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI2_OFFSET) #define CONFIG_SYS_PCIE1_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE1_OFFSET) + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE1_OFFSET) #define CONFIG_SYS_PCIE2_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE2_OFFSET) + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE2_OFFSET) #define CONFIG_SYS_PCIE3_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE3_OFFSET) + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE3_OFFSET) #define CONFIG_SYS_PCIE4_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PCIE4_OFFSET) + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCIE4_OFFSET)
#define CONFIG_SYS_SFP_ADDR \ (CONFIG_SYS_IMMR + CONFIG_SYS_SFP_OFFSET) @@ -2752,9 +2752,9 @@ struct dcsr_dcfg_regs { u8 res_524[0x1000 - 0x524]; /* 0x524 - 0x1000 */ };
-#define CONFIG_SYS_MPC85xx_SCFG \ - (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_SCFG_OFFSET) -#define CONFIG_SYS_MPC85xx_SCFG_OFFSET 0xfc000 +#define CFG_SYS_MPC85xx_SCFG \ + (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SCFG_OFFSET) +#define CFG_SYS_MPC85xx_SCFG_OFFSET 0xfc000 /* The supplement configuration unit register */ struct ccsr_scfg { u32 dpslpcr; /* 0x000 Deep Sleep Control register */ diff --git a/arch/powerpc/include/asm/mpc85xx_gpio.h b/arch/powerpc/include/asm/mpc85xx_gpio.h index feebe15caca8..0ed6beca387a 100644 --- a/arch/powerpc/include/asm/mpc85xx_gpio.h +++ b/arch/powerpc/include/asm/mpc85xx_gpio.h @@ -20,7 +20,7 @@ static inline void mpc85xx_gpio_set(unsigned int mask, unsigned int dir, unsigned int val) { - ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + ccsr_gpio_t *gpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
/* First mask off the unwanted parts of "dir" and "val" */ dir &= mask; @@ -56,7 +56,7 @@ static inline void mpc85xx_gpio_set_high(unsigned int gpios)
static inline unsigned int mpc85xx_gpio_get(unsigned int mask) { - ccsr_gpio_t *gpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + ccsr_gpio_t *gpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
/* Read the requested values */ return in_be32(&gpio->gpdat) & mask; diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index ad7235344021..3bd570a29c9b 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -28,7 +28,7 @@ #endif
#if defined(CONFIG_MPC85xx) -#define CONFIG_DCFG_ADDR CONFIG_SYS_MPC85xx_GUTS_ADDR +#define CONFIG_DCFG_ADDR CFG_SYS_MPC85xx_GUTS_ADDR #else #define CONFIG_DCFG_ADDR CONFIG_SYS_FSL_GUTS_ADDR #endif diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index 7a23d8f4c7c1..bc1b855aaed0 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -83,7 +83,7 @@ static u32 check_ie(struct fsl_secboot_img_priv *img)
int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]); u32 csf_flash_offset = csf_hdr_addr & ~(CONFIG_SYS_PBI_FLASH_BASE); u32 flash_addr, addr; diff --git a/board/freescale/common/mpc85xx_sleep.c b/board/freescale/common/mpc85xx_sleep.c index d2bb173c1833..71922aab4ef4 100644 --- a/board/freescale/common/mpc85xx_sleep.c +++ b/board/freescale/common/mpc85xx_sleep.c @@ -24,7 +24,7 @@ void __weak board_sleep_prepare(void)
bool is_warm_boot(void) { - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
if (in_be32(&gur->scrtsr[0]) & DCFG_CCSR_CRSTSR_WDRFR) return 1; @@ -46,7 +46,7 @@ static void dp_ddr_restore(void) { u64 *src, *dst; int i; - struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG; + struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_MPC85xx_SCFG;
/* get the address of ddr date from SPARECR3 */ src = (u64 *)(in_be32(&scfg->sparecr[2]) + DDR_BUFF_LEN - 8); @@ -80,7 +80,7 @@ int fsl_dp_resume(void) { u32 start_addr; void (*kernel_resume)(void); - struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_MPC85xx_SCFG; + struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_MPC85xx_SCFG;
if (!is_warm_boot()) return 0; diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index d2c9bbbfe993..3f5f33ebafbe 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -542,7 +542,7 @@ int adjust_vdd(ulong vdd_override) struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); #else ccsr_gur_t __iomem *gur = - (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); #endif u8 vid; u32 fusesr; diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 8886d8be3359..e4c951feb5ac 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -33,8 +33,8 @@ void local_bus_init(void);
int checkboard (void) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR);
/* PCI slot in USER bits CSR[6:7] by convention. */ uint pci_slot = get_pci_slot (); @@ -68,7 +68,7 @@ int checkboard (void) void local_bus_init(void) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); volatile fsl_lbc_t *lbc = LBC_BASE_ADDR;
uint clkdiv; diff --git a/board/freescale/p1010rdb/p1010rdb.c b/board/freescale/p1010rdb/p1010rdb.c index c796330f1915..c39df462e3bb 100644 --- a/board/freescale/p1010rdb/p1010rdb.c +++ b/board/freescale/p1010rdb/p1010rdb.c @@ -82,7 +82,7 @@ struct cpld_data {
int board_early_init_f(void) { - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; /* Clock configuration to access CPLD using IFC(GPCM) */ setbits_be32(&ifc.gregs->ifc_gcr, 1 << IFC_GCR_TBCTL_TRN_TIME_SHIFT); @@ -131,7 +131,7 @@ int board_early_init_r(void)
int config_board_mux(int ctrl_type) { - ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u8 tmp;
#if CONFIG_IS_ENABLED(DM_I2C) @@ -668,7 +668,7 @@ void board_reset(void)
int misc_init_r(void) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
if (hwconfig_subarg_cmp("fsl_p1010mux", "tdm_can", "can")) { clrbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_CAN1_TDM | diff --git a/board/freescale/p1010rdb/spl.c b/board/freescale/p1010rdb/spl.c index 88695002deb5..0db11f4c5f79 100644 --- a/board/freescale/p1010rdb/spl.c +++ b/board/freescale/p1010rdb/spl.c @@ -28,7 +28,7 @@ phys_size_t get_effective_memsize(void) void board_init_f(ulong bootflag) { u32 plat_ratio; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
console_init_f(); diff --git a/board/freescale/p1010rdb/spl_minimal.c b/board/freescale/p1010rdb/spl_minimal.c index a956c5af5b00..a262d5ca4af7 100644 --- a/board/freescale/p1010rdb/spl_minimal.c +++ b/board/freescale/p1010rdb/spl_minimal.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; void board_init_f(ulong bootflag) { u32 plat_ratio; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index b301491ef812..2999c85d0aed 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -149,7 +149,7 @@ void board_cpld_init(void) void board_gpio_init(void) { #ifdef CONFIG_QE - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); par_io_t *par_io = (par_io_t *) &(gur->qe_par_io);
/* Enable VSC7385 switch */ @@ -159,7 +159,7 @@ void board_gpio_init(void) setbits_be32(&par_io[GPIO_SLIC_PORT].cpdat, GPIO_SLIC_DATA); #else
- ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR);
/* * GPIO10 DDR Reset, open drain @@ -197,7 +197,7 @@ void board_gpio_init(void)
int board_early_init_f(void) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_SDHC_CD); #ifndef SDHC_WP_IS_GPIO @@ -227,7 +227,7 @@ int board_early_init_f(void) int checkboard(void) { struct cpld_data *cpld_data = (void *)(CONFIG_SYS_CPLD_BASE); - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u8 in, out, invert, io_config, val; int bus_num = CONFIG_SYS_SPD_BUS_NUM;
@@ -370,7 +370,7 @@ int board_eth_init(struct bd_info *bis) struct fsl_pq_mdio_info mdio_info; struct tsec_info_struct tsec_info[4]; ccsr_gur_t *gur __attribute__((unused)) = - (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); int num = 0;
#ifdef CONFIG_TSEC1 @@ -418,7 +418,7 @@ int board_eth_init(struct bd_info *bis) static void fix_max6370_watchdog(void *blob) { int off = fdt_node_offset_by_compatible(blob, -1, "maxim,max6370"); - ccsr_gpio_t *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + ccsr_gpio_t *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); u32 gpioval = in_be32(&pgpio->gpdat);
/* diff --git a/board/freescale/p1_p2_rdb_pc/spl.c b/board/freescale/p1_p2_rdb_pc/spl.c index eda84bf2b1fc..e7d4428d7c22 100644 --- a/board/freescale/p1_p2_rdb_pc/spl.c +++ b/board/freescale/p1_p2_rdb_pc/spl.c @@ -29,7 +29,7 @@ phys_size_t get_effective_memsize(void) void board_init_f(ulong bootflag) { u32 plat_ratio, bus_clk; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
/* * Call board_early_init_f() as early as possible as it workarounds diff --git a/board/freescale/p1_p2_rdb_pc/spl_minimal.c b/board/freescale/p1_p2_rdb_pc/spl_minimal.c index 72beeadf55c4..e467c7adc190 100644 --- a/board/freescale/p1_p2_rdb_pc/spl_minimal.c +++ b/board/freescale/p1_p2_rdb_pc/spl_minimal.c @@ -19,7 +19,7 @@ DECLARE_GLOBAL_DATA_PTR; void board_init_f(ulong bootflag) { u32 plat_ratio; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
#if defined(CONFIG_SYS_NAND_BR_PRELIM) && defined(CONFIG_SYS_NAND_OR_PRELIM) set_lbc_br(0, CONFIG_SYS_NAND_BR_PRELIM); diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 2a84e9bdf556..859ffc4935c8 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -66,7 +66,7 @@ int checkboard(void)
int board_early_init_f(void) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* board only uses the DDR_MCK0/1, so disable the DDR_MCK2/3 */ setbits_be32(&gur->ddrclkdr, 0x000f000f); @@ -81,7 +81,7 @@ int board_early_init_f(void)
void board_config_lanes_mux(void) { - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; int srds_prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
diff --git a/board/freescale/t102xrdb/eth_t102xrdb.c b/board/freescale/t102xrdb/eth_t102xrdb.c index 4f04d2ee06d6..be42efa5c764 100644 --- a/board/freescale/t102xrdb/eth_t102xrdb.c +++ b/board/freescale/t102xrdb/eth_t102xrdb.c @@ -33,7 +33,7 @@ int board_eth_init(struct bd_info *bis) struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; struct mii_dev *dev; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) & diff --git a/board/freescale/t102xrdb/spl.c b/board/freescale/t102xrdb/spl.c index af15da5427c7..3ba94fecaa24 100644 --- a/board/freescale/t102xrdb/spl.c +++ b/board/freescale/t102xrdb/spl.c @@ -29,7 +29,7 @@ phys_size_t get_effective_memsize(void) #define GPIO1_SD_SEL 0x00020000 int board_mmc_getcd(struct mmc *mmc) { - ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); u32 val = in_be32(&pgpio->gpdat);
/* GPIO1_14, 0: eMMC, 1: SD */ @@ -40,7 +40,7 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_getwp(struct mmc *mmc) { - ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); u32 val = in_be32(&pgpio->gpdat);
val &= GPIO1_SD_SEL; @@ -52,7 +52,7 @@ int board_mmc_getwp(struct mmc *mmc) void board_init_f(ulong bootflag) { u32 plat_ratio, sys_clk, ccb_clk; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); diff --git a/board/freescale/t102xrdb/t102xrdb.c b/board/freescale/t102xrdb/t102xrdb.c index 539a5c73444e..f777f5a2fe7f 100644 --- a/board/freescale/t102xrdb/t102xrdb.c +++ b/board/freescale/t102xrdb/t102xrdb.c @@ -49,7 +49,7 @@ int checkboard(void) { struct cpu_type *cpu = gd->arch.cpu; static const char *freq[3] = {"100.00MHZ", "125.00MHz", "156.25MHZ"}; - ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL; @@ -99,7 +99,7 @@ int checkboard(void) #ifdef CONFIG_TARGET_T1024RDB static void board_mux_lane(void) { - ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 srds_prtcl_s1; u8 reg = CPLD_READ(misc_ctl_status);
@@ -222,7 +222,7 @@ static void fdt_enable_nor(void *blob)
int board_mmc_getcd(struct mmc *mmc) { - ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); u32 val = in_be32(&pgpio->gpdat);
/* GPIO1_14, 0: eMMC, 1: SD/MMC */ @@ -233,7 +233,7 @@ int board_mmc_getcd(struct mmc *mmc)
int board_mmc_getwp(struct mmc *mmc) { - ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); + ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); u32 val = in_be32(&pgpio->gpdat);
val &= GPIO1_SD_SEL; @@ -243,8 +243,8 @@ int board_mmc_getwp(struct mmc *mmc)
static u32 t1023rdb_ctrl(u32 ctrl_type) { - ccsr_gpio_t __iomem *pgpio = (void *)(CONFIG_SYS_MPC85xx_GPIO_ADDR); - ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gpio_t __iomem *pgpio = (void *)(CFG_SYS_MPC85xx_GPIO_ADDR); + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 val; u8 tmp; int bus_num = I2C_PCA6408_BUS_NUM; @@ -274,7 +274,7 @@ static u32 t1023rdb_ctrl(u32 ctrl_type) setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); break; case GPIO3_GET_VERSION: - pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85xx_GPIO_ADDR + GPIO3_OFFSET); val = in_be32(&pgpio->gpdat); val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3; @@ -323,7 +323,7 @@ static u32 t1023rdb_ctrl(u32 ctrl_type) setbits_be32(&pgpio->gpdir, GPIO1_SD_SEL); break; case GPIO3_GET_VERSION: - pgpio = (ccsr_gpio_t *)(CONFIG_SYS_MPC85xx_GPIO_ADDR + pgpio = (ccsr_gpio_t *)(CFG_SYS_MPC85xx_GPIO_ADDR + GPIO3_OFFSET); val = in_be32(&pgpio->gpdat); val = ((val & GPIO3_BRD_VER_MASK) >> 26) & 0x3; diff --git a/board/freescale/t104xrdb/eth.c b/board/freescale/t104xrdb/eth.c index 3ae5d722aab3..bb6641b88a99 100644 --- a/board/freescale/t104xrdb/eth.c +++ b/board/freescale/t104xrdb/eth.c @@ -142,7 +142,7 @@ int board_eth_init(struct bd_info *bis) if (serdes_get_first_lane(FSL_SRDS_1, SGMII_FM1_DTSEC2) < 0) { /* Enable L2 On MAC2 using SCFG */ struct ccsr_scfg *scfg = (struct ccsr_scfg *) - CONFIG_SYS_MPC85xx_SCFG; + CFG_SYS_MPC85xx_SCFG;
out_be32(&scfg->esgmiiselcr, in_be32(&scfg->esgmiiselcr) | (0x80000000)); diff --git a/board/freescale/t104xrdb/spl.c b/board/freescale/t104xrdb/spl.c index dfaff1a9165c..c7fb4272c63b 100644 --- a/board/freescale/t104xrdb/spl.c +++ b/board/freescale/t104xrdb/spl.c @@ -33,7 +33,7 @@ void board_init_f(ulong bootflag) u32 porsr1, pinctl; u32 svr = get_svr(); #endif - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
#if defined(CONFIG_SPL_NAND_BOOT) && defined(CONFIG_A008044_WORKAROUND) if (IS_SVR_REV(svr, 1, 0)) { diff --git a/board/freescale/t104xrdb/t104xrdb.c b/board/freescale/t104xrdb/t104xrdb.c index 780043483dff..7d3fd291a019 100644 --- a/board/freescale/t104xrdb/t104xrdb.c +++ b/board/freescale/t104xrdb/t104xrdb.c @@ -93,7 +93,7 @@ int board_early_init_r(void)
int misc_init_r(void) { - ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) >> 24; diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index 2d7fc8bdda2e..dd1c35fa2015 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -189,7 +189,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, const char *phyconn; int off;
- ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_TARGET_T2080QDS serdes_corenet_t *srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; @@ -413,7 +413,7 @@ void fdt_fixup_board_enet(void *fdt) */ static void initialize_lane_to_slot(void) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CORENET2_RCWSR4_SRDS1_PRTCL;
@@ -459,7 +459,7 @@ int board_eth_init(struct bd_info *bis) int i, idx, lane, slot, interface; struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 rcwsr13 = in_be32(&gur->rcwsr[13]); u32 srds_s1;
diff --git a/board/freescale/t208xqds/spl.c b/board/freescale/t208xqds/spl.c index e934a3ca6f70..8b68329b9864 100644 --- a/board/freescale/t208xqds/spl.c +++ b/board/freescale/t208xqds/spl.c @@ -67,7 +67,7 @@ unsigned long get_board_ddr_clk(void) void board_init_f(ulong bootflag) { u32 plat_ratio, sys_clk, ccb_clk; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); diff --git a/board/freescale/t208xqds/t208xqds.c b/board/freescale/t208xqds/t208xqds.c index 1da3a714f27f..82710cf897b2 100644 --- a/board/freescale/t208xqds/t208xqds.c +++ b/board/freescale/t208xqds/t208xqds.c @@ -88,7 +88,7 @@ int i2c_multiplexer_select_vid_channel(u8 channel)
int brd_mux_lane_to_slot(void) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 srds_prtcl_s1;
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & diff --git a/board/freescale/t208xrdb/spl.c b/board/freescale/t208xrdb/spl.c index 60fe084bbb2a..3f9b1faa853e 100644 --- a/board/freescale/t208xrdb/spl.c +++ b/board/freescale/t208xrdb/spl.c @@ -27,7 +27,7 @@ phys_size_t get_effective_memsize(void) void board_init_f(ulong bootflag) { u32 plat_ratio, sys_clk, ccb_clk; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); diff --git a/board/freescale/t4rdb/eth.c b/board/freescale/t4rdb/eth.c index 34ffaa6aeb54..4041b3d9ac4c 100644 --- a/board/freescale/t4rdb/eth.c +++ b/board/freescale/t4rdb/eth.c @@ -43,7 +43,7 @@ int board_eth_init(struct bd_info *bis) struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; struct mii_dev *dev; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 srds_prtcl_s1, srds_prtcl_s2;
srds_prtcl_s1 = in_be32(&gur->rcwsr[4]) & diff --git a/board/freescale/t4rdb/spl.c b/board/freescale/t4rdb/spl.c index c7d5de35d58b..72d3b80b19b2 100644 --- a/board/freescale/t4rdb/spl.c +++ b/board/freescale/t4rdb/spl.c @@ -33,7 +33,7 @@ phys_size_t get_effective_memsize(void) void board_init_f(ulong bootflag) { u32 plat_ratio, sys_clk, ccb_clk; - ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR;
/* Memcpy existing GD at CONFIG_SPL_GD_ADDR */ memcpy((void *)CONFIG_SPL_GD_ADDR, (void *)gd, sizeof(gd_t)); diff --git a/board/keymile/kmcent2/kmcent2.c b/board/keymile/kmcent2/kmcent2.c index 44865384f653..758bd5b79ba1 100644 --- a/board/keymile/kmcent2/kmcent2.c +++ b/board/keymile/kmcent2/kmcent2.c @@ -45,7 +45,7 @@ int checkboard(void) int board_early_init_f(void) { struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL}; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); bool cpuwd_flag = false;
/* board specific IFC configuration: increased bus turnaround time */ @@ -221,8 +221,8 @@ EVENT_SPY(EVT_MISC_INIT_F, kmcent2_misc_init_f); int misc_init_r(void) { serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_MPC85xx_SCFG; - ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_MPC85xx_SCFG; + ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CFG_SYS_MPC85xx_GUTS_ADDR;
/* check SERDES bank 0 reference clock */ u32 actual = in_be32(®s->bank[USED_SRDS_BANK].pllcr0); diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index f9e1bc631648..e84f06b886cb 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -35,7 +35,7 @@ ulong flash_get_size (ulong base, int banknum);
int checkboard (void) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); char buf[64]; int f; int i = env_get_f("serial#", buf, sizeof(buf)); @@ -139,7 +139,7 @@ int misc_init_r (void) void local_bus_init (void) { volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - volatile ccsr_local_ecm_t *ecm = (void *)(CONFIG_SYS_MPC85xx_ECM_ADDR); + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_SYS_MPC85xx_ECM_ADDR); sys_info_t sysinfo; uint clkdiv; uint lbc_mhz; @@ -175,7 +175,7 @@ void local_bus_init (void) #ifdef CONFIG_BOARD_EARLY_INIT_R int board_early_init_r (void) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* set and reset the GPIO pin 2 which will reset the W83782G chip */ out_8((unsigned char*)&gur->gpoutdr, 0x3F ); diff --git a/board/xes/common/fsl_8xxx_clk.c b/board/xes/common/fsl_8xxx_clk.c index 20e88d43604f..c36b2afd50ed 100644 --- a/board/xes/common/fsl_8xxx_clk.c +++ b/board/xes/common/fsl_8xxx_clk.c @@ -13,7 +13,7 @@ unsigned long get_board_sys_clk(void) { #if defined(CONFIG_MPC85xx) - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); #elif defined(CONFIG_MPC86xx) immap_t *immap = (immap_t *)CONFIG_SYS_IMMR; volatile ccsr_gur_t *gur = &immap->im_gur; @@ -36,7 +36,7 @@ unsigned long get_board_sys_clk(void) */ unsigned long get_board_ddr_clk(void) { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 ddr_ratio = (in_be32(&gur->porpllsr) & 0x00003e00) >> 9;
if (ddr_ratio == 0x7) diff --git a/board/xes/common/fsl_8xxx_misc.c b/board/xes/common/fsl_8xxx_misc.c index b26810338f8f..9d921032eaff 100644 --- a/board/xes/common/fsl_8xxx_misc.c +++ b/board/xes/common/fsl_8xxx_misc.c @@ -28,7 +28,7 @@ int board_flash_wp_on(void) uint get_board_derivative(void) { #if defined(CONFIG_MPC85xx) - volatile ccsr_gur_t *gur = (void *)CONFIG_SYS_MPC85xx_GUTS_ADDR; + volatile ccsr_gur_t *gur = (void *)CFG_SYS_MPC85xx_GUTS_ADDR; #elif defined(CONFIG_MPC86xx) volatile immap_t *immap = (immap_t *)CONFIG_SYS_CCSRBAR; volatile ccsr_gur_t *gur = &immap->im_gur; diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c index d7b8064e5f10..9ed80d63ef05 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c @@ -21,7 +21,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR;
#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx) - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); uint svr; #endif
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index 1ed4d50cc743..47339c59737a 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -33,7 +33,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, int timeout; #ifdef CONFIG_SYS_FSL_ERRATUM_DDR111_DDR134 int timeout_save; - volatile ccsr_local_ecm_t *ecm = (void *)CONFIG_SYS_MPC85xx_ECM_ADDR; + volatile ccsr_local_ecm_t *ecm = (void *)CFG_SYS_MPC85xx_ECM_ADDR; unsigned int csn_bnds_backup = 0, cs_sa, cs_ea, *csn_bnds_t; int csn = -1; #endif diff --git a/drivers/dma/fsl_dma.c b/drivers/dma/fsl_dma.c index 1864b5d88b08..cd78e45d888a 100644 --- a/drivers/dma/fsl_dma.c +++ b/drivers/dma/fsl_dma.c @@ -24,9 +24,9 @@
#if defined(CONFIG_MPC83xx) -dma83xx_t *dma_base = (void *)(CONFIG_SYS_MPC83xx_DMA_ADDR); +dma83xx_t *dma_base = (void *)(CFG_SYS_MPC83xx_DMA_ADDR); #elif defined(CONFIG_MPC85xx) -ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC85xx_DMA_ADDR); +ccsr_dma_t *dma_base = (void *)(CFG_SYS_MPC85xx_DMA_ADDR); #elif defined(CONFIG_MPC86xx) ccsr_dma_t *dma_base = (void *)(CONFIG_SYS_MPC86xx_DMA_ADDR); #else diff --git a/drivers/net/fm/b4860.c b/drivers/net/fm/b4860.c index e622d86ba38c..1c5543e3c878 100644 --- a/drivers/net/fm/b4860.c +++ b/drivers/net/fm/b4860.c @@ -25,7 +25,7 @@ u32 port_to_devdisr[] = {
static int is_device_disabled(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2; @@ -33,14 +33,14 @@ static int is_device_disabled(enum fm_port port)
void fman_disable_port(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]); }
void fman_enable_port(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); } @@ -51,7 +51,7 @@ phy_interface_t fman_port_enet_if(enum fm_port port) u32 serdes2_prtcl; char buffer[HWCONFIG_BUFFER_SIZE]; char *buf = NULL; - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); #endif
if (is_device_disabled(port)) diff --git a/drivers/net/fm/p1023.c b/drivers/net/fm/p1023.c index c9b85fc8a8a6..9013b276bc95 100644 --- a/drivers/net/fm/p1023.c +++ b/drivers/net/fm/p1023.c @@ -16,7 +16,7 @@ static u32 port_to_devdisr[] = {
static int is_device_disabled(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 devdisr = in_be32(&gur->devdisr);
return port_to_devdisr[port] & devdisr; @@ -24,7 +24,7 @@ static int is_device_disabled(enum fm_port port)
void fman_disable_port(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* don't allow disabling of DTSEC1 as its needed for MDIO */ if (port == FM1_DTSEC1) @@ -35,14 +35,14 @@ void fman_disable_port(enum fm_port port)
void fman_enable_port(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr, port_to_devdisr[port]); }
phy_interface_t fman_port_enet_if(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 pordevsr = in_be32(&gur->pordevsr);
if (is_device_disabled(port)) diff --git a/drivers/net/fm/p4080.c b/drivers/net/fm/p4080.c index 577ee22cb0ad..7ad993221f78 100644 --- a/drivers/net/fm/p4080.c +++ b/drivers/net/fm/p4080.c @@ -24,7 +24,7 @@ static u32 port_to_devdisr[] = {
static int is_device_disabled(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2; @@ -32,7 +32,7 @@ static int is_device_disabled(enum fm_port port)
void fman_disable_port(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* don't allow disabling of DTSEC1 as its needed for MDIO */ if (port == FM1_DTSEC1) @@ -43,14 +43,14 @@ void fman_disable_port(enum fm_port port)
void fman_enable_port(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); }
phy_interface_t fman_port_enet_if(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port)) diff --git a/drivers/net/fm/p5020.c b/drivers/net/fm/p5020.c index 8ecc48276a91..f931491b1120 100644 --- a/drivers/net/fm/p5020.c +++ b/drivers/net/fm/p5020.c @@ -20,7 +20,7 @@ static u32 port_to_devdisr[] = {
static int is_device_disabled(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2; @@ -28,7 +28,7 @@ static int is_device_disabled(enum fm_port port)
void fman_disable_port(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* don't allow disabling of DTSEC1 as its needed for MDIO */ if (port == FM1_DTSEC1) @@ -39,14 +39,14 @@ void fman_disable_port(enum fm_port port)
void fman_enable_port(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); }
phy_interface_t fman_port_enet_if(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port)) diff --git a/drivers/net/fm/p5040.c b/drivers/net/fm/p5040.c index 3a1494d1315f..ef9f4bcce4dd 100644 --- a/drivers/net/fm/p5040.c +++ b/drivers/net/fm/p5040.c @@ -26,7 +26,7 @@ u32 port_to_devdisr[] = {
static int is_device_disabled(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2; @@ -34,7 +34,7 @@ static int is_device_disabled(enum fm_port port)
void fman_disable_port(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* don't allow disabling of DTSEC1 as its needed for MDIO */ if (port == FM1_DTSEC1) @@ -45,14 +45,14 @@ void fman_disable_port(enum fm_port port)
void fman_enable_port(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); }
phy_interface_t fman_port_enet_if(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 rcwsr11 = in_be32(&gur->rcwsr[11]);
if (is_device_disabled(port)) diff --git a/drivers/net/fm/t1024.c b/drivers/net/fm/t1024.c index 7110fb4fb116..70ab4610cdf6 100644 --- a/drivers/net/fm/t1024.c +++ b/drivers/net/fm/t1024.c @@ -20,7 +20,7 @@ u32 port_to_devdisr[] = {
static int is_device_disabled(enum fm_port port) { - ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2; @@ -28,14 +28,14 @@ static int is_device_disabled(enum fm_port port)
void fman_disable_port(enum fm_port port) { - ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]); }
phy_interface_t fman_port_enet_if(enum fm_port port) { - ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port)) diff --git a/drivers/net/fm/t1040.c b/drivers/net/fm/t1040.c index 192f1c6c81e7..5c260bed7fd5 100644 --- a/drivers/net/fm/t1040.c +++ b/drivers/net/fm/t1040.c @@ -11,7 +11,7 @@
phy_interface_t fman_port_enet_if(enum fm_port port) { - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
/* handle RGMII first */ diff --git a/drivers/net/fm/t2080.c b/drivers/net/fm/t2080.c index bfbd8de9cf14..6174934d2b81 100644 --- a/drivers/net/fm/t2080.c +++ b/drivers/net/fm/t2080.c @@ -28,7 +28,7 @@ u32 port_to_devdisr[] = {
static int is_device_disabled(enum fm_port port) { - ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2; @@ -36,14 +36,14 @@ static int is_device_disabled(enum fm_port port)
void fman_disable_port(enum fm_port port) { - ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]); }
phy_interface_t fman_port_enet_if(enum fm_port port) { - ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port)) diff --git a/drivers/net/fm/t4240.c b/drivers/net/fm/t4240.c index ba7b86282fbb..f0a02bfe457f 100644 --- a/drivers/net/fm/t4240.c +++ b/drivers/net/fm/t4240.c @@ -35,7 +35,7 @@ u32 port_to_devdisr[] = {
static int is_device_disabled(enum fm_port port) { - ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2; @@ -43,21 +43,21 @@ static int is_device_disabled(enum fm_port port)
void fman_disable_port(enum fm_port port) { - ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]); }
void fman_enable_port(enum fm_port port) { - ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR);
clrbits_be32(&gur->devdisr2, port_to_devdisr[port]); }
phy_interface_t fman_port_enet_if(enum fm_port port) { - ccsr_gur_t *gur = (void __iomem *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port)) diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 8342c3389c15..2799ef374d26 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -469,7 +469,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware) #ifdef CONFIG_ARCH_LS1021A struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; #else - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); #endif #endif if (!firmware) { @@ -609,7 +609,7 @@ int u_qe_upload_firmware(const struct qe_firmware *firmware) #ifdef CONFIG_ARCH_LS1021A struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; #else - ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); #endif #endif if (!firmware) { @@ -718,7 +718,7 @@ int u_qe_firmware_resume(const struct qe_firmware *firmware, qe_map_t *qe_immrr) const u32 *code; #ifdef CONFIG_DEEP_SLEEP #ifdef CONFIG_PPC - ccsr_gur_t __iomem *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); #else struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; #endif diff --git a/drivers/qe/uec.c b/drivers/qe/uec.c index c4bd5c4a147f..310887964352 100644 --- a/drivers/qe/uec.c +++ b/drivers/qe/uec.c @@ -562,7 +562,7 @@ static void phy_change(struct eth_device *dev) struct uec_priv *uec = (struct uec_priv *)dev->priv;
#if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR);
/* QE9 and QE12 need to be set for enabling QE MII management signals */ setbits_be32(&gur->pmuxcr, MPC85xx_PMUXCR_QE9); @@ -1194,7 +1194,7 @@ static int uec_init(struct eth_device *dev, struct bd_info *bd) int err, i; struct phy_info *curphy; #if defined(CONFIG_ARCH_P1021) || defined(CONFIG_ARCH_P1025) - ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); #endif
uec = (struct uec_priv *)dev->priv; diff --git a/drivers/spi/fsl_espi.c b/drivers/spi/fsl_espi.c index c7a692623fb9..b1d964d79d0c 100644 --- a/drivers/spi/fsl_espi.c +++ b/drivers/spi/fsl_espi.c @@ -390,7 +390,7 @@ struct spi_slave *spi_setup_slave(unsigned int bus, unsigned int cs, if (!fsl) return NULL;
- fsl->espi = (void *)(CONFIG_SYS_MPC85xx_ESPI_ADDR); + fsl->espi = (void *)(CFG_SYS_MPC85xx_ESPI_ADDR); fsl->mode = mode; fsl->max_transfer_length = ESPI_MAX_DATA_TRANSFER_LEN; fsl->speed_hz = max_hz; diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index eb7e94ec1882..2529c9380dbb 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -216,7 +216,7 @@
#ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC_PIN_MUX -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC83xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC83xx_ESDHC_ADDR #endif
/* diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 2c49326484ff..03b823db0e18 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -392,7 +392,7 @@ extern unsigned long get_sdram_size(void); #endif /* CONFIG_TSEC_ENET */
#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR #endif
/* diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index 135b9907fcd6..c2c03c82eb10 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -308,7 +308,7 @@ #endif
#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR #endif
/* diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index b730d176ab66..2366b2abdca4 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -365,7 +365,7 @@ * SDHC */ #ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR #endif
/* Qman/Bman */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 5a2ae8798f3f..148c9c425d80 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -346,7 +346,7 @@ */
#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR #endif
/* Qman/Bman */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 75ef2894faa3..5e54a1fe66e5 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -422,7 +422,7 @@ * SDHC */ #ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR #endif
/* diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index b61b40b6271a..49d6eaf79c8e 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -379,7 +379,7 @@ * SDHC */ #ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR #endif
/* diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 836a93219ee6..493c195aa607 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -382,7 +382,7 @@ */
#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR #endif
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index 428b8483e738..db4aa81bbbc4 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -417,7 +417,7 @@ */
#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CONFIG_SYS_MPC85xx_ESDHC_ADDR +#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR #endif
/* diff --git a/include/post.h b/include/post.h index a07a6bc5e252..ec03556e917e 100644 --- a/include/post.h +++ b/include/post.h @@ -27,7 +27,7 @@
#elif defined (CONFIG_MPC85xx) #include <asm/immap_85xx.h> -#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CONFIG_SYS_MPC85xx_PIC_OFFSET + \ +#define _POST_WORD_ADDR (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PIC_OFFSET + \ offsetof(ccsr_pic_t, tfrr)) #endif
On Fri, 28 Oct 2022 at 18:30, Tom Rini trini@konsulko.com wrote:
Migrate all of COFIG_SYS_MPC* to the CFG_SYS namespace.
Signed-off-by: Tom Rini trini@konsulko.com
arch/powerpc/cpu/mpc85xx/bsc9132_serdes.c | 2 +- arch/powerpc/cpu/mpc85xx/c29x_serdes.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu.c | 8 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 22 +- arch/powerpc/cpu/mpc85xx/cpu_init_early.c | 4 +- arch/powerpc/cpu/mpc85xx/fdt.c | 6 +- .../powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 4 +- arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 10 +-
Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace.
Signed-off-by: Tom Rini trini@konsulko.com --- README | 8 +- arch/arm/cpu/armv7/ls102xa/clock.c | 4 +- arch/arm/cpu/armv7/ls102xa/cpu.c | 10 +- arch/arm/cpu/armv7/ls102xa/fdt.c | 4 +- arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c | 8 +- arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c | 20 +- arch/arm/cpu/armv7/ls102xa/psci.S | 16 +- arch/arm/cpu/armv7/ls102xa/soc.c | 8 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 48 ++-- arch/arm/cpu/armv8/fsl-layerscape/fdt.c | 10 +- .../armv8/fsl-layerscape/fsl_lsch2_serdes.c | 14 +- .../armv8/fsl-layerscape/fsl_lsch2_speed.c | 4 +- .../armv8/fsl-layerscape/fsl_lsch3_serdes.c | 20 +- .../armv8/fsl-layerscape/fsl_lsch3_speed.c | 10 +- arch/arm/cpu/armv8/fsl-layerscape/icid.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S | 4 +- .../cpu/armv8/fsl-layerscape/ls1088a_serdes.c | 2 +- arch/arm/cpu/armv8/fsl-layerscape/mp.c | 10 +- arch/arm/cpu/armv8/fsl-layerscape/ppa.c | 4 +- arch/arm/cpu/armv8/fsl-layerscape/soc.c | 36 +-- .../include/asm/arch-fsl-layerscape/config.h | 28 +-- .../arm/include/asm/arch-fsl-layerscape/cpu.h | 6 +- .../asm/arch-fsl-layerscape/fsl_icid.h | 26 +-- .../asm/arch-fsl-layerscape/immap_lsch2.h | 48 ++-- .../asm/arch-fsl-layerscape/immap_lsch3.h | 60 ++--- arch/arm/include/asm/arch-imx8/imx-regs.h | 2 +- arch/arm/include/asm/arch-imx8m/imx-regs.h | 12 +- arch/arm/include/asm/arch-ls102xa/config.h | 24 +- .../asm/arch-ls102xa/ls102xa_stream_id.h | 18 +- arch/arm/include/asm/arch-mx6/imx-regs.h | 12 +- arch/arm/include/asm/arch-mx7/imx-regs.h | 12 +- arch/arm/include/asm/arch-mx7ulp/imx-regs.h | 12 +- arch/arm/mach-imx/cmd_dek.c | 2 +- arch/arm/mach-imx/cmd_mfgprot.c | 2 +- arch/arm/mach-imx/mx7/clock.c | 4 +- arch/arm/mach-imx/mx7ulp/clock.c | 4 +- arch/arm/mach-imx/speed.c | 12 +- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 2 +- arch/powerpc/cpu/mpc85xx/cpu.c | 12 +- arch/powerpc/cpu/mpc85xx/cpu_init.c | 14 +- arch/powerpc/cpu/mpc85xx/fdt.c | 10 +- .../powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c | 24 +- arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c | 10 +- arch/powerpc/cpu/mpc85xx/liodn.c | 14 +- arch/powerpc/cpu/mpc85xx/mp.c | 4 +- arch/powerpc/cpu/mpc85xx/speed.c | 4 +- arch/powerpc/cpu/mpc85xx/start.S | 2 +- arch/powerpc/cpu/mpc8xxx/law.c | 2 +- arch/powerpc/cpu/mpc8xxx/srio.c | 8 +- arch/powerpc/include/asm/config_mpc85xx.h | 81 ++++--- arch/powerpc/include/asm/fsl_liodn.h | 56 ++--- arch/powerpc/include/asm/immap_83xx.h | 2 +- arch/powerpc/include/asm/immap_85xx.h | 212 +++++++++--------- board/advantech/imx8mp_rsb3720a1/spl.c | 2 +- board/advantech/imx8qm_rom7720_a1/spl.c | 4 +- board/bosch/acc/acc.c | 2 +- board/compulab/cl-som-imx7/cl-som-imx7.c | 2 +- board/compulab/cm_fx6/cm_fx6.c | 2 +- board/congatec/cgtqmx8/cgtqmx8.c | 4 +- board/freescale/common/arm_sleep.c | 8 +- board/freescale/common/fsl_chain_of_trust.c | 2 +- board/freescale/common/fsl_validate.c | 4 +- board/freescale/common/ls102xa_stream_id.c | 2 +- board/freescale/common/ns_access.c | 2 +- board/freescale/common/vid.c | 2 +- board/freescale/imx8mq_evk/spl.c | 2 +- board/freescale/ls1012aqds/eth.c | 2 +- board/freescale/ls1012aqds/ls1012aqds.c | 2 +- board/freescale/ls1012ardb/eth.c | 2 +- board/freescale/ls1021aiot/ls1021aiot.c | 6 +- board/freescale/ls1021aqds/ls1021aqds.c | 8 +- board/freescale/ls1021atsn/ls1021atsn.c | 4 +- board/freescale/ls1021atwr/ls1021atwr.c | 6 +- board/freescale/ls1043aqds/eth.c | 4 +- board/freescale/ls1043aqds/ls1043aqds.c | 10 +- board/freescale/ls1043ardb/eth.c | 2 +- board/freescale/ls1043ardb/ls1043ardb.c | 4 +- board/freescale/ls1046afrwy/eth.c | 4 +- board/freescale/ls1046afrwy/ls1046afrwy.c | 2 +- board/freescale/ls1046aqds/eth.c | 2 +- board/freescale/ls1046aqds/ls1046aqds.c | 10 +- board/freescale/ls1046ardb/eth.c | 4 +- board/freescale/ls1046ardb/ls1046ardb.c | 4 +- board/freescale/ls1088a/eth_ls1088aqds.c | 14 +- board/freescale/ls1088a/eth_ls1088ardb.c | 6 +- board/freescale/ls1088a/ls1088a.c | 2 +- board/freescale/ls2080aqds/eth.c | 16 +- board/freescale/ls2080ardb/eth_ls2080rdb.c | 6 +- board/freescale/ls2080ardb/ls2080ardb.c | 4 +- board/freescale/lx2160a/eth_lx2160aqds.c | 12 +- board/freescale/lx2160a/eth_lx2160ardb.c | 6 +- board/freescale/lx2160a/eth_lx2162aqds.c | 12 +- board/freescale/lx2160a/lx2160a.c | 4 +- board/freescale/mx53loco/mx53loco.c | 2 +- board/freescale/p2041rdb/p2041rdb.c | 2 +- board/freescale/t208xqds/eth_t208xqds.c | 2 +- board/google/imx8mq_phanbell/spl.c | 2 +- board/keymile/kmcent2/kmcent2.c | 2 +- .../keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c | 4 +- board/kontron/pitx_imx8m/spl.c | 2 +- board/kontron/sl-mx6ul/spl.c | 2 +- board/liebherr/mccmon6/spl.c | 4 +- board/myir/mys_6ulx/spl.c | 2 +- board/phytec/pcl063/spl.c | 2 +- board/purism/librem5/spl.c | 2 +- board/ronetix/imx8mq-cm/spl.c | 2 +- board/seeed/npi_imx6ull/spl.c | 2 +- board/socrates/sdram.c | 2 +- board/toradex/apalis_imx6/apalis_imx6.c | 2 +- board/toradex/colibri_imx6/colibri_imx6.c | 2 +- board/traverse/ten64/ten64.c | 2 +- board/variscite/dart_6ul/spl.c | 2 +- board/wandboard/spl.c | 4 +- cmd/blob.c | 2 +- drivers/crypto/fsl/jobdesc.c | 6 +- drivers/crypto/fsl/jr.c | 8 +- drivers/crypto/fsl/sec.c | 2 +- drivers/ddr/fsl/arm_ddr_gen3.c | 10 +- drivers/ddr/fsl/ctrl_regs.c | 2 +- drivers/ddr/fsl/fsl_ddr_gen4.c | 10 +- drivers/ddr/fsl/fsl_mmdc.c | 2 +- drivers/ddr/fsl/main.c | 12 +- drivers/ddr/fsl/mpc85xx_ddr_gen1.c | 4 +- drivers/ddr/fsl/mpc85xx_ddr_gen2.c | 2 +- drivers/ddr/fsl/mpc85xx_ddr_gen3.c | 10 +- drivers/ddr/fsl/util.c | 26 +-- drivers/misc/fsl_devdis.c | 2 +- drivers/misc/fsl_portals.c | 8 +- drivers/mmc/fsl_esdhc.c | 2 +- drivers/mmc/fsl_esdhc_imx.c | 2 +- drivers/net/fm/eth.c | 2 +- drivers/net/fm/fm.c | 2 +- drivers/net/fm/init.c | 6 +- drivers/net/fm/ls1043.c | 6 +- drivers/net/fm/ls1046.c | 6 +- drivers/net/ldpaa_eth/ls1088a.c | 8 +- drivers/net/ldpaa_eth/ls2080a.c | 6 +- drivers/net/ldpaa_eth/lx2160a.c | 8 +- drivers/net/pfe_eth/pfe_eth.c | 2 +- drivers/net/pfe_eth/pfe_mdio.c | 2 +- drivers/pci/pcie_fsl.c | 2 +- drivers/power/power_fsl.c | 2 +- drivers/qe/qe.c | 8 +- include/configs/MPC837XERDB.h | 2 +- include/configs/P1010RDB.h | 2 +- include/configs/P2041RDB.h | 2 +- include/configs/T102xRDB.h | 2 +- include/configs/T104xRDB.h | 2 +- include/configs/T208xQDS.h | 2 +- include/configs/T208xRDB.h | 2 +- include/configs/T4240RDB.h | 2 +- include/configs/apalis-imx8.h | 4 +- include/configs/apalis_imx6.h | 4 +- include/configs/aristainetos2.h | 4 +- include/configs/cgtqmx8.h | 4 +- include/configs/cl-som-imx7.h | 4 +- include/configs/cm_fx6.h | 4 +- include/configs/colibri-imx6ull.h | 4 +- include/configs/colibri-imx8x.h | 4 +- include/configs/colibri_imx6.h | 4 +- include/configs/colibri_imx7.h | 6 +- include/configs/dart_6ul.h | 6 +- include/configs/dh_imx6.h | 4 +- include/configs/display5.h | 4 +- include/configs/el6x_common.h | 4 +- include/configs/embestmx6boards.h | 6 +- include/configs/ge_bx50v3.h | 2 +- include/configs/gw_ventana.h | 2 +- include/configs/imx6_logic.h | 4 +- include/configs/imx6q-bosch-acc.h | 6 +- include/configs/imx7-cm.h | 4 +- include/configs/imx8mm-cl-iot-gate.h | 4 +- include/configs/imx8mm_data_modul_edm_sbc.h | 4 +- include/configs/imx8mm_icore_mx8mm.h | 4 +- include/configs/imx8mn_bsh_smm_s2pro.h | 2 +- include/configs/imx8mn_var_som.h | 2 +- include/configs/imx8mp_dhcom_pdk2.h | 4 +- include/configs/imx8mp_rsb3720.h | 4 +- include/configs/imx8mq_cm.h | 4 +- include/configs/imx8mq_evk.h | 4 +- include/configs/imx8mq_phanbell.h | 4 +- include/configs/imx8qm_rom7720.h | 4 +- include/configs/imx93_evk.h | 2 +- include/configs/kontron-sl-mx6ul.h | 4 +- include/configs/kontron_pitx_imx8m.h | 4 +- include/configs/kontron_sl28.h | 4 +- include/configs/librem5.h | 4 +- include/configs/liteboard.h | 2 +- include/configs/ls1012a_common.h | 4 +- include/configs/ls1012afrwy.h | 2 +- include/configs/ls1028a_common.h | 4 +- include/configs/ls1043a_common.h | 2 +- include/configs/ls1046a_common.h | 2 +- include/configs/ls1046afrwy.h | 2 +- include/configs/ls1046ardb.h | 2 +- include/configs/ls1088a_common.h | 4 +- include/configs/ls2080a_common.h | 2 +- include/configs/lx2160a_common.h | 2 +- include/configs/m53menlo.h | 2 +- include/configs/mccmon6.h | 4 +- include/configs/mx51evk.h | 2 +- include/configs/mx53cx9020.h | 2 +- include/configs/mx53loco.h | 4 +- include/configs/mx6cuboxi.h | 2 +- include/configs/mx6sabre_common.h | 2 +- include/configs/mx6sabreauto.h | 2 +- include/configs/mx6sabresd.h | 2 +- include/configs/mx6slevk.h | 4 +- include/configs/mx6sllevk.h | 4 +- include/configs/mx6sxsabreauto.h | 4 +- include/configs/mx6sxsabresd.h | 2 +- include/configs/mx6ul_14x14_evk.h | 6 +- include/configs/mx6ullevk.h | 4 +- include/configs/mys_6ulx.h | 4 +- include/configs/nitrogen6x.h | 4 +- include/configs/novena.h | 4 +- include/configs/npi_imx6ull.h | 4 +- include/configs/p1_p2_rdb_pc.h | 2 +- include/configs/pcl063.h | 4 +- include/configs/pcl063_ull.h | 4 +- include/configs/pico-imx6.h | 2 +- include/configs/pico-imx6ul.h | 2 +- include/configs/pico-imx7d.h | 4 +- include/configs/pico-imx8mq.h | 4 +- include/configs/smegw01.h | 2 +- include/configs/somlabs_visionsom_6ull.h | 4 +- include/configs/tqma6.h | 2 +- include/configs/udoo.h | 2 +- include/configs/udoo_neo.h | 2 +- include/configs/usbarmory.h | 2 +- include/configs/vf610twr.h | 2 +- include/configs/vining_2000.h | 2 +- include/configs/wandboard.h | 4 +- include/configs/warp7.h | 4 +- include/configs/xpress.h | 2 +- include/fm_eth.h | 28 +-- include/fsl_sec.h | 4 +- 237 files changed, 862 insertions(+), 863 deletions(-)
diff --git a/README b/README index edbcc02444a9..db4cb2fe24b8 100644 --- a/README +++ b/README @@ -298,7 +298,7 @@ The following options need to be configured:
Enables a workaround for erratum A004510. If set, then CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV and - CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set. + CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY must be set.
CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV CONFIG_SYS_FSL_ERRATUM_A004510_SVR_REV2 (optional) @@ -314,7 +314,7 @@ The following options need to be configured: See Freescale App Note 4493 for more information about this erratum.
- CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY + CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY
This is the value to write into CCSR offset 0x18600 according to the A004510 workaround. @@ -330,7 +330,7 @@ The following options need to be configured: Freescale DDR driver in use. This type of DDR controller is found in mpc83xx, mpc85xx as well as some ARM core SoCs.
- CONFIG_SYS_FSL_DDR_ADDR + CFG_SYS_FSL_DDR_ADDR Freescale DDR memory-mapped register base.
CONFIG_SYS_FSL_IFC_CLK_DIV @@ -339,7 +339,7 @@ The following options need to be configured: CONFIG_SYS_FSL_LBC_CLK_DIV Defines divider of platform clock(clock input to eLBC controller).
- CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY + CFG_SYS_FSL_DDR_SDRAM_BASE_PHY Physical address from the view of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for all Power SoCs. But it could be different for ARM SoCs. diff --git a/arch/arm/cpu/armv7/ls102xa/clock.c b/arch/arm/cpu/armv7/ls102xa/clock.c index 86b5b21ef862..4e1fe281201f 100644 --- a/arch/arm/cpu/armv7/ls102xa/clock.c +++ b/arch/arm/cpu/armv7/ls102xa/clock.c @@ -15,8 +15,8 @@ DECLARE_GLOBAL_DATA_PTR;
void get_sys_info(struct sys_info *sys_info) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_LS1_CLK_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); + struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_LS1_CLK_ADDR); unsigned int cpu; const u8 core_cplx_pll[6] = { [0] = 0, /* CC1 PPL / 1 */ diff --git a/arch/arm/cpu/armv7/ls102xa/cpu.c b/arch/arm/cpu/armv7/ls102xa/cpu.c index 0b3e3b206411..d530e0655bc2 100644 --- a/arch/arm/cpu/armv7/ls102xa/cpu.c +++ b/arch/arm/cpu/armv7/ls102xa/cpu.c @@ -228,7 +228,7 @@ void enable_caches(void)
uint get_svr(void) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
return in_be32(&gur->svr); } @@ -237,7 +237,7 @@ uint get_svr(void) int print_cpuinfo(void) { char buf1[32], buf2[32]; - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); unsigned int svr, major, minor, ver, i;
svr = in_be32(&gur->svr); @@ -316,7 +316,7 @@ int arch_cpu_init(void) void *epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); void *rcpm2_base = (void *)(CONFIG_SYS_DCSRBAR + DCSR_RCPM2_BLOCK_OFFSET); - struct ccsr_scfg *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; u32 state;
icache_enable(); @@ -355,7 +355,7 @@ int arch_cpu_init(void) /* Set the address at which the secondary core starts from.*/ void smp_set_core_boot_addr(unsigned long addr, int corenr) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
out_be32(&gur->scratchrw[0], addr); } @@ -363,7 +363,7 @@ void smp_set_core_boot_addr(unsigned long addr, int corenr) /* Release the secondary core from holdoff state and kick it */ void smp_kick_all_cpus(void) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
out_be32(&gur->brrl, 0x2);
diff --git a/arch/arm/cpu/armv7/ls102xa/fdt.c b/arch/arm/cpu/armv7/ls102xa/fdt.c index e63a905eda18..41521c32cebd 100644 --- a/arch/arm/cpu/armv7/ls102xa/fdt.c +++ b/arch/arm/cpu/armv7/ls102xa/fdt.c @@ -92,7 +92,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) int off; int val; const char *sysclk_path; - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); unsigned int svr; svr = in_be32(&gur->svr);
@@ -105,7 +105,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) else { ccsr_sec_t __iomem *sec;
- sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR; fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); } #endif diff --git a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c index caf51e17b359..f74d819ea1ea 100644 --- a/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c +++ b/arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c @@ -39,7 +39,7 @@ int is_serdes_configured(enum srds_prtcl device)
int serdes_get_first_lane(u32 sd, enum srds_prtcl device) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 cfg = in_be32(&gur->rcwsr[4]); int i;
@@ -74,7 +74,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
u64 serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u64 serdes_prtcl_map = 0; u32 cfg; int lane; @@ -103,14 +103,14 @@ void fsl_serdes_init(void) #ifdef CONFIG_SYS_FSL_SRDS_1 if (!(serdes1_prtcl_map & (1ULL << NONE))) serdes1_prtcl_map = serdes_init(FSL_SRDS_1, - CONFIG_SYS_FSL_SERDES_ADDR, + CFG_SYS_FSL_SERDES_ADDR, RCWSR4_SRDS1_PRTCL_MASK, RCWSR4_SRDS1_PRTCL_SHIFT); #endif #ifdef CONFIG_SYS_FSL_SRDS_2 if (!(serdes2_prtcl_map & (1ULL << NONE))) serdes2_prtcl_map = serdes_init(FSL_SRDS_2, - CONFIG_SYS_FSL_SERDES_ADDR + + CFG_SYS_FSL_SERDES_ADDR + FSL_SRDS_2 * 0x1000, RCWSR4_SRDS2_PRTCL_MASK, RCWSR4_SRDS2_PRTCL_SHIFT); diff --git a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c index 28a794520747..b4d113dc1e08 100644 --- a/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c +++ b/arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c @@ -31,7 +31,7 @@ static void __secure ls1_save_ddr_head(void) { const char *src = (const char *)CONFIG_SYS_SDRAM_BASE; char *dest = (char *)(OCRAM_BASE_S_ADDR + OCRAM_S_SIZE - DDR_RESV_LEN); - struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; int i;
out_le32(&scfg->sparecr[2], dest); @@ -57,8 +57,8 @@ static void __secure ls1_fsm_setup(void)
static void __secure ls1_deepsleep_irq_cfg(void) { - struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; - struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR; + struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; + struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR; u32 ippdexpcr0, ippdexpcr1, pmcintecr = 0;
/* Mask interrupts from GIC */ @@ -120,8 +120,8 @@ static void __secure ls1_start_fsm(void) { void *dcsr_epu_base = (void *)(CONFIG_SYS_DCSRBAR + EPU_BLOCK_OFFSET); void *ccsr_gic_base = (void *)SYS_FSL_GIC_ADDR; - struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; - struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; + struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
/* Set HRSTCR */ setbits_be32(&scfg->hrstcr, 0x80000000); @@ -155,9 +155,9 @@ static void __secure ls1_start_fsm(void)
static void __secure ls1_deep_sleep(u32 entry_point) { - struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; - struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR; + struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; + struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR; #ifdef QIXIS_BASE u32 tmp; void *qixis_base = (void *)QIXIS_BASE; @@ -213,8 +213,8 @@ static void __secure ls1_deep_sleep(u32 entry_point) #else static void __secure ls1_sleep(void) { - struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; - struct ccsr_rcpm __iomem *rcpm = (void *)CONFIG_SYS_FSL_RCPM_ADDR; + struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; + struct ccsr_rcpm __iomem *rcpm = (void *)CFG_SYS_FSL_RCPM_ADDR;
#ifdef QIXIS_BASE u32 tmp; diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S index 3956178369f3..e7c4fbfb4342 100644 --- a/arch/arm/cpu/armv7/ls102xa/psci.S +++ b/arch/arm/cpu/armv7/ls102xa/psci.S @@ -129,8 +129,8 @@ psci_cpu_on: mov r1, r4
@ Get DCFG base address - movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff) - movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16) + movw r4, #(CFG_SYS_FSL_GUTS_ADDR & 0xffff) + movt r4, #(CFG_SYS_FSL_GUTS_ADDR >> 16)
@ Detect target CPU state ldr r2, [r4, #DCFG_CCSR_BRR] @@ -141,8 +141,8 @@ psci_cpu_on:
@ Reset target CPU @ Get SCFG base address - movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff) - movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16) + movw r0, #(CFG_SYS_FSL_SCFG_ADDR & 0xffff) + movt r0, #(CFG_SYS_FSL_SCFG_ADDR >> 16)
@ Enable CORE Soft Reset movw r5, #0 @@ -216,8 +216,8 @@ psci_affinity_info: mov r1, r4
@ Get RCPM base address - movw r4, #(CONFIG_SYS_FSL_RCPM_ADDR & 0xffff) - movt r4, #(CONFIG_SYS_FSL_RCPM_ADDR >> 16) + movw r4, #(CFG_SYS_FSL_RCPM_ADDR & 0xffff) + movt r4, #(CFG_SYS_FSL_RCPM_ADDR >> 16)
mov r0, #PSCI_AFFINITY_LEVEL_ON
@@ -236,8 +236,8 @@ out_affinity_info: .globl psci_system_reset psci_system_reset: @ Get DCFG base address - movw r1, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff) - movt r1, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16) + movw r1, #(CFG_SYS_FSL_GUTS_ADDR & 0xffff) + movt r1, #(CFG_SYS_FSL_GUTS_ADDR >> 16)
mov r2, #DCFG_CCSR_RSTCR_RESET_REQ rev r2, r2 diff --git a/arch/arm/cpu/armv7/ls102xa/soc.c b/arch/arm/cpu/armv7/ls102xa/soc.c index 728efc46f905..1dafa3c1b458 100644 --- a/arch/arm/cpu/armv7/ls102xa/soc.c +++ b/arch/arm/cpu/armv7/ls102xa/soc.c @@ -54,7 +54,7 @@ struct smmu_stream_id dev_stream_id[] = {
unsigned int get_soc_major_rev(void) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); unsigned int svr, major;
svr = in_be32(&gur->svr); @@ -113,7 +113,7 @@ static void erratum_a008850_early(void) /* part 1 of 2 */ struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + CONFIG_SYS_CCI400_OFFSET); - struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
/* disables propagation of barrier transactions to DDRC from CCI400 */ out_le32(&cci->ctrl_ord, CCI400_CTRLORD_TERM_BARRIER); @@ -129,7 +129,7 @@ void erratum_a008850_post(void) /* part 2 of 2 */ struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + CONFIG_SYS_CCI400_OFFSET); - struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR; u32 tmp;
/* enable propagation of barrier transactions to DDRC from CCI400 */ @@ -161,7 +161,7 @@ void erratum_a010315(void)
int arch_soc_init(void) { - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + CONFIG_SYS_CCI400_OFFSET); unsigned int major; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 487c0ed5539e..c11341a1d380 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -96,11 +96,11 @@ static struct mm_region early_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE, SYS_FSL_OCRAM_SPACE_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE }, - { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, + { CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_SIZE1, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE}, #ifdef CONFIG_FSL_IFC @@ -159,7 +159,7 @@ static struct mm_region early_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE, SYS_FSL_OCRAM_SPACE_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE }, @@ -168,7 +168,7 @@ static struct mm_region early_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, + { CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE }, @@ -204,7 +204,7 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE, SYS_FSL_OCRAM_SPACE_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE }, @@ -213,12 +213,12 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE | PTE_BLOCK_NS }, - { CONFIG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_BASE1, + { CFG_SYS_FSL_QSPI_BASE1, CFG_SYS_FSL_QSPI_BASE1, CONFIG_SYS_FSL_QSPI_SIZE1, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_BASE2, + { CFG_SYS_FSL_QSPI_BASE2, CFG_SYS_FSL_QSPI_BASE2, CONFIG_SYS_FSL_QSPI_SIZE2, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN @@ -333,7 +333,7 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_FSL_OCRAM_BASE, CONFIG_SYS_FSL_OCRAM_BASE, + { CFG_SYS_FSL_OCRAM_BASE, CFG_SYS_FSL_OCRAM_BASE, SYS_FSL_OCRAM_SPACE_SIZE, PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_NON_SHARE }, @@ -342,7 +342,7 @@ static struct mm_region final_map[] = { PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN }, - { CONFIG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_BASE, + { CFG_SYS_FSL_QSPI_BASE, CFG_SYS_FSL_QSPI_BASE, CONFIG_SYS_FSL_QSPI_SIZE, PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | PTE_BLOCK_NON_SHARE | PTE_BLOCK_PXN | PTE_BLOCK_UXN @@ -401,7 +401,7 @@ struct mm_region *mem_map = early_map;
void cpu_name(char *name) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); unsigned int i, svr, ver;
svr = gur_in32(&gur->svr); @@ -430,7 +430,7 @@ void cpu_name(char *name) #if !CONFIG_IS_ENABLED(SYS_DCACHE_OFF) /* * To start MMU before DDR is available, we create MMU table in SRAM. - * The base address of SRAM is CONFIG_SYS_FSL_OCRAM_BASE. We use three + * The base address of SRAM is CFG_SYS_FSL_OCRAM_BASE. We use three * levels of translation tables here to cover 40-bit address space. * We use 4KB granule size, with 40 bits physical address, T0SZ=24 * Address above EARLY_PGTABLE_SIZE (0x5000) is free for other purpose. @@ -443,7 +443,7 @@ static inline void early_mmu_setup(void)
/* global data is already setup, no allocation yet */ if (el == 3) - gd->arch.tlb_addr = CONFIG_SYS_FSL_OCRAM_BASE; + gd->arch.tlb_addr = CFG_SYS_FSL_OCRAM_BASE; else gd->arch.tlb_addr = CONFIG_SYS_DDR_SDRAM_BASE; gd->arch.tlb_fillptr = gd->arch.tlb_addr; @@ -466,7 +466,7 @@ static void fix_pcie_mmu_map(void) #ifdef CONFIG_ARCH_LS2080A unsigned int i; u32 svr, ver; - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
svr = gur_in32(&gur->svr); ver = SVR_SOC_VER(svr); @@ -775,7 +775,7 @@ enum boot_src get_boot_src(void) #if defined(CONFIG_FSL_LSCH3) u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; #elif defined(CONFIG_FSL_LSCH2) - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); #endif
if (current_el() == 2) { @@ -863,7 +863,7 @@ enum env_location arch_env_get_location(enum env_operation op, int prio)
u32 initiator_type(u32 cluster, int init_id) { - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 idx = (cluster >> (init_id * 8)) & TP_CLUSTER_INIT_MASK; u32 type = 0;
@@ -876,7 +876,7 @@ u32 initiator_type(u32 cluster, int init_id)
u32 cpu_pos_mask(void) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); int i = 0; u32 cluster, type, mask = 0;
@@ -897,7 +897,7 @@ u32 cpu_pos_mask(void)
u32 cpu_mask(void) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); int i = 0, count = 0; u32 cluster, type, mask = 0;
@@ -930,7 +930,7 @@ int cpu_numcores(void) int fsl_qoriq_core_to_cluster(unsigned int core) { struct ccsr_gur __iomem *gur = - (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); + (void __iomem *)(CFG_SYS_FSL_GUTS_ADDR); int i = 0, count = 0; u32 cluster;
@@ -954,7 +954,7 @@ int fsl_qoriq_core_to_cluster(unsigned int core) u32 fsl_qoriq_core_to_type(unsigned int core) { struct ccsr_gur __iomem *gur = - (void __iomem *)(CONFIG_SYS_FSL_GUTS_ADDR); + (void __iomem *)(CFG_SYS_FSL_GUTS_ADDR); int i = 0, count = 0; u32 cluster, type;
@@ -979,7 +979,7 @@ u32 fsl_qoriq_core_to_type(unsigned int core) #ifndef CONFIG_FSL_LSCH3 uint get_svr(void) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
return gur_in32(&gur->svr); } @@ -988,7 +988,7 @@ uint get_svr(void) #ifdef CONFIG_DISPLAY_CPUINFO int print_cpuinfo(void) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); struct sys_info sysinfo; char buf[32]; unsigned int i, core; @@ -1179,9 +1179,9 @@ int arch_early_init_r(void)
int timer_init(void) { - u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR; + u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR; #ifdef CONFIG_FSL_LSCH3 - u32 __iomem *cltbenr = (u32 *)CONFIG_SYS_FSL_PMU_CLTBENR; + u32 __iomem *cltbenr = (u32 *)CFG_SYS_FSL_PMU_CLTBENR; #endif #if defined(CONFIG_ARCH_LS2080A) || defined(CONFIG_ARCH_LS1088A) || \ defined(CONFIG_ARCH_LS1028A) @@ -1230,7 +1230,7 @@ int timer_init(void) }
#if !CONFIG_IS_ENABLED(SYSRESET) -__efi_runtime_data u32 __iomem *rstcr = (u32 *)CONFIG_SYS_FSL_RST_ADDR; +__efi_runtime_data u32 __iomem *rstcr = (u32 *)CFG_SYS_FSL_RST_ADDR;
void __efi_runtime reset_cpu(void) { diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c index 427de1cb339d..ee734577fca7 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fdt.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fdt.c @@ -171,9 +171,9 @@ static void fdt_fixup_gic(void *blob) { int offset, err; u64 reg[8]; - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); unsigned int val; - struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; int align_64k = 0;
val = gur_in32(&gur->svr); @@ -355,7 +355,7 @@ static int _fdt_fixup_pci_msi(void *blob, const char *name, int rev)
static void fdt_fixup_msi(void *blob) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); unsigned int rev;
rev = gur_in32(&gur->svr); @@ -620,7 +620,7 @@ void fdt_fixup_pfe_firmware(void *blob)
void ft_cpu_setup(void *blob, struct bd_info *bd) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); unsigned int svr = gur_in32(&gur->svr);
/* delete crypto node if not on an E-processor */ @@ -635,7 +635,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) fdt_fixup_kaslr(blob); #endif
- sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR; fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); } #endif diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c index 60769e139e4e..1541dfb3ec47 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_serdes.c @@ -40,7 +40,7 @@ int is_serdes_configured(enum srds_prtcl device)
int serdes_get_first_lane(u32 sd, enum srds_prtcl device) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 cfg = gur_in32(&gur->rcwsr[4]); int i;
@@ -76,7 +76,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device)
int get_serdes_protocol(void) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 cfg = gur_in32(&gur->rcwsr[4]) & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; cfg >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; @@ -101,7 +101,7 @@ const char *serdes_clock_to_string(u32 clock) void serdes_init(u32 sd, u32 sd_addr, u32 sd_prctl_mask, u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 cfg; int lane;
@@ -142,7 +142,7 @@ __weak int set_serdes_volt(int svdd)
int setup_serdes_volt(u32 svdd) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); struct ccsr_serdes *serdes1_base; #ifdef CONFIG_SYS_FSL_SRDS_2 struct ccsr_serdes *serdes2_base; @@ -168,7 +168,7 @@ int setup_serdes_volt(u32 svdd) if (svdd_cur == svdd_tar) return 0;
- serdes1_base = (void *)CONFIG_SYS_FSL_SERDES_ADDR; + serdes1_base = (void *)CFG_SYS_FSL_SERDES_ADDR; #ifdef CONFIG_SYS_FSL_SRDS_2 serdes2_base = (void *)serdes1_base + 0x10000; #endif @@ -406,14 +406,14 @@ void fsl_serdes_init(void) { #ifdef CONFIG_SYS_FSL_SRDS_1 serdes_init(FSL_SRDS_1, - CONFIG_SYS_FSL_SERDES_ADDR, + CFG_SYS_FSL_SERDES_ADDR, FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK, FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT, serdes1_prtcl_map); #endif #ifdef CONFIG_SYS_FSL_SRDS_2 serdes_init(FSL_SRDS_2, - CONFIG_SYS_FSL_SERDES_ADDR, + CFG_SYS_FSL_SERDES_ADDR, FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_MASK, FSL_CHASSIS2_RCWSR4_SRDS2_PRTCL_SHIFT, serdes2_prtcl_map); diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c index 898ed09b310a..6440ce714fd1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch2_speed.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR;
void get_sys_info(struct sys_info *sys_info) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); /* rcw_tmp is needed to get FMAN clock, or to get cluster group A * mux 2 clock for LS1043A/LS1046A. */ @@ -29,7 +29,7 @@ void get_sys_info(struct sys_info *sys_info) defined(CONFIG_ARCH_LS1043A) u32 rcw_tmp; #endif - struct ccsr_clk *clk = (void *)(CONFIG_SYS_FSL_CLK_ADDR); + struct ccsr_clk *clk = (void *)(CFG_SYS_FSL_CLK_ADDR); unsigned int cpu; const u8 core_cplx_pll[8] = { [0] = 0, /* CC1 PPL / 1 */ diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c index 181bd9c1b4e5..c0efc341afc1 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_serdes.c @@ -86,7 +86,7 @@ int is_serdes_configured(enum srds_prtcl device)
int serdes_get_first_lane(u32 sd, enum srds_prtcl device) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 cfg = 0; int i;
@@ -134,7 +134,7 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device) void serdes_init(u32 sd, u32 sd_addr, u32 rcwsr, u32 sd_prctl_mask, u32 sd_prctl_shift, u8 serdes_prtcl_map[SERDES_PRCTL_COUNT]) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 cfg; int lane;
@@ -399,18 +399,18 @@ static void do_pll_lock(u32 cfg,
int setup_serdes_volt(u32 svdd) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); struct ccsr_serdes __iomem *serdes1_base = - (void *)CONFIG_SYS_FSL_LSCH3_SERDES_ADDR; + (void *)CFG_SYS_FSL_LSCH3_SERDES_ADDR; u32 cfg_rcwsrds1 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]); #ifdef CONFIG_SYS_FSL_SRDS_2 struct ccsr_serdes __iomem *serdes2_base = - (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000); + (void *)(CFG_SYS_FSL_LSCH3_SERDES_ADDR + 0x10000); u32 cfg_rcwsrds2 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS2_REGSR - 1]); #endif #ifdef CONFIG_SYS_NXP_SRDS_3 struct ccsr_serdes __iomem *serdes3_base = - (void *)(CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000); + (void *)(CFG_SYS_FSL_LSCH3_SERDES_ADDR + 0x20000); u32 cfg_rcwsrds3 = gur_in32(&gur->rcwsr[FSL_CHASSIS3_SRDS3_REGSR - 1]); #endif u32 cfg_tmp; @@ -585,7 +585,7 @@ void fsl_serdes_init(void)
#ifdef CONFIG_SYS_FSL_SRDS_1 serdes_init(FSL_SRDS_1, - CONFIG_SYS_FSL_LSCH3_SERDES_ADDR, + CFG_SYS_FSL_LSCH3_SERDES_ADDR, FSL_CHASSIS3_SRDS1_REGSR, FSL_CHASSIS3_SRDS1_PRTCL_MASK, FSL_CHASSIS3_SRDS1_PRTCL_SHIFT, @@ -593,7 +593,7 @@ void fsl_serdes_init(void) #endif #ifdef CONFIG_SYS_FSL_SRDS_2 serdes_init(FSL_SRDS_2, - CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000, + CFG_SYS_FSL_LSCH3_SERDES_ADDR + FSL_SRDS_2 * 0x10000, FSL_CHASSIS3_SRDS2_REGSR, FSL_CHASSIS3_SRDS2_PRTCL_MASK, FSL_CHASSIS3_SRDS2_PRTCL_SHIFT, @@ -601,7 +601,7 @@ void fsl_serdes_init(void) #endif #ifdef CONFIG_SYS_NXP_SRDS_3 serdes_init(NXP_SRDS_3, - CONFIG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000, + CFG_SYS_FSL_LSCH3_SERDES_ADDR + NXP_SRDS_3 * 0x10000, FSL_CHASSIS3_SRDS3_REGSR, FSL_CHASSIS3_SRDS3_PRTCL_MASK, FSL_CHASSIS3_SRDS3_PRTCL_SHIFT, @@ -611,7 +611,7 @@ void fsl_serdes_init(void)
int serdes_set_env(int sd, int rcwsr, int sd_prctl_mask, int sd_prctl_shift) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); char scfg[16], snum[16]; int cfgr = 0; u32 cfg; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c index 58080d0047dd..137778dc136b 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/fsl_lsch3_speed.c @@ -23,13 +23,13 @@ DECLARE_GLOBAL_DATA_PTR;
void get_sys_info(struct sys_info *sys_info) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); struct ccsr_clk_cluster_group __iomem *clk_grp[2] = { - (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR), - (void *)(CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR) + (void *)(CFG_SYS_FSL_CH3_CLK_GRPA_ADDR), + (void *)(CFG_SYS_FSL_CH3_CLK_GRPB_ADDR) }; struct ccsr_clk_ctrl __iomem *clk_ctrl = - (void *)(CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR); + (void *)(CFG_SYS_FSL_CH3_CLK_CTRL_ADDR); unsigned int cpu; const u8 core_cplx_pll[16] = { [0] = 0, /* CC1 PPL / 1 */ @@ -68,7 +68,7 @@ void get_sys_info(struct sys_info *sys_info) uint freq_c_pll[CONFIG_SYS_FSL_NUM_CC_PLLS]; uint ratio[CONFIG_SYS_FSL_NUM_CC_PLLS]; unsigned long sysclk = get_board_sys_clk(); - int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; + int cc_group[12] = CFG_SYS_FSL_CLUSTER_CLOCKS; u32 c_pll_sel, cplx_pll; void *offset;
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/icid.c b/arch/arm/cpu/armv8/fsl-layerscape/icid.c index 2d87281ec214..e972603f24f8 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/icid.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/icid.c @@ -27,7 +27,7 @@ static void set_icid(struct icid_id_table *tbl, int size) void set_fman_icids(struct fman_icid_id_table *tbl, int size) { int i; - ccsr_fman_t *fm = (void *)CONFIG_SYS_FSL_FM1_ADDR; + ccsr_fman_t *fm = (void *)CFG_SYS_FSL_FM1_ADDR;
for (i = 0; i < size; i++) { out_be32(&fm->fm_bmi_common.fmbm_ppid[tbl[i].port_id - 1], diff --git a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S index 87410c73a920..4358c6ed11c0 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S +++ b/arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S @@ -325,8 +325,8 @@ ENDPROC(fsl_ocram_init)
ENTRY(fsl_clear_ocram) /* Clear OCRAM */ - ldr x0, =CONFIG_SYS_FSL_OCRAM_BASE - ldr x1, =(CONFIG_SYS_FSL_OCRAM_BASE + CONFIG_SYS_FSL_OCRAM_SIZE) + ldr x0, =CFG_SYS_FSL_OCRAM_BASE + ldr x1, =(CFG_SYS_FSL_OCRAM_BASE + CFG_SYS_FSL_OCRAM_SIZE) mov x2, #0 clear_loop: str x2, [x0] diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c index 26f8a4982692..fe667f06c395 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ls1088a_serdes.c @@ -53,7 +53,7 @@ static struct serdes_config *serdes_cfg_tbl[] = {
bool soc_has_mac1(void) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); unsigned int svr = gur_in32(&gur->svr); unsigned int version = SVR_SOC_VER(svr);
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/mp.c b/arch/arm/cpu/armv8/fsl-layerscape/mp.c index 722211914936..ce0c46ad0d4e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/mp.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/mp.c @@ -48,8 +48,8 @@ void update_os_arch_secondary_cores(uint8_t os_arch) #ifdef CONFIG_FSL_LSCH3 static void wake_secondary_core_n(int cluster, int core, int cluster_cores) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); - struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); + struct ccsr_reset __iomem *rst = (void *)(CFG_SYS_FSL_RST_ADDR); u32 mpidr = 0;
mpidr = ((cluster << 8) | core); @@ -73,13 +73,13 @@ static void wake_secondary_core_n(int cluster, int core, int cluster_cores)
int fsl_layerscape_wake_seconday_cores(void) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); #ifdef CONFIG_FSL_LSCH3 - struct ccsr_reset __iomem *rst = (void *)(CONFIG_SYS_FSL_RST_ADDR); + struct ccsr_reset __iomem *rst = (void *)(CFG_SYS_FSL_RST_ADDR); u32 svr, ver, cluster, type; int j = 0, cluster_cores = 0; #elif defined(CONFIG_FSL_LSCH2) - struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR); + struct ccsr_scfg __iomem *scfg = (void *)(CFG_SYS_FSL_SCFG_ADDR); #endif u32 cores, cpu_up_mask = 1; int i, timeout = 10; diff --git a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c index b9894d41bbdd..117b7a053c51 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/ppa.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/ppa.c @@ -253,7 +253,7 @@ int ppa_init(void) #endif
#ifdef CONFIG_FSL_LSCH3 - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); boot_loc_ptr_l = &gur->bootlocptrl; boot_loc_ptr_h = &gur->bootlocptrh;
@@ -261,7 +261,7 @@ int ppa_init(void) loadable_l = &gur->scratchrw[4]; loadable_h = &gur->scratchrw[5]; #elif defined(CONFIG_FSL_LSCH2) - struct ccsr_scfg __iomem *scfg = (void *)(CONFIG_SYS_FSL_SCFG_ADDR); + struct ccsr_scfg __iomem *scfg = (void *)(CFG_SYS_FSL_SCFG_ADDR); boot_loc_ptr_l = &scfg->scratchrw[1]; boot_loc_ptr_h = &scfg->scratchrw[0];
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 515dbe02fd79..89a6262c1282 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -80,7 +80,7 @@ int ls_gic_rd_tables_init(void *blob)
bool soc_has_dp_ddr(void) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 svr = gur_in32(&gur->svr);
/* LS2085A, LS2088A, LS2048A has DP_DDR */ @@ -94,7 +94,7 @@ bool soc_has_dp_ddr(void)
bool soc_has_aiop(void) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 svr = gur_in32(&gur->svr);
/* LS2085A has AIOP */ @@ -249,13 +249,13 @@ static void erratum_a008336(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A008336 u32 *eddrtqcr1;
-#ifdef CONFIG_SYS_FSL_DCSR_DDR_ADDR - eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR_ADDR + 0x800; +#ifdef CFG_SYS_FSL_DCSR_DDR_ADDR + eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR_ADDR + 0x800; if (fsl_ddr_get_version(0) == 0x50200) out_le32(eddrtqcr1, 0x63b30002); #endif -#ifdef CONFIG_SYS_FSL_DCSR_DDR2_ADDR - eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; +#ifdef CFG_SYS_FSL_DCSR_DDR2_ADDR + eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR2_ADDR + 0x800; if (fsl_ddr_get_version(0) == 0x50200) out_le32(eddrtqcr1, 0x63b30002); #endif @@ -271,8 +271,8 @@ static void erratum_a008514(void) #ifdef CONFIG_SYS_FSL_ERRATUM_A008514 u32 *eddrtqcr1;
-#ifdef CONFIG_SYS_FSL_DCSR_DDR3_ADDR - eddrtqcr1 = (void *)CONFIG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; +#ifdef CFG_SYS_FSL_DCSR_DDR3_ADDR + eddrtqcr1 = (void *)CFG_SYS_FSL_DCSR_DDR3_ADDR + 0x800; out_le32(eddrtqcr1, 0x63b20002); #endif #endif @@ -412,7 +412,7 @@ void fsl_lsch3_early_init_f(void) /* Get VDD in the unit mV from voltage ID */ int get_core_volt_from_fuse(void) { - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); int vdd; u32 fusesr; u8 vid; @@ -462,7 +462,7 @@ int get_core_volt_from_fuse(void) static void erratum_a009660(void) { #ifdef CONFIG_SYS_FSL_ERRATUM_A009660 - u32 *eddrtqcr1 = (void *)CONFIG_SYS_FSL_SCFG_ADDR + 0x20c; + u32 *eddrtqcr1 = (void *)CFG_SYS_FSL_SCFG_ADDR + 0x20c; out_be32(eddrtqcr1, 0x63b20042); #endif } @@ -473,7 +473,7 @@ static void erratum_a008850_early(void) /* part 1 of 2 */ struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + CONFIG_SYS_CCI400_OFFSET); - struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR;
/* Skip if running at lower exception level */ if (current_el() < 3) @@ -493,7 +493,7 @@ void erratum_a008850_post(void) /* part 2 of 2 */ struct ccsr_cci400 __iomem *cci = (void *)(CONFIG_SYS_IMMR + CONFIG_SYS_CCI400_OFFSET); - struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR; u32 tmp;
/* Skip if running at lower exception level */ @@ -526,21 +526,21 @@ void erratum_a010315(void) static void erratum_a010539(void) { #if defined(CONFIG_SYS_FSL_ERRATUM_A010539) && defined(CONFIG_QSPI_BOOT) - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 porsr1;
porsr1 = in_be32(&gur->porsr1); porsr1 &= ~FSL_CHASSIS2_CCSR_PORSR1_RCW_MASK; out_be32((void *)(CONFIG_SYS_DCSR_DCFG_ADDR + DCFG_DCSR_PORCR1), porsr1); - out_be32((void *)(CONFIG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff); + out_be32((void *)(CFG_SYS_FSL_SCFG_ADDR + 0x1a8), 0xffffffff); #endif }
/* Get VDD in the unit mV from voltage ID */ int get_core_volt_from_fuse(void) { - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); int vdd; u32 fusesr; u8 vid; @@ -588,7 +588,7 @@ static int setup_core_volt(u32 vdd) #ifdef CONFIG_SYS_FSL_DDR static void ddr_enable_0v9_volt(bool en) { - struct ccsr_ddr __iomem *ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + struct ccsr_ddr __iomem *ddr = (void *)CFG_SYS_FSL_DDR_ADDR; u32 tmp;
tmp = ddr_in32(&ddr->ddr_cdr1); @@ -629,7 +629,7 @@ int setup_chip_volt(void) #ifdef CONFIG_FSL_PFE void init_pfe_scfg_dcfg_regs(void) { - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; u32 ecccr2;
out_be32(&scfg->pfeasbcr, @@ -653,7 +653,7 @@ void fsl_lsch2_early_init_f(void) { struct ccsr_cci400 *cci = (struct ccsr_cci400 *)(CONFIG_SYS_IMMR + CONFIG_SYS_CCI400_OFFSET); - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; #if defined(CONFIG_FSL_QSPI) && defined(CONFIG_TFABOOT) enum boot_src src; #endif diff --git a/arch/arm/include/asm/arch-fsl-layerscape/config.h b/arch/arm/include/asm/arch-fsl-layerscape/config.h index 5824778ca286..ff752c21b14d 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/config.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/config.h @@ -24,7 +24,7 @@ #define SPL_TLB_SETBACK 0x1000000 /* 16MB under effective memory top */
#ifdef CONFIG_ARCH_LS2080A -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } +#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4, 4 } #define SRDS_MAX_LANES 8 #define CONFIG_SYS_PAGE_SIZE 0x10000 #ifndef L1_CACHE_BYTES @@ -32,9 +32,9 @@ #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) #endif
-#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ -#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ +#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
/* DDR */ #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) @@ -95,7 +95,7 @@ #define EPU_EPGCR 0x700060000ULL
#elif defined(CONFIG_ARCH_LS1088A) -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } +#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } #define CONFIG_SYS_PAGE_SIZE 0x10000
#define SRDS_MAX_LANES 4 @@ -126,9 +126,9 @@ #define CONFIG_MAX_MEM_MAPPED CONFIG_SYS_DDR_BLOCK1_SIZE
/* DCFG - GUR */ -#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ -#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ +#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
/* LX2160A/LX2162A Soc Support */ #elif defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) @@ -139,13 +139,13 @@ #define L1_CACHE_SHIFT 6 #define L1_CACHE_BYTES BIT(L1_CACHE_SHIFT) #endif -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 } +#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1, 4, 4, 4, 4 }
#define CONFIG_SYS_PAGE_SIZE 0x10000
-#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ -#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ +#define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
/* DDR */ #define CONFIG_SYS_DDR_BLOCK1_SIZE ((phys_size_t)2 << 30) @@ -161,7 +161,7 @@ /* DCFG - GUR */
#elif defined(CONFIG_ARCH_LS1028A) -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } +#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1 } #define CONFIG_FSL_TZASC_400
/* TZ Protection Controller Definitions */ @@ -180,9 +180,9 @@ #define SRDS_MAX_LANES 4 #define SRDS_BITS_PER_LANE 4
-#define CONFIG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ +#define CFG_SYS_FSL_OCRAM_BASE 0x18000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M */ -#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */ +#define CFG_SYS_FSL_OCRAM_SIZE 0x00040000 /* Real size 256K */
/* Generic Interrupt Controller Definitions */ #define GICD_BASE 0x06000000 @@ -200,9 +200,9 @@ /* DCFG - GUR */
#elif defined(CONFIG_FSL_LSCH2) -#define CONFIG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ +#define CFG_SYS_FSL_OCRAM_BASE 0x10000000 /* initial RAM */ #define SYS_FSL_OCRAM_SPACE_SIZE 0x00200000 /* 2M space */ -#define CONFIG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */ +#define CFG_SYS_FSL_OCRAM_SIZE 0x00020000 /* Real size 128K */
#define DCSR_DCFG_SBEESR2 0x20140534 #define DCSR_DCFG_MBEESR2 0x20140544 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h index c51b65ea36d9..4db479140ea2 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/cpu.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/cpu.h @@ -10,7 +10,7 @@ #ifdef CONFIG_FSL_LSCH3 #define CONFIG_SYS_FSL_CCSR_BASE 0x00000000 #define CONFIG_SYS_FSL_CCSR_SIZE 0x10000000 -#define CONFIG_SYS_FSL_QSPI_BASE1 0x20000000 +#define CFG_SYS_FSL_QSPI_BASE1 0x20000000 #define CONFIG_SYS_FSL_QSPI_SIZE1 0x10000000 #ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_FSL_IFC_BASE1 0x30000000 @@ -19,7 +19,7 @@ #endif #define CONFIG_SYS_FSL_DRAM_BASE1 0x80000000 #define CONFIG_SYS_FSL_DRAM_SIZE1 0x80000000 -#define CONFIG_SYS_FSL_QSPI_BASE2 0x400000000 +#define CFG_SYS_FSL_QSPI_BASE2 0x400000000 #define CONFIG_SYS_FSL_QSPI_SIZE2 0x100000000 #ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_FSL_IFC_BASE2 0x500000000 @@ -73,7 +73,7 @@ #define CONFIG_SYS_FSL_CCSR_SIZE 0xf000000 #define CONFIG_SYS_FSL_DCSR_BASE 0x20000000 #define CONFIG_SYS_FSL_DCSR_SIZE 0x4000000 -#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 +#define CFG_SYS_FSL_QSPI_BASE 0x40000000 #define CONFIG_SYS_FSL_QSPI_SIZE 0x20000000 #define CONFIG_SYS_FSL_IFC_BASE 0x60000000 #define CONFIG_SYS_FSL_IFC_SIZE 0x20000000 diff --git a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h index 8af0d35d27b7..9cddb41a89c8 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/fsl_icid.h @@ -70,7 +70,7 @@ void fdt_fixup_icid(void *blob);
#define SET_SCFG_ICID(compat, streamid, name, compataddr) \ SET_ICID_ENTRY(compat, streamid, (((streamid) << 24) | (1 << 23)), \ - offsetof(struct ccsr_scfg, name) + CONFIG_SYS_FSL_SCFG_ADDR, \ + offsetof(struct ccsr_scfg, name) + CFG_SYS_FSL_SCFG_ADDR, \ compataddr, SCFG_IS_LE)
#define SET_USB_ICID(usb_num, compat, streamid) \ @@ -83,7 +83,7 @@ void fdt_fixup_icid(void *blob);
#define SET_SDHC_ICID(streamid) \ SET_SCFG_ICID("fsl,esdhc", streamid, sdhc_icid,\ - CONFIG_SYS_FSL_ESDHC_ADDR) + CFG_SYS_FSL_ESDHC_ADDR)
#define SET_EDMA_ICID(streamid) \ SET_SCFG_ICID("fsl,vf610-edma", streamid, edma_icid,\ @@ -102,14 +102,14 @@ void fdt_fixup_icid(void *blob); #define SET_QMAN_ICID(streamid) \ SET_ICID_ENTRY("fsl,qman", streamid, streamid, \ offsetof(struct ccsr_qman, liodnr) + \ - CONFIG_SYS_FSL_QMAN_ADDR, \ - CONFIG_SYS_FSL_QMAN_ADDR, false) + CFG_SYS_FSL_QMAN_ADDR, \ + CFG_SYS_FSL_QMAN_ADDR, false)
#define SET_BMAN_ICID(streamid) \ SET_ICID_ENTRY("fsl,bman", streamid, streamid, \ offsetof(struct ccsr_bman, liodnr) + \ - CONFIG_SYS_FSL_BMAN_ADDR, \ - CONFIG_SYS_FSL_BMAN_ADDR, false) + CFG_SYS_FSL_BMAN_ADDR, \ + CFG_SYS_FSL_BMAN_ADDR, false)
#define SET_FMAN_ICID_ENTRY(_port_id, streamid) \ { .port_id = (_port_id), .icid = (streamid) } @@ -119,8 +119,8 @@ void fdt_fixup_icid(void *blob); #define SET_SEC_QI_ICID(streamid) \ SET_ICID_ENTRY("fsl,sec-v4.0", streamid, \ 0, offsetof(ccsr_sec_t, qilcr_ls) + \ - CONFIG_SYS_FSL_SEC_ADDR, \ - CONFIG_SYS_FSL_SEC_ADDR, SEC_IS_LE) + CFG_SYS_FSL_SEC_ADDR, \ + CFG_SYS_FSL_SEC_ADDR, SEC_IS_LE)
extern struct fman_icid_id_table fman_icid_tbl[]; extern int fman_icid_tbl_sz; @@ -137,7 +137,7 @@ extern int fman_icid_tbl_sz;
#define SET_GUR_ICID(compat, streamid, name, compataddr) \ SET_ICID_ENTRY(compat, streamid, streamid, \ - offsetof(struct ccsr_gur, name) + CONFIG_SYS_FSL_GUTS_ADDR, \ + offsetof(struct ccsr_gur, name) + CFG_SYS_FSL_GUTS_ADDR, \ compataddr, GUR_IS_LE)
#define SET_USB_ICID(usb_num, compat, streamid) \ @@ -180,24 +180,24 @@ extern int fman_icid_tbl_sz; SET_ICID_ENTRY( \ (CONFIG_IS_ENABLED(ARMV8_SEC_FIRMWARE_SUPPORT) && \ (FSL_SEC_JR##jr_num##_OFFSET == \ - SEC_JR3_OFFSET + CONFIG_SYS_FSL_SEC_OFFSET) \ + SEC_JR3_OFFSET + CFG_SYS_FSL_SEC_OFFSET) \ ? NULL \ : "fsl,sec-v4.0-job-ring"), \ streamid, \ SEC_ICID_REG_VAL(streamid), \ offsetof(ccsr_sec_t, jrliodnr[jr_num].ls) + \ - CONFIG_SYS_FSL_SEC_ADDR, \ + CFG_SYS_FSL_SEC_ADDR, \ FSL_SEC_JR##jr_num##_BASE_ADDR, SEC_IS_LE)
#define SET_SEC_DECO_ICID_ENTRY(deco_num, streamid) \ SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \ offsetof(ccsr_sec_t, decoliodnr[deco_num].ls) + \ - CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE) + CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
#define SET_SEC_RTIC_ICID_ENTRY(rtic_num, streamid) \ SET_ICID_ENTRY(NULL, streamid, SEC_ICID_REG_VAL(streamid), \ offsetof(ccsr_sec_t, rticliodnr[rtic_num].ls) + \ - CONFIG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE) + CFG_SYS_FSL_SEC_ADDR, 0, SEC_IS_LE)
extern struct icid_id_table icid_tbl[]; extern int icid_tbl_sz; diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h index 2b73647ab4a9..e8bd8d27136c 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch2.h @@ -14,18 +14,18 @@ #define CONFIG_SYS_DCSRBAR 0x20000000 #define CONFIG_SYS_DCSR_DCFG_ADDR (CONFIG_SYS_DCSRBAR + 0x00140000)
-#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) +#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x00550000) -#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) -#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) -#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) -#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0) -#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) -#define CONFIG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000) -#define CONFIG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000) -#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) -#define CONFIG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) +#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) +#define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) +#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) +#define CFG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00ee00b0) +#define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) +#define CFG_SYS_FSL_BMAN_ADDR (CONFIG_SYS_IMMR + 0x00890000) +#define CFG_SYS_FSL_QMAN_ADDR (CONFIG_SYS_IMMR + 0x00880000) +#define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) +#define CFG_SYS_FSL_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011c0600) #define CONFIG_SYS_NS16550_COM3 (CONFIG_SYS_IMMR + 0x011d0500) @@ -65,7 +65,7 @@ #define CONFIG_SYS_QMAN_CINH_SIZE (CONFIG_SYS_QMAN_MEM_SIZE >> 1) #define CONFIG_SYS_QMAN_SWP_ISDR_REG 0x3680
-#define CONFIG_SYS_FSL_TIMER_ADDR 0x02b00000 +#define CFG_SYS_FSL_TIMER_ADDR 0x02b00000
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01180000) #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01190000) @@ -165,24 +165,24 @@ struct sys_info { unsigned long freq_qman; };
-#define CONFIG_SYS_FSL_FM1_OFFSET 0xa00000 +#define CFG_SYS_FSL_FM1_OFFSET 0xa00000
-#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000 -#define CONFIG_SYS_FSL_FM1_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET) -#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) +#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET 0xae0000 +#define CFG_SYS_FSL_FM1_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_OFFSET) +#define CFG_SYS_FSL_FM1_DTSEC1_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_DTSEC1_OFFSET)
-#define CONFIG_SYS_FSL_SEC_OFFSET 0x700000ull -#define CONFIG_SYS_FSL_JR0_OFFSET 0x710000ull -#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET +#define CFG_SYS_FSL_SEC_OFFSET 0x700000ull +#define CFG_SYS_FSL_JR0_OFFSET 0x710000ull +#define FSL_SEC_JR0_OFFSET CFG_SYS_FSL_JR0_OFFSET #define FSL_SEC_JR1_OFFSET 0x720000ull #define FSL_SEC_JR2_OFFSET 0x730000ull #define FSL_SEC_JR3_OFFSET 0x740000ull -#define CONFIG_SYS_FSL_SEC_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) -#define CONFIG_SYS_FSL_JR0_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) +#define CFG_SYS_FSL_SEC_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET) +#define CFG_SYS_FSL_JR0_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET) #define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET) #define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET) #define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET) diff --git a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h index 570397b3c04c..f1ffb2327d63 100644 --- a/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h +++ b/arch/arm/include/asm/arch-fsl-layerscape/immap_lsch3.h @@ -9,19 +9,19 @@ #ifndef __ARCH_FSL_LSCH3_IMMAP_H_ #define __ARCH_FSL_LSCH3_IMMAP_H_
-#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) -#define CONFIG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) -#define CONFIG_SYS_FSL_DDR3_ADDR 0x08210000 -#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) -#define CONFIG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) +#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) +#define CFG_SYS_FSL_DDR2_ADDR (CONFIG_SYS_IMMR + 0x00090000) +#define CFG_SYS_FSL_DDR3_ADDR 0x08210000 +#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00E00000) +#define CFG_SYS_FSL_PMU_ADDR (CONFIG_SYS_IMMR + 0x00E30000) #if defined(CONFIG_ARCH_LX2160A) || defined(CONFIG_ARCH_LX2162A) -#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180) +#define CFG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00e88180) #else -#define CONFIG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) +#define CFG_SYS_FSL_RST_ADDR (CONFIG_SYS_IMMR + 0x00E60000) #endif -#define CONFIG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) -#define CONFIG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) -#define CONFIG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) +#define CFG_SYS_FSL_CH3_CLK_GRPA_ADDR (CONFIG_SYS_IMMR + 0x00300000) +#define CFG_SYS_FSL_CH3_CLK_GRPB_ADDR (CONFIG_SYS_IMMR + 0x00310000) +#define CFG_SYS_FSL_CH3_CLK_CTRL_ADDR (CONFIG_SYS_IMMR + 0x00370000) #ifndef CONFIG_NXP_LSCH3_2 #define SYS_FSL_QSPI_ADDR (CONFIG_SYS_IMMR + 0x010c0000) #else @@ -29,8 +29,8 @@ #define SYS_NXP_FSPI_LUTKEY_BASE_ADDR 0x18 #define SYS_NXP_FSPI_LUT_BASE_ADDR 0x200 #endif -#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) -#define FSL_ESDHC1_BASE_ADDR CONFIG_SYS_FSL_ESDHC_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x01140000) +#define FSL_ESDHC1_BASE_ADDR CFG_SYS_FSL_ESDHC_ADDR #define FSL_ESDHC2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01150000) #ifndef CONFIG_NXP_LSCH3_2 #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x01240000) @@ -38,20 +38,20 @@ #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011C0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011C0600) #define SYS_FSL_LS2080A_LS2085A_TIMER_ADDR 0x023d0000 -#define CONFIG_SYS_FSL_TIMER_ADDR 0x023e0000 -#define CONFIG_SYS_FSL_PMU_CLTBENR (CONFIG_SYS_FSL_PMU_ADDR + \ +#define CFG_SYS_FSL_TIMER_ADDR 0x023e0000 +#define CFG_SYS_FSL_PMU_CLTBENR (CFG_SYS_FSL_PMU_ADDR + \ 0x18A0) -#define FSL_PMU_PCTBENR_OFFSET (CONFIG_SYS_FSL_PMU_ADDR + 0x8A0) -#define FSL_LSCH3_SVR (CONFIG_SYS_FSL_GUTS_ADDR + 0xA4) +#define FSL_PMU_PCTBENR_OFFSET (CFG_SYS_FSL_PMU_ADDR + 0x8A0) +#define FSL_LSCH3_SVR (CFG_SYS_FSL_GUTS_ADDR + 0xA4)
-#define CONFIG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000) -#define CONFIG_SYS_FSL_WRIOP1_MDIO1 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x16000) -#define CONFIG_SYS_FSL_WRIOP1_MDIO2 (CONFIG_SYS_FSL_WRIOP1_ADDR + 0x17000) -#define CONFIG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000) +#define CFG_SYS_FSL_WRIOP1_ADDR (CONFIG_SYS_IMMR + 0x7B80000) +#define CFG_SYS_FSL_WRIOP1_MDIO1 (CFG_SYS_FSL_WRIOP1_ADDR + 0x16000) +#define CFG_SYS_FSL_WRIOP1_MDIO2 (CFG_SYS_FSL_WRIOP1_ADDR + 0x17000) +#define CFG_SYS_FSL_LSCH3_SERDES_ADDR (CONFIG_SYS_IMMR + 0xEA0000)
-#define CONFIG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL -#define CONFIG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL -#define CONFIG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL +#define CFG_SYS_FSL_DCSR_DDR_ADDR 0x70012c000ULL +#define CFG_SYS_FSL_DCSR_DDR2_ADDR 0x70012d000ULL +#define CFG_SYS_FSL_DCSR_DDR3_ADDR 0x700132000ULL
#define I2C1_BASE_ADDR (CONFIG_SYS_IMMR + 0x01000000) #define I2C2_BASE_ADDR (CONFIG_SYS_IMMR + 0x01010000) @@ -108,16 +108,16 @@ #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200)
/* SEC */ -#define CONFIG_SYS_FSL_SEC_OFFSET 0x07000000ull -#define CONFIG_SYS_FSL_JR0_OFFSET 0x07010000ull -#define FSL_SEC_JR0_OFFSET CONFIG_SYS_FSL_JR0_OFFSET +#define CFG_SYS_FSL_SEC_OFFSET 0x07000000ull +#define CFG_SYS_FSL_JR0_OFFSET 0x07010000ull +#define FSL_SEC_JR0_OFFSET CFG_SYS_FSL_JR0_OFFSET #define FSL_SEC_JR1_OFFSET 0x07020000ull #define FSL_SEC_JR2_OFFSET 0x07030000ull #define FSL_SEC_JR3_OFFSET 0x07040000ull -#define CONFIG_SYS_FSL_SEC_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) -#define CONFIG_SYS_FSL_JR0_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) +#define CFG_SYS_FSL_SEC_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET) +#define CFG_SYS_FSL_JR0_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET) #define FSL_SEC_JR0_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR0_OFFSET) #define FSL_SEC_JR1_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR1_OFFSET) #define FSL_SEC_JR2_BASE_ADDR (CONFIG_SYS_IMMR + FSL_SEC_JR2_OFFSET) diff --git a/arch/arm/include/asm/arch-imx8/imx-regs.h b/arch/arm/include/asm/arch-imx8/imx-regs.h index 3d32b7a02a18..f5691620c48e 100644 --- a/arch/arm/include/asm/arch-imx8/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8/imx-regs.h @@ -47,6 +47,6 @@ #define USB_BASE_ADDR 0x5b0d0000 #define USB_PHY0_BASE_ADDR 0x5b100000
-#define CONFIG_SYS_FSL_SEC_ADDR (0x31400000) +#define CFG_SYS_FSL_SEC_ADDR (0x31400000)
#endif /* __ASM_ARCH_IMX8_REGS_H__ */ diff --git a/arch/arm/include/asm/arch-imx8m/imx-regs.h b/arch/arm/include/asm/arch-imx8m/imx-regs.h index 29d5baaab8b8..586847f32e25 100644 --- a/arch/arm/include/asm/arch-imx8m/imx-regs.h +++ b/arch/arm/include/asm/arch-imx8m/imx-regs.h @@ -87,12 +87,12 @@ #define CAAM_ARB_BASE_ADDR (0x00100000) #define CAAM_ARB_END_ADDR (0x00107FFF) #define CAAM_IPS_BASE_ADDR (0x30900000) -#define CONFIG_SYS_FSL_SEC_OFFSET (0) -#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ - CONFIG_SYS_FSL_SEC_OFFSET) -#define CONFIG_SYS_FSL_JR0_OFFSET (0x1000) -#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ - CONFIG_SYS_FSL_JR0_OFFSET) +#define CFG_SYS_FSL_SEC_OFFSET (0) +#define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ + CFG_SYS_FSL_SEC_OFFSET) +#define CFG_SYS_FSL_JR0_OFFSET (0x1000) +#define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \ + CFG_SYS_FSL_JR0_OFFSET) #if !defined(__ASSEMBLY__) #include <asm/types.h> #include <linux/bitops.h> diff --git a/arch/arm/include/asm/arch-ls102xa/config.h b/arch/arm/include/asm/arch-ls102xa/config.h index 0e32828b4f1e..e85918eb7ec5 100644 --- a/arch/arm/include/asm/arch-ls102xa/config.h +++ b/arch/arm/include/asm/arch-ls102xa/config.h @@ -17,25 +17,25 @@ #define SYS_FSL_DCSR_RCPM_ADDR (CONFIG_SYS_DCSRBAR + 0x00222000)
#define SYS_FSL_GIC_ADDR (CONFIG_SYS_IMMR + 0x00400000) -#define CONFIG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) -#define CONFIG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) +#define CFG_SYS_FSL_DDR_ADDR (CONFIG_SYS_IMMR + 0x00080000) +#define CFG_SYS_FSL_CSU_ADDR (CONFIG_SYS_IMMR + 0x00510000) #define CONFIG_SYS_IFC_ADDR (CONFIG_SYS_IMMR + 0x00530000) -#define CONFIG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) -#define CONFIG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) -#define CONFIG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) -#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) +#define CFG_SYS_FSL_ESDHC_ADDR (CONFIG_SYS_IMMR + 0x00560000) +#define CFG_SYS_FSL_SCFG_ADDR (CONFIG_SYS_IMMR + 0x00570000) +#define CFG_SYS_FSL_SEC_ADDR (CONFIG_SYS_IMMR + 0x700000) +#define CFG_SYS_FSL_JR0_ADDR (CONFIG_SYS_IMMR + 0x710000) #define CONFIG_SYS_SEC_MON_ADDR (CONFIG_SYS_IMMR + 0x00e90000) #define CONFIG_SYS_SFP_ADDR (CONFIG_SYS_IMMR + 0x00e80200) -#define CONFIG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) -#define CONFIG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) -#define CONFIG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) -#define CONFIG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000) +#define CFG_SYS_FSL_SERDES_ADDR (CONFIG_SYS_IMMR + 0x00ea0000) +#define CFG_SYS_FSL_GUTS_ADDR (CONFIG_SYS_IMMR + 0x00ee0000) +#define CFG_SYS_FSL_LS1_CLK_ADDR (CONFIG_SYS_IMMR + 0x00ee1000) +#define CFG_SYS_FSL_RCPM_ADDR (CONFIG_SYS_IMMR + 0x00ee2000) #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_IMMR + 0x011c0500) #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_IMMR + 0x011d0500) #define CONFIG_SYS_XHCI_USB1_ADDR (CONFIG_SYS_IMMR + 0x02100000)
-#define CONFIG_SYS_FSL_SEC_OFFSET 0x00700000 -#define CONFIG_SYS_FSL_JR0_OFFSET 0x00710000 +#define CFG_SYS_FSL_SEC_OFFSET 0x00700000 +#define CFG_SYS_FSL_JR0_OFFSET 0x00710000 #define CONFIG_SYS_TSEC1_OFFSET 0x01d10000 #define CONFIG_SYS_MDIO1_OFFSET 0x01d24000
diff --git a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h index 93b0a26091e7..fb5ded890783 100644 --- a/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h +++ b/arch/arm/include/asm/arch-ls102xa/ls102xa_stream_id.h @@ -29,30 +29,30 @@ #define SET_SEC_JR_LIODN_ENTRY(jrnum, liodnA, liodnB) \ SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB, \ offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \ - CONFIG_SYS_FSL_SEC_OFFSET, \ - CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \ + CFG_SYS_FSL_SEC_OFFSET, \ + CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum), \ SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\ offsetof(ccsr_sec_t, jrliodnr[jrnum].ls) + \ - CONFIG_SYS_FSL_SEC_OFFSET, \ - CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum) + CFG_SYS_FSL_SEC_OFFSET, \ + CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrnum)
/* This is a bit evil since we treat rtic param as both a string & hex value */ #define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \ SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \ liodnA, \ offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ - CONFIG_SYS_FSL_SEC_OFFSET, \ - CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \ + CFG_SYS_FSL_SEC_OFFSET, \ + CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \ SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \ liodnA, \ offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ - CONFIG_SYS_FSL_SEC_OFFSET, \ - CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)) + CFG_SYS_FSL_SEC_OFFSET, \ + CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \ SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \ offsetof(ccsr_sec_t, decoliodnr[num].ls) + \ - CONFIG_SYS_FSL_SEC_OFFSET, 0) + CFG_SYS_FSL_SEC_OFFSET, 0)
struct liodn_id_table { const char *compat; diff --git a/arch/arm/include/asm/arch-mx6/imx-regs.h b/arch/arm/include/asm/arch-mx6/imx-regs.h index 56b3a58d478a..72944af18a40 100644 --- a/arch/arm/include/asm/arch-mx6/imx-regs.h +++ b/arch/arm/include/asm/arch-mx6/imx-regs.h @@ -238,12 +238,12 @@ #endif #define ARM_BASE_ADDR (ATZ2_BASE_ADDR + 0x40000)
-#define CONFIG_SYS_FSL_SEC_OFFSET 0 -#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \ - CONFIG_SYS_FSL_SEC_OFFSET) -#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 -#define CONFIG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \ - CONFIG_SYS_FSL_JR0_OFFSET) +#define CFG_SYS_FSL_SEC_OFFSET 0 +#define CFG_SYS_FSL_SEC_ADDR (CAAM_BASE_ADDR + \ + CFG_SYS_FSL_SEC_OFFSET) +#define CFG_SYS_FSL_JR0_OFFSET 0x1000 +#define CFG_SYS_FSL_JR0_ADDR (CAAM_BASE_ADDR + \ + CFG_SYS_FSL_JR0_OFFSET)
#define USB_PL301_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x0000) #define USB_BASE_ADDR (AIPS2_OFF_BASE_ADDR + 0x4000) diff --git a/arch/arm/include/asm/arch-mx7/imx-regs.h b/arch/arm/include/asm/arch-mx7/imx-regs.h index 1e9d11b7a5c1..c863cd9da360 100644 --- a/arch/arm/include/asm/arch-mx7/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7/imx-regs.h @@ -215,12 +215,12 @@
#define FEC_QUIRK_ENET_MAC #define SNVS_LPGPR 0x68 -#define CONFIG_SYS_FSL_SEC_OFFSET 0 -#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ - CONFIG_SYS_FSL_SEC_OFFSET) -#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 -#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ - CONFIG_SYS_FSL_JR0_OFFSET) +#define CFG_SYS_FSL_SEC_OFFSET 0 +#define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ + CFG_SYS_FSL_SEC_OFFSET) +#define CFG_SYS_FSL_JR0_OFFSET 0x1000 +#define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \ + CFG_SYS_FSL_JR0_OFFSET) #if !(defined(__KERNEL_STRICT_NAMES) || defined(__ASSEMBLY__)) #include <asm/mach-imx/regs-lcdif.h> #include <asm/types.h> diff --git a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h index ffa170f4d255..33a699ff71a9 100644 --- a/arch/arm/include/asm/arch-mx7ulp/imx-regs.h +++ b/arch/arm/include/asm/arch-mx7ulp/imx-regs.h @@ -228,12 +228,12 @@
#define CAAM_IPS_BASE_ADDR (AIPS2_BASE + 0x240000) /* 40240000 */
-#define CONFIG_SYS_FSL_SEC_OFFSET 0 -#define CONFIG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ - CONFIG_SYS_FSL_SEC_OFFSET) -#define CONFIG_SYS_FSL_JR0_OFFSET 0x1000 -#define CONFIG_SYS_FSL_JR0_ADDR (CONFIG_SYS_FSL_SEC_ADDR + \ - CONFIG_SYS_FSL_JR0_OFFSET) +#define CFG_SYS_FSL_SEC_OFFSET 0 +#define CFG_SYS_FSL_SEC_ADDR (CAAM_IPS_BASE_ADDR + \ + CFG_SYS_FSL_SEC_OFFSET) +#define CFG_SYS_FSL_JR0_OFFSET 0x1000 +#define CFG_SYS_FSL_JR0_ADDR (CFG_SYS_FSL_SEC_ADDR + \ + CFG_SYS_FSL_JR0_OFFSET)
#define IOMUXC_DPCR_DDR_DQS0 ((IOMUXC_DDR_RBASE + (4 * 32))) #define IOMUXC_DPCR_DDR_DQS1 ((IOMUXC_DDR_RBASE + (4 * 33))) diff --git a/arch/arm/mach-imx/cmd_dek.c b/arch/arm/mach-imx/cmd_dek.c index 04c4b20a84bc..b65bf874b837 100644 --- a/arch/arm/mach-imx/cmd_dek.c +++ b/arch/arm/mach-imx/cmd_dek.c @@ -40,7 +40,7 @@ static int blob_encap_dek(u32 src_addr, u32 dst_addr, u32 len)
hab_caam_clock_enable(1);
- u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + + u32 out_jr_size = sec_in32(CFG_SYS_FSL_JR0_ADDR + FSL_CAAM_ORSR_JRa_OFFSET); if (out_jr_size != FSL_CAAM_MAX_JR_SIZE) sec_init(); diff --git a/arch/arm/mach-imx/cmd_mfgprot.c b/arch/arm/mach-imx/cmd_mfgprot.c index ec8a8756f7fc..9576b48dde30 100644 --- a/arch/arm/mach-imx/cmd_mfgprot.c +++ b/arch/arm/mach-imx/cmd_mfgprot.c @@ -41,7 +41,7 @@ static int do_mfgprot(struct cmd_tbl *cmdtp, int flag, int argc, char *const arg /* Enable HAB clock */ hab_caam_clock_enable(1);
- u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + + u32 out_jr_size = sec_in32(CFG_SYS_FSL_JR0_ADDR + FSL_CAAM_ORSR_JRa_OFFSET);
if (out_jr_size != FSL_CAAM_MAX_JR_SIZE) diff --git a/arch/arm/mach-imx/mx7/clock.c b/arch/arm/mach-imx/mx7/clock.c index 304a0303134a..88f6fe027482 100644 --- a/arch/arm/mach-imx/mx7/clock.c +++ b/arch/arm/mach-imx/mx7/clock.c @@ -30,9 +30,9 @@ DECLARE_GLOBAL_DATA_PTR; int get_clocks(void) { #ifdef CONFIG_FSL_ESDHC_IMX -#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR +#if CFG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); -#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR +#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); #else gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); diff --git a/arch/arm/mach-imx/mx7ulp/clock.c b/arch/arm/mach-imx/mx7ulp/clock.c index 6191153917f7..37d8565c20fc 100644 --- a/arch/arm/mach-imx/mx7ulp/clock.c +++ b/arch/arm/mach-imx/mx7ulp/clock.c @@ -18,9 +18,9 @@ DECLARE_GLOBAL_DATA_PTR; int get_clocks(void) { #ifdef CONFIG_FSL_ESDHC_IMX -#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE +#if CFG_SYS_FSL_ESDHC_ADDR == USDHC0_RBASE gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); -#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE +#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC1_RBASE gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); #endif #endif diff --git a/arch/arm/mach-imx/speed.c b/arch/arm/mach-imx/speed.c index b729187ec817..0e81cc880a1a 100644 --- a/arch/arm/mach-imx/speed.c +++ b/arch/arm/mach-imx/speed.c @@ -21,21 +21,21 @@ int get_clocks(void) { #ifdef CONFIG_FSL_ESDHC_IMX #ifdef CONFIG_FSL_USDHC -#if CONFIG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR +#if CFG_SYS_FSL_ESDHC_ADDR == USDHC2_BASE_ADDR gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); -#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR +#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC3_BASE_ADDR gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); -#elif CONFIG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR +#elif CFG_SYS_FSL_ESDHC_ADDR == USDHC4_BASE_ADDR gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); #else gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); #endif #else -#if CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR +#if CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC2_BASE_ADDR gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); -#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR +#elif CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC3_BASE_ADDR gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); -#elif CONFIG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR +#elif CFG_SYS_FSL_ESDHC_ADDR == MMC_SDHC4_BASE_ADDR gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); #else gd->arch.sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index ff73596ba903..ed890114ec48 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -84,7 +84,7 @@ static void check_erratum_a4849(uint32_t svr) static void check_erratum_a4580(uint32_t svr) { const serdes_corenet_t __iomem *srds_regs = - (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR; unsigned int lane;
for (lane = 0; lane < SRDS_MAX_LANES; lane++) { diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 432d4b11dcf3..49a1aac42b53 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -98,7 +98,7 @@ int checkcpu (void) #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) if (SVR_SOC_VER(svr) == SVR_T4080) { ccsr_rcpm_t *rcpm = - (void __iomem *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); + (void __iomem *)(CFG_SYS_FSL_CORENET_RCPM_ADDR);
setbits_be32(&gur->devdisr2, FSL_CORENET_DEVDISR2_DTSEC1_6 || FSL_CORENET_DEVDISR2_DTSEC1_9); @@ -540,16 +540,16 @@ static void dump_spd_ddr_reg(void) for (i = 0; i < CONFIG_SYS_NUM_DDR_CTLRS; i++) { switch (i) { case 0: - ddr[i] = (void *)CONFIG_SYS_FSL_DDR_ADDR; + ddr[i] = (void *)CFG_SYS_FSL_DDR_ADDR; break; -#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) +#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) case 1: - ddr[i] = (void *)CONFIG_SYS_FSL_DDR2_ADDR; + ddr[i] = (void *)CFG_SYS_FSL_DDR2_ADDR; break; #endif -#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) +#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) case 2: - ddr[i] = (void *)CONFIG_SYS_FSL_DDR3_ADDR; + ddr[i] = (void *)CFG_SYS_FSL_DDR3_ADDR; break; #endif #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) diff --git a/arch/powerpc/cpu/mpc85xx/cpu_init.c b/arch/powerpc/cpu/mpc85xx/cpu_init.c index 46b44c51961c..2367b0932b7e 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu_init.c +++ b/arch/powerpc/cpu/mpc85xx/cpu_init.c @@ -160,7 +160,7 @@ void disable_cpc_sram(void) { int i;
- cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; + cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { if (in_be32(&cpc->cpcsrcr0) & CPC_SRCR0_SRAMEN) { @@ -217,7 +217,7 @@ void enable_cpc(void) char cpc_subarg[16]; bool have_hwconfig = false; int cpc_args = 0; - cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; + cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
/* Extract hwconfig from environment */ ret = env_get_f("hwconfig", buffer, sizeof(buffer)); @@ -271,7 +271,7 @@ void enable_cpc(void) static void invalidate_cpc(void) { int i; - cpc_corenet_t *cpc = (cpc_corenet_t *)CONFIG_SYS_FSL_CPC_ADDR; + cpc_corenet_t *cpc = (cpc_corenet_t *)CFG_SYS_FSL_CPC_ADDR;
for (i = 0; i < CONFIG_SYS_NUM_CPC; i++, cpc++) { /* skip CPC when it used as all SRAM */ @@ -300,7 +300,7 @@ static void invalidate_cpc(void) static void corenet_tb_init(void) { volatile ccsr_rcpm_t *rcpm = - (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); + (void *)(CFG_SYS_FSL_CORENET_RCPM_ADDR); volatile ccsr_pic_t *pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR); u32 whoami = in_be32(&pic->whoami); @@ -476,7 +476,7 @@ int enable_cluster_l2(void) do { int j, cluster_valid = 0;
- l2cache = (void __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000); + l2cache = (void __iomem *)(CFG_SYS_FSL_CLUSTER_1_L2 + i * 0x40000);
cluster = in_be32(&gur->tp_cluster[i].lower);
@@ -518,7 +518,7 @@ int l2cache_init(void) #ifdef CONFIG_L2_CACHE ccsr_l2cache_t *l2cache = (void __iomem *)CFG_SYS_MPC85xx_L2_ADDR; #elif defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && defined(CONFIG_E6500) - struct ccsr_cluster_l2 * l2cache = (void __iomem *)CONFIG_SYS_FSL_CLUSTER_1_L2; + struct ccsr_cluster_l2 * l2cache = (void __iomem *)CFG_SYS_FSL_CLUSTER_1_L2; #endif
puts ("L2: "); @@ -664,7 +664,7 @@ int cpu_init_r(void) const char *spin; #endif #ifdef CONFIG_SYS_FSL_ERRATUM_SEC_A003571 - ccsr_sec_t __iomem *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + ccsr_sec_t __iomem *sec = (void *)CFG_SYS_FSL_SEC_ADDR; #endif #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) || \ defined(CONFIG_SYS_FSL_ERRATUM_NMG_CPU_A011) diff --git a/arch/powerpc/cpu/mpc85xx/fdt.c b/arch/powerpc/cpu/mpc85xx/fdt.c index 266a61163f50..9d7e7d2e81eb 100644 --- a/arch/powerpc/cpu/mpc85xx/fdt.c +++ b/arch/powerpc/cpu/mpc85xx/fdt.c @@ -164,7 +164,7 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) static inline void ft_fixup_l3cache(void *blob, int off) { u32 line_size, num_ways, size, num_sets; - cpc_corenet_t *cpc = (void *)CONFIG_SYS_FSL_CPC_ADDR; + cpc_corenet_t *cpc = (void *)CFG_SYS_FSL_CPC_ADDR; u32 cfg0 = in_be32(&cpc->cpccfg0);
size = CPC_CFG0_SZ_K(cfg0) * 1024 * CONFIG_SYS_NUM_CPC; @@ -299,7 +299,7 @@ static inline void ft_fixup_l2cache(void *blob) u32 l2cfg0 = mfspr(SPRN_L2CFG0); #else struct ccsr_cluster_l2 *l2cache = - (struct ccsr_cluster_l2 __iomem *)(CONFIG_SYS_FSL_CLUSTER_1_L2); + (struct ccsr_cluster_l2 __iomem *)(CFG_SYS_FSL_CLUSTER_1_L2); u32 l2cfg0 = in_be32(&l2cache->l2cfg0); #endif u32 size, line_size, num_ways, num_sets; @@ -466,11 +466,11 @@ static void ft_fixup_dpaa_clks(void *blob)
get_sys_info(&sysinfo); #ifdef CONFIG_SYS_DPAA_FMAN - ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM1_OFFSET, + ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM1_OFFSET, sysinfo.freq_fman[0]);
#if (CONFIG_SYS_NUM_FMAN == 2) - ft_fixup_clks(blob, "fsl,fman", CONFIG_SYS_FSL_FM2_OFFSET, + ft_fixup_clks(blob, "fsl,fman", CFG_SYS_FSL_FM2_OFFSET, sysinfo.freq_fman[1]); #endif #endif @@ -611,7 +611,7 @@ void ft_cpu_setup(void *blob, struct bd_info *bd) else { ccsr_sec_t __iomem *sec;
- sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR; fdt_fixup_crypto_node(blob, sec_in32(&sec->secvid_ms)); } #endif diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c index 1a30395256b9..3a6ce32f7e6c 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet2_serdes.c @@ -21,10 +21,10 @@ static u8 serdes1_prtcl_map[SERDES_PRCTL_COUNT]; #ifdef CONFIG_SYS_FSL_SRDS_2 static u8 serdes2_prtcl_map[SERDES_PRCTL_COUNT]; #endif -#ifdef CONFIG_SYS_FSL_SRDS_3 +#ifdef CFG_SYS_FSL_SRDS_3 static u8 serdes3_prtcl_map[SERDES_PRCTL_COUNT]; #endif -#ifdef CONFIG_SYS_FSL_SRDS_4 +#ifdef CFG_SYS_FSL_SRDS_4 static u8 serdes4_prtcl_map[SERDES_PRCTL_COUNT]; #endif
@@ -104,13 +104,13 @@ int is_serdes_configured(enum srds_prtcl device)
ret |= serdes2_prtcl_map[device]; #endif -#ifdef CONFIG_SYS_FSL_SRDS_3 +#ifdef CFG_SYS_FSL_SRDS_3 if (!serdes3_prtcl_map[NONE]) fsl_serdes_init();
ret |= serdes3_prtcl_map[device]; #endif -#ifdef CONFIG_SYS_FSL_SRDS_4 +#ifdef CFG_SYS_FSL_SRDS_4 if (!serdes4_prtcl_map[NONE]) fsl_serdes_init();
@@ -139,13 +139,13 @@ int serdes_get_first_lane(u32 sd, enum srds_prtcl device) cfg >>= FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT; break; #endif -#ifdef CONFIG_SYS_FSL_SRDS_3 +#ifdef CFG_SYS_FSL_SRDS_3 case FSL_SRDS_3: cfg &= FSL_CORENET2_RCWSR4_SRDS3_PRTCL; cfg >>= FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT; break; #endif -#ifdef CONFIG_SYS_FSL_SRDS_4 +#ifdef CFG_SYS_FSL_SRDS_4 case FSL_SRDS_4: cfg &= FSL_CORENET2_RCWSR4_SRDS4_PRTCL; cfg >>= FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT; @@ -351,28 +351,28 @@ void fsl_serdes_init(void)
#ifdef CONFIG_SYS_FSL_SRDS_1 serdes_init(FSL_SRDS_1, - CONFIG_SYS_FSL_CORENET_SERDES_ADDR, + CFG_SYS_FSL_CORENET_SERDES_ADDR, FSL_CORENET2_RCWSR4_SRDS1_PRTCL, FSL_CORENET2_RCWSR4_SRDS1_PRTCL_SHIFT, serdes1_prtcl_map); #endif #ifdef CONFIG_SYS_FSL_SRDS_2 serdes_init(FSL_SRDS_2, - CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000, + CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_2 * 0x1000, FSL_CORENET2_RCWSR4_SRDS2_PRTCL, FSL_CORENET2_RCWSR4_SRDS2_PRTCL_SHIFT, serdes2_prtcl_map); #endif -#ifdef CONFIG_SYS_FSL_SRDS_3 +#ifdef CFG_SYS_FSL_SRDS_3 serdes_init(FSL_SRDS_3, - CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000, + CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_3 * 0x1000, FSL_CORENET2_RCWSR4_SRDS3_PRTCL, FSL_CORENET2_RCWSR4_SRDS3_PRTCL_SHIFT, serdes3_prtcl_map); #endif -#ifdef CONFIG_SYS_FSL_SRDS_4 +#ifdef CFG_SYS_FSL_SRDS_4 serdes_init(FSL_SRDS_4, - CONFIG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000, + CFG_SYS_FSL_CORENET_SERDES_ADDR + FSL_SRDS_4 * 0x1000, FSL_CORENET2_RCWSR4_SRDS4_PRTCL, FSL_CORENET2_RCWSR4_SRDS4_PRTCL_SHIFT, serdes4_prtcl_map); diff --git a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c index 1d35733c013d..437ecde61559 100644 --- a/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c +++ b/arch/powerpc/cpu/mpc85xx/fsl_corenet_serdes.c @@ -109,7 +109,7 @@ int serdes_get_bank_by_lane(int lane) int serdes_lane_enabled(int lane) { ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR;
int bank = lanes[lane].bank; int word = lanes[lane].lpd / 32; @@ -257,7 +257,7 @@ void serdes_reset_rx(enum srds_prtcl device) if (unlikely((in_be32(&gur->rcwsr[5]) & 0x2000) == 0)) return;
- regs = (typeof(regs))CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + regs = (typeof(regs))CFG_SYS_FSL_CORENET_SERDES_ADDR; prtcl = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26;
__serdes_reset_rx(regs, prtcl, device); @@ -466,7 +466,7 @@ static void p4080_erratum_serdes_a005(serdes_corenet_t *regs, unsigned int cfg) static void wait_for_rstdone(unsigned int bank) { serdes_corenet_t *srds_regs = - (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR; unsigned long long end_tick; u32 rstctl;
@@ -527,7 +527,7 @@ void fsl_serdes_init(void) if (!(in_be32(&gur->rcwsr[5]) & FSL_CORENET_RCWSR5_SRDS_EN)) return;
- srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR); + srds_regs = (void *)(CFG_SYS_FSL_CORENET_SERDES_ADDR); cfg = (in_be32(&gur->rcwsr[4]) & FSL_CORENET_RCWSR4_SRDS_PRTCL) >> 26; debug("Using SERDES configuration 0x%x, lane settings:\n", cfg);
@@ -601,7 +601,7 @@ void fsl_serdes_init(void) serdes_prtcl_map |= 1 << SATA1 | 1 << SATA2; break; default: - srds2_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES2_ADDR; + srds2_regs = (void *)CFG_SYS_FSL_CORENET_SERDES2_ADDR;
/* We don't need bank 4, so power it down */ setbits_be32(&srds2_regs->bank[0].rstctl, SRDS_RSTCTL_SDPD); diff --git a/arch/powerpc/cpu/mpc85xx/liodn.c b/arch/powerpc/cpu/mpc85xx/liodn.c index a08400249492..3aa3ca4c3ee0 100644 --- a/arch/powerpc/cpu/mpc85xx/liodn.c +++ b/arch/powerpc/cpu/mpc85xx/liodn.c @@ -76,7 +76,7 @@ static void set_fman_liodn(struct fman_liodn_id_table *tbl, int size)
static void setup_sec_liodn_base(void) { - ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + ccsr_sec_t *sec = (void *)CFG_SYS_FSL_SEC_ADDR; u32 base;
if (!IS_E_PROCESSOR(get_svr())) @@ -101,12 +101,12 @@ static void setup_fman_liodn_base(enum fsl_dpaa_dev dev,
switch(dev) { case FSL_HW_PORTAL_FMAN1: - fm = (void *)CONFIG_SYS_FSL_FM1_ADDR; + fm = (void *)CFG_SYS_FSL_FM1_ADDR; break;
#if (CONFIG_SYS_NUM_FMAN == 2) case FSL_HW_PORTAL_FMAN2: - fm = (void *)CONFIG_SYS_FSL_FM2_ADDR; + fm = (void *)CFG_SYS_FSL_FM2_ADDR; break; #endif default: @@ -130,7 +130,7 @@ static void setup_fman_liodn_base(enum fsl_dpaa_dev dev, static void setup_pme_liodn_base(void) { #ifdef CONFIG_SYS_DPAA_PME - ccsr_pme_t *pme = (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR; + ccsr_pme_t *pme = (void *)CFG_SYS_FSL_CORENET_PME_ADDR; u32 base = (liodn_bases[FSL_HW_PORTAL_PME].id[0] << 16) | liodn_bases[FSL_HW_PORTAL_PME].id[1];
@@ -141,7 +141,7 @@ static void setup_pme_liodn_base(void) #ifdef CONFIG_SYS_FSL_RAID_ENGINE static void setup_raide_liodn_base(void) { - struct ccsr_raide *raide = (void *)CONFIG_SYS_FSL_RAID_ENGINE_ADDR; + struct ccsr_raide *raide = (void *)CFG_SYS_FSL_RAID_ENGINE_ADDR;
/* setup raid engine liodn base for data/desc ; both set to 47 */ u32 base = (liodn_bases[FSL_HW_PORTAL_RAID_ENGINE].id[0] << 16) | @@ -155,7 +155,7 @@ static void setup_raide_liodn_base(void) static void set_rman_liodn(struct liodn_id_table *tbl, int size) { int i; - struct ccsr_rman *rman = (void *)CONFIG_SYS_FSL_CORENET_RMAN_ADDR; + struct ccsr_rman *rman = (void *)CFG_SYS_FSL_CORENET_RMAN_ADDR;
for (i = 0; i < size; i++) { /* write the RMan block number */ @@ -168,7 +168,7 @@ static void set_rman_liodn(struct liodn_id_table *tbl, int size) static void setup_rman_liodn_base(struct liodn_id_table *tbl, int size) { int i; - struct ccsr_rman *rman = (void *)CONFIG_SYS_FSL_CORENET_RMAN_ADDR; + struct ccsr_rman *rman = (void *)CFG_SYS_FSL_CORENET_RMAN_ADDR; u32 base = liodn_bases[FSL_HW_PORTAL_RMAN].id[0];
out_be32(&rman->mmliodnbr, base); diff --git a/arch/powerpc/cpu/mpc85xx/mp.c b/arch/powerpc/cpu/mpc85xx/mp.c index e1469eb296a0..f109ecb9ff76 100644 --- a/arch/powerpc/cpu/mpc85xx/mp.c +++ b/arch/powerpc/cpu/mpc85xx/mp.c @@ -265,8 +265,8 @@ static void plat_mp_up(unsigned long bootpg, unsigned int pagesize) struct law_entry e;
gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); - ccm = (void *)(CONFIG_SYS_FSL_CORENET_CCM_ADDR); - rcpm = (void *)(CONFIG_SYS_FSL_CORENET_RCPM_ADDR); + ccm = (void *)(CFG_SYS_FSL_CORENET_CCM_ADDR); + rcpm = (void *)(CFG_SYS_FSL_CORENET_RCPM_ADDR); pic = (void *)(CFG_SYS_MPC8xxx_PIC_ADDR);
whoami = in_be32(&pic->whoami); diff --git a/arch/powerpc/cpu/mpc85xx/speed.c b/arch/powerpc/cpu/mpc85xx/speed.c index a7004a670bbc..31d048192767 100644 --- a/arch/powerpc/cpu/mpc85xx/speed.c +++ b/arch/powerpc/cpu/mpc85xx/speed.c @@ -26,14 +26,14 @@ void get_sys_info(sys_info_t *sys_info) { volatile ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_FSL_CORENET - volatile ccsr_clk_t *clk = (void *)(CONFIG_SYS_FSL_CORENET_CLK_ADDR); + volatile ccsr_clk_t *clk = (void *)(CFG_SYS_FSL_CORENET_CLK_ADDR); unsigned int cpu; #ifdef CONFIG_HETROGENOUS_CLUSTERS unsigned int dsp_cpu; uint rcw_tmp1, rcw_tmp2; #endif #ifdef CONFIG_SYS_FSL_QORIQ_CHASSIS2 - int cc_group[12] = CONFIG_SYS_FSL_CLUSTER_CLOCKS; + int cc_group[12] = CFG_SYS_FSL_CLUSTER_CLOCKS; #endif __maybe_unused u32 svr;
diff --git a/arch/powerpc/cpu/mpc85xx/start.S b/arch/powerpc/cpu/mpc85xx/start.S index 024414e9ff96..534175697435 100644 --- a/arch/powerpc/cpu/mpc85xx/start.S +++ b/arch/powerpc/cpu/mpc85xx/start.S @@ -966,7 +966,7 @@ delete_ccsr_l2_tlb: erratum_set_dcsr 0xb0e38 0xe0400000 erratum_set_dcsr 0xb0008 0x00900000 erratum_set_dcsr 0xb0e40 0xe00a0000 - erratum_set_ccsr 0x18600 CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY + erratum_set_ccsr 0x18600 CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY #ifdef CONFIG_RAMBOOT_PBL erratum_set_ccsr 0x10f00 0x495e5000 #else diff --git a/arch/powerpc/cpu/mpc8xxx/law.c b/arch/powerpc/cpu/mpc8xxx/law.c index 38ceb8a93749..bcbbb7416b9b 100644 --- a/arch/powerpc/cpu/mpc8xxx/law.c +++ b/arch/powerpc/cpu/mpc8xxx/law.c @@ -20,7 +20,7 @@ DECLARE_GLOBAL_DATA_PTR; #define FSL_HW_NUM_LAWS CONFIG_SYS_FSL_NUM_LAWS
#ifdef CONFIG_FSL_CORENET -#define LAW_BASE (CONFIG_SYS_FSL_CORENET_CCM_ADDR) +#define LAW_BASE (CFG_SYS_FSL_CORENET_CCM_ADDR) #define LAWAR_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawar) #define LAWBARH_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarh) #define LAWBARL_ADDR(x) (&((ccsr_local_t *)LAW_BASE)->law[x].lawbarl) diff --git a/arch/powerpc/cpu/mpc8xxx/srio.c b/arch/powerpc/cpu/mpc8xxx/srio.c index 62524a243365..c815d19384bd 100644 --- a/arch/powerpc/cpu/mpc8xxx/srio.c +++ b/arch/powerpc/cpu/mpc8xxx/srio.c @@ -79,9 +79,9 @@ static int srio_erratum_a004034(u8 port) int idx, first, last; u32 i; unsigned long long end_tick; - struct ccsr_rio *srio_regs = (void *)CONFIG_SYS_FSL_SRIO_ADDR; + struct ccsr_rio *srio_regs = (void *)CFG_SYS_FSL_SRIO_ADDR;
- srds_regs = (void *)(CONFIG_SYS_FSL_CORENET_SERDES_ADDR); + srds_regs = (void *)(CFG_SYS_FSL_CORENET_SERDES_ADDR); conf_lane = (in_be32((void *)&srds_regs->srdspccr0) >> (12 - port * 4)) & 0x3; init_lane = (in_be32((void *)&srio_regs->lp_serial @@ -291,7 +291,7 @@ void srio_init(void) #ifdef CONFIG_SRIO_PCIE_BOOT_MASTER void srio_boot_master(int port) { - struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; + struct ccsr_rio *srio = (void *)CFG_SYS_FSL_SRIO_ADDR;
/* set port accept-all */ out_be32((void *)&srio->impl.port[port - 1].ptaacr, @@ -343,7 +343,7 @@ void srio_boot_master(int port)
void srio_boot_master_release_slave(int port) { - struct ccsr_rio *srio = (void *)CONFIG_SYS_FSL_SRIO_ADDR; + struct ccsr_rio *srio = (void *)CFG_SYS_FSL_SRIO_ADDR; u32 escsr; debug("SRIOBOOT - MASTER: " "Check the port status and release slave core ...\n"); diff --git a/arch/powerpc/include/asm/config_mpc85xx.h b/arch/powerpc/include/asm/config_mpc85xx.h index d3d4e9c053f4..25d1b4861746 100644 --- a/arch/powerpc/include/asm/config_mpc85xx.h +++ b/arch/powerpc/include/asm/config_mpc85xx.h @@ -17,10 +17,10 @@ #include <fsl_ddrc_version.h>
#if defined(CONFIG_ARCH_MPC8548) -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 1 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 +#define CFG_SYS_FSL_SRIO_MAX_PORTS 1 +#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_P1010) #define CONFIG_FSL_SDHC_V2_3 @@ -59,30 +59,30 @@ #define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_ARCH_P2020) -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 +#define CFG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2
#elif defined(CONFIG_ARCH_P2041) /* also supports P2040 */ #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 +#define CFG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P3041) #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 +#define CFG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_P4080) /* also supports P4040 */ #define CONFIG_SYS_NUM_FMAN 2 @@ -91,11 +91,11 @@ #define CONFIG_SYS_NUM_FM1_10GEC 1 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 -#define CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 -#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000 +#define CFG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CFG_SYS_FSL_SRIO_MSG_UNIT_NUM 2 +#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xff000000
#elif defined(CONFIG_ARCH_P5040) #define CONFIG_SYS_NUM_FMAN 2 @@ -104,7 +104,7 @@ #define CONFIG_SYS_NUM_FM2_DTSEC 5 #define CONFIG_SYS_NUM_FM2_10GEC 1 #define CONFIG_SYS_FM_MURAM_SIZE 0x28000 -#define CONFIG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000 +#define CFG_SYS_FSL_CORENET_SNOOPVEC_COREONLY 0xf0000000
#elif defined(CONFIG_ARCH_BSC9131) #define CONFIG_FSL_SDHC_V2_3 @@ -118,7 +118,7 @@
#elif defined(CONFIG_ARCH_T4240) #ifdef CONFIG_ARCH_T4240 -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } +#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 2 #define CONFIG_SYS_NUM_FM2_DTSEC 8 @@ -131,17 +131,17 @@ #endif #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_FSL_SRDS_2 -#define CONFIG_SYS_FSL_SRDS_3 -#define CONFIG_SYS_FSL_SRDS_4 +#define CFG_SYS_FSL_SRDS_3 +#define CFG_SYS_FSL_SRDS_4 #define CONFIG_SYS_NUM_FMAN 2 #define CONFIG_SYS_PME_CLK 0 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 #define CONFIG_SYS_FM1_CLK 3 #define CONFIG_SYS_FM2_CLK 3 #define CONFIG_SYS_FM_MURAM_SIZE 0x60000 -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CFG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5
#elif defined(CONFIG_ARCH_B4860) || defined(CONFIG_ARCH_B4420) #define CONFIG_SYS_FSL_SRDS_1 @@ -154,21 +154,21 @@ #ifdef CONFIG_ARCH_B4860 #define CONFIG_MAX_DSP_CPUS 12 #define CONFIG_NUM_DSP_CPUS 6 -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } +#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 6 #define CONFIG_SYS_NUM_FM1_10GEC 2 -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CFG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 #else #define CONFIG_MAX_DSP_CPUS 2 -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } +#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4 } #define CONFIG_SYS_NUM_FM1_DTSEC 4 #define CONFIG_SYS_NUM_FM1_10GEC 0 #endif
#elif defined(CONFIG_ARCH_T1040) || defined(CONFIG_ARCH_T1042) -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } +#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 5 @@ -184,8 +184,7 @@ #define QE_NUM_OF_SNUM 28
#elif defined(CONFIG_ARCH_T1024) -#define CONFIG_SYS_FSL_NUM_CC_PLL 2 -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } +#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 1, 1, 1 } #define CONFIG_SYS_FSL_SRDS_1 #define CONFIG_SYS_NUM_FMAN 1 #define CONFIG_SYS_NUM_FM1_DTSEC 4 @@ -202,15 +201,15 @@
#elif defined(CONFIG_ARCH_T2080) #define CONFIG_SYS_NUM_FMAN 1 -#define CONFIG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } +#define CFG_SYS_FSL_CLUSTER_CLOCKS { 1, 4, 4, 4 } #define CONFIG_SYS_FSL_SRDS_1 #if defined(CONFIG_ARCH_T2080) #define CONFIG_SYS_NUM_FM1_DTSEC 8 #define CONFIG_SYS_NUM_FM1_10GEC 4 #define CONFIG_SYS_FSL_SRDS_2 -#define CONFIG_SYS_FSL_SRIO_MAX_PORTS 2 -#define CONFIG_SYS_FSL_SRIO_OB_WIN_NUM 9 -#define CONFIG_SYS_FSL_SRIO_IB_WIN_NUM 5 +#define CFG_SYS_FSL_SRIO_MAX_PORTS 2 +#define CFG_SYS_FSL_SRIO_OB_WIN_NUM 9 +#define CFG_SYS_FSL_SRIO_IB_WIN_NUM 5 #endif #define CONFIG_PME_PLAT_CLK_DIV 1 #define CONFIG_SYS_PME_CLK CONFIG_PME_PLAT_CLK_DIV @@ -224,7 +223,7 @@ #define CONFIG_FSL_SDHC_V2_3 #define CONFIG_TSECV2_1 #define CONFIG_SYS_FSL_IFC_BANK_COUNT 8 -#define CONFIG_SYS_FSL_SEC_IDX_OFFSET 0x20000 +#define CFG_SYS_FSL_SEC_IDX_OFFSET 0x20000
#endif
diff --git a/arch/powerpc/include/asm/fsl_liodn.h b/arch/powerpc/include/asm/fsl_liodn.h index be55f99030e8..de85bcfdcf96 100644 --- a/arch/powerpc/include/asm/fsl_liodn.h +++ b/arch/powerpc/include/asm/fsl_liodn.h @@ -33,7 +33,7 @@ struct srio_liodn_id_table { { .id = { id_a }, .num_ids = 1, .portid = port, \ .reg_offset[0] = offsetof(struct ccsr_rio, liodn) \ + (port - 1) * 0x200 \ - + CONFIG_SYS_FSL_SRIO_ADDR, \ + + CFG_SYS_FSL_SRIO_ADDR, \ }
struct liodn_id_table { @@ -130,29 +130,29 @@ extern void fdt_fixup_liodn(void *blob); #define SET_QMAN_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,qman", liodn, \ offsetof(struct ccsr_qman, liodnr) + \ - CONFIG_SYS_FSL_QMAN_OFFSET, \ - CONFIG_SYS_FSL_QMAN_OFFSET) + CFG_SYS_FSL_QMAN_OFFSET, \ + CFG_SYS_FSL_QMAN_OFFSET)
#define SET_BMAN_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,bman", liodn, \ offsetof(struct ccsr_bman, liodnr) + \ - CONFIG_SYS_FSL_BMAN_OFFSET, \ - CONFIG_SYS_FSL_BMAN_OFFSET) + CFG_SYS_FSL_BMAN_OFFSET, \ + CFG_SYS_FSL_BMAN_OFFSET)
#define SET_PME_LIODN(liodn) \ SET_LIODN_ENTRY_1("fsl,pme", liodn, offsetof(ccsr_pme_t, liodnr) + \ - CONFIG_SYS_FSL_CORENET_PME_OFFSET, \ - CONFIG_SYS_FSL_CORENET_PME_OFFSET) + CFG_SYS_FSL_CORENET_PME_OFFSET, \ + CFG_SYS_FSL_CORENET_PME_OFFSET)
#define SET_PMAN_LIODN(num, liodn) \ SET_LIODN_ENTRY_2("fsl,pman", liodn, 0, \ offsetof(struct ccsr_pman, ppa1) + \ - CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \ - CONFIG_SYS_FSL_CORENET_PMAN##num##_OFFSET) + CFG_SYS_FSL_CORENET_PMAN##num##_OFFSET, \ + CFG_SYS_FSL_CORENET_PMAN##num##_OFFSET)
/* -1 from portID due to how immap has the registers */ #define FM_PPID_RX_PORT_OFFSET(fmNum, portID) \ - CONFIG_SYS_FSL_FM##fmNum##_OFFSET + \ + CFG_SYS_FSL_FM##fmNum##_OFFSET + \ offsetof(struct ccsr_fman, fm_bmi_common.fmbm_ppid[portID - 1])
#ifdef CONFIG_SYS_FMAN_V3 @@ -160,31 +160,31 @@ extern void fdt_fixup_liodn(void *blob); #define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \ SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-1g-rx", \ liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ - CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) + CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */ #define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \ SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \ liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ - CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) + CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET)
/* enetNum is 0, 1, 2... so we + 8 for type-2 10g to get to HW Port ID */ #define SET_FMAN_RX_10G_TYPE2_LIODN(fmNum, enetNum, liodn) \ SET_FMAN_LIODN_ENTRY("fsl,fman-v3-port-rx", "fsl,fman-port-10g-rx", \ liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ - CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) + CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) #else /* enetNum is 0, 1, 2... so we + 8 for 1g to get to HW Port ID */ #define SET_FMAN_RX_1G_LIODN(fmNum, enetNum, liodn) \ SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-1g-rx", \ liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 8), \ - CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET) + CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_1G_OFFSET)
/* enetNum is 0, 1, 2... so we + 16 for 10g to get to HW Port ID */ #define SET_FMAN_RX_10G_LIODN(fmNum, enetNum, liodn) \ SET_FMAN_LIODN_ENTRY("fsl,fman-v2-port-rx", "fsl,fman-port-10g-rx", \ liodn, FM_PPID_RX_PORT_OFFSET(fmNum, enetNum + 16), \ - CONFIG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) + CFG_SYS_FSL_FM##fmNum##_RX##enetNum##_10G_OFFSET) #endif /* * handle both old and new versioned SEC properties: @@ -193,44 +193,44 @@ extern void fdt_fixup_liodn(void *blob); #define SET_SEC_JR_LIODN_ENTRY(jrNum, liodnA, liodnB) \ SET_LIODN_ENTRY_2("fsl,sec4.0-job-ring", liodnA, liodnB,\ offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \ - CONFIG_SYS_FSL_SEC_OFFSET, \ - CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \ + CFG_SYS_FSL_SEC_OFFSET, \ + CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum), \ SET_LIODN_ENTRY_2("fsl,sec-v4.0-job-ring", liodnA, liodnB,\ offsetof(ccsr_sec_t, jrliodnr[jrNum].ls) + \ - CONFIG_SYS_FSL_SEC_OFFSET, \ - CONFIG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum) + CFG_SYS_FSL_SEC_OFFSET, \ + CFG_SYS_FSL_SEC_OFFSET + 0x1000 + 0x1000 * jrNum)
/* This is a bit evil since we treat rtic param as both a string & hex value */ #define SET_SEC_RTIC_LIODN_ENTRY(rtic, liodnA) \ SET_LIODN_ENTRY_1("fsl,sec4.0-rtic-memory", \ liodnA, \ offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ - CONFIG_SYS_FSL_SEC_OFFSET, \ - CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \ + CFG_SYS_FSL_SEC_OFFSET, \ + CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)), \ SET_LIODN_ENTRY_1("fsl,sec-v4.0-rtic-memory", \ liodnA, \ offsetof(ccsr_sec_t, rticliodnr[0x##rtic-0xa].ls) + \ - CONFIG_SYS_FSL_SEC_OFFSET, \ - CONFIG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa)) + CFG_SYS_FSL_SEC_OFFSET, \ + CFG_SYS_FSL_SEC_OFFSET + 0x6100 + 0x20 * (0x##rtic-0xa))
#define SET_SEC_DECO_LIODN_ENTRY(num, liodnA, liodnB) \ SET_LIODN_ENTRY_2(NULL, liodnA, liodnB, \ offsetof(ccsr_sec_t, decoliodnr[num].ls) + \ - CONFIG_SYS_FSL_SEC_OFFSET, 0) + CFG_SYS_FSL_SEC_OFFSET, 0)
#define SET_RAID_ENGINE_JQ_LIODN_ENTRY(jqNum, rNum, liodnA) \ SET_LIODN_ENTRY_1("fsl,raideng-v1.0-job-ring", \ liodnA, \ offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg1) + \ - CONFIG_SYS_FSL_RAID_ENGINE_OFFSET, \ + CFG_SYS_FSL_RAID_ENGINE_OFFSET, \ offsetof(struct ccsr_raide, jq[jqNum].ring[rNum].cfg0) + \ - CONFIG_SYS_FSL_RAID_ENGINE_OFFSET) + CFG_SYS_FSL_RAID_ENGINE_OFFSET)
#define SET_RMAN_LIODN(ibNum, liodn) \ SET_LIODN_ENTRY_1("fsl,rman-inbound-block", liodn, \ offsetof(struct ccsr_rman, mmitdr) + \ - CONFIG_SYS_FSL_CORENET_RMAN_OFFSET, \ - CONFIG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000) + CFG_SYS_FSL_CORENET_RMAN_OFFSET, \ + CFG_SYS_FSL_CORENET_RMAN_OFFSET + ibNum * 0x1000)
extern struct liodn_id_table liodn_tbl[], liodn_bases[], sec_liodn_tbl[]; extern struct liodn_id_table raide_liodn_tbl[]; diff --git a/arch/powerpc/include/asm/immap_83xx.h b/arch/powerpc/include/asm/immap_83xx.h index 0bf5b9c2ba57..8e1820267088 100644 --- a/arch/powerpc/include/asm/immap_83xx.h +++ b/arch/powerpc/include/asm/immap_83xx.h @@ -862,7 +862,7 @@ struct ccsr_gpio { };
#define CFG_SYS_MPC8xxx_DDR_OFFSET (0x2000) -#define CONFIG_SYS_FSL_DDR_ADDR \ +#define CFG_SYS_FSL_DDR_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET) #define CFG_SYS_MPC83xx_DMA_OFFSET (0x8000) #define CFG_SYS_MPC83xx_DMA_ADDR \ diff --git a/arch/powerpc/include/asm/immap_85xx.h b/arch/powerpc/include/asm/immap_85xx.h index 7a7a7f2113c6..c9ced5474c2c 100644 --- a/arch/powerpc/include/asm/immap_85xx.h +++ b/arch/powerpc/include/asm/immap_85xx.h @@ -963,7 +963,7 @@ struct rio_lp_serial { u32 prtoccsr; /* Port Response Time-out CCSR */ u8 res1[20]; u32 pgccsr; /* Port General CSR */ - struct rio_lp_serial_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; + struct rio_lp_serial_port port[CFG_SYS_FSL_SRIO_MAX_PORTS]; };
/* Logical error reporting registers */ @@ -993,7 +993,7 @@ struct rio_phys_err_port {
/* Physical error reporting registers */ struct rio_phys_err { - struct rio_phys_err_port port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; + struct rio_phys_err_port port[CFG_SYS_FSL_SRIO_MAX_PORTS]; };
/* Implementation Space: General Port-Common */ @@ -1033,7 +1033,7 @@ struct rio_impl_port_spec { /* Implementation Space: register */ struct rio_implement { struct rio_impl_common com; - struct rio_impl_port_spec port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; + struct rio_impl_port_spec port[CFG_SYS_FSL_SRIO_MAX_PORTS]; };
/* Revision Control Register */ @@ -1061,13 +1061,13 @@ struct rio_atmu_riw {
/* ATMU window registers */ struct rio_atmu_win { - struct rio_atmu_row outbw[CONFIG_SYS_FSL_SRIO_OB_WIN_NUM]; + struct rio_atmu_row outbw[CFG_SYS_FSL_SRIO_OB_WIN_NUM]; u8 res0[64]; - struct rio_atmu_riw inbw[CONFIG_SYS_FSL_SRIO_IB_WIN_NUM]; + struct rio_atmu_riw inbw[CFG_SYS_FSL_SRIO_IB_WIN_NUM]; };
struct rio_atmu { - struct rio_atmu_win port[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; + struct rio_atmu_win port[CFG_SYS_FSL_SRIO_MAX_PORTS]; };
#ifdef CONFIG_SYS_FSL_RMU @@ -1154,7 +1154,7 @@ struct ccsr_rio { struct rio_atmu atmu; #ifdef CONFIG_SYS_FSL_RMU u8 res5[8192]; - struct rio_msg msg[CONFIG_SYS_FSL_SRIO_MSG_UNIT_NUM]; + struct rio_msg msg[CFG_SYS_FSL_SRIO_MSG_UNIT_NUM]; u8 res6[512]; struct rio_dbell dbell; u8 res7[100]; @@ -1162,7 +1162,7 @@ struct ccsr_rio { #endif #ifdef CONFIG_SYS_FSL_SRIO_LIODN u8 res5[8192]; - struct rio_liodn liodn[CONFIG_SYS_FSL_SRIO_MAX_PORTS]; + struct rio_liodn liodn[CFG_SYS_FSL_SRIO_MAX_PORTS]; #endif }; #endif @@ -2431,17 +2431,17 @@ struct ccsr_pman { #endif
#ifdef CONFIG_FSL_CORENET -#define CONFIG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 +#define CFG_SYS_FSL_CORENET_CCM_OFFSET 0x0000 #ifdef CONFIG_SYS_PMAN -#define CONFIG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000 -#define CONFIG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000 -#define CONFIG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000 +#define CFG_SYS_FSL_CORENET_PMAN1_OFFSET 0x4000 +#define CFG_SYS_FSL_CORENET_PMAN2_OFFSET 0x5000 +#define CFG_SYS_FSL_CORENET_PMAN3_OFFSET 0x6000 #endif #define CFG_SYS_MPC8xxx_DDR_OFFSET 0x8000 #define CFG_SYS_MPC8xxx_DDR2_OFFSET 0x9000 #define CFG_SYS_MPC8xxx_DDR3_OFFSET 0xA000 -#define CONFIG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 -#define CONFIG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 +#define CFG_SYS_FSL_CORENET_CLK_OFFSET 0xE1000 +#define CFG_SYS_FSL_CORENET_RCPM_OFFSET 0xE2000 #ifdef CONFIG_SYS_FSL_SFP_VER_3_0 /* In SFPv3, OSPR register is now at offset 0x200. * * So directly mapping sfp register map to this address */ @@ -2450,13 +2450,13 @@ struct ccsr_pman { #else #define CONFIG_SYS_SFP_OFFSET 0xE8000 #endif -#define CONFIG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 -#define CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000 -#define CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000 -#define CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000 -#define CONFIG_SYS_FSL_CPC_OFFSET 0x10000 -#define CONFIG_SYS_FSL_SCFG_OFFSET 0xFC000 -#define CONFIG_SYS_FSL_PAMU_OFFSET 0x20000 +#define CFG_SYS_FSL_CORENET_SERDES_OFFSET 0xEA000 +#define CFG_SYS_FSL_CORENET_SERDES2_OFFSET 0xEB000 +#define CFG_SYS_FSL_CORENET_SERDES3_OFFSET 0xEC000 +#define CFG_SYS_FSL_CORENET_SERDES4_OFFSET 0xED000 +#define CFG_SYS_FSL_CPC_OFFSET 0x10000 +#define CFG_SYS_FSL_SCFG_OFFSET 0xFC000 +#define CFG_SYS_FSL_PAMU_OFFSET 0x20000 #define CFG_SYS_MPC85xx_DMA1_OFFSET 0x100000 #define CFG_SYS_MPC85xx_DMA2_OFFSET 0x101000 #define CFG_SYS_MPC85xx_DMA3_OFFSET 0x102000 @@ -2468,7 +2468,7 @@ struct ccsr_pman { #define CFG_SYS_MPC85xx_GPIO_OFFSET 0x130000 #define CFG_SYS_MPC85xx_TDM_OFFSET 0x185000 #define CFG_SYS_MPC85xx_QE_OFFSET 0x140000 -#define CONFIG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 +#define CFG_SYS_FSL_CORENET_RMAN_OFFSET 0x1e0000 #if defined(CONFIG_SYS_FSL_QORIQ_CHASSIS2) && !defined(CONFIG_ARCH_B4860) && \ !defined(CONFIG_ARCH_B4420) #define CFG_SYS_MPC85xx_PCIE1_OFFSET 0x240000 @@ -2487,33 +2487,33 @@ struct ccsr_pman { #define CFG_SYS_MPC85xx_USB2_PHY_OFFSET 0x214100 #define CFG_SYS_MPC85xx_SATA1_OFFSET 0x220000 #define CFG_SYS_MPC85xx_SATA2_OFFSET 0x221000 -#define CONFIG_SYS_FSL_SEC_OFFSET 0x300000 -#define CONFIG_SYS_FSL_JR0_OFFSET 0x301000 +#define CFG_SYS_FSL_SEC_OFFSET 0x300000 +#define CFG_SYS_FSL_JR0_OFFSET 0x301000 #define CONFIG_SYS_SEC_MON_OFFSET 0x314000 -#define CONFIG_SYS_FSL_CORENET_PME_OFFSET 0x316000 -#define CONFIG_SYS_FSL_QMAN_OFFSET 0x318000 -#define CONFIG_SYS_FSL_BMAN_OFFSET 0x31a000 -#define CONFIG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000 -#define CONFIG_SYS_FSL_FM1_OFFSET 0x400000 -#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000 -#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000 -#define CONFIG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000 -#define CONFIG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000 -#define CONFIG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000 -#define CONFIG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000 -#define CONFIG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000 -#define CONFIG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000 -#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000 -#define CONFIG_SYS_FSL_FM2_OFFSET 0x500000 -#define CONFIG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000 -#define CONFIG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000 -#define CONFIG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000 -#define CONFIG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000 -#define CONFIG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000 -#define CONFIG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000 -#define CONFIG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000 -#define CONFIG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000 -#define CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000 +#define CFG_SYS_FSL_CORENET_PME_OFFSET 0x316000 +#define CFG_SYS_FSL_QMAN_OFFSET 0x318000 +#define CFG_SYS_FSL_BMAN_OFFSET 0x31a000 +#define CFG_SYS_FSL_RAID_ENGINE_OFFSET 0x320000 +#define CFG_SYS_FSL_FM1_OFFSET 0x400000 +#define CFG_SYS_FSL_FM1_RX0_1G_OFFSET 0x488000 +#define CFG_SYS_FSL_FM1_RX1_1G_OFFSET 0x489000 +#define CFG_SYS_FSL_FM1_RX2_1G_OFFSET 0x48a000 +#define CFG_SYS_FSL_FM1_RX3_1G_OFFSET 0x48b000 +#define CFG_SYS_FSL_FM1_RX4_1G_OFFSET 0x48c000 +#define CFG_SYS_FSL_FM1_RX5_1G_OFFSET 0x48d000 +#define CFG_SYS_FSL_FM1_RX0_10G_OFFSET 0x490000 +#define CFG_SYS_FSL_FM1_RX1_10G_OFFSET 0x491000 +#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET 0x4e0000 +#define CFG_SYS_FSL_FM2_OFFSET 0x500000 +#define CFG_SYS_FSL_FM2_RX0_1G_OFFSET 0x588000 +#define CFG_SYS_FSL_FM2_RX1_1G_OFFSET 0x589000 +#define CFG_SYS_FSL_FM2_RX2_1G_OFFSET 0x58a000 +#define CFG_SYS_FSL_FM2_RX3_1G_OFFSET 0x58b000 +#define CFG_SYS_FSL_FM2_RX4_1G_OFFSET 0x58c000 +#define CFG_SYS_FSL_FM2_RX5_1G_OFFSET 0x58d000 +#define CFG_SYS_FSL_FM2_RX0_10G_OFFSET 0x590000 +#define CFG_SYS_FSL_FM2_RX1_10G_OFFSET 0x591000 +#define CFG_SYS_FSL_CLUSTER_1_L2_OFFSET 0xC20000 #else #define CFG_SYS_MPC85xx_ECM_OFFSET 0x0000 #define CFG_SYS_MPC8xxx_DDR_OFFSET 0x2000 @@ -2551,57 +2551,57 @@ struct ccsr_pman { #define CONFIG_SYS_MDIO1_OFFSET 0x24000 #define CFG_SYS_MPC85xx_ESDHC_OFFSET 0x2e000 #if defined(CONFIG_ARCH_C29X) -#define CONFIG_SYS_FSL_SEC_OFFSET 0x80000 -#define CONFIG_SYS_FSL_JR0_OFFSET 0x81000 +#define CFG_SYS_FSL_SEC_OFFSET 0x80000 +#define CFG_SYS_FSL_JR0_OFFSET 0x81000 #else -#define CONFIG_SYS_FSL_SEC_OFFSET 0x30000 -#define CONFIG_SYS_FSL_JR0_OFFSET 0x31000 +#define CFG_SYS_FSL_SEC_OFFSET 0x30000 +#define CFG_SYS_FSL_JR0_OFFSET 0x31000 #endif #define CFG_SYS_MPC85xx_SERDES2_OFFSET 0xE3100 #define CFG_SYS_MPC85xx_SERDES1_OFFSET 0xE3000 #define CONFIG_SYS_SEC_MON_OFFSET 0xE6000 #define CONFIG_SYS_SFP_OFFSET 0xE7000 -#define CONFIG_SYS_FSL_QMAN_OFFSET 0x88000 -#define CONFIG_SYS_FSL_BMAN_OFFSET 0x8a000 -#define CONFIG_SYS_FSL_FM1_OFFSET 0x100000 -#define CONFIG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000 -#define CONFIG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000 -#define CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000 +#define CFG_SYS_FSL_QMAN_OFFSET 0x88000 +#define CFG_SYS_FSL_BMAN_OFFSET 0x8a000 +#define CFG_SYS_FSL_FM1_OFFSET 0x100000 +#define CFG_SYS_FSL_FM1_RX0_1G_OFFSET 0x188000 +#define CFG_SYS_FSL_FM1_RX1_1G_OFFSET 0x189000 +#define CFG_SYS_FSL_FM1_DTSEC1_OFFSET 0x1e0000 #endif
#define CFG_SYS_MPC85xx_PIC_OFFSET 0x40000 #define CFG_SYS_MPC85xx_GUTS_OFFSET 0xE0000 -#define CONFIG_SYS_FSL_SRIO_OFFSET 0xC0000 - -#define CONFIG_SYS_FSL_CPC_ADDR \ - (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_CPC_OFFSET) -#define CONFIG_SYS_FSL_SCFG_ADDR \ - (CONFIG_SYS_CCSRBAR + CONFIG_SYS_FSL_SCFG_OFFSET) -#define CONFIG_SYS_FSL_QMAN_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_QMAN_OFFSET) -#define CONFIG_SYS_FSL_BMAN_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_BMAN_OFFSET) -#define CONFIG_SYS_FSL_CORENET_PME_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_PME_OFFSET) -#define CONFIG_SYS_FSL_RAID_ENGINE_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_RAID_ENGINE_OFFSET) -#define CONFIG_SYS_FSL_CORENET_RMAN_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RMAN_OFFSET) +#define CFG_SYS_FSL_SRIO_OFFSET 0xC0000 + +#define CFG_SYS_FSL_CPC_ADDR \ + (CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_CPC_OFFSET) +#define CFG_SYS_FSL_SCFG_ADDR \ + (CONFIG_SYS_CCSRBAR + CFG_SYS_FSL_SCFG_OFFSET) +#define CFG_SYS_FSL_QMAN_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_QMAN_OFFSET) +#define CFG_SYS_FSL_BMAN_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_BMAN_OFFSET) +#define CFG_SYS_FSL_CORENET_PME_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_PME_OFFSET) +#define CFG_SYS_FSL_RAID_ENGINE_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_RAID_ENGINE_OFFSET) +#define CFG_SYS_FSL_CORENET_RMAN_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_RMAN_OFFSET) #define CFG_SYS_MPC85xx_GUTS_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_GUTS_OFFSET) -#define CONFIG_SYS_FSL_CORENET_CCM_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CCM_OFFSET) -#define CONFIG_SYS_FSL_CORENET_CLK_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_CLK_OFFSET) -#define CONFIG_SYS_FSL_CORENET_RCPM_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_RCPM_OFFSET) +#define CFG_SYS_FSL_CORENET_CCM_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_CCM_OFFSET) +#define CFG_SYS_FSL_CORENET_CLK_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_CLK_OFFSET) +#define CFG_SYS_FSL_CORENET_RCPM_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_RCPM_OFFSET) #define CFG_SYS_MPC85xx_ECM_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_ECM_OFFSET) -#define CONFIG_SYS_FSL_DDR_ADDR \ +#define CFG_SYS_FSL_DDR_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR_OFFSET) -#define CONFIG_SYS_FSL_DDR2_ADDR \ +#define CFG_SYS_FSL_DDR2_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR2_OFFSET) -#define CONFIG_SYS_FSL_DDR3_ADDR \ +#define CFG_SYS_FSL_DDR3_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC8xxx_DDR3_OFFSET) #define CONFIG_SYS_LBC_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_LBC_OFFSET) @@ -2631,14 +2631,14 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES1_OFFSET) #define CFG_SYS_MPC85xx_SERDES2_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_SERDES2_OFFSET) -#define CONFIG_SYS_FSL_CORENET_SERDES_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES_OFFSET) -#define CONFIG_SYS_FSL_CORENET_SERDES2_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES2_OFFSET) -#define CONFIG_SYS_FSL_CORENET_SERDES3_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES3_OFFSET) -#define CONFIG_SYS_FSL_CORENET_SERDES4_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CORENET_SERDES4_OFFSET) +#define CFG_SYS_FSL_CORENET_SERDES_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES_OFFSET) +#define CFG_SYS_FSL_CORENET_SERDES2_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES2_OFFSET) +#define CFG_SYS_FSL_CORENET_SERDES3_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES3_OFFSET) +#define CFG_SYS_FSL_CORENET_SERDES4_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_CORENET_SERDES4_OFFSET) #define CFG_SYS_MPC85xx_USB1_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_OFFSET) #define CFG_SYS_MPC85xx_USB2_ADDR \ @@ -2647,20 +2647,20 @@ struct ccsr_pman { (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB1_PHY_OFFSET) #define CFG_SYS_MPC85xx_USB2_PHY_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_USB2_PHY_OFFSET) -#define CONFIG_SYS_FSL_SEC_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SEC_OFFSET) -#define CONFIG_SYS_FSL_JR0_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_JR0_OFFSET) -#define CONFIG_SYS_FSL_FM1_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_OFFSET) -#define CONFIG_SYS_FSL_FM1_DTSEC1_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET) -#define CONFIG_SYS_FSL_FM2_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_FM2_OFFSET) -#define CONFIG_SYS_FSL_SRIO_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_SRIO_OFFSET) +#define CFG_SYS_FSL_SEC_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_SEC_OFFSET) +#define CFG_SYS_FSL_JR0_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_JR0_OFFSET) +#define CFG_SYS_FSL_FM1_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_OFFSET) +#define CFG_SYS_FSL_FM1_DTSEC1_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM1_DTSEC1_OFFSET) +#define CFG_SYS_FSL_FM2_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_FM2_OFFSET) +#define CFG_SYS_FSL_SRIO_ADDR \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_SRIO_OFFSET) #define CONFIG_SYS_PAMU_ADDR \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_PAMU_OFFSET) + (CONFIG_SYS_IMMR + CFG_SYS_FSL_PAMU_OFFSET)
#define CONFIG_SYS_PCI1_ADDR \ (CONFIG_SYS_IMMR + CFG_SYS_MPC85xx_PCI1_OFFSET) @@ -2739,8 +2739,8 @@ struct ccsr_cluster_l2 { u32 l2erraddr; /* 0xe54 L2 cache error address */ u32 l2errctl; /* 0xe58 L2 cache error control */ }; -#define CONFIG_SYS_FSL_CLUSTER_1_L2 \ - (CONFIG_SYS_IMMR + CONFIG_SYS_FSL_CLUSTER_1_L2_OFFSET) +#define CFG_SYS_FSL_CLUSTER_1_L2 \ + (CONFIG_SYS_IMMR + CFG_SYS_FSL_CLUSTER_1_L2_OFFSET) #endif /* CONFIG_SYS_FSL_QORIQ_CHASSIS2 */
#define CONFIG_SYS_DCSR_DCFG_OFFSET 0X20000 diff --git a/board/advantech/imx8mp_rsb3720a1/spl.c b/board/advantech/imx8mp_rsb3720a1/spl.c index 74dd11545f35..6cc8c23ecf87 100644 --- a/board/advantech/imx8mp_rsb3720a1/spl.c +++ b/board/advantech/imx8mp_rsb3720a1/spl.c @@ -129,7 +129,7 @@ int board_mmc_init(struct bd_info *bis) * mmc0 USDHC1 * mmc1 USDHC2 */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: init_clk_usdhc(1); diff --git a/board/advantech/imx8qm_rom7720_a1/spl.c b/board/advantech/imx8qm_rom7720_a1/spl.c index 5fd60212df9c..22ed63979920 100644 --- a/board/advantech/imx8qm_rom7720_a1/spl.c +++ b/board/advantech/imx8qm_rom7720_a1/spl.c @@ -64,7 +64,7 @@ DECLARE_GLOBAL_DATA_PTR; #define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22) #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12)
-static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { +static struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = { {USDHC1_BASE_ADDR, 0, 8}, {USDHC2_BASE_ADDR, 0, 4}, {USDHC3_BASE_ADDR, 0, 4}, @@ -108,7 +108,7 @@ int board_mmc_init(struct bd_info *bis) * mmc1 USDHC2 * mmc2 USDHC3 */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: ret = sc_pm_set_resource_power_mode(-1, SC_R_SDHC_0, SC_PM_PW_MODE_ON); diff --git a/board/bosch/acc/acc.c b/board/bosch/acc/acc.c index dbc03c9371fe..770ca8b711b0 100644 --- a/board/bosch/acc/acc.c +++ b/board/bosch/acc/acc.c @@ -562,7 +562,7 @@ int board_mmc_init(struct bd_info *bis) * mmc0 USDHC2 * mmc1 USDHC4 */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: SETUP_IOMUX_PADS(usdhc2_pads); diff --git a/board/compulab/cl-som-imx7/cl-som-imx7.c b/board/compulab/cl-som-imx7/cl-som-imx7.c index 3ee133521860..9733a33ee2c2 100644 --- a/board/compulab/cl-som-imx7/cl-som-imx7.c +++ b/board/compulab/cl-som-imx7/cl-som-imx7.c @@ -90,7 +90,7 @@ int board_mmc_init(struct bd_info *bis) * mmc0 USDHC1 * mmc2 USDHC3 (eMMC) */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: cl_som_imx7_usdhc1_pads_set(); diff --git a/board/compulab/cm_fx6/cm_fx6.c b/board/compulab/cm_fx6/cm_fx6.c index c54bffdae450..847ac33ad6b0 100644 --- a/board/compulab/cm_fx6/cm_fx6.c +++ b/board/compulab/cm_fx6/cm_fx6.c @@ -622,7 +622,7 @@ int board_init(void) int i;
cm_fx6_set_usdhc_iomux(); - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) + for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) enable_usdhc_clk(1, i); } #endif diff --git a/board/congatec/cgtqmx8/cgtqmx8.c b/board/congatec/cgtqmx8/cgtqmx8.c index a50a052df768..e5da91fa282c 100644 --- a/board/congatec/cgtqmx8/cgtqmx8.c +++ b/board/congatec/cgtqmx8/cgtqmx8.c @@ -114,7 +114,7 @@ int board_early_init_f(void) #define USDHC1_CD_GPIO IMX_GPIO_NR(5, 22) #define USDHC2_CD_GPIO IMX_GPIO_NR(4, 12)
-static struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { +static struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = { {USDHC1_BASE_ADDR, 0, 8}, {USDHC2_BASE_ADDR, 0, 4}, {USDHC3_BASE_ADDR, 0, 4}, @@ -173,7 +173,7 @@ int board_mmc_init(struct bd_info *bis) * mmc1 (external SD card) USDHC2 * mmc2 (onboard µSD) USDHC3 */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: /* onboard eMMC */ diff --git a/board/freescale/common/arm_sleep.c b/board/freescale/common/arm_sleep.c index 733940860f55..f5bed6c35bb3 100644 --- a/board/freescale/common/arm_sleep.c +++ b/board/freescale/common/arm_sleep.c @@ -35,7 +35,7 @@ void __weak board_sleep_prepare(void)
bool is_warm_boot(void) { - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) return 1; @@ -57,7 +57,7 @@ static void dp_ddr_restore(void) { u64 *src, *dst; int i; - struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
/* get the address of ddr date from SPARECR3 */ src = (u64 *)in_le32(&scfg->sparecr[2]); @@ -71,7 +71,7 @@ static void dp_ddr_restore(void) void ls1_psci_resume_fixup(void) { u32 tmp; - struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef QIXIS_BASE void *qixis_base = (void *)QIXIS_BASE; @@ -114,7 +114,7 @@ int fsl_dp_resume(void) { u32 start_addr; void (*kernel_resume)(void); - struct ccsr_scfg __iomem *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg __iomem *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR;
if (!is_warm_boot()) return 0; diff --git a/board/freescale/common/fsl_chain_of_trust.c b/board/freescale/common/fsl_chain_of_trust.c index 3bd570a29c9b..d31ad026568b 100644 --- a/board/freescale/common/fsl_chain_of_trust.c +++ b/board/freescale/common/fsl_chain_of_trust.c @@ -30,7 +30,7 @@ #if defined(CONFIG_MPC85xx) #define CONFIG_DCFG_ADDR CFG_SYS_MPC85xx_GUTS_ADDR #else -#define CONFIG_DCFG_ADDR CONFIG_SYS_FSL_GUTS_ADDR +#define CONFIG_DCFG_ADDR CFG_SYS_FSL_GUTS_ADDR #endif
#ifdef CONFIG_SYS_FSL_CCSR_GUR_LE diff --git a/board/freescale/common/fsl_validate.c b/board/freescale/common/fsl_validate.c index bc1b855aaed0..3424d49208fe 100644 --- a/board/freescale/common/fsl_validate.c +++ b/board/freescale/common/fsl_validate.c @@ -114,7 +114,7 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) */ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 csf_hdr_addr = in_be32(&gur->scratchrw[0]);
if (memcmp((u8 *)(uintptr_t)csf_hdr_addr, @@ -130,7 +130,7 @@ int get_csf_base_addr(u32 *csf_addr, u32 *flash_base_addr) #if defined(CONFIG_ESBC_HDR_LS) static int get_ie_info_addr(uintptr_t *ie_addr) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); /* For LS-CH3, the address of IE Table is * stated in Scratch13 and scratch14 of DCFG. * Bootrom validates this table while validating uboot. diff --git a/board/freescale/common/ls102xa_stream_id.c b/board/freescale/common/ls102xa_stream_id.c index a6ee87da9f55..f754cf42fd38 100644 --- a/board/freescale/common/ls102xa_stream_id.c +++ b/board/freescale/common/ls102xa_stream_id.c @@ -9,7 +9,7 @@
void ls102xa_config_smmu_stream_id(struct smmu_stream_id *id, uint32_t num) { - void *scfg = (void *)CONFIG_SYS_FSL_SCFG_ADDR; + void *scfg = (void *)CFG_SYS_FSL_SCFG_ADDR; int i; u32 icid;
diff --git a/board/freescale/common/ns_access.c b/board/freescale/common/ns_access.c index ee8ed616cb51..a95d15c1ef39 100644 --- a/board/freescale/common/ns_access.c +++ b/board/freescale/common/ns_access.c @@ -180,7 +180,7 @@ static struct csu_ns_dev ns_dev[] = {
void set_devices_ns_access(unsigned long index, u16 val) { - u32 *base = (u32 *)CONFIG_SYS_FSL_CSU_ADDR; + u32 *base = (u32 *)CFG_SYS_FSL_CSU_ADDR; u32 *reg; uint32_t tmp;
diff --git a/board/freescale/common/vid.c b/board/freescale/common/vid.c index 3f5f33ebafbe..5ec3f2a76b19 100644 --- a/board/freescale/common/vid.c +++ b/board/freescale/common/vid.c @@ -539,7 +539,7 @@ int adjust_vdd(ulong vdd_override) { int re_enable = disable_interrupts(); #if defined(CONFIG_FSL_LSCH2) || defined(CONFIG_FSL_LSCH3) - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); #else ccsr_gur_t __iomem *gur = (void __iomem *)(CFG_SYS_MPC85xx_GUTS_ADDR); diff --git a/board/freescale/imx8mq_evk/spl.c b/board/freescale/imx8mq_evk/spl.c index b28056bb48b2..bea9ddc99604 100644 --- a/board/freescale/imx8mq_evk/spl.c +++ b/board/freescale/imx8mq_evk/spl.c @@ -121,7 +121,7 @@ int board_mmc_init(struct bd_info *bis) * mmc0 USDHC1 * mmc1 USDHC2 */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: init_clk_usdhc(0); diff --git a/board/freescale/ls1012aqds/eth.c b/board/freescale/ls1012aqds/eth.c index 27f69abf6091..38267acedde1 100644 --- a/board/freescale/ls1012aqds/eth.c +++ b/board/freescale/ls1012aqds/eth.c @@ -133,7 +133,7 @@ int pfe_eth_board_init(struct udevice *dev) struct mii_dev *bus; static const char *mdio_name; struct pfe_mdio_info mac_mdio_info; - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; u8 data8; struct pfe_eth_dev *priv = dev_get_priv(dev);
diff --git a/board/freescale/ls1012aqds/ls1012aqds.c b/board/freescale/ls1012aqds/ls1012aqds.c index 361bd5c582a2..3f70fbc35659 100644 --- a/board/freescale/ls1012aqds/ls1012aqds.c +++ b/board/freescale/ls1012aqds/ls1012aqds.c @@ -213,7 +213,7 @@ static void fdt_fsl_fixup_of_pfe(void *blob) struct pfe_prop_val prop_val; void *l_blob = blob;
- struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; unsigned int srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; srds_s1 >>= FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_SHIFT; diff --git a/board/freescale/ls1012ardb/eth.c b/board/freescale/ls1012ardb/eth.c index 565f80059656..5c661274987c 100644 --- a/board/freescale/ls1012ardb/eth.c +++ b/board/freescale/ls1012ardb/eth.c @@ -80,7 +80,7 @@ int pfe_eth_board_init(struct udevice *dev) struct mii_dev *bus; struct pfe_mdio_info mac_mdio_info; struct pfe_eth_dev *priv = dev_get_priv(dev); - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
int srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; diff --git a/board/freescale/ls1021aiot/ls1021aiot.c b/board/freescale/ls1021aiot/ls1021aiot.c index 3ed6100b7cf0..8605d064138a 100644 --- a/board/freescale/ls1021aiot/ls1021aiot.c +++ b/board/freescale/ls1021aiot/ls1021aiot.c @@ -38,7 +38,7 @@ int checkboard(void) puts("Board: LS1021AIOT\n");
#ifndef CONFIG_QSPI_BOOT - struct ccsr_gur *dcfg = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur *dcfg = (struct ccsr_gur *)CFG_SYS_FSL_GUTS_ADDR; u32 cpldrev;
cpldrev = in_be32(&dcfg->gpporcr1); @@ -51,7 +51,7 @@ int checkboard(void)
void ddrmc_init(void) { - struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; + struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR; u32 temp_sdram_cfg, tmp;
out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); @@ -111,7 +111,7 @@ int dram_init(void)
int board_early_init_f(void) { - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_TSEC_ENET /* clear BD & FR bits for BE BD's and frame data */ diff --git a/board/freescale/ls1021aqds/ls1021aqds.c b/board/freescale/ls1021aqds/ls1021aqds.c index 2eaad9e74249..d0674d014ac5 100644 --- a/board/freescale/ls1021aqds/ls1021aqds.c +++ b/board/freescale/ls1021aqds/ls1021aqds.c @@ -160,7 +160,7 @@ int dram_init(void)
int board_early_init_f(void) { - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_TSEC_ENET /* clear BD & FR bits for BE BD's and frame data */ @@ -185,7 +185,7 @@ int board_early_init_f(void) void board_init_f(ulong dummy) { #ifdef CONFIG_NAND_BOOT - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; u32 porsr1, pinctl;
/* @@ -234,7 +234,7 @@ void board_init_f(ulong dummy)
void config_etseccm_source(int etsec_gtx_125_mux) { - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
switch (etsec_gtx_125_mux) { case GE0_CLK125: @@ -308,7 +308,7 @@ int config_board_mux(int ctrl_type)
int config_serdes_mux(void) { - struct ccsr_gur *gur = (struct ccsr_gur *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur *gur = (struct ccsr_gur *)CFG_SYS_FSL_GUTS_ADDR; u32 cfg;
cfg = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK; diff --git a/board/freescale/ls1021atsn/ls1021atsn.c b/board/freescale/ls1021atsn/ls1021atsn.c index f016088670f6..d95eb734c2d2 100644 --- a/board/freescale/ls1021atsn/ls1021atsn.c +++ b/board/freescale/ls1021atsn/ls1021atsn.c @@ -28,7 +28,7 @@ DECLARE_GLOBAL_DATA_PTR; static void ddrmc_init(void) { #if (!defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD)) - struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; + struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR; u32 temp_sdram_cfg, tmp;
out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); @@ -130,7 +130,7 @@ int board_eth_init(struct bd_info *bis)
int board_early_init_f(void) { - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_TSEC_ENET /* diff --git a/board/freescale/ls1021atwr/ls1021atwr.c b/board/freescale/ls1021atwr/ls1021atwr.c index 746b35a678b0..119ae17a2c6c 100644 --- a/board/freescale/ls1021atwr/ls1021atwr.c +++ b/board/freescale/ls1021atwr/ls1021atwr.c @@ -143,7 +143,7 @@ int checkboard(void)
void ddrmc_init(void) { - struct ccsr_ddr *ddr = (struct ccsr_ddr *)CONFIG_SYS_FSL_DDR_ADDR; + struct ccsr_ddr *ddr = (struct ccsr_ddr *)CFG_SYS_FSL_DDR_ADDR; u32 temp_sdram_cfg, tmp;
out_be32(&ddr->sdram_cfg, DDR_SDRAM_CFG); @@ -288,7 +288,7 @@ static void convert_serdes_mux(int type, int need_reset)
int config_serdes_mux(void) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 protocol = in_be32(&gur->rcwsr[4]) & RCWSR4_SRDS1_PRTCL_MASK;
protocol >>= RCWSR4_SRDS1_PRTCL_SHIFT; @@ -383,7 +383,7 @@ conflict:
int board_early_init_f(void) { - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_TSEC_ENET /* clear BD & FR bits for BE BD's and frame data */ diff --git a/board/freescale/ls1043aqds/eth.c b/board/freescale/ls1043aqds/eth.c index 7bfbacde4fbd..6783ebebb59e 100644 --- a/board/freescale/ls1043aqds/eth.c +++ b/board/freescale/ls1043aqds/eth.c @@ -261,7 +261,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, void fdt_fixup_board_enet(void *fdt) { int i; - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) & @@ -302,7 +302,7 @@ int board_eth_init(struct bd_info *bis) int i, idx, lane, slot, interface; struct memac_mdio_info dtsec_mdio_info; struct memac_mdio_info tgec_mdio_info; - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 srds_s1;
srds_s1 = in_be32(&gur->rcwsr[4]) & diff --git a/board/freescale/ls1043aqds/ls1043aqds.c b/board/freescale/ls1043aqds/ls1043aqds.c index 7ac2c1ae901d..b02f649910f6 100644 --- a/board/freescale/ls1043aqds/ls1043aqds.c +++ b/board/freescale/ls1043aqds/ls1043aqds.c @@ -430,9 +430,9 @@ void board_retimer_init(void)
int board_early_init_f(void) { - u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR; + u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR; #ifdef CONFIG_HAS_FSL_XHCI_USB - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; u32 usb_pwrfault; #endif #ifdef CONFIG_LPUART @@ -475,7 +475,7 @@ int board_early_init_f(void) bool is_warm_boot(void) { #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) return 1; @@ -529,7 +529,7 @@ int board_init(void) select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0); board_retimer_init();
-#ifdef CONFIG_SYS_FSL_SERDES +#ifdef CFG_SYS_FSL_SERDES config_serdes_mux(); #endif
@@ -596,6 +596,6 @@ u16 flash_read16(void *addr) #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH) void *env_sf_get_env_addr(void) { - return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); + return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); } #endif diff --git a/board/freescale/ls1043ardb/eth.c b/board/freescale/ls1043ardb/eth.c index fa59116ce57b..00ff6028e69f 100644 --- a/board/freescale/ls1043ardb/eth.c +++ b/board/freescale/ls1043ardb/eth.c @@ -21,7 +21,7 @@ int board_eth_init(struct bd_info *bis) struct memac_mdio_info tgec_mdio_info; struct mii_dev *dev; u32 srds_s1; - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; diff --git a/board/freescale/ls1043ardb/ls1043ardb.c b/board/freescale/ls1043ardb/ls1043ardb.c index 8c91f0771fbe..799900e9c949 100644 --- a/board/freescale/ls1043ardb/ls1043ardb.c +++ b/board/freescale/ls1043ardb/ls1043ardb.c @@ -188,7 +188,7 @@ int checkboard(void)
int board_init(void) { - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_SYS_FSL_ERRATUM_A010315 erratum_a010315(); @@ -230,7 +230,7 @@ int board_init(void)
int config_board_mux(void) { - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; u32 usb_pwrfault;
if (hwconfig("qe-hdlc")) { diff --git a/board/freescale/ls1046afrwy/eth.c b/board/freescale/ls1046afrwy/eth.c index 06ccfe9e8ed5..71c4c21cd4fd 100644 --- a/board/freescale/ls1046afrwy/eth.c +++ b/board/freescale/ls1046afrwy/eth.c @@ -20,7 +20,7 @@ int board_eth_init(struct bd_info *bis) struct memac_mdio_info dtsec_mdio_info; struct mii_dev *dev; u32 srds_s1; - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; @@ -70,7 +70,7 @@ int fdt_update_ethernet_dt(void *blob) int i, prop; int offset, nodeoff; const char *path; - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; diff --git a/board/freescale/ls1046afrwy/ls1046afrwy.c b/board/freescale/ls1046afrwy/ls1046afrwy.c index 5a298cd311e4..f6e5c122ead6 100644 --- a/board/freescale/ls1046afrwy/ls1046afrwy.c +++ b/board/freescale/ls1046afrwy/ls1046afrwy.c @@ -146,7 +146,7 @@ int board_setup_core_volt(u32 vdd) void config_board_mux(void) { #ifdef CONFIG_HAS_FSL_XHCI_USB - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; u32 usb_pwrfault; /* * USB2 is used, configure mux to USB2_DRVVBUS/USB2_PWRFAULT diff --git a/board/freescale/ls1046aqds/eth.c b/board/freescale/ls1046aqds/eth.c index 13207a1a37d5..88265a399487 100644 --- a/board/freescale/ls1046aqds/eth.c +++ b/board/freescale/ls1046aqds/eth.c @@ -268,7 +268,7 @@ int board_eth_init(struct bd_info *bis) { int i, idx, lane, slot, interface; struct memac_mdio_info dtsec_mdio_info; - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 srds_s1, srds_s2; u8 brdcfg12;
diff --git a/board/freescale/ls1046aqds/ls1046aqds.c b/board/freescale/ls1046aqds/ls1046aqds.c index aa6e30e6b2a6..dfdc9f06ab14 100644 --- a/board/freescale/ls1046aqds/ls1046aqds.c +++ b/board/freescale/ls1046aqds/ls1046aqds.c @@ -300,9 +300,9 @@ int i2c_multiplexer_select_vid_channel(u8 channel)
int board_early_init_f(void) { - u32 __iomem *cntcr = (u32 *)CONFIG_SYS_FSL_TIMER_ADDR; + u32 __iomem *cntcr = (u32 *)CFG_SYS_FSL_TIMER_ADDR; #ifdef CONFIG_HAS_FSL_XHCI_USB - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; u32 usb_pwrfault; #endif #ifdef CONFIG_LPUART @@ -347,7 +347,7 @@ int board_early_init_f(void) bool is_warm_boot(void) { #define DCFG_CCSR_CRSTSR_WDRFR (1 << 3) - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
if (in_be32(&gur->crstsr) & DCFG_CCSR_CRSTSR_WDRFR) return 1; @@ -395,7 +395,7 @@ int board_init(void) { select_i2c_ch_pca9547(I2C_MUX_CH_DEFAULT, 0);
-#ifdef CONFIG_SYS_FSL_SERDES +#ifdef CFG_SYS_FSL_SERDES config_serdes_mux(); #endif
@@ -479,6 +479,6 @@ u16 flash_read16(void *addr) #if defined(CONFIG_TFABOOT) && defined(CONFIG_ENV_IS_IN_SPI_FLASH) void *env_sf_get_env_addr(void) { - return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); + return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); } #endif diff --git a/board/freescale/ls1046ardb/eth.c b/board/freescale/ls1046ardb/eth.c index a3e147a48b98..04fa57f81b29 100644 --- a/board/freescale/ls1046ardb/eth.c +++ b/board/freescale/ls1046ardb/eth.c @@ -22,7 +22,7 @@ int board_eth_init(struct bd_info *bis) struct memac_mdio_info tgec_mdio_info; struct mii_dev *dev; u32 srds_s1; - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; @@ -84,7 +84,7 @@ int fdt_update_ethernet_dt(void *blob) int i, prop; int offset, nodeoff; const char *path; - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
srds_s1 = in_be32(&gur->rcwsr[4]) & FSL_CHASSIS2_RCWSR4_SRDS1_PRTCL_MASK; diff --git a/board/freescale/ls1046ardb/ls1046ardb.c b/board/freescale/ls1046ardb/ls1046ardb.c index 05269fccd6ab..1d12d9189b78 100644 --- a/board/freescale/ls1046ardb/ls1046ardb.c +++ b/board/freescale/ls1046ardb/ls1046ardb.c @@ -80,7 +80,7 @@ int checkboard(void)
int board_init(void) { - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
#ifdef CONFIG_NXP_ESBC /* @@ -146,7 +146,7 @@ int power_init_board(void) void config_board_mux(void) { #ifdef CONFIG_HAS_FSL_XHCI_USB - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; u32 usb_pwrfault;
/* USB3 is not used, configure mux to IIC4_SCL/IIC4_SDA */ diff --git a/board/freescale/ls1088a/eth_ls1088aqds.c b/board/freescale/ls1088a/eth_ls1088aqds.c index 140733de6af0..8fe643f70b96 100644 --- a/board/freescale/ls1088a/eth_ls1088aqds.c +++ b/board/freescale/ls1088a/eth_ls1088aqds.c @@ -471,7 +471,7 @@ static int ls1088a_qds_mdio_init(char *realbusname, u8 muxval) */ static void initialize_dpmac_to_slot(void) { - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; u32 serdes1_prtcl, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & @@ -524,7 +524,7 @@ static void initialize_dpmac_to_slot(void) void ls1088a_handle_phy_interface_sgmii(int dpmac_id) { struct mii_dev *bus; - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; u32 serdes1_prtcl, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & @@ -576,7 +576,7 @@ void ls1088a_handle_phy_interface_sgmii(int dpmac_id) void ls1088a_handle_phy_interface_qsgmii(int dpmac_id) { struct mii_dev *bus; - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; u32 serdes1_prtcl, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & @@ -615,7 +615,7 @@ void ls1088a_handle_phy_interface_qsgmii(int dpmac_id)
void ls1088a_handle_phy_interface_xsgmii(int i) { - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; u32 serdes1_prtcl, cfg;
cfg = in_le32(&gur->rcwsr[FSL_CHASSIS3_SRDS1_REGSR - 1]) & @@ -639,7 +639,7 @@ void ls1088a_handle_phy_interface_xsgmii(int i)
static void ls1088a_handle_phy_interface_rgmii(int dpmac_id) { - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; u32 serdes1_prtcl, cfg; struct mii_dev *bus;
@@ -682,7 +682,7 @@ int board_eth_init(struct bd_info *bis) sizeof(struct memac_mdio_info)); memac_mdio0_info->regs = (struct memac_mdio_controller *) - CONFIG_SYS_FSL_WRIOP1_MDIO1; + CFG_SYS_FSL_WRIOP1_MDIO1; memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the real MDIO1 bus */ @@ -807,7 +807,7 @@ static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
int board_fit_config_name_match(const char *name) { - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); char expected_dts[100]; char srds_s1_str[2]; u32 srds_s1, cfg; diff --git a/board/freescale/ls1088a/eth_ls1088ardb.c b/board/freescale/ls1088a/eth_ls1088ardb.c index 1ba5e94d0a0a..5792070f9394 100644 --- a/board/freescale/ls1088a/eth_ls1088ardb.c +++ b/board/freescale/ls1088a/eth_ls1088ardb.c @@ -25,7 +25,7 @@ int board_eth_init(struct bd_info *bis) int i, interface; struct memac_mdio_info mdio_info; struct mii_dev *dev; - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); struct memac_mdio_controller *reg; u32 srds_s1, cfg;
@@ -35,14 +35,14 @@ int board_eth_init(struct bd_info *bis)
srds_s1 = serdes_get_number(FSL_SRDS_1, cfg);
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; + reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1; mdio_info.regs = reg; mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the EMI 1 */ fm_memac_mdio_init(bis, &mdio_info);
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; + reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2; mdio_info.regs = reg; mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 0157377354a5..ae81740dc36c 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -1031,7 +1031,7 @@ int is_flash_available(void) #ifdef CONFIG_ENV_IS_IN_SPI_FLASH void *env_sf_get_env_addr(void) { - return (void *)(CONFIG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); + return (void *)(CFG_SYS_FSL_QSPI_BASE + CONFIG_ENV_OFFSET); } #endif #endif diff --git a/board/freescale/ls2080aqds/eth.c b/board/freescale/ls2080aqds/eth.c index 7db37898220a..6da6e5c84152 100644 --- a/board/freescale/ls2080aqds/eth.c +++ b/board/freescale/ls2080aqds/eth.c @@ -502,7 +502,7 @@ static int ls2080a_qds_mdio_init(char *realbusname, u8 muxval) */ static void initialize_dpmac_to_slot(void) { - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; @@ -656,7 +656,7 @@ void ls2080a_handle_phy_interface_sgmii(int dpmac_id) { int lane, slot; struct mii_dev *bus; - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; @@ -799,7 +799,7 @@ void ls2080a_handle_phy_interface_qsgmii(int dpmac_id) { int lane = 0, slot; struct mii_dev *bus; - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; @@ -864,7 +864,7 @@ void ls2080a_handle_phy_interface_qsgmii(int dpmac_id)
void ls2080a_handle_phy_interface_xsgmii(int i) { - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; @@ -898,7 +898,7 @@ int board_eth_init(struct bd_info *bis) { #ifndef CONFIG_DM_ETH #if defined(CONFIG_FSL_MC_ENET) && !defined(CONFIG_SPL_BUILD) - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; int serdes1_prtcl = (in_le32(&gur->rcwsr[28]) & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK) >> FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT; @@ -920,7 +920,7 @@ int board_eth_init(struct bd_info *bis) sizeof(struct memac_mdio_info)); memac_mdio0_info->regs = (struct memac_mdio_controller *) - CONFIG_SYS_FSL_WRIOP1_MDIO1; + CFG_SYS_FSL_WRIOP1_MDIO1; memac_mdio0_info->name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the real MDIO1 bus */ @@ -930,7 +930,7 @@ int board_eth_init(struct bd_info *bis) sizeof(struct memac_mdio_info)); memac_mdio1_info->regs = (struct memac_mdio_controller *) - CONFIG_SYS_FSL_WRIOP1_MDIO2; + CFG_SYS_FSL_WRIOP1_MDIO2; memac_mdio1_info->name = DEFAULT_WRIOP_MDIO2_NAME;
/* Register the real MDIO2 bus */ @@ -1053,7 +1053,7 @@ static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
int board_fit_config_name_match(const char *name) { - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 rcw_status = in_le32(&gur->rcwsr[28]); char srds_s1_str[2], srds_s2_str[2]; u32 srds_s1, srds_s2; diff --git a/board/freescale/ls2080ardb/eth_ls2080rdb.c b/board/freescale/ls2080ardb/eth_ls2080rdb.c index 21b4c16ff27c..7034bc6e5d21 100644 --- a/board/freescale/ls2080ardb/eth_ls2080rdb.c +++ b/board/freescale/ls2080ardb/eth_ls2080rdb.c @@ -29,7 +29,7 @@ int board_eth_init(struct bd_info *bis) int i, interface; struct memac_mdio_info mdio_info; struct mii_dev *dev; - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 srds_s1; struct memac_mdio_controller *reg;
@@ -37,14 +37,14 @@ int board_eth_init(struct bd_info *bis) FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; + reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1; mdio_info.regs = reg; mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the EMI 1 */ fm_memac_mdio_init(bis, &mdio_info);
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; + reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2; mdio_info.regs = reg; mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
diff --git a/board/freescale/ls2080ardb/ls2080ardb.c b/board/freescale/ls2080ardb/ls2080ardb.c index fb0699cb94ff..aa2d65b45b89 100644 --- a/board/freescale/ls2080ardb/ls2080ardb.c +++ b/board/freescale/ls2080ardb/ls2080ardb.c @@ -242,7 +242,7 @@ int config_board_mux(int ctrl_type) ulong *cs4340_get_fw_addr(void) { #ifdef CONFIG_TFABOOT - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 svr = gur_in32(&gur->svr); #endif ulong cortina_fw_addr = CONFIG_CORTINA_FW_ADDR; @@ -318,7 +318,7 @@ int misc_init_r(void) char *env_hwconfig; u32 __iomem *dcfg_ccsr = (u32 __iomem *)DCFG_BASE; u32 val; - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 svr = gur_in32(&gur->svr);
val = in_le32(dcfg_ccsr + DCFG_RCWSR13 / 4); diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c b/board/freescale/lx2160a/eth_lx2160aqds.c index 1819b27561ed..374d0526b42f 100644 --- a/board/freescale/lx2160a/eth_lx2160aqds.c +++ b/board/freescale/lx2160a/eth_lx2160aqds.c @@ -459,7 +459,7 @@ int board_eth_init(struct bd_info *bis) size_t len; struct mii_dev *bus; const struct phy_config *phy_config; - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 srds_s1, srds_s2, srds_s3;
srds_s1 = in_le32(&gur->rcwsr[28]) & @@ -476,14 +476,14 @@ int board_eth_init(struct bd_info *bis)
sprintf(srds, "%d_%d_%d", srds_s1, srds_s2, srds_s3);
- regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; + regs = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1; mdio_info.regs = regs; mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/*Register the EMI 1*/ fm_memac_mdio_init(bis, &mdio_info);
- regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; + regs = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2; mdio_info.regs = regs; mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
@@ -670,9 +670,9 @@ int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset) priv->realbusnum, priv->ioslot);
if (priv->realbusnum == EMI1) - reg = CONFIG_SYS_FSL_WRIOP1_MDIO1; + reg = CFG_SYS_FSL_WRIOP1_MDIO1; else - reg = CONFIG_SYS_FSL_WRIOP1_MDIO2; + reg = CFG_SYS_FSL_WRIOP1_MDIO2;
offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg); if (offset < 0) { @@ -929,7 +929,7 @@ static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
int board_fit_config_name_match(const char *name) { - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 rcw_status = in_le32(&gur->rcwsr[28]); char srds_s1_str[2], srds_s2_str[2], srds_s3_str[2]; u32 srds_s1, srds_s2, srds_s3; diff --git a/board/freescale/lx2160a/eth_lx2160ardb.c b/board/freescale/lx2160a/eth_lx2160ardb.c index 15cbc58d59a7..8a9c60f46cd5 100644 --- a/board/freescale/lx2160a/eth_lx2160ardb.c +++ b/board/freescale/lx2160a/eth_lx2160ardb.c @@ -48,21 +48,21 @@ int board_eth_init(struct bd_info *bis) struct memac_mdio_controller *reg; int i, interface; struct mii_dev *dev; - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 srds_s1;
srds_s1 = in_le32(&gur->rcwsr[28]) & FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_MASK; srds_s1 >>= FSL_CHASSIS3_RCWSR28_SRDS1_PRTCL_SHIFT;
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; + reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1; mdio_info.regs = reg; mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/* Register the EMI 1 */ fm_memac_mdio_init(bis, &mdio_info);
- reg = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; + reg = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2; mdio_info.regs = reg; mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
diff --git a/board/freescale/lx2160a/eth_lx2162aqds.c b/board/freescale/lx2160a/eth_lx2162aqds.c index ac6218ebe4ac..25fee899618f 100644 --- a/board/freescale/lx2160a/eth_lx2162aqds.c +++ b/board/freescale/lx2160a/eth_lx2162aqds.c @@ -480,7 +480,7 @@ int board_eth_init(struct bd_info *bis) size_t len; struct mii_dev *bus; const struct phy_config *phy_config; - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 srds_s1, srds_s2;
srds_s1 = in_le32(&gur->rcwsr[28]) & @@ -493,14 +493,14 @@ int board_eth_init(struct bd_info *bis)
sprintf(srds, "%d_%d", srds_s1, srds_s2);
- regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO1; + regs = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO1; mdio_info.regs = regs; mdio_info.name = DEFAULT_WRIOP_MDIO1_NAME;
/*Register the EMI 1*/ fm_memac_mdio_init(bis, &mdio_info);
- regs = (struct memac_mdio_controller *)CONFIG_SYS_FSL_WRIOP1_MDIO2; + regs = (struct memac_mdio_controller *)CFG_SYS_FSL_WRIOP1_MDIO2; mdio_info.regs = regs; mdio_info.name = DEFAULT_WRIOP_MDIO2_NAME;
@@ -679,9 +679,9 @@ int fdt_get_ioslot_offset(void *fdt, struct mii_dev *mii_dev, int fpga_offset) priv->realbusnum, priv->ioslot);
if (priv->realbusnum == EMI1) - reg = CONFIG_SYS_FSL_WRIOP1_MDIO1; + reg = CFG_SYS_FSL_WRIOP1_MDIO1; else - reg = CONFIG_SYS_FSL_WRIOP1_MDIO2; + reg = CFG_SYS_FSL_WRIOP1_MDIO2;
offset = fdt_node_offset_by_compat_reg(fdt, "fsl,fman-memac-mdio", reg); if (offset < 0) { @@ -946,7 +946,7 @@ static void get_str_protocol(u8 serdes_block, u32 protocol, char *str)
int board_fit_config_name_match(const char *name) { - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 rcw_status = in_le32(&gur->rcwsr[28]); char srds_s1_str[2], srds_s2_str[2]; u32 srds_s1, srds_s2; diff --git a/board/freescale/lx2160a/lx2160a.c b/board/freescale/lx2160a/lx2160a.c index 5f0cc9eb7e9e..437675517ebd 100644 --- a/board/freescale/lx2160a/lx2160a.c +++ b/board/freescale/lx2160a/lx2160a.c @@ -180,7 +180,7 @@ void esdhc_dspi_status_fixup(void *blob) const char dspi1_path[] = "/soc/spi@2110000"; const char dspi2_path[] = "/soc/spi@2120000";
- struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 sdhc1_base_pmux; u32 sdhc2_base_pmux; u32 iic5_pmux; @@ -385,7 +385,7 @@ static void esdhc_adapter_card_ident(void) int config_board_mux(void) { u8 reg11, reg5, reg13; - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 sdhc1_base_pmux; u32 sdhc2_base_pmux; u32 iic5_pmux; diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index a9800ed7698f..4f27d3e8ecce 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -124,7 +124,7 @@ static int power_init(void) return ret; }
- if (!i2c_probe(CONFIG_SYS_FSL_PMIC_I2C_ADDR)) { + if (!i2c_probe(CFG_SYS_FSL_PMIC_I2C_ADDR)) { ret = pmic_init(I2C_0); if (ret) return ret; diff --git a/board/freescale/p2041rdb/p2041rdb.c b/board/freescale/p2041rdb/p2041rdb.c index 859ffc4935c8..1b1263091e50 100644 --- a/board/freescale/p2041rdb/p2041rdb.c +++ b/board/freescale/p2041rdb/p2041rdb.c @@ -167,7 +167,7 @@ unsigned long get_board_sys_clk(void)
int misc_init_r(void) { - serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR; u32 actual[NUM_SRDS_BANKS]; unsigned int i; u8 sw; diff --git a/board/freescale/t208xqds/eth_t208xqds.c b/board/freescale/t208xqds/eth_t208xqds.c index dd1c35fa2015..555985b6f251 100644 --- a/board/freescale/t208xqds/eth_t208xqds.c +++ b/board/freescale/t208xqds/eth_t208xqds.c @@ -192,7 +192,7 @@ void board_ft_fman_fixup_port(void *fdt, char *compat, phys_addr_t addr, ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); #ifdef CONFIG_TARGET_T2080QDS serdes_corenet_t *srds_regs = - (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR; u32 srds1_pccr1 = in_be32(&srds_regs->srdspccr1); #endif u32 srds_s1 = in_be32(&gur->rcwsr[4]) & diff --git a/board/google/imx8mq_phanbell/spl.c b/board/google/imx8mq_phanbell/spl.c index eec3f3d931b2..83de5bfd75fa 100644 --- a/board/google/imx8mq_phanbell/spl.c +++ b/board/google/imx8mq_phanbell/spl.c @@ -97,7 +97,7 @@ int board_mmc_init(struct bd_info *bis) * mmc0 USDHC1 * mmc1 USDHC2 */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: init_clk_usdhc(0); diff --git a/board/keymile/kmcent2/kmcent2.c b/board/keymile/kmcent2/kmcent2.c index 758bd5b79ba1..6a1711092b62 100644 --- a/board/keymile/kmcent2/kmcent2.c +++ b/board/keymile/kmcent2/kmcent2.c @@ -220,7 +220,7 @@ EVENT_SPY(EVT_MISC_INIT_F, kmcent2_misc_init_f);
int misc_init_r(void) { - serdes_corenet_t *regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + serdes_corenet_t *regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR; struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_MPC85xx_SCFG; ccsr_gur_t __iomem *gur = (ccsr_gur_t __iomem *)CFG_SYS_MPC85xx_GUTS_ADDR;
diff --git a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c index ed8142d868f9..3719bcf7317e 100644 --- a/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c +++ b/board/keymile/pg-wcom-ls102xa/pg-wcom-ls102xa.c @@ -50,8 +50,8 @@ int dram_init(void)
int board_early_init_f(void) { - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; struct fsl_ifc ifc = {(void *)CONFIG_SYS_IFC_ADDR, (void *)NULL};
/* Disable unused MCK1 */ diff --git a/board/kontron/pitx_imx8m/spl.c b/board/kontron/pitx_imx8m/spl.c index ef3256898de6..f6fd17048d04 100644 --- a/board/kontron/pitx_imx8m/spl.c +++ b/board/kontron/pitx_imx8m/spl.c @@ -132,7 +132,7 @@ int board_mmc_init(struct bd_info *bis) * mmc0 USDHC1 * mmc1 USDHC2 */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: init_clk_usdhc(0); diff --git a/board/kontron/sl-mx6ul/spl.c b/board/kontron/sl-mx6ul/spl.c index 3ae8bf620949..bae0e70a657d 100644 --- a/board/kontron/sl-mx6ul/spl.c +++ b/board/kontron/sl-mx6ul/spl.c @@ -105,7 +105,7 @@ int board_mmc_init(struct bd_info *bis) * mmc0 USDHC1 * mmc1 USDHC2 */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); diff --git a/board/liebherr/mccmon6/spl.c b/board/liebherr/mccmon6/spl.c index 56eae3b4e9ee..b1f6881275d5 100644 --- a/board/liebherr/mccmon6/spl.c +++ b/board/liebherr/mccmon6/spl.c @@ -539,7 +539,7 @@ int board_mmc_init(struct bd_info *bis) * mmc0 Soldered on board eMMC device * mmc1 MicroSD card */ - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + for (index = 0; index < CFG_SYS_FSL_USDHC_NUM; ++index) { switch (index) { case 0: SETUP_IOMUX_PADS(usdhc3_pads); @@ -554,7 +554,7 @@ int board_mmc_init(struct bd_info *bis) break; default: printf("Warning: More USDHC controllers (%d) than supported (%d)\n", - index + 1, CONFIG_SYS_FSL_USDHC_NUM); + index + 1, CFG_SYS_FSL_USDHC_NUM); return -EINVAL; }
diff --git a/board/myir/mys_6ulx/spl.c b/board/myir/mys_6ulx/spl.c index 5cd4d0528309..3cf14e2bc660 100644 --- a/board/myir/mys_6ulx/spl.c +++ b/board/myir/mys_6ulx/spl.c @@ -155,7 +155,7 @@ int board_mmc_init(struct bd_info *bis) { int i, ret;
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: SETUP_IOMUX_PADS(usdhc1_pads); diff --git a/board/phytec/pcl063/spl.c b/board/phytec/pcl063/spl.c index fea4aa33655a..b6d459fdfce6 100644 --- a/board/phytec/pcl063/spl.c +++ b/board/phytec/pcl063/spl.c @@ -156,7 +156,7 @@ int board_mmc_init(struct bd_info *bis) { int i, ret;
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: SETUP_IOMUX_PADS(usdhc1_pads); diff --git a/board/purism/librem5/spl.c b/board/purism/librem5/spl.c index a068f76460d8..1bfd948806f2 100644 --- a/board/purism/librem5/spl.c +++ b/board/purism/librem5/spl.c @@ -204,7 +204,7 @@ int board_mmc_init(struct bd_info *bis) * mmc0 USDHC1 * mmc1 USDHC2 */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { log_debug("Initializing FSL USDHC port %d\n", i); switch (i) { case 0: diff --git a/board/ronetix/imx8mq-cm/spl.c b/board/ronetix/imx8mq-cm/spl.c index c32a06f12706..b9a67451aecc 100644 --- a/board/ronetix/imx8mq-cm/spl.c +++ b/board/ronetix/imx8mq-cm/spl.c @@ -89,7 +89,7 @@ int board_mmc_init(struct bd_info *bis) * mmc0 USDHC1 * mmc1 USDHC2 */ - for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: init_clk_usdhc(0); diff --git a/board/seeed/npi_imx6ull/spl.c b/board/seeed/npi_imx6ull/spl.c index 4b56f52d985b..b29da2c1fc1e 100644 --- a/board/seeed/npi_imx6ull/spl.c +++ b/board/seeed/npi_imx6ull/spl.c @@ -154,7 +154,7 @@ int board_mmc_init(struct bd_info *bis) { int i, ret;
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: SETUP_IOMUX_PADS(usdhc1_pads); diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index d358a209a4a3..04527cf79ab2 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -26,7 +26,7 @@ phys_size_t fixed_sdram(void) { struct ccsr_ddr __iomem *ddr = - (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); + (struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR);
/* * Disable memory controller. diff --git a/board/toradex/apalis_imx6/apalis_imx6.c b/board/toradex/apalis_imx6/apalis_imx6.c index 8d2642f25d08..96d0185329d2 100644 --- a/board/toradex/apalis_imx6/apalis_imx6.c +++ b/board/toradex/apalis_imx6/apalis_imx6.c @@ -322,7 +322,7 @@ int board_ehci_hcd_init(int port)
#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD) /* use the following sequence: eMMC, MMC1, SD1 */ -struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { +struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = { {USDHC3_BASE_ADDR}, {USDHC1_BASE_ADDR}, {USDHC2_BASE_ADDR}, diff --git a/board/toradex/colibri_imx6/colibri_imx6.c b/board/toradex/colibri_imx6/colibri_imx6.c index ab2ab587ffb6..475250d8013a 100644 --- a/board/toradex/colibri_imx6/colibri_imx6.c +++ b/board/toradex/colibri_imx6/colibri_imx6.c @@ -290,7 +290,7 @@ int board_ehci_hcd_init(int port)
#if defined(CONFIG_FSL_ESDHC_IMX) && defined(CONFIG_SPL_BUILD) /* use the following sequence: eMMC, MMC */ -struct fsl_esdhc_cfg usdhc_cfg[CONFIG_SYS_FSL_USDHC_NUM] = { +struct fsl_esdhc_cfg usdhc_cfg[CFG_SYS_FSL_USDHC_NUM] = { {USDHC3_BASE_ADDR}, {USDHC1_BASE_ADDR}, }; diff --git a/board/traverse/ten64/ten64.c b/board/traverse/ten64/ten64.c index a15b81b0cfdc..e6403cad1f51 100644 --- a/board/traverse/ten64/ten64.c +++ b/board/traverse/ten64/ten64.c @@ -61,7 +61,7 @@ int board_early_init_f(void)
static u32 ten64_get_board_rev(void) { - struct ccsr_gur *dcfg = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur *dcfg = (void *)CFG_SYS_FSL_GUTS_ADDR; u32 board_rev_in = in_le32(&dcfg->gpporcr1); return board_rev_in; } diff --git a/board/variscite/dart_6ul/spl.c b/board/variscite/dart_6ul/spl.c index 91d470f6e5e2..17b1ae748846 100644 --- a/board/variscite/dart_6ul/spl.c +++ b/board/variscite/dart_6ul/spl.c @@ -159,7 +159,7 @@ int board_mmc_init(struct bd_info *bis) { int i, ret;
- for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + for (i = 0; i < CFG_SYS_FSL_USDHC_NUM; i++) { switch (i) { case 0: SETUP_IOMUX_PADS(usdhc1_pads); diff --git a/board/wandboard/spl.c b/board/wandboard/spl.c index 0983d1005881..717e02a039b7 100644 --- a/board/wandboard/spl.c +++ b/board/wandboard/spl.c @@ -487,7 +487,7 @@ int board_mmc_init(struct bd_info *bis) * mmc0 SOM MicroSD * mmc1 Carrier board MicroSD */ - for (index = 0; index < CONFIG_SYS_FSL_USDHC_NUM; ++index) { + for (index = 0; index < CFG_SYS_FSL_USDHC_NUM; ++index) { switch (index) { case 0: SETUP_IOMUX_PADS(usdhc3_pads); @@ -504,7 +504,7 @@ int board_mmc_init(struct bd_info *bis) default: printf("Warning: you configured more USDHC controllers" "(%d) then supported by the board (%d)\n", - index + 1, CONFIG_SYS_FSL_USDHC_NUM); + index + 1, CFG_SYS_FSL_USDHC_NUM); return -EINVAL; }
diff --git a/cmd/blob.c b/cmd/blob.c index e2efae7a1159..7c77c410d528 100644 --- a/cmd/blob.c +++ b/cmd/blob.c @@ -84,7 +84,7 @@ static int do_blob(struct cmd_tbl *cmdtp, int flag, int argc,
hab_caam_clock_enable(1);
- u32 out_jr_size = sec_in32(CONFIG_SYS_FSL_JR0_ADDR + + u32 out_jr_size = sec_in32(CFG_SYS_FSL_JR0_ADDR + FSL_CAAM_ORSR_JRa_OFFSET); if (out_jr_size != FSL_CAAM_MAX_JR_SIZE) sec_init(); diff --git a/drivers/crypto/fsl/jobdesc.c b/drivers/crypto/fsl/jobdesc.c index 542b1652d80d..d32c1fe5c31a 100644 --- a/drivers/crypto/fsl/jobdesc.c +++ b/drivers/crypto/fsl/jobdesc.c @@ -28,7 +28,7 @@ uint32_t secmem_set_cmd(uint32_t sec_mem_cmd) { uint32_t temp_reg;
- ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + ccsr_sec_t *sec = (void *)CFG_SYS_FSL_SEC_ADDR; uint32_t sm_vid = SM_VERSION(sec_in32(&sec->smvid)); uint32_t jr_id = 0;
@@ -58,7 +58,7 @@ int caam_page_alloc(uint8_t page_num, uint8_t partition_num) { uint32_t temp_reg;
- ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + ccsr_sec_t *sec = (void *)CFG_SYS_FSL_SEC_ADDR; uint32_t sm_vid = SM_VERSION(sec_in32(&sec->smvid)); uint32_t jr_id = 0;
@@ -116,7 +116,7 @@ int caam_page_alloc(uint8_t page_num, uint8_t partition_num) int inline_cnstr_jobdesc_blob_dek(uint32_t *desc, const uint8_t *plain_txt, uint8_t *dek_blob, uint32_t in_sz) { - ccsr_sec_t *sec = (void *)CONFIG_SYS_FSL_SEC_ADDR; + ccsr_sec_t *sec = (void *)CFG_SYS_FSL_SEC_ADDR; uint32_t sm_vid = SM_VERSION(sec_in32(&sec->smvid)); uint32_t jr_id = 0;
diff --git a/drivers/crypto/fsl/jr.c b/drivers/crypto/fsl/jr.c index 8c0fb27b5322..ee822edd6c8e 100644 --- a/drivers/crypto/fsl/jr.c +++ b/drivers/crypto/fsl/jr.c @@ -33,8 +33,8 @@ uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = { 0, #if defined(CONFIG_ARCH_C29X) - CONFIG_SYS_FSL_SEC_IDX_OFFSET, - 2 * CONFIG_SYS_FSL_SEC_IDX_OFFSET + CFG_SYS_FSL_SEC_IDX_OFFSET, + 2 * CFG_SYS_FSL_SEC_IDX_OFFSET #endif };
@@ -42,11 +42,11 @@ uint32_t sec_offset[CONFIG_SYS_FSL_MAX_NUM_OF_SEC] = { struct udevice *caam_dev; #else #define SEC_ADDR(idx) \ - (ulong)((CONFIG_SYS_FSL_SEC_ADDR + sec_offset[idx])) + (ulong)((CFG_SYS_FSL_SEC_ADDR + sec_offset[idx]))
#define SEC_JR0_ADDR(idx) \ (ulong)(SEC_ADDR(idx) + \ - (CONFIG_SYS_FSL_JR0_OFFSET - CONFIG_SYS_FSL_SEC_OFFSET)) + (CFG_SYS_FSL_JR0_OFFSET - CFG_SYS_FSL_SEC_OFFSET)) struct caam_regs caam_st; #endif
diff --git a/drivers/crypto/fsl/sec.c b/drivers/crypto/fsl/sec.c index f0a4a63d8863..9de30a6112fa 100644 --- a/drivers/crypto/fsl/sec.c +++ b/drivers/crypto/fsl/sec.c @@ -128,7 +128,7 @@ u8 caam_get_era(void) {0x0A1C, 1, 5} };
- ccsr_sec_t __iomem *sec = (void __iomem *)CONFIG_SYS_FSL_SEC_ADDR; + ccsr_sec_t __iomem *sec = (void __iomem *)CFG_SYS_FSL_SEC_ADDR; u32 secvid_ms = sec_in32(&sec->secvid_ms); u32 ccbvid = sec_in32(&sec->ccbvid); u16 ip_id = (secvid_ms & SEC_SECVID_MS_IPID_MASK) >> diff --git a/drivers/ddr/fsl/arm_ddr_gen3.c b/drivers/ddr/fsl/arm_ddr_gen3.c index 629ba6784e0d..5e8fb7a89c21 100644 --- a/drivers/ddr/fsl/arm_ddr_gen3.c +++ b/drivers/ddr/fsl/arm_ddr_gen3.c @@ -40,16 +40,16 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
switch (ctrl_num) { case 0: - ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + ddr = (void *)CFG_SYS_FSL_DDR_ADDR; break; -#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) +#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) case 1: - ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; + ddr = (void *)CFG_SYS_FSL_DDR2_ADDR; break; #endif -#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) +#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) case 2: - ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; + ddr = (void *)CFG_SYS_FSL_DDR3_ADDR; break; #endif #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) diff --git a/drivers/ddr/fsl/ctrl_regs.c b/drivers/ddr/fsl/ctrl_regs.c index 0b0b4e5cb7ee..df7ec484651a 100644 --- a/drivers/ddr/fsl/ctrl_regs.c +++ b/drivers/ddr/fsl/ctrl_regs.c @@ -2590,7 +2590,7 @@ compute_fsl_memctl_config_regs(const unsigned int ctrl_num, void erratum_a009942_check_cpo(void) { struct ccsr_ddr __iomem *ddr = - (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); + (struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR); u32 cpo, cpo_e, cpo_o, cpo_target, cpo_optimal; u32 cpo_min = ddr_in32(&ddr->debug[9]) >> 24; u32 cpo_max = cpo_min; diff --git a/drivers/ddr/fsl/fsl_ddr_gen4.c b/drivers/ddr/fsl/fsl_ddr_gen4.c index 89cb4d352eed..3c1f7a189120 100644 --- a/drivers/ddr/fsl/fsl_ddr_gen4.c +++ b/drivers/ddr/fsl/fsl_ddr_gen4.c @@ -86,16 +86,16 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, #endif switch (ctrl_num) { case 0: - ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + ddr = (void *)CFG_SYS_FSL_DDR_ADDR; break; -#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) +#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) case 1: - ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; + ddr = (void *)CFG_SYS_FSL_DDR2_ADDR; break; #endif -#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) +#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) case 2: - ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; + ddr = (void *)CFG_SYS_FSL_DDR3_ADDR; break; #endif #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) diff --git a/drivers/ddr/fsl/fsl_mmdc.c b/drivers/ddr/fsl/fsl_mmdc.c index cbd625b7eeac..28f2219b2a43 100644 --- a/drivers/ddr/fsl/fsl_mmdc.c +++ b/drivers/ddr/fsl/fsl_mmdc.c @@ -28,7 +28,7 @@ static void set_wait_for_bits_clear(void *ptr, u32 value, u32 bits)
void mmdc_init(const struct fsl_mmdc_info *priv) { - struct mmdc_regs *mmdc = (struct mmdc_regs *)CONFIG_SYS_FSL_DDR_ADDR; + struct mmdc_regs *mmdc = (struct mmdc_regs *)CFG_SYS_FSL_DDR_ADDR; unsigned int tmp;
/* 1. set configuration request */ diff --git a/drivers/ddr/fsl/main.c b/drivers/ddr/fsl/main.c index ed3313a53151..fcff223b4f0d 100644 --- a/drivers/ddr/fsl/main.c +++ b/drivers/ddr/fsl/main.c @@ -21,18 +21,18 @@ #include <asm/bitops.h>
/* - * CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view + * CFG_SYS_FSL_DDR_SDRAM_BASE_PHY is the physical address from the view * of DDR controllers. It is the same as CONFIG_SYS_DDR_SDRAM_BASE for * all Power SoCs. But it could be different for ARM SoCs. For example, * fsl_lsch3 has a mapping mechanism to map DDR memory to ranges (in order) of * 0x00_8000_0000 ~ 0x00_ffff_ffff * 0x80_8000_0000 ~ 0xff_ffff_ffff */ -#ifndef CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY +#ifndef CFG_SYS_FSL_DDR_SDRAM_BASE_PHY #ifdef CONFIG_MPC83xx -#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_SDRAM_BASE #else -#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY CONFIG_SYS_DDR_SDRAM_BASE #endif #endif
@@ -898,7 +898,7 @@ phys_size_t fsl_ddr_sdram(void)
/* Reset info structure. */ memset(&info, 0, sizeof(fsl_ddr_info_t)); - info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; + info.mem_base = CFG_SYS_FSL_DDR_SDRAM_BASE_PHY; info.first_ctrl = 0; info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS; info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR; @@ -946,7 +946,7 @@ fsl_ddr_sdram_size(void) unsigned long long total_memory = 0;
memset(&info, 0 , sizeof(fsl_ddr_info_t)); - info.mem_base = CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY; + info.mem_base = CFG_SYS_FSL_DDR_SDRAM_BASE_PHY; info.first_ctrl = 0; info.num_ctrls = CONFIG_SYS_FSL_DDR_MAIN_NUM_CTRLS; info.dimm_slots_per_ctrl = CONFIG_DIMM_SLOTS_PER_CTLR; diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c index 9c2ddeaf932f..0f1e99eeb039 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen1.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen1.c @@ -18,7 +18,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, { unsigned int i; struct ccsr_ddr __iomem *ddr = - (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; + (struct ccsr_ddr __iomem *)CFG_SYS_FSL_DDR_ADDR;
if (ctrl_num != 0) { printf("%s unexpected ctrl_num = %u\n", __FUNCTION__, ctrl_num); @@ -71,7 +71,7 @@ void ddr_enable_ecc(unsigned int dram_size) { struct ccsr_ddr __iomem *ddr = - (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); + (struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR);
dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size);
diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c index 9ed80d63ef05..b830e7cbd141 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen2.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen2.c @@ -18,7 +18,7 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs, { unsigned int i; struct ccsr_ddr __iomem *ddr = - (struct ccsr_ddr __iomem *)CONFIG_SYS_FSL_DDR_ADDR; + (struct ccsr_ddr __iomem *)CFG_SYS_FSL_DDR_ADDR;
#if defined(CONFIG_SYS_FSL_ERRATUM_NMG_DDR120) && defined(CONFIG_MPC85xx) ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); diff --git a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c index 47339c59737a..0f2dc243cb82 100644 --- a/drivers/ddr/fsl/mpc85xx_ddr_gen3.c +++ b/drivers/ddr/fsl/mpc85xx_ddr_gen3.c @@ -52,16 +52,16 @@ void fsl_ddr_set_memctl_regs(const fsl_ddr_cfg_regs_t *regs,
switch (ctrl_num) { case 0: - ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + ddr = (void *)CFG_SYS_FSL_DDR_ADDR; break; -#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) +#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) case 1: - ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; + ddr = (void *)CFG_SYS_FSL_DDR2_ADDR; break; #endif -#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) +#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) case 2: - ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; + ddr = (void *)CFG_SYS_FSL_DDR3_ADDR; break; #endif #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) diff --git a/drivers/ddr/fsl/util.c b/drivers/ddr/fsl/util.c index 43cb01804b71..fd8c2dd1a9ca 100644 --- a/drivers/ddr/fsl/util.c +++ b/drivers/ddr/fsl/util.c @@ -34,16 +34,16 @@ u32 fsl_ddr_get_version(unsigned int ctrl_num)
switch (ctrl_num) { case 0: - ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + ddr = (void *)CFG_SYS_FSL_DDR_ADDR; break; -#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) +#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) case 1: - ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; + ddr = (void *)CFG_SYS_FSL_DDR2_ADDR; break; #endif -#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) +#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) case 2: - ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; + ddr = (void *)CFG_SYS_FSL_DDR3_ADDR; break; #endif #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) @@ -181,7 +181,7 @@ u32 fsl_ddr_get_intl3r(void) void print_ddr_info(unsigned int start_ctrl) { struct ccsr_ddr __iomem *ddr = - (struct ccsr_ddr __iomem *)(CONFIG_SYS_FSL_DDR_ADDR); + (struct ccsr_ddr __iomem *)(CFG_SYS_FSL_DDR_ADDR);
#if defined(CONFIG_E6500) && (CONFIG_SYS_NUM_DDR_CTLRS == 3) u32 *mcintl3r = (void *) (CONFIG_SYS_IMMR + 0x18004); @@ -195,14 +195,14 @@ void print_ddr_info(unsigned int start_ctrl) #if CONFIG_SYS_NUM_DDR_CTLRS >= 2 if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) || (start_ctrl == 1)) { - ddr = (void __iomem *)CONFIG_SYS_FSL_DDR2_ADDR; + ddr = (void __iomem *)CFG_SYS_FSL_DDR2_ADDR; sdram_cfg = ddr_in32(&ddr->sdram_cfg); } #endif #if CONFIG_SYS_NUM_DDR_CTLRS >= 3 if ((!(sdram_cfg & SDRAM_CFG_MEM_EN)) || (start_ctrl == 2)) { - ddr = (void __iomem *)CONFIG_SYS_FSL_DDR3_ADDR; + ddr = (void __iomem *)CFG_SYS_FSL_DDR3_ADDR; sdram_cfg = ddr_in32(&ddr->sdram_cfg); } #endif @@ -353,16 +353,16 @@ void fsl_ddr_sync_memctl_refresh(unsigned int first_ctrl, for (i = first_ctrl; i <= last_ctrl; i++) { switch (i) { case 0: - ddr = (void *)CONFIG_SYS_FSL_DDR_ADDR; + ddr = (void *)CFG_SYS_FSL_DDR_ADDR; break; -#if defined(CONFIG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) +#if defined(CFG_SYS_FSL_DDR2_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 1) case 1: - ddr = (void *)CONFIG_SYS_FSL_DDR2_ADDR; + ddr = (void *)CFG_SYS_FSL_DDR2_ADDR; break; #endif -#if defined(CONFIG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) +#if defined(CFG_SYS_FSL_DDR3_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 2) case 2: - ddr = (void *)CONFIG_SYS_FSL_DDR3_ADDR; + ddr = (void *)CFG_SYS_FSL_DDR3_ADDR; break; #endif #if defined(CONFIG_SYS_FSL_DDR4_ADDR) && (CONFIG_SYS_NUM_DDR_CTLRS > 3) diff --git a/drivers/misc/fsl_devdis.c b/drivers/misc/fsl_devdis.c index cfe03b40cd01..179053a298af 100644 --- a/drivers/misc/fsl_devdis.c +++ b/drivers/misc/fsl_devdis.c @@ -14,7 +14,7 @@ void device_disable(const struct devdis_table *tbl, uint32_t num) { int i; - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
/* * Extract hwconfig from environment and disable unused device. diff --git a/drivers/misc/fsl_portals.c b/drivers/misc/fsl_portals.c index 59df57a9acc7..30a9409e5ab2 100644 --- a/drivers/misc/fsl_portals.c +++ b/drivers/misc/fsl_portals.c @@ -28,7 +28,7 @@ void setup_qbman_portals(void) CONFIG_SYS_BMAN_SWP_ISDR_REG; void __iomem *qpaddr = (void *)CONFIG_SYS_QMAN_CINH_BASE + CONFIG_SYS_QMAN_SWP_ISDR_REG; - struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR; + struct ccsr_qman *qman = (void *)CFG_SYS_FSL_QMAN_ADDR;
/* Set the Qman initiator BAR to match the LAW (for DQRR stashing) */ #ifdef CONFIG_PHYS_64BIT @@ -159,7 +159,7 @@ static int fdt_qportal(void *blob, int off, int id, char *name, if (!strncmp(name, "pme", 3)) { u32 pme_rev1, pme_rev2; ccsr_pme_t *pme_regs = - (void *)CONFIG_SYS_FSL_CORENET_PME_ADDR; + (void *)CFG_SYS_FSL_CORENET_PME_ADDR;
pme_rev1 = in_be32(&pme_regs->pm_ip_rev_1); pme_rev2 = in_be32(&pme_regs->pm_ip_rev_2); @@ -190,7 +190,7 @@ void fdt_fixup_qportals(void *blob) int off, err; unsigned int maj, min; unsigned int ip_cfg; - struct ccsr_qman *qman = (void *)CONFIG_SYS_FSL_QMAN_ADDR; + struct ccsr_qman *qman = (void *)CFG_SYS_FSL_QMAN_ADDR; u32 rev_1 = in_be32(&qman->ip_rev_1); u32 rev_2 = in_be32(&qman->ip_rev_2); char compat[64]; @@ -302,7 +302,7 @@ void fdt_fixup_bportals(void *blob) int off, err; unsigned int maj, min; unsigned int ip_cfg; - struct ccsr_bman *bman = (void *)CONFIG_SYS_FSL_BMAN_ADDR; + struct ccsr_bman *bman = (void *)CFG_SYS_FSL_BMAN_ADDR; u32 rev_1 = in_be32(&bman->ip_rev_1); u32 rev_2 = in_be32(&bman->ip_rev_2); char compat[64]; diff --git a/drivers/mmc/fsl_esdhc.c b/drivers/mmc/fsl_esdhc.c index ca5a87969f88..d5066666698c 100644 --- a/drivers/mmc/fsl_esdhc.c +++ b/drivers/mmc/fsl_esdhc.c @@ -988,7 +988,7 @@ int fsl_esdhc_mmc_init(struct bd_info *bis) struct fsl_esdhc_cfg *cfg;
cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); - cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; + cfg->esdhc_base = CFG_SYS_FSL_ESDHC_ADDR; cfg->max_bus_width = CONFIG_SYS_FSL_ESDHC_DEFAULT_BUS_WIDTH; /* Prefer peripheral clock which provides higher frequency. */ if (gd->arch.sdhc_per_clk) diff --git a/drivers/mmc/fsl_esdhc_imx.c b/drivers/mmc/fsl_esdhc_imx.c index 92b152fc9794..5ee3ce782313 100644 --- a/drivers/mmc/fsl_esdhc_imx.c +++ b/drivers/mmc/fsl_esdhc_imx.c @@ -1351,7 +1351,7 @@ int fsl_esdhc_mmc_init(struct bd_info *bis) struct fsl_esdhc_cfg *cfg;
cfg = calloc(sizeof(struct fsl_esdhc_cfg), 1); - cfg->esdhc_base = CONFIG_SYS_FSL_ESDHC_ADDR; + cfg->esdhc_base = CFG_SYS_FSL_ESDHC_ADDR; cfg->sdhc_clk = gd->arch.sdhc_clk; return fsl_esdhc_initialize(bis, cfg); } diff --git a/drivers/net/fm/eth.c b/drivers/net/fm/eth.c index 1ffe9e2b7a58..c23e0c07702f 100644 --- a/drivers/net/fm/eth.c +++ b/drivers/net/fm/eth.c @@ -125,7 +125,7 @@ qsgmii_loop: static void dtsec_init_phy(struct fm_eth *fm_eth) { #ifndef CONFIG_SYS_FMAN_V3 - struct dtsec *regs = (struct dtsec *)CONFIG_SYS_FSL_FM1_DTSEC1_ADDR; + struct dtsec *regs = (struct dtsec *)CFG_SYS_FSL_FM1_DTSEC1_ADDR;
/* Assign a Physical address to the TBI */ out_be32(®s->tbipa, CONFIG_SYS_TBIPA_VALUE); diff --git a/drivers/net/fm/fm.c b/drivers/net/fm/fm.c index ee96abbf77f3..9b6dbe2882fd 100644 --- a/drivers/net/fm/fm.c +++ b/drivers/net/fm/fm.c @@ -403,7 +403,7 @@ int fm_init_common(int index, struct ccsr_fman *reg) } else { ret = spi_flash_read(ucode_flash, CONFIG_SYS_FMAN_FW_ADDR + - CONFIG_SYS_FSL_QSPI_BASE, + CFG_SYS_FSL_QSPI_BASE, CONFIG_SYS_QE_FMAN_FW_LENGTH, addr); if (ret) diff --git a/drivers/net/fm/init.c b/drivers/net/fm/init.c index af94dabe291e..5cfed425a42b 100644 --- a/drivers/net/fm/init.c +++ b/drivers/net/fm/init.c @@ -92,7 +92,7 @@ int fm_standard_init(struct bd_info *bis) int i; struct ccsr_fman *reg;
- reg = (void *)CONFIG_SYS_FSL_FM1_ADDR; + reg = (void *)CFG_SYS_FSL_FM1_ADDR; if (fm_init_common(0, reg)) return 0;
@@ -102,7 +102,7 @@ int fm_standard_init(struct bd_info *bis) }
#if (CONFIG_SYS_NUM_FMAN == 2) - reg = (void *)CONFIG_SYS_FSL_FM2_ADDR; + reg = (void *)CFG_SYS_FSL_FM2_ADDR; if (fm_init_common(1, reg)) return 0;
@@ -247,7 +247,7 @@ int ft_fixup_port(void *blob, struct fm_eth_info *info, char *prop) phys_addr_t paddr = CONFIG_SYS_CCSRBAR_PHYS + info->compat_offset; #ifndef CONFIG_SYS_FMAN_V3 u64 dtsec1_addr = (u64)CONFIG_SYS_CCSRBAR_PHYS + - CONFIG_SYS_FSL_FM1_DTSEC1_OFFSET; + CFG_SYS_FSL_FM1_DTSEC1_OFFSET; #endif
off = fdt_node_offset_by_compat_reg(blob, prop, paddr); diff --git a/drivers/net/fm/ls1043.c b/drivers/net/fm/ls1043.c index cd8376a6150d..3db5c907a2ab 100644 --- a/drivers/net/fm/ls1043.c +++ b/drivers/net/fm/ls1043.c @@ -35,7 +35,7 @@ u32 port_to_devdisr[] = {
static int is_device_disabled(enum fm_port port) { - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2; @@ -43,14 +43,14 @@ static int is_device_disabled(enum fm_port port)
void fman_disable_port(enum fm_port port) { - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]); }
phy_interface_t fman_port_enet_if(enum fm_port port) { - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port)) diff --git a/drivers/net/fm/ls1046.c b/drivers/net/fm/ls1046.c index 876f48b14775..3b0ee98ddd35 100644 --- a/drivers/net/fm/ls1046.c +++ b/drivers/net/fm/ls1046.c @@ -35,7 +35,7 @@ u32 port_to_devdisr[] = {
static int is_device_disabled(enum fm_port port) { - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 devdisr2 = in_be32(&gur->devdisr2);
return port_to_devdisr[port] & devdisr2; @@ -43,14 +43,14 @@ static int is_device_disabled(enum fm_port port)
void fman_disable_port(enum fm_port port) { - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR);
setbits_be32(&gur->devdisr2, port_to_devdisr[port]); }
phy_interface_t fman_port_enet_if(enum fm_port port) { - struct ccsr_gur *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 rcwsr13 = in_be32(&gur->rcwsr[13]);
if (is_device_disabled(port)) diff --git a/drivers/net/ldpaa_eth/ls1088a.c b/drivers/net/ldpaa_eth/ls1088a.c index 943113b20aa2..32bcb51725ac 100644 --- a/drivers/net/ldpaa_eth/ls1088a.c +++ b/drivers/net/ldpaa_eth/ls1088a.c @@ -25,7 +25,7 @@ u32 dpmac_to_devdisr[] = {
static int is_device_disabled(int dpmac_id) { - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; u32 devdisr2 = in_le32(&gur->devdisr2);
return dpmac_to_devdisr[dpmac_id] & devdisr2; @@ -33,14 +33,14 @@ static int is_device_disabled(int dpmac_id)
void wriop_dpmac_disable(int dpmac_id) { - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); }
void wriop_dpmac_enable(int dpmac_id) { - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); } @@ -90,7 +90,7 @@ void wriop_init_dpmac_qsgmii(int sd, int lane_prtcl) #ifdef CONFIG_SYS_FSL_HAS_RGMII void fsl_rgmii_init(void) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 ec;
#ifdef CONFIG_SYS_FSL_EC1 diff --git a/drivers/net/ldpaa_eth/ls2080a.c b/drivers/net/ldpaa_eth/ls2080a.c index 62e1d6b86910..845a36bce875 100644 --- a/drivers/net/ldpaa_eth/ls2080a.c +++ b/drivers/net/ldpaa_eth/ls2080a.c @@ -37,7 +37,7 @@ u32 dpmac_to_devdisr[] = {
static int is_device_disabled(int dpmac_id) { - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; u32 devdisr2 = in_le32(&gur->devdisr2);
return dpmac_to_devdisr[dpmac_id] & devdisr2; @@ -45,14 +45,14 @@ static int is_device_disabled(int dpmac_id)
void wriop_dpmac_disable(int dpmac_id) { - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); }
void wriop_dpmac_enable(int dpmac_id) { - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); } diff --git a/drivers/net/ldpaa_eth/lx2160a.c b/drivers/net/ldpaa_eth/lx2160a.c index f0f8ee1d4de7..c2641a92d7ec 100644 --- a/drivers/net/ldpaa_eth/lx2160a.c +++ b/drivers/net/ldpaa_eth/lx2160a.c @@ -33,7 +33,7 @@ u32 dpmac_to_devdisr[] = {
static int is_device_disabled(int dpmac_id) { - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; u32 devdisr2 = in_le32(&gur->devdisr2);
return dpmac_to_devdisr[dpmac_id] & devdisr2; @@ -41,14 +41,14 @@ static int is_device_disabled(int dpmac_id)
void wriop_dpmac_disable(int dpmac_id) { - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
setbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); }
void wriop_dpmac_enable(int dpmac_id) { - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR;
clrbits_le32(&gur->devdisr2, dpmac_to_devdisr[dpmac_id]); } @@ -84,7 +84,7 @@ phy_interface_t wriop_dpmac_enet_if(int dpmac_id, int lane_prtcl) #ifdef CONFIG_SYS_FSL_HAS_RGMII void fsl_rgmii_init(void) { - struct ccsr_gur __iomem *gur = (void *)(CONFIG_SYS_FSL_GUTS_ADDR); + struct ccsr_gur __iomem *gur = (void *)(CFG_SYS_FSL_GUTS_ADDR); u32 ec;
#ifdef CONFIG_SYS_FSL_EC1 diff --git a/drivers/net/pfe_eth/pfe_eth.c b/drivers/net/pfe_eth/pfe_eth.c index d338b363d57c..ab532c5a420e 100644 --- a/drivers/net/pfe_eth/pfe_eth.c +++ b/drivers/net/pfe_eth/pfe_eth.c @@ -51,7 +51,7 @@ static inline void pfe_gemac_disable(void *gemac_base)
static inline void pfe_gemac_set_speed(void *gemac_base, u32 speed) { - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR; u32 ecr = readl(gemac_base + EMAC_ECNTRL_REG) & ~EMAC_ECNTRL_SPEED; u32 rcr = readl(gemac_base + EMAC_RCNTRL_REG) & ~EMAC_RCNTRL_RMII_10T; u32 rgmii_pcr = in_be32(&scfg->rgmiipcr) & diff --git a/drivers/net/pfe_eth/pfe_mdio.c b/drivers/net/pfe_eth/pfe_mdio.c index ae5b6fc2800a..ff48726dbf55 100644 --- a/drivers/net/pfe_eth/pfe_mdio.c +++ b/drivers/net/pfe_eth/pfe_mdio.c @@ -213,7 +213,7 @@ int pfe_phy_configure(struct pfe_eth_dev *priv, int dev_id, int phy_id) struct phy_device *phydev = NULL; struct udevice *dev = priv->dev; struct gemac_s *gem = priv->gem; - struct ccsr_scfg *scfg = (struct ccsr_scfg *)CONFIG_SYS_FSL_SCFG_ADDR; + struct ccsr_scfg *scfg = (struct ccsr_scfg *)CFG_SYS_FSL_SCFG_ADDR;
if (!gem->bus) return -1; diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 59c38f905771..a8f8c31bef8f 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -463,7 +463,7 @@ static int fsl_pcie_init_port(struct fsl_pcie *pcie) if (!fsl_pcie_link_up(pcie)) { serdes_corenet_t *srds_regs;
- srds_regs = (void *)CONFIG_SYS_FSL_CORENET_SERDES_ADDR; + srds_regs = (void *)CFG_SYS_FSL_CORENET_SERDES_ADDR; val_32 = in_be32(&srds_regs->srdspccr0);
if ((val_32 >> 28) == 3) { diff --git a/drivers/power/power_fsl.c b/drivers/power/power_fsl.c index a163300ab6b8..7180b5127a5b 100644 --- a/drivers/power/power_fsl.c +++ b/drivers/power/power_fsl.c @@ -47,7 +47,7 @@ int pmic_init(unsigned char bus) p->hw.spi.prepare_tx = pmic_spi_prepare_tx; #elif defined(CONFIG_POWER_I2C) p->interface = PMIC_I2C; - p->hw.i2c.addr = CONFIG_SYS_FSL_PMIC_I2C_ADDR; + p->hw.i2c.addr = CFG_SYS_FSL_PMIC_I2C_ADDR; p->hw.i2c.tx_num = FSL_PMIC_I2C_LENGTH; #else #error "You must select CONFIG_POWER_SPI or CONFIG_POWER_I2C" diff --git a/drivers/qe/qe.c b/drivers/qe/qe.c index 2799ef374d26..fb1f683f9bd4 100644 --- a/drivers/qe/qe.c +++ b/drivers/qe/qe.c @@ -238,7 +238,7 @@ void u_qe_init(void)
if (src == BOOT_SOURCE_QSPI_NOR) addr = (void *)(CONFIG_SYS_QE_FW_ADDR + - CONFIG_SYS_FSL_QSPI_BASE); + CFG_SYS_FSL_QSPI_BASE);
if (src == BOOT_SOURCE_SD_MMC) { int dev = CONFIG_SYS_MMC_ENV_DEV; @@ -467,7 +467,7 @@ int qe_upload_firmware(const struct qe_firmware *firmware) const struct qe_header *hdr; #ifdef CONFIG_DEEP_SLEEP #ifdef CONFIG_ARCH_LS1021A - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; #else ccsr_gur_t *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); #endif @@ -607,7 +607,7 @@ int u_qe_upload_firmware(const struct qe_firmware *firmware) const struct qe_header *hdr; #ifdef CONFIG_DEEP_SLEEP #ifdef CONFIG_ARCH_LS1021A - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; #else ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); #endif @@ -720,7 +720,7 @@ int u_qe_firmware_resume(const struct qe_firmware *firmware, qe_map_t *qe_immrr) #ifdef CONFIG_PPC ccsr_gur_t __iomem *gur = (void *)(CFG_SYS_MPC85xx_GUTS_ADDR); #else - struct ccsr_gur __iomem *gur = (void *)CONFIG_SYS_FSL_GUTS_ADDR; + struct ccsr_gur __iomem *gur = (void *)CFG_SYS_FSL_GUTS_ADDR; #endif #endif
diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index 2529c9380dbb..ced01249285c 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -216,7 +216,7 @@
#ifdef CONFIG_MMC #define CONFIG_FSL_ESDHC_PIN_MUX -#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC83xx_ESDHC_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC83xx_ESDHC_ADDR #endif
/* diff --git a/include/configs/P1010RDB.h b/include/configs/P1010RDB.h index 03b823db0e18..addb306d57fc 100644 --- a/include/configs/P1010RDB.h +++ b/include/configs/P1010RDB.h @@ -392,7 +392,7 @@ extern unsigned long get_sdram_size(void); #endif /* CONFIG_TSEC_ENET */
#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR #endif
/* diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index c2c03c82eb10..50cb6222d33a 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -308,7 +308,7 @@ #endif
#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR #endif
/* diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 2366b2abdca4..463fa6c714c6 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -365,7 +365,7 @@ * SDHC */ #ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR #endif
/* Qman/Bman */ diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 148c9c425d80..77e1d9f14132 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -346,7 +346,7 @@ */
#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR #endif
/* Qman/Bman */ diff --git a/include/configs/T208xQDS.h b/include/configs/T208xQDS.h index 5e54a1fe66e5..d0cd15012070 100644 --- a/include/configs/T208xQDS.h +++ b/include/configs/T208xQDS.h @@ -422,7 +422,7 @@ * SDHC */ #ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR #endif
/* diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index 49d6eaf79c8e..dfaf0d095d01 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -379,7 +379,7 @@ * SDHC */ #ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR #endif
/* diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 493c195aa607..9e40c572d6f2 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -382,7 +382,7 @@ */
#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR #endif
diff --git a/include/configs/apalis-imx8.h b/include/configs/apalis-imx8.h index c9f876f5da7e..e2e491bdb0aa 100644 --- a/include/configs/apalis-imx8.h +++ b/include/configs/apalis-imx8.h @@ -9,7 +9,7 @@ #include <asm/arch/imx-regs.h> #include <linux/sizes.h>
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5b010000 #define USDHC2_BASE_ADDR 0x5b020000
@@ -61,7 +61,7 @@ /* Link Definitions */
/* On Apalis iMX8 USDHC1 is eMMC, USDHC2 is 8-bit and USDHC3 is 4-bit MMC/SD */ -#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CFG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 diff --git a/include/configs/apalis_imx6.h b/include/configs/apalis_imx6.h index 8f3389434757..192c9cf0c30c 100644 --- a/include/configs/apalis_imx6.h +++ b/include/configs/apalis_imx6.h @@ -22,8 +22,8 @@ #define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CFG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_USDHC_NUM 3
/* Network */ #define PHY_ANEG_TIMEOUT 15000 /* PHY needs longer aneg time */ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 8997c6a0ea90..1f2b3b58ca69 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -26,7 +26,7 @@
/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define CONFIG_FEC_MXC_PHYADDR 0
@@ -412,7 +412,7 @@ #define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
-#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_USDHC_NUM 2
/* DMA stuff, needed for GPMI/MXS NAND support */
diff --git a/include/configs/cgtqmx8.h b/include/configs/cgtqmx8.h index 2c0bf877e86b..c395384c8d38 100644 --- a/include/configs/cgtqmx8.h +++ b/include/configs/cgtqmx8.h @@ -20,7 +20,7 @@ /* Flat Device Tree Definitions */
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 #define USDHC3_BASE_ADDR 0x5B030000 @@ -109,7 +109,7 @@
/* Link Definitions */
-#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CFG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 diff --git a/include/configs/cl-som-imx7.h b/include/configs/cl-som-imx7.h index 1043eb75060f..cbf85341a64d 100644 --- a/include/configs/cl-som-imx7.h +++ b/include/configs/cl-som-imx7.h @@ -92,9 +92,9 @@
/* MMC Config*/ #ifdef CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
-#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_USDHC_NUM 2 #endif
/* USB Configs */ diff --git a/include/configs/cm_fx6.h b/include/configs/cm_fx6.h index e5e8c13090a8..874c0eb2175a 100644 --- a/include/configs/cm_fx6.h +++ b/include/configs/cm_fx6.h @@ -15,8 +15,8 @@ /* Machine config */
/* MMC */ -#define CONFIG_SYS_FSL_USDHC_NUM 3 -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR +#define CFG_SYS_FSL_USDHC_NUM 3 +#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* RAM */ #define PHYS_SDRAM_1 MMDC0_ARB_BASE_ADDR diff --git a/include/configs/colibri-imx6ull.h b/include/configs/colibri-imx6ull.h index 2d29503a985d..f111abce3397 100644 --- a/include/configs/colibri-imx6ull.h +++ b/include/configs/colibri-imx6ull.h @@ -18,8 +18,8 @@ /* ENET1 */
/* MMC Config */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CFG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_USDHC_NUM 1
#define CONFIG_IPADDR 192.168.10.2 #define CONFIG_NETMASK 255.255.255.0 diff --git a/include/configs/colibri-imx8x.h b/include/configs/colibri-imx8x.h index 5d6449c7f74a..d641fbf47e75 100644 --- a/include/configs/colibri-imx8x.h +++ b/include/configs/colibri-imx8x.h @@ -10,7 +10,7 @@ #include <linux/sizes.h> #include <linux/stringify.h>
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5b010000 #define USDHC2_BASE_ADDR 0x5b020000
@@ -94,7 +94,7 @@ /* Environment in eMMC, before config block at the end of 1st "boot sector" */
/* On Colibri iMX8X USDHC1 is eMMC, USDHC2 is 4-bit SD */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_USDHC_NUM 2
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 diff --git a/include/configs/colibri_imx6.h b/include/configs/colibri_imx6.h index d8b873662384..14fdf5b50e66 100644 --- a/include/configs/colibri_imx6.h +++ b/include/configs/colibri_imx6.h @@ -22,8 +22,8 @@ #define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_USDHC_NUM 2
/* USB Configs */ /* Host */ diff --git a/include/configs/colibri_imx7.h b/include/configs/colibri_imx7.h index c95b732f8dcc..7380440ae7aa 100644 --- a/include/configs/colibri_imx7.h +++ b/include/configs/colibri_imx7.h @@ -14,11 +14,11 @@ #include "mx7_common.h"
/* MMC Config*/ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR 0 #ifdef CONFIG_TARGET_COLIBRI_IMX7_NAND -#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CFG_SYS_FSL_USDHC_NUM 1 #elif CONFIG_TARGET_COLIBRI_IMX7_EMMC -#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_USDHC_NUM 2 #endif
#define CONFIG_IPADDR 192.168.10.2 diff --git a/include/configs/dart_6ul.h b/include/configs/dart_6ul.h index 36052fe7d867..6079596caec0 100644 --- a/include/configs/dart_6ul.h +++ b/include/configs/dart_6ul.h @@ -15,9 +15,9 @@
/* NAND pin conflicts with usdhc2 */ #ifdef CONFIG_CMD_NAND -#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CFG_SYS_FSL_USDHC_NUM 1 #else -#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_USDHC_NUM 2 #endif
#ifdef CONFIG_CMD_NET @@ -35,7 +35,7 @@
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* I2C configs */
diff --git a/include/configs/dh_imx6.h b/include/configs/dh_imx6.h index 2040deb2b877..54b2192b4a83 100644 --- a/include/configs/dh_imx6.h +++ b/include/configs/dh_imx6.h @@ -27,8 +27,8 @@ /* Miscellaneous configurable options */
/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CFG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_USDHC_NUM 3
/* UART */ #define CONFIG_MXC_UART_BASE UART1_BASE diff --git a/include/configs/display5.h b/include/configs/display5.h index c23a57ee7a2b..eb65f17cbe48 100644 --- a/include/configs/display5.h +++ b/include/configs/display5.h @@ -42,8 +42,8 @@ #define CONFIG_I2C_MULTI_BUS
/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_USDHC_NUM 2
#define PARTS_DEFAULT \ /* Linux partitions */ \ diff --git a/include/configs/el6x_common.h b/include/configs/el6x_common.h index 7fc3459ef295..affe20a10198 100644 --- a/include/configs/el6x_common.h +++ b/include/configs/el6x_common.h @@ -17,8 +17,8 @@ #endif
/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_USDHC_NUM 2
/* PMIC */ #define CONFIG_POWER_PFUZE100 diff --git a/include/configs/embestmx6boards.h b/include/configs/embestmx6boards.h index 7526d3b0f515..555239b8e813 100644 --- a/include/configs/embestmx6boards.h +++ b/include/configs/embestmx6boards.h @@ -22,7 +22,7 @@ #define CONFIG_MXC_USB_FLAGS 0
/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR 0
/* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR @@ -36,11 +36,11 @@ #if defined(CONFIG_ENV_IS_IN_MMC) /* RiOTboard */ #define CONFIG_FDTFILE "imx6dl-riotboard.dtb" -#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CFG_SYS_FSL_USDHC_NUM 3 #elif defined(CONFIG_ENV_IS_IN_SPI_FLASH) /* MarSBoard */ #define CONFIG_FDTFILE "imx6q-marsboard.dtb" -#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_USDHC_NUM 2 #endif
/* Framebuffer */ diff --git a/include/configs/ge_bx50v3.h b/include/configs/ge_bx50v3.h index ad00769bdeef..c46102fc3f3d 100644 --- a/include/configs/ge_bx50v3.h +++ b/include/configs/ge_bx50v3.h @@ -100,7 +100,7 @@
/* environment organization */
-#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CFG_SYS_FSL_USDHC_NUM 3
/* Framebuffer */ #define CONFIG_HIDE_LOGO_VERSION diff --git a/include/configs/gw_ventana.h b/include/configs/gw_ventana.h index 7300fcd90ba9..abfac3dc5e5f 100644 --- a/include/configs/gw_ventana.h +++ b/include/configs/gw_ventana.h @@ -22,7 +22,7 @@ /* NAND */
/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR 0
/* * PCI express diff --git a/include/configs/imx6_logic.h b/include/configs/imx6_logic.h index 619399366a23..a4dbf6daa6dd 100644 --- a/include/configs/imx6_logic.h +++ b/include/configs/imx6_logic.h @@ -18,8 +18,8 @@ #include "mx6_common.h"
/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_USDHC_NUM 2
/* Ethernet Configs */ diff --git a/include/configs/imx6q-bosch-acc.h b/include/configs/imx6q-bosch-acc.h index 201684ba802c..5025ad9d9f2e 100644 --- a/include/configs/imx6q-bosch-acc.h +++ b/include/configs/imx6q-bosch-acc.h @@ -94,17 +94,17 @@ #include "imx6_spl.h"
#ifdef CONFIG_SPL_BUILD -#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_USDHC_NUM 2
#ifdef CONFIG_SYS_BOOT_EMMC
/* Boot from eMMC */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 1 +#define CFG_SYS_FSL_ESDHC_ADDR 1
#else
/* Boot from SD-card */ -# define CONFIG_SYS_FSL_ESDHC_ADDR 0 +# define CFG_SYS_FSL_ESDHC_ADDR 0
#endif
diff --git a/include/configs/imx7-cm.h b/include/configs/imx7-cm.h index f0f800b8409b..caa6a11d4077 100644 --- a/include/configs/imx7-cm.h +++ b/include/configs/imx7-cm.h @@ -74,8 +74,8 @@ #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Config*/ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR -#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR +#define CFG_SYS_FSL_USDHC_NUM 2
/* USB Configs */ diff --git a/include/configs/imx8mm-cl-iot-gate.h b/include/configs/imx8mm-cl-iot-gate.h index 8046a13e8003..917d567d2eca 100644 --- a/include/configs/imx8mm-cl-iot-gate.h +++ b/include/configs/imx8mm-cl-iot-gate.h @@ -133,8 +133,8 @@
/* USDHC */
-#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_FEC_MXC_PHYADDR 0
diff --git a/include/configs/imx8mm_data_modul_edm_sbc.h b/include/configs/imx8mm_data_modul_edm_sbc.h index 363378b574c7..dd9f93f35c29 100644 --- a/include/configs/imx8mm_data_modul_edm_sbc.h +++ b/include/configs/imx8mm_data_modul_edm_sbc.h @@ -31,8 +31,8 @@ #define PHY_ANEG_TIMEOUT 20000
/* USDHC */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_EXTRA_ENV_SETTINGS \ "altbootcmd=setenv devpart 2 && run bootcmd ; reset\0" \ diff --git a/include/configs/imx8mm_icore_mx8mm.h b/include/configs/imx8mm_icore_mx8mm.h index 66bc8eef8d96..9cdba70493b2 100644 --- a/include/configs/imx8mm_icore_mx8mm.h +++ b/include/configs/imx8mm_icore_mx8mm.h @@ -48,7 +48,7 @@ #define PHYS_SDRAM_SIZE SZ_2G /* 2GB DDR */
/* USDHC */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif /* __IMX8MM_ICORE_MX8MM_H */ diff --git a/include/configs/imx8mn_bsh_smm_s2pro.h b/include/configs/imx8mn_bsh_smm_s2pro.h index 37fda66f98e6..035e5c7bd90f 100644 --- a/include/configs/imx8mn_bsh_smm_s2pro.h +++ b/include/configs/imx8mn_bsh_smm_s2pro.h @@ -30,6 +30,6 @@ #define PHYS_SDRAM_SIZE SZ_512M
/* USDHC */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif /* __IMX8MN_BSH_SMM_S2PRO_H */ diff --git a/include/configs/imx8mn_var_som.h b/include/configs/imx8mn_var_som.h index a1a93e6bee57..a484d9136492 100644 --- a/include/configs/imx8mn_var_som.h +++ b/include/configs/imx8mn_var_som.h @@ -51,6 +51,6 @@ #define PHYS_SDRAM_SIZE SZ_1G /* 1GB DDR */
/* USDHC */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif /* __IMX8MN_VAR_SOM_H */ diff --git a/include/configs/imx8mp_dhcom_pdk2.h b/include/configs/imx8mp_dhcom_pdk2.h index 124119edc98b..bf8782513644 100644 --- a/include/configs/imx8mp_dhcom_pdk2.h +++ b/include/configs/imx8mp_dhcom_pdk2.h @@ -25,8 +25,8 @@ #define FEC_QUIRK_ENET_MAC
/* USDHC */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_EXTRA_ENV_SETTINGS \ "altbootcmd=run bootcmd ; reset\0" \ diff --git a/include/configs/imx8mp_rsb3720.h b/include/configs/imx8mp_rsb3720.h index 5caabf21a646..5be46090a145 100644 --- a/include/configs/imx8mp_rsb3720.h +++ b/include/configs/imx8mp_rsb3720.h @@ -150,8 +150,8 @@
#define CONFIG_MXC_UART_BASE UART3_BASE_ADDR
-#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_ESDHC_ADDR 0
#ifdef CONFIG_FSL_FSPI #define FSL_FSPI_FLASH_SIZE SZ_32M diff --git a/include/configs/imx8mq_cm.h b/include/configs/imx8mq_cm.h index 6aad04e9e97e..4b2107e40574 100644 --- a/include/configs/imx8mq_cm.h +++ b/include/configs/imx8mq_cm.h @@ -56,7 +56,7 @@
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
-#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif diff --git a/include/configs/imx8mq_evk.h b/include/configs/imx8mq_evk.h index 8ecd3b7c2717..2d4c8d78c676 100644 --- a/include/configs/imx8mq_evk.h +++ b/include/configs/imx8mq_evk.h @@ -62,7 +62,7 @@
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
-#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif diff --git a/include/configs/imx8mq_phanbell.h b/include/configs/imx8mq_phanbell.h index df5af640d45e..1905e538c5be 100644 --- a/include/configs/imx8mq_phanbell.h +++ b/include/configs/imx8mq_phanbell.h @@ -94,7 +94,7 @@
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
-#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif diff --git a/include/configs/imx8qm_rom7720.h b/include/configs/imx8qm_rom7720.h index 308f17fd5959..67f19bc19220 100644 --- a/include/configs/imx8qm_rom7720.h +++ b/include/configs/imx8qm_rom7720.h @@ -11,7 +11,7 @@ #include <asm/arch/imx-regs.h>
#define CONFIG_SYS_BOOTMAPSZ (256 << 20) -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR 0 #define USDHC1_BASE_ADDR 0x5B010000 #define USDHC2_BASE_ADDR 0x5B020000 #define USDHC3_BASE_ADDR 0x5B030000 @@ -106,7 +106,7 @@ * USDHC3 is for SD on base board On DDR4 board, USDHC1 is mux for NAND, * USDHC2 is for SD, USDHC3 is for SD on base board */ -#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CFG_SYS_FSL_USDHC_NUM 3
#define CONFIG_SYS_SDRAM_BASE 0x80000000 #define PHYS_SDRAM_1 0x80000000 diff --git a/include/configs/imx93_evk.h b/include/configs/imx93_evk.h index a9749a1bcaa2..b28146640863 100644 --- a/include/configs/imx93_evk.h +++ b/include/configs/imx93_evk.h @@ -131,7 +131,7 @@ #define PHYS_SDRAM 0x80000000 #define PHYS_SDRAM_SIZE 0x80000000 /* 2GB DDR */
-#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_USDHC_NUM 2
/* Using ULP WDOG for reset */ #define WDOG_BASE_ADDR WDG3_BASE_ADDR diff --git a/include/configs/kontron-sl-mx6ul.h b/include/configs/kontron-sl-mx6ul.h index f0586f7f721b..e36dc3f92f95 100644 --- a/include/configs/kontron-sl-mx6ul.h +++ b/include/configs/kontron-sl-mx6ul.h @@ -45,8 +45,8 @@
/* MMC Configs */ #ifdef CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR -#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR +#define CFG_SYS_FSL_USDHC_NUM 2 #endif
#define CONFIG_EXTRA_ENV_SETTINGS BOOTENV diff --git a/include/configs/kontron_pitx_imx8m.h b/include/configs/kontron_pitx_imx8m.h index 5b461d290b70..6acd2f792534 100644 --- a/include/configs/kontron_pitx_imx8m.h +++ b/include/configs/kontron_pitx_imx8m.h @@ -70,7 +70,7 @@
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(3)
-#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif diff --git a/include/configs/kontron_sl28.h b/include/configs/kontron_sl28.h index de20f9b2e002..38860bfd5ca8 100644 --- a/include/configs/kontron_sl28.h +++ b/include/configs/kontron_sl28.h @@ -20,7 +20,7 @@
#define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
@@ -32,7 +32,7 @@ /* generic timer */
/* early heap for SPL DM */ -#define CONFIG_MALLOC_F_ADDR CONFIG_SYS_FSL_OCRAM_BASE +#define CONFIG_MALLOC_F_ADDR CFG_SYS_FSL_OCRAM_BASE
/* serial port */ #define CONFIG_SYS_NS16550_CLK (get_bus_freq(0) / 2) diff --git a/include/configs/librem5.h b/include/configs/librem5.h index a83363ec869a..dbd7d107dae9 100644 --- a/include/configs/librem5.h +++ b/include/configs/librem5.h @@ -25,7 +25,7 @@
#endif /* CONFIG_SPL_BUILD*/
-#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_USDHC_NUM 2
#define CONFIG_USBD_HS
@@ -88,6 +88,6 @@
/* Monitor Command Prompt */
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif diff --git a/include/configs/liteboard.h b/include/configs/liteboard.h index a1fc056c305a..a784002158b0 100644 --- a/include/configs/liteboard.h +++ b/include/configs/liteboard.h @@ -20,7 +20,7 @@
/* MMC Configs */ #ifdef CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR #endif
#define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/ls1012a_common.h b/include/configs/ls1012a_common.h index 87eb10db19fd..77f84e1c9eaa 100644 --- a/include/configs/ls1012a_common.h +++ b/include/configs/ls1012a_common.h @@ -11,12 +11,12 @@ #include <linux/sizes.h>
#define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
/*SPI device */ -#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 +#define CFG_SYS_FSL_QSPI_BASE 0x40000000
/* SATA */
diff --git a/include/configs/ls1012afrwy.h b/include/configs/ls1012afrwy.h index a0ff3b897904..1b417c72e704 100644 --- a/include/configs/ls1012afrwy.h +++ b/include/configs/ls1012afrwy.h @@ -17,7 +17,7 @@ #define SYS_SDRAM_SIZE_1024 0x40000000
/* ENV */ -#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 +#define CFG_SYS_FSL_QSPI_BASE 0x40000000
#undef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/ls1028a_common.h b/include/configs/ls1028a_common.h index 24422665e876..43dbeea1b3bd 100644 --- a/include/configs/ls1028a_common.h +++ b/include/configs/ls1028a_common.h @@ -14,7 +14,7 @@
#define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL
@@ -57,7 +57,7 @@ "env exists secureboot && esbc_halt;"
#define OCRAM_NONSECURE_SIZE 0x00010000 -#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 +#define CFG_SYS_FSL_QSPI_BASE 0x20000000
/* I2C bus multiplexer */ #define I2C_MUX_PCA_ADDR_PRI 0x77 /* Primary Mux*/ diff --git a/include/configs/ls1043a_common.h b/include/configs/ls1043a_common.h index c43eb232fb27..4468070d5a85 100644 --- a/include/configs/ls1043a_common.h +++ b/include/configs/ls1043a_common.h @@ -33,7 +33,7 @@
#define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
diff --git a/include/configs/ls1046a_common.h b/include/configs/ls1046a_common.h index e94ed26337c9..1eedbdef246d 100644 --- a/include/configs/ls1046a_common.h +++ b/include/configs/ls1046a_common.h @@ -33,7 +33,7 @@
#define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000 -#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x880000000ULL
diff --git a/include/configs/ls1046afrwy.h b/include/configs/ls1046afrwy.h index 582b1ee93cd0..48408f285834 100644 --- a/include/configs/ls1046afrwy.h +++ b/include/configs/ls1046afrwy.h @@ -73,7 +73,7 @@ /* * Environment */ -#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 +#define CFG_SYS_FSL_QSPI_BASE 0x40000000
#undef BOOT_TARGET_DEVICES #define BOOT_TARGET_DEVICES(func) \ diff --git a/include/configs/ls1046ardb.h b/include/configs/ls1046ardb.h index f5f16bae2d60..769349336af9 100644 --- a/include/configs/ls1046ardb.h +++ b/include/configs/ls1046ardb.h @@ -104,7 +104,7 @@ /* * Environment */ -#define CONFIG_SYS_FSL_QSPI_BASE 0x40000000 +#define CFG_SYS_FSL_QSPI_BASE 0x40000000
#define AQR105_IRQ_MASK 0x80000000 /* FMan */ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index bbe52824ccd9..846667c325ec 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -27,11 +27,11 @@ /* Link Definitions */
/* Link Definitions */ -#define CONFIG_SYS_FSL_QSPI_BASE 0x20000000 +#define CFG_SYS_FSL_QSPI_BASE 0x20000000
#define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL /* diff --git a/include/configs/ls2080a_common.h b/include/configs/ls2080a_common.h index b0f686084f48..9f5ca2c7a034 100644 --- a/include/configs/ls2080a_common.h +++ b/include/configs/ls2080a_common.h @@ -18,7 +18,7 @@
#define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_DDR_BLOCK2_BASE 0x8080000000ULL
diff --git a/include/configs/lx2160a_common.h b/include/configs/lx2160a_common.h index 59e54bf6f074..8b2b7479c11b 100644 --- a/include/configs/lx2160a_common.h +++ b/include/configs/lx2160a_common.h @@ -15,7 +15,7 @@ /* DDR */ #define CONFIG_VERY_BIG_RAM #define CONFIG_SYS_DDR_SDRAM_BASE 0x80000000UL -#define CONFIG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 +#define CFG_SYS_FSL_DDR_SDRAM_BASE_PHY 0 #define CONFIG_SYS_DDR_BLOCK2_BASE 0x2080000000ULL #define CONFIG_SYS_SDRAM_SIZE 0x200000000UL #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE diff --git a/include/configs/m53menlo.h b/include/configs/m53menlo.h index bf1560b23b95..f3259f7e5de2 100644 --- a/include/configs/m53menlo.h +++ b/include/configs/m53menlo.h @@ -37,7 +37,7 @@ * MMC Driver */ #ifdef CONFIG_CMD_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR 0 #endif
/* diff --git a/include/configs/mccmon6.h b/include/configs/mccmon6.h index 17986a0e348a..69ca7c527534 100644 --- a/include/configs/mccmon6.h +++ b/include/configs/mccmon6.h @@ -22,8 +22,8 @@ #define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configuration */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_ESDHC_ADDR 0
/* NOR 16-bit mode */ #define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR diff --git a/include/configs/mx51evk.h b/include/configs/mx51evk.h index fbc9a0416938..95afb350ec34 100644 --- a/include/configs/mx51evk.h +++ b/include/configs/mx51evk.h @@ -34,7 +34,7 @@ /* * MMC Configs * */ -#define CONFIG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR MMC_SDHC1_BASE_ADDR
/* USB Configs */ #define CONFIG_MXC_USB_PORT 1 diff --git a/include/configs/mx53cx9020.h b/include/configs/mx53cx9020.h index d58d1534a3bd..778356397202 100644 --- a/include/configs/mx53cx9020.h +++ b/include/configs/mx53cx9020.h @@ -17,7 +17,7 @@ #define CONFIG_MXC_UART_BASE UART2_BASE
/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR 0
/* bootz: zImage/initrd.img support */
diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 60ec34cf8e06..3c9b2ad58ee4 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -14,7 +14,7 @@ #define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR 0
/* USB Configs */ #define CONFIG_MXC_USB_PORT 1 @@ -25,7 +25,7 @@ #define CONFIG_POWER_FSL #define CONFIG_POWER_FSL_MC13892 #define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 -#define CONFIG_SYS_FSL_PMIC_I2C_ADDR 0x8 +#define CFG_SYS_FSL_PMIC_I2C_ADDR 0x8
/* Command definition */
diff --git a/include/configs/mx6cuboxi.h b/include/configs/mx6cuboxi.h index cffbb64bcd53..bc90b9563ade 100644 --- a/include/configs/mx6cuboxi.h +++ b/include/configs/mx6cuboxi.h @@ -14,7 +14,7 @@ #include "imx6_spl.h"
/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* Framebuffer */ #define CONFIG_IMX_HDMI diff --git a/include/configs/mx6sabre_common.h b/include/configs/mx6sabre_common.h index bfcab1bed5b8..bc9fab12909a 100644 --- a/include/configs/mx6sabre_common.h +++ b/include/configs/mx6sabre_common.h @@ -13,7 +13,7 @@ #include "mx6_common.h"
/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR 0
#ifdef CONFIG_SUPPORT_EMMC_BOOT #define EMMC_ENV \ diff --git a/include/configs/mx6sabreauto.h b/include/configs/mx6sabreauto.h index 7e54bb2312bc..61570b7af534 100644 --- a/include/configs/mx6sabreauto.h +++ b/include/configs/mx6sabreauto.h @@ -33,7 +33,7 @@ #define CONFIG_SYS_FLASH_BASE WEIM_ARB_BASE_ADDR #endif
-#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_USDHC_NUM 2
/* NAND stuff */ #define CONFIG_SYS_NAND_BASE 0x40000000 diff --git a/include/configs/mx6sabresd.h b/include/configs/mx6sabresd.h index 16f8858abb8f..49cd1512dc58 100644 --- a/include/configs/mx6sabresd.h +++ b/include/configs/mx6sabresd.h @@ -21,7 +21,7 @@
/* Falcon Mode - MMC support: args@1MB kernel@2MB */
-#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CFG_SYS_FSL_USDHC_NUM 3
#ifdef CONFIG_CMD_PCI #define CONFIG_PCIE_IMX_PERST_GPIO IMX_GPIO_NR(7, 12) diff --git a/include/configs/mx6slevk.h b/include/configs/mx6slevk.h index 9f890938f982..26b97bd3f2e4 100644 --- a/include/configs/mx6slevk.h +++ b/include/configs/mx6slevk.h @@ -17,7 +17,7 @@ #define CONFIG_MXC_UART_BASE UART1_IPS_BASE_ADDR
/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
#define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ @@ -98,6 +98,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #endif
-#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CFG_SYS_FSL_USDHC_NUM 3
#endif /* __CONFIG_H */ diff --git a/include/configs/mx6sllevk.h b/include/configs/mx6sllevk.h index e9ccb99d3cec..44a5eeff1984 100644 --- a/include/configs/mx6sllevk.h +++ b/include/configs/mx6sllevk.h @@ -89,8 +89,8 @@ /* Environment organization */
/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR -#define CONFIG_SYS_FSL_USDHC_NUM 3 +#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR +#define CFG_SYS_FSL_USDHC_NUM 3
#define CONFIG_IOMUX_LPSR
diff --git a/include/configs/mx6sxsabreauto.h b/include/configs/mx6sxsabreauto.h index 407b64383ee6..0d9764e3b4c1 100644 --- a/include/configs/mx6sxsabreauto.h +++ b/include/configs/mx6sxsabreauto.h @@ -83,7 +83,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Configuration */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
/* NAND stuff */ #define CONFIG_SYS_NAND_BASE 0x40000000 @@ -100,6 +100,6 @@ #define CONFIG_MXC_USB_FLAGS 0 #endif
-#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_USDHC_NUM 2
#endif /* __CONFIG_H */ diff --git a/include/configs/mx6sxsabresd.h b/include/configs/mx6sxsabresd.h index 570e2ce687ac..83779f09bfc6 100644 --- a/include/configs/mx6sxsabresd.h +++ b/include/configs/mx6sxsabresd.h @@ -115,7 +115,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Configuration */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
/* Network */
diff --git a/include/configs/mx6ul_14x14_evk.h b/include/configs/mx6ul_14x14_evk.h index ab56ea0205da..d0e3d3f02849 100644 --- a/include/configs/mx6ul_14x14_evk.h +++ b/include/configs/mx6ul_14x14_evk.h @@ -22,13 +22,13 @@
/* MMC Configs */ #ifdef CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* NAND pin conflicts with usdhc2 */ #ifdef CONFIG_NAND_MXS -#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CFG_SYS_FSL_USDHC_NUM 1 #else -#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_USDHC_NUM 2 #endif
#endif diff --git a/include/configs/mx6ullevk.h b/include/configs/mx6ullevk.h index 00cc547b900c..604923ec2b77 100644 --- a/include/configs/mx6ullevk.h +++ b/include/configs/mx6ullevk.h @@ -20,8 +20,8 @@
/* MMC Configs */ #ifdef CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR -#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR +#define CFG_SYS_FSL_USDHC_NUM 2 #endif
#define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/mys_6ulx.h b/include/configs/mys_6ulx.h index bb68ddbd39da..a777305ec76e 100644 --- a/include/configs/mys_6ulx.h +++ b/include/configs/mys_6ulx.h @@ -13,13 +13,13 @@ /* SPL options */ #include "imx6_spl.h"
-#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CFG_SYS_FSL_USDHC_NUM 1
/* Console configs */ #define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* Physical Memory Map */ #define PHYS_SDRAM MMDC0_ARB_BASE_ADDR diff --git a/include/configs/nitrogen6x.h b/include/configs/nitrogen6x.h index 26e6de2d2c8d..af6fa6a12681 100644 --- a/include/configs/nitrogen6x.h +++ b/include/configs/nitrogen6x.h @@ -16,8 +16,8 @@ #define CONFIG_MXC_UART_BASE UART2_BASE
/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_USDHC_NUM 2
#define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_FEC_MXC_PHYADDR 6 diff --git a/include/configs/novena.h b/include/configs/novena.h index 1696aa28520f..f2a04ca61854 100644 --- a/include/configs/novena.h +++ b/include/configs/novena.h @@ -43,8 +43,8 @@ /* I2C EEPROM */
/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 -#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_USDHC_NUM 2
/* PCI express */ #ifdef CONFIG_CMD_PCI diff --git a/include/configs/npi_imx6ull.h b/include/configs/npi_imx6ull.h index 8ff26feb741d..ccc203f5f24d 100644 --- a/include/configs/npi_imx6ull.h +++ b/include/configs/npi_imx6ull.h @@ -13,13 +13,13 @@ /* SPL options */ #include "imx6_spl.h"
-#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CFG_SYS_FSL_USDHC_NUM 1
/* Console configs */ #define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
#define CONFIG_NETMASK 255.255.255.0
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index db4aa81bbbc4..75d35d96c6b9 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -417,7 +417,7 @@ */
#ifdef CONFIG_MMC -#define CONFIG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR CFG_SYS_MPC85xx_ESDHC_ADDR #endif
/* diff --git a/include/configs/pcl063.h b/include/configs/pcl063.h index 5b38a94aa5d1..dea87122ebc6 100644 --- a/include/configs/pcl063.h +++ b/include/configs/pcl063.h @@ -22,14 +22,14 @@ * Tweak the SPL text base address to avoid this. */
-#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CFG_SYS_FSL_USDHC_NUM 1
/* Console configs */ #define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
/* Miscellaneous configurable options */
diff --git a/include/configs/pcl063_ull.h b/include/configs/pcl063_ull.h index 688d161964a4..2bdae8afa8c1 100644 --- a/include/configs/pcl063_ull.h +++ b/include/configs/pcl063_ull.h @@ -16,7 +16,7 @@ /* SPL options */ #include "imx6_spl.h"
-#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_USDHC_NUM 2
/* Environment settings */
@@ -29,7 +29,7 @@
/* MMC Configs */
-#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* I2C configs */
diff --git a/include/configs/pico-imx6.h b/include/configs/pico-imx6.h index dcbcd8d24495..687133b9bdda 100644 --- a/include/configs/pico-imx6.h +++ b/include/configs/pico-imx6.h @@ -21,7 +21,7 @@ #define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configuration */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
/* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/pico-imx6ul.h b/include/configs/pico-imx6ul.h index 2ac48c40c96e..8402efaf5bbe 100644 --- a/include/configs/pico-imx6ul.h +++ b/include/configs/pico-imx6ul.h @@ -27,7 +27,7 @@ #define CONFIG_MXC_UART_BASE UART6_BASE_ADDR
/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
/* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/pico-imx7d.h b/include/configs/pico-imx7d.h index 7fbf2c3f55fb..159bf4c68ca5 100644 --- a/include/configs/pico-imx7d.h +++ b/include/configs/pico-imx7d.h @@ -21,7 +21,7 @@ #define CONFIG_MXC_UART_BASE UART5_IPS_BASE_ADDR
/* MMC Config */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_DFU_ENV_SETTINGS \ "dfu_alt_info=" \ @@ -113,7 +113,7 @@
/* Environment starts at 768k = 768 * 1024 = 786432 */
-#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_USDHC_NUM 2
/* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/pico-imx8mq.h b/include/configs/pico-imx8mq.h index 1ee1edbdfffa..17af19d49dc1 100644 --- a/include/configs/pico-imx8mq.h +++ b/include/configs/pico-imx8mq.h @@ -73,7 +73,7 @@
#define CONFIG_MXC_UART_BASE UART_BASE_ADDR(1)
-#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_ESDHC_ADDR 0
#endif diff --git a/include/configs/smegw01.h b/include/configs/smegw01.h index 681c831747ba..faa13c65216f 100644 --- a/include/configs/smegw01.h +++ b/include/configs/smegw01.h @@ -15,7 +15,7 @@ #define PHYS_SDRAM_SIZE SZ_512M
/* MMC Config*/ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_EXTRA_ENV_SETTINGS \ "image=zImage\0" \ diff --git a/include/configs/somlabs_visionsom_6ull.h b/include/configs/somlabs_visionsom_6ull.h index eeee587bafd5..49672dfe7c3f 100644 --- a/include/configs/somlabs_visionsom_6ull.h +++ b/include/configs/somlabs_visionsom_6ull.h @@ -19,9 +19,9 @@
/* MMC Configs */ #ifdef CONFIG_FSL_USDHC -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
-#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CFG_SYS_FSL_USDHC_NUM 1 #endif /* CONFIG_FSL_USDHC */
#define CONFIG_EXTRA_ENV_SETTINGS \ diff --git a/include/configs/tqma6.h b/include/configs/tqma6.h index 9498dbeadf41..2c5891589525 100644 --- a/include/configs/tqma6.h +++ b/include/configs/tqma6.h @@ -44,7 +44,7 @@ #endif
/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR 0
/* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/udoo.h b/include/configs/udoo.h index 03e5c04af6ee..8af5151c503d 100644 --- a/include/configs/udoo.h +++ b/include/configs/udoo.h @@ -15,7 +15,7 @@ #define CONFIG_MXC_UART_BASE UART2_BASE
/* MMC Configuration */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_EXTRA_ENV_SETTINGS \ "console=ttymxc1,115200\0" \ diff --git a/include/configs/udoo_neo.h b/include/configs/udoo_neo.h index e30b6cc82d8b..093e2e8dae7c 100644 --- a/include/configs/udoo_neo.h +++ b/include/configs/udoo_neo.h @@ -15,7 +15,7 @@ #include "imx6_spl.h"
/* MMC Configuration */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* Command definition */ #define CONFIG_MXC_UART_BASE UART1_BASE diff --git a/include/configs/usbarmory.h b/include/configs/usbarmory.h index 08a6f5fbccdc..c381934f31a9 100644 --- a/include/configs/usbarmory.h +++ b/include/configs/usbarmory.h @@ -20,7 +20,7 @@ #define CONFIG_MXC_UART_BASE UART1_BASE
/* SD/MMC */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR 0
/* USB */ #define CONFIG_MXC_USB_PORT 1 diff --git a/include/configs/vf610twr.h b/include/configs/vf610twr.h index dde6d130caa6..7e3d3473b442 100644 --- a/include/configs/vf610twr.h +++ b/include/configs/vf610twr.h @@ -19,7 +19,7 @@ /* Dynamic MTD partition support */ #endif
-#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_ESDHC_ADDR 0
#define CONFIG_FEC_MXC_PHYADDR 0
diff --git a/include/configs/vining_2000.h b/include/configs/vining_2000.h index 6eb022f26c5f..a4484fd3f8ca 100644 --- a/include/configs/vining_2000.h +++ b/include/configs/vining_2000.h @@ -32,7 +32,7 @@ #define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE
/* MMC Configuration */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR USDHC4_BASE_ADDR
/* PMIC */ #define CONFIG_POWER_PFUZE100 diff --git a/include/configs/wandboard.h b/include/configs/wandboard.h index 899b8ca470e2..91c1f4b3b514 100644 --- a/include/configs/wandboard.h +++ b/include/configs/wandboard.h @@ -15,8 +15,8 @@ #define CONFIG_MXC_UART_BASE UART1_BASE
/* MMC Configuration */ -#define CONFIG_SYS_FSL_USDHC_NUM 2 -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CFG_SYS_FSL_USDHC_NUM 2 +#define CFG_SYS_FSL_ESDHC_ADDR 0
/* USB Configs */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/warp7.h b/include/configs/warp7.h index a9cc85953576..a4b12dc55ed0 100644 --- a/include/configs/warp7.h +++ b/include/configs/warp7.h @@ -14,7 +14,7 @@ #define PHYS_SDRAM_SIZE SZ_512M
/* MMC Config*/ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR USDHC3_BASE_ADDR
#define CONFIG_DFU_ENV_SETTINGS \ "dfu_alt_info=boot raw 0x2 0x1000 mmcpart 1\0" \ @@ -90,7 +90,7 @@
/* environment organization */
-#define CONFIG_SYS_FSL_USDHC_NUM 1 +#define CFG_SYS_FSL_USDHC_NUM 1
#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) diff --git a/include/configs/xpress.h b/include/configs/xpress.h index 0e43b373649a..fc8ec3204b1b 100644 --- a/include/configs/xpress.h +++ b/include/configs/xpress.h @@ -16,7 +16,7 @@ #define CONFIG_MXC_UART_BASE MX6UL_UART7_BASE_ADDR
/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR +#define CFG_SYS_FSL_ESDHC_ADDR USDHC2_BASE_ADDR
/* Miscellaneous configurable options */
diff --git a/include/fm_eth.h b/include/fm_eth.h index bf9570679d2e..7475b5150738 100644 --- a/include/fm_eth.h +++ b/include/fm_eth.h @@ -51,18 +51,18 @@ enum fm_eth_type { */ #ifdef CONFIG_SYS_FMAN_V3 #ifdef CONFIG_TARGET_LS1046AFRWY -#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000) +#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfd000) #else -#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfc000) +#define CONFIG_SYS_FM1_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfc000) #endif -#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xfd000) +#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xfd000) #if (CONFIG_SYS_NUM_FMAN == 2) -#define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfc000) -#define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM2_ADDR + 0xfd000) +#define CONFIG_SYS_FM2_DTSEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfc000) +#define CONFIG_SYS_FM2_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM2_ADDR + 0xfd000) #endif #else -#define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xe1120) -#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CONFIG_SYS_FSL_FM1_ADDR + 0xf1000) +#define CONFIG_SYS_FM1_DTSEC1_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xe1120) +#define CONFIG_SYS_FM1_TGEC_MDIO_ADDR (CFG_SYS_FSL_FM1_ADDR + 0xf1000) #endif
#define DEFAULT_FM_MDIO_NAME "FSL_MDIO0" @@ -84,7 +84,7 @@ enum fm_eth_type { .port = FM##idx##_DTSEC##n, \ .rx_port_id = RX_PORT_1G_BASE + n - 1, \ .tx_port_id = TX_PORT_1G_BASE + n - 1, \ - .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \ offsetof(struct ccsr_fman, memac[n-1]),\ }
@@ -98,7 +98,7 @@ enum fm_eth_type { .port = FM##idx##_10GEC##n, \ .rx_port_id = RX_PORT_10G_BASE2 + n - 1, \ .tx_port_id = TX_PORT_10G_BASE2 + n - 1, \ - .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \ offsetof(struct ccsr_fman, memac[n-1]),\ } #else @@ -112,7 +112,7 @@ enum fm_eth_type { .port = FM##idx##_10GEC##n, \ .rx_port_id = RX_PORT_10G_BASE + n - 1, \ .tx_port_id = TX_PORT_10G_BASE + n - 1, \ - .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \ offsetof(struct ccsr_fman, memac[n-1+8]),\ } #else @@ -125,7 +125,7 @@ enum fm_eth_type { .port = FM##idx##_10GEC##n, \ .rx_port_id = RX_PORT_10G_BASE + n - 1, \ .tx_port_id = TX_PORT_10G_BASE + n - 1, \ - .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \ offsetof(struct ccsr_fman, memac[n-1+8]),\ } #endif @@ -141,7 +141,7 @@ enum fm_eth_type { .port = FM##idx##_10GEC##n, \ .rx_port_id = RX_PORT_10G_BASE2 + n - 3, \ .tx_port_id = TX_PORT_10G_BASE2 + n - 3, \ - .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \ offsetof(struct ccsr_fman, memac[n-1-2]),\ } #endif @@ -156,7 +156,7 @@ enum fm_eth_type { .port = FM##idx##_DTSEC##n, \ .rx_port_id = RX_PORT_1G_BASE + n - 1, \ .tx_port_id = TX_PORT_1G_BASE + n - 1, \ - .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \ offsetof(struct ccsr_fman, mac_1g[n-1]),\ }
@@ -169,7 +169,7 @@ enum fm_eth_type { .port = FM##idx##_10GEC##n, \ .rx_port_id = RX_PORT_10G_BASE + n - 1, \ .tx_port_id = TX_PORT_10G_BASE + n - 1, \ - .compat_offset = CONFIG_SYS_FSL_FM##idx##_OFFSET + \ + .compat_offset = CFG_SYS_FSL_FM##idx##_OFFSET + \ offsetof(struct ccsr_fman, mac_10g[n-1]),\ } #endif diff --git a/include/fsl_sec.h b/include/fsl_sec.h index d57c4ca820c8..d8861d1d0b76 100644 --- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -272,7 +272,7 @@ struct sg_entry { #if defined(CONFIG_MX6) || defined(CONFIG_MX7) || \ defined(CONFIG_MX7ULP) || defined(CONFIG_IMX8M) || defined(CONFIG_IMX8) /* Job Ring Base Address */ -#define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1)) +#define JR_BASE_ADDR(x) (CFG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1)) /* Secure Memory Offset varies accross versions */ #define SM_V1_OFFSET 0x0f4 #define SM_V2_OFFSET 0xa00 @@ -287,7 +287,7 @@ struct sg_entry { /* JR Allocation Error */ #define SMCSJR_AERR (3 << 12) /* Secure memory partition 0 page 0 owner register */ -#define CAAM_SMPO_0 (CONFIG_SYS_FSL_SEC_ADDR + 0x1FBC) +#define CAAM_SMPO_0 (CFG_SYS_FSL_SEC_ADDR + 0x1FBC) /* Secure memory command register */ #define CAAM_SMCJR(v, jr) (JR_BASE_ADDR(jr) + SM_OFFSET(v) + SM_CMD(v)) /* Secure memory command status register */
On Fri, 28 Oct 2022 at 18:31, Tom Rini trini@konsulko.com wrote:
Migrate all of COFIG_SYS_FSL* to the CFG_SYS namespace.
Signed-off-by: Tom Rini trini@konsulko.com
README | 8 +- arch/arm/cpu/armv7/ls102xa/clock.c | 4 +- arch/arm/cpu/armv7/ls102xa/cpu.c | 10 +- arch/arm/cpu/armv7/ls102xa/fdt.c | 4 +- arch/arm/cpu/armv7/ls102xa/fsl_ls1_serdes.c | 8 +- arch/arm/cpu/armv7/ls102xa/ls102xa_psci.c | 20 +- arch/arm/cpu/armv7/ls102xa/psci.S | 16 +- arch/arm/cpu/armv7/ls102xa/soc.c | 8 +- arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 48 ++--
Reviewed-by: Simon Glass sjg@chromium.org
Migrate all of CONFIG_HPS* to the CFG namespace.
Signed-off-by: Tom Rini trini@konsulko.com --- arch/arm/mach-socfpga/qts-filter.sh | 4 +- arch/arm/mach-socfpga/wrap_iocsr_config.c | 8 +- arch/arm/mach-socfpga/wrap_pll_config.c | 100 ++++++------ arch/arm/mach-socfpga/wrap_sdram_config.c | 148 +++++++++--------- board/altera/arria5-socdk/qts/iocsr_config.h | 8 +- board/altera/arria5-socdk/qts/pll_config.h | 136 ++++++++-------- board/altera/arria5-socdk/qts/sdram_config.h | 140 ++++++++--------- .../altera/cyclone5-socdk/qts/iocsr_config.h | 8 +- board/altera/cyclone5-socdk/qts/pll_config.h | 136 ++++++++-------- .../altera/cyclone5-socdk/qts/sdram_config.h | 140 ++++++++--------- board/aries/mcvevk/qts/iocsr_config.h | 8 +- board/aries/mcvevk/qts/pll_config.h | 136 ++++++++-------- board/aries/mcvevk/qts/sdram_config.h | 140 ++++++++--------- board/devboards/dbm-soc1/qts/iocsr_config.h | 8 +- board/devboards/dbm-soc1/qts/pll_config.h | 136 ++++++++-------- board/devboards/dbm-soc1/qts/sdram_config.h | 140 ++++++++--------- board/ebv/socrates/qts/iocsr_config.h | 8 +- board/ebv/socrates/qts/pll_config.h | 136 ++++++++-------- board/ebv/socrates/qts/sdram_config.h | 140 ++++++++--------- board/is1/qts/iocsr_config.h | 8 +- board/is1/qts/pll_config.h | 136 ++++++++-------- board/is1/qts/sdram_config.h | 140 ++++++++--------- board/keymile/secu1/qts/iocsr_config.h | 8 +- board/keymile/secu1/qts/pll_config.h | 136 ++++++++-------- board/keymile/secu1/qts/sdram_config.h | 140 ++++++++--------- board/softing/vining_fpga/qts/iocsr_config.h | 8 +- board/softing/vining_fpga/qts/pll_config.h | 136 ++++++++-------- board/softing/vining_fpga/qts/sdram_config.h | 140 ++++++++--------- board/sr1500/qts/iocsr_config.h | 8 +- board/sr1500/qts/pll_config.h | 136 ++++++++-------- board/sr1500/qts/sdram_config.h | 140 ++++++++--------- board/terasic/de0-nano-soc/qts/iocsr_config.h | 8 +- board/terasic/de0-nano-soc/qts/pll_config.h | 136 ++++++++-------- board/terasic/de0-nano-soc/qts/sdram_config.h | 146 ++++++++--------- board/terasic/de1-soc/qts/iocsr_config.h | 8 +- board/terasic/de1-soc/qts/pll_config.h | 148 +++++++++--------- board/terasic/de1-soc/qts/sdram_config.h | 140 ++++++++--------- board/terasic/de10-nano/qts/iocsr_config.h | 8 +- board/terasic/de10-nano/qts/pll_config.h | 136 ++++++++-------- board/terasic/de10-nano/qts/sdram_config.h | 140 ++++++++--------- .../terasic/de10-standard/qts/iocsr_config.h | 8 +- board/terasic/de10-standard/qts/pll_config.h | 136 ++++++++-------- .../terasic/de10-standard/qts/sdram_config.h | 140 ++++++++--------- board/terasic/sockit/qts/iocsr_config.h | 8 +- board/terasic/sockit/qts/pll_config.h | 136 ++++++++-------- board/terasic/sockit/qts/sdram_config.h | 140 ++++++++--------- 46 files changed, 2127 insertions(+), 2127 deletions(-)
diff --git a/arch/arm/mach-socfpga/qts-filter.sh b/arch/arm/mach-socfpga/qts-filter.sh index a49cd1b68a9e..203f99e3f560 100755 --- a/arch/arm/mach-socfpga/qts-filter.sh +++ b/arch/arm/mach-socfpga/qts-filter.sh @@ -36,7 +36,7 @@ EOF # Retrieve the scan chain lengths fix_newlines_in_macros \ ${in_bsp_dir}/generated/iocsr_config_${soc}.h | - grep 'CONFIG_HPS_IOCSR_SCANCHAIN[0-9]+_LENGTH' | tr -d "()" + grep 'CFG_HPS_IOCSR_SCANCHAIN[0-9]+_LENGTH' | tr -d "()"
echo ""
@@ -128,7 +128,7 @@ EOF # Filter out only the macros which are actually used by the code # grep_sdram_config() { - egrep "#define (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ|CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_EMR_OCD_ENABLE|RW_MGR_EMR|RW_MGR_EMR2|RW_MGR_EMR3|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_INIT_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MR_CALIB|RW_MGR_MR_USER|RW_MGR_MR_DLL_RESET|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_NOP|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|AFI_CLK_FREQ|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC|CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)[[:space:]]" + egrep "#define (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE|CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL|CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER|CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT|CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN|CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW|CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR|CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD|CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT|CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT|CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES|CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES|CFG_HPS_SDR_CTRLCFG_DRAMODT_READ|CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS|CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS|CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH|CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH|CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN|CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK|CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL|CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA|CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH|CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH|CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP|CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP|CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP|CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP|CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR|CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN|CFG_HPS_SDR_CTRLCFG_FPGAPORTRST|CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE|CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC|CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14|CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46|CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0|CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0|CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32|CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0|CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4|CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36|CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0|CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32|CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64|RW_MGR_ACTIVATE_0_AND_1|RW_MGR_ACTIVATE_0_AND_1_WAIT1|RW_MGR_ACTIVATE_0_AND_1_WAIT2|RW_MGR_ACTIVATE_1|RW_MGR_CLEAR_DQS_ENABLE|RW_MGR_EMR_OCD_ENABLE|RW_MGR_EMR|RW_MGR_EMR2|RW_MGR_EMR3|RW_MGR_GUARANTEED_READ|RW_MGR_GUARANTEED_READ_CONT|RW_MGR_GUARANTEED_WRITE|RW_MGR_GUARANTEED_WRITE_WAIT0|RW_MGR_GUARANTEED_WRITE_WAIT1|RW_MGR_GUARANTEED_WRITE_WAIT2|RW_MGR_GUARANTEED_WRITE_WAIT3|RW_MGR_IDLE|RW_MGR_IDLE_LOOP1|RW_MGR_IDLE_LOOP2|RW_MGR_INIT_RESET_0_CKE_0|RW_MGR_INIT_RESET_1_CKE_0|RW_MGR_INIT_CKE_0|RW_MGR_LFSR_WR_RD_BANK_0|RW_MGR_LFSR_WR_RD_BANK_0_DATA|RW_MGR_LFSR_WR_RD_BANK_0_DQS|RW_MGR_LFSR_WR_RD_BANK_0_NOP|RW_MGR_LFSR_WR_RD_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_BANK_0_WL_1|RW_MGR_LFSR_WR_RD_DM_BANK_0|RW_MGR_LFSR_WR_RD_DM_BANK_0_DATA|RW_MGR_LFSR_WR_RD_DM_BANK_0_DQS|RW_MGR_LFSR_WR_RD_DM_BANK_0_NOP|RW_MGR_LFSR_WR_RD_DM_BANK_0_WAIT|RW_MGR_LFSR_WR_RD_DM_BANK_0_WL_1|RW_MGR_MR_CALIB|RW_MGR_MR_USER|RW_MGR_MR_DLL_RESET|RW_MGR_MRS0_DLL_RESET|RW_MGR_MRS0_DLL_RESET_MIRR|RW_MGR_MRS0_USER|RW_MGR_MRS0_USER_MIRR|RW_MGR_MRS1|RW_MGR_MRS1_MIRR|RW_MGR_MRS2|RW_MGR_MRS2_MIRR|RW_MGR_MRS3|RW_MGR_MRS3_MIRR|RW_MGR_NOP|RW_MGR_PRECHARGE_ALL|RW_MGR_READ_B2B|RW_MGR_READ_B2B_WAIT1|RW_MGR_READ_B2B_WAIT2|RW_MGR_REFRESH|RW_MGR_REFRESH_ALL|RW_MGR_RETURN|RW_MGR_SGLE_READ|RW_MGR_ZQCL|RW_MGR_TRUE_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_ADDRESS_MIRRORING|RW_MGR_MEM_DATA_MASK_WIDTH|RW_MGR_MEM_DATA_WIDTH|RW_MGR_MEM_DQ_PER_READ_DQS|RW_MGR_MEM_DQ_PER_WRITE_DQS|RW_MGR_MEM_IF_READ_DQS_WIDTH|RW_MGR_MEM_IF_WRITE_DQS_WIDTH|RW_MGR_MEM_NUMBER_OF_CS_PER_DIMM|RW_MGR_MEM_NUMBER_OF_RANKS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_READ_DQS|RW_MGR_MEM_VIRTUAL_GROUPS_PER_WRITE_DQS|IO_DELAY_PER_DCHAIN_TAP|IO_DELAY_PER_DQS_EN_DCHAIN_TAP|IO_DELAY_PER_OPA_TAP|IO_DLL_CHAIN_LENGTH|IO_DQDQS_OUT_PHASE_MAX|IO_DQS_EN_DELAY_MAX|IO_DQS_EN_DELAY_OFFSET|IO_DQS_EN_PHASE_MAX|IO_DQS_IN_DELAY_MAX|IO_DQS_IN_RESERVE|IO_DQS_OUT_RESERVE|IO_IO_IN_DELAY_MAX|IO_IO_OUT1_DELAY_MAX|IO_IO_OUT2_DELAY_MAX|IO_SHIFT_DQS_EN_WHEN_SHIFT_DQS|AFI_RATE_RATIO|AFI_CLK_FREQ|CALIB_LFIFO_OFFSET|CALIB_VFIFO_OFFSET|ENABLE_SUPER_QUICK_CALIBRATION|MAX_LATENCY_COUNT_WIDTH|READ_VALID_FIFO_SIZE|REG_FILE_INIT_SEQ_SIGNATURE|TINIT_CNTR0_VAL|TINIT_CNTR1_VAL|TINIT_CNTR2_VAL|TRESET_CNTR0_VAL|TRESET_CNTR1_VAL|TRESET_CNTR2_VAL|CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR|CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC|CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP)[[:space:]]" }
# diff --git a/arch/arm/mach-socfpga/wrap_iocsr_config.c b/arch/arm/mach-socfpga/wrap_iocsr_config.c index f810fade92a9..ce86f04cad1f 100644 --- a/arch/arm/mach-socfpga/wrap_iocsr_config.c +++ b/arch/arm/mach-socfpga/wrap_iocsr_config.c @@ -17,19 +17,19 @@ int iocsr_get_config_table(const unsigned int chain_id, switch (chain_id) { case 0: *table = iocsr_scan_chain0_table; - *table_len = CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH; + *table_len = CFG_HPS_IOCSR_SCANCHAIN0_LENGTH; break; case 1: *table = iocsr_scan_chain1_table; - *table_len = CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH; + *table_len = CFG_HPS_IOCSR_SCANCHAIN1_LENGTH; break; case 2: *table = iocsr_scan_chain2_table; - *table_len = CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH; + *table_len = CFG_HPS_IOCSR_SCANCHAIN2_LENGTH; break; case 3: *table = iocsr_scan_chain3_table; - *table_len = CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH; + *table_len = CFG_HPS_IOCSR_SCANCHAIN3_LENGTH; break; default: return -EINVAL; diff --git a/arch/arm/mach-socfpga/wrap_pll_config.c b/arch/arm/mach-socfpga/wrap_pll_config.c index bd631e0fb5fb..0c40ae987613 100644 --- a/arch/arm/mach-socfpga/wrap_pll_config.c +++ b/arch/arm/mach-socfpga/wrap_pll_config.c @@ -8,116 +8,116 @@ #include <qts/pll_config.h>
#define MAIN_VCO_BASE ( \ - (CONFIG_HPS_MAINPLLGRP_VCO_DENOM << \ + (CFG_HPS_MAINPLLGRP_VCO_DENOM << \ CLKMGR_MAINPLLGRP_VCO_DENOM_OFFSET) | \ - (CONFIG_HPS_MAINPLLGRP_VCO_NUMER << \ + (CFG_HPS_MAINPLLGRP_VCO_NUMER << \ CLKMGR_MAINPLLGRP_VCO_NUMER_OFFSET) \ )
#define PERI_VCO_BASE ( \ - (CONFIG_HPS_PERPLLGRP_VCO_PSRC << \ + (CFG_HPS_PERPLLGRP_VCO_PSRC << \ CLKMGR_PERPLLGRP_VCO_PSRC_OFFSET) | \ - (CONFIG_HPS_PERPLLGRP_VCO_DENOM << \ + (CFG_HPS_PERPLLGRP_VCO_DENOM << \ CLKMGR_PERPLLGRP_VCO_DENOM_OFFSET) | \ - (CONFIG_HPS_PERPLLGRP_VCO_NUMER << \ + (CFG_HPS_PERPLLGRP_VCO_NUMER << \ CLKMGR_PERPLLGRP_VCO_NUMER_OFFSET) \ )
#define SDR_VCO_BASE ( \ - (CONFIG_HPS_SDRPLLGRP_VCO_SSRC << \ + (CFG_HPS_SDRPLLGRP_VCO_SSRC << \ CLKMGR_SDRPLLGRP_VCO_SSRC_OFFSET) | \ - (CONFIG_HPS_SDRPLLGRP_VCO_DENOM << \ + (CFG_HPS_SDRPLLGRP_VCO_DENOM << \ CLKMGR_SDRPLLGRP_VCO_DENOM_OFFSET) | \ - (CONFIG_HPS_SDRPLLGRP_VCO_NUMER << \ + (CFG_HPS_SDRPLLGRP_VCO_NUMER << \ CLKMGR_SDRPLLGRP_VCO_NUMER_OFFSET) \ )
static const struct cm_config cm_default_cfg = { /* main group */ MAIN_VCO_BASE, - (CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT << + (CFG_HPS_MAINPLLGRP_MPUCLK_CNT << CLKMGR_MAINPLLGRP_MPUCLK_CNT_OFFSET), - (CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT << + (CFG_HPS_MAINPLLGRP_MAINCLK_CNT << CLKMGR_MAINPLLGRP_MAINCLK_CNT_OFFSET), - (CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT << + (CFG_HPS_MAINPLLGRP_DBGATCLK_CNT << CLKMGR_MAINPLLGRP_DBGATCLK_CNT_OFFSET), - (CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT << + (CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT << CLKMGR_MAINPLLGRP_MAINQSPICLK_CNT_OFFSET), - (CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT << + (CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT << CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET), - (CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT << + (CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT << CLKMGR_MAINPLLGRP_CFGS2FUSER0CLK_CNT_OFFSET), - (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK << + (CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK << CLKMGR_MAINPLLGRP_MAINDIV_L3MPCLK_OFFSET) | - (CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK << + (CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK << CLKMGR_MAINPLLGRP_MAINDIV_L3SPCLK_OFFSET) | - (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK << + (CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK << CLKMGR_MAINPLLGRP_MAINDIV_L4MPCLK_OFFSET) | - (CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK << + (CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK << CLKMGR_MAINPLLGRP_MAINDIV_L4SPCLK_OFFSET), - (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK << + (CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK << CLKMGR_MAINPLLGRP_DBGDIV_DBGATCLK_OFFSET) | - (CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK << + (CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK << CLKMGR_MAINPLLGRP_DBGDIV_DBGCLK_OFFSET), - (CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK << + (CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK << CLKMGR_MAINPLLGRP_TRACEDIV_TRACECLK_OFFSET), - (CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP << + (CFG_HPS_MAINPLLGRP_L4SRC_L4MP << CLKMGR_MAINPLLGRP_L4SRC_L4MP_OFFSET) | - (CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP << + (CFG_HPS_MAINPLLGRP_L4SRC_L4SP << CLKMGR_MAINPLLGRP_L4SRC_L4SP_OFFSET),
/* peripheral group */ PERI_VCO_BASE, - (CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT << + (CFG_HPS_PERPLLGRP_EMAC0CLK_CNT << CLKMGR_PERPLLGRP_EMAC0CLK_CNT_OFFSET), - (CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT << + (CFG_HPS_PERPLLGRP_EMAC1CLK_CNT << CLKMGR_PERPLLGRP_EMAC1CLK_CNT_OFFSET), - (CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT << + (CFG_HPS_PERPLLGRP_PERQSPICLK_CNT << CLKMGR_PERPLLGRP_PERQSPICLK_CNT_OFFSET), - (CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT << + (CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT << CLKMGR_PERPLLGRP_PERNANDSDMMCCLK_CNT_OFFSET), - (CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT << + (CFG_HPS_PERPLLGRP_PERBASECLK_CNT << CLKMGR_PERPLLGRP_PERBASECLK_CNT_OFFSET), - (CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT << + (CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT << CLKMGR_PERPLLGRP_S2FUSER1CLK_CNT_OFFSET), - (CONFIG_HPS_PERPLLGRP_DIV_USBCLK << + (CFG_HPS_PERPLLGRP_DIV_USBCLK << CLKMGR_PERPLLGRP_DIV_USBCLK_OFFSET) | - (CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK << + (CFG_HPS_PERPLLGRP_DIV_SPIMCLK << CLKMGR_PERPLLGRP_DIV_SPIMCLK_OFFSET) | - (CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK << + (CFG_HPS_PERPLLGRP_DIV_CAN0CLK << CLKMGR_PERPLLGRP_DIV_CAN0CLK_OFFSET) | - (CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK << + (CFG_HPS_PERPLLGRP_DIV_CAN1CLK << CLKMGR_PERPLLGRP_DIV_CAN1CLK_OFFSET), - (CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK << + (CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK << CLKMGR_PERPLLGRP_GPIODIV_GPIODBCLK_OFFSET), - (CONFIG_HPS_PERPLLGRP_SRC_QSPI << + (CFG_HPS_PERPLLGRP_SRC_QSPI << CLKMGR_PERPLLGRP_SRC_QSPI_OFFSET) | - (CONFIG_HPS_PERPLLGRP_SRC_NAND << + (CFG_HPS_PERPLLGRP_SRC_NAND << CLKMGR_PERPLLGRP_SRC_NAND_OFFSET) | - (CONFIG_HPS_PERPLLGRP_SRC_SDMMC << + (CFG_HPS_PERPLLGRP_SRC_SDMMC << CLKMGR_PERPLLGRP_SRC_SDMMC_OFFSET),
/* sdram pll group */ SDR_VCO_BASE, - (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE << + (CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE << CLKMGR_SDRPLLGRP_DDRDQSCLK_PHASE_OFFSET) | - (CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT << + (CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT << CLKMGR_SDRPLLGRP_DDRDQSCLK_CNT_OFFSET), - (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE << + (CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE << CLKMGR_SDRPLLGRP_DDR2XDQSCLK_PHASE_OFFSET) | - (CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT << + (CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT << CLKMGR_SDRPLLGRP_DDR2XDQSCLK_CNT_OFFSET), - (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE << + (CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE << CLKMGR_SDRPLLGRP_DDRDQCLK_PHASE_OFFSET) | - (CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT << + (CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT << CLKMGR_SDRPLLGRP_DDRDQCLK_CNT_OFFSET), - (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE << + (CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE << CLKMGR_SDRPLLGRP_S2FUSER2CLK_PHASE_OFFSET) | - (CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT << + (CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT << CLKMGR_SDRPLLGRP_S2FUSER2CLK_CNT_OFFSET),
/* altera group */ - CONFIG_HPS_ALTERAGRP_MPUCLK, + CFG_HPS_ALTERAGRP_MPUCLK, };
const struct cm_config * const cm_get_default_config(void) @@ -128,19 +128,19 @@ const struct cm_config * const cm_get_default_config(void) const unsigned int cm_get_osc_clk_hz(const int osc) { if (osc == 1) - return CONFIG_HPS_CLK_OSC1_HZ; + return CFG_HPS_CLK_OSC1_HZ; else if (osc == 2) - return CONFIG_HPS_CLK_OSC2_HZ; + return CFG_HPS_CLK_OSC2_HZ; else return 0; }
const unsigned int cm_get_f2s_per_ref_clk_hz(void) { - return CONFIG_HPS_CLK_F2S_PER_REF_HZ; + return CFG_HPS_CLK_F2S_PER_REF_HZ; }
const unsigned int cm_get_f2s_sdr_ref_clk_hz(void) { - return CONFIG_HPS_CLK_F2S_SDR_REF_HZ; + return CFG_HPS_CLK_F2S_SDR_REF_HZ; } diff --git a/arch/arm/mach-socfpga/wrap_sdram_config.c b/arch/arm/mach-socfpga/wrap_sdram_config.c index 4ea32e72c7c9..cd3a0f663355 100644 --- a/arch/arm/mach-socfpga/wrap_sdram_config.c +++ b/arch/arm/mach-socfpga/wrap_sdram_config.c @@ -12,180 +12,180 @@
static const struct socfpga_sdram_config sdram_config = { .ctrl_cfg = - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE << + (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE << SDR_CTRLGRP_CTRLCFG_MEMTYPE_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL << + (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL << SDR_CTRLGRP_CTRLCFG_MEMBL_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER << + (CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER << SDR_CTRLGRP_CTRLCFG_ADDRORDER_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN << + (CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN << SDR_CTRLGRP_CTRLCFG_ECCEN_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN << + (CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN << SDR_CTRLGRP_CTRLCFG_ECCCORREN_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN << + (CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN << SDR_CTRLGRP_CTRLCFG_REORDEREN_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT << + (CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT << SDR_CTRLGRP_CTRLCFG_STARVELIMIT_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN << + (CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN << SDR_CTRLGRP_CTRLCFG_DQSTRKEN_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS << + (CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS << SDR_CTRLGRP_CTRLCFG_NODMPINS_LSB), .dram_timing1 = - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL << + (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL << SDR_CTRLGRP_DRAMTIMING1_TCWL_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL << + (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL << SDR_CTRLGRP_DRAMTIMING1_TAL_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL << + (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL << SDR_CTRLGRP_DRAMTIMING1_TCL_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD << + (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD << SDR_CTRLGRP_DRAMTIMING1_TRRD_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW << + (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW << SDR_CTRLGRP_DRAMTIMING1_TFAW_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC << + (CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC << SDR_CTRLGRP_DRAMTIMING1_TRFC_LSB), .dram_timing2 = - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI << + (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI << SDR_CTRLGRP_DRAMTIMING2_TREFI_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD << + (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD << SDR_CTRLGRP_DRAMTIMING2_TRCD_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP << + (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP << SDR_CTRLGRP_DRAMTIMING2_TRP_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR << + (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR << SDR_CTRLGRP_DRAMTIMING2_TWR_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR << + (CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR << SDR_CTRLGRP_DRAMTIMING2_TWTR_LSB), .dram_timing3 = - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP << + (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP << SDR_CTRLGRP_DRAMTIMING3_TRTP_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS << + (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS << SDR_CTRLGRP_DRAMTIMING3_TRAS_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC << + (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC << SDR_CTRLGRP_DRAMTIMING3_TRC_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD << + (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD << SDR_CTRLGRP_DRAMTIMING3_TMRD_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD << + (CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD << SDR_CTRLGRP_DRAMTIMING3_TCCD_LSB), .dram_timing4 = - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT << + (CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT << SDR_CTRLGRP_DRAMTIMING4_SELFRFSHEXIT_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT << + (CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT << SDR_CTRLGRP_DRAMTIMING4_PWRDOWNEXIT_LSB), .lowpwr_timing = - (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES << + (CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES << SDR_CTRLGRP_LOWPWRTIMING_AUTOPDCYCLES_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES << + (CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES << SDR_CTRLGRP_LOWPWRTIMING_CLKDISABLECYCLES_LSB), .dram_odt = - (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ << + (CFG_HPS_SDR_CTRLCFG_DRAMODT_READ << SDR_CTRLGRP_DRAMODT_READ_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE << + (CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE << SDR_CTRLGRP_DRAMODT_WRITE_LSB), -#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */ +#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */ .extratime1 = - (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR << + (CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR << SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC << + (CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC << SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_BC_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP << + (CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP << SDR_CTRLGRP_EXTRATIME1_RD_TO_WR_DIFF_LSB), #endif .dram_addrw = - (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS << + (CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS << SDR_CTRLGRP_DRAMADDRW_COLBITS_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS << + (CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS << SDR_CTRLGRP_DRAMADDRW_ROWBITS_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS << + (CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS << SDR_CTRLGRP_DRAMADDRW_BANKBITS_LSB) | - ((CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) << + ((CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS - 1) << SDR_CTRLGRP_DRAMADDRW_CSBITS_LSB), .dram_if_width = - (CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH << + (CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH << SDR_CTRLGRP_DRAMIFWIDTH_IFWIDTH_LSB), .dram_dev_width = - (CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH << + (CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH << SDR_CTRLGRP_DRAMDEVWIDTH_DEVWIDTH_LSB), .dram_intr = - (CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN << + (CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN << SDR_CTRLGRP_DRAMINTR_INTREN_LSB), .lowpwr_eq = - (CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK << + (CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK << SDR_CTRLGRP_LOWPWREQ_SELFRFSHMASK_LSB), .static_cfg = - (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL << + (CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL << SDR_CTRLGRP_STATICCFG_MEMBL_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA << + (CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA << SDR_CTRLGRP_STATICCFG_USEECCASDATA_LSB), .ctrl_width = - (CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH << + (CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH << SDR_CTRLGRP_CTRLWIDTH_CTRLWIDTH_LSB), .cport_width = - (CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH << + (CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH << SDR_CTRLGRP_CPORTWIDTH_CMDPORTWIDTH_LSB), .cport_wmap = - (CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP << + (CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP << SDR_CTRLGRP_CPORTWMAP_CPORTWFIFOMAP_LSB), .cport_rmap = - (CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP << + (CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP << SDR_CTRLGRP_CPORTRMAP_CPORTRFIFOMAP_LSB), .rfifo_cmap = - (CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP << + (CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP << SDR_CTRLGRP_RFIFOCMAP_RFIFOCPORTMAP_LSB), .wfifo_cmap = - (CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP << + (CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP << SDR_CTRLGRP_WFIFOCMAP_WFIFOCPORTMAP_LSB), .cport_rdwr = - (CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR << + (CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR << SDR_CTRLGRP_CPORTRDWR_CPORTRDWR_LSB), .port_cfg = - (CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN << + (CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN << SDR_CTRLGRP_PORTCFG_AUTOPCHEN_LSB), - .fpgaport_rst = CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST, + .fpgaport_rst = CFG_HPS_SDR_CTRLCFG_FPGAPORTRST, .fifo_cfg = - (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE << + (CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE << SDR_CTRLGRP_FIFOCFG_SYNCMODE_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC << + (CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC << SDR_CTRLGRP_FIFOCFG_INCSYNC_LSB), .mp_priority = - (CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY << + (CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY << SDR_CTRLGRP_MPPRIORITY_USERPRIORITY_LSB), .mp_weight0 = - (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 << + (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_0_STATICWEIGHT_31_0_LSB), .mp_weight1 = - (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 << + (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_STATICWEIGHT_49_32_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 << + (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_1_SUMOFWEIGHTS_13_0_LSB), .mp_weight2 = - (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 << + (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_2_SUMOFWEIGHTS_45_14_LSB), .mp_weight3 = - (CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 << + (CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 << SDR_CTRLGRP_MPWEIGHT_MPWEIGHT_3_SUMOFWEIGHTS_63_46_LSB), .mp_pacing0 = - (CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 << + (CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 << SDR_CTRLGRP_MPPACING_MPPACING_0_THRESHOLD1_31_0_LSB), .mp_pacing1 = - (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 << + (CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 << SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD1_59_32_LSB) | - (CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 << + (CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 << SDR_CTRLGRP_MPPACING_MPPACING_1_THRESHOLD2_3_0_LSB), .mp_pacing2 = - (CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 << + (CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 << SDR_CTRLGRP_MPPACING_MPPACING_2_THRESHOLD2_35_4_LSB), .mp_pacing3 = - (CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 << + (CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 << SDR_CTRLGRP_MPPACING_MPPACING_3_THRESHOLD2_59_36_LSB), .mp_threshold0 = - (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 << + (CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 << SDR_CTRLGRP_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0_LSB), .mp_threshold1 = - (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 << + (CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 << SDR_CTRLGRP_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32_LSB), .mp_threshold2 = - (CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 << + (CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 << SDR_CTRLGRP_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64_LSB), - .phy_ctrl0 = CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0, + .phy_ctrl0 = CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0, };
static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = { @@ -202,7 +202,7 @@ static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = { .guaranteed_write_wait3 = RW_MGR_GUARANTEED_WRITE_WAIT3, .idle_loop1 = RW_MGR_IDLE_LOOP1, .idle_loop2 = RW_MGR_IDLE_LOOP2, -#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */ +#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */ .emr = RW_MGR_EMR, .emr2 = RW_MGR_EMR2, .emr3 = RW_MGR_EMR3, @@ -213,7 +213,7 @@ static const struct socfpga_sdram_rw_mgr_config rw_mgr_config = { .mr_user = RW_MGR_MR_USER, .mr_dll_reset = RW_MGR_MR_DLL_RESET, .emr_ocd_enable = RW_MGR_EMR_OCD_ENABLE, -#elif (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */ +#elif (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 2) /* DDR3 */ .activate_1 = RW_MGR_ACTIVATE_1, .idle = RW_MGR_IDLE, .init_reset_0_cke_0 = RW_MGR_INIT_RESET_0_CKE_0, @@ -287,7 +287,7 @@ static const struct socfpga_sdram_io_config io_config = { };
static const struct socfpga_sdram_misc_config misc_config = { -#if (CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */ +#if (CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE == 1) /* DDR2 */ .afi_clk_freq = AFI_CLK_FREQ, #endif .afi_rate_ratio = AFI_RATE_RATIO, diff --git a/board/altera/arria5-socdk/qts/iocsr_config.h b/board/altera/arria5-socdk/qts/iocsr_config.h index 69a92de6361b..f201ad345877 100644 --- a/board/altera/arria5-socdk/qts/iocsr_config.h +++ b/board/altera/arria5-socdk/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/altera/arria5-socdk/qts/pll_config.h b/board/altera/arria5-socdk/qts/pll_config.h index 6c8325434440..7fe290b28d96 100644 --- a/board/altera/arria5-socdk/qts/pll_config.h +++ b/board/altera/arria5-socdk/qts/pll_config.h @@ -6,79 +6,79 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 41 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 2 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 8 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 41 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 2 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 8 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 1 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 1 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 9 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 1 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 79 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 1 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 9 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 1 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 1 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 127 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 2 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 127 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1050000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 1066000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 350000000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 100000000 -#define CONFIG_HPS_CLK_CAN1_HZ 100000000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1050000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 1066000000 +#define CFG_HPS_CLK_EMAC0_HZ 250000000 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 350000000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 100000000 +#define CFG_HPS_CLK_CAN1_HZ 100000000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 0 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 2 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 +#define CFG_HPS_ALTERAGRP_MPUCLK 0 +#define CFG_HPS_ALTERAGRP_MAINCLK 2 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/altera/arria5-socdk/qts/sdram_config.h b/board/altera/arria5-socdk/qts/sdram_config.h index 927a7a4f8e04..1d032e1af4bd 100644 --- a/board/altera/arria5-socdk/qts/sdram_config.h +++ b/board/altera/arria5-socdk/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 19 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 139 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 4160 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 19 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 26 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/altera/cyclone5-socdk/qts/iocsr_config.h b/board/altera/cyclone5-socdk/qts/iocsr_config.h index 81c507b842bc..a571fb3e509b 100644 --- a/board/altera/cyclone5-socdk/qts/iocsr_config.h +++ b/board/altera/cyclone5-socdk/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h index ae5cfab0cf70..a46d124e9e99 100644 --- a/board/altera/cyclone5-socdk/qts/pll_config.h +++ b/board/altera/cyclone5-socdk/qts/pll_config.h @@ -6,79 +6,79 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 73 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 1 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 370000000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 100000000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1850000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 370000000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 100000000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 4 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 4 +#define CFG_HPS_ALTERAGRP_DBGATCLK 4
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/altera/cyclone5-socdk/qts/sdram_config.h b/board/altera/cyclone5-socdk/qts/sdram_config.h index 8adbfec11f95..e3a8cfbfb38c 100644 --- a/board/altera/cyclone5-socdk/qts/sdram_config.h +++ b/board/altera/cyclone5-socdk/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 40 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/aries/mcvevk/qts/iocsr_config.h b/board/aries/mcvevk/qts/iocsr_config.h index e233d02b97db..dbcc1d719d41 100644 --- a/board/aries/mcvevk/qts/iocsr_config.h +++ b/board/aries/mcvevk/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/aries/mcvevk/qts/pll_config.h b/board/aries/mcvevk/qts/pll_config.h index 4fa868e458f0..62cf6796afc9 100644 --- a/board/aries/mcvevk/qts/pll_config.h +++ b/board/aries/mcvevk/qts/pll_config.h @@ -6,79 +6,79 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 1 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 1 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 -#define CONFIG_HPS_CLK_EMAC1_HZ 1953125 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 3125000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 100000000 -#define CONFIG_HPS_CLK_CAN1_HZ 100000000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_EMAC0_HZ 250000000 +#define CFG_HPS_CLK_EMAC1_HZ 1953125 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 3125000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 100000000 +#define CFG_HPS_CLK_CAN1_HZ 100000000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 3 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/aries/mcvevk/qts/sdram_config.h b/board/aries/mcvevk/qts/sdram_config.h index fd72926a89e3..c6a24f5632a6 100644 --- a/board/aries/mcvevk/qts/sdram_config.h +++ b/board/aries/mcvevk/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/devboards/dbm-soc1/qts/iocsr_config.h b/board/devboards/dbm-soc1/qts/iocsr_config.h index 99ed62bb503e..56b2130671a3 100644 --- a/board/devboards/dbm-soc1/qts/iocsr_config.h +++ b/board/devboards/dbm-soc1/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/devboards/dbm-soc1/qts/pll_config.h b/board/devboards/dbm-soc1/qts/pll_config.h index f6ffa08654ad..104e324d8a4f 100644 --- a/board/devboards/dbm-soc1/qts/pll_config.h +++ b/board/devboards/dbm-soc1/qts/pll_config.h @@ -6,79 +6,79 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 400000000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 12500000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 400000000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 3 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/devboards/dbm-soc1/qts/sdram_config.h b/board/devboards/dbm-soc1/qts/sdram_config.h index 2022969bed9b..2c4559b1aad8 100644 --- a/board/devboards/dbm-soc1/qts/sdram_config.h +++ b/board/devboards/dbm-soc1/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/ebv/socrates/qts/iocsr_config.h b/board/ebv/socrates/qts/iocsr_config.h index 18b9c6ce4dfc..c24b5cb5f0b2 100644 --- a/board/ebv/socrates/qts/iocsr_config.h +++ b/board/ebv/socrates/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/ebv/socrates/qts/pll_config.h b/board/ebv/socrates/qts/pll_config.h index 71d3674758fc..eaa18c1c802c 100644 --- a/board/ebv/socrates/qts/pll_config.h +++ b/board/ebv/socrates/qts/pll_config.h @@ -6,79 +6,79 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 1 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 2 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 79 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666 -#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 400000000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 100000000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 666666666 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 400000000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 100000000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 3 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/ebv/socrates/qts/sdram_config.h b/board/ebv/socrates/qts/sdram_config.h index 2f8465bf77ca..318ef0cd1dd5 100644 --- a/board/ebv/socrates/qts/sdram_config.h +++ b/board/ebv/socrates/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 117 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1300 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 12 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 117 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1300 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 12 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/is1/qts/iocsr_config.h b/board/is1/qts/iocsr_config.h index 1d2774aa41a7..e54af2caed49 100644 --- a/board/is1/qts/iocsr_config.h +++ b/board/is1/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/is1/qts/pll_config.h b/board/is1/qts/pll_config.h index 218ab35c0424..0a5f5dd196fb 100644 --- a/board/is1/qts/pll_config.h +++ b/board/is1/qts/pll_config.h @@ -6,79 +6,79 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 59 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 59 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 39 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 39 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1500000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 488281 -#define CONFIG_HPS_CLK_SDMMC_HZ 1953125 -#define CONFIG_HPS_CLK_QSPI_HZ 375000000 -#define CONFIG_HPS_CLK_SPIM_HZ 12500000 -#define CONFIG_HPS_CLK_CAN0_HZ 12500000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1500000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_EMAC0_HZ 250000000 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 488281 +#define CFG_HPS_CLK_SDMMC_HZ 1953125 +#define CFG_HPS_CLK_QSPI_HZ 375000000 +#define CFG_HPS_CLK_SPIM_HZ 12500000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 4 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 4 +#define CFG_HPS_ALTERAGRP_DBGATCLK 4
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/is1/qts/sdram_config.h b/board/is1/qts/sdram_config.h index 2573171abeb1..d8521a7e0248 100644 --- a/board/is1/qts/sdram_config.h +++ b/board/is1/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 16 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 64 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x777 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 16 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 64 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x777 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/keymile/secu1/qts/iocsr_config.h b/board/keymile/secu1/qts/iocsr_config.h index 7640c56db166..9f05fce8b30b 100644 --- a/board/keymile/secu1/qts/iocsr_config.h +++ b/board/keymile/secu1/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 1337 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 1528 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = { 0x00100000, diff --git a/board/keymile/secu1/qts/pll_config.h b/board/keymile/secu1/qts/pll_config.h index f0c31860ca4b..7bc704a1820d 100644 --- a/board/keymile/secu1/qts/pll_config.h +++ b/board/keymile/secu1/qts/pll_config.h @@ -6,78 +6,78 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 39 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 24 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 7 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 1 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 24 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 7 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 4 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 1 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 14 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 14 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 40000000 -#define CONFIG_HPS_CLK_OSC2_HZ 40000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 600000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 -#define CONFIG_HPS_CLK_EMAC1_HZ 1953125 -#define CONFIG_HPS_CLK_USBCLK_HZ 12500000 -#define CONFIG_HPS_CLK_NAND_HZ 31250000 -#define CONFIG_HPS_CLK_SDMMC_HZ 3125000 -#define CONFIG_HPS_CLK_QSPI_HZ 3125000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 12500000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 40000000 +#define CFG_HPS_CLK_OSC2_HZ 40000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 600000000 +#define CFG_HPS_CLK_EMAC0_HZ 250000000 +#define CFG_HPS_CLK_EMAC1_HZ 1953125 +#define CFG_HPS_CLK_USBCLK_HZ 12500000 +#define CFG_HPS_CLK_NAND_HZ 31250000 +#define CFG_HPS_CLK_SDMMC_HZ 3125000 +#define CFG_HPS_CLK_QSPI_HZ 3125000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 3 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/keymile/secu1/qts/sdram_config.h b/board/keymile/secu1/qts/sdram_config.h index b0ff86ef3814..a0ce0b26ca91 100644 --- a/board/keymile/secu1/qts/sdram_config.h +++ b/board/keymile/secu1/qts/sdram_config.h @@ -8,76 +8,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 60 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 2341 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 13 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 3 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 3 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 3 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 60 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 2341 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 13 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 17 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 3 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 3 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 3 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x11 diff --git a/board/softing/vining_fpga/qts/iocsr_config.h b/board/softing/vining_fpga/qts/iocsr_config.h index 8c78aecdd3de..4059ed5ad12a 100644 --- a/board/softing/vining_fpga/qts/iocsr_config.h +++ b/board/softing/vining_fpga/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/softing/vining_fpga/qts/pll_config.h b/board/softing/vining_fpga/qts/pll_config.h index fa0461833694..40bc8f7f7c12 100644 --- a/board/softing/vining_fpga/qts/pll_config.h +++ b/board/softing/vining_fpga/qts/pll_config.h @@ -6,79 +6,79 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 488281 -#define CONFIG_HPS_CLK_SDMMC_HZ 1953125 -#define CONFIG_HPS_CLK_QSPI_HZ 320000000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 12500000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_EMAC0_HZ 250000000 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 488281 +#define CFG_HPS_CLK_SDMMC_HZ 1953125 +#define CFG_HPS_CLK_QSPI_HZ 320000000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 3 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/softing/vining_fpga/qts/sdram_config.h b/board/softing/vining_fpga/qts/sdram_config.h index ec067eb473d1..27e3f3b2a570 100644 --- a/board/softing/vining_fpga/qts/sdram_config.h +++ b/board/softing/vining_fpga/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/sr1500/qts/iocsr_config.h b/board/sr1500/qts/iocsr_config.h index b3b167fa7fc0..2622b960314d 100644 --- a/board/sr1500/qts/iocsr_config.h +++ b/board/sr1500/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = { 0x00100000, diff --git a/board/sr1500/qts/pll_config.h b/board/sr1500/qts/pll_config.h index 02f068f74244..885fe91eebab 100644 --- a/board/sr1500/qts/pll_config.h +++ b/board/sr1500/qts/pll_config.h @@ -6,79 +6,79 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 400000000 -#define CONFIG_HPS_CLK_SPIM_HZ 12500000 -#define CONFIG_HPS_CLK_CAN0_HZ 12500000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 400000000 +#define CFG_HPS_CLK_SPIM_HZ 12500000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 3 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/sr1500/qts/sdram_config.h b/board/sr1500/qts/sdram_config.h index d25354bb49cd..3438221d6863 100644 --- a/board/sr1500/qts/sdram_config.h +++ b/board/sr1500/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x330 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 16 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 140 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 1560 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 5 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x330 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/terasic/de0-nano-soc/qts/iocsr_config.h b/board/terasic/de0-nano-soc/qts/iocsr_config.h index 6ff5bd57112a..b856474b7706 100644 --- a/board/terasic/de0-nano-soc/qts/iocsr_config.h +++ b/board/terasic/de0-nano-soc/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/terasic/de0-nano-soc/qts/pll_config.h b/board/terasic/de0-nano-soc/qts/pll_config.h index e439336d45ab..36d8fd1df2c1 100644 --- a/board/terasic/de0-nano-soc/qts/pll_config.h +++ b/board/terasic/de0-nano-soc/qts/pll_config.h @@ -6,78 +6,78 @@ #ifndef _PRELOADER_PLL_CONFIG_H_ #define _PRELOADER_PLL_CONFIG_H_
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 73 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 3613281 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 12500000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1850000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 3613281 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 4 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 4 +#define CFG_HPS_ALTERAGRP_DBGATCLK 4
#endif /* _PRELOADER_PLL_CONFIG_H_ */ diff --git a/board/terasic/de0-nano-soc/qts/sdram_config.h b/board/terasic/de0-nano-soc/qts/sdram_config.h index 0504dd688f9b..3fb2f2a58b4d 100644 --- a/board/terasic/de0-nano-soc/qts/sdram_config.h +++ b/board/terasic/de0-nano-soc/qts/sdram_config.h @@ -5,80 +5,80 @@ #ifndef __SDRAM_CONFIG_H #define __SDRAM_CONFIG_H
-#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200
-#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED 0x1 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED 0x1 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED 0x3 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x311 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST_READ_PORT_USED 0x1 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST_WRITE_PORT_USED 0x1 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST_COMMAND_PORT_USED 0x3 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x311
/* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/terasic/de1-soc/qts/iocsr_config.h b/board/terasic/de1-soc/qts/iocsr_config.h index c65183ed8c08..359fd0e4173b 100644 --- a/board/terasic/de1-soc/qts/iocsr_config.h +++ b/board/terasic/de1-soc/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/terasic/de1-soc/qts/pll_config.h b/board/terasic/de1-soc/qts/pll_config.h index 4544f926935a..2811e04c4807 100644 --- a/board/terasic/de1-soc/qts/pll_config.h +++ b/board/terasic/de1-soc/qts/pll_config.h @@ -6,85 +6,85 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 400000000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 12500000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 400000000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 3 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/terasic/de1-soc/qts/sdram_config.h b/board/terasic/de1-soc/qts/sdram_config.h index c60426f2ff66..7b0ff2ce01bc 100644 --- a/board/terasic/de1-soc/qts/sdram_config.h +++ b/board/terasic/de1-soc/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 18 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 18 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 200 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/terasic/de10-nano/qts/iocsr_config.h b/board/terasic/de10-nano/qts/iocsr_config.h index bc5b7a07c7d6..a889d3da3485 100644 --- a/board/terasic/de10-nano/qts/iocsr_config.h +++ b/board/terasic/de10-nano/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/terasic/de10-nano/qts/pll_config.h b/board/terasic/de10-nano/qts/pll_config.h index 854936b2a33a..192ffb4e27b2 100644 --- a/board/terasic/de10-nano/qts/pll_config.h +++ b/board/terasic/de10-nano/qts/pll_config.h @@ -6,79 +6,79 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 19 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 3125000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 12500000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 3125000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 3 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/terasic/de10-nano/qts/sdram_config.h b/board/terasic/de10-nano/qts/sdram_config.h index 26910ef348b7..abf29f25c1a4 100644 --- a/board/terasic/de10-nano/qts/sdram_config.h +++ b/board/terasic/de10-nano/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 120 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x10441 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x78 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0x0 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/terasic/de10-standard/qts/iocsr_config.h b/board/terasic/de10-standard/qts/iocsr_config.h index c062b5521fd1..4aed74e8b298 100644 --- a/board/terasic/de10-standard/qts/iocsr_config.h +++ b/board/terasic/de10-standard/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/terasic/de10-standard/qts/pll_config.h b/board/terasic/de10-standard/qts/pll_config.h index b08a97791795..c1ecd4b8208f 100644 --- a/board/terasic/de10-standard/qts/pll_config.h +++ b/board/terasic/de10-standard/qts/pll_config.h @@ -6,79 +6,79 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 73 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 18 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 370000000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 12500000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1850000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 370000000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 4 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 4 +#define CFG_HPS_ALTERAGRP_DBGATCLK 4
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/terasic/de10-standard/qts/sdram_config.h b/board/terasic/de10-standard/qts/sdram_config.h index 630b5511a61c..1bfa4277282d 100644 --- a/board/terasic/de10-standard/qts/sdram_config.h +++ b/board/terasic/de10-standard/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 11 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 18 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 11 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 7 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 18 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 2 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 2 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 2 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D diff --git a/board/terasic/sockit/qts/iocsr_config.h b/board/terasic/sockit/qts/iocsr_config.h index b8cb5f08ab69..7b72ae9c3c2c 100644 --- a/board/terasic/sockit/qts/iocsr_config.h +++ b/board/terasic/sockit/qts/iocsr_config.h @@ -6,10 +6,10 @@ #ifndef __SOCFPGA_IOCSR_CONFIG_H__ #define __SOCFPGA_IOCSR_CONFIG_H__
-#define CONFIG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 -#define CONFIG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 -#define CONFIG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 -#define CONFIG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766 +#define CFG_HPS_IOCSR_SCANCHAIN0_LENGTH 764 +#define CFG_HPS_IOCSR_SCANCHAIN1_LENGTH 1719 +#define CFG_HPS_IOCSR_SCANCHAIN2_LENGTH 955 +#define CFG_HPS_IOCSR_SCANCHAIN3_LENGTH 16766
const unsigned long iocsr_scan_chain0_table[] = { 0x00000000, diff --git a/board/terasic/sockit/qts/pll_config.h b/board/terasic/sockit/qts/pll_config.h index f6ffa08654ad..104e324d8a4f 100644 --- a/board/terasic/sockit/qts/pll_config.h +++ b/board/terasic/sockit/qts/pll_config.h @@ -6,79 +6,79 @@ #ifndef __SOCFPGA_PLL_CONFIG_H__ #define __SOCFPGA_PLL_CONFIG_H__
-#define CONFIG_HPS_DBCTRL_STAYOSC1 1 +#define CFG_HPS_DBCTRL_STAYOSC1 1
-#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 -#define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 -#define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 -#define CONFIG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 -#define CONFIG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 -#define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1 +#define CFG_HPS_MAINPLLGRP_VCO_DENOM 0 +#define CFG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CFG_HPS_MAINPLLGRP_MPUCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 +#define CFG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 +#define CFG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 +#define CFG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 +#define CFG_HPS_MAINPLLGRP_MAINDIV_L4SPCLK 1 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGATCLK 0 +#define CFG_HPS_MAINPLLGRP_DBGDIV_DBGCLK 1 +#define CFG_HPS_MAINPLLGRP_TRACEDIV_TRACECLK 0 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4MP 1 +#define CFG_HPS_MAINPLLGRP_L4SRC_L4SP 1
-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 -#define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 -#define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 -#define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 -#define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 4 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 -#define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 -#define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 -#define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 -#define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1 +#define CFG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CFG_HPS_PERPLLGRP_VCO_NUMER 39 +#define CFG_HPS_PERPLLGRP_VCO_PSRC 0 +#define CFG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 +#define CFG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 +#define CFG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 +#define CFG_HPS_PERPLLGRP_PERBASECLK_CNT 4 +#define CFG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 +#define CFG_HPS_PERPLLGRP_DIV_USBCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_SPIMCLK 0 +#define CFG_HPS_PERPLLGRP_DIV_CAN0CLK 4 +#define CFG_HPS_PERPLLGRP_DIV_CAN1CLK 4 +#define CFG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 +#define CFG_HPS_PERPLLGRP_SRC_SDMMC 2 +#define CFG_HPS_PERPLLGRP_SRC_NAND 2 +#define CFG_HPS_PERPLLGRP_SRC_QSPI 1
-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 -#define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 -#define CONFIG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 -#define CONFIG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 -#define CONFIG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CFG_HPS_SDRPLLGRP_VCO_NUMER 31 +#define CFG_HPS_SDRPLLGRP_VCO_SSRC 0 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_CNT 0 +#define CFG_HPS_SDRPLLGRP_DDR2XDQSCLK_PHASE 0 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_CNT 1 +#define CFG_HPS_SDRPLLGRP_DDRDQCLK_PHASE 4 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_CNT 5 +#define CFG_HPS_SDRPLLGRP_S2FUSER2CLK_PHASE 0
-#define CONFIG_HPS_CLK_OSC1_HZ 25000000 -#define CONFIG_HPS_CLK_OSC2_HZ 25000000 -#define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 -#define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 -#define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 -#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 -#define CONFIG_HPS_CLK_EMAC1_HZ 250000000 -#define CONFIG_HPS_CLK_USBCLK_HZ 200000000 -#define CONFIG_HPS_CLK_NAND_HZ 50000000 -#define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 400000000 -#define CONFIG_HPS_CLK_SPIM_HZ 200000000 -#define CONFIG_HPS_CLK_CAN0_HZ 12500000 -#define CONFIG_HPS_CLK_CAN1_HZ 12500000 -#define CONFIG_HPS_CLK_GPIODB_HZ 32000 -#define CONFIG_HPS_CLK_L4_MP_HZ 100000000 -#define CONFIG_HPS_CLK_L4_SP_HZ 100000000 +#define CFG_HPS_CLK_OSC1_HZ 25000000 +#define CFG_HPS_CLK_OSC2_HZ 25000000 +#define CFG_HPS_CLK_F2S_SDR_REF_HZ 0 +#define CFG_HPS_CLK_F2S_PER_REF_HZ 0 +#define CFG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CFG_HPS_CLK_PERVCO_HZ 1000000000 +#define CFG_HPS_CLK_SDRVCO_HZ 800000000 +#define CFG_HPS_CLK_EMAC0_HZ 1953125 +#define CFG_HPS_CLK_EMAC1_HZ 250000000 +#define CFG_HPS_CLK_USBCLK_HZ 200000000 +#define CFG_HPS_CLK_NAND_HZ 50000000 +#define CFG_HPS_CLK_SDMMC_HZ 200000000 +#define CFG_HPS_CLK_QSPI_HZ 400000000 +#define CFG_HPS_CLK_SPIM_HZ 200000000 +#define CFG_HPS_CLK_CAN0_HZ 12500000 +#define CFG_HPS_CLK_CAN1_HZ 12500000 +#define CFG_HPS_CLK_GPIODB_HZ 32000 +#define CFG_HPS_CLK_L4_MP_HZ 100000000 +#define CFG_HPS_CLK_L4_SP_HZ 100000000
-#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 +#define CFG_HPS_ALTERAGRP_MPUCLK 1 +#define CFG_HPS_ALTERAGRP_MAINCLK 3 +#define CFG_HPS_ALTERAGRP_DBGATCLK 3
#endif /* __SOCFPGA_PLL_CONFIG_H__ */ diff --git a/board/terasic/sockit/qts/sdram_config.h b/board/terasic/sockit/qts/sdram_config.h index 96cc35703413..efdbc8557408 100644 --- a/board/terasic/sockit/qts/sdram_config.h +++ b/board/terasic/sockit/qts/sdram_config.h @@ -7,76 +7,76 @@ #define __SOCFPGA_SDRAM_CONFIG_H__
/* SDRAM configuration */ -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A -#define CONFIG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 -#define CONFIG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 -#define CONFIG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 11 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 8 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 -#define CONFIG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 -#define CONFIG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 -#define CONFIG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 -#define CONFIG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 -#define CONFIG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 -#define CONFIG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 -#define CONFIG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 -#define CONFIG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 -#define CONFIG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 -#define CONFIG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 -#define CONFIG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 -#define CONFIG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 -#define CONFIG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 -#define CONFIG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543 +#define CFG_HPS_SDR_CTRLCFG_CPORTRDWR_CPORTRDWR 0x5A56A +#define CFG_HPS_SDR_CTRLCFG_CPORTRMAP_CPORTRMAP 0xB00088 +#define CFG_HPS_SDR_CTRLCFG_CPORTWIDTH_CPORTWIDTH 0x44555 +#define CFG_HPS_SDR_CTRLCFG_CPORTWMAP_CPORTWMAP 0x2C011000 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ADDRORDER 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_DQSTRKEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCCORREN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_ECCEN 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMBL 8 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_MEMTYPE 2 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_NODMPINS 0 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_REORDEREN 1 +#define CFG_HPS_SDR_CTRLCFG_CTRLCFG_STARVELIMIT 10 +#define CFG_HPS_SDR_CTRLCFG_CTRLWIDTH_CTRLWIDTH 2 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_BANKBITS 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_COLBITS 10 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_CSBITS 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMADDRW_ROWBITS 15 +#define CFG_HPS_SDR_CTRLCFG_DRAMDEVWIDTH_DEVWIDTH 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMIFWIDTH_IFWIDTH 32 +#define CFG_HPS_SDR_CTRLCFG_DRAMINTR_INTREN 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_READ 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMODT_WRITE 1 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_AL 0 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCL 11 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TCWL 8 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TFAW 12 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRFC 104 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING1_TRRD 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRCD 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TREFI 3120 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TRP 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWR 6 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING2_IF_TWTR 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TCCD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TMRD 4 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRAS 14 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRC 20 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING3_TRTP 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_PWRDOWNEXIT 3 +#define CFG_HPS_SDR_CTRLCFG_DRAMTIMING4_SELFRFSHEXIT 512 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_BC 0 +#define CFG_HPS_SDR_CTRLCFG_EXTRATIME1_CFG_EXTRA_CTL_CLK_RD_TO_WR_DIFF_CHIP 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_INCSYNC 0 +#define CFG_HPS_SDR_CTRLCFG_FIFOCFG_SYNCMODE 0 +#define CFG_HPS_SDR_CTRLCFG_FPGAPORTRST 0x1FF +#define CFG_HPS_SDR_CTRLCFG_LOWPWREQ_SELFRFSHMASK 3 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_AUTOPDCYCLES 0 +#define CFG_HPS_SDR_CTRLCFG_LOWPWRTIMING_CLKDISABLECYCLES 8 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_0_THRESHOLD1_31_0 0x20820820 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD1_59_32 0x8208208 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_1_THRESHOLD2_3_0 0 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_2_THRESHOLD2_35_4 0x41041041 +#define CFG_HPS_SDR_CTRLCFG_MPPACING_3_THRESHOLD2_59_36 0x410410 +#define CFG_HPS_SDR_CTRLCFG_MPPRIORITY_USERPRIORITY 0x3FFD1088 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_0_THRESHOLDRSTCYCLES_31_0 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_1_THRESHOLDRSTCYCLES_63_32 0x01010101 +#define CFG_HPS_SDR_CTRLCFG_MPTHRESHOLDRST_2_THRESHOLDRSTCYCLES_79_64 0x0101 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_0_STATICWEIGHT_31_0 0x21084210 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_STATICWEIGHT_49_32 0x1EF84 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_1_SUMOFWEIGHT_13_0 0x2020 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_2_SUMOFWEIGHT_45_14 0x0 +#define CFG_HPS_SDR_CTRLCFG_MPWIEIGHT_3_SUMOFWEIGHT_63_46 0xF800 +#define CFG_HPS_SDR_CTRLCFG_PHYCTRL_PHYCTRL_0 0x200 +#define CFG_HPS_SDR_CTRLCFG_PORTCFG_AUTOPCHEN 0 +#define CFG_HPS_SDR_CTRLCFG_RFIFOCMAP_RFIFOCMAP 0x760210 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_MEMBL 2 +#define CFG_HPS_SDR_CTRLCFG_STATICCFG_USEECCASDATA 0 +#define CFG_HPS_SDR_CTRLCFG_WFIFOCMAP_WFIFOCMAP 0x980543
/* Sequencer auto configuration */ #define RW_MGR_ACTIVATE_0_AND_1 0x0D
On Fri, 28 Oct 2022 at 18:30, Tom Rini trini@konsulko.com wrote:
Migrate all of CONFIG_HPS* to the CFG namespace.
Signed-off-by: Tom Rini trini@konsulko.com
arch/arm/mach-socfpga/qts-filter.sh | 4 +- arch/arm/mach-socfpga/wrap_iocsr_config.c | 8 +- arch/arm/mach-socfpga/wrap_pll_config.c | 100 ++++++------ arch/arm/mach-socfpga/wrap_sdram_config.c | 148 +++++++++--------- board/altera/arria5-socdk/qts/iocsr_config.h | 8 +- board/altera/arria5-socdk/qts/pll_config.h | 136 ++++++++-------- board/altera/arria5-socdk/qts/sdram_config.h | 140 ++++++++--------- .../altera/cyclone5-socdk/qts/iocsr_config.h | 8 +- board/altera/cyclone5-socdk/qts/pll_config.h | 136 ++++++++-------- .../altera/cyclone5-socdk/qts/sdram_config.h | 140 ++++++++--------- board/aries/mcvevk/qts/iocsr_config.h | 8 +- board/aries/mcvevk/qts/pll_config.h | 136 ++++++++-------- board/aries/mcvevk/qts/sdram_config.h | 140 ++++++++--------- board/devboards/dbm-soc1/qts/iocsr_config.h | 8 +- board/devboards/dbm-soc1/qts/pll_config.h | 136 ++++++++--------
Reviewed-by: Simon Glass sjg@chromium.org
On Fri, 28 Oct 2022 at 18:27, Tom Rini trini@konsulko.com wrote:
This converts the following to Kconfig: CONFIG_SYS_I2C_INIT_BOARD
Signed-off-by: Tom Rini trini@konsulko.com
README | 11 ----------- board/keymile/Kconfig | 3 +++ board/samsung/common/board.c | 4 ---- board/samsung/goni/goni.c | 10 ---------- drivers/i2c/fsl_i2c.c | 7 ------- drivers/i2c/mv_i2c.c | 24 ------------------------ include/configs/km/pg-wcom-ls102xa.h | 1 - 7 files changed, 3 insertions(+), 57 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
On Fri, Oct 28, 2022 at 08:26:54PM -0400, Tom Rini wrote:
This converts the following to Kconfig: CONFIG_SYS_I2C_INIT_BOARD
Signed-off-by: Tom Rini trini@konsulko.com Reviewed-by: Simon Glass sjg@chromium.org
For the series, applied to u-boot/master, thanks!
participants (3)
-
Jaehoon Chung -
Simon Glass -
Tom Rini