On 05/10/2016 10:13 PM, dinguyen@opensource.altera.com wrote:

From: Dinh Nguyen dinguyen@kernel.org

Update the pinmux and pll configuration for the Cyclone5 RevE or later devkit.

Signed-off-by: Dinh Nguyen dinguyen@opensource.altera.com

Hi Marek,

Hi!

Without these pinmux and pll changes, DS-5 is unable to connect to my board and Linux is stuck in a loop and eventually the watchdog will trigger a reset.

I tested these changes on an earlier rev board, and it seem to be stable as well. When you get a chance, can you try on your devkit?

Tested-by: Marek Vasut marex@denx.de

This is chip rev. AAAA, so probably one of the oldest :)

I'm suggesting that we should include these changes to support the latest devkit. What do you think?

Yes, I agree.

CCing Tom, maybe we can get this into 2016.05 still.

Thanks!

Thanks, Dinh

---

board/altera/cyclone5-socdk/qts/pinmux_config.h | 38 ++++++++++++------------- board/altera/cyclone5-socdk/qts/pll_config.h | 34 +++++++++++----------- 2 files changed, 36 insertions(+), 36 deletions(-)

diff --git a/board/altera/cyclone5-socdk/qts/pinmux_config.h b/board/altera/cyclone5-socdk/qts/pinmux_config.h index f1e6d2b..2d123ba 100644 --- a/board/altera/cyclone5-socdk/qts/pinmux_config.h +++ b/board/altera/cyclone5-socdk/qts/pinmux_config.h @@ -8,7 +8,7 @@ #define __SOCFPGA_PINMUX_CONFIG_H__

const u8 sys_mgr_init_table[] = {

• 3, /* EMACIO0 */

• 0, /* EMACIO0 */ 2, /* EMACIO1 */ 2, /* EMACIO2 */ 2, /* EMACIO3 */

@@ -17,7 +17,7 @@ const u8 sys_mgr_init_table[] = { 2, /* EMACIO6 */ 2, /* EMACIO7 */ 2, /* EMACIO8 */

• 3, /* EMACIO9 */

• 0, /* EMACIO9 */ 2, /* EMACIO10 */ 2, /* EMACIO11 */ 2, /* EMACIO12 */

@@ -32,27 +32,27 @@ const u8 sys_mgr_init_table[] = { 0, /* FLASHIO1 */ 3, /* FLASHIO2 */ 3, /* FLASHIO3 */

• 3, /* FLASHIO4 */
• 3, /* FLASHIO5 */
• 3, /* FLASHIO6 */
• 3, /* FLASHIO7 */

• 0, /* FLASHIO4 */
• 0, /* FLASHIO5 */
• 0, /* FLASHIO6 */
• 0, /* FLASHIO7 */ 0, /* FLASHIO8 */ 3, /* FLASHIO9 */ 3, /* FLASHIO10 */ 3, /* FLASHIO11 */

• 0, /* GENERALIO0 */
• 1, /* GENERALIO1 */
• 1, /* GENERALIO2 */
• 0, /* GENERALIO3 */
• 0, /* GENERALIO4 */
• 1, /* GENERALIO5 */
• 1, /* GENERALIO6 */
• 1, /* GENERALIO7 */
• 1, /* GENERALIO8 */
• 0, /* GENERALIO9 */
• 0, /* GENERALIO10 */
• 0, /* GENERALIO11 */
• 0, /* GENERALIO12 */

• 3, /* GENERALIO0 */
• 3, /* GENERALIO1 */
• 3, /* GENERALIO2 */
• 3, /* GENERALIO3 */
• 3, /* GENERALIO4 */
• 3, /* GENERALIO5 */
• 3, /* GENERALIO6 */
• 3, /* GENERALIO7 */
• 3, /* GENERALIO8 */
• 3, /* GENERALIO9 */
• 3, /* GENERALIO10 */
• 3, /* GENERALIO11 */
• 3, /* GENERALIO12 */ 2, /* GENERALIO13 */ 2, /* GENERALIO14 */ 3, /* GENERALIO15 */

diff --git a/board/altera/cyclone5-socdk/qts/pll_config.h b/board/altera/cyclone5-socdk/qts/pll_config.h index 4abd2e0..408235e 100644 --- a/board/altera/cyclone5-socdk/qts/pll_config.h +++ b/board/altera/cyclone5-socdk/qts/pll_config.h @@ -10,13 +10,13 @@ #define CONFIG_HPS_DBCTRL_STAYOSC1 1

#define CONFIG_HPS_MAINPLLGRP_VCO_DENOM 0 -#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 63 +#define CONFIG_HPS_MAINPLLGRP_VCO_NUMER 73 #define CONFIG_HPS_MAINPLLGRP_MPUCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_MAINCLK_CNT 0 #define CONFIG_HPS_MAINPLLGRP_DBGATCLK_CNT 0 -#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 3 +#define CONFIG_HPS_MAINPLLGRP_MAINQSPICLK_CNT 4 #define CONFIG_HPS_MAINPLLGRP_MAINNANDSDMMCCLK_CNT 511 -#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 15 +#define CONFIG_HPS_MAINPLLGRP_CFGS2FUSER0CLK_CNT 14 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3MPCLK 1 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L3SPCLK 1 #define CONFIG_HPS_MAINPLLGRP_MAINDIV_L4MPCLK 1 @@ -27,26 +27,26 @@ #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4MP 1 #define CONFIG_HPS_MAINPLLGRP_L4SRC_L4SP 1

-#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 1 -#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 79 +#define CONFIG_HPS_PERPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_PERPLLGRP_VCO_NUMER 39 #define CONFIG_HPS_PERPLLGRP_VCO_PSRC 0 -#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 3 +#define CONFIG_HPS_PERPLLGRP_EMAC0CLK_CNT 511 #define CONFIG_HPS_PERPLLGRP_EMAC1CLK_CNT 3 #define CONFIG_HPS_PERPLLGRP_PERQSPICLK_CNT 511 #define CONFIG_HPS_PERPLLGRP_PERNANDSDMMCCLK_CNT 4 #define CONFIG_HPS_PERPLLGRP_PERBASECLK_CNT 4 #define CONFIG_HPS_PERPLLGRP_S2FUSER1CLK_CNT 511 #define CONFIG_HPS_PERPLLGRP_DIV_USBCLK 0 -#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 4 +#define CONFIG_HPS_PERPLLGRP_DIV_SPIMCLK 0 #define CONFIG_HPS_PERPLLGRP_DIV_CAN0CLK 1 -#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 1 +#define CONFIG_HPS_PERPLLGRP_DIV_CAN1CLK 4 #define CONFIG_HPS_PERPLLGRP_GPIODIV_GPIODBCLK 6249 #define CONFIG_HPS_PERPLLGRP_SRC_SDMMC 2 #define CONFIG_HPS_PERPLLGRP_SRC_NAND 2 #define CONFIG_HPS_PERPLLGRP_SRC_QSPI 1

-#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 2 -#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 79 +#define CONFIG_HPS_SDRPLLGRP_VCO_DENOM 0 +#define CONFIG_HPS_SDRPLLGRP_VCO_NUMER 31 #define CONFIG_HPS_SDRPLLGRP_VCO_SSRC 0 #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_CNT 1 #define CONFIG_HPS_SDRPLLGRP_DDRDQSCLK_PHASE 0 @@ -61,25 +61,25 @@ #define CONFIG_HPS_CLK_OSC2_HZ 25000000 #define CONFIG_HPS_CLK_F2S_SDR_REF_HZ 0 #define CONFIG_HPS_CLK_F2S_PER_REF_HZ 0 -#define CONFIG_HPS_CLK_MAINVCO_HZ 1600000000 +#define CONFIG_HPS_CLK_MAINVCO_HZ 1850000000 #define CONFIG_HPS_CLK_PERVCO_HZ 1000000000 -#define CONFIG_HPS_CLK_SDRVCO_HZ 666666666 -#define CONFIG_HPS_CLK_EMAC0_HZ 250000000 +#define CONFIG_HPS_CLK_SDRVCO_HZ 800000000 +#define CONFIG_HPS_CLK_EMAC0_HZ 1953125 #define CONFIG_HPS_CLK_EMAC1_HZ 250000000 #define CONFIG_HPS_CLK_USBCLK_HZ 200000000 #define CONFIG_HPS_CLK_NAND_HZ 50000000 #define CONFIG_HPS_CLK_SDMMC_HZ 200000000 -#define CONFIG_HPS_CLK_QSPI_HZ 400000000 +#define CONFIG_HPS_CLK_QSPI_HZ 370000000 #define CONFIG_HPS_CLK_SPIM_HZ 200000000 #define CONFIG_HPS_CLK_CAN0_HZ 100000000 -#define CONFIG_HPS_CLK_CAN1_HZ 100000000 +#define CONFIG_HPS_CLK_CAN1_HZ 12500000 #define CONFIG_HPS_CLK_GPIODB_HZ 32000 #define CONFIG_HPS_CLK_L4_MP_HZ 100000000 #define CONFIG_HPS_CLK_L4_SP_HZ 100000000

#define CONFIG_HPS_ALTERAGRP_MPUCLK 1 -#define CONFIG_HPS_ALTERAGRP_MAINCLK 3 -#define CONFIG_HPS_ALTERAGRP_DBGATCLK 3 +#define CONFIG_HPS_ALTERAGRP_MAINCLK 4 +#define CONFIG_HPS_ALTERAGRP_DBGATCLK 4

#endif /* __SOCFPGA_PLL_CONFIG_H__ */