[U-Boot] [PATCH] add block write function to spartan3 slave serial load
Using seperate function calls for each bit-bang of slave serial load can be painfully slow. This patch adds the possibility to supply a block write function that loads the complete block of data in one call (like it can already be done with Altera FPGAs). On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load time from around 15 seconds to around 3 seconds
Signed-off-by: Wolfgang Wegner w.wegner@astro-kom.de --- drivers/fpga/spartan3.c | 54 +++++++++++++++++++++++++--------------------- include/spartan3.h | 1 + include/xilinx.h | 1 + 3 files changed, 31 insertions(+), 25 deletions(-)
diff --git a/drivers/fpga/spartan3.c b/drivers/fpga/spartan3.c index 0fe3041..7a89b56 100644 --- a/drivers/fpga/spartan3.c +++ b/drivers/fpga/spartan3.c @@ -385,34 +385,38 @@ static int Spartan3_ss_load (Xilinx_desc * desc, void *buf, size_t bsize) } while ((*fn->init) (cookie));
/* Load the data */ - while (bytecount < bsize) { - - /* Xilinx detects an error if INIT goes low (active) - while DONE is low (inactive) */ - if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) { - puts ("** CRC error during FPGA load.\n"); - return (FPGA_FAIL); - } - val = data [bytecount ++]; - i = 8; - do { - /* Deassert the clock */ - (*fn->clk) (FALSE, TRUE, cookie); - CONFIG_FPGA_DELAY (); - /* Write data */ - (*fn->wr) ((val & 0x80), TRUE, cookie); - CONFIG_FPGA_DELAY (); - /* Assert the clock */ - (*fn->clk) (TRUE, TRUE, cookie); - CONFIG_FPGA_DELAY (); - val <<= 1; - i --; - } while (i > 0); + if(*fn->bwr) + (*fn->bwr) (data, bsize, TRUE, cookie); + else { + while (bytecount < bsize) { + + /* Xilinx detects an error if INIT goes low (active) + while DONE is low (inactive) */ + if ((*fn->done) (cookie) == 0 && (*fn->init) (cookie)) { + puts ("** CRC error during FPGA load.\n"); + return (FPGA_FAIL); + } + val = data [bytecount ++]; + i = 8; + do { + /* Deassert the clock */ + (*fn->clk) (FALSE, TRUE, cookie); + CONFIG_FPGA_DELAY (); + /* Write data */ + (*fn->wr) ((val & 0x80), TRUE, cookie); + CONFIG_FPGA_DELAY (); + /* Assert the clock */ + (*fn->clk) (TRUE, TRUE, cookie); + CONFIG_FPGA_DELAY (); + val <<= 1; + i --; + } while (i > 0);
#ifdef CONFIG_SYS_FPGA_PROG_FEEDBACK - if (bytecount % (bsize / 40) == 0) - putc ('.'); /* let them know we are alive */ + if (bytecount % (bsize / 40) == 0) + putc ('.'); /* let them know we are alive */ #endif + } }
CONFIG_FPGA_DELAY (); diff --git a/include/spartan3.h b/include/spartan3.h index 30b1c2d..d5a589d 100644 --- a/include/spartan3.h +++ b/include/spartan3.h @@ -57,6 +57,7 @@ typedef struct { Xilinx_done_fn done; Xilinx_wr_fn wr; Xilinx_post_fn post; + Xilinx_bwr_fn bwr; /* block write function */ } Xilinx_Spartan3_Slave_Serial_fns;
/* Device Image Sizes diff --git a/include/xilinx.h b/include/xilinx.h index d0799bc..2cb2e5b 100644 --- a/include/xilinx.h +++ b/include/xilinx.h @@ -100,5 +100,6 @@ typedef int (*Xilinx_busy_fn)( int cookie ); typedef int (*Xilinx_abort_fn)( int cookie ); typedef int (*Xilinx_pre_fn)( int cookie ); typedef int (*Xilinx_post_fn)( int cookie ); +typedef int (*Xilinx_bwr_fn)( void *buf, size_t len, int flush, int cookie );
#endif /* _XILINX_H_ */
Dear Wolfgang Wegner,
In message 1256918102-3760-1-git-send-email-w.wegner@astro-kom.de you wrote:
Using seperate function calls for each bit-bang of slave serial load can be painfully slow. This patch adds the possibility to supply a block write function that loads the complete block of data in one call (like it can already be done with Altera FPGAs). On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load time from around 15 seconds to around 3 seconds
Where is this block write function being implemented?
I don't see it anywhere in the patch, nor any code that actually uses it?
Best regards,
Wolfgang Denk
Dear Wolfgang Denk,
On 2 Dec 2009 at 22:44, Wolfgang Denk wrote:
Dear Wolfgang Wegner,
In message 1256918102-3760-1-git-send-email-w.wegner@astro-kom.de you wrote:
Using seperate function calls for each bit-bang of slave serial load can be painfully slow. This patch adds the possibility to supply a block write function that loads the complete block of data in one call (like it can already be done with Altera FPGAs). On an MCF5373L (240 MHz) loading an XC3S4000 this reduces the load time from around 15 seconds to around 3 seconds
Where is this block write function being implemented?
I don't see it anywhere in the patch, nor any code that actually uses it?
sorry, my wording was probably wrong. This current patch only adds the framework in the FPGA code needed to use such a block write function.
Like all FPGA load functions, the function itself is located in my board- specific code (which is not yet submitted because I have to clean up some coding style issues in one of the files and it depends on the other patches I sent). My understanding was that such framework changes should always be sent as seperate patches and the (new) board that uses it as a different patch.
Best regards, Wolfgang
Dear w.wegner@astro-kom.de,
In message 4B18E5C5.22102.97D23@w.wegner.astro-kom.de you wrote:
Where is this block write function being implemented?
I don't see it anywhere in the patch, nor any code that actually uses it?
sorry, my wording was probably wrong. This current patch only adds the framework in the FPGA code needed to use such a block write function.
Like all FPGA load functions, the function itself is located in my board- specific code (which is not yet submitted because I have to clean up some coding style issues in one of the files and it depends on the other patches I sent). My understanding was that such framework changes should always be sent as seperate patches and the (new) board that uses it as a different patch.
Yes, but we don't add one without the other. There have been too many cases where people asked for fancy features for specific boards that were out-of-tree ports without any attempts to get merged, so we now always wait for actual use cases. [I do not want to suggest that I consider yours as one of these situations, but the effect is the same.]
I put this patch on hold until you submit code that requires / uses it.
Best regards,
Wolfgang Denk
On 4 Dec 2009 at 11:16, Wolfgang Denk wrote:
[...]
Yes, but we don't add one without the other. There have been too many cases where people asked for fancy features for specific boards that were out-of-tree ports without any attempts to get merged, so we now always wait for actual use cases. [I do not want to suggest that I consider yours as one of these situations, but the effect is the same.]
I put this patch on hold until you submit code that requires / uses it.
Agreed and working on it.
[But hey, it´s not fancy, it is just a tiny step towards consistency with Altera FPGA code which always uses block write. ;-) ]
Regards, Wolfgang
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Wolfgang Wegner