[PATCH 00/10] arm64: zynqmp: Various DT fixes
Hi,
I am sending couple of patches to extend DT for zynqmp boards. Modepin and si5328 dt bindings are available in the Linux kernel. The rest are small changes with the existing DT binding mostly in Linux.
Thanks, Michal
Michal Simek (7): arm64: zynqmp: Add gpio labels for modepin arm64: zynqmp: Fix opp-table-cpu arm64: zynqmp: Add power domain description for PL arm64: zynqmp: Add dmas, gpu, rtc, watchdogs and opp nodes for SOM arm64: zynqmp: Add PHY description for SGMII on vck190 SC arm64: zynqmp: Add linux,code for fwuen button arm64: zynqmp: Add DT description for si5328 for zcu102/zcu106
Piyush Mehta (1): arm64: zynqmp: Add mode-pin GPIO controller DT node
T Karthik Reddy (1): Revert "arm64: zynqmp: Add zynqmp firmware specific DT nodes"
Vishal Patel (1): arm64: zynqmp: Add pwm-fan node and fix ttc0 pwm-cells property
arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 15 ++++ arch/arm/dts/zynqmp-mini-emmc0.dts | 40 --------- arch/arm/dts/zynqmp-mini-emmc1.dts | 40 --------- arch/arm/dts/zynqmp-sm-k26-revA.dts | 113 ++++++++++++++++++++++++ arch/arm/dts/zynqmp-zcu102-revA.dts | 21 ++++- arch/arm/dts/zynqmp-zcu106-revA.dts | 21 ++++- arch/arm/dts/zynqmp.dtsi | 11 ++- 7 files changed, 178 insertions(+), 83 deletions(-)
From: Piyush Mehta piyush.mehta@xilinx.com
Add mode-pin GPIO controller DT node in zynqmp.dtsi and also setup default reset-gpios property for usb which is default Xilinx setup.
Signed-off-by: Piyush Mehta piyush.mehta@xilinx.com Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp.dtsi | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index c44260885023..6b711c810e67 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -13,6 +13,7 @@ */
#include <dt-bindings/dma/xlnx-zynqmp-dpdma.h> +#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/power/xlnx-zynqmp-power.h> #include <dt-bindings/reset/xlnx-zynqmp-resets.h>
@@ -189,6 +190,12 @@ compatible = "xlnx,zynqmp-pinctrl"; status = "disabled"; }; + + modepin_gpio: gpio { + compatible = "xlnx,zynqmp-gpio-modepin"; + gpio-controller; + #gpio-cells = <2>; + }; }; };
@@ -874,6 +881,7 @@ <&zynqmp_reset ZYNQMP_RESET_USB0_HIBERRESET>, <&zynqmp_reset ZYNQMP_RESET_USB0_APB>; reset-names = "usb_crst", "usb_hibrst", "usb_apbrst"; + reset-gpios = <&modepin_gpio 1 GPIO_ACTIVE_LOW>; ranges;
dwc3_0: usb@fe200000 {
From: Michal Simek michal.simek@xilinx.com
Using labels helps with better identifications of chips.
Signed-off-by: Michal Simek michal.simek@xilinx.com Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp-sm-k26-revA.dts | 4 ++++ 1 file changed, 4 insertions(+)
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index e904cd8ea093..a2c88dc34c6b 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -89,6 +89,10 @@ }; };
+&modepin_gpio { + label = "modepin"; +}; + &uart1 { /* MIO36/MIO37 */ status = "okay"; };
OPP table name now should start with "opp-table" and OPP entries shouldn't contain commas and @ signs in accordance to the new schema requirement.
The same change was done in Linux by commit c6d4a8977598 ("ARM: tegra: Rename CPU and EMC OPP table device-tree nodes"), commit ffbe853a3f5a ("ARM: dts: sunxi: Fix OPPs node name") or commit b7072cc5704d ("arm64: dts: qcom: qcs404: Rename CPU and CPR OPP tables").
Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp.dtsi | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index 6b711c810e67..a0f664a59db6 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -76,7 +76,7 @@ }; };
- cpu_opp_table: cpu-opp-table { + cpu_opp_table: opp-table-cpu { compatible = "operating-points-v2"; opp-shared; opp00 {
From: Michal Simek michal.simek@xilinx.com
PL has own power domain which is not described in DT. That's why add it there by default.
Signed-off-by: Michal Simek michal.simek@xilinx.com Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp.dtsi | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/dts/zynqmp.dtsi b/arch/arm/dts/zynqmp.dtsi index a0f664a59db6..dae8f0669df8 100644 --- a/arch/arm/dts/zynqmp.dtsi +++ b/arch/arm/dts/zynqmp.dtsi @@ -218,6 +218,7 @@ #address-cells = <2>; #size-cells = <2>; ranges; + power-domains = <&zynqmp_firmware PD_PL>; };
amba: axi {
From: Vishal Patel vishal.patel@xilinx.com
Add pwm-fan node to control fan through hwmon and change pwm-cells property to 3 to allow fancontrol utility to function correctly.
Signed-off-by: Vishal Patel vishal.patel@xilinx.com Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp-sm-k26-revA.dts | 11 +++++++++++ 1 file changed, 11 insertions(+)
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index a2c88dc34c6b..8b2cd512da56 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -87,12 +87,23 @@ <&xilinx_ams 24>, <&xilinx_ams 25>, <&xilinx_ams 26>, <&xilinx_ams 27>, <&xilinx_ams 28>, <&xilinx_ams 29>; }; + + pwm-fan { + compatible = "pwm-fan"; + status = "okay"; + pwms = <&ttc0 2 40000 0>; + }; };
&modepin_gpio { label = "modepin"; };
+&ttc0 { + status = "okay"; + #pwm-cells = <3>; +}; + &uart1 { /* MIO36/MIO37 */ status = "okay"; };
From: Michal Simek michal.simek@xilinx.com
There are couple of IPs which are enabled in origin HW design which are missing in SOM dt. Add them to match default setup.
Signed-off-by: Michal Simek michal.simek@xilinx.com Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp-sm-k26-revA.dts | 95 +++++++++++++++++++++++++++++ 1 file changed, 95 insertions(+)
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index 8b2cd512da56..35fab915172b 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -356,3 +356,98 @@ &zynqmp_dpsub { status = "okay"; }; + +&rtc { + status = "okay"; +}; + +&lpd_dma_chan1 { + status = "okay"; +}; + +&lpd_dma_chan2 { + status = "okay"; +}; + +&lpd_dma_chan3 { + status = "okay"; +}; + +&lpd_dma_chan4 { + status = "okay"; +}; + +&lpd_dma_chan5 { + status = "okay"; +}; + +&lpd_dma_chan6 { + status = "okay"; +}; + +&lpd_dma_chan7 { + status = "okay"; +}; + +&lpd_dma_chan8 { + status = "okay"; +}; + +&fpd_dma_chan1 { + status = "okay"; +}; + +&fpd_dma_chan2 { + status = "okay"; +}; + +&fpd_dma_chan3 { + status = "okay"; +}; + +&fpd_dma_chan4 { + status = "okay"; +}; + +&fpd_dma_chan5 { + status = "okay"; +}; + +&fpd_dma_chan6 { + status = "okay"; +}; + +&fpd_dma_chan7 { + status = "okay"; +}; + +&fpd_dma_chan8 { + status = "okay"; +}; + +&gpu { + status = "okay"; +}; + +&lpd_watchdog { + status = "okay"; +}; + +&watchdog0 { + status = "okay"; +}; + +&cpu_opp_table { + opp00 { + opp-hz = /bits/ 64 <1333333333>; + }; + opp01 { + opp-hz = /bits/ 64 <666666666>; + }; + opp02 { + opp-hz = /bits/ 64 <444444444>; + }; + opp03 { + opp-hz = /bits/ 64 <333333333>; + }; +};
From: T Karthik Reddy t.karthik.reddy@xilinx.com
This reverts commit 50a6bd000f94832658f42fb01b9aaf9e39a52004.
As zynqmp mini emmc does not rely on firmware, remove firmware related device tree modes from zynqmp mini emmc dts files.
Signed-off-by: T Karthik Reddy t.karthik.reddy@xilinx.com Acked-by: Ashok Reddy Soma ashok.reddy.soma@xilinx.com Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp-mini-emmc0.dts | 40 ------------------------------ arch/arm/dts/zynqmp-mini-emmc1.dts | 40 ------------------------------ 2 files changed, 80 deletions(-)
diff --git a/arch/arm/dts/zynqmp-mini-emmc0.dts b/arch/arm/dts/zynqmp-mini-emmc0.dts index 8d9f9ca37259..8467dd8e1cc7 100644 --- a/arch/arm/dts/zynqmp-mini-emmc0.dts +++ b/arch/arm/dts/zynqmp-mini-emmc0.dts @@ -41,46 +41,6 @@ clock-frequency = <200000000>; };
- firmware { - zynqmp_firmware: zynqmp-firmware { - compatible = "xlnx,zynqmp-firmware"; - #power-domain-cells = <1>; - method = "smc"; - u-boot,dm-pre-reloc; - - zynqmp_power: zynqmp-power { - u-boot,dm-pre-reloc; - compatible = "xlnx,zynqmp-power"; - mboxes = <&ipi_mailbox_pmu1 0>, - <&ipi_mailbox_pmu1 1>; - mbox-names = "tx", "rx"; - }; - }; - }; - - zynqmp_ipi: zynqmp_ipi { - u-boot,dm-pre-reloc; - compatible = "xlnx,zynqmp-ipi-mailbox"; - xlnx,ipi-id = <0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ipi_mailbox_pmu1: mailbox@ff990400 { - u-boot,dm-pre-reloc; - reg = <0x0 0xff9905c0 0x0 0x20>, - <0x0 0xff9905e0 0x0 0x20>, - <0x0 0xff990e80 0x0 0x20>, - <0x0 0xff990ea0 0x0 0x20>; - reg-names = "local_request_region", - "local_response_region", - "remote_request_region", - "remote_response_region"; - #mbox-cells = <1>; - xlnx,ipi-id = <4>; - }; - }; - amba: amba { compatible = "simple-bus"; #address-cells = <2>; diff --git a/arch/arm/dts/zynqmp-mini-emmc1.dts b/arch/arm/dts/zynqmp-mini-emmc1.dts index 5722b762d679..2afcc7751b9f 100644 --- a/arch/arm/dts/zynqmp-mini-emmc1.dts +++ b/arch/arm/dts/zynqmp-mini-emmc1.dts @@ -41,46 +41,6 @@ clock-frequency = <200000000>; };
- firmware { - zynqmp_firmware: zynqmp-firmware { - compatible = "xlnx,zynqmp-firmware"; - #power-domain-cells = <1>; - method = "smc"; - u-boot,dm-pre-reloc; - - zynqmp_power: zynqmp-power { - u-boot,dm-pre-reloc; - compatible = "xlnx,zynqmp-power"; - mboxes = <&ipi_mailbox_pmu1 0>, - <&ipi_mailbox_pmu1 1>; - mbox-names = "tx", "rx"; - }; - }; - }; - - zynqmp_ipi: zynqmp_ipi { - u-boot,dm-pre-reloc; - compatible = "xlnx,zynqmp-ipi-mailbox"; - xlnx,ipi-id = <0>; - #address-cells = <2>; - #size-cells = <2>; - ranges; - - ipi_mailbox_pmu1: mailbox@ff990400 { - u-boot,dm-pre-reloc; - reg = <0x0 0xff9905c0 0x0 0x20>, - <0x0 0xff9905e0 0x0 0x20>, - <0x0 0xff990e80 0x0 0x20>, - <0x0 0xff990ea0 0x0 0x20>; - reg-names = "local_request_region", - "local_response_region", - "remote_request_region", - "remote_response_region"; - #mbox-cells = <1>; - xlnx,ipi-id = <4>; - }; - }; - amba: amba { compatible = "simple-bus"; #address-cells = <2>;
From: Michal Simek michal.simek@xilinx.com
SGMII requires phy to be configured. The support for this has been added to Linux and U-Boot already that's why also describe the phy via DT. Clock is coming from si5332 chip (output 1) 125MHz which is only one GT line use on this board.
Signed-off-by: Michal Simek michal.simek@xilinx.com Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 15 +++++++++++++++ 1 file changed, 15 insertions(+)
diff --git a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts index f229880a7021..726183782305 100644 --- a/arch/arm/dts/zynqmp-e-a2197-00-revA.dts +++ b/arch/arm/dts/zynqmp-e-a2197-00-revA.dts @@ -42,6 +42,12 @@ reg = <0x0 0x0 0x0 0x80000000>; };
+ si5332_1: si5332_1 { /* u142 - GEM0 */ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <125000000>; + }; + ina226-vccint { compatible = "iio-hwmon"; io-channels = <&vccint 0>, <&vccint 1>, <&vccint 2>, <&vccint 3>; @@ -135,8 +141,17 @@ xlnx,mio-bank = <1>; };
+/* GEM SGMII */ +&psgtr { + status = "okay"; + /* gem0 */ + clocks = <&si5332_1>; + clock-names = "ref0"; +}; + &gem0 { status = "okay"; + phys = <&psgtr 0 PHY_TYPE_SGMII 0 0>; phy-handle = <&phy0>; phy-mode = "sgmii"; is-internal-pcspma;
BTN_MISC looks like the most reasonable option for this button. Button is used by firmware to indicate (after reset, power up) that user wants to do firmware upgrade via firmware update utility. For bootloader or OS is this just user button which is worth to have it mapped. Also button can be used as a wakeup source and pressing it for more time can generate more chars that's why also adding wakeup-source and autorepeat properties.
Signed-off-by: Michal Simek michal.simek@amd.com Reviewed-by: Radhey Shyam Pandey radhey.shyam.pandey@amd.com ---
arch/arm/dts/zynqmp-sm-k26-revA.dts | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/arm/dts/zynqmp-sm-k26-revA.dts b/arch/arm/dts/zynqmp-sm-k26-revA.dts index 35fab915172b..7c2bfa395da7 100644 --- a/arch/arm/dts/zynqmp-sm-k26-revA.dts +++ b/arch/arm/dts/zynqmp-sm-k26-revA.dts @@ -56,6 +56,9 @@ fwuen { label = "fwuen"; gpios = <&gpio 12 GPIO_ACTIVE_LOW>; + linux,code = <BTN_MISC>; + wakeup-source; + autorepeat; }; };
From: Michal Simek michal.simek@xilinx.com
Origin DT binding just specify driver but wasn't aligned with DT binding which came later. Extend description for zcu102 and zcu106 to cover latest binding.
Signed-off-by: Michal Simek michal.simek@xilinx.com Signed-off-by: Michal Simek michal.simek@amd.com ---
arch/arm/dts/zynqmp-zcu102-revA.dts | 21 ++++++++++++++++++++- arch/arm/dts/zynqmp-zcu106-revA.dts | 21 ++++++++++++++++++++- 2 files changed, 40 insertions(+), 2 deletions(-)
diff --git a/arch/arm/dts/zynqmp-zcu102-revA.dts b/arch/arm/dts/zynqmp-zcu102-revA.dts index aac798d6e74a..c13b52a6aeaa 100644 --- a/arch/arm/dts/zynqmp-zcu102-revA.dts +++ b/arch/arm/dts/zynqmp-zcu102-revA.dts @@ -604,7 +604,26 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - /* SI5328 - u20 */ + si5328: clock-generator@69 {/* SI5328 - u20 */ + compatible = "silabs,si5328"; + reg = <0x69>; + /* + * Chip has interrupt present connected to PL + * interrupt-parent = <&>; + * interrupts = <>; + */ + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + clocks = <&refhdmi>; + clock-names = "xtal"; + clock-output-names = "si5328"; + + si5328_clk: clk0@0 { + reg = <0>; + clock-frequency = <27000000>; + }; + }; }; /* 5 - 7 unconnected */ }; diff --git a/arch/arm/dts/zynqmp-zcu106-revA.dts b/arch/arm/dts/zynqmp-zcu106-revA.dts index 03624648cd71..6dfc8fe17bf2 100644 --- a/arch/arm/dts/zynqmp-zcu106-revA.dts +++ b/arch/arm/dts/zynqmp-zcu106-revA.dts @@ -593,7 +593,26 @@ #address-cells = <1>; #size-cells = <0>; reg = <4>; - /* SI5328 - u20 */ + si5328: clock-generator@69 {/* SI5328 - u20 */ + compatible = "silabs,si5328"; + reg = <0x69>; + /* + * Chip has interrupt present connected to PL + * interrupt-parent = <&>; + * interrupts = <>; + */ + #address-cells = <1>; + #size-cells = <0>; + #clock-cells = <1>; + clocks = <&refhdmi>; + clock-names = "xtal"; + clock-output-names = "si5328"; + + si5328_clk: clk0@0 { + reg = <0>; + clock-frequency = <27000000>; + }; + }; }; i2c@5 { #address-cells = <1>;
st 11. 5. 2022 v 11:52 odesÃlatel Michal Simek monstr@monstr.eu napsal:
Hi,
I am sending couple of patches to extend DT for zynqmp boards. Modepin and si5328 dt bindings are available in the Linux kernel. The rest are small changes with the existing DT binding mostly in Linux.
Thanks, Michal
Michal Simek (7): arm64: zynqmp: Add gpio labels for modepin arm64: zynqmp: Fix opp-table-cpu arm64: zynqmp: Add power domain description for PL arm64: zynqmp: Add dmas, gpu, rtc, watchdogs and opp nodes for SOM arm64: zynqmp: Add PHY description for SGMII on vck190 SC arm64: zynqmp: Add linux,code for fwuen button arm64: zynqmp: Add DT description for si5328 for zcu102/zcu106
Piyush Mehta (1): arm64: zynqmp: Add mode-pin GPIO controller DT node
T Karthik Reddy (1): Revert "arm64: zynqmp: Add zynqmp firmware specific DT nodes"
Vishal Patel (1): arm64: zynqmp: Add pwm-fan node and fix ttc0 pwm-cells property
arch/arm/dts/zynqmp-e-a2197-00-revA.dts | 15 ++++ arch/arm/dts/zynqmp-mini-emmc0.dts | 40 --------- arch/arm/dts/zynqmp-mini-emmc1.dts | 40 --------- arch/arm/dts/zynqmp-sm-k26-revA.dts | 113 ++++++++++++++++++++++++ arch/arm/dts/zynqmp-zcu102-revA.dts | 21 ++++- arch/arm/dts/zynqmp-zcu106-revA.dts | 21 ++++- arch/arm/dts/zynqmp.dtsi | 11 ++- 7 files changed, 178 insertions(+), 83 deletions(-)
-- 2.36.0
Applied. M
participants (1)
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Michal Simek