[PATCH V2 0/5] board: beagle: Enable 32k and debounce configuration and fixups
Hi,
Rev 2 of the series.
This is a follow up from [1] - Without the 32k crystal configuration, wlan doesn't work. Debounce is needed for HDMI Hot plug detect(hpd) gpio interrupt not storming.
At least the 32k configuration has been done for toradex and phytec boards, follow similar model of programming.
Series is now based off master branch.
Bootlog: https://gist.github.com/nmenon/75df38bee907785d1d78d1ec4abd7304
Changes from V2: - Removed depedency on [2] - depending on which way the merge sequence goes, one of the series will need a rebase. - Added a patch for a bug that Jan noticed - Fixup for the fat finger missing 0x in 0x4080 :(
V1: https://lore.kernel.org/all/20240212155332.541949-1-nm@ti.com/
Nishanth Menon : board: beagle: beagleplay: Enable 32k crystal configs: am62x_beagleplay_r5_defconfig: Enable SPL_BOARD_INIT arm: mach-k3: am62: Add Debounce configuration register definitions board: beagle: beagleplay: Configure debounce registers board: beagle: beagleplay: env: Drop usb and pxe as boot targets
arch/arm/mach-k3/include/mach/am62_hardware.h | 3 + board/beagle/beagleplay/beagleplay.c | 61 +++++++++++++++++++ board/beagle/beagleplay/beagleplay.env | 2 +- configs/am62x_beagleplay_r5_defconfig | 1 + 4 files changed, 66 insertions(+), 1 deletion(-)
base-commit: 3e6f2a94bfc25f1782ce2d45db27f47ec781feb1
[1] https://lore.kernel.org/u-boot/20230725185253.2123433-4-nm@ti.com/ [2] https://lore.kernel.org/u-boot/20240212194726.1093771-1-nm@ti.com/
Enable the external 32k crystal similar to that found on other production AM62X board. The trim settings for the crystal is board dependent, so the sequences tend to be board specific. Since this is a configuration that needs to be done prior to DM managing the system and all other muxes get set, do the same from R5 context.
Tested-by: Robert Nelson robertcnelson@gmail.com Signed-off-by: Nishanth Menon nm@ti.com --- Changes from V1: * Added Robert's tested by.
V1: https://lore.kernel.org/r/20240212155332.541949-2-nm@ti.com
board/beagle/beagleplay/beagleplay.c | 37 ++++++++++++++++++++++++++++ 1 file changed, 37 insertions(+)
diff --git a/board/beagle/beagleplay/beagleplay.c b/board/beagle/beagleplay/beagleplay.c index 1c376dea372f..2adb2517ef00 100644 --- a/board/beagle/beagleplay/beagleplay.c +++ b/board/beagle/beagleplay/beagleplay.c @@ -11,6 +11,8 @@ #include <fdt_support.h> #include <spl.h>
+#include <asm/arch/hardware.h> + DECLARE_GLOBAL_DATA_PTR;
int board_init(void) @@ -27,3 +29,38 @@ int dram_init_banksize(void) { return fdtdec_setup_memory_banksize(); } + +#ifdef CONFIG_SPL_BOARD_INIT + +/* + * Enable the 32k Crystal: needed for accurate 32k clock + * and external clock sources such as wlan 32k input clock + * supplied from the SoC to the wlan chip. + * + * The trim setup can be very highly board type specific choice of the crystal + * So this is done in the board file, though, in this case, no specific trim + * is necessary. + */ +static void crystal_32k_enable(void) +{ + /* Only mess with 32k at the start of boot from R5 */ + if (IS_ENABLED(CONFIG_CPU_V7R)) { + /* + * We have external 32k crystal, so lets enable it (0x0) + * and disable bypass (0x0) + */ + writel(0x0, MCU_CTRL_LFXOSC_CTRL); + + /* Add any crystal specific TRIM needed here.. */ + + /* Make sure to mux the SoC 32k from the crystal */ + writel(MCU_CTRL_DEVICE_CLKOUT_LFOSC_SELECT_VAL, + MCU_CTRL_DEVICE_CLKOUT_32K_CTRL); + } +} + +void spl_board_init(void) +{ + crystal_32k_enable(); +} +#endif
Enable CONFIG_SPL_BOARD_INIT to configure the 32k crystal.
Signed-off-by: Nishanth Menon nm@ti.com --- Changes since V1: * No change
V1: https://lore.kernel.org/r/20240212155332.541949-3-nm@ti.com
configs/am62x_beagleplay_r5_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/am62x_beagleplay_r5_defconfig b/configs/am62x_beagleplay_r5_defconfig index 2f3264b7ede6..9413c859870f 100644 --- a/configs/am62x_beagleplay_r5_defconfig +++ b/configs/am62x_beagleplay_r5_defconfig @@ -36,6 +36,7 @@ CONFIG_SPL_HAS_BSS_LINKER_SECTION=y CONFIG_SPL_BSS_START_ADDR=0x43c3b000 CONFIG_SPL_BSS_MAX_SIZE=0x3000 CONFIG_SPL_SYS_REPORT_STACK_F_USAGE=y +CONFIG_SPL_BOARD_INIT=y CONFIG_SPL_SYS_MALLOC_SIMPLE=y CONFIG_SPL_STACK_R=y CONFIG_SPL_SEPARATE_BSS=y
Add the Debounce configuration registers that need to be configured one time for the platform for the entire SoC.
Signed-off-by: Nishanth Menon nm@ti.com --- Changes since V1: * Fix 4080 to 0x4080
V1: https://lore.kernel.org/r/20240212155332.541949-4-nm@ti.com
arch/arm/mach-k3/include/mach/am62_hardware.h | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-k3/include/mach/am62_hardware.h b/arch/arm/mach-k3/include/mach/am62_hardware.h index 54380f36e161..4cf7778a89ee 100644 --- a/arch/arm/mach-k3/include/mach/am62_hardware.h +++ b/arch/arm/mach-k3/include/mach/am62_hardware.h @@ -75,6 +75,9 @@
#define CTRLMMR_MCU_RST_CTRL (MCU_CTRL_MMR0_BASE + 0x18170)
+/* Debounce register configuration */ +#define CTRLMMR_DBOUNCE_CFG(index) (MCU_CTRL_MMR0_BASE + 0x4080 + (index * 4)) + #define ROM_EXTENDED_BOOT_DATA_INFO 0x43c3f1e0
#define TI_SRAM_SCRATCH_BOARD_EEPROM_START 0x43c30000
Configure the debounce configuration that makes sense for BeaglePlay usage model.
Signed-off-by: Nishanth Menon nm@ti.com --- Changes since V1: * No change
V1: https://lore.kernel.org/r/20240212155332.541949-5-nm@ti.com
board/beagle/beagleplay/beagleplay.c | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
diff --git a/board/beagle/beagleplay/beagleplay.c b/board/beagle/beagleplay/beagleplay.c index 2adb2517ef00..fe1c4f920329 100644 --- a/board/beagle/beagleplay/beagleplay.c +++ b/board/beagle/beagleplay/beagleplay.c @@ -59,8 +59,32 @@ static void crystal_32k_enable(void) } }
+static void debounce_configure(void) +{ + /* Configure debounce one time from R5 */ + if (IS_ENABLED(CONFIG_CPU_V7R)) { + /* + * Setup debounce time registers. + * arbitrary values. Times are approx + */ + /* 1.9ms debounce @ 32k */ + writel(0x1, CTRLMMR_DBOUNCE_CFG(1)); + /* 5ms debounce @ 32k */ + writel(0x5, CTRLMMR_DBOUNCE_CFG(2)); + /* 20ms debounce @ 32k */ + writel(0x14, CTRLMMR_DBOUNCE_CFG(3)); + /* 46ms debounce @ 32k */ + writel(0x18, CTRLMMR_DBOUNCE_CFG(4)); + /* 100ms debounce @ 32k */ + writel(0x1c, CTRLMMR_DBOUNCE_CFG(5)); + /* 156ms debounce @ 32k */ + writel(0x1f, CTRLMMR_DBOUNCE_CFG(6)); + } +} + void spl_board_init(void) { crystal_32k_enable(); + debounce_configure(); } #endif
We had enabled USB and network pxe boot with the hope to get it all merged on time. However, it has not panned out. Drop usb and pxe boot else bootflow scan -l throws in: a) Unknown uclass 'usb' in label b) Crashes when attempting pxe - cpsw/mdio driver apparently has missing error handling of what ever form. This is the one that Jan noticed in his log.
We can enable these on a later date once things are working.
Cc: Roger Quadros rogerq@kernel.org
Reported-by: Jan Kiszka jan.kiszka@siemens.com Closes: https://lore.kernel.org/all/782ea2c0-eef5-478d-a122-cc6e2d066762@siemens.com... Signed-off-by: Nishanth Menon nm@ti.com --- - New patch in V2 of the series.
board/beagle/beagleplay/beagleplay.env | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/board/beagle/beagleplay/beagleplay.env b/board/beagle/beagleplay/beagleplay.env index 4f0a94a8113e..db737e069b58 100644 --- a/board/beagle/beagleplay/beagleplay.env +++ b/board/beagle/beagleplay/beagleplay.env @@ -14,6 +14,6 @@ boot=mmc mmcdev=1 bootpart=1:1 bootdir=/boot -boot_targets=mmc1 mmc0 usb pxe +boot_targets=mmc1 mmc0 bootmeths=script extlinux efi pxe rd_spec=-
On Tue, 20 Feb 2024 12:39:47 -0600, Nishanth Menon wrote:
Rev 2 of the series.
This is a follow up from [1] - Without the 32k crystal configuration, wlan doesn't work. Debounce is needed for HDMI Hot plug detect(hpd) gpio interrupt not storming.
At least the 32k configuration has been done for toradex and phytec boards, follow similar model of programming.
[...]
Applied to u-boot/master, thanks!
participants (2)
-
Nishanth Menon -
Tom Rini