[U-Boot] [PATCH 0/8] Update/enhance sbc8548 support
This series represents a significant usability improvement to the sbc8548 board, by delivering:
-64MB SODIMM flash now usable from u-boot -PCI and PCI-e properly configured and functional -twice the size of LBC SDRAM available -easy selection of configuration via Makefile target rules -a README file that sucks less.
I've also cleaned up a bunch of stuff that was left over from when this board support was cloned off of the MPC8548CDS. There are still a couple things I'd like to get working on this board, like DDR config via SPD, and booting from the alternate flash bank (for ease of recovery), but what is here now is validated and complete, so no point in me sitting on these bits.
Patches are in e-mail for review, or can be pulled as per below.
Thanks, Paul.
The following changes since commit 15fba3279b56333bdb65ead366f82c945ed320d1: Kumar Gala (1): ppc/85xx: Disable all async interrupt sources when we boot
are available in the git repository at:
git://openlinux.windriver.com/people/paulg/u-boot sbc8548
Paul Gortmaker (8): sbc8548: delete unused MPC8548CDS info carried over from port sbc8548: get_clock_freq is not valid for this board sbc8548: enable access to second bank of flash sbc8548: correct local bus SDRAM size from 64M to 128M sbc8548: update PCI/PCI-e support code sbc8548: enable use of PCI network cards sbc8548: allow enabling PCI via a make config option sbc8548: replace README with completely new document
MAKEALL | 4 + Makefile | 26 ++++++- board/sbc8548/Makefile | 4 +- board/sbc8548/law.c | 12 +++- board/sbc8548/sbc8548.c | 98 ++++++++---------------- board/sbc8548/tlb.c | 64 ++++++++++----- doc/README.sbc8548 | 189 ++++++++++++++++++++++++++++++++++++++++----- include/configs/sbc8548.h | 114 +++++++++++++++++---------- 8 files changed, 356 insertions(+), 155 deletions(-)
There are a couple defines and PCI bridge quirks related to the PCI backplane of the MPC8548CDS that have no meaning in the context of the port to the sbc8548 board, so delete them.
Also, the form factor of the sbc8548 is a standalone board with a single PCI-X and a single PCI-e slot. That pretty much guarantees that it will never be a PCI agent itself, so the host/agent and root complex/end node distinctions have been removed.
Similarly, since there is no physical connector mapping to PCI2, so all references of PCI2 in the board support files have been removed as well.
Signed-off-by: Paul Gortmaker paul.gortmaker@windriver.com --- board/sbc8548/sbc8548.c | 63 ++++---------------------------------------- include/configs/sbc8548.h | 9 ------ 2 files changed, 6 insertions(+), 66 deletions(-)
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index e5b21b5..f4fd204 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -311,35 +311,9 @@ long int fixed_sdram (void) } #endif
-#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) -/* For some reason the Tundra PCI bridge shows up on itself as a - * different device. Work around that by refusing to configure it. - */ -void dummy_func(struct pci_controller* hose, pci_dev_t dev, struct pci_config_table *tab) { } - -static struct pci_config_table pci_sbc8548_config_table[] = { - {0x10e3, 0x0513, PCI_ANY_ID, 1, 3, PCI_ANY_ID, dummy_func, {0,0,0}}, - {0x1106, 0x0686, PCI_ANY_ID, 1, VIA_ID, 0, mpc85xx_config_via, {0,0,0}}, - {0x1106, 0x0571, PCI_ANY_ID, 1, VIA_ID, 1, - mpc85xx_config_via_usbide, {0,0,0}}, - {0x1105, 0x3038, PCI_ANY_ID, 1, VIA_ID, 2, - mpc85xx_config_via_usb, {0,0,0}}, - {0x1106, 0x3038, PCI_ANY_ID, 1, VIA_ID, 3, - mpc85xx_config_via_usb2, {0,0,0}}, - {0x1106, 0x3058, PCI_ANY_ID, 1, VIA_ID, 5, - mpc85xx_config_via_power, {0,0,0}}, - {0x1106, 0x3068, PCI_ANY_ID, 1, VIA_ID, 6, - mpc85xx_config_via_ac97, {0,0,0}}, - {}, -}; - -static struct pci_controller pci1_hose = { - config_table: pci_sbc8548_config_table}; -#endif /* CONFIG_PCI */ - -#ifdef CONFIG_PCI2 -static struct pci_controller pci2_hose; -#endif /* CONFIG_PCI2 */ +#ifdef CONFIG_PCI1 +static struct pci_controller pci1_hose; +#endif /* CONFIG_PCI1 */
#ifdef CONFIG_PCIE1 static struct pci_controller pcie1_hose; @@ -356,24 +330,20 @@ pci_init_board(void) { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCI1_ADDR; struct pci_controller *hose = &pci1_hose; - struct pci_config_table *table; struct pci_region *r = hose->regions;
uint pci_32 = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_PCI32; /* PORDEVSR[15] */ uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
- uint pci_agent = is_fsl_pci_agent(LAW_TRGT_IF_PCI_1, host_agent); - uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */
if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { - printf (" PCI: %d bit, %s MHz, %s, %s, %s\n", + printf (" PCI host: %d bit, %s MHz, %s, %s\n", (pci_32) ? 32 : 64, (pci_speed == 33333000) ? "33" : (pci_speed == 66666000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", - pci_agent ? "agent" : "host", pci_arb ? "arbiter" : "external-arbiter" );
@@ -392,12 +362,6 @@ pci_init_board(void) PCI_REGION_IO); hose->region_count = r - hose->regions;
- /* relocate config table pointers */ - hose->config_table = \ - (struct pci_config_table *)((uint)hose->config_table + gd->reloc_off); - for (table = hose->config_table; table && table->vendor; table++) - table->config_device += gd->reloc_off; - hose->first_busno=first_free_busno;
fsl_pci_init(hose, (u32)&pci->cfg_addr, (u32)&pci->cfg_data); @@ -422,33 +386,18 @@ pci_init_board(void) gur->devdisr |= MPC85xx_DEVDISR_PCI1; /* disable */ #endif
-#ifdef CONFIG_PCI2 -{ - uint pci2_clk_sel = gur->porpllsr & 0x4000; /* PORPLLSR[17] */ - uint pci_dual = get_pci_dual (); /* PCI DUAL in CM_PCI[3] */ - if (pci_dual) { - printf (" PCI2: 32 bit, 66 MHz, %s\n", - pci2_clk_sel ? "sync" : "async"); - } else { - printf (" PCI2: disabled\n"); - } -} -#else - gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable */ -#endif /* CONFIG_PCI2 */ + gur->devdisr |= MPC85xx_DEVDISR_PCI2; /* disable PCI2 */
#ifdef CONFIG_PCIE1 { volatile ccsr_fsl_pci_t *pci = (ccsr_fsl_pci_t *) CONFIG_SYS_PCIE1_ADDR; struct pci_controller *hose = &pcie1_hose; - int pcie_ep = is_fsl_pci_agent(LAW_TRGT_IF_PCIE_1, host_agent); struct pci_region *r = hose->regions;
int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ - printf ("\n PCIE connected to slot as %s (base address %x)", - pcie_ep ? "End Point" : "Root Complex", + printf ("\n PCIE at base address %x", (uint)pci);
if (pci->pme_msg_det) { diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 838b4db..3d05afb 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -42,7 +42,6 @@ #undef CONFIG_PCI1 /* PCI controller 1 */ #undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ #undef CONFIG_RIO -#undef CONFIG_PCI2 #undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */
#define CONFIG_TSEC_ENET /* tsec ethernet support */ @@ -343,14 +342,6 @@ #define CONFIG_SYS_RIO_MEM_SIZE 0x20000000 /* 512M */ #endif
-#ifdef CONFIG_LEGACY -#define BRIDGE_ID 17 -#define VIA_ID 2 -#else -#define BRIDGE_ID 28 -#define VIA_ID 4 -#endif - #if defined(CONFIG_PCI)
#define CONFIG_NET_MULTI
The get_clock_freq() comes from freescale/common/cadmus.c and is only valid for the CDS based 85xx reference platforms. It would be nice if we could read the 33 vs. 66MHz status somehow, but in the meantime, tie it to CONFIG_SYS_CLK_FREQ like all the other non-CDS boards do.
Signed-off-by: Paul Gortmaker paul.gortmaker@windriver.com --- board/sbc8548/sbc8548.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index f4fd204..3104d37 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -336,13 +336,13 @@ pci_init_board(void) uint pci_arb = gur->pordevsr & MPC85xx_PORDEVSR_PCI1_ARB; /* PORDEVSR[14] */ uint pci_clk_sel = gur->porpllsr & MPC85xx_PORDEVSR_PCI1_SPD; /* PORPLLSR[16] */
- uint pci_speed = get_clock_freq (); /* PCI PSPEED in [4:5] */ + uint pci_speed = CONFIG_SYS_CLK_FREQ; /* get_clock_freq() */
if (!(gur->devdisr & MPC85xx_DEVDISR_PCI1)) { printf (" PCI host: %d bit, %s MHz, %s, %s\n", (pci_32) ? 32 : 64, - (pci_speed == 33333000) ? "33" : - (pci_speed == 66666000) ? "66" : "unknown", + (pci_speed == 33000000) ? "33" : + (pci_speed == 66000000) ? "66" : "unknown", pci_clk_sel ? "sync" : "async", pci_arb ? "arbiter" : "external-arbiter" );
The sbc8548 has a 64MB SODIMM flash module off of CS6 that previously wasn't enumerated by u-boot. There were already BR6/OR6 settings for it [used by cpu_init_f()] but there was no TLB entry and it wasn't in the list of flash banks reported to u-boot.
The location of the 64MB flash is "pulled back" 8MB from a 64MB boundary, in order to allow address space for the 8MB boot flash that is at the end of 32 bit address space. This means creating two 4MB TLB entries for the 8MB chunk, and then expanding the original boot flash entry to 64MB in order to cover the 8MB boot flash and the remainder (56MB) of the user flash.
Signed-off-by: Paul Gortmaker paul.gortmaker@windriver.com --- board/sbc8548/tlb.c | 26 ++++++++++++++++++++++---- include/configs/sbc8548.h | 7 ++++--- 2 files changed, 26 insertions(+), 7 deletions(-)
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index 18d11f6..dbb9ba8 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -42,13 +42,14 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 0, BOOKE_PAGESZ_4K, 0),
/* - * TLB 0: 16M Non-cacheable, guarded - * 0xff800000 16M TLB for 8MB FLASH + * TLB 0: 64M Non-cacheable, guarded + * 0xfc000000 56M 8MB -> 64MB of user flash + * 0xff800000 8M boot FLASH * Out of reset this entry is only 4K. */ - SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x800000, CONFIG_SYS_ALT_FLASH + 0x800000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 0, BOOKE_PAGESZ_16M, 1), + 0, 0, BOOKE_PAGESZ_64M, 1),
/* * TLB 1: 256M Non-cacheable, guarded @@ -103,6 +104,23 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_16M, 1), + + /* + * TLB 7: 4M Non-cacheable, guarded + * 0xfb800000 4M 1st 4MB block of 64MB user FLASH + */ + SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 7, BOOKE_PAGESZ_4M, 1), + + /* + * TLB 8: 4M Non-cacheable, guarded + * 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH + */ + SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, CONFIG_SYS_ALT_FLASH + 0x400000, + MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, + 0, 8, BOOKE_PAGESZ_4M, 1), + };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 3d05afb..8edba20 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -163,6 +163,7 @@ */
#define CONFIG_SYS_BOOT_BLOCK 0xff800000 /* start of 8MB Flash */ +#define CONFIG_SYS_ALT_FLASH 0xfb800000 /* 64MB "user" flash */ #define CONFIG_SYS_FLASH_BASE CONFIG_SYS_BOOT_BLOCK /* start of FLASH 16M */
#define CONFIG_SYS_BR0_PRELIM 0xff800801 @@ -171,9 +172,9 @@ #define CONFIG_SYS_OR0_PRELIM 0xff806e65 #define CONFIG_SYS_OR6_PRELIM 0xf8006e65
-#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE} -#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */ -#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */ +#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_ALT_FLASH} +#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* number of banks */ +#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */ #undef CONFIG_SYS_FLASH_CHECKSUM #define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */
The size of the LB SDRAM on this board is 128MB, spanning CS3 and CS4. It was previously only being configured for 64MB on CS3, since that was what the original codebase of the MPC8548CDS had. In addition to setting up BR4/OR4, this also adds the TLB entry for the second half of the SDRAM.
Signed-off-by: Paul Gortmaker paul.gortmaker@windriver.com --- board/sbc8548/sbc8548.c | 8 +++++++- board/sbc8548/tlb.c | 22 +++++++++++++++------- include/configs/sbc8548.h | 42 ++++++++++++++++++++++++++++++++++++++---- 3 files changed, 60 insertions(+), 12 deletions(-)
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 3104d37..1db32ec 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -152,7 +152,7 @@ local_bus_init(void) void sdram_init(void) { -#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) +#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
uint idx; volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); @@ -172,6 +172,12 @@ sdram_init(void) lbc->br3 = CONFIG_SYS_BR3_PRELIM; asm("msync");
+ lbc->or4 = CONFIG_SYS_OR4_PRELIM; + asm("msync"); + + lbc->br4 = CONFIG_SYS_BR4_PRELIM; + asm("msync"); + lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync");
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index dbb9ba8..e173245 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -88,14 +88,22 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* * TLB 5: 64M Cacheable, non-guarded - * 0xf0000000 64M LBC SDRAM + * 0xf0000000 64M LBC SDRAM First half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 5, BOOKE_PAGESZ_64M, 1),
/* - * TLB 6: 16M Cacheable, non-guarded + * TLB 6: 64M Cacheable, non-guarded + * 0xf4000000 64M LBC SDRAM Second half + */ + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, + MAS3_SX|MAS3_SW|MAS3_SR, 0, + 0, 6, BOOKE_PAGESZ_64M, 1), + + /* + * TLB 7: 16M Cacheable, non-guarded * 0xf8000000 1M 7-segment LED display * 0xf8100000 1M User switches * 0xf8300000 1M Board revision @@ -103,23 +111,23 @@ struct fsl_e_tlb_entry tlb_table[] = { */ SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_16M, 1), + 0, 7, BOOKE_PAGESZ_16M, 1),
/* - * TLB 7: 4M Non-cacheable, guarded + * TLB 8: 4M Non-cacheable, guarded * 0xfb800000 4M 1st 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_4M, 1), + 0, 8, BOOKE_PAGESZ_4M, 1),
/* - * TLB 8: 4M Non-cacheable, guarded + * TLB 9: 4M Non-cacheable, guarded * 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, CONFIG_SYS_ALT_FLASH + 0x400000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_4M, 1), + 0, 9, BOOKE_PAGESZ_4M, 1),
};
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 8edba20..4751013 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -196,13 +196,13 @@ #define CONFIG_SYS_EEPROM_BASE 0xf8b00000
/* - * SDRAM on the Local Bus + * SDRAM on the Local Bus (CS3 and CS4) */ #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ +#define CONFIG_SYS_LBC_SDRAM_SIZE 128 /* LBC SDRAM is 128MB */
/* - * Base Register 3 and Option Register 3 configure SDRAM. + * Base Register 3 and Option Register 3 configure the 1st 1/2 SDRAM. * The SDRAM base address, CONFIG_SYS_LBC_SDRAM_BASE, is 0xf0000000. * * For BR3, need: @@ -220,7 +220,7 @@ #define CONFIG_SYS_BR3_PRELIM 0xf0001861
/* - * The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. * * For OR3, need: * 64MB mask for AM, OR3[0:7] = 1111 1100 @@ -235,6 +235,40 @@
#define CONFIG_SYS_OR3_PRELIM 0xfc006cc0
+/* + * Base Register 4 and Option Register 4 configure the 2nd 1/2 SDRAM. + * The base address, (SDRAM_BASE + 1/2*SIZE), is 0xf4000000. + * + * For BR4, need: + * Base address of 0xf4000000 = BR[0:16] = 1111 0100 0000 0000 0 + * port-size = 32-bits = BR2[19:20] = 11 + * no parity checking = BR2[21:22] = 00 + * SDRAM for MSEL = BR2[24:26] = 011 + * Valid = BR[31] = 1 + * + * 0 4 8 12 16 20 24 28 + * 1111 0000 0000 0000 0001 1000 0110 0001 = f4001861 + * + */ + +#define CONFIG_SYS_BR4_PRELIM 0xf4001861 + +/* + * The SDRAM size in MB, of 1/2 CONFIG_SYS_LBC_SDRAM_SIZE, is 64. + * + * For OR4, need: + * 64MB mask for AM, OR3[0:7] = 1111 1100 + * XAM, OR3[17:18] = 11 + * 10 columns OR3[19-21] = 011 + * 12 rows OR3[23-25] = 011 + * EAD set for extra time OR[31] = 0 + * + * 0 4 8 12 16 20 24 28 + * 1111 1100 0000 0000 0110 1100 1100 0000 = fc006cc0 + */ + +#define CONFIG_SYS_OR4_PRELIM 0xfc006cc0 + #define CONFIG_SYS_LBC_LCRR 0x00000002 /* LB clock ratio reg */ #define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */ #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
The PCI/PCI-e support for the sbc8548 was based on an earlier version of what the MPC8548CDS board was using, and in its current state it won't even compile. This re-syncs it to match current MPC85xxCDS/MDS PCI-e support.
It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O back to 0xe280_0000 (where PCI2 would be on MPC8548CDS), and similarly it coalesces the PCI and PCI-e mem into one single TLB.
Both PCI-x and PCI-e have been tested with intel e1000 cards under linux (with an accompanying dts change in place)
Signed-off-by: Paul Gortmaker paul.gortmaker@windriver.com --- board/sbc8548/law.c | 12 +++++++++- board/sbc8548/sbc8548.c | 9 ++++--- board/sbc8548/tlb.c | 48 +++++++++++++++++++------------------------- include/configs/sbc8548.h | 43 +++++++++++++++++++++------------------ 4 files changed, 59 insertions(+), 53 deletions(-)
diff --git a/board/sbc8548/law.c b/board/sbc8548/law.c index e8c7ae2..6d1efc0 100644 --- a/board/sbc8548/law.c +++ b/board/sbc8548/law.c @@ -32,8 +32,10 @@ * * 0x0000_0000 0x0fff_ffff DDR 256M * 0x8000_0000 0x9fff_ffff PCI1 MEM 512M + * 0xa000_0000 0xbfff_ffff PCIe MEM 512M * 0xe000_0000 0xe000_ffff CCSR 1M - * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M + * 0xe200_0000 0xe27f_ffff PCI1 IO 8M + * 0xe280_0000 0xe2ff_ffff PCIe IO 8M * 0xf000_0000 0xf7ff_ffff SDRAM 128M * 0xf8b0_0000 0xf80f_ffff EEPROM 1M * 0xfb80_0000 0xff7f_ffff FLASH (2nd bank) 64M @@ -48,8 +50,14 @@ struct law_entry law_table[] = { #ifndef CONFIG_SPD_EEPROM SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif +#ifdef CONFIG_SYS_PCI1_MEM_PHYS SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), + SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCI), +#endif +#ifdef CONFIG_SYS_PCIE1_MEM_PHYS + SET_LAW(CONFIG_SYS_PCIE1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCIE_1), + SET_LAW(CONFIG_SYS_PCIE1_IO_PHYS, LAW_SIZE_8M, LAW_TRGT_IF_PCIE_1), +#endif /* LBC window - maps 256M 0xf0000000 -> 0xffffffff */ SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), }; diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 1db32ec..0387140 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -355,14 +355,14 @@ pci_init_board(void)
/* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCI1_MEM_BASE, + CONFIG_SYS_PCI1_MEM_BUS, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_SIZE, PCI_REGION_MEM);
/* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCI1_IO_BASE, + CONFIG_SYS_PCI1_IO_BUS, CONFIG_SYS_PCI1_IO_PHYS, CONFIG_SYS_PCI1_IO_SIZE, PCI_REGION_IO); @@ -400,6 +400,7 @@ pci_init_board(void) struct pci_controller *hose = &pcie1_hose; struct pci_region *r = hose->regions;
+ uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19; int pcie_configured = is_fsl_pci_cfg(LAW_TRGT_IF_PCIE_1, io_sel);
if (pcie_configured && !(gur->devdisr & MPC85xx_DEVDISR_PCIE)){ @@ -414,14 +415,14 @@ pci_init_board(void)
/* outbound memory */ pci_set_region(r++, - CONFIG_SYS_PCIE1_MEM_BASE, + CONFIG_SYS_PCIE1_MEM_BUS, CONFIG_SYS_PCIE1_MEM_PHYS, CONFIG_SYS_PCIE1_MEM_SIZE, PCI_REGION_MEM);
/* outbound io */ pci_set_region(r++, - CONFIG_SYS_PCIE1_IO_BASE, + CONFIG_SYS_PCIE1_IO_BUS, CONFIG_SYS_PCIE1_IO_PHYS, CONFIG_SYS_PCIE1_IO_SIZE, PCI_REGION_IO); diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index e173245..dab0eb1 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -52,58 +52,52 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 0, BOOKE_PAGESZ_64M, 1),
/* - * TLB 1: 256M Non-cacheable, guarded - * 0x80000000 256M PCI1 MEM First half + * TLB 1: 1G Non-cacheable, guarded + * 0x80000000 512M PCI1 MEM + * 0xa0000000 512M PCIe MEM */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS, CONFIG_SYS_PCI1_MEM_PHYS, + SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_VIRT, CONFIG_SYS_PCI1_MEM_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 1, BOOKE_PAGESZ_256M, 1), + 0, 1, BOOKE_PAGESZ_1G, 1),
/* - * TLB 2: 256M Non-cacheable, guarded - * 0x90000000 256M PCI1 MEM Second half - */ - SET_TLB_ENTRY(1, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, CONFIG_SYS_PCI1_MEM_PHYS + 0x10000000, - MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 2, BOOKE_PAGESZ_256M, 1), - - /* - * TLB 3: 256M Cacheable, non-guarded + * TLB 2: 256M Cacheable, non-guarded * 0x0 256M DDR SDRAM */ #if !defined(CONFIG_SPD_EEPROM) SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 3, BOOKE_PAGESZ_256M, 1), + 0, 2, BOOKE_PAGESZ_256M, 1), #endif
/* - * TLB 4: 64M Non-cacheable, guarded + * TLB 3: 64M Non-cacheable, guarded * 0xe0000000 1M CCSRBAR - * 0xe2000000 16M PCI1 IO + * 0xe2000000 8M PCI1 IO + * 0xe2800000 8M PCIe IO */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 4, BOOKE_PAGESZ_64M, 1), + 0, 3, BOOKE_PAGESZ_64M, 1),
/* - * TLB 5: 64M Cacheable, non-guarded + * TLB 4: 64M Cacheable, non-guarded * 0xf0000000 64M LBC SDRAM First half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 5, BOOKE_PAGESZ_64M, 1), + 0, 4, BOOKE_PAGESZ_64M, 1),
/* - * TLB 6: 64M Cacheable, non-guarded + * TLB 5: 64M Cacheable, non-guarded * 0xf4000000 64M LBC SDRAM Second half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 6, BOOKE_PAGESZ_64M, 1), + 0, 5, BOOKE_PAGESZ_64M, 1),
/* - * TLB 7: 16M Cacheable, non-guarded + * TLB 6: 16M Cacheable, non-guarded * 0xf8000000 1M 7-segment LED display * 0xf8100000 1M User switches * 0xf8300000 1M Board revision @@ -111,23 +105,23 @@ struct fsl_e_tlb_entry tlb_table[] = { */ SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_16M, 1), + 0, 6, BOOKE_PAGESZ_16M, 1),
/* - * TLB 8: 4M Non-cacheable, guarded + * TLB 7: 4M Non-cacheable, guarded * 0xfb800000 4M 1st 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_4M, 1), + 0, 7, BOOKE_PAGESZ_4M, 1),
/* - * TLB 9: 4M Non-cacheable, guarded + * TLB 8: 4M Non-cacheable, guarded * 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, CONFIG_SYS_ALT_FLASH + 0x400000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 9, BOOKE_PAGESZ_4M, 1), + 0, 8, BOOKE_PAGESZ_4M, 1),
};
diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 4751013..e77e9e9 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -42,7 +42,14 @@ #undef CONFIG_PCI1 /* PCI controller 1 */ #undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ #undef CONFIG_RIO -#undef CONFIG_FSL_PCI_INIT /* Use common FSL init code */ + +#ifdef CONFIG_PCI +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */ +#endif +#ifdef CONFIG_PCIE1 +#define CONFIG_FSL_PCIE_RESET 1 /* need PCIe reset errata */ +#endif
#define CONFIG_TSEC_ENET /* tsec ethernet support */ #define CONFIG_ENV_OVERWRITE @@ -342,31 +349,27 @@ * General PCI * Memory space is mapped 1-1, but I/O space must start from 0. */ +#define CONFIG_SYS_PCI_VIRT 0x80000000 /* 1G PCI TLB */ #define CONFIG_SYS_PCI_PHYS 0x80000000 /* 1G PCI TLB */
-#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 -#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE +#define CONFIG_SYS_PCI1_MEM_VIRT 0x80000000 +#define CONFIG_SYS_PCI1_MEM_BUS 0x80000000 +#define CONFIG_SYS_PCI1_MEM_PHYS 0x80000000 #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 -#define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */ - -#ifdef CONFIG_PCI2 -#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE -#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCI2_IO_BASE 0x00000000 -#define CONFIG_SYS_PCI2_IO_PHYS 0xe2800000 -#define CONFIG_SYS_PCI2_IO_SIZE 0x00100000 /* 1M */ -#endif +#define CONFIG_SYS_PCI1_IO_VIRT 0xe2000000 +#define CONFIG_SYS_PCI1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 +#define CONFIG_SYS_PCI1_IO_SIZE 0x00800000 /* 8M */
#ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_MEM_BASE 0xa0000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS CONFIG_SYS_PCIE1_MEM_BASE +#define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE1_IO_BASE 0x00000000 -#define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ +#define CONFIG_SYS_PCIE1_IO_VIRT 0xe2800000 +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_PHYS 0xe2800000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00800000 /* 8M */ #endif
#ifdef CONFIG_RIO
Create a board_eth_init to allow a place to hook in the PCI ethernet init after all the eTSEC are up and configured.
Signed-off-by: Paul Gortmaker paul.gortmaker@windriver.com --- board/sbc8548/sbc8548.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-)
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 0387140..c4dc5c5 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -32,6 +32,8 @@ #include <asm/fsl_pci.h> #include <asm/fsl_ddr_sdram.h> #include <spd_sdram.h> +#include <netdev.h> +#include <tsec.h> #include <miiphy.h> #include <libfdt.h> #include <fdt_support.h> @@ -446,6 +448,13 @@ pci_init_board(void)
}
+int board_eth_init(bd_t *bis) +{ + tsec_standard_init(bis); + pci_eth_init(bis); + return 0; /* otherwise cpu_eth_init gets run */ +} + int last_stage_init(void) { return 0;
Prior to this commit, to enable PCI, you had to go manually edit the board config header, and if you had 33MHz PCI, you had to manually change CONFIG_SYS_NS16550_CLK too, which was not real user friendly,
This adds the typical PCI and clock speed make targets to the toplevel Makefile in accordance with what is being done with other boards.
Signed-off-by: Paul Gortmaker paul.gortmaker@windriver.com --- MAKEALL | 4 ++++ Makefile | 26 ++++++++++++++++++++++++-- include/configs/sbc8548.h | 13 ++++++++----- 3 files changed, 36 insertions(+), 7 deletions(-)
diff --git a/MAKEALL b/MAKEALL index 1d50c34..b394adb 100755 --- a/MAKEALL +++ b/MAKEALL @@ -399,6 +399,10 @@ LIST_85xx=" \ PM856 \ sbc8540 \ sbc8548 \ + sbc8548_PCI_33 \ + sbc8548_PCI_66 \ + sbc8548_PCI_33_PCIE \ + sbc8548_PCI_66_PCIE \ sbc8560 \ socrates \ stxgp3 \ diff --git a/Makefile b/Makefile index 0b61d05..28b20af 100644 --- a/Makefile +++ b/Makefile @@ -2570,8 +2570,30 @@ sbc8540_66_config: unconfig fi @$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560
-sbc8548_config: unconfig - @$(MKCONFIG) $(@:_config=) ppc mpc85xx sbc8548 +sbc8548_config \ +sbc8548_PCI_33_config \ +sbc8548_PCI_66_config \ +sbc8548_PCI_33_PCIE_config \ +sbc8548_PCI_66_PCIE_config: unconfig + @mkdir -p $(obj)include + @if [ "$(findstring _PCI_,$@)" ] ; then \ + $(XECHO) -n "... PCI HOST at " ; \ + echo "#define CONFIG_PCI" >>$(obj)include/config.h ; \ + echo "#define CONFIG_PCI1" >>$(obj)include/config.h ; \ + fi ; \ + if [ "$(findstring _33_,$@)" ] ; then \ + $(XECHO) -n "33MHz ..." ; \ + echo "#define CONFIG_SYS_CLK_DIV 2" >>$(obj)include/config.h ; \ + fi ; \ + if [ "$(findstring _66_,$@)" ] ; then \ + $(XECHO) -n "66MHz...." ; \ + echo "#define CONFIG_SYS_CLK_DIV 1" >>$(obj)include/config.h ; \ + fi ; \ + if [ "$(findstring _PCIE_,$@)" ] ; then \ + $(XECHO) -n " with PCI-e ... " ; \ + echo "#define CONFIG_PCIE1" >>$(obj)include/config.h ; \ + fi + @$(MKCONFIG) -a sbc8548 ppc mpc85xx sbc8548
sbc8560_config \ sbc8560_33_config \ diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index e77e9e9..8eb5b4c 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -38,9 +38,6 @@ #define CONFIG_MPC8548 1 /* MPC8548 specific */ #define CONFIG_SBC8548 1 /* SBC8548 board specific */
-#undef CONFIG_PCI /* enable any pci type devices */ -#undef CONFIG_PCI1 /* PCI controller 1 */ -#undef CONFIG_PCIE1 /* PCIE controler 1 (slot 1) */ #undef CONFIG_RIO
#ifdef CONFIG_PCI @@ -58,7 +55,13 @@
#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
-#define CONFIG_SYS_CLK_FREQ 66000000 /* SBC8548 default SYSCLK */ +/* + * Below assumes that CCB:SYSCLK remains unchanged at 6:1 via SW2:[1-4] + */ +#ifndef CONFIG_SYS_CLK_DIV +#define CONFIG_SYS_CLK_DIV 1 /* 2, if 33MHz PCI card installed */ +#endif +#define CONFIG_SYS_CLK_FREQ (66000000 / CONFIG_SYS_CLK_DIV)
/* * These can be toggled for performance analysis, otherwise use default. @@ -315,7 +318,7 @@ #define CONFIG_SYS_NS16550 #define CONFIG_SYS_NS16550_SERIAL #define CONFIG_SYS_NS16550_REG_SIZE 1 -#define CONFIG_SYS_NS16550_CLK 400000000 /* get_bus_freq(0) */ +#define CONFIG_SYS_NS16550_CLK (400000000 / CONFIG_SYS_CLK_DIV)
#define CONFIG_SYS_BAUDRATE_TABLE \ {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200}
The previous README.sbc8548 was pretty much content-free. Replace it with something that actually gives the end user some relevant hardware details, and also lists the u-boot configuration choices.
Also in the cosmetic department, fix the bogus line in the Makefile that was carried over from the SBC8560 Makefile, and the typo in the sbc8548.c copyright.
Signed-off-by: Paul Gortmaker paul.gortmaker@windriver.com --- board/sbc8548/Makefile | 4 +- board/sbc8548/sbc8548.c | 3 +- doc/README.sbc8548 | 189 ++++++++++++++++++++++++++++++++++++++++++----- 3 files changed, 173 insertions(+), 23 deletions(-)
diff --git a/board/sbc8548/Makefile b/board/sbc8548/Makefile index 9919a6e..09e5c2e 100644 --- a/board/sbc8548/Makefile +++ b/board/sbc8548/Makefile @@ -2,8 +2,8 @@ # (C) Copyright 2004-2006 # Wolfgang Denk, DENX Software Engineering, wd@denx.de. # -# (C) Copyright 2004 Wind River Systems Inc <www.windriver.com>. -# Added support for Wind River SBC8560 board +# (C) Copyright 2007 Wind River Systems Inc <www.windriver.com>. +# Added support for Wind River SBC8548 board # # See file CREDITS for list of people who contributed to this # project. diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index c4dc5c5..2978884 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -1,5 +1,6 @@ /* - * Copyright 2007 Wind River Systemes, Inc. <www.windriver.com> + * Copyright 2007,2009 Wind River Systems, Inc. <www.windriver.com> + * * Copyright 2007 Embedded Specialties, Inc. * * Copyright 2004, 2007 Freescale Semiconductor. diff --git a/doc/README.sbc8548 b/doc/README.sbc8548 index b34d040..d72d97d 100644 --- a/doc/README.sbc8548 +++ b/doc/README.sbc8548 @@ -1,27 +1,176 @@ -Wind River SBC8548 reference board -=========================== +Intro: +======
-Copyright 2007, Embedded Specialties, Inc. -Copyright 2007 Wind River Systemes, Inc. ------------------------------ +The SBC8548 is a stand alone single board computer with a 1GHz +MPC8548 CPU, 8MB boot flash, 64MB user flash and, 256MB DDR2 400MHz +memory. It also has 128MB SDRAM 100MHz LBC memory, with both a PCI-e, +and a PCI-X slot, dual mini-DB9 for UART, and dual RJ-45 for eTSEC +ethernet connections.
-1. Building U-Boot ------------------- -The SBC8548 code is known to build using ELDK 4.1. +U-boot Configuration: +=====================
- $ make sbc8548_config - Configuring for sbc8548 board... +The following possible u-boot configuration targets are available:
- $ make + 1) sbc8548_config + 2) sbc8548_PCI_33_config + 3) sbc8548_PCI_66_config + 4) sbc8548_PCI_33_PCIE_config + 5) sbc8548_PCI_66_PCIE_config
+Generally speaking, most people should choose to use #5. Details +of each choice are listed below.
-2. Switch and Jumper Settings ------------------------------ -All Jumpers & Switches are in their default positions. Please refer to -the board documentation for details. Some settings control CPU voltages -and settings may change with board revisions. +Choice #1 does not enable CONFIG_PCI, and assumes that the PCI slot +will be left empty (M66EN high), and so the board will operate with +a base clock of 66MHz. Note that you need both PCI enabled in u-boot +and linux in order to have functional PCI under linux.
-3. Known limitations --------------------- -PCI: - The code to support PCI is currently disabled and has not been verified. +The second enables PCI support and builds for a 33MHz clock rate. Note +that if a 33MHz 32bit card is inserted in the slot, then the whole board +will clock down to a 33MHz base clock instead of the default 66MHz. This +will change the baud clocks and mess up your serial console output if you +were previously running at 66MHz. If you want to use a 33MHz PCI card, +then you should build a U-Boot with a _PCI_33_ config and store this +to flash prior to powering down the board and inserting the 33MHz PCI +card. [The above discussion assumes that the SW2[1-4] has not been changed +to reflect a different CCB:SYSCLK ratio] + +The third option builds PCI support in, and leaves the clocking at the +default 66MHz. Options four and five are just repeats of option two +and three, but with PCI-e support enabled as well. + +PCI output listing with an intel e1000 PCI-x and a Syskonnect SK-9Exx +is shown below for sbc8548_PCI_66_PCIE_config. (Note that PCI-e with +a 33MHz PCI configuration is currently untested.) + + => pci 0 + Scanning PCI devices on bus 0 + BusDevFun VendorId DeviceId Device Class Sub-Class + _____________________________________________________________ + 00.00.00 0x1057 0x0012 Processor 0x20 + 00.01.00 0x8086 0x1026 Network controller 0x00 + => pci 1 + Scanning PCI devices on bus 1 + BusDevFun VendorId DeviceId Device Class Sub-Class + _____________________________________________________________ + 01.00.00 0x1957 0x0012 Processor 0x20 + => pci 2 + Scanning PCI devices on bus 2 + BusDevFun VendorId DeviceId Device Class Sub-Class + _____________________________________________________________ + 02.00.00 0x1148 0x9e00 Network controller 0x00 + => + + +Hardware Reference: +=================== + +The following contains some summary information on hardware settings +that are relevant to u-boot, based on the board manual. For the +most up to date and complete details of the board, please request the +reference manual ERG-00327-001.pdf from www.windriver.com + +Boot flash: + intel V28F640Jx, 8192x8 (one device) at 0xff80_0000 + +Sodimm flash: + intel V28F128Jx, 16384x8 (4 devices) at 0xfb80_0000 + + + Jumpers: + +Jumper Name ON OFF +---------------------------------------------------------------- +JP12 CS0/CS6 swap see note[*] see note[*] + +JP13 SODIMM flash write OK writes disabled + write prot. + +JP14 HRESET/TRST joined isolated + +JP15 PWR ON when AC pwr use S1 for on/off + +JP16 Demo LEDs lit not lit + +JP19 PCI mode PCI PCI-X + + +[*]JP12, when jumpered parallel to the SODIMM, puts the boot flash +onto /CS0 and the SODIMM flash on /CS6 (default). When JP12 +is jumpered parallel to the LBC-SDRAM, then /CS0 is for the +SODIMM flash and /CS6 is for the boot flash. Note that in this +alternate setting, you also need to switch SW2.8 to ON. Currently +u-boot doesn't support booting off the SODIMM in this alternate +setting without manually altering BR0/OR0 and BR6/OR6 in the +board config file appropriately. + + + Switches: + +The defaults are marked with a * + +Name Desc. ON OFF +------------------------------------------------------------------ +S1 Pwr toggle n/a n/a + +SW2.1 CFG_SYS_PLL0 1 0* +SW2.2 CFG_SYS_PLL1 1* 0 +SW2.3 CFG_SYS_PLL2 1* 0 +SW2.4 CFG_SYS_PLL3 1 0* +SW2.5 CFG_CORE_PLL0 1* 0 +SW2.6 CFG_CORE_PLL1 1 0* +SW2.7 CFG_CORE_PLL2 1* 0 +SW2.8 CFG_ROM_LOC1 1 0* + +SW3.1 CFG_HOST_AGT0 1* 0 +SW3.2 CFG_HOST_AGT1 1* 0 +SW3.3 CFG_HOST_AGT2 1* 0 +SW3.4 CFG_IO_PORTS0 1* 0 +SW3.5 CFG_IO_PORTS0 1 0* +SW3.6 CFG_IO_PORTS0 1 0* + +SerDes CLK(MHz) SW5.1 SW5.2 +---------------------------------------------- +25 0 0 +100* 1 0 +125 0 1 +200 1 1 + +SerDes CLK spread SW5.3 SW5.4 +---------------------------------------------- ++/- 0.25% 0 0 +-0.50% 1 0 +-0.75% 0 1 +No Spread* 1 1 + +SW4 settings are readable from the EPLD and are currently not used for +any hardware settings (i.e. user configuration switches). + + LEDs: + +Name Desc. ON OFF +------------------------------------------------------------------ +D13 PCI/PCI-X PCI-X PCI +D14 3.3V PWR 3.3V no power +D15 SYSCLK 66MHz 33MHz + + + Default Memory Map: + +start end CS<n> width Desc. +---------------------------------------------------------------------- +0000_0000 0fff_ffff MCS0,1 64 DDR2 (256MB) +f000_0000 f7ff_ffff CS3,4 32 LB SDRAM (128MB) +f800_0000 f8b0_1fff CS5 - EPLD +fb80_0000 ff7f_ffff CS6 32 SODIMM flash (64MB) +ff80_0000 ffff_ffff CS0 8 Boot flash (8MB) + +The EPLD on CS5 demuxes the following devices at the following offsets: + +offset size width device +-------------------------------------------------------- +0 1fff 8 7 segment display LED +10_0000 1fff 4 user switches +30_0000 1fff 4 HW Rev. register +b0_0000 1fff 8 8kB EEPROM
On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote:
The previous README.sbc8548 was pretty much content-free. Replace it with something that actually gives the end user some relevant hardware details, and also lists the u-boot configuration choices.
Also in the cosmetic department, fix the bogus line in the Makefile that was carried over from the SBC8560 Makefile, and the typo in the sbc8548.c copyright.
Signed-off-by: Paul Gortmaker paul.gortmaker@windriver.com
board/sbc8548/Makefile | 4 +- board/sbc8548/sbc8548.c | 3 +- doc/README.sbc8548 | 189 ++++++++++++++++++++++++++++++++++++++ ++++----- 3 files changed, 173 insertions(+), 23 deletions(-)
applied to 85xx.
- k
On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote:
Prior to this commit, to enable PCI, you had to go manually edit the board config header, and if you had 33MHz PCI, you had to manually change CONFIG_SYS_NS16550_CLK too, which was not real user friendly,
This adds the typical PCI and clock speed make targets to the toplevel Makefile in accordance with what is being done with other boards.
Signed-off-by: Paul Gortmaker paul.gortmaker@windriver.com
MAKEALL | 4 ++++ Makefile | 26 ++++++++++++++++++++++++-- include/configs/sbc8548.h | 13 ++++++++----- 3 files changed, 36 insertions(+), 7 deletions(-)
diff --git a/MAKEALL b/MAKEALL index 1d50c34..b394adb 100755 --- a/MAKEALL +++ b/MAKEALL @@ -399,6 +399,10 @@ LIST_85xx=" \ PM856 \ sbc8540 \ sbc8548 \
- sbc8548_PCI_33 \
- sbc8548_PCI_66 \
- sbc8548_PCI_33_PCIE \
- sbc8548_PCI_66_PCIE \ sbc8560 \ socrates \ stxgp3 \
diff --git a/Makefile b/Makefile index 0b61d05..28b20af 100644 --- a/Makefile +++ b/Makefile @@ -2570,8 +2570,30 @@ sbc8540_66_config: unconfig fi @$(MKCONFIG) -a SBC8540 ppc mpc85xx sbc8560
-sbc8548_config: unconfig
- @$(MKCONFIG) $(@:_config=) ppc mpc85xx sbc8548
+sbc8548_config \ +sbc8548_PCI_33_config \ +sbc8548_PCI_66_config \ +sbc8548_PCI_33_PCIE_config \ +sbc8548_PCI_66_PCIE_config: unconfig
- @mkdir -p $(obj)include
Use the new -t option to mkconfig:
commit 804d83a563c47b55e1f14f5de3b6e9d7e2a7ef5e Author: Wolfgang Denk wd@denx.de Date: Tue Sep 15 22:12:31 2009 +0200
mkconfig: split the board make target to multiple config targets
To simplify the top level makefile it useful to be able to parse the top level makefile target to multiple individual target, then put them to the config.h, leave the board config file to handle the different targets.
Note that this method uses the '_'(underline) as the delimiter when splits the board make target.
Signed-off-by: Mingkai Hu Mingkai.hu@freescale.com
This also reverts commit 511c02f611cb5afa1b8ca5980caaaabaa0de377f.
Signed-off-by: Wolfgang Denk wd@denx.de
- k
On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote:
Create a board_eth_init to allow a place to hook in the PCI ethernet init after all the eTSEC are up and configured.
Signed-off-by: Paul Gortmaker paul.gortmaker@windriver.com
board/sbc8548/sbc8548.c | 9 +++++++++ 1 files changed, 9 insertions(+), 0 deletions(-)
applied to 85xx.
- k
Dear Paul Gortmaker,
In message 7d1e5723fdd2d2e1cf51559f876edf17ae8e7a46.1253315004.git.paul.gortmaker@windriver.com you wrote:
The PCI/PCI-e support for the sbc8548 was based on an earlier version of what the MPC8548CDS board was using, and in its current state it won't even compile. This re-syncs it to match current MPC85xxCDS/MDS PCI-e support.
It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O back to 0xe280_0000 (where PCI2 would be on MPC8548CDS), and similarly it coalesces the PCI and PCI-e mem into one single TLB.
Both PCI-x and PCI-e have been tested with intel e1000 cards under linux (with an accompanying dts change in place)
...
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 1db32ec..0387140 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c
...
@@ -400,6 +400,7 @@ pci_init_board(void) struct pci_controller *hose = &pcie1_hose; struct pci_region *r = hose->regions;
- uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
Please use I/O accessors. Check globally, please.
Best regards,
Wolfgang Denk
Wolfgang Denk wrote:
Dear Paul Gortmaker,
In message 7d1e5723fdd2d2e1cf51559f876edf17ae8e7a46.1253315004.git.paul.gortmaker@windriver.com you wrote:
The PCI/PCI-e support for the sbc8548 was based on an earlier version of what the MPC8548CDS board was using, and in its current state it won't even compile. This re-syncs it to match current MPC85xxCDS/MDS PCI-e support.
It borrows from the MPC8568MDS, in that it pulls the PCI-e I/O back to 0xe280_0000 (where PCI2 would be on MPC8548CDS), and similarly it coalesces the PCI and PCI-e mem into one single TLB.
Both PCI-x and PCI-e have been tested with intel e1000 cards under linux (with an accompanying dts change in place)
...
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 1db32ec..0387140 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c
...
@@ -400,6 +400,7 @@ pci_init_board(void) struct pci_controller *hose = &pcie1_hose; struct pci_region *r = hose->regions;
- uint io_sel = (gur->pordevsr & MPC85xx_PORDEVSR_IO_SEL) >> 19;
Please use I/O accessors. Check globally, please.
Already done - commit 48539e37c38c4f6ff78aba6134de2ae3cc3b5dab in the 85xx tree does a global sweep of the board file, and commit ac2cb674bd5dd1405ea0413adb71c253481d9a00 (also in 85xx) is an updated version of this commit that uses the I/O accessors, and also the new PCI helper functions that Kumar requested.
Thanks, Paul.
Best regards,
Wolfgang Denk
On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote:
The size of the LB SDRAM on this board is 128MB, spanning CS3 and CS4. It was previously only being configured for 64MB on CS3, since that was what the original codebase of the MPC8548CDS had. In addition to setting up BR4/OR4, this also adds the TLB entry for the second half of the SDRAM.
Signed-off-by: Paul Gortmaker paul.gortmaker@windriver.com
board/sbc8548/sbc8548.c | 8 +++++++- board/sbc8548/tlb.c | 22 +++++++++++++++------- include/configs/sbc8548.h | 42 ++++++++++++++++++++++++++++++++++++ ++---- 3 files changed, 60 insertions(+), 12 deletions(-)
diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 3104d37..1db32ec 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -152,7 +152,7 @@ local_bus_init(void) void sdram_init(void) { -#if defined(CONFIG_SYS_OR3_PRELIM) && defined(CONFIG_SYS_BR3_PRELIM) +#if defined(CONFIG_SYS_LBC_SDRAM_SIZE)
uint idx; volatile ccsr_lbc_t *lbc = (void *)(CONFIG_SYS_MPC85xx_LBC_ADDR); @@ -172,6 +172,12 @@ sdram_init(void) lbc->br3 = CONFIG_SYS_BR3_PRELIM; asm("msync");
- lbc->or4 = CONFIG_SYS_OR4_PRELIM;
- asm("msync");
- lbc->br4 = CONFIG_SYS_BR4_PRELIM;
- asm("msync");
- lbc->lbcr = CONFIG_SYS_LBC_LBCR; asm("msync");
it would be nice to move this to using IO accessors (out_be32)
- k
Dear Kumar Gala,
In message 96E0CBB9-5B6C-40EE-B6BD-703B3D8CCB0E@kernel.crashing.org you wrote:
On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote:
...
it would be nice to move this to using IO accessors (out_be32)
Not only nice, but necessary. Thanks for catching this.
Best regards,
Wolfgang Denk
Dear Paul Gortmaker,
In message 8c4c3a2e238ee8ef67637f499cc3269acbb1bf00.1253315004.git.paul.gortmaker@windriver.com you wrote:
The size of the LB SDRAM on this board is 128MB, spanning CS3 and CS4. It was previously only being configured for 64MB on CS3, since that was what the original codebase of the MPC8548CDS had. In addition to setting up BR4/OR4, this also adds the TLB entry for the second half of the SDRAM.
...
* TLB 6: 64M Cacheable, non-guarded* 0xf4000000 64M LBC SDRAM Second half*/- SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000,
Line too long. Please check globally.
...
SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, CONFIG_SYS_ALT_FLASH + 0x400000,
Please also fix this one, while you are there.
Best regards,
Wolfgang Denk
On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote:
The sbc8548 has a 64MB SODIMM flash module off of CS6 that previously wasn't enumerated by u-boot. There were already BR6/OR6 settings for it [used by cpu_init_f()] but there was no TLB entry and it wasn't in the list of flash banks reported to u-boot.
The location of the 64MB flash is "pulled back" 8MB from a 64MB boundary, in order to allow address space for the 8MB boot flash that is at the end of 32 bit address space. This means creating two 4MB TLB entries for the 8MB chunk, and then expanding the original boot flash entry to 64MB in order to cover the 8MB boot flash and the remainder (56MB) of the user flash.
Signed-off-by: Paul Gortmaker paul.gortmaker@windriver.com
board/sbc8548/tlb.c | 26 ++++++++++++++++++++++---- include/configs/sbc8548.h | 7 ++++--- 2 files changed, 26 insertions(+), 7 deletions(-)
applied to 85xx.
- k
Dear Kumar Gala,
In message 47177DAB-3638-4978-BD72-78629ADCD9EA@kernel.crashing.org you wrote:
On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote:
...
applied to 85xx.
Argh... So how much time do you allow for code reviews?
I ask you to wait at least 3...5 working days, please.
Please undo, this needs fixing.
Best regards,
Wolfgang Denk
Wolfgang Denk wrote:
Dear Kumar Gala,
In message 47177DAB-3638-4978-BD72-78629ADCD9EA@kernel.crashing.org you wrote:
On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote:
...
applied to 85xx.
Argh... So how much time do you allow for code reviews?
I ask you to wait at least 3...5 working days, please.
Please undo, this needs fixing.
I'd considered the line length, but there were many lines in tlb.c that were already way past 80 char (see directly under the comment /* TLB 0 - for temp stack in cache */ ) so I decided to be consistent with existing code.
If you prefer, I can create an add-on patch that re-wraps both the old/existing code, and the updated line(s).
Let me know what you would prefer.
Paul.
Best regards,
Wolfgang Denk
Dear Paul Gortmaker,
In message 4ABA81DA.8020007@windriver.com you wrote:
I'd considered the line length, but there were many lines in tlb.c that were already way past 80 char (see directly under the comment /* TLB 0 - for temp stack in cache */ ) so I decided to be consistent with existing code.
I see.
If you prefer, I can create an add-on patch that re-wraps both the old/existing code, and the updated line(s).
It would be better to fix the existing code in an initial patch, and then apply an update patch.
Best regards,
Wolfgang Denk
[Re: [U-Boot] [PATCH 3/8] sbc8548: enable access to second bank of flash] On 23/09/2009 (Wed 22:48) Wolfgang Denk wrote:
Dear Paul Gortmaker,
In message 4ABA81DA.8020007@windriver.com you wrote:
I'd considered the line length, but there were many lines in tlb.c that were already way past 80 char (see directly under the comment /* TLB 0 - for temp stack in cache */ ) so I decided to be consistent with existing code.
I see.
If you prefer, I can create an add-on patch that re-wraps both the old/existing code, and the updated line(s).
It would be better to fix the existing code in an initial patch, and then apply an update patch.
To do this, I've rewound my copy of the 85xx repo to just before the 1st offending patch, inserted the cosmetic line wrap patch, and then re-applied all the remaining 85xx updates that I was responsible for.
The patches are all unchanged, with the exception of re-wrapping any long lines in tlb.c -- which impacted the patches marked with a "*"
I hope this what you had in mind. If not, or if you want patches in e-mail then let me know.
Thanks, Paul.
---
The following changes since commit 80f0cc6009a7bfdbb1458fcd50c4592badd33f83: Paul Gortmaker (1): sbc8548: get_clock_freq is not valid for this board
are available in the git repository at:
git://openlinux.windriver.com/people/paulg/u-boot wd-sbc8548
Paul Gortmaker (9): sbc8548: cosmetic line re-wrap * sbc8548: enable access to second bank of flash sbc8548: remove eTSEC3/4 voltage hack sbc8548: use I/O accessors * sbc8548: correct local bus SDRAM size from 64M to 128M fsl_pci: create a SET_STD_PCI_INFO() helper wrapper * sbc8548: update PCI/PCI-e support code sbc8548: allow enabling PCI via a make config option sbc85x0: tidy up Makefile to use new configuration script.
MAKEALL | 4 + Makefile | 26 ++---- board/sbc8548/law.c | 12 ++- board/sbc8548/sbc8548.c | 234 +++++++++++++++++--------------------------- board/sbc8548/tlb.c | 80 ++++++++++----- include/asm-ppc/fsl_pci.h | 12 +++ include/configs/SBC8540.h | 19 ++-- include/configs/sbc8548.h | 137 +++++++++++++++++++------- include/configs/sbc8560.h | 17 +++- 9 files changed, 300 insertions(+), 241 deletions(-)
Dear Paul Gortmaker,
In message 918ca661b391ce156f39e6c8a086ea93d845caea.1253315004.git.paul.gortmaker@windriver.com you wrote:
The sbc8548 has a 64MB SODIMM flash module off of CS6 that previously wasn't enumerated by u-boot. There were already BR6/OR6 settings for it [used by cpu_init_f()] but there was no TLB entry and it wasn't in the list of flash banks reported to u-boot.
The location of the 64MB flash is "pulled back" 8MB from a 64MB boundary, in order to allow address space for the 8MB boot flash that is at the end of 32 bit address space. This means creating two 4MB TLB entries for the 8MB chunk, and then expanding the original boot flash entry to 64MB in order to cover the 8MB boot flash and the remainder (56MB) of the user flash.
... ...
- SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE,
- SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x800000, CONFIG_SYS_ALT_FLASH + 0x800000,
Line too long.
- /*
* TLB 8: 4M Non-cacheable, guarded* 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH*/- SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, CONFIG_SYS_ALT_FLASH + 0x400000,
Ditto.
+#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE, CONFIG_SYS_ALT_FLASH}
Ditto.
Best regards,
Wolfgang Denk
On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote:
The get_clock_freq() comes from freescale/common/cadmus.c and is only valid for the CDS based 85xx reference platforms. It would be nice if we could read the 33 vs. 66MHz status somehow, but in the meantime, tie it to CONFIG_SYS_CLK_FREQ like all the other non-CDS boards do.
Signed-off-by: Paul Gortmaker paul.gortmaker@windriver.com
board/sbc8548/sbc8548.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-)
applied to 85xx.
- k
On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote:
There are a couple defines and PCI bridge quirks related to the PCI backplane of the MPC8548CDS that have no meaning in the context of the port to the sbc8548 board, so delete them.
Also, the form factor of the sbc8548 is a standalone board with a single PCI-X and a single PCI-e slot. That pretty much guarantees that it will never be a PCI agent itself, so the host/agent and root complex/end node distinctions have been removed.
Similarly, since there is no physical connector mapping to PCI2, so all references of PCI2 in the board support files have been removed as well.
Signed-off-by: Paul Gortmaker paul.gortmaker@windriver.com
board/sbc8548/sbc8548.c | 63 +++ +---------------------------------------- include/configs/sbc8548.h | 9 ------ 2 files changed, 6 insertions(+), 66 deletions(-)
Can we look at using fsl_pci_init_port()?
See my recent patches for p2020/mpc8572ds/mpc8536ds
- k
Kumar Gala wrote:
On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote:
There are a couple defines and PCI bridge quirks related to the PCI backplane of the MPC8548CDS that have no meaning in the context of the port to the sbc8548 board, so delete them.
Also, the form factor of the sbc8548 is a standalone board with a single PCI-X and a single PCI-e slot. That pretty much guarantees that it will never be a PCI agent itself, so the host/agent and root complex/end node distinctions have been removed.
Similarly, since there is no physical connector mapping to PCI2, so all references of PCI2 in the board support files have been removed as well.
Signed-off-by: Paul Gortmaker paul.gortmaker@windriver.com
board/sbc8548/sbc8548.c | 63 ++++---------------------------------------- include/configs/sbc8548.h | 9 ------ 2 files changed, 6 insertions(+), 66 deletions(-)
Can we look at using fsl_pci_init_port()?
Sure.
See my recent patches for p2020/mpc8572ds/mpc8536ds
What did you have in mind - me creating a similar patch like the above to layer on what I've got now, or is there a preference for me to munge the same change into the existing 5/8 PCI update patch? I guess the former gives an extra bisection point...
P.
- k
On Sep 19, 2009, at 11:05 AM, Paul Gortmaker wrote:
Kumar Gala wrote:
On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote:
There are a couple defines and PCI bridge quirks related to the PCI backplane of the MPC8548CDS that have no meaning in the context of the port to the sbc8548 board, so delete them.
Also, the form factor of the sbc8548 is a standalone board with a single PCI-X and a single PCI-e slot. That pretty much guarantees that it will never be a PCI agent itself, so the host/agent and root complex/end node distinctions have been removed.
Similarly, since there is no physical connector mapping to PCI2, so all references of PCI2 in the board support files have been removed as well.
Signed-off-by: Paul Gortmaker paul.gortmaker@windriver.com
board/sbc8548/sbc8548.c | 63 +++ +---------------------------------------- include/configs/sbc8548.h | 9 ------ 2 files changed, 6 insertions(+), 66 deletions(-)
Can we look at using fsl_pci_init_port()?
Sure.
See my recent patches for p2020/mpc8572ds/mpc8536ds
What did you have in mind - me creating a similar patch like the above to layer on what I've got now, or is there a preference for me to munge the same change into the existing 5/8 PCI update patch? I guess the former gives an extra bisection point...
Which ever works for you, the later sounds a bit easier to review.
- k
On Sep 18, 2009, at 6:08 PM, Paul Gortmaker wrote:
There are a couple defines and PCI bridge quirks related to the PCI backplane of the MPC8548CDS that have no meaning in the context of the port to the sbc8548 board, so delete them.
Also, the form factor of the sbc8548 is a standalone board with a single PCI-X and a single PCI-e slot. That pretty much guarantees that it will never be a PCI agent itself, so the host/agent and root complex/end node distinctions have been removed.
Similarly, since there is no physical connector mapping to PCI2, so all references of PCI2 in the board support files have been removed as well.
Signed-off-by: Paul Gortmaker paul.gortmaker@windriver.com
board/sbc8548/sbc8548.c | 63 +++ +---------------------------------------- include/configs/sbc8548.h | 9 ------ 2 files changed, 6 insertions(+), 66 deletions(-)
applied to 85xx.
- k
participants (3)
-
Kumar Gala -
Paul Gortmaker -
Wolfgang Denk