On 10/11/23 05:15, Venkatesh Yadav Abbarapu wrote:

When 64-bit address is passed only lower 32-bit address is getting updated. Program the upper 32-bit address in the DMA destination memory address MSBs register.

Signed-off-by: Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com

drivers/spi/cadence_ospi_versal.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)

diff --git a/drivers/spi/cadence_ospi_versal.c b/drivers/spi/cadence_ospi_versal.c index a7685a2f51..e02a3b3de3 100644 --- a/drivers/spi/cadence_ospi_versal.c +++ b/drivers/spi/cadence_ospi_versal.c @@ -44,8 +44,10 @@ int cadence_qspi_apb_dma_read(struct cadence_spi_priv *priv, priv->regbase + CQSPI_REG_INDIR_TRIG_ADDR_RANGE); writel(CQSPI_DFLT_DMA_PERIPH_CFG, priv->regbase + CQSPI_REG_DMA_PERIPH_CFG);

• writel((unsigned long)rxbuf, priv->regbase +
  

• writel(lower_32_bits((unsigned long)rxbuf), priv->regbase +
    CQSPI_DMA_DST_ADDR_REG);
  

• writel(upper_32_bits((unsigned long)rxbuf), priv->regbase +
  

•        CQSPI_DMA_DST_ADDR_MSB_REG);
  

  writel(priv->trigger_address, priv->regbase + CQSPI_DMA_SRC_RD_ADDR_REG); writel(bytes_to_dma, priv->regbase +

Applied. M