Move all the CCSR related device nodes into /soc similiar to the linux device tree.

Signed-off-by: Michael Walle michael@walle.cc --- changes since v1: - remove u-boot,dm-pre-reloc from rdb and qds boards

.../dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 4 + .../dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi | 2 +- .../dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi | 2 +- .../dts/fsl-ls1028a-qds-7777-sch-30841.dtsi | 8 +- .../dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi | 4 +- .../dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi | 2 +- .../fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi | 8 +- .../dts/fsl-ls1028a-qds-9999-sch-24801.dtsi | 8 +- .../fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi | 8 +- .../fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi | 8 +- .../dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi | 2 +- .../dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi | 2 +- arch/arm/dts/fsl-ls1028a-qds.dtsi | 1 - arch/arm/dts/fsl-ls1028a-rdb.dts | 1 - arch/arm/dts/fsl-ls1028a.dtsi | 767 +++++++++--------- 15 files changed, 418 insertions(+), 409 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi index b3861ed98c..fa4c05212a 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi @@ -266,6 +266,10 @@ u-boot,dm-pre-reloc; };

+&soc { + u-boot,dm-pre-reloc; +}; + &sysclk { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi index 23816da8ee..181fd2ddcb 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-1xxx-sch-30842.dtsi @@ -16,5 +16,5 @@ &enetc0 { status = "okay"; phy-mode = "usxgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi index c6558ae2e0..67b68f1b3d 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-6xxx-sch-30842.dtsi @@ -15,5 +15,5 @@ &enetc0 { status = "okay"; phy-mode = "sgmii-2500"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi index 5a0f060c16..433731df0e 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-7777-sch-30841.dtsi @@ -31,25 +31,25 @@ &mscc_felix_port0 { status = "okay"; phy-mode = "sgmii-2500"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@00}>; };

&mscc_felix_port1 { status = "okay"; phy-mode = "sgmii-2500"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@01}>; };

&mscc_felix_port2 { status = "okay"; phy-mode = "sgmii-2500"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; };

&mscc_felix_port3 { status = "okay"; phy-mode = "sgmii-2500"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; };

&mscc_felix_port4 { diff --git a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi index 39a83e10c4..cb74c8b371 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-7xx7-sch-30841R.dtsi @@ -20,13 +20,13 @@ &mscc_felix_port0 { status = "okay"; phy-mode = "sgmii-2500"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@02}>; };

&mscc_felix_port3 { status = "okay"; phy-mode = "sgmii-2500"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@03}>; };

&mscc_felix_port4 { diff --git a/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi index 7d4702e4ff..979c0ddd48 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-8xxx-sch-24801.dtsi @@ -15,5 +15,5 @@ &enetc0 { status = "okay"; phy-mode = "sgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>; }; diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi index 021fe3fbc6..f74c1433af 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801-LBRW.dtsi @@ -45,25 +45,25 @@ &mscc_felix_port0 { status = "okay"; phy-mode = "sgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>; };

&mscc_felix_port1 { status = "okay"; phy-mode = "sgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@1c}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@1c}>; };

&mscc_felix_port2 { status = "okay"; phy-mode = "sgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>; };

&mscc_felix_port3 { status = "okay"; phy-mode = "sgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>; };

&mscc_felix_port4 { diff --git a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi index b6704d8089..4edc428b27 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-9999-sch-24801.dtsi @@ -30,25 +30,25 @@ &mscc_felix_port0 { status = "okay"; phy-mode = "sgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1c}>; };

&mscc_felix_port1 { status = "okay"; phy-mode = "sgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1d}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1d}>; };

&mscc_felix_port2 { status = "okay"; phy-mode = "sgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1e}>; };

&mscc_felix_port3 { status = "okay"; phy-mode = "sgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@40/phy@1f}>; };

&mscc_felix_port4 { diff --git a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi index 8c10897e56..7fefb4c99f 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-x3xx-sch-30841-LBRW.dtsi @@ -30,25 +30,25 @@ &mscc_felix_port0 { status = "okay"; phy-mode = "usxgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@00}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@00}>; };

&mscc_felix_port1 { status = "okay"; phy-mode = "usxgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@01}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@01}>; };

&mscc_felix_port2 { status = "okay"; phy-mode = "usxgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>; };

&mscc_felix_port3 { status = "okay"; phy-mode = "usxgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@03}>; };

&mscc_felix_port4 { diff --git a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi index 1d800dacef..223145756a 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-x5xx-sch-28021-LBRW.dtsi @@ -24,25 +24,25 @@ &mscc_felix_port0 { status = "okay"; phy-mode = "qsgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@08}>; };

&mscc_felix_port1 { status = "okay"; phy-mode = "qsgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@09}>; };

&mscc_felix_port2 { status = "okay"; phy-mode = "qsgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0a}>; };

&mscc_felix_port3 { status = "okay"; phy-mode = "qsgmii"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@0b}>; };

&mscc_felix_port4 { diff --git a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi index 1fb2cdf0c2..1834418ae2 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-x7xx-sch-30842.dtsi @@ -20,7 +20,7 @@ &mscc_felix_port1 { status = "okay"; phy-mode = "sgmii-2500"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@50/phy@02}>; };

&mscc_felix_port4 { diff --git a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi index 2333f74e5a..2ee11bcacb 100644 --- a/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds-xx7x-sch-30842.dtsi @@ -20,7 +20,7 @@ &mscc_felix_port2 { status = "okay"; phy-mode = "sgmii-2500"; - phy-handle = <&{/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>; + phy-handle = <&{/soc/i2c@2000000/fpga@66/mux-mdio@54/mdio@60/phy@02}>; };

&mscc_felix_port4 { diff --git a/arch/arm/dts/fsl-ls1028a-qds.dtsi b/arch/arm/dts/fsl-ls1028a-qds.dtsi index 69632fa796..335d7b1e4c 100644 --- a/arch/arm/dts/fsl-ls1028a-qds.dtsi +++ b/arch/arm/dts/fsl-ls1028a-qds.dtsi @@ -130,7 +130,6 @@

&i2c0 { status = "okay"; - u-boot,dm-pre-reloc;

fpga@66 { #address-cells = <1>; diff --git a/arch/arm/dts/fsl-ls1028a-rdb.dts b/arch/arm/dts/fsl-ls1028a-rdb.dts index 82a8c0a0cd..708182f65c 100644 --- a/arch/arm/dts/fsl-ls1028a-rdb.dts +++ b/arch/arm/dts/fsl-ls1028a-rdb.dts @@ -61,7 +61,6 @@

&i2c0 { status = "okay"; - u-boot,dm-pre-reloc;

i2c-mux@77 {

diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 53b052ed32..b3b497218f 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -21,13 +21,6 @@ clock-output-names = "sysclk"; };

- clockgen: clocking@1300000 { - compatible = "fsl,ls1028a-clockgen"; - reg = <0x0 0x1300000 0x0 0xa0000>; - #clock-cells = <2>; - clocks = <&sysclk>; - }; - memory@01080000 { device_type = "memory"; reg = <0x00000000 0x01080000 0 0x80000000>; @@ -56,432 +49,446 @@ IRQ_TYPE_LEVEL_LOW)>; };

- fspi: flexspi@20c0000 { - compatible = "nxp,lx2160a-fspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x20c0000 0x0 0x10000>, - <0x0 0x20000000 0x0 0x10000000>; - reg-names = "fspi_base", "fspi_mmap"; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "fspi_en", "fspi"; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - serial0: serial@21c0500 { - device_type = "serial"; - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21c0500 0x0 0x100>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - serial1: serial@21c0600 { - device_type = "serial"; - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21c0600 0x0 0x100>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; - - pcie1: pcie@3400000 { - compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; - reg = <0x00 0x03400000 0x0 0x80000 - 0x00 0x03480000 0x0 0x40000 /* lut registers */ - 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ - 0x80 0x00000000 0x0 0x20000>; /* configuration space */ - reg-names = "dbi", "lut", "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - }; + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges;

- pcie2: pcie@3500000 { - compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; - reg = <0x00 0x03500000 0x0 0x80000 - 0x00 0x03580000 0x0 0x40000 /* lut registers */ - 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */ - 0x88 0x00000000 0x0 0x20000>; /* configuration space */ - reg-names = "dbi", "lut", "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - }; + clockgen: clocking@1300000 { + compatible = "fsl,ls1028a-clockgen"; + reg = <0x0 0x1300000 0x0 0xa0000>; + #clock-cells = <2>; + clocks = <&sysclk>; + };

- pcie@1f0000000 { - compatible = "pci-host-ecam-generic"; - /* ECAM bus 0, HW has more space reserved but not populated */ - bus-range = <0x0 0x0>; - reg = <0x01 0xf0000000 0x0 0x100000>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>; - enetc0: pci@0,0 { - reg = <0x000000 0 0 0 0>; + fspi: flexspi@20c0000 { + compatible = "nxp,lx2160a-fspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20c0000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + clocks = <&clockgen 4 3>, <&clockgen 4 3>; + clock-names = "fspi_en", "fspi"; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; - enetc1: pci@0,1 { - reg = <0x000100 0 0 0 0>; + + serial0: serial@21c0500 { + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21c0500 0x0 0x100>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; }; - enetc2: pci@0,2 { - reg = <0x000200 0 0 0 0>; - status = "disabled"; - phy-mode = "internal";

- fixed-link { - speed = <2500>; - full-duplex; - }; - }; - mdio0: pci@0,3 { - #address-cells=<0>; - #size-cells=<1>; - reg = <0x000300 0 0 0 0>; + serial1: serial@21c0600 { + device_type = "serial"; + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x0 0x21c0600 0x0 0x100>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; - - fixed-link { - speed = <1000>; - full-duplex; - }; };

- mscc_felix: pci@0,5 { - reg = <0x000500 0 0 0 0>; - status = "disabled"; + pcie1: pcie@3400000 { + compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; + reg = <0x00 0x03400000 0x0 0x80000 + 0x00 0x03480000 0x0 0x40000 /* lut registers */ + 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ + 0x80 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + };

- ports { - #address-cells = <1>; - #size-cells = <0>; + pcie2: pcie@3500000 { + compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; + reg = <0x00 0x03500000 0x0 0x80000 + 0x00 0x03580000 0x0 0x40000 /* lut registers */ + 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */ + 0x88 0x00000000 0x0 0x20000>; /* configuration space */ + reg-names = "dbi", "lut", "ctrl", "config"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + num-lanes = <4>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + };

- mscc_felix_port0: port@0 { - reg = <0>; - status = "disabled"; + pcie@1f0000000 { + compatible = "pci-host-ecam-generic"; + /* ECAM bus 0, HW has more space reserved but not populated */ + bus-range = <0x0 0x0>; + reg = <0x01 0xf0000000 0x0 0x100000>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>; + enetc0: pci@0,0 { + reg = <0x000000 0 0 0 0>; + status = "disabled"; + }; + enetc1: pci@0,1 { + reg = <0x000100 0 0 0 0>; + status = "disabled"; + }; + enetc2: pci@0,2 { + reg = <0x000200 0 0 0 0>; + status = "disabled"; + phy-mode = "internal"; + + fixed-link { + speed = <2500>; + full-duplex; }; - - mscc_felix_port1: port@1 { - reg = <1>; - status = "disabled"; + }; + mdio0: pci@0,3 { + #address-cells=<0>; + #size-cells=<1>; + reg = <0x000300 0 0 0 0>; + status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; }; + };

- mscc_felix_port2: port@2 { - reg = <2>; - status = "disabled"; - }; + mscc_felix: pci@0,5 { + reg = <0x000500 0 0 0 0>; + status = "disabled";

- mscc_felix_port3: port@3 { - reg = <3>; - status = "disabled"; - }; + ports { + #address-cells = <1>; + #size-cells = <0>;

- mscc_felix_port4: port@4 { - reg = <4>; - phy-mode = "internal"; - status = "disabled"; + mscc_felix_port0: port@0 { + reg = <0>; + status = "disabled"; + };

- fixed-link { - speed = <2500>; - full-duplex; + mscc_felix_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + mscc_felix_port2: port@2 { + reg = <2>; + status = "disabled"; }; - };

- mscc_felix_port5: port@5 { - reg = <5>; - phy-mode = "internal"; - status = "disabled"; + mscc_felix_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + mscc_felix_port4: port@4 { + reg = <4>; + phy-mode = "internal"; + status = "disabled";

- fixed-link { - speed = <1000>; - full-duplex; + fixed-link { + speed = <2500>; + full-duplex; + }; };

+ mscc_felix_port5: port@5 { + reg = <5>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + + }; }; }; + + enetc6: pci@0,6 { + reg = <0x000600 0 0 0 0>; + status = "disabled"; + phy-mode = "internal"; + }; };

- enetc6: pci@0,6 { - reg = <0x000600 0 0 0 0>; + i2c0: i2c@2000000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2000000 0x0 0x10000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; status = "disabled"; - phy-mode = "internal"; }; - };

- i2c0: i2c@2000000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2000000 0x0 0x10000>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - - i2c1: i2c@2010000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2010000 0x0 0x10000>; - interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; + i2c1: i2c@2010000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2010000 0x0 0x10000>; + interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + };

- i2c2: i2c@2020000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2020000 0x0 0x10000>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; + i2c2: i2c@2020000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2020000 0x0 0x10000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + };

- i2c3: i2c@2030000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2030000 0x0 0x10000>; - interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; + i2c3: i2c@2030000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2030000 0x0 0x10000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + };

- i2c4: i2c@2040000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2040000 0x0 0x10000>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; + i2c4: i2c@2040000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2040000 0x0 0x10000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + };

- i2c5: i2c@2050000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2050000 0x0 0x10000>; - interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; + i2c5: i2c@2050000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2050000 0x0 0x10000>; + interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + };

- i2c6: i2c@2060000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2060000 0x0 0x10000>; - interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; + i2c6: i2c@2060000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2060000 0x0 0x10000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + };

- i2c7: i2c@2070000 { - compatible = "fsl,vf610-i2c"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2070000 0x0 0x10000>; - interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; + i2c7: i2c@2070000 { + compatible = "fsl,vf610-i2c"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2070000 0x0 0x10000>; + interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "i2c"; + clocks = <&clockgen 4 0>; + status = "disabled"; + };

- lpuart0: serial@2260000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2260000 0x0 0x1000>; - interrupts = <0 232 0x4>; - clocks = <&sysclk>; - clock-names = "ipg"; - little-endian; - status = "disabled"; - }; + lpuart0: serial@2260000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2260000 0x0 0x1000>; + interrupts = <0 232 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + little-endian; + status = "disabled"; + };

- lpuart1: serial@2270000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2270000 0x0 0x1000>; - interrupts = <0 233 0x4>; - clocks = <&sysclk>; - clock-names = "ipg"; - little-endian; - status = "disabled"; - }; + lpuart1: serial@2270000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2270000 0x0 0x1000>; + interrupts = <0 233 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + little-endian; + status = "disabled"; + };

- lpuart2: serial@2280000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2280000 0x0 0x1000>; - interrupts = <0 234 0x4>; - clocks = <&sysclk>; - clock-names = "ipg"; - little-endian; - status = "disabled"; - }; + lpuart2: serial@2280000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2280000 0x0 0x1000>; + interrupts = <0 234 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + little-endian; + status = "disabled"; + };

- lpuart3: serial@2290000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x2290000 0x0 0x1000>; - interrupts = <0 235 0x4>; - clocks = <&sysclk>; - clock-names = "ipg"; - little-endian; - status = "disabled"; - }; + lpuart3: serial@2290000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x2290000 0x0 0x1000>; + interrupts = <0 235 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + little-endian; + status = "disabled"; + };

- lpuart4: serial@22a0000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x22a0000 0x0 0x1000>; - interrupts = <0 236 0x4>; - clocks = <&sysclk>; - clock-names = "ipg"; - little-endian; - status = "disabled"; - }; + lpuart4: serial@22a0000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x22a0000 0x0 0x1000>; + interrupts = <0 236 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + little-endian; + status = "disabled"; + };

- lpuart5: serial@22b0000 { - compatible = "fsl,ls1021a-lpuart"; - reg = <0x0 0x22b0000 0x0 0x1000>; - interrupts = <0 237 0x4>; - clocks = <&sysclk>; - clock-names = "ipg"; - little-endian; - status = "disabled"; - }; + lpuart5: serial@22b0000 { + compatible = "fsl,ls1021a-lpuart"; + reg = <0x0 0x22b0000 0x0 0x1000>; + interrupts = <0 237 0x4>; + clocks = <&sysclk>; + clock-names = "ipg"; + little-endian; + status = "disabled"; + };

- usb1: usb3@3100000 { - compatible = "fsl,layerscape-dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - status = "disabled"; - }; + usb1: usb3@3100000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + status = "disabled"; + };

- usb2: usb3@3110000 { - compatible = "fsl,layerscape-dwc3"; - reg = <0x0 0x3110000 0x0 0x10000>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - status = "disabled"; - }; + usb2: usb3@3110000 { + compatible = "fsl,layerscape-dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + status = "disabled"; + };

- dspi0: dspi@2100000 { - compatible = "fsl,vf610-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2100000 0x0 0x10000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "dspi"; - clocks = <&clockgen 4 0>; - num-cs = <5>; - litte-endian; - status = "disabled"; - }; + dspi0: dspi@2100000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2100000 0x0 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <5>; + litte-endian; + status = "disabled"; + };

- dspi1: dspi@2110000 { - compatible = "fsl,vf610-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2110000 0x0 0x10000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "dspi"; - clocks = <&clockgen 4 0>; - num-cs = <5>; - little-endian; - status = "disabled"; - }; + dspi1: dspi@2110000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2110000 0x0 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <5>; + little-endian; + status = "disabled"; + };

- dspi2: dspi@2120000 { - compatible = "fsl,vf610-dspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x2120000 0x0 0x10000>; - interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "dspi"; - clocks = <&clockgen 4 0>; - num-cs = <5>; - little-endian; - status = "disabled"; - }; + dspi2: dspi@2120000 { + compatible = "fsl,vf610-dspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x2120000 0x0 0x10000>; + interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; + clock-names = "dspi"; + clocks = <&clockgen 4 0>; + num-cs = <5>; + little-endian; + status = "disabled"; + };

- esdhc0: esdhc@2140000 { - compatible = "fsl,esdhc"; - reg = <0x0 0x2140000 0x0 0x10000>; - interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - big-endian; - bus-width = <4>; - status = "disabled"; - }; + esdhc0: esdhc@2140000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x2140000 0x0 0x10000>; + interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; + big-endian; + bus-width = <4>; + status = "disabled"; + };

- esdhc1: esdhc@2150000 { - compatible = "fsl,esdhc"; - reg = <0x0 0x2150000 0x0 0x10000>; - interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; - big-endian; - non-removable; - bus-width = <4>; - status = "disabled"; - }; + esdhc1: esdhc@2150000 { + compatible = "fsl,esdhc"; + reg = <0x0 0x2150000 0x0 0x10000>; + interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; + big-endian; + non-removable; + bus-width = <4>; + status = "disabled"; + };

- gpio0: gpio@2300000 { - compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; - reg = <0x0 0x2300000 0x0 0x10000>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - little-endian; - }; + gpio0: gpio@2300000 { + compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; + reg = <0x0 0x2300000 0x0 0x10000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + little-endian; + };

- gpio1: gpio@2310000 { - compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; - reg = <0x0 0x2310000 0x0 0x10000>; - interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - little-endian; - }; + gpio1: gpio@2310000 { + compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; + reg = <0x0 0x2310000 0x0 0x10000>; + interrupts = <GIC_SPI 36 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + little-endian; + };

- gpio2: gpio@2320000 { - compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; - reg = <0x0 0x2320000 0x0 0x10000>; - interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; - gpio-controller; - #gpio-cells = <2>; - interrupt-controller; - #interrupt-cells = <2>; - little-endian; - }; + gpio2: gpio@2320000 { + compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; + reg = <0x0 0x2320000 0x0 0x10000>; + interrupts = <GIC_SPI 37 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + little-endian; + };

- sata: sata@3200000 { - compatible = "fsl,ls1028a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ - 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/ - reg-names = "sata-base", "ecc-addr"; - interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; + sata: sata@3200000 { + compatible = "fsl,ls1028a-ahci"; + reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ + 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/ + reg-names = "sata-base", "ecc-addr"; + interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + };

- cluster1_core0_watchdog: wdt@c000000 { - compatible = "arm,sp805-wdt"; - reg = <0x0 0xc000000 0x0 0x1000>; + cluster1_core0_watchdog: wdt@c000000 { + compatible = "arm,sp805-wdt"; + reg = <0x0 0xc000000 0x0 0x1000>; + }; }; };

This node is some hodgepodge between the ddr controller node at SoC offset 0x1080000 and some static memory size of 2GiB. Remove this bogus node because it doesn't seem to be used at all.

Signed-off-by: Michael Walle michael@walle.cc Reviewed-by: Vladimir Oltean vladimir.oltean@nxp.com Tested-by: Vladimir Oltean vladimir.oltean@nxp.com --- changes since v1: - none

arch/arm/dts/fsl-ls1028a.dtsi | 6 ------ 1 file changed, 6 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index b3b497218f..8559562803 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -21,12 +21,6 @@ clock-output-names = "sysclk"; };

- memory@01080000 { - device_type = "memory"; - reg = <0x00000000 0x01080000 0 0x80000000>; - /* DRAM space - 1, size : 2 GB DRAM */ - }; - gic: interrupt-controller@6000000 { compatible = "arm,gic-v3"; reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */

The official ls1028a binding of the driver uses the following as compatibles: compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi";

Add the missing compatible to the driver and update the device tree. We can use the fallback "fsl,ls1021a-v1.0-dspi", because the endianness is determined by the little-endian property and not by the compatible string itself. Further, we won't need and specific details on the DMA configuration (which is different on the LS1021A). If it's ever needed, we can later add the more specific "fsl,ls1028a-dspi" compatible to the driver.

Signed-off-by: Michael Walle michael@walle.cc Reviewed-by: Vladimir Oltean vladimir.oltean@nxp.com --- changes since v1: - add more information to the commit message - fix typo

arch/arm/dts/fsl-ls1028a.dtsi | 6 +++--- drivers/spi/fsl_dspi.c | 1 + 2 files changed, 4 insertions(+), 3 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 09d748c4d0..4186df17e1 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -381,7 +381,7 @@ };

dspi0: dspi@2100000 { - compatible = "fsl,vf610-dspi"; + compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2100000 0x0 0x10000>; @@ -394,7 +394,7 @@ };

dspi1: dspi@2110000 { - compatible = "fsl,vf610-dspi"; + compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2110000 0x0 0x10000>; @@ -407,7 +407,7 @@ };

dspi2: dspi@2120000 { - compatible = "fsl,vf610-dspi"; + compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2120000 0x0 0x10000>; diff --git a/drivers/spi/fsl_dspi.c b/drivers/spi/fsl_dspi.c index 8fe3508c64..23d812f476 100644 --- a/drivers/spi/fsl_dspi.c +++ b/drivers/spi/fsl_dspi.c @@ -654,6 +654,7 @@ static const struct dm_spi_ops fsl_dspi_ops = {

static const struct udevice_id fsl_dspi_ids[] = { { .compatible = "fsl,vf610-dspi" }, + { .compatible = "fsl,ls1021a-v1.0-dspi" }, { } };

Now that everything is prepared, copy the fsl-ls1028a.dtsi from the linux kernel v5.14.

Signed-off-by: Michael Walle michael@walle.cc --- changes since v1: - none

arch/arm/dts/fsl-ls1028a.dtsi | 1212 +++++++++++++---- .../dt-bindings/clock/fsl,qoriq-clockgen.h | 15 + 2 files changed, 958 insertions(+), 269 deletions(-) create mode 100644 include/dt-bindings/clock/fsl,qoriq-clockgen.h

diff --git a/arch/arm/dts/fsl-ls1028a.dtsi b/arch/arm/dts/fsl-ls1028a.dtsi index 69850fe7f2..343ecf0e89 100644 --- a/arch/arm/dts/fsl-ls1028a.dtsi +++ b/arch/arm/dts/fsl-ls1028a.dtsi @@ -1,12 +1,16 @@ -// SPDX-License-Identifier: GPL-2.0+ OR X11 +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) /* - * NXP ls1028a SOC common device tree source + * Device Tree Include file for NXP Layerscape-1028A family SoC. * - * Copyright 2019-2020 NXP + * Copyright 2018-2020 NXP + * + * Harninder Rai harninder.rai@nxp.com * */

+#include <dt-bindings/clock/fsl,qoriq-clockgen.h> #include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/thermal/thermal.h>

/ { compatible = "fsl,ls1028a"; @@ -14,6 +18,54 @@ #address-cells = <2>; #size-cells = <2>;

+ cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x0>; + enable-method = "psci"; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; + next-level-cache = <&l2>; + cpu-idle-states = <&CPU_PW20>; + #cooling-cells = <2>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a72"; + reg = <0x1>; + enable-method = "psci"; + clocks = <&clockgen QORIQ_CLK_CMUX 0>; + next-level-cache = <&l2>; + cpu-idle-states = <&CPU_PW20>; + #cooling-cells = <2>; + }; + + l2: l2-cache { + compatible = "cache"; + }; + }; + + idle-states { + /* + * PSCI node is not added default, U-boot will add missing + * parts if it determines to use PSCI. + */ + entry-method = "psci"; + + CPU_PW20: cpu-pw20 { + compatible = "arm,idle-state"; + idle-state-name = "PW20"; + arm,psci-suspend-param = <0x0>; + entry-latency-us = <2000>; + exit-latency-us = <2000>; + min-residency-us = <6000>; + }; + }; + sysclk: sysclk { compatible = "fixed-clock"; #clock-cells = <0>; @@ -21,14 +73,33 @@ clock-output-names = "sysclk"; };

- gic: interrupt-controller@6000000 { - compatible = "arm,gic-v3"; - reg = <0x0 0x06000000 0 0x10000>, /* GIC Dist */ - <0x0 0x06040000 0 0x40000>; - #interrupt-cells = <3>; - interrupt-controller; - interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | - IRQ_TYPE_LEVEL_LOW)>; + osc_27m: clock-osc-27m { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <27000000>; + clock-output-names = "phy_27m"; + }; + + dpclk: clock-controller@f1f0000 { + compatible = "fsl,ls1028a-plldig"; + reg = <0x0 0xf1f0000 0x0 0xffff>; + #clock-cells = <0>; + clocks = <&osc_27m>; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + status = "disabled"; + }; + }; + + reboot { + compatible ="syscon-reboot"; + regmap = <&rst>; + offset = <0>; + mask = <0x02>; };

timer { @@ -43,177 +114,127 @@ IRQ_TYPE_LEVEL_LOW)>; };

- soc: soc { - compatible = "simple-bus"; + pmu { + compatible = "arm,cortex-a72-pmu"; + interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH>; + }; + + gic: interrupt-controller@6000000 { + compatible= "arm,gic-v3"; #address-cells = <2>; #size-cells = <2>; ranges; - - clockgen: clocking@1300000 { - compatible = "fsl,ls1028a-clockgen"; - reg = <0x0 0x1300000 0x0 0xa0000>; - #clock-cells = <2>; - clocks = <&sysclk>; + reg= <0x0 0x06000000 0 0x10000>, /* GIC Dist */ + <0x0 0x06040000 0 0x40000>; /* GIC Redistributor */ + #interrupt-cells= <3>; + interrupt-controller; + interrupts = <GIC_PPI 9 (GIC_CPU_MASK_RAW(0xf) | + IRQ_TYPE_LEVEL_LOW)>; + its: gic-its@6020000 { + compatible = "arm,gic-v3-its"; + msi-controller; + reg = <0x0 0x06020000 0 0x20000>;/* GIC Translater */ }; + };

- fspi: flexspi@20c0000 { - compatible = "nxp,lx2160a-fspi"; - #address-cells = <1>; - #size-cells = <0>; - reg = <0x0 0x20c0000 0x0 0x10000>, - <0x0 0x20000000 0x0 0x10000000>; - reg-names = "fspi_base", "fspi_mmap"; - clocks = <&clockgen 4 3>, <&clockgen 4 3>; - clock-names = "fspi_en", "fspi"; - interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; + thermal-zones { + ddr-controller { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 0>;

- duart0: serial@21c0500 { - device_type = "serial"; - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21c0500 0x0 0x100>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; - }; + trips { + ddr-ctrler-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + };

- duart1: serial@21c0600 { - device_type = "serial"; - compatible = "fsl,ns16550", "ns16550a"; - reg = <0x0 0x21c0600 0x0 0x100>; - interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; - status = "disabled"; + ddr-ctrler-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; + }; + }; };

- pcie1: pcie@3400000 { - compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; - reg = <0x00 0x03400000 0x0 0x80000 - 0x00 0x03480000 0x0 0x40000 /* lut registers */ - 0x00 0x034c0000 0x0 0x40000 /* pf controls registers */ - 0x80 0x00000000 0x0 0x20000>; /* configuration space */ - reg-names = "dbi", "lut", "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x80 0x00020000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - }; + core-cluster { + polling-delay-passive = <1000>; + polling-delay = <5000>; + thermal-sensors = <&tmu 1>;

- pcie2: pcie@3500000 { - compatible = "fsl,ls-pcie", "fsl,ls1028-pcie", "snps,dw-pcie"; - reg = <0x00 0x03500000 0x0 0x80000 - 0x00 0x03580000 0x0 0x40000 /* lut registers */ - 0x00 0x035c0000 0x0 0x40000 /* pf controls registers */ - 0x88 0x00000000 0x0 0x20000>; /* configuration space */ - reg-names = "dbi", "lut", "ctrl", "config"; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - num-lanes = <4>; - bus-range = <0x0 0xff>; - ranges = <0x81000000 0x0 0x00000000 0x88 0x00020000 0x0 0x00010000 /* downstream I/O */ - 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ - }; - - pcie@1f0000000 { - compatible = "pci-host-ecam-generic"; - /* ECAM bus 0, HW has more space reserved but not populated */ - bus-range = <0x0 0x0>; - reg = <0x01 0xf0000000 0x0 0x100000>; - #address-cells = <3>; - #size-cells = <2>; - device_type = "pci"; - ranges= <0x82000000 0x0 0x00000000 0x1 0xf8000000 0x0 0x160000>; - enetc_port0: pci@0,0 { - reg = <0x000000 0 0 0 0>; - status = "disabled"; - }; - enetc_port1: pci@0,1 { - reg = <0x000100 0 0 0 0>; - status = "disabled"; - }; - enetc_port2: pci@0,2 { - reg = <0x000200 0 0 0 0>; - status = "disabled"; - phy-mode = "internal"; + trips { + core_cluster_alert: core-cluster-alert { + temperature = <85000>; + hysteresis = <2000>; + type = "passive"; + };

- fixed-link { - speed = <2500>; - full-duplex; + core_cluster_crit: core-cluster-crit { + temperature = <95000>; + hysteresis = <2000>; + type = "critical"; }; }; - enetc_mdio_pf3: pci@0,3 { - #address-cells=<0>; - #size-cells=<1>; - reg = <0x000300 0 0 0 0>; - status = "disabled";

- fixed-link { - speed = <1000>; - full-duplex; + cooling-maps { + map0 { + trip = <&core_cluster_alert>; + cooling-device = + <&cpu0 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>, + <&cpu1 THERMAL_NO_LIMIT THERMAL_NO_LIMIT>; }; }; + }; + };

- mscc_felix: pci@0,5 { - reg = <0x000500 0 0 0 0>; - status = "disabled"; - - ports { - #address-cells = <1>; - #size-cells = <0>; - - mscc_felix_port0: port@0 { - reg = <0>; - status = "disabled"; - }; - - mscc_felix_port1: port@1 { - reg = <1>; - status = "disabled"; - }; - - mscc_felix_port2: port@2 { - reg = <2>; - status = "disabled"; - }; - - mscc_felix_port3: port@3 { - reg = <3>; - status = "disabled"; - }; + soc: soc { + compatible = "simple-bus"; + #address-cells = <2>; + #size-cells = <2>; + ranges;

- mscc_felix_port4: port@4 { - reg = <4>; - phy-mode = "internal"; - status = "disabled"; + ddr: memory-controller@1080000 { + compatible = "fsl,qoriq-memory-controller"; + reg = <0x0 0x1080000 0x0 0x1000>; + interrupts = <GIC_SPI 17 IRQ_TYPE_LEVEL_HIGH>; + little-endian; + };

- fixed-link { - speed = <2500>; - full-duplex; - }; - }; + dcfg: syscon@1e00000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "fsl,ls1028a-dcfg", "syscon", "simple-mfd"; + reg = <0x0 0x1e00000 0x0 0x10000>; + ranges = <0x0 0x0 0x1e00000 0x10000>; + little-endian;

- mscc_felix_port5: port@5 { - reg = <5>; - phy-mode = "internal"; - status = "disabled"; + fspi_clk: clock-controller@900 { + compatible = "fsl,ls1028a-flexspi-clk"; + reg = <0x900 0x4>; + #clock-cells = <0>; + clocks = <&clockgen QORIQ_CLK_HWACCEL 0>; + clock-output-names = "fspi_clk"; + }; + };

- fixed-link { - speed = <1000>; - full-duplex; - }; + rst: syscon@1e60000 { + compatible = "syscon"; + reg = <0x0 0x1e60000 0x0 0x10000>; + little-endian; + };

- }; - }; - }; + scfg: syscon@1fc0000 { + compatible = "fsl,ls1028a-scfg", "syscon"; + reg = <0x0 0x1fc0000 0x0 0x10000>; + big-endian; + };

- enetc_port3: pci@0,6 { - reg = <0x000600 0 0 0 0>; - status = "disabled"; - phy-mode = "internal"; - }; + clockgen: clock-controller@1300000 { + compatible = "fsl,ls1028a-clockgen"; + reg = <0x0 0x1300000 0x0 0xa0000>; + #clock-cells = <2>; + clocks = <&sysclk>; };

i2c0: i2c@2000000 { @@ -222,8 +243,8 @@ #size-cells = <0>; reg = <0x0 0x2000000 0x0 0x10000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; };

@@ -233,8 +254,8 @@ #size-cells = <0>; reg = <0x0 0x2010000 0x0 0x10000>; interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; };

@@ -244,8 +265,8 @@ #size-cells = <0>; reg = <0x0 0x2020000 0x0 0x10000>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; };

@@ -255,8 +276,8 @@ #size-cells = <0>; reg = <0x0 0x2030000 0x0 0x10000>; interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; };

@@ -266,8 +287,8 @@ #size-cells = <0>; reg = <0x0 0x2040000 0x0 0x10000>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; };

@@ -277,8 +298,8 @@ #size-cells = <0>; reg = <0x0 0x2050000 0x0 0x10000>; interrupts = <GIC_SPI 74 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; };

@@ -288,8 +309,8 @@ #size-cells = <0>; reg = <0x0 0x2060000 0x0 0x10000>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; };

@@ -299,145 +320,237 @@ #size-cells = <0>; reg = <0x0 0x2070000 0x0 0x10000>; interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>; - clock-names = "i2c"; - clocks = <&clockgen 4 0>; - status = "disabled"; - }; - - lpuart0: serial@2260000 { - compatible = "fsl,ls1028a-lpuart"; - reg = <0x0 0x2260000 0x0 0x1000>; - interrupts = <0 232 0x4>; - clocks = <&sysclk>; - clock-names = "ipg"; - little-endian; - status = "disabled"; - }; - - lpuart1: serial@2270000 { - compatible = "fsl,ls1028a-lpuart"; - reg = <0x0 0x2270000 0x0 0x1000>; - interrupts = <0 233 0x4>; - clocks = <&sysclk>; - clock-names = "ipg"; - little-endian; - status = "disabled"; - }; - - lpuart2: serial@2280000 { - compatible = "fsl,ls1028a-lpuart"; - reg = <0x0 0x2280000 0x0 0x1000>; - interrupts = <0 234 0x4>; - clocks = <&sysclk>; - clock-names = "ipg"; - little-endian; - status = "disabled"; - }; - - lpuart3: serial@2290000 { - compatible = "fsl,ls1028a-lpuart"; - reg = <0x0 0x2290000 0x0 0x1000>; - interrupts = <0 235 0x4>; - clocks = <&sysclk>; - clock-names = "ipg"; - little-endian; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(4)>; status = "disabled"; };

- lpuart4: serial@22a0000 { - compatible = "fsl,ls1028a-lpuart"; - reg = <0x0 0x22a0000 0x0 0x1000>; - interrupts = <0 236 0x4>; - clocks = <&sysclk>; - clock-names = "ipg"; - little-endian; - status = "disabled"; - }; - - lpuart5: serial@22b0000 { - compatible = "fsl,ls1028a-lpuart"; - reg = <0x0 0x22b0000 0x0 0x1000>; - interrupts = <0 237 0x4>; - clocks = <&sysclk>; - clock-names = "ipg"; - little-endian; - status = "disabled"; - }; - - usb0: usb3@3100000 { - compatible = "fsl,layerscape-dwc3"; - reg = <0x0 0x3100000 0x0 0x10000>; - interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; - status = "disabled"; - }; - - usb1: usb3@3110000 { - compatible = "fsl,layerscape-dwc3"; - reg = <0x0 0x3110000 0x0 0x10000>; - interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; - dr_mode = "host"; + fspi: spi@20c0000 { + compatible = "nxp,lx2160a-fspi"; + #address-cells = <1>; + #size-cells = <0>; + reg = <0x0 0x20c0000 0x0 0x10000>, + <0x0 0x20000000 0x0 0x10000000>; + reg-names = "fspi_base", "fspi_mmap"; + interrupts = <GIC_SPI 25 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&fspi_clk>, <&fspi_clk>; + clock-names = "fspi_en", "fspi"; status = "disabled"; };

- dspi0: dspi@2100000 { + dspi0: spi@2100000 { compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2100000 0x0 0x10000>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; clock-names = "dspi"; - clocks = <&clockgen 4 0>; - num-cs = <5>; - litte-endian; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + dmas = <&edma0 0 62>, <&edma0 0 60>; + dma-names = "tx", "rx"; + spi-num-chipselects = <4>; + little-endian; status = "disabled"; };

- dspi1: dspi@2110000 { + dspi1: spi@2110000 { compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2110000 0x0 0x10000>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; clock-names = "dspi"; - clocks = <&clockgen 4 0>; - num-cs = <5>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + dmas = <&edma0 0 58>, <&edma0 0 56>; + dma-names = "tx", "rx"; + spi-num-chipselects = <4>; little-endian; status = "disabled"; };

- dspi2: dspi@2120000 { + dspi2: spi@2120000 { compatible = "fsl,ls1028a-dspi", "fsl,ls1021a-v1.0-dspi"; #address-cells = <1>; #size-cells = <0>; reg = <0x0 0x2120000 0x0 0x10000>; interrupts = <GIC_SPI 26 IRQ_TYPE_LEVEL_HIGH>; clock-names = "dspi"; - clocks = <&clockgen 4 0>; - num-cs = <5>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + dmas = <&edma0 0 54>, <&edma0 0 2>; + dma-names = "tx", "rx"; + spi-num-chipselects = <3>; little-endian; status = "disabled"; };

- esdhc: esdhc@2140000 { - compatible = "fsl,esdhc"; + esdhc: mmc@2140000 { + compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; reg = <0x0 0x2140000 0x0 0x10000>; interrupts = <GIC_SPI 28 IRQ_TYPE_LEVEL_HIGH>; - big-endian; + clock-frequency = <0>; /* fixed up by bootloader */ + clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + little-endian; bus-width = <4>; status = "disabled"; };

- esdhc1: esdhc@2150000 { - compatible = "fsl,esdhc"; + esdhc1: mmc@2150000 { + compatible = "fsl,ls1028a-esdhc", "fsl,esdhc"; reg = <0x0 0x2150000 0x0 0x10000>; interrupts = <GIC_SPI 63 IRQ_TYPE_LEVEL_HIGH>; - big-endian; - non-removable; + clock-frequency = <0>; /* fixed up by bootloader */ + clocks = <&clockgen QORIQ_CLK_HWACCEL 1>; + voltage-ranges = <1800 1800 3300 3300>; + sdhci,auto-cmd12; + broken-cd; + little-endian; bus-width = <4>; status = "disabled"; };

+ can0: can@2180000 { + compatible = "fsl,lx2160ar1-flexcan"; + reg = <0x0 0x2180000 0x0 0x10000>; + interrupts = <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + can1: can@2190000 { + compatible = "fsl,lx2160ar1-flexcan"; + reg = <0x0 0x2190000 0x0 0x10000>; + interrupts = <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + clock-names = "ipg", "per"; + status = "disabled"; + }; + + duart0: serial@21c0500 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x00 0x21c0500 0x0 0x100>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + status = "disabled"; + }; + + duart1: serial@21c0600 { + compatible = "fsl,ns16550", "ns16550a"; + reg = <0x00 0x21c0600 0x0 0x100>; + interrupts = <GIC_SPI 32 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + status = "disabled"; + }; + + + lpuart0: serial@2260000 { + compatible = "fsl,ls1028a-lpuart"; + reg = <0x0 0x2260000 0x0 0x1000>; + interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + clock-names = "ipg"; + dma-names = "rx","tx"; + dmas = <&edma0 1 32>, + <&edma0 1 33>; + status = "disabled"; + }; + + lpuart1: serial@2270000 { + compatible = "fsl,ls1028a-lpuart"; + reg = <0x0 0x2270000 0x0 0x1000>; + interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + clock-names = "ipg"; + dma-names = "rx","tx"; + dmas = <&edma0 1 30>, + <&edma0 1 31>; + status = "disabled"; + }; + + lpuart2: serial@2280000 { + compatible = "fsl,ls1028a-lpuart"; + reg = <0x0 0x2280000 0x0 0x1000>; + interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + clock-names = "ipg"; + dma-names = "rx","tx"; + dmas = <&edma0 1 28>, + <&edma0 1 29>; + status = "disabled"; + }; + + lpuart3: serial@2290000 { + compatible = "fsl,ls1028a-lpuart"; + reg = <0x0 0x2290000 0x0 0x1000>; + interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + clock-names = "ipg"; + dma-names = "rx","tx"; + dmas = <&edma0 1 26>, + <&edma0 1 27>; + status = "disabled"; + }; + + lpuart4: serial@22a0000 { + compatible = "fsl,ls1028a-lpuart"; + reg = <0x0 0x22a0000 0x0 0x1000>; + interrupts = <GIC_SPI 236 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + clock-names = "ipg"; + dma-names = "rx","tx"; + dmas = <&edma0 1 24>, + <&edma0 1 25>; + status = "disabled"; + }; + + lpuart5: serial@22b0000 { + compatible = "fsl,ls1028a-lpuart"; + reg = <0x0 0x22b0000 0x0 0x1000>; + interrupts = <GIC_SPI 237 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + clock-names = "ipg"; + dma-names = "rx","tx"; + dmas = <&edma0 1 22>, + <&edma0 1 23>; + status = "disabled"; + }; + + edma0: dma-controller@22c0000 { + #dma-cells = <2>; + compatible = "fsl,ls1028a-edma", "fsl,vf610-edma"; + reg = <0x0 0x22c0000 0x0 0x10000>, + <0x0 0x22d0000 0x0 0x10000>, + <0x0 0x22e0000 0x0 0x10000>; + interrupts = <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 56 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "edma-tx", "edma-err"; + dma-channels = <32>; + clock-names = "dmamux0", "dmamux1"; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + }; + gpio1: gpio@2300000 { compatible = "fsl,ls1028a-gpio","fsl,qoriq-gpio"; reg = <0x0 0x2300000 0x0 0x10000>; @@ -471,18 +584,579 @@ little-endian; };

+ usb0: usb@3100000 { + compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; + reg = <0x0 0x3100000 0x0 0x10000>; + interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + snps,dis_rxdet_inp3_quirk; + snps,quirk-frame-length-adjustment = <0x20>; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + }; + + usb1: usb@3110000 { + compatible = "fsl,ls1028a-dwc3", "snps,dwc3"; + reg = <0x0 0x3110000 0x0 0x10000>; + interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>; + dr_mode = "host"; + snps,dis_rxdet_inp3_quirk; + snps,quirk-frame-length-adjustment = <0x20>; + snps,incr-burst-type-adjustment = <1>, <4>, <8>, <16>; + }; + sata: sata@3200000 { compatible = "fsl,ls1028a-ahci"; - reg = <0x0 0x3200000 0x0 0x10000 /* ccsr sata base */ - 0x7 0x100520 0x0 0x4>; /* ecc sata addr*/ - reg-names = "sata-base", "ecc-addr"; + reg = <0x0 0x3200000 0x0 0x10000>, + <0x7 0x100520 0x0 0x4>; + reg-names = "ahci", "sata-ecc"; interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + status = "disabled"; + }; + + pcie1: pcie@3400000 { + compatible = "fsl,ls1028a-pcie"; + reg = <0x00 0x03400000 0x0 0x00100000>, /* controller registers */ + <0x80 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>, /* PME interrupt */ + <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; /* aer interrupt */ + interrupt-names = "pme", "aer"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + num-viewport = <8>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x80 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x80 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ status = "disabled"; };

- cluster1_core0_watchdog: wdt@c000000 { + pcie2: pcie@3500000 { + compatible = "fsl,ls1028a-pcie"; + reg = <0x00 0x03500000 0x0 0x00100000>, /* controller registers */ + <0x88 0x00000000 0x0 0x00002000>; /* configuration space */ + reg-names = "regs", "config"; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "pme", "aer"; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + dma-coherent; + num-viewport = <8>; + bus-range = <0x0 0xff>; + ranges = <0x81000000 0x0 0x00000000 0x88 0x00010000 0x0 0x00010000 /* downstream I/O */ + 0x82000000 0x0 0x40000000 0x88 0x40000000 0x0 0x40000000>; /* non-prefetchable memory */ + msi-parent = <&its>; + #interrupt-cells = <1>; + interrupt-map-mask = <0 0 0 7>; + interrupt-map = <0000 0 0 1 &gic 0 0 GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 2 &gic 0 0 GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 3 &gic 0 0 GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>, + <0000 0 0 4 &gic 0 0 GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + iommu-map = <0 &smmu 0 1>; /* Fixed-up by bootloader */ + status = "disabled"; + }; + + smmu: iommu@5000000 { + compatible = "arm,mmu-500"; + reg = <0 0x5000000 0 0x800000>; + #global-interrupts = <8>; + #iommu-cells = <1>; + stream-match-mask = <0x7c00>; + /* global secure fault */ + interrupts = <GIC_SPI 13 IRQ_TYPE_LEVEL_HIGH>, + /* combined secure interrupt */ + <GIC_SPI 14 IRQ_TYPE_LEVEL_HIGH>, + /* global non-secure fault */ + <GIC_SPI 15 IRQ_TYPE_LEVEL_HIGH>, + /* combined non-secure interrupt */ + <GIC_SPI 16 IRQ_TYPE_LEVEL_HIGH>, + /* performance counter interrupts 0-7 */ + <GIC_SPI 211 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 212 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 213 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 214 IRQ_TYPE_LEVEL_HIGH>, + /* per context interrupt, 64 interrupts */ + <GIC_SPI 146 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 148 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 149 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 151 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 157 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 158 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 159 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 160 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 161 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 162 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 163 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 164 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 165 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 166 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 167 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 168 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 169 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 170 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 171 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 172 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 173 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 174 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 175 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 176 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 177 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 178 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 179 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 180 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 181 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 182 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 183 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 184 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 185 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 186 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 187 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 188 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 189 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 199 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 200 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 201 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 202 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 203 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 204 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 205 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 206 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 207 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 208 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 209 IRQ_TYPE_LEVEL_HIGH>; + }; + + crypto: crypto@8000000 { + compatible = "fsl,sec-v5.0", "fsl,sec-v4.0"; + fsl,sec-era = <10>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00 0x8000000 0x100000>; + reg = <0x00 0x8000000 0x0 0x100000>; + interrupts = <GIC_SPI 139 IRQ_TYPE_LEVEL_HIGH>; + dma-coherent; + + sec_jr0: jr@10000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x10000 0x10000>; + interrupts = <GIC_SPI 140 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr1: jr@20000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x20000 0x10000>; + interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr2: jr@30000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x30000 0x10000>; + interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH>; + }; + + sec_jr3: jr@40000 { + compatible = "fsl,sec-v5.0-job-ring", + "fsl,sec-v4.0-job-ring"; + reg = <0x40000 0x10000>; + interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + qdma: dma-controller@8380000 { + compatible = "fsl,ls1028a-qdma", "fsl,ls1021a-qdma"; + reg = <0x0 0x8380000 0x0 0x1000>, /* Controller regs */ + <0x0 0x8390000 0x0 0x10000>, /* Status regs */ + <0x0 0x83a0000 0x0 0x40000>; /* Block regs */ + interrupts = <GIC_SPI 43 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 251 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 252 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 253 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 254 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "qdma-error", "qdma-queue0", + "qdma-queue1", "qdma-queue2", "qdma-queue3"; + dma-channels = <8>; + block-number = <1>; + block-offset = <0x10000>; + fsl,dma-queues = <2>; + status-sizes = <64>; + queue-sizes = <64 64>; + }; + + cluster1_core0_watchdog: watchdog@c000000 { compatible = "arm,sp805", "arm,primecell"; reg = <0x0 0xc000000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + cluster1_core1_watchdog: watchdog@c010000 { + compatible = "arm,sp805", "arm,primecell"; + reg = <0x0 0xc010000 0x0 0x1000>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(16)>; + clock-names = "wdog_clk", "apb_pclk"; + }; + + sai1: audio-controller@f100000 { + #sound-dai-cells = <0>; + compatible = "fsl,vf610-sai"; + reg = <0x0 0xf100000 0x0 0x10000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "tx", "rx"; + dmas = <&edma0 1 4>, + <&edma0 1 3>; + fsl,sai-asynchronous; + status = "disabled"; + }; + + sai2: audio-controller@f110000 { + #sound-dai-cells = <0>; + compatible = "fsl,vf610-sai"; + reg = <0x0 0xf110000 0x0 0x10000>; + interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "tx", "rx"; + dmas = <&edma0 1 6>, + <&edma0 1 5>; + fsl,sai-asynchronous; + status = "disabled"; + }; + + sai3: audio-controller@f120000 { + #sound-dai-cells = <0>; + compatible = "fsl,vf610-sai"; + reg = <0x0 0xf120000 0x0 0x10000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "tx", "rx"; + dmas = <&edma0 1 8>, + <&edma0 1 7>; + fsl,sai-asynchronous; + status = "disabled"; + }; + + sai4: audio-controller@f130000 { + #sound-dai-cells = <0>; + compatible = "fsl,vf610-sai"; + reg = <0x0 0xf130000 0x0 0x10000>; + interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "tx", "rx"; + dmas = <&edma0 1 10>, + <&edma0 1 9>; + fsl,sai-asynchronous; + status = "disabled"; + }; + + sai5: audio-controller@f140000 { + #sound-dai-cells = <0>; + compatible = "fsl,vf610-sai"; + reg = <0x0 0xf140000 0x0 0x10000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "tx", "rx"; + dmas = <&edma0 1 12>, + <&edma0 1 11>; + fsl,sai-asynchronous; + status = "disabled"; + }; + + sai6: audio-controller@f150000 { + #sound-dai-cells = <0>; + compatible = "fsl,vf610-sai"; + reg = <0x0 0xf150000 0x0 0x10000>; + interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>, + <&clockgen QORIQ_CLK_PLATFORM_PLL + QORIQ_CLK_PLL_DIV(2)>; + clock-names = "bus", "mclk1", "mclk2", "mclk3"; + dma-names = "tx", "rx"; + dmas = <&edma0 1 14>, + <&edma0 1 13>; + fsl,sai-asynchronous; + status = "disabled"; + }; + + tmu: tmu@1f80000 { + compatible = "fsl,qoriq-tmu"; + reg = <0x0 0x1f80000 0x0 0x10000>; + interrupts = <0 23 0x4>; + fsl,tmu-range = <0xb0000 0xa0026 0x80048 0x70061>; + fsl,tmu-calibration = <0x00000000 0x00000024 + 0x00000001 0x0000002b + 0x00000002 0x00000031 + 0x00000003 0x00000038 + 0x00000004 0x0000003f + 0x00000005 0x00000045 + 0x00000006 0x0000004c + 0x00000007 0x00000053 + 0x00000008 0x00000059 + 0x00000009 0x00000060 + 0x0000000a 0x00000066 + 0x0000000b 0x0000006d + + 0x00010000 0x0000001c + 0x00010001 0x00000024 + 0x00010002 0x0000002c + 0x00010003 0x00000035 + 0x00010004 0x0000003d + 0x00010005 0x00000045 + 0x00010006 0x0000004d + 0x00010007 0x00000055 + 0x00010008 0x0000005e + 0x00010009 0x00000066 + 0x0001000a 0x0000006e + + 0x00020000 0x00000018 + 0x00020001 0x00000022 + 0x00020002 0x0000002d + 0x00020003 0x00000038 + 0x00020004 0x00000043 + 0x00020005 0x0000004d + 0x00020006 0x00000058 + 0x00020007 0x00000063 + 0x00020008 0x0000006e + + 0x00030000 0x00000010 + 0x00030001 0x0000001c + 0x00030002 0x00000029 + 0x00030003 0x00000036 + 0x00030004 0x00000042 + 0x00030005 0x0000004f + 0x00030006 0x0000005b + 0x00030007 0x00000068>; + little-endian; + #thermal-sensor-cells = <1>; + }; + + pcie@1f0000000 { /* Integrated Endpoint Root Complex */ + compatible = "pci-host-ecam-generic"; + reg = <0x01 0xf0000000 0x0 0x100000>; + #address-cells = <3>; + #size-cells = <2>; + msi-parent = <&its>; + device_type = "pci"; + bus-range = <0x0 0x0>; + dma-coherent; + msi-map = <0 &its 0x17 0xe>; + iommu-map = <0 &smmu 0x17 0xe>; + /* PF0-6 BAR0 - non-prefetchable memory */ + ranges = <0x82000000 0x1 0xf8000000 0x1 0xf8000000 0x0 0x160000 + /* PF0-6 BAR2 - prefetchable memory */ + 0xc2000000 0x1 0xf8160000 0x1 0xf8160000 0x0 0x070000 + /* PF0: VF0-1 BAR0 - non-prefetchable memory */ + 0x82000000 0x1 0xf81d0000 0x1 0xf81d0000 0x0 0x020000 + /* PF0: VF0-1 BAR2 - prefetchable memory */ + 0xc2000000 0x1 0xf81f0000 0x1 0xf81f0000 0x0 0x020000 + /* PF1: VF0-1 BAR0 - non-prefetchable memory */ + 0x82000000 0x1 0xf8210000 0x1 0xf8210000 0x0 0x020000 + /* PF1: VF0-1 BAR2 - prefetchable memory */ + 0xc2000000 0x1 0xf8230000 0x1 0xf8230000 0x0 0x020000 + /* BAR4 (PF5) - non-prefetchable memory */ + 0x82000000 0x1 0xfc000000 0x1 0xfc000000 0x0 0x400000>; + + enetc_port0: ethernet@0,0 { + compatible = "fsl,enetc"; + reg = <0x000000 0 0 0 0>; + status = "disabled"; + }; + + enetc_port1: ethernet@0,1 { + compatible = "fsl,enetc"; + reg = <0x000100 0 0 0 0>; + status = "disabled"; + }; + + enetc_port2: ethernet@0,2 { + compatible = "fsl,enetc"; + reg = <0x000200 0 0 0 0>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + enetc_mdio_pf3: mdio@0,3 { + compatible = "fsl,enetc-mdio"; + reg = <0x000300 0 0 0 0>; + #address-cells = <1>; + #size-cells = <0>; + }; + + ethernet@0,4 { + compatible = "fsl,enetc-ptp"; + reg = <0x000400 0 0 0 0>; + clocks = <&clockgen QORIQ_CLK_HWACCEL 3>; + little-endian; + fsl,extts-fifo; + }; + + mscc_felix: ethernet-switch@0,5 { + reg = <0x000500 0 0 0 0>; + /* IEP INT_B */ + interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>; + status = "disabled"; + + ports { + #address-cells = <1>; + #size-cells = <0>; + + /* External ports */ + mscc_felix_port0: port@0 { + reg = <0>; + status = "disabled"; + }; + + mscc_felix_port1: port@1 { + reg = <1>; + status = "disabled"; + }; + + mscc_felix_port2: port@2 { + reg = <2>; + status = "disabled"; + }; + + mscc_felix_port3: port@3 { + reg = <3>; + status = "disabled"; + }; + + /* Internal ports */ + mscc_felix_port4: port@4 { + reg = <4>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <2500>; + full-duplex; + }; + }; + + mscc_felix_port5: port@5 { + reg = <5>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + }; + }; + + enetc_port3: ethernet@0,6 { + compatible = "fsl,enetc"; + reg = <0x000600 0 0 0 0>; + phy-mode = "internal"; + status = "disabled"; + + fixed-link { + speed = <1000>; + full-duplex; + }; + }; + + rcec@1f,0 { + reg = <0x00f800 0 0 0 0>; + /* IEP INT_A */ + interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + /* Integrated Endpoint Register Block */ + ierb@1f0800000 { + compatible = "fsl,ls1028a-enetc-ierb"; + reg = <0x01 0xf0800000 0x0 0x10000>; + }; + + rcpm: power-controller@1e34040 { + compatible = "fsl,ls1028a-rcpm", "fsl,qoriq-rcpm-2.1+"; + reg = <0x0 0x1e34040 0x0 0x1c>; + #fsl,rcpm-wakeup-cells = <7>; + little-endian; + }; + + ftm_alarm0: timer@2800000 { + compatible = "fsl,ls1028a-ftm-alarm"; + reg = <0x0 0x2800000 0x0 0x10000>; + fsl,rcpm-wakeup = <&rcpm 0x0 0x0 0x0 0x0 0x4000 0x0 0x0>; + interrupts = <GIC_SPI 44 IRQ_TYPE_LEVEL_HIGH>; + }; + }; + + malidp0: display@f080000 { + compatible = "arm,mali-dp500"; + reg = <0x0 0xf080000 0x0 0x10000>; + interrupts = <0 222 IRQ_TYPE_LEVEL_HIGH>, + <0 223 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "DE", "SE"; + clocks = <&dpclk>, + <&clockgen QORIQ_CLK_HWACCEL 2>, + <&clockgen QORIQ_CLK_HWACCEL 2>, + <&clockgen QORIQ_CLK_HWACCEL 2>; + clock-names = "pxlclk", "mclk", "aclk", "pclk"; + arm,malidp-output-port-lines = /bits/ 8 <8 8 8>; + arm,malidp-arqos-value = <0xd000d000>; + + port { + dp0_out: endpoint { + + }; }; }; }; diff --git a/include/dt-bindings/clock/fsl,qoriq-clockgen.h b/include/dt-bindings/clock/fsl,qoriq-clockgen.h new file mode 100644 index 0000000000..ddec7d0bdc --- /dev/null +++ b/include/dt-bindings/clock/fsl,qoriq-clockgen.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0-only */ + +#ifndef DT_CLOCK_FSL_QORIQ_CLOCKGEN_H +#define DT_CLOCK_FSL_QORIQ_CLOCKGEN_H + +#define QORIQ_CLK_SYSCLK 0 +#define QORIQ_CLK_CMUX 1 +#define QORIQ_CLK_HWACCEL 2 +#define QORIQ_CLK_FMAN 3 +#define QORIQ_CLK_PLATFORM_PLL 4 +#define QORIQ_CLK_CORECLK 5 + +#define QORIQ_CLK_PLL_DIV(x) ((x) - 1) + +#endif /* DT_CLOCK_FSL_QORIQ_CLOCKGEN_H */

Copy the board device tree files from linux v5.14. On top of the v5.14 dtbs the changes of these two patches are included here which are needed for u-boot: https://lore.kernel.org/linux-devicetree/20210831134013.1625527-7-michael@wa... https://lore.kernel.org/linux-devicetree/20210831134013.1625527-8-michael@wa...

At the time of this writing the patches are still pending but already have Reviewed-by tags.

Signed-off-by: Michael Walle michael@walle.cc --- changes since v1: - none

.../dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi | 12 +- .../arm/dts/fsl-ls1028a-kontron-sl28-var1.dts | 31 +-- .../fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi | 8 + .../arm/dts/fsl-ls1028a-kontron-sl28-var2.dts | 40 +-- .../arm/dts/fsl-ls1028a-kontron-sl28-var4.dts | 16 +- arch/arm/dts/fsl-ls1028a-kontron-sl28.dts | 250 +++++++++++++++--- 6 files changed, 265 insertions(+), 92 deletions(-)

diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi index 42bd3138b2..f80c699a3c 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-u-boot.dtsi @@ -4,12 +4,9 @@

/ { aliases { - mmc0 = &esdhc1; - mmc1 = &esdhc; i2c0 = &i2c0; i2c1 = &i2c3; i2c2 = &i2c4; - rtc0 = &rtc; ethernet2 = &enetc_port2; ethernet3 = &enetc_port3; }; @@ -234,11 +231,6 @@ }; #endif

-&i2c0 { - rtc: rtc@32 { - }; -}; - &fspi { u-boot,dm-pre-reloc; flash@0 { @@ -266,6 +258,10 @@ u-boot,dm-pre-reloc; };

+&sata { + status = "okay"; +}; + &soc { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts index ba2e4de96d..7cd29ab970 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var1.dts @@ -8,7 +8,7 @@ * None of the four SerDes lanes are used by the module, instead they are * all led out to the carrier for customer use. * - * Copyright (C) 2020 Michael Walle michael@walle.cc + * Copyright (C) 2021 Michael Walle michael@walle.cc * */

@@ -21,28 +21,17 @@ compatible = "kontron,sl28-var1", "kontron,sl28", "fsl,ls1028a"; };

-&enetc_port0 { - status = "disabled"; - /delete-property/ phy-handle; -}; - -&enetc_port1 { - phy-handle = <&phy0>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - -/delete-node/ &phy0; &enetc_mdio_pf3 { + /* Delete unused phy node */ + /delete-node/ ethernet-phy@5; + phy0: ethernet-phy@4 { reg = <0x4>; eee-broken-1000t; eee-broken-100tx; - qca,clk-out-frequency = <125000000>; qca,clk-out-strength = <AR803X_STRENGTH_FULL>; qca,keep-pll-enabled; - vddio-supply = <&vddio>;

vddio: vddio-regulator { @@ -56,3 +45,15 @@ }; }; }; + +&enetc_port0 { + status = "disabled"; + /* Delete the phy-handle to the old phy0 label */ + /delete-property/ phy-handle; +}; + +&enetc_port1 { + phy-handle = <&phy0>; + phy-mode = "rgmii-id"; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi index 4e0ce3f77d..c010ea0dc7 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2-u-boot.dtsi @@ -7,3 +7,11 @@ ethernet1 = &mscc_felix_port1; }; }; + +&mscc_felix_port0 { + label = "gbe0"; +}; + +&mscc_felix_port1 { + label = "gbe1"; +}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts index db80874f4e..330e34f933 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var2.dts @@ -2,10 +2,10 @@ /* * Device Tree file for the Kontron SMARC-sAL28 board. * - * This is for the network variant 2 which has no ethernet support in the - * bootloader. + * This is for the network variant 2 which has two ethernet ports. These + * ports are connected to the internal switch. * - * Copyright (C) 2020 Michael Walle michael@walle.cc + * Copyright (C) 2021 Michael Walle michael@walle.cc * */

@@ -17,8 +17,21 @@ compatible = "kontron,sl28-var2", "kontron,sl28", "fsl,ls1028a"; };

+&enetc_mdio_pf3 { + phy1: ethernet-phy@4 { + reg = <0x4>; + eee-broken-1000t; + eee-broken-100tx; + }; +}; + &enetc_port0 { status = "disabled"; + /* + * In the base device tree the PHY at address 5 was assigned for + * this port. On this module this PHY is connected to a switch + * port instead. Therefore, delete the phy-handle property here. + */ /delete-property/ phy-handle; };

@@ -31,14 +44,16 @@ };

&mscc_felix_port0 { - label = "gbe0"; + label = "swp0"; + managed = "in-band-status"; phy-handle = <&phy0>; phy-mode = "sgmii"; status = "okay"; };

&mscc_felix_port1 { - label = "gbe1"; + label = "swp1"; + managed = "in-band-status"; phy-handle = <&phy1>; phy-mode = "sgmii"; status = "okay"; @@ -48,18 +63,3 @@ ethernet = <&enetc_port2>; status = "okay"; }; - -/delete-node/ &phy0; -&enetc_mdio_pf3 { - phy0: ethernet-phy@5 { - reg = <0x5>; - eee-broken-1000t; - eee-broken-100tx; - }; - - phy1: ethernet-phy@4 { - reg = <0x4>; - eee-broken-1000t; - eee-broken-100tx; - }; -}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts index 54d12ab992..9b5e92fb75 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28-var4.dts @@ -5,7 +5,7 @@ * This is for the network variant 4 which has two ethernet ports. It * extends the base and provides one more port connected via RGMII. * - * Copyright (C) 2019 Michael Walle michael@walle.cc + * Copyright (C) 2021 Michael Walle michael@walle.cc * */

@@ -18,22 +18,14 @@ compatible = "kontron,sl28-var4", "kontron,sl28", "fsl,ls1028a"; };

-&enetc_port1 { - phy-handle = <&phy1>; - phy-mode = "rgmii-id"; - status = "okay"; -}; - &enetc_mdio_pf3 { phy1: ethernet-phy@4 { reg = <0x4>; eee-broken-1000t; eee-broken-100tx; - qca,clk-out-frequency = <125000000>; qca,clk-out-strength = <AR803X_STRENGTH_FULL>; qca,keep-pll-enabled; - vddio-supply = <&vddio>;

vddio: vddio-regulator { @@ -47,3 +39,9 @@ }; }; }; + +&enetc_port1 { + phy-handle = <&phy1>; + phy-mode = "rgmii-id"; + status = "okay"; +}; diff --git a/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts b/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts index 9ae70ba541..ab713b4949 100644 --- a/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts +++ b/arch/arm/dts/fsl-ls1028a-kontron-sl28.dts @@ -2,23 +2,61 @@ /* * Device Tree file for the Kontron SMARC-sAL28 board. * - * Copyright (C) 2019 Michael Walle michael@walle.cc + * Copyright (C) 2021 Michael Walle michael@walle.cc * */

/dts-v1/; #include "fsl-ls1028a.dtsi" +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/input/input.h>

/ { model = "Kontron SMARC-sAL28"; compatible = "kontron,sl28", "fsl,ls1028a";

aliases { + crypto = &crypto; serial0 = &duart0; serial1 = &duart1; serial2 = &lpuart1; spi0 = &fspi; spi1 = &dspi2; + mmc0 = &esdhc1; + mmc1 = &esdhc; + rtc0 = &rtc; + rtc1 = &ftm_alarm0; + }; + + buttons0 { + compatible = "gpio-keys"; + + power-button { + interrupts-extended = <&sl28cpld_intc + 4 IRQ_TYPE_EDGE_BOTH>; + linux,code = <KEY_POWER>; + label = "Power"; + }; + + sleep-button { + interrupts-extended = <&sl28cpld_intc + 5 IRQ_TYPE_EDGE_BOTH>; + linux,code = <KEY_SLEEP>; + label = "Sleep"; + }; + }; + + buttons1 { + compatible = "gpio-keys-polled"; + poll-interval = <200>; + + lid-switch { + linux,input-type = <EV_SW>; + linux,code = <SW_LID>; + gpios = <&sl28cpld_gpio3 4 GPIO_ACTIVE_LOW>; + label = "Lid"; + }; };

chosen { @@ -26,22 +64,35 @@ }; };

+&can0 { + status = "okay"; +}; + &dspi2 { status = "okay"; };

-&enetc_port0 { - phy-handle = <&phy0>; - phy-mode = "sgmii"; +&duart0 { + status = "okay"; +}; + +&duart1 { status = "okay"; };

-&enetc_port2 { - status = "disabled"; +&enetc_mdio_pf3 { + phy0: ethernet-phy@5 { + reg = <0x5>; + eee-broken-1000t; + eee-broken-100tx; + }; };

-&enetc_port3 { - status = "disabled"; +&enetc_port0 { + phy-handle = <&phy0>; + phy-mode = "sgmii"; + managed = "in-band-status"; + status = "okay"; };

&esdhc { @@ -63,8 +114,6 @@ status = "okay";

flash@0 { - #address-cells = <1>; - #size-cells = <1>; compatible = "jedec,spi-nor"; m25p,fast-read; spi-max-frequency = <133000000>; @@ -72,17 +121,167 @@ /* The following setting enables 1-1-2 (CMD-ADDR-DATA) mode */ spi-rx-bus-width = <2>; /* 2 SPI Rx lines */ spi-tx-bus-width = <1>; /* 1 SPI Tx line */ + + partitions { + compatible = "fixed-partitions"; + #address-cells = <1>; + #size-cells = <1>; + + partition@0 { + reg = <0x000000 0x010000>; + label = "rcw"; + read-only; + }; + + partition@10000 { + reg = <0x010000 0x1d0000>; + label = "failsafe bootloader"; + read-only; + }; + + partition@200000 { + reg = <0x200000 0x010000>; + label = "configuration store"; + }; + + partition@210000 { + reg = <0x210000 0x1d0000>; + label = "bootloader"; + }; + + partition@3e0000 { + reg = <0x3e0000 0x020000>; + label = "bootloader environment"; + }; + }; }; };

+&gpio1 { + gpio-line-names = + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "TDO", "TCK", + "", "", "", "", "", "", "", ""; +}; + +&gpio2 { + gpio-line-names = + "", "", "", "", "", "", "TMS", "TDI", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", "", + "", "", "", "", "", "", "", ""; +}; + &i2c0 { status = "okay";

- rtc@32 { + rtc: rtc@32 { compatible = "microcrystal,rv8803"; reg = <0x32>; };

+ sl28cpld@4a { + compatible = "kontron,sl28cpld"; + reg = <0x4a>; + #address-cells = <1>; + #size-cells = <0>; + + watchdog@4 { + compatible = "kontron,sl28cpld-wdt"; + reg = <0x4>; + kontron,assert-wdt-timeout-pin; + }; + + hwmon@b { + compatible = "kontron,sl28cpld-fan"; + reg = <0xb>; + }; + + sl28cpld_pwm0: pwm@c { + compatible = "kontron,sl28cpld-pwm"; + reg = <0xc>; + #pwm-cells = <2>; + }; + + sl28cpld_pwm1: pwm@e { + compatible = "kontron,sl28cpld-pwm"; + reg = <0xe>; + #pwm-cells = <2>; + }; + + sl28cpld_gpio0: gpio@10 { + compatible = "kontron,sl28cpld-gpio"; + reg = <0x10>; + interrupts-extended = <&gpio2 6 + IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "GPIO0_CAM0_PWR_N", "GPIO1_CAM1_PWR_N", + "GPIO2_CAM0_RST_N", "GPIO3_CAM1_RST_N", + "GPIO4_HDA_RST_N", "GPIO5_PWM_OUT", + "GPIO6_TACHIN", "GPIO7"; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sl28cpld_gpio1: gpio@15 { + compatible = "kontron,sl28cpld-gpio"; + reg = <0x15>; + interrupts-extended = <&gpio2 6 + IRQ_TYPE_EDGE_FALLING>; + + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "GPIO8", "GPIO9", "GPIO10", "GPIO11", + "", "", "", ""; + + interrupt-controller; + #interrupt-cells = <2>; + }; + + sl28cpld_gpio2: gpio@1a { + compatible = "kontron,sl28cpld-gpo"; + reg = <0x1a>; + + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "LCD0 voltage enable", + "LCD0 backlight enable", + "eMMC reset", "LVDS bridge reset", + "LVDS bridge power-down", + "SDIO power enable", + "", ""; + }; + + sl28cpld_gpio3: gpio@1b { + compatible = "kontron,sl28cpld-gpi"; + reg = <0x1b>; + + gpio-controller; + #gpio-cells = <2>; + gpio-line-names = + "Power button", "Force recovery", "Sleep", + "Battery low", "Lid state", "Charging", + "Charger present", ""; + }; + + sl28cpld_intc: interrupt-controller@1c { + compatible = "kontron,sl28cpld-intc"; + reg = <0x1c>; + interrupts-extended = <&gpio2 6 + IRQ_TYPE_EDGE_FALLING>; + + interrupt-controller; + #interrupt-cells = <2>; + }; + }; + eeprom@50 { compatible = "atmel,24c32"; reg = <0x50>; @@ -107,32 +306,3 @@ &lpuart1 { status = "okay"; }; - -&enetc_mdio_pf3 { - status = "okay"; - phy0: ethernet-phy@5 { - reg = <0x5>; - eee-broken-1000t; - eee-broken-100tx; - }; -}; - -&sata { - status = "okay"; -}; - -&duart0 { - status = "okay"; -}; - -&duart1 { - status = "okay"; -}; - -&usb0 { - status = "okay"; -}; - -&usb1 { - status = "okay"; -};