[U-Boot] [PATCH v2 01/15] cgtqmx6eval: Use default prompt

Remove the custom prompt and use the default instead.
Signed-off-by: Otavio Salvador otavio@ossystems.com.br ---
Changes in v2: None
include/configs/cgtqmx6eval.h | 3 --- 1 file changed, 3 deletions(-)
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index dd06c05..5f753e7 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -87,9 +87,6 @@ "fi; " \ "else echo ERR: Fail to boot from mmc; fi"
-/* Miscellaneous configurable options */ -#define CONFIG_SYS_PROMPT "CGT-QMX6-Quad U-Boot > " - /* Print Buffer Size */ #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16)

Entering the maximum number of characters defined by CONFIG_SYS_CBSIZE into the console and hitting enter afterwards, causes a hang in the system because CONFIG_SYS_PBSIZE is not capable of storing the extra characters of the error message: "Unknown command '' - try 'help'".
Use the default CONFIG_SYS_PBSIZE definition from config_fallbacks.h to solve this problem.
Signed-off-by: Otavio Salvador otavio@ossystems.com.br ---
Changes in v2: None
include/configs/cgtqmx6eval.h | 3 --- 1 file changed, 3 deletions(-)
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 5f753e7..9d9e388 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -87,9 +87,6 @@ "fi; " \ "else echo ERR: Fail to boot from mmc; fi"
-/* Print Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) - #define CONFIG_SYS_MEMTEST_START 0x10000000 #define CONFIG_SYS_MEMTEST_END 0x10010000 #define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000

Declare 'static' when possible.
Signed-off-by: Otavio Salvador otavio@ossystems.com.br ---
Changes in v2: None
board/congatec/cgtqmx6eval/cgtqmx6eval.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index 7492534..eb6395a 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -34,12 +34,12 @@ int dram_init(void) return 0; }
-iomux_v3_cfg_t const uart2_pads[] = { +static iomux_v3_cfg_t const uart2_pads[] = { MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), };
-iomux_v3_cfg_t const usdhc2_pads[] = { +static iomux_v3_cfg_t const usdhc2_pads[] = { MX6_PAD_SD2_CLK__SD2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD2_CMD__SD2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD2_DAT0__SD2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -49,7 +49,7 @@ iomux_v3_cfg_t const usdhc2_pads[] = { MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(USDHC_PAD_CTRL), };
-iomux_v3_cfg_t const usdhc4_pads[] = { +static iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_DAT0__SD4_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -69,7 +69,7 @@ static void setup_iomux_uart(void) }
#ifdef CONFIG_FSL_ESDHC -struct fsl_esdhc_cfg usdhc_cfg[] = { +static struct fsl_esdhc_cfg usdhc_cfg[] = { {USDHC2_BASE_ADDR}, {USDHC4_BASE_ADDR}, };

Perfoming an OR operation on the error is not a good approach.
Return the error immediately for each ESDHC instance instead.
Signed-off-by: Otavio Salvador otavio@ossystems.com.br ---
Changes in v2: - use ARRAY_SIZE(usdhc_cfg) (Marek)
board/congatec/cgtqmx6eval/cgtqmx6eval.c | 10 +++++++--- 1 file changed, 7 insertions(+), 3 deletions(-)
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index eb6395a..0f43d3c 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -98,6 +98,7 @@ int board_mmc_getcd(struct mmc *mmc) int board_mmc_init(bd_t *bis) { s32 status = 0; + int i;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); @@ -107,10 +108,13 @@ int board_mmc_init(bd_t *bis) imx_iomux_v3_setup_multiple_pads( usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
- status = fsl_esdhc_initialize(bis, &usdhc_cfg[0]) | - fsl_esdhc_initialize(bis, &usdhc_cfg[1]); + for (i = 0; i < ARRAY_SIZE(usdhc_cfg); i++) { + status = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (status) + return status; + }
- return status; + return 0; } #endif

There is no need to use multiple lines when they fit into a single line.
Signed-off-by: Otavio Salvador otavio@ossystems.com.br ---
Changes in v2: None
board/congatec/cgtqmx6eval/cgtqmx6eval.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index 0f43d3c..a740d95 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -103,10 +103,8 @@ int board_mmc_init(bd_t *bis) usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
- imx_iomux_v3_setup_multiple_pads( - usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); - imx_iomux_v3_setup_multiple_pads( - usdhc4_pads, ARRAY_SIZE(usdhc4_pads)); + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
for (i = 0; i < ARRAY_SIZE(usdhc_cfg); i++) { status = fsl_esdhc_initialize(bis, &usdhc_cfg[i]);

cgtqmx6eval has an eMMC connected to ESDHC3.
Add support for it.
Signed-off-by: Otavio Salvador otavio@ossystems.com.br ---
Changes in v2: - Use ARRAY_SIZE(usdhc_cfg) - Remove CONFIG_SYS_FSL_USDHC_NUM definition
board/congatec/cgtqmx6eval/cgtqmx6eval.c | 22 +++++++++++++++++++++- 1 file changed, 21 insertions(+), 1 deletion(-)
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index a740d95..e05060c 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -49,6 +49,20 @@ static iomux_v3_cfg_t const usdhc2_pads[] = { MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(USDHC_PAD_CTRL), };
+static iomux_v3_cfg_t const usdhc3_pads[] = { + MX6_PAD_SD3_CLK__SD3_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_CMD__SD3_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT0__SD3_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT1__SD3_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT2__SD3_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT3__SD3_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT4__SD3_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT5__SD3_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT6__SD3_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_DAT7__SD3_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + MX6_PAD_SD3_RST__SD3_RESET | MUX_PAD_CTRL(USDHC_PAD_CTRL), +}; + static iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_SD4_CLK__SD4_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), MX6_PAD_SD4_CMD__SD4_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), @@ -71,6 +85,7 @@ static void setup_iomux_uart(void) #ifdef CONFIG_FSL_ESDHC static struct fsl_esdhc_cfg usdhc_cfg[] = { {USDHC2_BASE_ADDR}, + {USDHC3_BASE_ADDR}, {USDHC4_BASE_ADDR}, };
@@ -84,6 +99,9 @@ int board_mmc_getcd(struct mmc *mmc) gpio_direction_input(IMX_GPIO_NR(1, 4)); ret = !gpio_get_value(IMX_GPIO_NR(1, 4)); break; + case USDHC3_BASE_ADDR: + ret = 1; /* eMMC is always present */ + break; case USDHC4_BASE_ADDR: gpio_direction_input(IMX_GPIO_NR(2, 6)); ret = !gpio_get_value(IMX_GPIO_NR(2, 6)); @@ -101,9 +119,11 @@ int board_mmc_init(bd_t *bis) int i;
usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC2_CLK); - usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(MXC_ESDHC3_CLK); + usdhc_cfg[2].sdhc_clk = mxc_get_clock(MXC_ESDHC4_CLK);
imx_iomux_v3_setup_multiple_pads(usdhc2_pads, ARRAY_SIZE(usdhc2_pads)); + imx_iomux_v3_setup_multiple_pads(usdhc3_pads, ARRAY_SIZE(usdhc3_pads)); imx_iomux_v3_setup_multiple_pads(usdhc4_pads, ARRAY_SIZE(usdhc4_pads));
for (i = 0; i < ARRAY_SIZE(usdhc_cfg); i++) {

Add board_mmc_getwp() for reading the ESDHC write-protect pin.
Signed-off-by: Otavio Salvador otavio@ossystems.com.br ---
Changes in v2: None
board/congatec/cgtqmx6eval/cgtqmx6eval.c | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+)
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index e05060c..1ae126c 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -113,6 +113,25 @@ int board_mmc_getcd(struct mmc *mmc) return ret; }
+int board_mmc_getwp(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC2_BASE_ADDR: + return -1; /* no write protection for onboard \B5SD */ + case USDHC3_BASE_ADDR: + return -1; /* no write protection for eMMC */ + case USDHC4_BASE_ADDR: + gpio_direction_input(IMX_GPIO_NR(2, 7)); + ret = gpio_get_value(IMX_GPIO_NR(2, 7)); + break; + } + + return ret; +} + int board_mmc_init(bd_t *bis) { s32 status = 0;

Add SPI NOR support:
=> sf probe SF: Detected SST25VF032B with page size 256 Bytes, erase size 4 KiB, total 4 MiB
Signed-off-by: Otavio Salvador otavio@ossystems.com.br ---
Changes in v2: None
board/congatec/cgtqmx6eval/cgtqmx6eval.c | 23 +++++++++++++++++++++++ include/configs/cgtqmx6eval.h | 10 ++++++++++ 2 files changed, 33 insertions(+)
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index 1ae126c..197bb89 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -27,6 +27,10 @@ DECLARE_GLOBAL_DATA_PTR; #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define SPI_PAD_CTRL (PAD_CTL_HYS | \ + PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -77,11 +81,24 @@ static iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ };
+static iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); }
+void setup_spinor(void) +{ + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + gpio_direction_output(IMX_GPIO_NR(3, 19), 0); +} + #ifdef CONFIG_FSL_ESDHC static struct fsl_esdhc_cfg usdhc_cfg[] = { {USDHC2_BASE_ADDR}, @@ -158,6 +175,7 @@ int board_mmc_init(bd_t *bis) int board_early_init_f(void) { setup_iomux_uart(); + setup_spinor();
return 0; } @@ -177,6 +195,11 @@ int checkboard(void) return 0; }
+int board_spi_cs_gpio(unsigned bus, unsigned cs) +{ + return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -EINVAL; +} + #ifdef CONFIG_CMD_BMODE static const struct boot_mode board_boot_modes[] = { /* 4 bit bus width */ diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 9d9e388..b0ceffc 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -29,6 +29,16 @@ /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
+/* SPI NOR */ +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SST +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0) + /* Miscellaneous commands */ #define CONFIG_CMD_BMODE

On 14 July 2015 at 00:31, Otavio Salvador otavio@ossystems.com.br wrote:
Add SPI NOR support:
=> sf probe SF: Detected SST25VF032B with page size 256 Bytes, erase size 4 KiB, total 4 MiB
Signed-off-by: Otavio Salvador otavio@ossystems.com.br
Reviewed-by: Jagan Teki jteki@openedev.com
Changes in v2: None
board/congatec/cgtqmx6eval/cgtqmx6eval.c | 23 +++++++++++++++++++++++ include/configs/cgtqmx6eval.h | 10 ++++++++++ 2 files changed, 33 insertions(+)
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index 1ae126c..197bb89 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -27,6 +27,10 @@ DECLARE_GLOBAL_DATA_PTR; #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | PAD_CTL_SPEED_LOW |\ PAD_CTL_DSE_80ohm | PAD_CTL_SRE_FAST | PAD_CTL_HYS)
+#define SPI_PAD_CTRL (PAD_CTL_HYS | \
PAD_CTL_SPEED_MED | \
PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -77,11 +81,24 @@ static iomux_v3_cfg_t const usdhc4_pads[] = { MX6_PAD_NANDF_D6__GPIO2_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), /* CD */ };
+static iomux_v3_cfg_t const ecspi1_pads[] = {
MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL),
MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL),
+};
static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); }
+void setup_spinor(void) +{
imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads));
gpio_direction_output(IMX_GPIO_NR(3, 19), 0);
+}
#ifdef CONFIG_FSL_ESDHC static struct fsl_esdhc_cfg usdhc_cfg[] = { {USDHC2_BASE_ADDR}, @@ -158,6 +175,7 @@ int board_mmc_init(bd_t *bis) int board_early_init_f(void) { setup_iomux_uart();
setup_spinor(); return 0;
} @@ -177,6 +195,11 @@ int checkboard(void) return 0; }
+int board_spi_cs_gpio(unsigned bus, unsigned cs) +{
return (bus == 0 && cs == 0) ? (IMX_GPIO_NR(3, 19)) : -EINVAL;
+}
#ifdef CONFIG_CMD_BMODE static const struct boot_mode board_boot_modes[] = { /* 4 bit bus width */ diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 9d9e388..b0ceffc 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -29,6 +29,16 @@ /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
+/* SPI NOR */ +#define CONFIG_CMD_SF +#define CONFIG_SPI_FLASH +#define CONFIG_SPI_FLASH_STMICRO +#define CONFIG_SPI_FLASH_SST +#define CONFIG_MXC_SPI +#define CONFIG_SF_DEFAULT_BUS 0 +#define CONFIG_SF_DEFAULT_SPEED 20000000 +#define CONFIG_SF_DEFAULT_MODE (SPI_MODE_0)
/* Miscellaneous commands */ #define CONFIG_CMD_BMODE
-- 2.4.5
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot

On Thu, Aug 13, 2015 at 4:07 PM, Jagan Teki jteki@openedev.com wrote:
On 14 July 2015 at 00:31, Otavio Salvador otavio@ossystems.com.br wrote:
Add SPI NOR support:
=> sf probe SF: Detected SST25VF032B with page size 256 Bytes, erase size 4 KiB, total 4 MiB
Signed-off-by: Otavio Salvador otavio@ossystems.com.br
Reviewed-by: Jagan Teki jteki@openedev.com
We will send it again as part of SPL support as we want to protect the manufactor area to avoid any bad surprise for end users.

cgtqmx6eval can be populated with a AR8035 or KSZ9031 depending on the board revision.
Add Ethernet support.
Signed-off-by: Otavio Salvador otavio@ossystems.com.br ---
Changes in v2: None
board/congatec/cgtqmx6eval/cgtqmx6eval.c | 205 +++++++++++++++++++++++++++++++ include/configs/cgtqmx6eval.h | 14 +++ 2 files changed, 219 insertions(+)
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index 197bb89..04a96e8 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -16,8 +16,11 @@ #include <asm/gpio.h> #include <asm/imx-common/iomux-v3.h> #include <asm/imx-common/boot_mode.h> +#include <malloc.h> #include <mmc.h> #include <fsl_esdhc.h> +#include <miiphy.h> +#include <netdev.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -31,6 +34,10 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST)
+#define ENET_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -88,6 +95,204 @@ static iomux_v3_cfg_t const ecspi1_pads[] = { MX6_PAD_EIM_D19__GPIO3_IO19 | MUX_PAD_CTRL(NO_PAD_CTRL), };
+static iomux_v3_cfg_t enet_pads_ksz9031[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__GPIO6_IO30 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD0__GPIO6_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD1__GPIO6_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD2__GPIO6_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RD3__GPIO6_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__GPIO6_IO24 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t enet_pads_final_ksz9031[] = { + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t enet_pads_ar8035[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +int board_eth_init(bd_t *bis) +{ + struct phy_device *phydev; + struct mii_dev *bus; + unsigned short id1, id2; + int ret; + + iomux_v3_cfg_t enet_reset = MX6_PAD_EIM_D23__GPIO3_IO23 | + MUX_PAD_CTRL(NO_PAD_CTRL); + + /* check whether KSZ9031 or AR8035 has to be configured */ + imx_iomux_v3_setup_multiple_pads(enet_pads_ar8035, + ARRAY_SIZE(enet_pads_ar8035)); + imx_iomux_v3_setup_pad(enet_reset); + + /* phy reset */ + gpio_direction_output(IMX_GPIO_NR(3, 23), 0); + udelay(2000); + gpio_set_value(IMX_GPIO_NR(3, 23), 1); + udelay(500); + + bus = fec_get_miibus(IMX_FEC_BASE, -1); + if (!bus) + return -EINVAL; + phydev = phy_find_by_mask(bus, (0xf << 4), PHY_INTERFACE_MODE_RGMII); + if (!phydev) { + printf("Error: phy device not found.\n"); + ret = -ENODEV; + goto free_bus; + } + + /* get the PHY id */ + id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); + id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); + + if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) { + /* re-configure for Micrel KSZ9031 */ + printf("configure Micrel KSZ9031 Ethernet Phy at address %d\n", + phydev->addr); + + /* phy reset: gpio3-23 */ + gpio_set_value(IMX_GPIO_NR(3, 23), 0); + gpio_set_value(IMX_GPIO_NR(6, 30), (phydev->addr >> 2)); + gpio_set_value(IMX_GPIO_NR(6, 25), 1); + gpio_set_value(IMX_GPIO_NR(6, 27), 1); + gpio_set_value(IMX_GPIO_NR(6, 28), 1); + gpio_set_value(IMX_GPIO_NR(6, 29), 1); + imx_iomux_v3_setup_multiple_pads(enet_pads_ksz9031, + ARRAY_SIZE(enet_pads_ksz9031)); + gpio_set_value(IMX_GPIO_NR(6, 24), 1); + udelay(500); + gpio_set_value(IMX_GPIO_NR(3, 23), 1); + imx_iomux_v3_setup_multiple_pads(enet_pads_final_ksz9031, + ARRAY_SIZE(enet_pads_final_ksz9031)); + } else if ((id1 == 0x004d) && (id2 == 0xd072)) { + /* configure Atheros AR8035 - actually nothing to do */ + printf("configure Atheros AR8035 Ethernet Phy at address %d\n", + phydev->addr); + } else { + printf("Unknown Ethernet-Phy: 0x%04x 0x%04x\n", id1, id2); + ret = -EINVAL; + goto free_phydev; + } + + ret = fec_probe(bis, -1, IMX_FEC_BASE, bus, phydev); + if (ret) + goto free_phydev; + + return 0; + +free_phydev: + free(phydev); +free_bus: + free(bus); + return ret; +} + +int mx6_rgmii_rework(struct phy_device *phydev) +{ + unsigned short id1, id2; + unsigned short val; + + /* check whether KSZ9031 or AR8035 has to be configured */ + id1 = phy_read(phydev, MDIO_DEVAD_NONE, 2); + id2 = phy_read(phydev, MDIO_DEVAD_NONE, 3); + + if ((id1 == 0x22) && ((id2 & 0xFFF0) == 0x1620)) { + /* finalize phy configuration for Micrel KSZ9031 */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x0d, 2); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0e, 4); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0d, 0xc002); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0e, 0x0000); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x0d, 2); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0e, 5); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0d, 0xc002); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0e, 0x0000); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x0d, 2); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0e, 6); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0d, 0xc002); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0e, 0xFFFF); + + phy_write(phydev, MDIO_DEVAD_NONE, 0x0d, 2); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0e, 8); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0d, 0xc002); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0e, 0x3FFF); + + /* fix KSZ9031 link up issue */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x0d, 0x0); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0e, 0x4); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0d, 0x4000); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0e, 0x6); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0d, 0x0000); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0e, 0x3); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0d, 0x4000); + phy_write(phydev, MDIO_DEVAD_NONE, 0x0e, 0x1A80); + } + + if ((id1 == 0x004d) && (id2 == 0xd072)) { + /* enable AR8035 ouput a 125MHz clk from CLK_25M */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x7); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= 0xfe63; + val |= 0x18; + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* introduce tx clock delay */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x5); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + val |= 0x0100; + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val); + + /* disable hibernation */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0xb); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, 0x3c40); + } + return 0; +} + +int board_phy_config(struct phy_device *phydev) +{ + mx6_rgmii_rework(phydev); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + static void setup_iomux_uart(void) { imx_iomux_v3_setup_multiple_pads(uart2_pads, ARRAY_SIZE(uart2_pads)); diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index b0ceffc..31ad366 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -42,6 +42,20 @@ /* Miscellaneous commands */ #define CONFIG_CMD_BMODE
+/* Ethernet */ +#define CONFIG_CMD_PING +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_MII +#define CONFIG_FEC_MXC +#define CONFIG_MII +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 6 + +#define CONFIG_PHYLIB +#define CONFIG_PHY_ATHEROS + #define CONFIG_DEFAULT_FDT_FILE "imx6q-congatec.dtb"
#define CONFIG_EXTRA_ENV_SETTINGS \

Add thermal support so that we can see the following message on boot:
CPU: Industrial temperature grade (-40C to 105C) at 33C
Signed-off-by: Otavio Salvador otavio@ossystems.com.br ---
Changes in v2: None
configs/cgtqmx6qeval_defconfig | 3 +++ include/configs/cgtqmx6eval.h | 8 ++++++++ 2 files changed, 11 insertions(+)
diff --git a/configs/cgtqmx6qeval_defconfig b/configs/cgtqmx6qeval_defconfig index e1eb871..6fd29a0 100644 --- a/configs/cgtqmx6qeval_defconfig +++ b/configs/cgtqmx6qeval_defconfig @@ -1,6 +1,9 @@ CONFIG_ARM=y CONFIG_TARGET_CGTQMX6EVAL=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx6eval/imximage.cfg,MX6Q" +CONFIG_CMD_NET=y +CONFIG_DM=y +CONFIG_DM_THERMAL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 31ad366..f031940 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -56,6 +56,14 @@ #define CONFIG_PHYLIB #define CONFIG_PHY_ATHEROS
+/* Thermal support */ +#define CONFIG_IMX6_THERMAL + +#define CONFIG_CMD_FUSE +#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL) +#define CONFIG_MXC_OCOTP +#endif + #define CONFIG_DEFAULT_FDT_FILE "imx6q-congatec.dtb"
#define CONFIG_EXTRA_ENV_SETTINGS \

Hi,
On 13 July 2015 at 13:01, Otavio Salvador otavio@ossystems.com.br wrote:
Add thermal support so that we can see the following message on boot:
CPU: Industrial temperature grade (-40C to 105C) at 33C
Signed-off-by: Otavio Salvador otavio@ossystems.com.br
Changes in v2: None
configs/cgtqmx6qeval_defconfig | 3 +++ include/configs/cgtqmx6eval.h | 8 ++++++++ 2 files changed, 11 insertions(+)
Reviewed-by: Simon Glass sjg@chromium.org
While you are in there, do you think you could fix the comments in thermal.h, which are mostly bogus?
diff --git a/configs/cgtqmx6qeval_defconfig b/configs/cgtqmx6qeval_defconfig index e1eb871..6fd29a0 100644 --- a/configs/cgtqmx6qeval_defconfig +++ b/configs/cgtqmx6qeval_defconfig @@ -1,6 +1,9 @@ CONFIG_ARM=y CONFIG_TARGET_CGTQMX6EVAL=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx6eval/imximage.cfg,MX6Q" +CONFIG_CMD_NET=y +CONFIG_DM=y +CONFIG_DM_THERMAL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 31ad366..f031940 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -56,6 +56,14 @@ #define CONFIG_PHYLIB #define CONFIG_PHY_ATHEROS
+/* Thermal support */ +#define CONFIG_IMX6_THERMAL
This could move to Kconfig.
+#define CONFIG_CMD_FUSE +#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL) +#define CONFIG_MXC_OCOTP +#endif
#define CONFIG_DEFAULT_FDT_FILE "imx6q-congatec.dtb"
#define CONFIG_EXTRA_ENV_SETTINGS \
2.4.5
Regards, Simon

Hi Simon,
On Mon, Jul 13, 2015 at 6:11 PM, Simon Glass sjg@chromium.org wrote:
While you are in there, do you think you could fix the comments in thermal.h, which are mostly bogus?
Just sent a patch fixing it.
+/* Thermal support */ +#define CONFIG_IMX6_THERMAL
This could move to Kconfig.
There is a patch from Peter Robinson that centralizes this config option into mx6_common.h.
Regards,
Fabio Estevam

On Mon, Jul 13, 2015 at 8:01 PM, Otavio Salvador otavio@ossystems.com.br wrote:
Add thermal support so that we can see the following message on boot:
CPU: Industrial temperature grade (-40C to 105C) at 33C
Signed-off-by: Otavio Salvador otavio@ossystems.com.br
Changes in v2: None
configs/cgtqmx6qeval_defconfig | 3 +++ include/configs/cgtqmx6eval.h | 8 ++++++++ 2 files changed, 11 insertions(+)
diff --git a/configs/cgtqmx6qeval_defconfig b/configs/cgtqmx6qeval_defconfig index e1eb871..6fd29a0 100644 --- a/configs/cgtqmx6qeval_defconfig +++ b/configs/cgtqmx6qeval_defconfig @@ -1,6 +1,9 @@ CONFIG_ARM=y CONFIG_TARGET_CGTQMX6EVAL=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/congatec/cgtqmx6eval/imximage.cfg,MX6Q" +CONFIG_CMD_NET=y +CONFIG_DM=y +CONFIG_DM_THERMAL=y # CONFIG_CMD_IMLS is not set # CONFIG_CMD_FLASH is not set # CONFIG_CMD_SETEXPR is not set diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 31ad366..f031940 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -56,6 +56,14 @@ #define CONFIG_PHYLIB #define CONFIG_PHY_ATHEROS
+/* Thermal support */ +#define CONFIG_IMX6_THERMAL
+#define CONFIG_CMD_FUSE +#if defined(CONFIG_CMD_FUSE) || defined(CONFIG_IMX6_THERMAL) +#define CONFIG_MXC_OCOTP +#endif
See my previous patch set, just resent, to centralise these in mx6_common.h as they're a standard SoC feature.
Peter

cgtqmx6eval has a PFUZE100 FSL PMIC connected to I2C2.
Add support for it.
Signed-off-by: Otavio Salvador otavio@ossystems.com.br ---
Changes in v2: - Rework indent-level for code (Marek)
board/congatec/cgtqmx6eval/cgtqmx6eval.c | 85 ++++++++++++++++++++++++++++++++ include/configs/cgtqmx6eval.h | 13 +++++ 2 files changed, 98 insertions(+)
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index 04a96e8..60e1e9a 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -16,11 +16,15 @@ #include <asm/gpio.h> #include <asm/imx-common/iomux-v3.h> #include <asm/imx-common/boot_mode.h> +#include <asm/imx-common/mxc_i2c.h> #include <malloc.h> #include <mmc.h> #include <fsl_esdhc.h> #include <miiphy.h> #include <netdev.h> +#include <i2c.h> +#include <power/pmic.h> +#include <power/pfuze100_pmic.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -38,6 +42,13 @@ DECLARE_GLOBAL_DATA_PTR; PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
+#define I2C_PAD_CTRL (PAD_CTL_PKE | PAD_CTL_PUE | \ + PAD_CTL_PUS_100K_UP | PAD_CTL_SPEED_MED | \ + PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ + PAD_CTL_ODE | PAD_CTL_SRE_FAST) + +#define MX6Q_QMX6_PFUZE_MUX IMX_GPIO_NR(6, 9) + int dram_init(void) { gd->ram_size = get_ram_size((void *)PHYS_SDRAM, PHYS_SDRAM_SIZE); @@ -140,6 +151,78 @@ static iomux_v3_cfg_t enet_pads_ar8035[] = { MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), };
+#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, + .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, + .gp = IMX_GPIO_NR(4, 12) + }, + .sda = { + .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, + .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, + .gp = IMX_GPIO_NR(4, 13) + } +}; + +#define I2C_PMIC 1 /* I2C2 port is used to connect to the PMIC */ + +struct interface_level { + char *name; + uchar value; +}; + +static struct interface_level mipi_levels[] = { + {"0V0", 0x00}, + {"2V5", 0x17}, +}; + +/* setup board specific PMIC */ +int power_init_board(void) +{ + struct pmic *p; + u32 id1, id2, i; + int ret; + char const *lv_mipi; + + /* configure I2C multiplexer */ + gpio_direction_output(MX6Q_QMX6_PFUZE_MUX, 1); + + power_pfuze100_init(I2C_PMIC); + p = pmic_get("PFUZE100"); + if (!p) + return -EINVAL; + + ret = pmic_probe(p); + if (ret) + return ret; + + pmic_reg_read(p, PFUZE100_DEVICEID, &id1); + pmic_reg_read(p, PFUZE100_REVID, &id2); + printf("PFUZE100 Rev. [%02x/%02x] detected\n", id1, id2); + + if (id2 >= 0x20) + return 0; + + /* set level of MIPI if specified */ + lv_mipi = getenv("lv_mipi"); + if (lv_mipi) + return 0; + + for (i = 0; i < ARRAY_SIZE(mipi_levels); i++) { + if (!strcmp(mipi_levels[i].name, lv_mipi)) { + printf("set MIPI level %s\n", + mipi_levels[i].name); + ret = pmic_reg_write(p, PFUZE100_VGEN4VOL, + mipi_levels[i].value); + if (ret) + return ret; + } + } + + return 0; +} + int board_eth_init(bd_t *bis) { struct phy_device *phydev; @@ -390,6 +473,8 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
+ setup_i2c(1, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + return 0; }
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index f031940..df22534 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -64,6 +64,19 @@ #define CONFIG_MXC_OCOTP #endif
+/* I2C Configs */ +#define CONFIG_CMD_I2C +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_SPEED 100000 + +/* PMIC */ +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#define CONFIG_POWER_PFUZE100 +#define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08 + #define CONFIG_DEFAULT_FDT_FILE "imx6q-congatec.dtb"
#define CONFIG_EXTRA_ENV_SETTINGS \

Add USB support.
Signed-off-by: Otavio Salvador otavio@ossystems.com.br ---
Changes in v2: - Use plan gpio API call (Marek)
board/congatec/cgtqmx6eval/cgtqmx6eval.c | 44 ++++++++++++++++++++++++++++++++ include/configs/cgtqmx6eval.h | 15 +++++++++++ 2 files changed, 59 insertions(+)
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index 60e1e9a..812f7bb 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -151,6 +151,11 @@ static iomux_v3_cfg_t enet_pads_ar8035[] = { MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), };
+static iomux_v3_cfg_t const usb_otg_pads[] = { + MX6_PAD_EIM_D22__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + #define PC MUX_PAD_CTRL(I2C_PAD_CTRL) struct i2c_pads_info i2c_pad_info1 = { .scl = { @@ -460,6 +465,45 @@ int board_mmc_init(bd_t *bis) } #endif
+int board_ehci_hcd_init(int port) +{ + switch (port) { + case 0: + imx_iomux_v3_setup_multiple_pads(usb_otg_pads, + ARRAY_SIZE(usb_otg_pads)); + /* + * set daisy chain for otg_pin_id on 6q. + * for 6dl, this bit is reserved + */ + imx_iomux_set_gpr_register(1, 13, 1, 0); + break; + case 1: + /* nothing to do */ + break; + default: + printf("Invalid USB port: %d\n", port); + return -EINVAL; + } + + return 0; +} + +int board_ehci_power(int port, int on) +{ + switch (port) { + case 0: + break; + case 1: + gpio_direction_output(IMX_GPIO_NR(5, 5), on); + break; + default: + printf("Invalid USB port: %d\n", port); + return -EINVAL; + } + + return 0; +} + int board_early_init_f(void) { setup_iomux_uart(); diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index df22534..ce995a8 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -77,6 +77,21 @@ #define CONFIG_POWER_PFUZE100 #define CONFIG_POWER_PFUZE100_I2C_ADDR 0x08
+/* USB Configs */ +#define CONFIG_CMD_USB +#define CONFIG_CMD_FAT +#define CONFIG_USB_EHCI +#define CONFIG_USB_EHCI_MX6 +#define CONFIG_USB_STORAGE +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 /* Enabled USB controller number */ +#define CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP + #define CONFIG_DEFAULT_FDT_FILE "imx6q-congatec.dtb"
#define CONFIG_EXTRA_ENV_SETTINGS \

Add LVDS and HDMI support.
Signed-off-by: Otavio Salvador otavio@ossystems.com.br ---
Changes in v2: - Rework code to use setbits_le32 (Marek)
board/congatec/cgtqmx6eval/cgtqmx6eval.c | 173 +++++++++++++++++++++++++++++++ include/configs/cgtqmx6eval.h | 20 ++++ 2 files changed, 193 insertions(+)
diff --git a/board/congatec/cgtqmx6eval/cgtqmx6eval.c b/board/congatec/cgtqmx6eval/cgtqmx6eval.c index 812f7bb..a926b0d 100644 --- a/board/congatec/cgtqmx6eval/cgtqmx6eval.c +++ b/board/congatec/cgtqmx6eval/cgtqmx6eval.c @@ -17,6 +17,8 @@ #include <asm/imx-common/iomux-v3.h> #include <asm/imx-common/boot_mode.h> #include <asm/imx-common/mxc_i2c.h> +#include <asm/arch/mxc_hdmi.h> +#include <asm/arch/crm_regs.h> #include <malloc.h> #include <mmc.h> #include <fsl_esdhc.h> @@ -25,6 +27,8 @@ #include <i2c.h> #include <power/pmic.h> #include <power/pfuze100_pmic.h> +#include <linux/fb.h> +#include <ipu_pixfmt.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -504,10 +508,179 @@ int board_ehci_power(int port, int on) return 0; }
+struct display_info_t { + int bus; + int addr; + int pixfmt; + int (*detect)(struct display_info_t const *dev); + void (*enable)(struct display_info_t const *dev); + struct fb_videomode mode; +}; + +static void disable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + + clrbits_le32(&iomux->gpr[2], IOMUXC_GPR2_LVDS_CH0_MODE_MASK | + IOMUXC_GPR2_LVDS_CH1_MODE_MASK); +} + +static void do_enable_hdmi(struct display_info_t const *dev) +{ + disable_lvds(dev); + imx_enable_hdmi_phy(); +} + +static struct display_info_t const displays[] = { +{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB666, + .detect = NULL, + .enable = NULL, + .mode = { + .name = + "Hannstar-XGA", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED } }, +{ + .bus = -1, + .addr = 0, + .pixfmt = IPU_PIX_FMT_RGB24, + .detect = NULL, + .enable = do_enable_hdmi, + .mode = { + .name = "HDMI", + .refresh = 60, + .xres = 1024, + .yres = 768, + .pixclock = 15385, + .left_margin = 220, + .right_margin = 40, + .upper_margin = 21, + .lower_margin = 7, + .hsync_len = 60, + .vsync_len = 10, + .sync = FB_SYNC_EXT, + .vmode = FB_VMODE_NONINTERLACED } } +}; + +int board_video_skip(void) +{ + int i; + int ret; + char const *panel = getenv("panel"); + if (!panel) { + for (i = 0; i < ARRAY_SIZE(displays); i++) { + struct display_info_t const *dev = displays + i; + if (dev->detect && dev->detect(dev)) { + panel = dev->mode.name; + printf("auto-detected panel %s\n", panel); + break; + } + } + if (!panel) { + panel = displays[0].mode.name; + printf("No panel detected: default to %s\n", panel); + i = 0; + } + } else { + for (i = 0; i < ARRAY_SIZE(displays); i++) { + if (!strcmp(panel, displays[i].mode.name)) + break; + } + } + if (i < ARRAY_SIZE(displays)) { + ret = ipuv3_fb_init(&displays[i].mode, 0, displays[i].pixfmt); + if (!ret) { + if (displays[i].enable) + displays[i].enable(displays + i); + printf("Display: %s (%ux%u)\n", + displays[i].mode.name, displays[i].mode.xres, + displays[i].mode.yres); + } else + printf("LCD %s cannot be configured: %d\n", + displays[i].mode.name, ret); + } else { + printf("unsupported panel %s\n", panel); + return -EINVAL; + } + + return 0; +} + +static void setup_display(void) +{ + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + int reg; + + enable_ipu_clock(); + imx_setup_hdmi(); + + /* Turn on LDB0, LDB1, IPU,IPU DI0 clocks */ + setbits_le32(&mxc_ccm->CCGR3, MXC_CCM_CCGR3_LDB_DI0_MASK | + MXC_CCM_CCGR3_LDB_DI1_MASK); + + /* set LDB0, LDB1 clk select to 011/011 */ + reg = readl(&mxc_ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK | + MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (3 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) | + (3 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &mxc_ccm->cs2cdr); + + setbits_le32(&mxc_ccm->cscmr2, MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV | + MXC_CCM_CSCMR2_LDB_DI1_IPU_DIV); + + setbits_le32(&mxc_ccm->chsccdr, CHSCCDR_CLK_SEL_LDB_DI0 << + MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET | + CHSCCDR_CLK_SEL_LDB_DI0 << + MXC_CCM_CHSCCDR_IPU1_DI1_CLK_SEL_OFFSET); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_LOW + | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_LOW + | IOMUXC_GPR2_BIT_MAPPING_CH1_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH1_18BIT + | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH0_18BIT + | IOMUXC_GPR2_LVDS_CH0_MODE_DISABLED + | IOMUXC_GPR2_LVDS_CH1_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~(IOMUXC_GPR3_LVDS1_MUX_CTL_MASK | + IOMUXC_GPR3_HDMI_MUX_CTL_MASK)) | + (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << + IOMUXC_GPR3_LVDS1_MUX_CTL_OFFSET); + writel(reg, &iomux->gpr[3]); +} + +/* + * Do not overwrite the console + * Use always serial for U-Boot console + */ +int overwrite_console(void) +{ + return 1; +} + int board_early_init_f(void) { setup_iomux_uart(); setup_spinor(); + setup_display();
return 0; } diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index ce995a8..5c72d34 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -92,6 +92,26 @@ #define CONFIG_USB_KEYBOARD #define CONFIG_SYS_USB_EVENT_POLL_VIA_CONTROL_EP
+/* Framebuffer */ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_IPUV3 +#define CONFIG_CFB_CONSOLE +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SYS_CONSOLE_IS_IN_ENV +#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#ifdef CONFIG_MX6DL +#define CONFIG_IPUV3_CLK 198000000 +#else +#define CONFIG_IPUV3_CLK 264000000 +#endif +#define CONFIG_IMX_HDMI + #define CONFIG_DEFAULT_FDT_FILE "imx6q-congatec.dtb"
#define CONFIG_EXTRA_ENV_SETTINGS \

Add SATA support.
Signed-off-by: Otavio Salvador otavio@ossystems.com.br ---
Changes in v2: None
include/configs/cgtqmx6eval.h | 9 +++++++++ 1 file changed, 9 insertions(+)
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index 5c72d34..d4b1538 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -112,6 +112,15 @@ #endif #define CONFIG_IMX_HDMI
+/* SATA */ +#define CONFIG_CMD_SATA +#define CONFIG_DWC_AHSATA +#define CONFIG_SYS_SATA_MAX_DEVICE 1 +#define CONFIG_DWC_AHSATA_PORT_ID 0 +#define CONFIG_DWC_AHSATA_BASE_ADDR SATA_ARB_BASE_ADDR +#define CONFIG_LBA48 +#define CONFIG_LIBATA + #define CONFIG_DEFAULT_FDT_FILE "imx6q-congatec.dtb"
#define CONFIG_EXTRA_ENV_SETTINGS \

Use more standard boot scripts and also add the capability of booting via NFS.
Signed-off-by: Otavio Salvador otavio@ossystems.com.br ---
Changes in v2: None
include/configs/cgtqmx6eval.h | 94 ++++++++++++++++++++++++++++++------------- 1 file changed, 66 insertions(+), 28 deletions(-)
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index d4b1538..ac8c15a 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -121,36 +121,75 @@ #define CONFIG_LBA48 #define CONFIG_LIBATA
-#define CONFIG_DEFAULT_FDT_FILE "imx6q-congatec.dtb" +/* Command definition */ + +#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_CONSOLE_DEV "ttymxc1" +#define CONFIG_MMCROOT "/dev/mmcblk0p2" +#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \ - "fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \ - "boot_dir=/boot\0" \ - "console=ttymxc1\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "fdt_addr=0x18000000\0" \ + "fdtfile=imx6q-qmx6.dtb\0" \ + "fdt_addr_r=0x18000000\0" \ "boot_fdt=try\0" \ - "mmcdev=1\0" \ + "ip_dyn=yes\0" \ + "console=" CONFIG_CONSOLE_DEV "\0" \ + "bootm_size=0x10000000\0" \ + "mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=1\0" \ - "mmcroot=/dev/mmcblk0p1 rootwait rw\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "update_sd_firmware=" \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "if mmc dev ${mmcdev}; then " \ + "if ${get_cmd} ${update_sd_firmware_filename}; then " \ + "setexpr fw_sz ${filesize} / 0x200; " \ + "setexpr fw_sz ${fw_sz} + 1; " \ + "mmc write ${loadaddr} 0x2 ${fw_sz}; " \ + "fi; " \ + "fi\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ "loadbootscript=" \ - "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ - "loadimage=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ - "${boot_dir}/${image}\0" \ - "loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdt_addr} " \ - "${boot_dir}/${fdt_file}\0" \ + "loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \ + "loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \ - "bootz ${loadaddr} - ${fdt_addr}; " \ + "bootz ${loadaddr} - ${fdt_addr_r}; " \ + "else " \ + "if test ${boot_fdt} = try; then " \ + "bootz; " \ + "else " \ + "echo WARN: Cannot load the DT; " \ + "fi; " \ + "fi; " \ + "else " \ + "bootz; " \ + "fi;\0" \ + "netargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/nfs " \ + "ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \ + "netboot=echo Booting from net ...; " \ + "run netargs; " \ + "if test ${ip_dyn} = yes; then " \ + "setenv get_cmd dhcp; " \ + "else " \ + "setenv get_cmd tftp; " \ + "fi; " \ + "${get_cmd} ${image}; " \ + "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ + "if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \ + "bootz ${loadaddr} - ${fdt_addr_r}; " \ "else " \ "if test ${boot_fdt} = try; then " \ "bootz; " \ @@ -160,21 +199,20 @@ "fi; " \ "else " \ "bootz; " \ - "fi;\0" + "fi;\0" \
#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "mmc dev ${mmcdev}; if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run loadimage; then " \ - "run mmcboot; " \ - "else "\ - "echo ERR: Fail to boot from mmc; " \ - "fi; " \ - "fi; " \ - "else echo ERR: Fail to boot from mmc; fi" + "mmc dev ${mmcdev};" \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run loadimage; then " \ + "run mmcboot; " \ + "else run netboot; " \ + "fi; " \ + "fi; " \ + "else run netboot; fi"
#define CONFIG_SYS_MEMTEST_START 0x10000000 #define CONFIG_SYS_MEMTEST_END 0x10010000

On Mon, Jul 13, 2015 at 8:01 PM, Otavio Salvador otavio@ossystems.com.br wrote:
Use more standard boot scripts and also add the capability of booting via NFS.
It would actually be useful I think if you used the distro defaults support for booting here
Peter
Signed-off-by: Otavio Salvador otavio@ossystems.com.br
Changes in v2: None
include/configs/cgtqmx6eval.h | 94 ++++++++++++++++++++++++++++++------------- 1 file changed, 66 insertions(+), 28 deletions(-)
diff --git a/include/configs/cgtqmx6eval.h b/include/configs/cgtqmx6eval.h index d4b1538..ac8c15a 100644 --- a/include/configs/cgtqmx6eval.h +++ b/include/configs/cgtqmx6eval.h @@ -121,36 +121,75 @@ #define CONFIG_LBA48 #define CONFIG_LIBATA
-#define CONFIG_DEFAULT_FDT_FILE "imx6q-congatec.dtb" +/* Command definition */
+#define CONFIG_MXC_UART_BASE UART2_BASE +#define CONFIG_CONSOLE_DEV "ttymxc1" +#define CONFIG_MMCROOT "/dev/mmcblk0p2" +#define CONFIG_SYS_MMC_ENV_DEV 0
#define CONFIG_EXTRA_ENV_SETTINGS \ "script=boot.scr\0" \ "image=zImage\0" \
"fdt_file=" CONFIG_DEFAULT_FDT_FILE "\0" \
"boot_dir=/boot\0" \
"console=ttymxc1\0" \
"fdt_high=0xffffffff\0" \
"initrd_high=0xffffffff\0" \
"fdt_addr=0x18000000\0" \
"fdtfile=imx6q-qmx6.dtb\0" \
"fdt_addr_r=0x18000000\0" \ "boot_fdt=try\0" \
"mmcdev=1\0" \
"ip_dyn=yes\0" \
"console=" CONFIG_CONSOLE_DEV "\0" \
"bootm_size=0x10000000\0" \
"mmcdev=" __stringify(CONFIG_SYS_MMC_ENV_DEV) "\0" \ "mmcpart=1\0" \
"mmcroot=/dev/mmcblk0p1 rootwait rw\0" \
"mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \
"update_sd_firmware=" \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"if mmc dev ${mmcdev}; then " \
"if ${get_cmd} ${update_sd_firmware_filename}; then " \
"setexpr fw_sz ${filesize} / 0x200; " \
"setexpr fw_sz ${fw_sz} + 1; " \
"mmc write ${loadaddr} 0x2 ${fw_sz}; " \
"fi; " \
"fi\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ "loadbootscript=" \
"ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \
"fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \
"loadimage=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \
"${boot_dir}/${image}\0" \
"loadfdt=ext2load mmc ${mmcdev}:${mmcpart} ${fdt_addr} " \
"${boot_dir}/${fdt_file}\0" \
"loadimage=fatload mmc ${mmcdev}:${mmcpart} ${loadaddr} ${image}\0" \
"loadfdt=fatload mmc ${mmcdev}:${mmcpart} ${fdt_addr_r} ${fdtfile}\0" \ "mmcboot=echo Booting from mmc ...; " \ "run mmcargs; " \ "if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \ "if run loadfdt; then " \
"bootz ${loadaddr} - ${fdt_addr}; " \
"bootz ${loadaddr} - ${fdt_addr_r}; " \
"else " \
"if test ${boot_fdt} = try; then " \
"bootz; " \
"else " \
"echo WARN: Cannot load the DT; " \
"fi; " \
"fi; " \
"else " \
"bootz; " \
"fi;\0" \
"netargs=setenv bootargs console=${console},${baudrate} " \
"root=/dev/nfs " \
"ip=dhcp nfsroot=${serverip}:${nfsroot},v3,tcp\0" \
"netboot=echo Booting from net ...; " \
"run netargs; " \
"if test ${ip_dyn} = yes; then " \
"setenv get_cmd dhcp; " \
"else " \
"setenv get_cmd tftp; " \
"fi; " \
"${get_cmd} ${image}; " \
"if test ${boot_fdt} = yes || test ${boot_fdt} = try; then " \
"if ${get_cmd} ${fdt_addr_r} ${fdtfile}; then " \
"bootz ${loadaddr} - ${fdt_addr_r}; " \ "else " \ "if test ${boot_fdt} = try; then " \ "bootz; " \
@@ -160,21 +199,20 @@ "fi; " \ "else " \ "bootz; " \
"fi;\0"
"fi;\0" \
#define CONFIG_BOOTCOMMAND \
"mmc dev ${mmcdev};" \
"mmc dev ${mmcdev}; if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loadimage; then " \
"run mmcboot; " \
"else "\
"echo ERR: Fail to boot from mmc; " \
"fi; " \
"fi; " \
"else echo ERR: Fail to boot from mmc; fi"
"mmc dev ${mmcdev};" \
"if mmc rescan; then " \
"if run loadbootscript; then " \
"run bootscript; " \
"else " \
"if run loadimage; then " \
"run mmcboot; " \
"else run netboot; " \
"fi; " \
"fi; " \
"else run netboot; fi"
#define CONFIG_SYS_MEMTEST_START 0x10000000
#define CONFIG_SYS_MEMTEST_END 0x10010000
2.4.5

On Mon, Jul 13, 2015 at 8:56 PM, Peter Robinson pbrobinson@gmail.com wrote:
On Mon, Jul 13, 2015 at 8:01 PM, Otavio Salvador otavio@ossystems.com.br wrote:
Use more standard boot scripts and also add the capability of booting via NFS.
It would actually be useful I think if you used the distro defaults support for booting here
Yes; agreed but this will be done afterwards. We need to add this support at OE-Core to be able to use it here.
participants (6)
-
Fabio Estevam
-
Jagan Teki
-
Otavio Salvador
-
Otavio Salvador
-
Peter Robinson
-
Simon Glass