[U-Boot] [PATCH 0/2] ARM: mmu: Set domain permissions to client access
Currently for ARM based cpu's, mmu pagetable attributes are set with manager permissions for all 4GB address space. Because of this the 'execute never (XN)' permission is never checked on read sensitive regions which results in speculative aborts.
This series changes the domain permissions of the full 4GB space to client access for OMAP socs. This avoids all the speculative aborts that are currently seen on OMAP5 secure devices.
Tested on OMAP5 SDP (HS) soc.
This series depends on [1] the patch sent by <Vincent Stehle v-stehle@ti.com
[1] http://www.mail-archive.com/u-boot@lists.denx.de/msg102709.html
R Sricharan (2): ARM: mmu: Introduce weak dram_bank_setup function ARM: mmu: Set domain permissions to client access
arch/arm/cpu/armv7/cache_v7.c | 3 ++ arch/arm/cpu/armv7/omap-common/hwinit-common.c | 35 ++++++++++++++++++++++++ arch/arm/include/asm/cache.h | 1 + arch/arm/include/asm/system.h | 14 ++++++++++ arch/arm/lib/cache-cp15.c | 13 ++++++++- 5 files changed, 65 insertions(+), 1 deletion(-)
Introduce a weak version of dram_bank_setup function to allow a platform specific function.
This is used in the subsequent patch to setup dram region without 'XN' attribute in order to enable the region under client permissions.
Signed-off-by: R Sricharan r.sricharan@ti.com Cc: Vincent Stehle v-stehle@ti.com Cc: Tom Rini trini@ti.com --- arch/arm/include/asm/cache.h | 1 + arch/arm/lib/cache-cp15.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index eef6a5a..93811d2 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -42,6 +42,7 @@ static inline void invalidate_l2_cache(void) void l2_cache_enable(void); void l2_cache_disable(void);
+void dram_bank_mmu_setup(int bank); /* * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We * use that value for aligning DMA buffers unless the board config has specified diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 6edf815..3e5de55 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -23,6 +23,8 @@
#include <common.h> #include <asm/system.h> +#include <asm/cache.h> +#include <linux/compiler.h>
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
@@ -77,7 +79,7 @@ void mmu_set_region_dcache_behaviour(u32 start, int size, mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); }
-static inline void dram_bank_mmu_setup(int bank) +__weak void dram_bank_mmu_setup(int bank) { bd_t *bd = gd->bd; int i;
Introduce a weak version of dram_bank_setup function to allow a platform specific function.
This is used in the subsequent patch to setup dram region without 'XN' attribute in order to enable the region under client permissions.
Signed-off-by: R Sricharan r.sricharan@ti.com Cc: Vincent Stehle v-stehle@ti.com Cc: Tom Rini trini@ti.com --- arch/arm/include/asm/cache.h | 1 + arch/arm/lib/cache-cp15.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index eef6a5a..93811d2 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -42,6 +42,7 @@ static inline void invalidate_l2_cache(void) void l2_cache_enable(void); void l2_cache_disable(void);
+void dram_bank_mmu_setup(int bank); /* * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We * use that value for aligning DMA buffers unless the board config has specified diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 6edf815..3e5de55 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -23,6 +23,8 @@
#include <common.h> #include <asm/system.h> +#include <asm/cache.h> +#include <linux/compiler.h>
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
@@ -77,7 +79,7 @@ void mmu_set_region_dcache_behaviour(u32 start, int size, mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); }
-static inline void dram_bank_mmu_setup(int bank) +__weak void dram_bank_mmu_setup(int bank) { bd_t *bd = gd->bd; int i;
The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client.
This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices.
Signed-off-by: R Sricharan r.sricharan@ti.com Tested-by: Vincent Stehle v-stehle@ti.com Cc: Vincent Stehle v-stehle@ti.com Cc: Tom Rini trini@ti.com --- arch/arm/cpu/armv7/cache_v7.c | 3 ++ arch/arm/cpu/armv7/omap-common/hwinit-common.c | 35 ++++++++++++++++++++++++ arch/arm/include/asm/system.h | 14 ++++++++++ arch/arm/lib/cache-cp15.c | 7 +++++ 4 files changed, 59 insertions(+)
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 5f6d039..8748c14 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -340,6 +340,9 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop) { }
+void arm_init_domains(void) +{ +} #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
#ifndef CONFIG_SYS_ICACHE_OFF diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 9ef10bd..4eaf75b 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -32,6 +32,12 @@ #include <asm/arch/sys_proto.h> #include <asm/sizes.h> #include <asm/emif.h> +#include <asm/cache.h> +#include <asm/system.h> + +#define ARMV7_DCACHE_WRITEBACK 0xe +#define ARMV7_DOMAIN_CLIENT 1 +#define ARMV7_DOMAIN_MASK (0x3 << 0)
DECLARE_GLOBAL_DATA_PTR;
@@ -258,4 +264,33 @@ void enable_caches(void) /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); } + +void dram_bank_mmu_setup(int bank) +{ + bd_t *bd = gd->bd; + int i; + + u32 start = bd->bi_dram[bank].start >> 20; + u32 size = bd->bi_dram[bank].size >> 20; + u32 end = start + size; + + debug("%s: bank: %d\n", __func__, bank); + for (i = start; i < end; i++) + set_section_dcache(i, ARMV7_DCACHE_WRITEBACK); + +} + +void arm_init_domains(void) +{ + u32 reg; + + reg = get_dacr(); + /* + * Set DOMAIN to client access so that all permissions + * set in pagetables are validated by the mmu. + */ + reg &= ~ARMV7_DOMAIN_MASK; + reg |= ARMV7_DOMAIN_CLIENT; + set_dacr(reg); +} #endif diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 78ca8e0..9cfbb17 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -75,6 +75,20 @@ static inline void set_cr(unsigned int val) isb(); }
+static inline unsigned int get_dacr(void) +{ + unsigned int val; + asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc"); + return val; +} + +static inline void set_dacr(unsigned int val) +{ + asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR" + : : "r" (val) : "cc"); + isb(); +} + /* options available for data cache on each page */ enum dcache_option { DCACHE_OFF = 0x12, diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 3e5de55..0852f40 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -36,6 +36,10 @@ void __arm_init_before_mmu(void) void arm_init_before_mmu(void) __attribute__((weak, alias("__arm_init_before_mmu")));
+__weak void arm_init_domains(void) +{ +} + static void cp_delay (void) { volatile int i; @@ -117,6 +121,9 @@ static inline void mmu_setup(void) /* Set the access control to all-supervisor */ asm volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (~0)); + + arm_init_domains(); + /* and enable the mmu */ reg = get_cr(); /* get control reg. */ cp_delay();
Hi R Sicharan, Vincent,
On Tue, 8 Jan 2013 23:38:22 +0530, R Sricharan r.sricharan@ti.com wrote:
Currently for ARM based cpu's, mmu pagetable attributes are set with manager permissions for all 4GB address space. Because of this the 'execute never (XN)' permission is never checked on read sensitive regions which results in speculative aborts.
This series changes the domain permissions of the full 4GB space to client access for OMAP socs. This avoids all the speculative aborts that are currently seen on OMAP5 secure devices.
Tested on OMAP5 SDP (HS) soc.
This series depends on [1] the patch sent by <Vincent Stehle v-stehle@ti.com
[1] http://www.mail-archive.com/u-boot@lists.denx.de/msg102709.html
R Sricharan (2): ARM: mmu: Introduce weak dram_bank_setup function ARM: mmu: Set domain permissions to client access
arch/arm/cpu/armv7/cache_v7.c | 3 ++ arch/arm/cpu/armv7/omap-common/hwinit-common.c | 35 ++++++++++++++++++++++++ arch/arm/include/asm/cache.h | 1 + arch/arm/include/asm/system.h | 14 ++++++++++ arch/arm/lib/cache-cp15.c | 13 ++++++++- 5 files changed, 65 insertions(+), 1 deletion(-)
Does that mean the rest of Vincent's patch set is not needed any more?
Amicalement,
Hi,
On Sunday 03 February 2013 07:47 PM, Albert ARIBAUD wrote:
Hi R Sicharan, Vincent,
On Tue, 8 Jan 2013 23:38:22 +0530, R Sricharan r.sricharan@ti.com wrote:
Currently for ARM based cpu's, mmu pagetable attributes are set with manager permissions for all 4GB address space. Because of this the 'execute never (XN)' permission is never checked on read sensitive regions which results in speculative aborts.
This series changes the domain permissions of the full 4GB space to client access for OMAP socs. This avoids all the speculative aborts that are currently seen on OMAP5 secure devices.
Tested on OMAP5 SDP (HS) soc.
This series depends on [1] the patch sent by <Vincent Stehle v-stehle@ti.com
[1] http://www.mail-archive.com/u-boot@lists.denx.de/msg102709.html
R Sricharan (2): ARM: mmu: Introduce weak dram_bank_setup function ARM: mmu: Set domain permissions to client access
arch/arm/cpu/armv7/cache_v7.c | 3 ++ arch/arm/cpu/armv7/omap-common/hwinit-common.c | 35 ++++++++++++++++++++++++ arch/arm/include/asm/cache.h | 1 + arch/arm/include/asm/system.h | 14 ++++++++++ arch/arm/lib/cache-cp15.c | 13 ++++++++- 5 files changed, 65 insertions(+), 1 deletion(-)
Does that mean the rest of Vincent's patch set is not needed any more?
Except for one patch that i have mentioned, rest are needed
http://www.mail-archive.com/u-boot@lists.denx.de/msg102709.html
Regards, Sricharan
Hi, On Sunday 03 February 2013 07:49 PM, R Sricharan wrote:
Hi,
On Sunday 03 February 2013 07:47 PM, Albert ARIBAUD wrote:
Hi R Sicharan, Vincent,
On Tue, 8 Jan 2013 23:38:22 +0530, R Sricharan r.sricharan@ti.com wrote: i meant
Currently for ARM based cpu's, mmu pagetable attributes are set with manager permissions for all 4GB address space. Because of this the 'execute never (XN)' permission is never checked on read sensitive regions which results in speculative aborts.
This series changes the domain permissions of the full 4GB space to client access for OMAP socs. This avoids all the speculative aborts that are currently seen on OMAP5 secure devices.
Tested on OMAP5 SDP (HS) soc.
This series depends on [1] the patch sent by <Vincent Stehle v-stehle@ti.com
[1] http://www.mail-archive.com/u-boot@lists.denx.de/msg102709.html
R Sricharan (2): ARM: mmu: Introduce weak dram_bank_setup function ARM: mmu: Set domain permissions to client access
arch/arm/cpu/armv7/cache_v7.c | 3 ++ arch/arm/cpu/armv7/omap-common/hwinit-common.c | 35 ++++++++++++++++++++++++ arch/arm/include/asm/cache.h | 1 + arch/arm/include/asm/system.h | 14 ++++++++++ arch/arm/lib/cache-cp15.c | 13 ++++++++- 5 files changed, 65 insertions(+), 1 deletion(-)
Does that mean the rest of Vincent's patch set is not needed any more?
Except for one patch that i have mentioned, rest are needed
http://www.mail-archive.com/u-boot@lists.denx.de/msg102709.html
Sorry.. i meant Except for one patch, rest are "not needed"
Regards, Sricharan
Hi R,
On Sun, 3 Feb 2013 19:52:04 +0530, R Sricharan r.sricharan@ti.com wrote:
Hi, On Sunday 03 February 2013 07:49 PM, R Sricharan wrote:
Hi,
On Sunday 03 February 2013 07:47 PM, Albert ARIBAUD wrote:
Hi R Sicharan, Vincent,
On Tue, 8 Jan 2013 23:38:22 +0530, R Sricharan r.sricharan@ti.com wrote: i meant
Currently for ARM based cpu's, mmu pagetable attributes are set with manager permissions for all 4GB address space. Because of this the 'execute never (XN)' permission is never checked on read sensitive regions which results in speculative aborts.
This series changes the domain permissions of the full 4GB space to client access for OMAP socs. This avoids all the speculative aborts that are currently seen on OMAP5 secure devices.
Tested on OMAP5 SDP (HS) soc.
This series depends on [1] the patch sent by <Vincent Stehle v-stehle@ti.com
[1] http://www.mail-archive.com/u-boot@lists.denx.de/msg102709.html
R Sricharan (2): ARM: mmu: Introduce weak dram_bank_setup function ARM: mmu: Set domain permissions to client access
arch/arm/cpu/armv7/cache_v7.c | 3 ++ arch/arm/cpu/armv7/omap-common/hwinit-common.c | 35 ++++++++++++++++++++++++ arch/arm/include/asm/cache.h | 1 + arch/arm/include/asm/system.h | 14 ++++++++++ arch/arm/lib/cache-cp15.c | 13 ++++++++- 5 files changed, 65 insertions(+), 1 deletion(-)
Does that mean the rest of Vincent's patch set is not needed any more?
Except for one patch that i have mentioned, rest are needed
http://www.mail-archive.com/u-boot@lists.denx.de/msg102709.html
Sorry.. i meant Except for one patch, rest are "not needed"
Sorry, I may not have made myself clear enough. Does your patchset replace Vincent's patches 2/3 and 3/3 and should I consider them "superseded"?
Regards, Sricharan
Amicalement,
On Sunday 03 February 2013 08:55 PM, Albert ARIBAUD wrote:
Hi R,
On Sun, 3 Feb 2013 19:52:04 +0530, R Sricharan r.sricharan@ti.com wrote:
Hi, On Sunday 03 February 2013 07:49 PM, R Sricharan wrote:
Hi,
On Sunday 03 February 2013 07:47 PM, Albert ARIBAUD wrote:
Hi R Sicharan, Vincent,
On Tue, 8 Jan 2013 23:38:22 +0530, R Sricharan r.sricharan@ti.com wrote: i meant
Currently for ARM based cpu's, mmu pagetable attributes are set with manager permissions for all 4GB address space. Because of this the 'execute never (XN)' permission is never checked on read sensitive regions which results in speculative aborts.
This series changes the domain permissions of the full 4GB space to client access for OMAP socs. This avoids all the speculative aborts that are currently seen on OMAP5 secure devices.
Tested on OMAP5 SDP (HS) soc.
This series depends on [1] the patch sent by <Vincent Stehle v-stehle@ti.com
[1] http://www.mail-archive.com/u-boot@lists.denx.de/msg102709.html
R Sricharan (2): ARM: mmu: Introduce weak dram_bank_setup function ARM: mmu: Set domain permissions to client access
arch/arm/cpu/armv7/cache_v7.c | 3 ++ arch/arm/cpu/armv7/omap-common/hwinit-common.c | 35 ++++++++++++++++++++++++ arch/arm/include/asm/cache.h | 1 + arch/arm/include/asm/system.h | 14 ++++++++++ arch/arm/lib/cache-cp15.c | 13 ++++++++- 5 files changed, 65 insertions(+), 1 deletion(-)
Does that mean the rest of Vincent's patch set is not needed any more?
Except for one patch that i have mentioned, rest are needed
http://www.mail-archive.com/u-boot@lists.denx.de/msg102709.htmlSorry.. i meant Except for one patch, rest are "not needed"
Sorry, I may not have made myself clear enough. Does your patchset replace Vincent's patches 2/3 and 3/3 and should I consider them "superseded"?
Yes, you are correct.
Regards, Sricharan
(sorry for any duplicate of this mail)
Hi R Sricharan,
On Tue, 8 Jan 2013 23:38:22 +0530, R Sricharan r.sricharan@ti.com wrote:
Currently for ARM based cpu's, mmu pagetable attributes are set with manager permissions for all 4GB address space. Because of this the 'execute never (XN)' permission is never checked on read sensitive regions which results in speculative aborts.
This series changes the domain permissions of the full 4GB space to client access for OMAP socs. This avoids all the speculative aborts that are currently seen on OMAP5 secure devices.
Tested on OMAP5 SDP (HS) soc.
This series depends on [1] the patch sent by <Vincent Stehle v-stehle@ti.com
[1] http://www.mail-archive.com/u-boot@lists.denx.de/msg102709.html
R Sricharan (2): ARM: mmu: Introduce weak dram_bank_setup function ARM: mmu: Set domain permissions to client access
arch/arm/cpu/armv7/cache_v7.c | 3 ++ arch/arm/cpu/armv7/omap-common/hwinit-common.c | 35 ++++++++++++++++++++++++ arch/arm/include/asm/cache.h | 1 + arch/arm/include/asm/system.h | 14 ++++++++++ arch/arm/lib/cache-cp15.c | 13 ++++++++- 5 files changed, 65 insertions(+), 1 deletion(-)
Series applied to u-boot-arm/master, thanks!
Amicalement,
On Thu, 28 Feb 2013 15:20:44 +0100, Albert ARIBAUD albert.u.boot@aribaud.net wrote:
(sorry for any duplicate of this mail)
Hi R Sricharan,
On Tue, 8 Jan 2013 23:38:22 +0530, R Sricharan r.sricharan@ti.com wrote:
Currently for ARM based cpu's, mmu pagetable attributes are set with manager permissions for all 4GB address space. Because of this the 'execute never (XN)' permission is never checked on read sensitive regions which results in speculative aborts.
This series changes the domain permissions of the full 4GB space to client access for OMAP socs. This avoids all the speculative aborts that are currently seen on OMAP5 secure devices.
Tested on OMAP5 SDP (HS) soc.
This series depends on [1] the patch sent by <Vincent Stehle v-stehle@ti.com
[1] http://www.mail-archive.com/u-boot@lists.denx.de/msg102709.html
R Sricharan (2): ARM: mmu: Introduce weak dram_bank_setup function ARM: mmu: Set domain permissions to client access
arch/arm/cpu/armv7/cache_v7.c | 3 ++ arch/arm/cpu/armv7/omap-common/hwinit-common.c | 35 ++++++++++++++++++++++++ arch/arm/include/asm/cache.h | 1 + arch/arm/include/asm/system.h | 14 ++++++++++ arch/arm/lib/cache-cp15.c | 13 ++++++++- 5 files changed, 65 insertions(+), 1 deletion(-)
Series applied to u-boot-arm/master, thanks!
Correction: I'd wrongly inferred from the testing done on OMAP5 that the series would build fine. However it appears that for targets omap4_sdp4430, omap4_panda and omap5_evm, patch 2/2 has warnings:
hwinit-common.c: In function 'dram_bank_mmu_setup': hwinit-common.c:279:3: warning: implicit declaration of function 'set_section_dcache' [-Wimplicit-function-declaration]
Luckily, I had not committed to the git repo yet.
R Sicharan, can you please check and fix this warning?
Amicalement,
Hi Albert,
On Thursday 28 February 2013 08:35 PM, Albert ARIBAUD wrote:
On Thu, 28 Feb 2013 15:20:44 +0100, Albert ARIBAUD albert.u.boot@aribaud.net wrote:
(sorry for any duplicate of this mail)
Hi R Sricharan,
On Tue, 8 Jan 2013 23:38:22 +0530, R Sricharanr.sricharan@ti.com wrote:
Currently for ARM based cpu's, mmu pagetable attributes are set with manager permissions for all 4GB address space. Because of this the 'execute never (XN)' permission is never checked on read sensitive regions which results in speculative aborts.
This series changes the domain permissions of the full 4GB space to client access for OMAP socs. This avoids all the speculative aborts that are currently seen on OMAP5 secure devices.
Tested on OMAP5 SDP (HS) soc.
This series depends on [1] the patch sent by <Vincent Stehlev-stehle@ti.com
[1] http://www.mail-archive.com/u-boot@lists.denx.de/msg102709.html
R Sricharan (2): ARM: mmu: Introduce weak dram_bank_setup function ARM: mmu: Set domain permissions to client access
arch/arm/cpu/armv7/cache_v7.c | 3 ++ arch/arm/cpu/armv7/omap-common/hwinit-common.c | 35 ++++++++++++++++++++++++ arch/arm/include/asm/cache.h | 1 + arch/arm/include/asm/system.h | 14 ++++++++++ arch/arm/lib/cache-cp15.c | 13 ++++++++- 5 files changed, 65 insertions(+), 1 deletion(-)
Series applied to u-boot-arm/master, thanks!
Correction: I'd wrongly inferred from the testing done on OMAP5 that the series would build fine. However it appears that for targets omap4_sdp4430, omap4_panda and omap5_evm, patch 2/2 has warnings:
hwinit-common.c: In function 'dram_bank_mmu_setup': hwinit-common.c:279:3: warning: implicit declaration of function 'set_section_dcache' [-Wimplicit-function-declaration]
Luckily, I had not committed to the git repo yet.
R Sicharan, can you please check and fix this warning?
Amicalement,
Oh, thats because as i mentioned above, it depends on the below patch from vincent .
http://www.mail-archive.com/u-boot@lists.denx.de/msg102709.html
I did not repost it though. I will do it now for clarity.
Regards, Sricharan
From: Vincent Stehlé v-stehle@ti.com
We declare the set_section_dcache function globally in the cache header, for later use by e.g. machine specific code.
Signed-off-by: Vincent Stehlé <v-stehle <at> ti.com> Cc: Tom Rini <trini <at> ti.com> Cc: Albert ARIBAUD albert.u.boot@aribaud.net --- arch/arm/include/asm/cache.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index eef6a5a..416d2c8 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -41,6 +41,7 @@ static inline void invalidate_l2_cache(void)
void l2_cache_enable(void); void l2_cache_disable(void); +void set_section_dcache(int section, enum dcache_option option);
/* * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We
Hi Sricharan,
On Fri, 1 Mar 2013 09:57:25 +0530, Sricharan R r.sricharan@ti.com wrote:
Hi Albert,
On Thursday 28 February 2013 08:35 PM, Albert ARIBAUD wrote:
On Thu, 28 Feb 2013 15:20:44 +0100, Albert ARIBAUD albert.u.boot@aribaud.net wrote:
(sorry for any duplicate of this mail)
Hi R Sricharan,
On Tue, 8 Jan 2013 23:38:22 +0530, R Sricharanr.sricharan@ti.com wrote:
Currently for ARM based cpu's, mmu pagetable attributes are set with manager permissions for all 4GB address space. Because of this the 'execute never (XN)' permission is never checked on read sensitive regions which results in speculative aborts.
This series changes the domain permissions of the full 4GB space to client access for OMAP socs. This avoids all the speculative aborts that are currently seen on OMAP5 secure devices.
Tested on OMAP5 SDP (HS) soc.
This series depends on [1] the patch sent by <Vincent Stehlev-stehle@ti.com
[1] http://www.mail-archive.com/u-boot@lists.denx.de/msg102709.html
R Sricharan (2): ARM: mmu: Introduce weak dram_bank_setup function ARM: mmu: Set domain permissions to client access
arch/arm/cpu/armv7/cache_v7.c | 3 ++ arch/arm/cpu/armv7/omap-common/hwinit-common.c | 35 ++++++++++++++++++++++++ arch/arm/include/asm/cache.h | 1 + arch/arm/include/asm/system.h | 14 ++++++++++ arch/arm/lib/cache-cp15.c | 13 ++++++++- 5 files changed, 65 insertions(+), 1 deletion(-)
Series applied to u-boot-arm/master, thanks!
Correction: I'd wrongly inferred from the testing done on OMAP5 that the series would build fine. However it appears that for targets omap4_sdp4430, omap4_panda and omap5_evm, patch 2/2 has warnings:
hwinit-common.c: In function 'dram_bank_mmu_setup': hwinit-common.c:279:3: warning: implicit declaration of function 'set_section_dcache' [-Wimplicit-function-declaration]
Luckily, I had not committed to the git repo yet.
R Sicharan, can you please check and fix this warning?
Amicalement,
Oh, thats because as i mentioned above, it depends on the below patch from vincent .
http://www.mail-archive.com/u-boot@lists.denx.de/msg102709.html
I did not repost it though. I will do it now for clarity.
Ok -- Vincent's patch was not in my Patchwork TODO and I had read patches 1/2 and 2/2 in Patchwork, but I had not read the cover letter thoroughly enough so I had missed the dependency.
(Cc:ing Vincent and Tom)
Vincent's patch series is delegated to Tom and marked "superseded" in Patchwork but I don't see any later, superseding, series. What can/should I make of it?
Regards, Sricharan
Amicalement,
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1
On 03/01/2013 02:45 AM, Albert ARIBAUD wrote:
Hi Sricharan,
On Fri, 1 Mar 2013 09:57:25 +0530, Sricharan R r.sricharan@ti.com wrote:
Hi Albert,
On Thursday 28 February 2013 08:35 PM, Albert ARIBAUD wrote:
On Thu, 28 Feb 2013 15:20:44 +0100, Albert ARIBAUD albert.u.boot@aribaud.net wrote:
(sorry for any duplicate of this mail)
Hi R Sricharan,
On Tue, 8 Jan 2013 23:38:22 +0530, R Sricharanr.sricharan@ti.com wrote:
Currently for ARM based cpu's, mmu pagetable attributes are set with manager permissions for all 4GB address space. Because of this the 'execute never (XN)' permission is never checked on read sensitive regions which results in speculative aborts.
This series changes the domain permissions of the full 4GB space to client access for OMAP socs. This avoids all the speculative aborts that are currently seen on OMAP5 secure devices.
Tested on OMAP5 SDP (HS) soc.
This series depends on [1] the patch sent by <Vincent Stehlev-stehle@ti.com
[1] http://www.mail-archive.com/u-boot@lists.denx.de/msg102709.html
R Sricharan (2):
ARM: mmu: Introduce weak dram_bank_setup function ARM: mmu: Set domain permissions to client access
arch/arm/cpu/armv7/cache_v7.c | 3 ++ arch/arm/cpu/armv7/omap-common/hwinit-common.c | 35 ++++++++++++++++++++++++ arch/arm/include/asm/cache.h | 1 + arch/arm/include/asm/system.h | 14 ++++++++++ arch/arm/lib/cache-cp15.c | 13 ++++++++- 5 files changed, 65 insertions(+), 1 deletion(-)
Series applied to u-boot-arm/master, thanks!
Correction: I'd wrongly inferred from the testing done on OMAP5 that the series would build fine. However it appears that for targets omap4_sdp4430, omap4_panda and omap5_evm, patch 2/2 has warnings:
hwinit-common.c: In function 'dram_bank_mmu_setup': hwinit-common.c:279:3: warning: implicit declaration of function 'set_section_dcache' [-Wimplicit-function-declaration]
Luckily, I had not committed to the git repo yet.
R Sicharan, can you please check and fix this warning?
Amicalement,
Oh, thats because as i mentioned above, it depends on the below patch from vincent .
http://www.mail-archive.com/u-boot@lists.denx.de/msg102709.html
I did not repost it though. I will do it now for clarity.
Ok -- Vincent's patch was not in my Patchwork TODO and I had read patches 1/2 and 2/2 in Patchwork, but I had not read the cover letter thoroughly enough so I had missed the dependency.
(Cc:ing Vincent and Tom)
Vincent's patch series is delegated to Tom and marked "superseded" in Patchwork but I don't see any later, superseding, series. What can/should I make of it?
It's possible I mis-read things and it shouldn't be superseded. Can you list all of the patches that Albert should apply please? Thanks!
- -- Tom
Hi Tom/Albert, ________________________________________ From: Rini, Tom Sent: Friday, March 01, 2013 7:51 PM To: Albert ARIBAUD Cc: R, Sricharan; U-Boot; Stehle, Vincent Subject: Re: [U-Boot] [PATCH 0/2] ARM: mmu: Set domain permissions to client access - build warnings!
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1
On 03/01/2013 02:45 AM, Albert ARIBAUD wrote:
Hi Sricharan,
On Fri, 1 Mar 2013 09:57:25 +0530, Sricharan R r.sricharan@ti.com wrote:
Hi Albert,
On Thursday 28 February 2013 08:35 PM, Albert ARIBAUD wrote:
On Thu, 28 Feb 2013 15:20:44 +0100, Albert ARIBAUD albert.u.boot@aribaud.net wrote:
(sorry for any duplicate of this mail)
Hi R Sricharan,
On Tue, 8 Jan 2013 23:38:22 +0530, R Sricharanr.sricharan@ti.com wrote:
Currently for ARM based cpu's, mmu pagetable attributes are set with manager permissions for all 4GB address space. Because of this the 'execute never (XN)' permission is never checked on read sensitive regions which results in speculative aborts.
This series changes the domain permissions of the full 4GB space to client access for OMAP socs. This avoids all the speculative aborts that are currently seen on OMAP5 secure devices.
Tested on OMAP5 SDP (HS) soc.
This series depends on [1] the patch sent by <Vincent Stehlev-stehle@ti.com
[1] http://www.mail-archive.com/u-boot@lists.denx.de/msg102709.html
R Sricharan (2):
ARM: mmu: Introduce weak dram_bank_setup function ARM: mmu: Set domain permissions to client access
arch/arm/cpu/armv7/cache_v7.c | 3 ++ arch/arm/cpu/armv7/omap-common/hwinit-common.c | 35 ++++++++++++++++++++++++ arch/arm/include/asm/cache.h | 1 + arch/arm/include/asm/system.h | 14 ++++++++++ arch/arm/lib/cache-cp15.c | 13 ++++++++- 5 files changed, 65 insertions(+), 1 deletion(-)
Series applied to u-boot-arm/master, thanks!
Correction: I'd wrongly inferred from the testing done on OMAP5 that the series would build fine. However it appears that for targets omap4_sdp4430, omap4_panda and omap5_evm, patch 2/2 has warnings:
hwinit-common.c: In function 'dram_bank_mmu_setup': hwinit-common.c:279:3: warning: implicit declaration of function 'set_section_dcache' [-Wimplicit-function-declaration]
Luckily, I had not committed to the git repo yet.
R Sicharan, can you please check and fix this warning?
Amicalement,
Oh, thats because as i mentioned above, it depends on the below patch from vincent .
http://www.mail-archive.com/u-boot@lists.denx.de/msg102709.html
I did not repost it though. I will do it now for clarity.
Ok -- Vincent's patch was not in my Patchwork TODO and I had read patches 1/2 and 2/2 in Patchwork, but I had not read the cover letter thoroughly enough so I had missed the dependency.
(Cc:ing Vincent and Tom)
Vincent's patch series is delegated to Tom and marked "superseded" in Patchwork but I don't see any later, superseding, series. What can/should I make of it?
It's possible I mis-read things and it shouldn't be superseded. Can you list all of the patches that Albert should apply please? Thanks!
Sorry, i should have mentioned this clearly previously.
I reposted it again. (ie) only the below patch from Vincent should be applied first. http://www.mail-archive.com/u-boot@lists.denx.de/msg107190.html
Apologies for the confusion..
Regards, Sricharan
Hi Sricharan,
On Sat, 2 Mar 2013 10:08:20 +0000, "R, Sricharan" r.sricharan@ti.com wrote:
Hi Tom/Albert, ________________________________________ From: Rini, Tom Sent: Friday, March 01, 2013 7:51 PM To: Albert ARIBAUD Cc: R, Sricharan; U-Boot; Stehle, Vincent Subject: Re: [U-Boot] [PATCH 0/2] ARM: mmu: Set domain permissions to client access - build warnings!
-----BEGIN PGP SIGNED MESSAGE----- Hash: SHA1
On 03/01/2013 02:45 AM, Albert ARIBAUD wrote:
Hi Sricharan,
On Fri, 1 Mar 2013 09:57:25 +0530, Sricharan R r.sricharan@ti.com wrote:
Hi Albert,
On Thursday 28 February 2013 08:35 PM, Albert ARIBAUD wrote:
On Thu, 28 Feb 2013 15:20:44 +0100, Albert ARIBAUD albert.u.boot@aribaud.net wrote:
(sorry for any duplicate of this mail)
Hi R Sricharan,
On Tue, 8 Jan 2013 23:38:22 +0530, R Sricharanr.sricharan@ti.com wrote:
Currently for ARM based cpu's, mmu pagetable attributes are set with manager permissions for all 4GB address space. Because of this the 'execute never (XN)' permission is never checked on read sensitive regions which results in speculative aborts.
This series changes the domain permissions of the full 4GB space to client access for OMAP socs. This avoids all the speculative aborts that are currently seen on OMAP5 secure devices.
Tested on OMAP5 SDP (HS) soc.
This series depends on [1] the patch sent by <Vincent Stehlev-stehle@ti.com
[1] http://www.mail-archive.com/u-boot@lists.denx.de/msg102709.html
R Sricharan (2):
ARM: mmu: Introduce weak dram_bank_setup function ARM: mmu: Set domain permissions to client access
arch/arm/cpu/armv7/cache_v7.c | 3 ++ arch/arm/cpu/armv7/omap-common/hwinit-common.c | 35 ++++++++++++++++++++++++ arch/arm/include/asm/cache.h | 1 + arch/arm/include/asm/system.h | 14 ++++++++++ arch/arm/lib/cache-cp15.c | 13 ++++++++- 5 files changed, 65 insertions(+), 1 deletion(-)
Series applied to u-boot-arm/master, thanks!
Correction: I'd wrongly inferred from the testing done on OMAP5 that the series would build fine. However it appears that for targets omap4_sdp4430, omap4_panda and omap5_evm, patch 2/2 has warnings:
hwinit-common.c: In function 'dram_bank_mmu_setup': hwinit-common.c:279:3: warning: implicit declaration of function 'set_section_dcache' [-Wimplicit-function-declaration]
Luckily, I had not committed to the git repo yet.
R Sicharan, can you please check and fix this warning?
Amicalement,
Oh, thats because as i mentioned above, it depends on the below patch from vincent .
http://www.mail-archive.com/u-boot@lists.denx.de/msg102709.html
I did not repost it though. I will do it now for clarity.
Ok -- Vincent's patch was not in my Patchwork TODO and I had read patches 1/2 and 2/2 in Patchwork, but I had not read the cover letter thoroughly enough so I had missed the dependency.
(Cc:ing Vincent and Tom)
Vincent's patch series is delegated to Tom and marked "superseded" in Patchwork but I don't see any later, superseding, series. What can/should I make of it?
It's possible I mis-read things and it shouldn't be superseded. Can you list all of the patches that Albert should apply please? Thanks!
Sorry, i should have mentioned this clearly previously.
I reposted it again. (ie) only the below patch from Vincent should be applied first. http://www.mail-archive.com/u-boot@lists.denx.de/msg107190.html
Apologies for the confusion..
Just to be clear: to apply Sricharan's series, patch 1/3 of Vincent's series is reqired, but I think Vincent's series should be applied in one go, not patch by patch. Basically, this means we need Vincent's series to be applied first, then we can apply Sricharan's.
Regards, Sricharan
Amicalement,
On 03/02/2013 11:46 PM, Albert ARIBAUD wrote:
(..) Basically, this means we need Vincent's series to be applied first, then we can apply Sricharan's.
Hi,
I think this is too much trouble for a "one liner". Please feel free to squash.
Best regards,
V.
Currently for ARM based cpu's, mmu pagetable attributes are set with manager permissions for all 4GB address space. Because of this the 'execute never (XN)' permission is never checked on read sensitive regions which results in speculative aborts.
This series changes the domain permissions of the full 4GB space to client access for OMAP socs. This avoids all the speculative aborts that are currently seen on OMAP5 secure devices.
Tested on OMAP5 SDP (HS) soc.
This is a repost of the older series to include Vincent's patch in the same one.
R Sricharan (2): ARM: mmu: Introduce weak dram_bank_setup function ARM: mmu: Set domain permissions to client access
Vincent Stehlé (1): ARM: cache: declare set_section_dcache
arch/arm/cpu/armv7/cache_v7.c | 3 ++ arch/arm/cpu/armv7/omap-common/hwinit-common.c | 35 ++++++++++++++++++++++++ arch/arm/include/asm/cache.h | 2 ++ arch/arm/include/asm/system.h | 14 ++++++++++ arch/arm/lib/cache-cp15.c | 11 +++++++- 5 files changed, 64 insertions(+), 1 deletion(-)
From: Vincent Stehlé v-stehle@ti.com
We declare the set_section_dcache function globally in the cache header, for later use by e.g. machine specific code.
Signed-off-by: Vincent Stehlé <v-stehle <at> ti.com> Cc: Tom Rini <trini <at> ti.com> Cc: Albert ARIBAUD albert.u.boot@aribaud.net --- arch/arm/include/asm/cache.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index eef6a5a..416d2c8 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -41,6 +41,7 @@ static inline void invalidate_l2_cache(void)
void l2_cache_enable(void); void l2_cache_disable(void); +void set_section_dcache(int section, enum dcache_option option);
/* * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We
From: R Sricharan r.sricharan@ti.com
Introduce a weak version of dram_bank_setup function to allow a platform specific function.
This is used in the subsequent patch to setup dram region without 'XN' attribute in order to enable the region under client permissions.
Signed-off-by: R Sricharan r.sricharan@ti.com Cc: Vincent Stehle v-stehle@ti.com Cc: Tom Rini trini@ti.com Cc: Albert ARIBAUD albert.u.boot@aribaud.net --- arch/arm/include/asm/cache.h | 1 + arch/arm/lib/cache-cp15.c | 4 +++- 2 files changed, 4 insertions(+), 1 deletion(-)
diff --git a/arch/arm/include/asm/cache.h b/arch/arm/include/asm/cache.h index 416d2c8..8153484 100644 --- a/arch/arm/include/asm/cache.h +++ b/arch/arm/include/asm/cache.h @@ -43,6 +43,7 @@ void l2_cache_enable(void); void l2_cache_disable(void); void set_section_dcache(int section, enum dcache_option option);
+void dram_bank_mmu_setup(int bank); /* * The current upper bound for ARM L1 data cache line sizes is 64 bytes. We * use that value for aligning DMA buffers unless the board config has specified diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index b6e5e95..6ecbedf 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -23,6 +23,8 @@
#include <common.h> #include <asm/system.h> +#include <asm/cache.h> +#include <linux/compiler.h>
#if !(defined(CONFIG_SYS_ICACHE_OFF) && defined(CONFIG_SYS_DCACHE_OFF))
@@ -77,7 +79,7 @@ void mmu_set_region_dcache_behaviour(u32 start, int size, mmu_page_table_flush((u32)&page_table[start], (u32)&page_table[end]); }
-static inline void dram_bank_mmu_setup(int bank) +__weak void dram_bank_mmu_setup(int bank) { bd_t *bd = gd->bd; int i;
From: R Sricharan r.sricharan@ti.com
The 'XN' execute never bit is set in the pagetables. This will prevent speculative prefetches to non executable regions. But the domain permissions are set as master in the DACR register. So the pagetable attribute for 'XN' is not effective. Change the permissions to client.
This fixes lot of speculative prefetch aborts seen on OMAP5 secure devices.
Signed-off-by: R Sricharan r.sricharan@ti.com Tested-by: Vincent Stehle v-stehle@ti.com Cc: Vincent Stehle v-stehle@ti.com Cc: Tom Rini trini@ti.com Cc: Albert ARIBAUD albert.u.boot@aribaud.net --- arch/arm/cpu/armv7/cache_v7.c | 3 ++ arch/arm/cpu/armv7/omap-common/hwinit-common.c | 35 ++++++++++++++++++++++++ arch/arm/include/asm/system.h | 14 ++++++++++ arch/arm/lib/cache-cp15.c | 7 +++++ 4 files changed, 59 insertions(+)
diff --git a/arch/arm/cpu/armv7/cache_v7.c b/arch/arm/cpu/armv7/cache_v7.c index 5f6d039..8748c14 100644 --- a/arch/arm/cpu/armv7/cache_v7.c +++ b/arch/arm/cpu/armv7/cache_v7.c @@ -340,6 +340,9 @@ void mmu_page_table_flush(unsigned long start, unsigned long stop) { }
+void arm_init_domains(void) +{ +} #endif /* #ifndef CONFIG_SYS_DCACHE_OFF */
#ifndef CONFIG_SYS_ICACHE_OFF diff --git a/arch/arm/cpu/armv7/omap-common/hwinit-common.c b/arch/arm/cpu/armv7/omap-common/hwinit-common.c index 9ef10bd..4eaf75b 100644 --- a/arch/arm/cpu/armv7/omap-common/hwinit-common.c +++ b/arch/arm/cpu/armv7/omap-common/hwinit-common.c @@ -32,6 +32,12 @@ #include <asm/arch/sys_proto.h> #include <asm/sizes.h> #include <asm/emif.h> +#include <asm/cache.h> +#include <asm/system.h> + +#define ARMV7_DCACHE_WRITEBACK 0xe +#define ARMV7_DOMAIN_CLIENT 1 +#define ARMV7_DOMAIN_MASK (0x3 << 0)
DECLARE_GLOBAL_DATA_PTR;
@@ -258,4 +264,33 @@ void enable_caches(void) /* Enable D-cache. I-cache is already enabled in start.S */ dcache_enable(); } + +void dram_bank_mmu_setup(int bank) +{ + bd_t *bd = gd->bd; + int i; + + u32 start = bd->bi_dram[bank].start >> 20; + u32 size = bd->bi_dram[bank].size >> 20; + u32 end = start + size; + + debug("%s: bank: %d\n", __func__, bank); + for (i = start; i < end; i++) + set_section_dcache(i, ARMV7_DCACHE_WRITEBACK); + +} + +void arm_init_domains(void) +{ + u32 reg; + + reg = get_dacr(); + /* + * Set DOMAIN to client access so that all permissions + * set in pagetables are validated by the mmu. + */ + reg &= ~ARMV7_DOMAIN_MASK; + reg |= ARMV7_DOMAIN_CLIENT; + set_dacr(reg); +} #endif diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 1918492..760345f 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -81,6 +81,20 @@ static inline void set_cr(unsigned int val) isb(); }
+static inline unsigned int get_dacr(void) +{ + unsigned int val; + asm("mrc p15, 0, %0, c3, c0, 0 @ get DACR" : "=r" (val) : : "cc"); + return val; +} + +static inline void set_dacr(unsigned int val) +{ + asm volatile("mcr p15, 0, %0, c3, c0, 0 @ set DACR" + : : "r" (val) : "cc"); + isb(); +} + /* options available for data cache on each page */ enum dcache_option { DCACHE_OFF = 0x12, diff --git a/arch/arm/lib/cache-cp15.c b/arch/arm/lib/cache-cp15.c index 6ecbedf..4abe1cf 100644 --- a/arch/arm/lib/cache-cp15.c +++ b/arch/arm/lib/cache-cp15.c @@ -36,6 +36,10 @@ void __arm_init_before_mmu(void) void arm_init_before_mmu(void) __attribute__((weak, alias("__arm_init_before_mmu")));
+__weak void arm_init_domains(void) +{ +} + static void cp_delay (void) { volatile int i; @@ -117,6 +121,9 @@ static inline void mmu_setup(void) /* Set the access control to all-supervisor */ asm volatile("mcr p15, 0, %0, c3, c0, 0" : : "r" (~0)); + + arm_init_domains(); + /* and enable the mmu */ reg = get_cr(); /* get control reg. */ cp_delay();
Hi Albert,
On Tuesday 05 March 2013 11:34 AM, Sricharan R wrote:
Currently for ARM based cpu's, mmu pagetable attributes are set with manager permissions for all 4GB address space. Because of this the 'execute never (XN)' permission is never checked on read sensitive regions which results in speculative aborts.
This series changes the domain permissions of the full 4GB space to client access for OMAP socs. This avoids all the speculative aborts that are currently seen on OMAP5 secure devices.
Tested on OMAP5 SDP (HS) soc.
This is a repost of the older series to include Vincent's patch in the same one.
R Sricharan (2): ARM: mmu: Introduce weak dram_bank_setup function ARM: mmu: Set domain permissions to client access
Vincent Stehlé (1): ARM: cache: declare set_section_dcache
arch/arm/cpu/armv7/cache_v7.c | 3 ++ arch/arm/cpu/armv7/omap-common/hwinit-common.c | 35 ++++++++++++++++++++++++ arch/arm/include/asm/cache.h | 2 ++ arch/arm/include/asm/system.h | 14 ++++++++++ arch/arm/lib/cache-cp15.c | 11 +++++++- 5 files changed, 64 insertions(+), 1 deletion(-)
Is this ok to get in now ?
Regards, Sricharan
Hi Sricharan,
On Tue, 5 Mar 2013 11:34:42 +0530, Sricharan R r.sricharan@ti.com wrote:
Currently for ARM based cpu's, mmu pagetable attributes are set with manager permissions for all 4GB address space. Because of this the 'execute never (XN)' permission is never checked on read sensitive regions which results in speculative aborts.
This series changes the domain permissions of the full 4GB space to client access for OMAP socs. This avoids all the speculative aborts that are currently seen on OMAP5 secure devices.
Tested on OMAP5 SDP (HS) soc.
This is a repost of the older series to include Vincent's patch in the same one.
R Sricharan (2): ARM: mmu: Introduce weak dram_bank_setup function ARM: mmu: Set domain permissions to client access
Vincent Stehlé (1): ARM: cache: declare set_section_dcache
arch/arm/cpu/armv7/cache_v7.c | 3 ++ arch/arm/cpu/armv7/omap-common/hwinit-common.c | 35 ++++++++++++++++++++++++ arch/arm/include/asm/cache.h | 2 ++ arch/arm/include/asm/system.h | 14 ++++++++++ arch/arm/lib/cache-cp15.c | 11 +++++++- 5 files changed, 64 insertions(+), 1 deletion(-)
Series applied to u-boot-arm/master, thanks!
Amicalement,
Hi, On Monday 04 March 2013 03:38 PM, Vincent Stehlé wrote:
On 03/02/2013 11:46 PM, Albert ARIBAUD wrote:
(..) Basically, this means we need Vincent's series to be applied first, then we can apply Sricharan's.
Hi,
I think this is too much trouble for a "one liner". Please feel free to squash.
Best regards,
V.
Ok, i reposted the series again after squashing.
http://www.mail-archive.com/u-boot@lists.denx.de/msg107487.html
Regards, Sricharan
participants (6)
-
Albert ARIBAUD -
R Sricharan -
R, Sricharan
-
Sricharan R
-
Tom Rini -
Vincent Stehlé