Re: [U-Boot] [PATCH 1/2] i.MX28: Fix ref_cpu clock setup
Hi Robert,
On 2/2/12, Robert Deliën robert@delien.nl wrote:
Hi,
This patch fixes ref_cpu clock setup. This bug leads to a hanging board after rebooting from the Kernel, due to failing memory size detection: U-Boot 2011.12-svn342 (Feb 02 2012 - 17:20:00)
Freescale i.MX28 family
I2C: ready
DRAM: 0 Bytes
The cause of the bug is register hw_clkctrl_frac0 being accessed as a 32-bit long, whereas the manual specifically states it can be accessed as bytes only. Applying this patch fixes this problem.
Signed-off-by: Robert Delien (robert@delien.nl)
Very good, Robert! I tested your patch and it fixes the reboot issue on my mx28evk.
Also checked in the MX28 Reference Manual about the fact that hw_clkctrl_frac0 can only be accessed as bytes.
I have some suggestions though:
1. Your patch comes as attachment. Please use git send-email instead.
2. Please grep the locations where hw_clkctrl_frac0 is assigned as 32-bit and change those as well.
3. Send the two patches in a series via git send-email: 1/2 and 2/2
Good to know that you fixed the stepping issue as well. Good work!
Regards,
Fabio Estevam
On 2/2/12, Fabio Estevam festevam@gmail.com wrote:
- Please grep the locations where hw_clkctrl_frac0 is assigned as
32-bit and change those as well.
Please do the same for hw_clkctrl_frac1 as well. There is one location in clock.c where it is read as 32-bit.
Thanks,
Fabio Estevam
- Please grep the locations where hw_clkctrl_frac0 is assigned as
32-bit and change those as well.
Please do the same for hw_clkctrl_frac1 as well. There is one location in clock.c where it is read as 32-bit.
I will check all hw_clkctrl_frac* register access, but tomorrow because the building closes is a couple of minutes.
Ideally I'd like to set up these registers as uint8_t*. Any ideas? I'll also check if bye-lane shifting is done automatically here.
On 2/2/12, Robert Deliën robert@delien.nl wrote:
Ideally I'd like to set up these registers as uint8_t*. Any ideas? I'll also check if bye-lane shifting is done automatically here.
You can write: writeb(19 , &clkctrl_regs->hw_clkctrl_frac0);
Regards,
Fabio Estevam
You can write: writeb(19 , &clkctrl_regs->hw_clkctrl_frac0);
Yes, for the first byte I can (and do), but the three higher bytes would get ugly with this method: writeb(bitset >> 8, (unit8_t*)&clkctrl_regs->hw_clkctrl_frac0 + 1);
Hi Fabio,
Very good, Robert! I tested your patch and it fixes the reboot issue on my mx28evk.
You're most welcome! I'm glad to hear it fixes your problem too.
Also checked in the MX28 Reference Manual about the fact that hw_clkctrl_frac0 can only be accessed as bytes.
It's easy to overlook, I have to admit.
I have some suggestions though:
- Your patch comes as attachment. Please use git send-email instead.
I knew I was violating protocol, but I wanted to get it off my chest. I will work on this problem today. I work at two locations, and only at my home office I have an SMTP server I can user. Here at Agilent, unfortunately I only have an MS Exchange server I can use. If I can get that configured at all, there's a good chance it will break my patches.
- Please grep the locations where hw_clkctrl_frac0 is assigned as
32-bit and change those as well.
Will do!
- Send the two patches in a series via git send-email: 1/2 and 2/2
Will do! I'm reading up on that right now, as Wolfgang suggested earlier. I may as well switch our own internal repository from SVN to GIT, but not today.
Good to know that you fixed the stepping issue as well. Good work!
Thanks. I would really like to urge you guys to test the second patch as well. Marek made a remark on that too, so that will be my next mail to answer.
Cheers,
Robert.
participants (2)
-
Fabio Estevam -
Robert Deliën