Add the entry for the rk3188 requiring rc4-encryption of the SPL.

Signed-off-by: Heiko Stuebner heiko@sntech.de --- tools/rkcommon.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/tools/rkcommon.c b/tools/rkcommon.c index ed9b24137a..6595e02c1c 100644 --- a/tools/rkcommon.c +++ b/tools/rkcommon.c @@ -57,6 +57,7 @@ struct spl_info {

static struct spl_info spl_infos[] = { { "rk3036", "RK30", 0x1000, false }, + { "rk3188", "RK31", 0x8000 - 0x800, true }, { "rk3288", "RK32", 0x8000, false }, { "rk3399", "RK33", 0x20000, false }, };

Add a driver which supports pin multiplexing setup for the most commonly used peripherals.

Signed-off-by: Heiko Stuebner heiko@sntech.de Acked-by: Simon Glass sjg@chromium.org --- drivers/pinctrl/Kconfig | 9 + drivers/pinctrl/rockchip/Makefile | 1 + drivers/pinctrl/rockchip/pinctrl_rk3188.c | 611 ++++++++++++++++++++++++++++++ 3 files changed, 621 insertions(+) create mode 100644 drivers/pinctrl/rockchip/pinctrl_rk3188.c

diff --git a/drivers/pinctrl/Kconfig b/drivers/pinctrl/Kconfig index efcb4c0003..c68860c092 100644 --- a/drivers/pinctrl/Kconfig +++ b/drivers/pinctrl/Kconfig @@ -132,6 +132,15 @@ config ROCKCHIP_RK3036_PINCTRL definitions and pin control functions for each available multiplex function.

+config ROCKCHIP_RK3188_PINCTRL + bool "Rockchip pin control driver" + depends on DM + help + Support pin multiplexing control on Rockchip rk3188 SoCs. The driver + is controlled by a device tree node which contains both the GPIO + definitions and pin control functions for each available multiplex + function. + config ROCKCHIP_RK3288_PINCTRL bool "Rockchip pin control driver" depends on DM diff --git a/drivers/pinctrl/rockchip/Makefile b/drivers/pinctrl/rockchip/Makefile index 805c833ec9..cc99aeebb5 100644 --- a/drivers/pinctrl/rockchip/Makefile +++ b/drivers/pinctrl/rockchip/Makefile @@ -6,5 +6,6 @@ #

obj-$(CONFIG_ROCKCHIP_RK3036_PINCTRL) += pinctrl_rk3036.o +obj-$(CONFIG_ROCKCHIP_RK3188_PINCTRL) += pinctrl_rk3188.o obj-$(CONFIG_ROCKCHIP_RK3288_PINCTRL) += pinctrl_rk3288.o obj-$(CONFIG_ROCKCHIP_RK3399_PINCTRL) += pinctrl_rk3399.o diff --git a/drivers/pinctrl/rockchip/pinctrl_rk3188.c b/drivers/pinctrl/rockchip/pinctrl_rk3188.c new file mode 100644 index 0000000000..ef94dab210 --- /dev/null +++ b/drivers/pinctrl/rockchip/pinctrl_rk3188.c @@ -0,0 +1,611 @@ +/* + * Pinctrl driver for Rockchip RK3188 SoCs + * Copyright (c) 2016 Heiko Stuebner heiko@sntech.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <errno.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/grf_rk3188.h> +#include <asm/arch/hardware.h> +#include <asm/arch/periph.h> +#include <asm/arch/pmu_rk3188.h> +#include <dm/pinctrl.h> +#include <dm/root.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct rk3188_pinctrl_priv { + struct rk3188_grf *grf; + struct rk3188_pmu *pmu; + int num_banks; +}; + +/** + * Encode variants of iomux registers into a type variable + */ +#define IOMUX_GPIO_ONLY BIT(0) + +/** + * @type: iomux variant using IOMUX_* constants + * @offset: if initialized to -1 it will be autocalculated, by specifying + * an initial offset value the relevant source offset can be reset + * to a new value for autocalculating the following iomux registers. + */ +struct rockchip_iomux { + u8 type; + s16 offset; +}; + +/** + * @reg: register offset of the gpio bank + * @nr_pins: number of pins in this bank + * @bank_num: number of the bank, to account for holes + * @name: name of the bank + * @iomux: array describing the 4 iomux sources of the bank + */ +struct rockchip_pin_bank { + u16 reg; + u8 nr_pins; + u8 bank_num; + char *name; + struct rockchip_iomux iomux[4]; +}; + +#define PIN_BANK(id, pins, label) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + .iomux = { \ + { .offset = -1 }, \ + { .offset = -1 }, \ + { .offset = -1 }, \ + { .offset = -1 }, \ + }, \ + } + +#define PIN_BANK_IOMUX_FLAGS(id, pins, label, iom0, iom1, iom2, iom3) \ + { \ + .bank_num = id, \ + .nr_pins = pins, \ + .name = label, \ + .iomux = { \ + { .type = iom0, .offset = -1 }, \ + { .type = iom1, .offset = -1 }, \ + { .type = iom2, .offset = -1 }, \ + { .type = iom3, .offset = -1 }, \ + }, \ + } + +#ifndef CONFIG_SPL_BUILD +static struct rockchip_pin_bank rk3188_pin_banks[] = { + PIN_BANK_IOMUX_FLAGS(0, 32, "gpio0", IOMUX_GPIO_ONLY, 0, 0, 0), + PIN_BANK(1, 32, "gpio1"), + PIN_BANK(2, 32, "gpio2"), + PIN_BANK(3, 32, "gpio3"), +}; +#endif + +static void pinctrl_rk3188_pwm_config(struct rk3188_grf *grf, int pwm_id) +{ + switch (pwm_id) { + case PERIPH_ID_PWM0: + rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D3_MASK << GPIO3D3_SHIFT, + GPIO3D3_PWM_0 << GPIO3D3_SHIFT); + break; + case PERIPH_ID_PWM1: + rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D4_MASK << GPIO3D4_SHIFT, + GPIO3D4_PWM_1 << GPIO3D4_SHIFT); + break; + case PERIPH_ID_PWM2: + rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D5_MASK << GPIO3D5_SHIFT, + GPIO3D5_PWM_2 << GPIO3D5_SHIFT); + break; + case PERIPH_ID_PWM3: + rk_clrsetreg(&grf->gpio3d_iomux, GPIO3D6_MASK << GPIO3D6_SHIFT, + GPIO3D6_PWM_3 << GPIO3D6_SHIFT); + break; + default: + debug("pwm id = %d iomux error!\n", pwm_id); + break; + } +} + +static void pinctrl_rk3188_i2c_config(struct rk3188_grf *grf, + struct rk3188_pmu *pmu, int i2c_id) +{ + switch (i2c_id) { + case PERIPH_ID_I2C0: + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D1_MASK << GPIO1D1_SHIFT | + GPIO1D0_MASK << GPIO1D0_SHIFT, + GPIO1D1_I2C0_SCL << GPIO1D1_SHIFT | + GPIO1D0_I2C0_SDA << GPIO1D0_SHIFT); + /* enable new i2c controller */ + rk_clrsetreg(&grf->soc_con1, 1 << RKI2C0_SEL_SHIFT, + 1 << RKI2C0_SEL_SHIFT); + break; + case PERIPH_ID_I2C1: + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D3_MASK << GPIO1D3_SHIFT | + GPIO1D2_MASK << GPIO1D2_SHIFT, + GPIO1D3_I2C1_SCL << GPIO1D2_SHIFT | + GPIO1D2_I2C1_SDA << GPIO1D2_SHIFT); + rk_clrsetreg(&grf->soc_con1, 1 << RKI2C1_SEL_SHIFT, + 1 << RKI2C1_SEL_SHIFT); + break; + case PERIPH_ID_I2C2: + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D5_MASK << GPIO1D5_SHIFT | + GPIO1D4_MASK << GPIO1D4_SHIFT, + GPIO1D5_I2C2_SCL << GPIO1D5_SHIFT | + GPIO1D4_I2C2_SDA << GPIO1D4_SHIFT); + rk_clrsetreg(&grf->soc_con1, 1 << RKI2C2_SEL_SHIFT, + 1 << RKI2C2_SEL_SHIFT); + break; + case PERIPH_ID_I2C3: + rk_clrsetreg(&grf->gpio3b_iomux, + GPIO3B7_MASK << GPIO3B7_SHIFT | + GPIO3B6_MASK << GPIO3B6_SHIFT, + GPIO3B7_I2C3_SCL << GPIO3B7_SHIFT | + GPIO3B6_I2C3_SDA << GPIO3B6_SHIFT); + rk_clrsetreg(&grf->soc_con1, 1 << RKI2C3_SEL_SHIFT, + 1 << RKI2C3_SEL_SHIFT); + break; + case PERIPH_ID_I2C4: + rk_clrsetreg(&grf->gpio1d_iomux, + GPIO1D7_MASK << GPIO1D7_SHIFT | + GPIO1D6_MASK << GPIO1D6_SHIFT, + GPIO1D7_I2C4_SCL << GPIO1D7_SHIFT | + GPIO1D6_I2C4_SDA << GPIO1D6_SHIFT); + rk_clrsetreg(&grf->soc_con1, 1 << RKI2C4_SEL_SHIFT, + 1 << RKI2C4_SEL_SHIFT); + break; + default: + debug("i2c id = %d iomux error!\n", i2c_id); + break; + } +} + +static int pinctrl_rk3188_spi_config(struct rk3188_grf *grf, + enum periph_id spi_id, int cs) +{ + switch (spi_id) { + case PERIPH_ID_SPI0: + switch (cs) { + case 0: + rk_clrsetreg(&grf->gpio1a_iomux, + GPIO1A7_MASK << GPIO1A7_SHIFT, + GPIO1A7_SPI0_CSN0 << GPIO1A7_SHIFT); + break; + case 1: + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B7_MASK << GPIO1B7_SHIFT, + GPIO1B7_SPI0_CSN1 << GPIO1B7_SHIFT); + break; + default: + goto err; + } + rk_clrsetreg(&grf->gpio1a_iomux, + GPIO1A4_MASK << GPIO1A4_SHIFT | + GPIO1A5_MASK << GPIO1A5_SHIFT | + GPIO1A6_MASK << GPIO1A6_SHIFT, + GPIO1A4_SPI0_RXD << GPIO1A4_SHIFT | + GPIO1A5_SPI0_TXD << GPIO1A5_SHIFT | + GPIO1A6_SPI0_CLK << GPIO1A6_SHIFT); + break; + case PERIPH_ID_SPI1: + switch (cs) { + case 0: + rk_clrsetreg(&grf->gpio0d_iomux, + GPIO0D7_MASK << GPIO0D7_SHIFT, + GPIO0D7_SPI1_CSN0 << GPIO0D7_SHIFT); + break; + case 1: + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B6_MASK << GPIO1B6_SHIFT, + GPIO1B6_SPI1_CSN1 << GPIO1B6_SHIFT); + break; + default: + goto err; + } + rk_clrsetreg(&grf->gpio0d_iomux, + GPIO0D4_MASK << GPIO0D4_SHIFT | + GPIO0D5_MASK << GPIO0D5_SHIFT | + GPIO0D6_MASK << GPIO0D6_SHIFT, + GPIO0D4_SPI0_RXD << GPIO0D4_SHIFT | + GPIO0D5_SPI1_TXD << GPIO0D5_SHIFT | + GPIO0D6_SPI1_CLK << GPIO0D6_SHIFT); + break; + default: + goto err; + } + + return 0; +err: + debug("rkspi: periph%d cs=%d not supported", spi_id, cs); + return -ENOENT; +} + +static void pinctrl_rk3188_uart_config(struct rk3188_grf *grf, int uart_id) +{ + switch (uart_id) { + case PERIPH_ID_UART0: + rk_clrsetreg(&grf->gpio1a_iomux, + GPIO1A3_MASK << GPIO1A3_SHIFT | + GPIO1A2_MASK << GPIO1A2_SHIFT | + GPIO1A1_MASK << GPIO1A1_SHIFT | + GPIO1A0_MASK << GPIO1A0_SHIFT, + GPIO1A3_UART0_RTS_N << GPIO1A3_SHIFT | + GPIO1A2_UART0_CTS_N << GPIO1A2_SHIFT | + GPIO1A1_UART0_SOUT << GPIO1A1_SHIFT | + GPIO1A0_UART0_SIN << GPIO1A0_SHIFT); + break; + case PERIPH_ID_UART1: + rk_clrsetreg(&grf->gpio1a_iomux, + GPIO1A7_MASK << GPIO1A7_SHIFT | + GPIO1A6_MASK << GPIO1A6_SHIFT | + GPIO1A5_MASK << GPIO1A5_SHIFT | + GPIO1A4_MASK << GPIO1A4_SHIFT, + GPIO1A7_UART1_RTS_N << GPIO1A7_SHIFT | + GPIO1A6_UART1_CTS_N << GPIO1A6_SHIFT | + GPIO1A5_UART1_SOUT << GPIO1A5_SHIFT | + GPIO1A4_UART1_SIN << GPIO1A4_SHIFT); + break; + case PERIPH_ID_UART2: + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK << GPIO1B1_SHIFT | + GPIO1B0_MASK << GPIO1B0_SHIFT, + GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | + GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); + break; + case PERIPH_ID_UART3: + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B5_MASK << GPIO1B5_SHIFT | + GPIO1B4_MASK << GPIO1B4_SHIFT | + GPIO1B3_MASK << GPIO1B3_SHIFT | + GPIO1B2_MASK << GPIO1B2_SHIFT, + GPIO1B5_UART3_RTS_N << GPIO1B5_SHIFT | + GPIO1B4_UART3_CTS_N << GPIO1B4_SHIFT | + GPIO1B3_UART3_SOUT << GPIO1B3_SHIFT | + GPIO1B2_UART3_SIN << GPIO1B2_SHIFT); + break; + default: + debug("uart id = %d iomux error!\n", uart_id); + break; + } +} + +static void pinctrl_rk3188_sdmmc_config(struct rk3188_grf *grf, int mmc_id) +{ + switch (mmc_id) { + case PERIPH_ID_EMMC: + rk_clrsetreg(&grf->soc_con0, 1 << EMMC_FLASH_SEL_SHIFT, + 1 << EMMC_FLASH_SEL_SHIFT); + rk_clrsetreg(&grf->gpio0d_iomux, + GPIO0D2_MASK << GPIO0D2_SHIFT | + GPIO0D0_MASK << GPIO0D0_SHIFT, + GPIO0D2_EMMC_CMD << GPIO0D2_SHIFT | + GPIO0D0_EMMC_CLKOUT << GPIO0D0_SHIFT); + break; + case PERIPH_ID_SDCARD: + rk_clrsetreg(&grf->gpio3b_iomux, + GPIO3B0_MASK << GPIO3B0_SHIFT, + GPIO3B0_SDMMC_DETECT_N << GPIO3B0_SHIFT); + rk_clrsetreg(&grf->gpio3a_iomux, + GPIO3A7_MASK << GPIO3A7_SHIFT | + GPIO3A6_MASK << GPIO3A6_SHIFT | + GPIO3A5_MASK << GPIO3A5_SHIFT | + GPIO3A4_MASK << GPIO3A4_SHIFT | + GPIO3A3_MASK << GPIO3A3_SHIFT | + GPIO3A3_MASK << GPIO3A2_SHIFT, + GPIO3A7_SDMMC0_DATA3 << GPIO3A7_SHIFT | + GPIO3A6_SDMMC0_DATA2 << GPIO3A6_SHIFT | + GPIO3A5_SDMMC0_DATA1 << GPIO3A5_SHIFT | + GPIO3A4_SDMMC0_DATA0 << GPIO3A4_SHIFT | + GPIO3A3_SDMMC0_CMD << GPIO3A3_SHIFT | + GPIO3A2_SDMMC0_CLKOUT << GPIO3A2_SHIFT); + break; + default: + debug("mmc id = %d iomux error!\n", mmc_id); + break; + } +} + +static int rk3188_pinctrl_request(struct udevice *dev, int func, int flags) +{ + struct rk3188_pinctrl_priv *priv = dev_get_priv(dev); + + debug("%s: func=%x, flags=%x\n", __func__, func, flags); + switch (func) { + case PERIPH_ID_PWM0: + case PERIPH_ID_PWM1: + case PERIPH_ID_PWM2: + case PERIPH_ID_PWM3: + case PERIPH_ID_PWM4: + pinctrl_rk3188_pwm_config(priv->grf, func); + break; + case PERIPH_ID_I2C0: + case PERIPH_ID_I2C1: + case PERIPH_ID_I2C2: + case PERIPH_ID_I2C3: + case PERIPH_ID_I2C4: + case PERIPH_ID_I2C5: + pinctrl_rk3188_i2c_config(priv->grf, priv->pmu, func); + break; + case PERIPH_ID_SPI0: + case PERIPH_ID_SPI1: + case PERIPH_ID_SPI2: + pinctrl_rk3188_spi_config(priv->grf, func, flags); + break; + case PERIPH_ID_UART0: + case PERIPH_ID_UART1: + case PERIPH_ID_UART2: + case PERIPH_ID_UART3: + case PERIPH_ID_UART4: + pinctrl_rk3188_uart_config(priv->grf, func); + break; + break; + case PERIPH_ID_SDMMC0: + case PERIPH_ID_SDMMC1: + pinctrl_rk3188_sdmmc_config(priv->grf, func); + break; + default: + return -EINVAL; + } + + return 0; +} + +static int rk3188_pinctrl_get_periph_id(struct udevice *dev, + struct udevice *periph) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + u32 cell[3]; + int ret; + + ret = fdtdec_get_int_array(gd->fdt_blob, periph->of_offset, + "interrupts", cell, ARRAY_SIZE(cell)); + if (ret < 0) + return -EINVAL; + + switch (cell[1]) { + case 44: + return PERIPH_ID_SPI0; + case 45: + return PERIPH_ID_SPI1; + case 46: + return PERIPH_ID_SPI2; + case 60: + return PERIPH_ID_I2C0; + case 62: /* Note strange order */ + return PERIPH_ID_I2C1; + case 61: + return PERIPH_ID_I2C2; + case 63: + return PERIPH_ID_I2C3; + case 64: + return PERIPH_ID_I2C4; + case 65: + return PERIPH_ID_I2C5; + } +#endif + + return -ENOENT; +} + +static int rk3188_pinctrl_set_state_simple(struct udevice *dev, + struct udevice *periph) +{ + int func; + + func = rk3188_pinctrl_get_periph_id(dev, periph); + if (func < 0) + return func; + return rk3188_pinctrl_request(dev, func, 0); +} + +#ifndef CONFIG_SPL_BUILD +int rk3188_pinctrl_get_pin_info(struct rk3188_pinctrl_priv *priv, + int banknum, int ind, u32 **addrp, uint *shiftp, + uint *maskp) +{ + struct rockchip_pin_bank *bank = &rk3188_pin_banks[banknum]; + uint muxnum; + u32 *addr; + + for (muxnum = 0; muxnum < 4; muxnum++) { + struct rockchip_iomux *mux = &bank->iomux[muxnum]; + + if (ind >= 8) { + ind -= 8; + continue; + } + + addr = &priv->grf->gpio0c_iomux - 2; + addr += mux->offset; + *shiftp = ind & 7; + *maskp = 3; + *shiftp *= 2; + + debug("%s: addr=%p, mask=%x, shift=%x\n", __func__, addr, + *maskp, *shiftp); + *addrp = addr; + return 0; + } + + return -EINVAL; +} + +static int rk3188_pinctrl_get_gpio_mux(struct udevice *dev, int banknum, + int index) +{ + struct rk3188_pinctrl_priv *priv = dev_get_priv(dev); + uint shift; + uint mask; + u32 *addr; + int ret; + + ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift, + &mask); + if (ret) + return ret; + return (readl(addr) & mask) >> shift; +} + +static int rk3188_pinctrl_set_pins(struct udevice *dev, int banknum, int index, + int muxval, int flags) +{ + struct rk3188_pinctrl_priv *priv = dev_get_priv(dev); + uint shift, ind = index; + uint mask; + u32 *addr; + int ret; + + debug("%s: %x %x %x %x\n", __func__, banknum, index, muxval, flags); + ret = rk3188_pinctrl_get_pin_info(priv, banknum, index, &addr, &shift, + &mask); + if (ret) + return ret; + rk_clrsetreg(addr, mask << shift, muxval << shift); + + /* Handle pullup/pulldown */ + if (flags) { + uint val = 0; + + if (flags & (1 << PIN_CONFIG_BIAS_PULL_UP)) + val = 1; + else if (flags & (1 << PIN_CONFIG_BIAS_PULL_DOWN)) + val = 2; + + ind = index >> 3; + + if (banknum == 0 && index < 12) { + addr = &priv->pmu->gpio0_p[ind]; + shift = (index & 7) * 2; + } else if (banknum == 0 && index >= 12) { + addr = &priv->grf->gpio0_p[ind - 1]; + /* + * The bits in the grf-registers have an inverse + * ordering with the lowest pin being in bits 15:14 + * and the highest pin in bits 1:0 . + */ + shift = (7 - (index & 7)) * 2; + } else { + addr = &priv->grf->gpio1_p[banknum - 1][ind]; + shift = (7 - (index & 7)) * 2; + } + debug("%s: addr=%p, val=%x, shift=%x\n", __func__, addr, val, + shift); + rk_clrsetreg(addr, 3 << shift, val << shift); + } + + return 0; +} + +static int rk3188_pinctrl_set_state(struct udevice *dev, struct udevice *config) +{ + const void *blob = gd->fdt_blob; + int pcfg_node, ret, flags, count, i; + u32 cell[60], *ptr; + + debug("%s: %s %s\n", __func__, dev->name, config->name); + ret = fdtdec_get_int_array_count(blob, config->of_offset, + "rockchip,pins", cell, + ARRAY_SIZE(cell)); + if (ret < 0) { + debug("%s: bad array %d\n", __func__, ret); + return -EINVAL; + } + count = ret; + for (i = 0, ptr = cell; i < count; i += 4, ptr += 4) { + pcfg_node = fdt_node_offset_by_phandle(blob, ptr[3]); + if (pcfg_node < 0) + return -EINVAL; + flags = pinctrl_decode_pin_config(blob, pcfg_node); + if (flags < 0) + return flags; + + ret = rk3188_pinctrl_set_pins(dev, ptr[0], ptr[1], ptr[2], + flags); + if (ret) + return ret; + } + + return 0; +} +#endif + +static struct pinctrl_ops rk3188_pinctrl_ops = { +#ifndef CONFIG_SPL_BUILD + .set_state = rk3188_pinctrl_set_state, + .get_gpio_mux = rk3188_pinctrl_get_gpio_mux, +#endif + .set_state_simple = rk3188_pinctrl_set_state_simple, + .request = rk3188_pinctrl_request, + .get_periph_id = rk3188_pinctrl_get_periph_id, +}; + +#ifndef CONFIG_SPL_BUILD +static int rk3188_pinctrl_parse_tables(struct rk3188_pinctrl_priv *priv, + struct rockchip_pin_bank *banks, + int count) +{ + struct rockchip_pin_bank *bank; + uint reg, muxnum, banknum; + + reg = 0; + for (banknum = 0; banknum < count; banknum++) { + bank = &banks[banknum]; + bank->reg = reg; + debug("%s: bank %d, reg %x\n", __func__, banknum, reg * 4); + for (muxnum = 0; muxnum < 4; muxnum++) { + struct rockchip_iomux *mux = &bank->iomux[muxnum]; + + mux->offset = reg; + reg += 1; + } + } + + return 0; +} +#endif + +static int rk3188_pinctrl_probe(struct udevice *dev) +{ + struct rk3188_pinctrl_priv *priv = dev_get_priv(dev); + int ret = 0; + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); + debug("%s: grf=%p, pmu=%p\n", __func__, priv->grf, priv->pmu); +#ifndef CONFIG_SPL_BUILD + ret = rk3188_pinctrl_parse_tables(priv, rk3188_pin_banks, + ARRAY_SIZE(rk3188_pin_banks)); +#endif + + return ret; +} + +static const struct udevice_id rk3188_pinctrl_ids[] = { + { .compatible = "rockchip,rk3188-pinctrl" }, + { } +}; + +U_BOOT_DRIVER(pinctrl_rk3188) = { + .name = "rockchip_rk3188_pinctrl", + .id = UCLASS_PINCTRL, + .of_match = rk3188_pinctrl_ids, + .priv_auto_alloc_size = sizeof(struct rk3188_pinctrl_priv), + .ops = &rk3188_pinctrl_ops, +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + .bind = dm_scan_fdt_dev, +#endif + .probe = rk3188_pinctrl_probe, +};

Add a driver for setting up and modifying the various PLLs and peripheral clocks on the RK3188.

Signed-off-by: Heiko Stuebner heiko@sntech.de --- arch/arm/include/asm/arch-rockchip/cru_rk3188.h | 191 +++++++++ drivers/clk/rockchip/Makefile | 1 + drivers/clk/rockchip/clk_rk3188.c | 523 ++++++++++++++++++++++++ 3 files changed, 715 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/cru_rk3188.h create mode 100644 drivers/clk/rockchip/clk_rk3188.c

diff --git a/arch/arm/include/asm/arch-rockchip/cru_rk3188.h b/arch/arm/include/asm/arch-rockchip/cru_rk3188.h new file mode 100644 index 0000000000..74f0fedcc6 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/cru_rk3188.h @@ -0,0 +1,191 @@ +/* + * (C) Copyright 2016 Heiko Stuebner heiko@sntech.de + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#ifndef _ASM_ARCH_CRU_RK3188_H +#define _ASM_ARCH_CRU_RK3188_H + +#define OSC_HZ (24 * 1000 * 1000) + +#define APLL_HZ (1608 * 1000000) +#define GPLL_HZ (594 * 1000000) +#define CPLL_HZ (384 * 1000000) + +/* The SRAM is clocked off aclk_cpu, so we want to max it out for boot speed */ +#define CPU_ACLK_HZ 297000000 +#define CPU_HCLK_HZ 148500000 +#define CPU_PCLK_HZ 74250000 +#define CPU_H2P_HZ 74250000 + +#define PERI_ACLK_HZ 148500000 +#define PERI_HCLK_HZ 148500000 +#define PERI_PCLK_HZ 74250000 + +/* Private data for the clock driver - used by rockchip_get_cru() */ +struct rk3188_clk_priv { + struct rk3188_grf *grf; + struct rk3188_cru *cru; + ulong rate; + bool has_bwadj; +}; + +struct rk3188_cru { + struct rk3188_pll { + u32 con0; + u32 con1; + u32 con2; + u32 con3; + } pll[4]; + u32 cru_mode_con; + u32 cru_clksel_con[35]; + u32 cru_clkgate_con[10]; + u32 reserved1[2]; + u32 cru_glb_srst_fst_value; + u32 cru_glb_srst_snd_value; + u32 reserved2[2]; + u32 cru_softrst_con[9]; + u32 cru_misc_con; + u32 reserved3[2]; + u32 cru_glb_cnt_th; +}; +check_member(rk3188_cru, cru_glb_cnt_th, 0x0140); + +/* CRU_CLKSEL0_CON */ +enum { + /* a9_core_div: core = core_src / (a9_core_div + 1) */ + A9_CORE_DIV_SHIFT = 9, + A9_CORE_DIV_MASK = 0x1f, + CORE_PLL_SHIFT = 8, + CORE_PLL_MASK = 1, + CORE_PLL_SELECT_APLL = 0, + CORE_PLL_SELECT_GPLL, + + /* core peri div: core:core_peri = 2:1, 4:1, 8:1 or 16:1 */ + CORE_PERI_DIV_SHIFT = 6, + CORE_PERI_DIV_MASK = 3, + + /* aclk_cpu pll selection */ + CPU_ACLK_PLL_SHIFT = 5, + CPU_ACLK_PLL_MASK = 1, + CPU_ACLK_PLL_SELECT_APLL = 0, + CPU_ACLK_PLL_SELECT_GPLL, + + /* a9_cpu_div: aclk_cpu = cpu_src / (a9_cpu_div + 1) */ + A9_CPU_DIV_SHIFT = 0, + A9_CPU_DIV_MASK = 0x1f, +}; + +/* CRU_CLKSEL1_CON */ +enum { + /* ahb2apb_pclk_div: hclk_cpu:pclk_cpu = 1:1, 2:1 or 4:1 */ + AHB2APB_DIV_SHIFT = 14, + AHB2APB_DIV_MASK = 3, + + /* cpu_pclk_div: aclk_cpu:pclk_cpu = 1:1, 2:1, 4:1 or 8:1 */ + CPU_PCLK_DIV_SHIFT = 12, + CPU_PCLK_DIV_MASK = 3, + + /* cpu_hclk_div: aclk_cpu:hclk_cpu = 1:1, 2:1 or 4:1 */ + CPU_HCLK_DIV_SHIFT = 8, + CPU_HCLK_DIV_MASK = 3, + + /* core_aclk_div: cire:aclk_core = 1:1, 2:1, 3:1, 4:1 or 8:1 */ + CORE_ACLK_DIV_SHIFT = 3, + CORE_ACLK_DIV_MASK = 7, +}; + +/* CRU_CLKSEL10_CON */ +enum { + PERI_SEL_PLL_MASK = 1, + PERI_SEL_PLL_SHIFT = 15, + PERI_SEL_CPLL = 0, + PERI_SEL_GPLL, + + /* peri pclk div: aclk_bus:pclk_bus = 1:1, 2:1, 4:1 or 8:1 */ + PERI_PCLK_DIV_SHIFT = 12, + PERI_PCLK_DIV_MASK = 3, + + /* peripheral bus hclk div:aclk_bus: hclk_bus = 1:1, 2:1 or 4:1 */ + PERI_HCLK_DIV_SHIFT = 8, + PERI_HCLK_DIV_MASK = 3, + + /* peri aclk div: aclk_peri = periph_src / (peri_aclk_div + 1) */ + PERI_ACLK_DIV_SHIFT = 0, + PERI_ACLK_DIV_MASK = 0x1f, +}; +/* CRU_CLKSEL11_CON */ +enum { + HSICPHY_DIV_SHIFT = 8, + HSICPHY_DIV_MASK = 0x3f, + + MMC0_DIV_SHIFT = 0, + MMC0_DIV_MASK = 0x3f, +}; + +/* CRU_CLKSEL12_CON */ +enum { + UART_PLL_SHIFT = 15, + UART_PLL_MASK = 1, + UART_PLL_SELECT_GENERAL = 0, + UART_PLL_SELECT_CODEC, + + EMMC_DIV_SHIFT = 8, + EMMC_DIV_MASK = 0x3f, + + SDIO_DIV_SHIFT = 0, + SDIO_DIV_MASK = 0x3f, +}; + +/* CRU_CLKSEL25_CON */ +enum { + SPI1_DIV_SHIFT = 8, + SPI1_DIV_MASK = 0x7f, + + SPI0_DIV_SHIFT = 0, + SPI0_DIV_MASK = 0x7f, +}; + +/* CRU_MODE_CON */ +enum { + GPLL_MODE_SHIFT = 12, + GPLL_MODE_MASK = 3, + GPLL_MODE_SLOW = 0, + GPLL_MODE_NORMAL, + GPLL_MODE_DEEP, + + CPLL_MODE_SHIFT = 8, + CPLL_MODE_MASK = 3, + CPLL_MODE_SLOW = 0, + CPLL_MODE_NORMAL, + CPLL_MODE_DEEP, + + DPLL_MODE_SHIFT = 4, + DPLL_MODE_MASK = 3, + DPLL_MODE_SLOW = 0, + DPLL_MODE_NORMAL, + DPLL_MODE_DEEP, + + APLL_MODE_SHIFT = 0, + APLL_MODE_MASK = 3, + APLL_MODE_SLOW = 0, + APLL_MODE_NORMAL, + APLL_MODE_DEEP, +}; + +/* CRU_APLL_CON0 */ +enum { + CLKR_SHIFT = 8, + CLKR_MASK = 0x3f, + + CLKOD_SHIFT = 0, + CLKOD_MASK = 0x3f, +}; + +/* CRU_APLL_CON1 */ +enum { + CLKF_SHIFT = 0, + CLKF_MASK = 0x1fff, +}; + +#endif diff --git a/drivers/clk/rockchip/Makefile b/drivers/clk/rockchip/Makefile index 1f8e41739d..b66e81e810 100644 --- a/drivers/clk/rockchip/Makefile +++ b/drivers/clk/rockchip/Makefile @@ -5,5 +5,6 @@ #

obj-$(CONFIG_ROCKCHIP_RK3036) += clk_rk3036.o +obj-$(CONFIG_ROCKCHIP_RK3188) += clk_rk3188.o obj-$(CONFIG_ROCKCHIP_RK3288) += clk_rk3288.o obj-$(CONFIG_ROCKCHIP_RK3399) += clk_rk3399.o diff --git a/drivers/clk/rockchip/clk_rk3188.c b/drivers/clk/rockchip/clk_rk3188.c new file mode 100644 index 0000000000..c276772136 --- /dev/null +++ b/drivers/clk/rockchip/clk_rk3188.c @@ -0,0 +1,523 @@ +/* + * (C) Copyright 2015 Google, Inc + * (C) Copyright 2016 Heiko Stuebner heiko@sntech.de + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#include <common.h> +#include <clk-uclass.h> +#include <dm.h> +#include <dt-structs.h> +#include <errno.h> +#include <mapmem.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3188.h> +#include <asm/arch/grf_rk3188.h> +#include <asm/arch/hardware.h> +#include <dt-bindings/clock/rk3188-cru.h> +#include <dm/device-internal.h> +#include <dm/lists.h> +#include <dm/uclass-internal.h> +#include <linux/log2.h> + +DECLARE_GLOBAL_DATA_PTR; + +enum rk3188_clk_type { + RK3188_CRU, + RK3188A_CRU, +}; + +struct rk3188_clk_plat { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3188_cru dtd; +#endif +}; + +struct pll_div { + u32 nr; + u32 nf; + u32 no; +}; + +enum { + VCO_MAX_HZ = 2200U * 1000000, + VCO_MIN_HZ = 440 * 1000000, + OUTPUT_MAX_HZ = 2200U * 1000000, + OUTPUT_MIN_HZ = 30 * 1000000, + FREF_MAX_HZ = 2200U * 1000000, + FREF_MIN_HZ = 30 * 1000, +}; + +enum { + /* PLL CON0 */ + PLL_OD_MASK = 0x0f, + + /* PLL CON1 */ + PLL_NF_MASK = 0x1fff, + + /* PLL CON2 */ + PLL_BWADJ_MASK = 0x0fff, + + /* PLL CON3 */ + PLL_RESET_SHIFT = 5, + + /* GRF_SOC_STATUS0 */ + SOCSTS_DPLL_LOCK = 1 << 5, + SOCSTS_APLL_LOCK = 1 << 6, + SOCSTS_CPLL_LOCK = 1 << 7, + SOCSTS_GPLL_LOCK = 1 << 8, +}; + +#define RATE_TO_DIV(input_rate, output_rate) \ + ((input_rate) / (output_rate) - 1); + +#define DIV_TO_RATE(input_rate, div) ((input_rate) / ((div) + 1)) + +#define PLL_DIVISORS(hz, _nr, _no) {\ + .nr = _nr, .nf = (u32)((u64)hz * _nr * _no / OSC_HZ), .no = _no};\ + _Static_assert(((u64)hz * _nr * _no / OSC_HZ) * OSC_HZ /\ + (_nr * _no) == hz, #hz "Hz cannot be hit with PLL "\ + "divisors on line " __stringify(__LINE__)); + +/* Keep divisors as low as possible to reduce jitter and power usage */ +static const struct pll_div gpll_init_cfg = PLL_DIVISORS(GPLL_HZ, 2, 2); +static const struct pll_div cpll_init_cfg = PLL_DIVISORS(CPLL_HZ, 1, 2); + +static int rkclk_set_pll(struct rk3188_cru *cru, enum rk_clk_id clk_id, + const struct pll_div *div, bool has_bwadj) +{ + int pll_id = rk_pll_id(clk_id); + struct rk3188_pll *pll = &cru->pll[pll_id]; + /* All PLLs have same VCO and output frequency range restrictions. */ + uint vco_hz = OSC_HZ / 1000 * div->nf / div->nr * 1000; + uint output_hz = vco_hz / div->no; + + debug("PLL at %x: nf=%d, nr=%d, no=%d, vco=%u Hz, output=%u Hz\n", + (uint)pll, div->nf, div->nr, div->no, vco_hz, output_hz); + assert(vco_hz >= VCO_MIN_HZ && vco_hz <= VCO_MAX_HZ && + output_hz >= OUTPUT_MIN_HZ && output_hz <= OUTPUT_MAX_HZ && + (div->no == 1 || !(div->no % 2))); + + /* enter reset */ + rk_setreg(&pll->con3, 1 << PLL_RESET_SHIFT); + + rk_clrsetreg(&pll->con0, + CLKR_MASK << CLKR_SHIFT | PLL_OD_MASK, + ((div->nr - 1) << CLKR_SHIFT) | (div->no - 1)); + rk_clrsetreg(&pll->con1, CLKF_MASK, div->nf - 1); + + if (has_bwadj) + rk_clrsetreg(&pll->con2, PLL_BWADJ_MASK, (div->nf >> 1) - 1); + + udelay(10); + + /* return from reset */ + rk_clrreg(&pll->con3, 1 << PLL_RESET_SHIFT); + + return 0; +} + +static int rkclk_configure_ddr(struct rk3188_cru *cru, struct rk3188_grf *grf, + unsigned int hz, bool has_bwadj) +{ + static const struct pll_div dpll_cfg[] = { + {.nf = 25, .nr = 2, .no = 1}, + {.nf = 400, .nr = 9, .no = 2}, + {.nf = 500, .nr = 9, .no = 2}, + {.nf = 100, .nr = 3, .no = 1}, + }; + int cfg; + + switch (hz) { + case 300000000: + cfg = 0; + break; + case 533000000: /* actually 533.3P MHz */ + cfg = 1; + break; + case 666000000: /* actually 666.6P MHz */ + cfg = 2; + break; + case 800000000: + cfg = 3; + break; + default: + debug("Unsupported SDRAM frequency"); + return -EINVAL; + } + + /* pll enter slow-mode */ + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, + DPLL_MODE_SLOW << DPLL_MODE_SHIFT); + + rkclk_set_pll(cru, CLK_DDR, &dpll_cfg[cfg], has_bwadj); + + /* wait for pll lock */ + while (!(readl(&grf->soc_status0) & SOCSTS_DPLL_LOCK)) + udelay(1); + + /* PLL enter normal-mode */ + rk_clrsetreg(&cru->cru_mode_con, DPLL_MODE_MASK << DPLL_MODE_SHIFT, + DPLL_MODE_NORMAL << DPLL_MODE_SHIFT); + + return 0; +} + +#ifdef CONFIG_SPL_BUILD +static void rkclk_init(struct rk3188_cru *cru, struct rk3188_grf *grf, + bool has_bwadj) +{ + u32 aclk_div, hclk_div, pclk_div, h2p_div; + + /* pll enter slow-mode */ + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK << GPLL_MODE_SHIFT | + CPLL_MODE_MASK << CPLL_MODE_SHIFT, + GPLL_MODE_SLOW << GPLL_MODE_SHIFT | + CPLL_MODE_SLOW << CPLL_MODE_SHIFT); + + /* init pll */ + rkclk_set_pll(cru, CLK_GENERAL, &gpll_init_cfg, has_bwadj); + rkclk_set_pll(cru, CLK_CODEC, &cpll_init_cfg, has_bwadj); + + /* waiting for pll lock */ + while ((readl(&grf->soc_status0) & + (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) != + (SOCSTS_CPLL_LOCK | SOCSTS_GPLL_LOCK)) + udelay(1); + + /* + * cpu clock pll source selection and + * reparent aclk_cpu_pre from apll to gpll + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + aclk_div = RATE_TO_DIV(GPLL_HZ, CPU_ACLK_HZ); + assert((aclk_div + 1) * CPU_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + + rk_clrsetreg(&cru->cru_clksel_con[0], + CPU_ACLK_PLL_MASK << CPU_ACLK_PLL_SHIFT | + A9_CPU_DIV_MASK << A9_CPU_DIV_SHIFT, + CPU_ACLK_PLL_SELECT_GPLL << CPU_ACLK_PLL_SHIFT | + aclk_div << A9_CPU_DIV_SHIFT); + + hclk_div = ilog2(CPU_ACLK_HZ / CPU_HCLK_HZ); + assert((1 << hclk_div) * CPU_HCLK_HZ == CPU_ACLK_HZ && hclk_div < 0x3); + pclk_div = ilog2(CPU_ACLK_HZ / CPU_PCLK_HZ); + assert((1 << pclk_div) * CPU_PCLK_HZ == CPU_ACLK_HZ && pclk_div < 0x4); + h2p_div = ilog2(CPU_HCLK_HZ / CPU_H2P_HZ); + assert((1 << h2p_div) * CPU_H2P_HZ == CPU_HCLK_HZ && pclk_div < 0x3); + + rk_clrsetreg(&cru->cru_clksel_con[1], + AHB2APB_DIV_MASK << AHB2APB_DIV_SHIFT | + CPU_PCLK_DIV_MASK << CPU_PCLK_DIV_SHIFT | + CPU_HCLK_DIV_MASK << CPU_HCLK_DIV_SHIFT, + h2p_div << AHB2APB_DIV_SHIFT | + pclk_div << CPU_PCLK_DIV_SHIFT | + hclk_div << CPU_HCLK_DIV_SHIFT); + + /* + * peri clock pll source selection and + * set up dependent divisors for PCLK/HCLK and ACLK clocks. + */ + aclk_div = GPLL_HZ / PERI_ACLK_HZ - 1; + assert((aclk_div + 1) * PERI_ACLK_HZ == GPLL_HZ && aclk_div < 0x1f); + + hclk_div = ilog2(PERI_ACLK_HZ / PERI_HCLK_HZ); + assert((1 << hclk_div) * PERI_HCLK_HZ == + PERI_ACLK_HZ && (hclk_div < 0x4)); + + pclk_div = ilog2(PERI_ACLK_HZ / PERI_PCLK_HZ); + assert((1 << pclk_div) * PERI_PCLK_HZ == + PERI_ACLK_HZ && (pclk_div < 0x4)); + + rk_clrsetreg(&cru->cru_clksel_con[10], + PERI_PCLK_DIV_MASK << PERI_PCLK_DIV_SHIFT | + PERI_HCLK_DIV_MASK << PERI_HCLK_DIV_SHIFT | + PERI_ACLK_DIV_MASK << PERI_ACLK_DIV_SHIFT, + PERI_SEL_GPLL << PERI_SEL_PLL_SHIFT | + pclk_div << PERI_PCLK_DIV_SHIFT | + hclk_div << PERI_HCLK_DIV_SHIFT | + aclk_div << PERI_ACLK_DIV_SHIFT); + + /* PLL enter normal-mode */ + rk_clrsetreg(&cru->cru_mode_con, + GPLL_MODE_MASK << GPLL_MODE_SHIFT | + CPLL_MODE_MASK << CPLL_MODE_SHIFT, + GPLL_MODE_NORMAL << GPLL_MODE_SHIFT | + CPLL_MODE_NORMAL << CPLL_MODE_SHIFT); +} +#endif + +/* Get pll rate by id */ +static uint32_t rkclk_pll_get_rate(struct rk3188_cru *cru, + enum rk_clk_id clk_id) +{ + uint32_t nr, no, nf; + uint32_t con; + int pll_id = rk_pll_id(clk_id); + struct rk3188_pll *pll = &cru->pll[pll_id]; + static u8 clk_shift[CLK_COUNT] = { + 0xff, APLL_MODE_SHIFT, DPLL_MODE_SHIFT, CPLL_MODE_SHIFT, + GPLL_MODE_SHIFT + }; + uint shift; + + con = readl(&cru->cru_mode_con); + shift = clk_shift[clk_id]; + switch ((con >> shift) & APLL_MODE_MASK) { + case APLL_MODE_SLOW: + return OSC_HZ; + case APLL_MODE_NORMAL: + /* normal mode */ + con = readl(&pll->con0); + no = ((con >> CLKOD_SHIFT) & CLKOD_MASK) + 1; + nr = ((con >> CLKR_SHIFT) & CLKR_MASK) + 1; + con = readl(&pll->con1); + nf = ((con >> CLKF_SHIFT) & CLKF_MASK) + 1; + + return (24 * nf / (nr * no)) * 1000000; + case APLL_MODE_DEEP: + default: + return 32768; + } +} + +static ulong rockchip_mmc_get_clk(struct rk3188_cru *cru, uint gclk_rate, + int periph) +{ + uint div; + u32 con; + + switch (periph) { + case HCLK_EMMC: + con = readl(&cru->cru_clksel_con[12]); + div = (con >> EMMC_DIV_SHIFT) & EMMC_DIV_MASK; + break; + case HCLK_SDMMC: + con = readl(&cru->cru_clksel_con[11]); + div = (con >> MMC0_DIV_SHIFT) & MMC0_DIV_MASK; + break; + case HCLK_SDIO: + con = readl(&cru->cru_clksel_con[12]); + div = (con >> SDIO_DIV_SHIFT) & SDIO_DIV_MASK; + break; + default: + return -EINVAL; + } + + return DIV_TO_RATE(gclk_rate, div); +} + +static ulong rockchip_mmc_set_clk(struct rk3188_cru *cru, uint gclk_rate, + int periph, uint freq) +{ + int src_clk_div; + + debug("%s: gclk_rate=%u\n", __func__, gclk_rate); + src_clk_div = RATE_TO_DIV(gclk_rate, freq); + assert(src_clk_div <= 0x3f); + + switch (periph) { + case HCLK_EMMC: + rk_clrsetreg(&cru->cru_clksel_con[12], + EMMC_DIV_MASK << EMMC_DIV_SHIFT, + src_clk_div << EMMC_DIV_SHIFT); + break; + case HCLK_SDMMC: + rk_clrsetreg(&cru->cru_clksel_con[11], + MMC0_DIV_MASK << MMC0_DIV_SHIFT, + src_clk_div << MMC0_DIV_SHIFT); + break; + case HCLK_SDIO: + rk_clrsetreg(&cru->cru_clksel_con[12], + SDIO_DIV_MASK << SDIO_DIV_SHIFT, + src_clk_div << SDIO_DIV_SHIFT); + break; + default: + return -EINVAL; + } + + return rockchip_mmc_get_clk(cru, gclk_rate, periph); +} + +static ulong rockchip_spi_get_clk(struct rk3188_cru *cru, uint gclk_rate, + int periph) +{ + uint div; + u32 con; + + switch (periph) { + case SCLK_SPI0: + con = readl(&cru->cru_clksel_con[25]); + div = (con >> SPI0_DIV_SHIFT) & SPI0_DIV_MASK; + break; + case SCLK_SPI1: + con = readl(&cru->cru_clksel_con[25]); + div = (con >> SPI1_DIV_SHIFT) & SPI1_DIV_MASK; + break; + default: + return -EINVAL; + } + + return DIV_TO_RATE(gclk_rate, div); +} + +static ulong rockchip_spi_set_clk(struct rk3188_cru *cru, uint gclk_rate, + int periph, uint freq) +{ + int src_clk_div = RATE_TO_DIV(gclk_rate, freq); + + switch (periph) { + case SCLK_SPI0: + assert(src_clk_div <= SPI0_DIV_MASK); + rk_clrsetreg(&cru->cru_clksel_con[25], + SPI0_DIV_MASK << SPI0_DIV_SHIFT, + src_clk_div << SPI0_DIV_SHIFT); + break; + case SCLK_SPI1: + assert(src_clk_div <= SPI1_DIV_MASK); + rk_clrsetreg(&cru->cru_clksel_con[25], + SPI1_DIV_MASK << SPI1_DIV_SHIFT, + src_clk_div << SPI1_DIV_SHIFT); + break; + default: + return -EINVAL; + } + + return rockchip_spi_get_clk(cru, gclk_rate, periph); +} + +static ulong rk3188_clk_get_rate(struct clk *clk) +{ + struct rk3188_clk_priv *priv = dev_get_priv(clk->dev); + ulong new_rate, gclk_rate; + + gclk_rate = rkclk_pll_get_rate(priv->cru, CLK_GENERAL); + switch (clk->id) { + case 1 ... 4: + new_rate = rkclk_pll_get_rate(priv->cru, clk->id); + break; + case HCLK_EMMC: + case HCLK_SDMMC: + case HCLK_SDIO: + new_rate = rockchip_mmc_get_clk(priv->cru, PERI_HCLK_HZ, + clk->id); + break; + case SCLK_SPI0: + case SCLK_SPI1: + new_rate = rockchip_spi_get_clk(priv->cru, PERI_PCLK_HZ, + clk->id); + break; + case PCLK_I2C0: + case PCLK_I2C1: + case PCLK_I2C2: + case PCLK_I2C3: + case PCLK_I2C4: + return gclk_rate; + default: + return -ENOENT; + } + + return new_rate; +} + +static ulong rk3188_clk_set_rate(struct clk *clk, ulong rate) +{ + struct rk3188_clk_priv *priv = dev_get_priv(clk->dev); + struct rk3188_cru *cru = priv->cru; + ulong new_rate; + + switch (clk->id) { + case CLK_DDR: + new_rate = rkclk_configure_ddr(priv->cru, priv->grf, rate, + priv->has_bwadj); + break; + case HCLK_EMMC: + case HCLK_SDMMC: + case HCLK_SDIO: + new_rate = rockchip_mmc_set_clk(cru, PERI_HCLK_HZ, + clk->id, rate); + break; + case SCLK_SPI0: + case SCLK_SPI1: + new_rate = rockchip_spi_set_clk(cru, PERI_PCLK_HZ, + clk->id, rate); + break; + default: + return -ENOENT; + } + + return new_rate; +} + +static struct clk_ops rk3188_clk_ops = { + .get_rate = rk3188_clk_get_rate, + .set_rate = rk3188_clk_set_rate, +}; + +static int rk3188_clk_ofdata_to_platdata(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3188_clk_priv *priv = dev_get_priv(dev); + + priv->cru = (struct rk3188_cru *)dev_get_addr(dev); +#endif + + return 0; +} + +static int rk3188_clk_probe(struct udevice *dev) +{ + struct rk3188_clk_priv *priv = dev_get_priv(dev); + enum rk3188_clk_type type = dev_get_driver_data(dev); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + if (IS_ERR(priv->grf)) + return PTR_ERR(priv->grf); + priv->has_bwadj = (type == RK3188A_CRU) ? 1 : 0; + +#ifdef CONFIG_SPL_BUILD +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3188_clk_plat *plat = dev_get_platdata(dev); + + priv->cru = map_sysmem(plat->dtd.reg[0], plat->dtd.reg[1]); +#endif + + rkclk_init(priv->cru, priv->grf, priv->has_bwadj); +#endif + + return 0; +} + +static int rk3188_clk_bind(struct udevice *dev) +{ + int ret; + + /* The reset driver does not have a device node, so bind it here */ + ret = device_bind_driver(gd->dm_root, "rk3188_sysreset", "reset", &dev); + if (ret) + debug("Warning: No rk3188 reset driver: ret=%d\n", ret); + + return 0; +} + +static const struct udevice_id rk3188_clk_ids[] = { + { .compatible = "rockchip,rk3188-cru", .data = RK3188_CRU }, + { .compatible = "rockchip,rk3188a-cru", .data = RK3188A_CRU }, + { } +}; + +U_BOOT_DRIVER(rockchip_rk3188_cru) = { + .name = "rockchip_rk3188_cru", + .id = UCLASS_CLK, + .of_match = rk3188_clk_ids, + .priv_auto_alloc_size = sizeof(struct rk3188_clk_priv), + .platdata_auto_alloc_size = sizeof(struct rk3188_clk_plat), + .ops = &rk3188_clk_ops, + .bind = rk3188_clk_bind, + .ofdata_to_platdata = rk3188_clk_ofdata_to_platdata, + .probe = rk3188_clk_probe, +};

Add the core architecture code for the rk3188. It doesn't support the SPL yet, as because of some unknown error it doesn't start yet.

Signed-off-by: Heiko Stuebner heiko@sntech.de --- arch/arm/mach-rockchip/Kconfig | 16 ++++ arch/arm/mach-rockchip/Makefile | 5 ++ arch/arm/mach-rockchip/rk3188/Kconfig | 24 +++++ arch/arm/mach-rockchip/rk3188/Makefile | 10 +++ arch/arm/mach-rockchip/rk3188/clk_rk3188.c | 33 +++++++ arch/arm/mach-rockchip/rk3188/syscon_rk3188.c | 55 ++++++++++++ include/configs/rk3188_common.h | 125 ++++++++++++++++++++++++++ 7 files changed, 268 insertions(+) create mode 100644 arch/arm/mach-rockchip/rk3188/Kconfig create mode 100644 arch/arm/mach-rockchip/rk3188/Makefile create mode 100644 arch/arm/mach-rockchip/rk3188/clk_rk3188.c create mode 100644 arch/arm/mach-rockchip/rk3188/syscon_rk3188.c create mode 100644 include/configs/rk3188_common.h

diff --git a/arch/arm/mach-rockchip/Kconfig b/arch/arm/mach-rockchip/Kconfig index a776df35f4..ba9fbbbd33 100644 --- a/arch/arm/mach-rockchip/Kconfig +++ b/arch/arm/mach-rockchip/Kconfig @@ -11,6 +11,21 @@ config ROCKCHIP_RK3036 and video codec support. Peripherals include Gigabit Ethernet, USB2 host and OTG, SDIO, I2S, UART, SPI, I2C and PWMs.

+config ROCKCHIP_RK3188 + bool "Support Rockchip RK3188" + select CPU_V7 + select SUPPORT_SPL + select SUPPORT_TPL + select SPL + select TPL + select ROCKCHIP_BROM_HELPER + help + The Rockchip RK3188 is a ARM-based SoC with a quad-core Cortex-A9 + including NEON and GPU, 512KB L2 cache, Mali-400 graphics, two + video interfaces, several memory options and video codec support. + Peripherals include Fast Ethernet, USB2 host and OTG, SDIO, I2S, + UART, SPI, I2C and PWMs. + config ROCKCHIP_RK3288 bool "Support Rockchip RK3288" select CPU_V7 @@ -50,6 +65,7 @@ config SPL_MMC_SUPPORT default y if !ROCKCHIP_SPL_BACK_TO_BROM

source "arch/arm/mach-rockchip/rk3036/Kconfig" +source "arch/arm/mach-rockchip/rk3188/Kconfig" source "arch/arm/mach-rockchip/rk3288/Kconfig" source "arch/arm/mach-rockchip/rk3399/Kconfig" endif diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index f9ccc9bb2c..2be7e14e3e 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -16,5 +16,10 @@ ifndef CONFIG_ARM64 obj-y += rk_timer.o endif obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036/ + +ifndef CONFIG_TPL_BUILD +obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188/ +endif + obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288/ obj-$(CONFIG_ROCKCHIP_RK3399) += rk3399/ diff --git a/arch/arm/mach-rockchip/rk3188/Kconfig b/arch/arm/mach-rockchip/rk3188/Kconfig new file mode 100644 index 0000000000..f8e1d0316b --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188/Kconfig @@ -0,0 +1,24 @@ +if ROCKCHIP_RK3188 + +config SYS_SOC + default "rockchip" + +config SYS_MALLOC_F_LEN + default 0x0800 + +config SPL_LIBCOMMON_SUPPORT + default y + +config SPL_LIBGENERIC_SUPPORT + default y + +config SPL_SERIAL_SUPPORT + default y + +config TPL_LIBCOMMON_SUPPORT + default y + +config TPL_SERIAL_SUPPORT + default y + +endif diff --git a/arch/arm/mach-rockchip/rk3188/Makefile b/arch/arm/mach-rockchip/rk3188/Makefile new file mode 100644 index 0000000000..7fa010405b --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188/Makefile @@ -0,0 +1,10 @@ +# +# Copyright (c) 2015 Google, Inc +# +# SPDX-License-Identifier: GPL-2.0+ +# + +ifndef CONFIG_TPL_BUILD +obj-y += clk_rk3188.o +obj-y += syscon_rk3188.o +endif diff --git a/arch/arm/mach-rockchip/rk3188/clk_rk3188.c b/arch/arm/mach-rockchip/rk3188/clk_rk3188.c new file mode 100644 index 0000000000..1ec9e1cb75 --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188/clk_rk3188.c @@ -0,0 +1,33 @@ +/* + * Copyright (C) 2015 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3188.h> + +int rockchip_get_clk(struct udevice **devp) +{ + return uclass_get_device_by_driver(UCLASS_CLK, + DM_GET_DRIVER(rockchip_rk3188_cru), devp); +} + +void *rockchip_get_cru(void) +{ + struct rk3188_clk_priv *priv; + struct udevice *dev; + int ret; + + ret = rockchip_get_clk(&dev); + if (ret) + return ERR_PTR(ret); + + priv = dev_get_priv(dev); + + return priv->cru; +} diff --git a/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c new file mode 100644 index 0000000000..aeee6bfcad --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188/syscon_rk3188.c @@ -0,0 +1,55 @@ +/* + * Copyright (C) 2015 Google, Inc + * Written by Simon Glass sjg@chromium.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <dm.h> +#include <syscon.h> +#include <asm/arch/clock.h> + +static const struct udevice_id rk3188_syscon_ids[] = { + { .compatible = "rockchip,rk3188-noc", .data = ROCKCHIP_SYSCON_NOC }, + { .compatible = "rockchip,rk3188-grf", .data = ROCKCHIP_SYSCON_GRF }, + { .compatible = "rockchip,rk3188-pmu", .data = ROCKCHIP_SYSCON_PMU }, + { } +}; + +U_BOOT_DRIVER(syscon_rk3188) = { + .name = "rk3188_syscon", + .id = UCLASS_SYSCON, + .of_match = rk3188_syscon_ids, +}; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int rk3188_syscon_bind_of_platdata(struct udevice *dev) +{ + dev->driver_data = dev->driver->of_match->data; + debug("syscon: %s %d\n", dev->name, (uint)dev->driver_data); + + return 0; +} + +U_BOOT_DRIVER(rockchip_rk3188_noc) = { + .name = "rockchip_rk3188_noc", + .id = UCLASS_SYSCON, + .of_match = rk3188_syscon_ids, + .bind = rk3188_syscon_bind_of_platdata, +}; + +U_BOOT_DRIVER(rockchip_rk3188_grf) = { + .name = "rockchip_rk3188_grf", + .id = UCLASS_SYSCON, + .of_match = rk3188_syscon_ids + 1, + .bind = rk3188_syscon_bind_of_platdata, +}; + +U_BOOT_DRIVER(rockchip_rk3188_pmu) = { + .name = "rockchip_rk3188_pmu", + .id = UCLASS_SYSCON, + .of_match = rk3188_syscon_ids + 2, + .bind = rk3188_syscon_bind_of_platdata, +}; +#endif diff --git a/include/configs/rk3188_common.h b/include/configs/rk3188_common.h new file mode 100644 index 0000000000..3bd04214ec --- /dev/null +++ b/include/configs/rk3188_common.h @@ -0,0 +1,125 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __CONFIG_RK3188_COMMON_H +#define __CONFIG_RK3188_COMMON_H + +#define CONFIG_SYS_CACHELINE_SIZE 64 + +#include <asm/arch/hardware.h> +#include "rockchip-common.h" + +#define CONFIG_SKIP_LOWLEVEL_INIT_ONLY +#define CONFIG_SYS_NO_FLASH +#define CONFIG_NR_DRAM_BANKS 1 +#define CONFIG_ENV_SIZE 0x2000 +#define CONFIG_SYS_MAXARGS 16 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SYS_MALLOC_LEN (32 << 20) +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_THUMB_BUILD + +#define CONFIG_SYS_TIMER_RATE (24 * 1000 * 1000) +#define CONFIG_SYS_TIMER_BASE 0x2000e000 /* TIMER3 */ +#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMER_BASE + 8) +#define CONFIG_SYS_TIMER_COUNTS_DOWN + +#define CONFIG_SYS_NS16550_MEM32 +#define CONFIG_SPL_BOARD_INIT + +#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM +/* Bootrom will load u-boot binary to 0x60000000 once return from SPL */ +#define CONFIG_SYS_TEXT_BASE 0x60000000 +#else +#define CONFIG_SYS_TEXT_BASE 0x60100000 +#endif +#define CONFIG_SYS_INIT_SP_ADDR 0x60100000 +#define CONFIG_SYS_LOAD_ADDR 0x60800800 + +#define CONFIG_ROCKCHIP_MAX_INIT_SIZE (0x8000 - 0x800) +#define CONFIG_ROCKCHIP_CHIP_TAG "RK31" + +#ifdef CONFIG_TPL_BUILD +#define CONFIG_SPL_TEXT_BASE 0x10080804 +/* tpl size 1kb - 4byte RK31 header */ +#define CONFIG_SPL_MAX_SIZE (0x400 - 0x4) +#elif defined(CONFIG_SPL_BUILD) +/* spl size 32kb sram - 2kb bootrom - 1kb spl */ +#define CONFIG_SPL_MAX_SIZE (0x8000 - 0xC00) +#define CONFIG_SPL_TEXT_BASE 0x10080C00 +#define CONFIG_SPL_FRAMEWORK 1 +#define CONFIG_SPL_CLK 1 +#define CONFIG_SPL_PINCTRL 1 +#define CONFIG_SPL_REGMAP 1 +#define CONFIG_SPL_SYSCON 1 +#define CONFIG_SPL_RAM 1 +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT 1 +#define CONFIG_ROCKCHIP_SERIAL 1 +#endif + +#define CONFIG_SPL_STACK 0x10087fff + +/* MMC/SD IP block */ +#define CONFIG_GENERIC_MMC +#define CONFIG_BOUNCE_BUFFER + +#define CONFIG_DOS_PARTITION +#define CONFIG_FAT_WRITE +#define CONFIG_PARTITION_UUIDS +#define CONFIG_CMD_PART + +#define CONFIG_SYS_SDRAM_BASE 0x60000000 +#define CONFIG_NR_DRAM_BANKS 1 +#define SDRAM_BANK_SIZE (2UL << 30) + +#define CONFIG_SPI_FLASH +#define CONFIG_SPI +#define CONFIG_SF_DEFAULT_SPEED 20000000 + +#ifndef CONFIG_SPL_BUILD +/* usb otg */ +#define CONFIG_USB_GADGET +#define CONFIG_USB_GADGET_DUALSPEED +#define CONFIG_USB_GADGET_DWC2_OTG +#define CONFIG_ROCKCHIP_USB2_PHY +#define CONFIG_USB_GADGET_VBUS_DRAW 0 + +#define CONFIG_USB_GADGET_DOWNLOAD +#define CONFIG_G_DNL_MANUFACTURER "Rockchip" +#define CONFIG_G_DNL_VENDOR_NUM 0x2207 +#define CONFIG_G_DNL_PRODUCT_NUM 0x310a + +/* usb host support */ +#ifdef CONFIG_CMD_USB +#define CONFIG_USB_DWC2 +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_ETHER_ASIX +#endif +#define ENV_MEM_LAYOUT_SETTINGS \ + "scriptaddr=0x60000000\0" \ + "pxefile_addr_r=0x60100000\0" \ + "fdt_addr_r=0x61f00000\0" \ + "kernel_addr_r=0x62000000\0" \ + "ramdisk_addr_r=0x64000000\0" + +#include <config_distro_bootcmd.h> + +/* Linux fails to load the fdt if it's loaded above 256M on a Rock board, + * so limit the fdt reallocation to that */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "fdt_high=0x6fffffff\0" \ + "initrd_high=0x6fffffff\0" \ + "partitions=" PARTS_DEFAULT \ + ENV_MEM_LAYOUT_SETTINGS \ + ROCKCHIP_DEVICE_SETTINGS \ + BOOTENV + +#endif /* CONFIG_SPL_BUILD */ + +#define CONFIG_PREBOOT + +#endif

The sdram controller blocks are very similar to the rk3288 in utilizing memory scheduler, Designware uPCTL and Designware PUBL blocks, only limited to one bank instead of two.

There are some minimal differences when setting up the ram, so it gets a separate driver for the rk3188 but reuses the driver structs, as there is no need to define the same again.

More optimization can happen when the modelling of the controller parts in the dts actually follow the hardware layout hopefully at some point in the future.

Signed-off-by: Heiko Stuebner heiko@sntech.de --- arch/arm/include/asm/arch-rockchip/ddr_rk3188.h | 22 + arch/arm/mach-rockchip/rk3188/Makefile | 1 + arch/arm/mach-rockchip/rk3188/sdram_rk3188.c | 985 ++++++++++++++++++++++++ 3 files changed, 1008 insertions(+) create mode 100644 arch/arm/include/asm/arch-rockchip/ddr_rk3188.h create mode 100644 arch/arm/mach-rockchip/rk3188/sdram_rk3188.c

diff --git a/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h new file mode 100644 index 0000000000..993c58d1a8 --- /dev/null +++ b/arch/arm/include/asm/arch-rockchip/ddr_rk3188.h @@ -0,0 +1,22 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0 + */ + +#ifndef _ASM_ARCH_DDR_RK3188_H +#define _ASM_ARCH_DDR_RK3188_H + +#include <asm/arch/ddr_rk3288.h> + +struct rk3188_msch { + u32 coreid; + u32 revisionid; + u32 ddrconf; + u32 ddrtiming; + u32 ddrmode; + u32 readlatency; +}; +check_member(rk3188_msch, readlatency, 0x0014); + +#endif diff --git a/arch/arm/mach-rockchip/rk3188/Makefile b/arch/arm/mach-rockchip/rk3188/Makefile index 7fa010405b..2dc9511de7 100644 --- a/arch/arm/mach-rockchip/rk3188/Makefile +++ b/arch/arm/mach-rockchip/rk3188/Makefile @@ -6,5 +6,6 @@

ifndef CONFIG_TPL_BUILD obj-y += clk_rk3188.o +obj-y += sdram_rk3188.o obj-y += syscon_rk3188.o endif diff --git a/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c b/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c new file mode 100644 index 0000000000..9e41723c9f --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188/sdram_rk3188.c @@ -0,0 +1,985 @@ +/* + * (C) Copyright 2015 Google, Inc + * Copyright 2014 Rockchip Inc. + * + * SPDX-License-Identifier: GPL-2.0 + * + * Adapted from coreboot. + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <dt-structs.h> +#include <errno.h> +#include <ram.h> +#include <regmap.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/cru_rk3188.h> +#include <asm/arch/ddr_rk3188.h> +#include <asm/arch/grf_rk3188.h> +#include <asm/arch/pmu_rk3188.h> +#include <asm/arch/sdram.h> +#include <linux/err.h> + +DECLARE_GLOBAL_DATA_PTR; + +struct chan_info { + struct rk3288_ddr_pctl *pctl; + struct rk3288_ddr_publ *publ; + struct rk3188_msch *msch; +}; + +struct dram_info { + struct chan_info chan[1]; + struct ram_info info; + struct clk ddr_clk; + struct rk3188_cru *cru; + struct rk3188_grf *grf; + struct rk3188_sgrf *sgrf; + struct rk3188_pmu *pmu; +}; + +struct rk3188_sdram_params { +#if CONFIG_IS_ENABLED(OF_PLATDATA) + struct dtd_rockchip_rk3188_dmc of_plat; +#endif + struct rk3288_sdram_channel ch[2]; + struct rk3288_sdram_pctl_timing pctl_timing; + struct rk3288_sdram_phy_timing phy_timing; + struct rk3288_base_params base; + int num_channels; + struct regmap *map; +}; + +#define TEST_PATTEN 0x5aa5f00f +#define DQS_GATE_TRAINING_ERROR_RANK0 (1 << 4) +#define DQS_GATE_TRAINING_ERROR_RANK1 (2 << 4) + +#ifdef CONFIG_SPL_BUILD +static void copy_to_reg(u32 *dest, const u32 *src, u32 n) +{ + int i; + + for (i = 0; i < n / sizeof(u32); i++) { + writel(*src, dest); + src++; + dest++; + } +} + +static void ddr_reset(struct rk3188_cru *cru, u32 ch, u32 ctl, u32 phy) +{ + u32 phy_ctl_srstn_shift = 5 + 8 * ch; + u32 ctl_psrstn_shift = 3 + 8 * ch; + u32 ctl_srstn_shift = 2 + 8 * ch; + u32 phy_psrstn_shift = 1 + 8 * ch; + u32 phy_srstn_shift = 8 * ch; + + rk_clrsetreg(&cru->cru_softrst_con[5], + 1 << phy_ctl_srstn_shift | 1 << ctl_psrstn_shift | + 1 << ctl_srstn_shift | 1 << phy_psrstn_shift | + 1 << phy_srstn_shift, + phy << phy_ctl_srstn_shift | ctl << ctl_psrstn_shift | + ctl << ctl_srstn_shift | phy << phy_psrstn_shift | + phy << phy_srstn_shift); +} + +static void ddr_phy_ctl_reset(struct rk3188_cru *cru, u32 ch, u32 n) +{ + u32 phy_ctl_srstn_shift = 5 + 8 * ch; + + rk_clrsetreg(&cru->cru_softrst_con[5], + 1 << phy_ctl_srstn_shift, n << phy_ctl_srstn_shift); +} + +static void phy_pctrl_reset(struct rk3188_cru *cru, + struct rk3288_ddr_publ *publ, + u32 channel) +{ + int i; + + ddr_reset(cru, channel, 1, 1); + udelay(1); + clrbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); + for (i = 0; i < 4; i++) + clrbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); + + udelay(10); + setbits_le32(&publ->acdllcr, ACDLLCR_DLLSRST); + for (i = 0; i < 4; i++) + setbits_le32(&publ->datx8[i].dxdllcr, DXDLLCR_DLLSRST); + + udelay(10); + ddr_reset(cru, channel, 1, 0); + udelay(10); + ddr_reset(cru, channel, 0, 0); + udelay(10); +} + +static void phy_dll_bypass_set(struct rk3288_ddr_publ *publ, + u32 freq) +{ + int i; + if (freq <= 250000000) { + if (freq <= 150000000) + clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); + else + setbits_le32(&publ->dllgcr, SBIAS_BYPASS); + setbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); + for (i = 0; i < 4; i++) + setbits_le32(&publ->datx8[i].dxdllcr, + DXDLLCR_DLLDIS); + + setbits_le32(&publ->pir, PIR_DLLBYP); + } else { + clrbits_le32(&publ->dllgcr, SBIAS_BYPASS); + clrbits_le32(&publ->acdllcr, ACDLLCR_DLLDIS); + for (i = 0; i < 4; i++) { + clrbits_le32(&publ->datx8[i].dxdllcr, + DXDLLCR_DLLDIS); + } + + clrbits_le32(&publ->pir, PIR_DLLBYP); + } +} + +static void dfi_cfg(struct rk3288_ddr_pctl *pctl, u32 dramtype) +{ + writel(DFI_INIT_START, &pctl->dfistcfg0); + writel(DFI_DRAM_CLK_SR_EN | DFI_DRAM_CLK_DPD_EN, + &pctl->dfistcfg1); + writel(DFI_PARITY_INTR_EN | DFI_PARITY_EN, &pctl->dfistcfg2); + writel(7 << TLP_RESP_TIME_SHIFT | LP_SR_EN | LP_PD_EN, + &pctl->dfilpcfg0); + + writel(2 << TCTRL_DELAY_TIME_SHIFT, &pctl->dfitctrldelay); + writel(1 << TPHY_WRDATA_TIME_SHIFT, &pctl->dfitphywrdata); + writel(0xf << TPHY_RDLAT_TIME_SHIFT, &pctl->dfitphyrdlat); + writel(2 << TDRAM_CLK_DIS_TIME_SHIFT, &pctl->dfitdramclkdis); + writel(2 << TDRAM_CLK_EN_TIME_SHIFT, &pctl->dfitdramclken); + writel(1, &pctl->dfitphyupdtype0); + + /* cs0 and cs1 write odt enable */ + writel((RANK0_ODT_WRITE_SEL | RANK1_ODT_WRITE_SEL), + &pctl->dfiodtcfg); + /* odt write length */ + writel(7 << ODT_LEN_BL8_W_SHIFT, &pctl->dfiodtcfg1); + /* phyupd and ctrlupd disabled */ + writel(0, &pctl->dfiupdcfg); +} + +static void ddr_set_enable(struct rk3188_grf *grf, uint channel, bool enable) +{ + uint val = 0; + + if (enable) + val = 1 << DDR_16BIT_EN_SHIFT; + + rk_clrsetreg(&grf->ddrc_con0, 1 << DDR_16BIT_EN_SHIFT, val); +} + +static void ddr_set_ddr3_mode(struct rk3188_grf *grf, uint channel, + bool ddr3_mode) +{ + uint mask, val; + + mask = 1 << MSCH4_MAINDDR3_SHIFT; + val = ddr3_mode << MSCH4_MAINDDR3_SHIFT; + rk_clrsetreg(&grf->soc_con2, mask, val); +} + +#define RANK_2_ROW15_EN 1 +static void ddr_rank_2_row15en(struct rk3188_grf *grf, bool enable) +{ + uint mask, val; + + mask = 1 << RANK_2_ROW15_EN; + val = enable << RANK_2_ROW15_EN; + rk_clrsetreg(&grf->soc_con2, mask, val); +} + +static void pctl_cfg(u32 channel, struct rk3288_ddr_pctl *pctl, + struct rk3188_sdram_params *sdram_params, + struct rk3188_grf *grf) +{ + copy_to_reg(&pctl->togcnt1u, &sdram_params->pctl_timing.togcnt1u, + sizeof(sdram_params->pctl_timing)); + switch (sdram_params->base.dramtype) { + case DDR3: + if (sdram_params->phy_timing.mr[1] & DDR3_DLL_DISABLE) { + writel(sdram_params->pctl_timing.tcl - 3, + &pctl->dfitrddataen); + } else { + writel(sdram_params->pctl_timing.tcl - 2, + &pctl->dfitrddataen); + } + writel(sdram_params->pctl_timing.tcwl - 1, + &pctl->dfitphywrlat); + writel(0 << MDDR_LPDDR2_CLK_STOP_IDLE_SHIFT | DDR3_EN | + DDR2_DDR3_BL_8 | (6 - 4) << TFAW_SHIFT | PD_EXIT_SLOW | + 1 << PD_TYPE_SHIFT | 0 << PD_IDLE_SHIFT, + &pctl->mcfg); + ddr_set_ddr3_mode(grf, channel, true); + ddr_set_enable(grf, channel, true); + break; + } + + setbits_le32(&pctl->scfg, 1); +} + +static void phy_cfg(const struct chan_info *chan, u32 channel, + struct rk3188_sdram_params *sdram_params) +{ + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3188_msch *msch = chan->msch; + uint ddr_freq_mhz = sdram_params->base.ddr_freq / 1000000; + u32 dinit2; + int i; + + dinit2 = DIV_ROUND_UP(ddr_freq_mhz * 200000, 1000); + /* DDR PHY Timing */ + copy_to_reg(&publ->dtpr[0], &sdram_params->phy_timing.dtpr0, + sizeof(sdram_params->phy_timing)); + writel(sdram_params->base.noc_timing, &msch->ddrtiming); + writel(0x3f, &msch->readlatency); + writel(DIV_ROUND_UP(ddr_freq_mhz * 5120, 1000) << PRT_DLLLOCK_SHIFT | + DIV_ROUND_UP(ddr_freq_mhz * 50, 1000) << PRT_DLLSRST_SHIFT | + 8 << PRT_ITMSRST_SHIFT, &publ->ptr[0]); + writel(DIV_ROUND_UP(ddr_freq_mhz * 500000, 1000) << PRT_DINIT0_SHIFT | + DIV_ROUND_UP(ddr_freq_mhz * 400, 1000) << PRT_DINIT1_SHIFT, + &publ->ptr[1]); + writel(min(dinit2, 0x1ffffU) << PRT_DINIT2_SHIFT | + DIV_ROUND_UP(ddr_freq_mhz * 1000, 1000) << PRT_DINIT3_SHIFT, + &publ->ptr[2]); + + switch (sdram_params->base.dramtype) { + case DDR3: + clrbits_le32(&publ->pgcr, 0x1f); + clrsetbits_le32(&publ->dcr, DDRMD_MASK << DDRMD_SHIFT, + DDRMD_DDR3 << DDRMD_SHIFT); + break; + } + if (sdram_params->base.odt) { + /*dynamic RTT enable */ + for (i = 0; i < 4; i++) + setbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); + } else { + /*dynamic RTT disable */ + for (i = 0; i < 4; i++) + clrbits_le32(&publ->datx8[i].dxgcr, DQSRTT | DQRTT); + } +} + +static void phy_init(struct rk3288_ddr_publ *publ) +{ + setbits_le32(&publ->pir, PIR_INIT | PIR_DLLSRST + | PIR_DLLLOCK | PIR_ZCAL | PIR_ITMSRST | PIR_CLRSR); + udelay(1); + while ((readl(&publ->pgsr) & + (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) != + (PGSR_IDONE | PGSR_DLDONE | PGSR_ZCDONE)) + ; +} + +static void send_command(struct rk3288_ddr_pctl *pctl, u32 rank, + u32 cmd, u32 arg) +{ + writel((START_CMD | (rank << 20) | arg | cmd), &pctl->mcmd); + udelay(1); + while (readl(&pctl->mcmd) & START_CMD) + ; +} + +static inline void send_command_op(struct rk3288_ddr_pctl *pctl, + u32 rank, u32 cmd, u32 ma, u32 op) +{ + send_command(pctl, rank, cmd, (ma & LPDDR2_MA_MASK) << LPDDR2_MA_SHIFT | + (op & LPDDR2_OP_MASK) << LPDDR2_OP_SHIFT); +} + +static void memory_init(struct rk3288_ddr_publ *publ, + u32 dramtype) +{ + setbits_le32(&publ->pir, + (PIR_INIT | PIR_DRAMINIT | PIR_LOCKBYP + | PIR_ZCALBYP | PIR_CLRSR | PIR_ICPC + | (dramtype == DDR3 ? PIR_DRAMRST : 0))); + udelay(1); + while ((readl(&publ->pgsr) & (PGSR_IDONE | PGSR_DLDONE)) + != (PGSR_IDONE | PGSR_DLDONE)) + ; +} + +static void move_to_config_state(struct rk3288_ddr_publ *publ, + struct rk3288_ddr_pctl *pctl) +{ + unsigned int state; + + while (1) { + state = readl(&pctl->stat) & PCTL_STAT_MSK; + + switch (state) { + case LOW_POWER: + writel(WAKEUP_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) + != ACCESS) + ; + /* wait DLL lock */ + while ((readl(&publ->pgsr) & PGSR_DLDONE) + != PGSR_DLDONE) + ; + /* if at low power state,need wakeup first, + * and then enter the config, so + * fallthrough + */ + case ACCESS: + /* fallthrough */ + case INIT_MEM: + writel(CFG_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) + ; + break; + case CONFIG: + return; + default: + break; + } + } +} + +static void set_bandwidth_ratio(const struct chan_info *chan, u32 channel, + u32 n, struct rk3188_grf *grf) +{ + struct rk3288_ddr_pctl *pctl = chan->pctl; + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3188_msch *msch = chan->msch; + + if (n == 1) { + setbits_le32(&pctl->ppcfg, 1); + ddr_set_enable(grf, channel, 1); + setbits_le32(&msch->ddrtiming, 1 << 31); + /* Data Byte disable*/ + clrbits_le32(&publ->datx8[2].dxgcr, 1); + clrbits_le32(&publ->datx8[3].dxgcr, 1); + /* disable DLL */ + setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); + setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); + } else { + clrbits_le32(&pctl->ppcfg, 1); + ddr_set_enable(grf, channel, 0); + clrbits_le32(&msch->ddrtiming, 1 << 31); + /* Data Byte enable*/ + setbits_le32(&publ->datx8[2].dxgcr, 1); + setbits_le32(&publ->datx8[3].dxgcr, 1); + + /* enable DLL */ + clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLDIS); + clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLDIS); + /* reset DLL */ + clrbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); + clrbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); + udelay(10); + setbits_le32(&publ->datx8[2].dxdllcr, DXDLLCR_DLLSRST); + setbits_le32(&publ->datx8[3].dxdllcr, DXDLLCR_DLLSRST); + } + setbits_le32(&pctl->dfistcfg0, 1 << 2); +} + +static int data_training(const struct chan_info *chan, u32 channel, + struct rk3188_sdram_params *sdram_params) +{ + unsigned int j; + int ret = 0; + u32 rank; + int i; + u32 step[2] = { PIR_QSTRN, PIR_RVTRN }; + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3288_ddr_pctl *pctl = chan->pctl; + + /* disable auto refresh */ + writel(0, &pctl->trefi); + + if (sdram_params->base.dramtype != LPDDR3) + setbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); + rank = sdram_params->ch[channel].rank | 1; + for (j = 0; j < ARRAY_SIZE(step); j++) { + /* + * trigger QSTRN and RVTRN + * clear DTDONE status + */ + setbits_le32(&publ->pir, PIR_CLRSR); + + /* trigger DTT */ + setbits_le32(&publ->pir, + PIR_INIT | step[j] | PIR_LOCKBYP | PIR_ZCALBYP | + PIR_CLRSR); + udelay(1); + /* wait echo byte DTDONE */ + while ((readl(&publ->datx8[0].dxgsr[0]) & rank) + != rank) + ; + while ((readl(&publ->datx8[1].dxgsr[0]) & rank) + != rank) + ; + if (!(readl(&pctl->ppcfg) & 1)) { + while ((readl(&publ->datx8[2].dxgsr[0]) + & rank) != rank) + ; + while ((readl(&publ->datx8[3].dxgsr[0]) + & rank) != rank) + ; + } + if (readl(&publ->pgsr) & + (PGSR_DTERR | PGSR_RVERR | PGSR_RVEIRR)) { + ret = -1; + break; + } + } + /* send some auto refresh to complement the lost while DTT */ + for (i = 0; i < (rank > 1 ? 8 : 4); i++) + send_command(pctl, rank, REF_CMD, 0); + + if (sdram_params->base.dramtype != LPDDR3) + clrbits_le32(&publ->pgcr, 1 << PGCR_DQSCFG_SHIFT); + + /* resume auto refresh */ + writel(sdram_params->pctl_timing.trefi, &pctl->trefi); + + return ret; +} + +static void move_to_access_state(const struct chan_info *chan) +{ + struct rk3288_ddr_publ *publ = chan->publ; + struct rk3288_ddr_pctl *pctl = chan->pctl; + unsigned int state; + + while (1) { + state = readl(&pctl->stat) & PCTL_STAT_MSK; + + switch (state) { + case LOW_POWER: + if (((readl(&pctl->stat) >> LP_TRIG_SHIFT) & + LP_TRIG_MASK) == 1) + return; + + writel(WAKEUP_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != ACCESS) + ; + /* wait DLL lock */ + while ((readl(&publ->pgsr) & PGSR_DLDONE) + != PGSR_DLDONE) + ; + break; + case INIT_MEM: + writel(CFG_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) != CONFIG) + ; + /* fallthrough */ + case CONFIG: + writel(GO_STATE, &pctl->sctl); + while ((readl(&pctl->stat) & PCTL_STAT_MSK) == CONFIG) + ; + break; + case ACCESS: + return; + default: + break; + } + } +} + +static void dram_cfg_rbc(const struct chan_info *chan, u32 chnum, + struct rk3188_sdram_params *sdram_params) +{ + struct rk3288_ddr_publ *publ = chan->publ; + + if (sdram_params->ch[chnum].bk == 3) + clrsetbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT, + 1 << PDQ_SHIFT); + else + clrbits_le32(&publ->dcr, PDQ_MASK << PDQ_SHIFT); + + writel(sdram_params->base.ddrconfig, &chan->msch->ddrconf); +} + +static void dram_all_config(const struct dram_info *dram, + struct rk3188_sdram_params *sdram_params) +{ + unsigned int chan; + u32 sys_reg = 0; + + sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT; + sys_reg |= (sdram_params->num_channels - 1) << SYS_REG_NUM_CH_SHIFT; + for (chan = 0; chan < sdram_params->num_channels; chan++) { + const struct rk3288_sdram_channel *info = + &sdram_params->ch[chan]; + + sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(chan); + sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(chan); + sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(chan); + sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(chan); + sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(chan); + sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(chan); + sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(chan); + sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(chan); + sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(chan); + + dram_cfg_rbc(&dram->chan[chan], chan, sdram_params); + } + if (sdram_params->ch[0].rank == 2) + ddr_rank_2_row15en(dram->grf, 0); + else + ddr_rank_2_row15en(dram->grf, 1); + writel(sys_reg, &dram->pmu->sys_reg[2]); +} +const int ddrconf_table[] = { + /* + * [5:4] row(13+n) + * [1:0] col(9+n), assume bw=2 + * row col,bw */ + 0, + ((2 << 4) | 1), + ((1 << 4) | 1), + ((0 << 4) | 1), + ((2 << 4) | 2), + ((1 << 4) | 2), + ((0 << 4) | 2), + ((1 << 4) | 0), + ((0 << 4) | 0), + 0, + 0, + 0, + 0, + 0, + 0, + 0, +}; + +static int sdram_rank_bw_detect(struct dram_info *dram, int channel, + struct rk3188_sdram_params *sdram_params) +{ + int reg; + int need_trainig = 0; + const struct chan_info *chan = &dram->chan[channel]; + struct rk3288_ddr_publ *publ = chan->publ; + + ddr_rank_2_row15en(dram->grf, 0); + + if (-1 == data_training(chan, channel, sdram_params)) { + printf("first data training fail!\n"); + reg = readl(&publ->datx8[0].dxgsr[0]); + /* Check the result for rank 0 */ + if ((channel == 0) && (reg & DQS_GATE_TRAINING_ERROR_RANK0)) { + printf("data training fail!\n"); + return -EIO; + } + + /* Check the result for rank 1 */ + if (reg & DQS_GATE_TRAINING_ERROR_RANK1) { + sdram_params->ch[channel].rank = 1; + clrsetbits_le32(&publ->pgcr, 0xF << 18, + sdram_params->ch[channel].rank << 18); + need_trainig = 1; + } + reg = readl(&publ->datx8[2].dxgsr[0]); + if (reg & (1 << 4)) { + sdram_params->ch[channel].bw = 1; + set_bandwidth_ratio(chan, channel, + sdram_params->ch[channel].bw, + dram->grf); + need_trainig = 1; + } + } + /* Assume the Die bit width are the same with the chip bit width */ + sdram_params->ch[channel].dbw = sdram_params->ch[channel].bw; + + if (need_trainig && + (-1 == data_training(chan, channel, sdram_params))) { + if (sdram_params->base.dramtype == LPDDR3) { + ddr_phy_ctl_reset(dram->cru, channel, 1); + udelay(10); + ddr_phy_ctl_reset(dram->cru, channel, 0); + udelay(10); + } + printf("2nd data training failed!"); + return -EIO; + } + + return 0; +} + +static int sdram_col_row_detect(struct dram_info *dram, int channel, + struct rk3188_sdram_params *sdram_params) +{ + int row, col; + unsigned int addr; + const struct chan_info *chan = &dram->chan[channel]; + struct rk3288_ddr_pctl *pctl = chan->pctl; + struct rk3288_ddr_publ *publ = chan->publ; + int ret = 0; + + /* Detect col */ + for (col = 11; col >= 9; col--) { + writel(0, CONFIG_SYS_SDRAM_BASE); + addr = CONFIG_SYS_SDRAM_BASE + + (1 << (col + sdram_params->ch[channel].bw - 1)); + writel(TEST_PATTEN, addr); + if ((readl(addr) == TEST_PATTEN) && + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + break; + } + if (col == 8) { + printf("Col detect error\n"); + ret = -EINVAL; + goto out; + } else { + sdram_params->ch[channel].col = col; + } + + ddr_rank_2_row15en(dram->grf, 1); + move_to_config_state(publ, pctl); + writel(1, &chan->msch->ddrconf); + move_to_access_state(chan); + /* Detect row, max 15,min13 in rk3188*/ + for (row = 16; row >= 13; row--) { + writel(0, CONFIG_SYS_SDRAM_BASE); + addr = CONFIG_SYS_SDRAM_BASE + (1 << (row + 15 - 1)); + writel(TEST_PATTEN, addr); + if ((readl(addr) == TEST_PATTEN) && + (readl(CONFIG_SYS_SDRAM_BASE) == 0)) + break; + } + if (row == 12) { + printf("Row detect error\n"); + ret = -EINVAL; + } else { + sdram_params->ch[channel].cs1_row = row; + sdram_params->ch[channel].row_3_4 = 0; + printf("chn %d col %d, row %d\n", channel, col, row); + sdram_params->ch[channel].cs0_row = row; + } + +out: + return ret; +} + +static int sdram_get_niu_config(struct rk3188_sdram_params *sdram_params) +{ + int i, tmp, size, ret = 0; + + tmp = sdram_params->ch[0].col - 9; + tmp -= (sdram_params->ch[0].bw == 2) ? 0 : 1; + tmp |= ((sdram_params->ch[0].cs0_row - 13) << 4); + size = sizeof(ddrconf_table)/sizeof(ddrconf_table[0]); + for (i = 0; i < size; i++) + if (tmp == ddrconf_table[i]) + break; + if (i >= size) { + printf("niu config not found\n"); + ret = -EINVAL; + } else { + printf("niu config %d\n", i); + sdram_params->base.ddrconfig = i; + } + + return ret; +} + +static int sdram_init(struct dram_info *dram, + struct rk3188_sdram_params *sdram_params) +{ + int channel; + int zqcr; + int ret; + + printf("%s start 001\n", __func__); + if ((sdram_params->base.dramtype == DDR3 && + sdram_params->base.ddr_freq > 800000000)) { + printf("SDRAM frequency is too high!"); + return -E2BIG; + } + + ret = clk_set_rate(&dram->ddr_clk, sdram_params->base.ddr_freq); + printf("ret=%d\n", ret); + if (ret) { + printf("Could not set DDR clock\n"); + return ret; + } + + for (channel = 0; channel < 1; channel++) { + const struct chan_info *chan = &dram->chan[channel]; + struct rk3288_ddr_pctl *pctl = chan->pctl; + struct rk3288_ddr_publ *publ = chan->publ; + + phy_pctrl_reset(dram->cru, publ, channel); + phy_dll_bypass_set(publ, sdram_params->base.ddr_freq); + + dfi_cfg(pctl, sdram_params->base.dramtype); + + pctl_cfg(channel, pctl, sdram_params, dram->grf); + + phy_cfg(chan, channel, sdram_params); + + phy_init(publ); + + writel(POWER_UP_START, &pctl->powctl); + while (!(readl(&pctl->powstat) & POWER_UP_DONE)) + ; + + memory_init(publ, sdram_params->base.dramtype); + move_to_config_state(publ, pctl); + + /* Using 32bit bus width for detect */ + sdram_params->ch[channel].bw = 2; + set_bandwidth_ratio(chan, channel, + sdram_params->ch[channel].bw, dram->grf); + /* + * set cs, using n=3 for detect + * CS0, n=1 + * CS1, n=2 + * CS0 & CS1, n = 3 + */ + sdram_params->ch[channel].rank = 2, + clrsetbits_le32(&publ->pgcr, 0xF << 18, + (sdram_params->ch[channel].rank | 1) << 18); + + /* DS=40ohm,ODT=155ohm */ + zqcr = 1 << ZDEN_SHIFT | 2 << PU_ONDIE_SHIFT | + 2 << PD_ONDIE_SHIFT | 0x19 << PU_OUTPUT_SHIFT | + 0x19 << PD_OUTPUT_SHIFT; + writel(zqcr, &publ->zq1cr[0]); + writel(zqcr, &publ->zq0cr[0]); + + /* Detect the rank and bit-width with data-training */ + writel(1, &chan->msch->ddrconf); + sdram_rank_bw_detect(dram, channel, sdram_params); + + if (sdram_params->base.dramtype == LPDDR3) { + u32 i; + writel(0, &pctl->mrrcfg0); + for (i = 0; i < 17; i++) + send_command_op(pctl, 1, MRR_CMD, i, 0); + } + writel(4, &chan->msch->ddrconf); + move_to_access_state(chan); + /* DDR3 and LPDDR3 are always 8 bank, no need detect */ + sdram_params->ch[channel].bk = 3; + /* Detect Col and Row number*/ + ret = sdram_col_row_detect(dram, channel, sdram_params); + if (ret) + goto error; + } + /* Find NIU DDR configuration */ + ret = sdram_get_niu_config(sdram_params); + if (ret) + goto error; + + dram_all_config(dram, sdram_params); + printf("%s done\n", __func__); + + return 0; +error: + printf("DRAM init failed!\n"); + hang(); +} +#endif /* CONFIG_SPL_BUILD */ + +size_t sdram_size_mb(struct rk3188_pmu *pmu) +{ + u32 rank, col, bk, cs0_row, cs1_row, bw, row_3_4; + size_t chipsize_mb = 0; + size_t size_mb = 0; + u32 ch; + u32 sys_reg = readl(&pmu->sys_reg[2]); + u32 chans; + + chans = 1 + ((sys_reg >> SYS_REG_NUM_CH_SHIFT) & SYS_REG_NUM_CH_MASK); + + for (ch = 0; ch < chans; ch++) { + rank = 1 + (sys_reg >> SYS_REG_RANK_SHIFT(ch) & + SYS_REG_RANK_MASK); + col = 9 + (sys_reg >> SYS_REG_COL_SHIFT(ch) & SYS_REG_COL_MASK); + bk = 3 - ((sys_reg >> SYS_REG_BK_SHIFT(ch)) & SYS_REG_BK_MASK); + cs0_row = 13 + (sys_reg >> SYS_REG_CS0_ROW_SHIFT(ch) & + SYS_REG_CS0_ROW_MASK); + cs1_row = 13 + (sys_reg >> SYS_REG_CS1_ROW_SHIFT(ch) & + SYS_REG_CS1_ROW_MASK); + bw = (2 >> ((sys_reg >> SYS_REG_BW_SHIFT(ch)) & + SYS_REG_BW_MASK)); + row_3_4 = sys_reg >> SYS_REG_ROW_3_4_SHIFT(ch) & + SYS_REG_ROW_3_4_MASK; + chipsize_mb = (1 << (cs0_row + col + bk + bw - 20)); + + if (rank > 1) + chipsize_mb += chipsize_mb >> + (cs0_row - cs1_row); + if (row_3_4) + chipsize_mb = chipsize_mb * 3 / 4; + size_mb += chipsize_mb; + } + + /* there can be no more than 2gb of memory */ + size_mb = min(size_mb, 0x80000000 >> 20); + + return size_mb; +} + +#ifdef CONFIG_SPL_BUILD +static int setup_sdram(struct udevice *dev) +{ + struct dram_info *priv = dev_get_priv(dev); + struct rk3188_sdram_params *params = dev_get_platdata(dev); + + return sdram_init(priv, params); +} + +static int rk3188_dmc_ofdata_to_platdata(struct udevice *dev) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + struct rk3188_sdram_params *params = dev_get_platdata(dev); + const void *blob = gd->fdt_blob; + int node = dev->of_offset; + int ret; + + /* rk3188 supports only one-channel */ + params->num_channels = 1; + ret = fdtdec_get_int_array(blob, node, "rockchip,pctl-timing", + (u32 *)&params->pctl_timing, + sizeof(params->pctl_timing) / sizeof(u32)); + if (ret) { + printf("%s: Cannot read rockchip,pctl-timing\n", __func__); + return -EINVAL; + } + ret = fdtdec_get_int_array(blob, node, "rockchip,phy-timing", + (u32 *)&params->phy_timing, + sizeof(params->phy_timing) / sizeof(u32)); + if (ret) { + printf("%s: Cannot read rockchip,phy-timing\n", __func__); + return -EINVAL; + } + ret = fdtdec_get_int_array(blob, node, "rockchip,sdram-params", + (u32 *)&params->base, + sizeof(params->base) / sizeof(u32)); + if (ret) { + printf("%s: Cannot read rockchip,sdram-params\n", __func__); + return -EINVAL; + } + ret = regmap_init_mem(dev, &params->map); + if (ret) + return ret; +#endif + + return 0; +} +#endif /* CONFIG_SPL_BUILD */ + +#if CONFIG_IS_ENABLED(OF_PLATDATA) +static int conv_of_platdata(struct udevice *dev) +{ + struct rk3188_sdram_params *plat = dev_get_platdata(dev); + struct dtd_rockchip_rk3188_dmc *of_plat = &plat->of_plat; + int ret; + + memcpy(&plat->pctl_timing, of_plat->rockchip_pctl_timing, + sizeof(plat->pctl_timing)); + memcpy(&plat->phy_timing, of_plat->rockchip_phy_timing, + sizeof(plat->phy_timing)); + memcpy(&plat->base, of_plat->rockchip_sdram_params, sizeof(plat->base)); + /* rk3188 supports dual-channel, set default channel num to 2 */ + plat->num_channels = 1; + ret = regmap_init_mem_platdata(dev, of_plat->reg, + ARRAY_SIZE(of_plat->reg) / 2, + &plat->map); + if (ret) + return ret; + + return 0; +} +#endif + +static int rk3188_dmc_probe(struct udevice *dev) +{ +#ifdef CONFIG_SPL_BUILD + struct rk3188_sdram_params *plat = dev_get_platdata(dev); +#endif + struct dram_info *priv = dev_get_priv(dev); + struct regmap *map; + int ret; + struct udevice *dev_clk; + +#if CONFIG_IS_ENABLED(OF_PLATDATA) + ret = conv_of_platdata(dev); + if (ret) + return ret; +#endif + map = syscon_get_regmap_by_driver_data(ROCKCHIP_SYSCON_NOC); + if (IS_ERR(map)) + return PTR_ERR(map); + priv->chan[0].msch = regmap_get_range(map, 0); + + priv->grf = syscon_get_first_range(ROCKCHIP_SYSCON_GRF); + priv->pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); + +#ifdef CONFIG_SPL_BUILD + priv->chan[0].pctl = regmap_get_range(plat->map, 0); + priv->chan[0].publ = regmap_get_range(plat->map, 1); +#endif + + ret = rockchip_get_clk(&dev_clk); + if (ret) + return ret; + priv->ddr_clk.id = CLK_DDR; + ret = clk_request(dev_clk, &priv->ddr_clk); + if (ret) + return ret; + + priv->cru = rockchip_get_cru(); + if (IS_ERR(priv->cru)) + return PTR_ERR(priv->cru); +#ifdef CONFIG_SPL_BUILD + ret = setup_sdram(dev); + if (ret) + return ret; +#endif + priv->info.base = 0; + priv->info.size = sdram_size_mb(priv->pmu) << 20; + + return 0; +} + +static int rk3188_dmc_get_info(struct udevice *dev, struct ram_info *info) +{ + struct dram_info *priv = dev_get_priv(dev); + + *info = priv->info; + + return 0; +} + +static struct ram_ops rk3188_dmc_ops = { + .get_info = rk3188_dmc_get_info, +}; + +static const struct udevice_id rk3188_dmc_ids[] = { + { .compatible = "rockchip,rk3188-dmc" }, + { } +}; + +U_BOOT_DRIVER(dmc_rk3188) = { + .name = "rockchip_rk3188_dmc", + .id = UCLASS_RAM, + .of_match = rk3188_dmc_ids, + .ops = &rk3188_dmc_ops, +#ifdef CONFIG_SPL_BUILD + .ofdata_to_platdata = rk3188_dmc_ofdata_to_platdata, +#endif + .probe = rk3188_dmc_probe, + .priv_auto_alloc_size = sizeof(struct dram_info), +#ifdef CONFIG_SPL_BUILD + .platdata_auto_alloc_size = sizeof(struct rk3188_sdram_params), +#endif +};

The rk3188 needs 3 uboot stages: a tpl living in 1KB of sram, a spl the resides in the rest of the sram and loads the regular uboot living in regular ram.

Signed-off-by: Heiko Stuebner heiko@sntech.de --- arch/arm/mach-rockchip/Makefile | 7 +- arch/arm/mach-rockchip/rk3188-board-spl.c | 220 ++++++++++++++++++++++++++++++ arch/arm/mach-rockchip/rk3188-board-tpl.c | 87 ++++++++++++ arch/arm/mach-rockchip/rk3188-board.c | 71 ++++++++++ 4 files changed, 384 insertions(+), 1 deletion(-) create mode 100644 arch/arm/mach-rockchip/rk3188-board-spl.c create mode 100644 arch/arm/mach-rockchip/rk3188-board-tpl.c create mode 100644 arch/arm/mach-rockchip/rk3188-board.c

diff --git a/arch/arm/mach-rockchip/Makefile b/arch/arm/mach-rockchip/Makefile index 2be7e14e3e..7b8abc2266 100644 --- a/arch/arm/mach-rockchip/Makefile +++ b/arch/arm/mach-rockchip/Makefile @@ -4,11 +4,16 @@ # SPDX-License-Identifier: GPL-2.0+ #

-ifdef CONFIG_SPL_BUILD +ifdef CONFIG_TPL_BUILD +obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-tpl.o +obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o +else ifdef CONFIG_SPL_BUILD obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board-spl.o +obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board-spl.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board-spl.o obj-$(CONFIG_ROCKCHIP_BROM_HELPER) += save_boot_param.o else +obj-$(CONFIG_ROCKCHIP_RK3188) += rk3188-board.o obj-$(CONFIG_ROCKCHIP_RK3288) += rk3288-board.o obj-$(CONFIG_ROCKCHIP_RK3036) += rk3036-board.o endif diff --git a/arch/arm/mach-rockchip/rk3188-board-spl.c b/arch/arm/mach-rockchip/rk3188-board-spl.c new file mode 100644 index 0000000000..b528a2f73d --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188-board-spl.c @@ -0,0 +1,220 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <dm.h> +#include <fdtdec.h> +#include <led.h> +#include <malloc.h> +#include <ram.h> +#include <spl.h> +#include <asm/gpio.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/hardware.h> +#include <asm/arch/periph.h> +#include <asm/arch/pmu_rk3188.h> +#include <asm/arch/sdram.h> +#include <asm/arch/timer.h> +#include <dm/pinctrl.h> +#include <dm/root.h> +#include <dm/test.h> +#include <dm/util.h> +#include <power/regulator.h> +#include <syscon.h> + +DECLARE_GLOBAL_DATA_PTR; + +u32 spl_boot_device(void) +{ +#if !CONFIG_IS_ENABLED(OF_PLATDATA) + const void *blob = gd->fdt_blob; + struct udevice *dev; + const char *bootdev; + int node; + int ret; + + bootdev = fdtdec_get_config_string(blob, "u-boot,boot0"); + debug("Boot device %s\n", bootdev); + if (!bootdev) + goto fallback; + + node = fdt_path_offset(blob, bootdev); + if (node < 0) { + debug("node=%d\n", node); + goto fallback; + } + ret = device_get_global_by_of_offset(node, &dev); + if (ret) { + debug("device at node %s/%d not found: %d\n", bootdev, node, + ret); + goto fallback; + } + debug("Found device %s\n", dev->name); + switch (device_get_uclass_id(dev)) { + case UCLASS_SPI_FLASH: + return BOOT_DEVICE_SPI; + case UCLASS_MMC: + return BOOT_DEVICE_MMC1; + default: + debug("Booting from device uclass '%s' not supported\n", + dev_get_uclass_name(dev)); + } + +fallback: +#endif + return BOOT_DEVICE_MMC1; +} + +u32 spl_boot_mode(const u32 boot_device) +{ + return MMCSD_MODE_RAW; +} + +extern u32 SAVE_SP_ADDR; +extern void back_to_bootrom(void); +void board_init_f(ulong dummy) +{ + struct udevice *pinctrl, *dev; + struct rk3188_pmu *pmu; + int ret; + +#define EARLY_UART + /* Example code showing how to enable the debug UART on RK3188 */ +#ifdef EARLY_UART +#include <asm/arch/grf_rk3188.h> + /* Enable early UART on the RK3188 */ +#define GRF_BASE 0x20008000 + struct rk3188_grf * const grf = (void *)GRF_BASE; + + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK << GPIO1B1_SHIFT | + GPIO1B0_MASK << GPIO1B0_SHIFT, + GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | + GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + debug_uart_init(); + printch('s'); + printch('p'); + printch('l'); + printch('\n'); +#endif + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + rockchip_timer_init(); + + ret = rockchip_get_clk(&dev); + if (ret) { + debug("CLK init failed: %d\n", ret); + return; + } + + /* + * Recover the bootrom's stackpointer. + * For whatever reason needs to run after rockchip_get_clk. + */ + pmu = syscon_get_first_range(ROCKCHIP_SYSCON_PMU); + if (IS_ERR(pmu)) + error("pmu syscon returned %ld\n", PTR_ERR(pmu)); + SAVE_SP_ADDR = readl(&pmu->sys_reg[2]); + + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("Pinctrl init failed: %d\n", ret); + return; + } + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) { + debug("DRAM init failed: %d\n", ret); + return; + } + +#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) && !defined(CONFIG_SPL_BOARD_INIT) + back_to_bootrom(); +#endif +} + +static int setup_led(void) +{ +#ifdef CONFIG_SPL_LED + struct udevice *dev; + char *led_name; + int ret; + + led_name = fdtdec_get_config_string(gd->fdt_blob, "u-boot,boot-led"); + if (!led_name) + return 0; + ret = led_get_by_label(led_name, &dev); + if (ret) { + debug("%s: get=%d\n", __func__, ret); + return ret; + } + ret = led_set_on(dev, 1); + if (ret) + return ret; +#endif + + return 0; +} + +void spl_board_init(void) +{ + struct udevice *pinctrl; + int ret; + + ret = setup_led(); + if (ret) { + debug("LED ret=%d\n", ret); + hang(); + } + + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + goto err; + } + +#ifdef CONFIG_SPL_MMC_SUPPORT + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); + if (ret) { + debug("%s: Failed to set up SD card\n", __func__); + goto err; + } +#endif + + /* Enable debug UART */ + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_UART_DBG); + if (ret) { + debug("%s: Failed to set up console UART\n", __func__); + goto err; + } + + preloader_console_init(); +#ifdef CONFIG_ROCKCHIP_SPL_BACK_TO_BROM + back_to_bootrom(); +#endif + return; + +err: + printf("spl_board_init: Error %d\n", ret); + + /* No way to report error here */ + hang(); +} diff --git a/arch/arm/mach-rockchip/rk3188-board-tpl.c b/arch/arm/mach-rockchip/rk3188-board-tpl.c new file mode 100644 index 0000000000..62cdb8976a --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188-board-tpl.c @@ -0,0 +1,87 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <debug_uart.h> +#include <spl.h> +#include <asm/io.h> +#include <asm/arch/pmu_rk3188.h> + +DECLARE_GLOBAL_DATA_PTR; + +/* track how often we were entered */ +static int rk3188_num_entries; +extern void back_to_bootrom(void); + +#define PMU_BASE 0x20004000 +#define TPL_ENTRY 0x10080C00 +extern u32 SAVE_SP_ADDR; +static void jump_to_tpl(void) +{ + typedef void __noreturn (*image_entry_noargs_t)(void); + + struct rk3188_pmu * const pmu = (void *)PMU_BASE; + image_entry_noargs_t tpl_entry = + (image_entry_noargs_t)(unsigned long)TPL_ENTRY; + + /* Store the SAVE_SP_ADDR in a location shared with TPL. */ + writel(SAVE_SP_ADDR, &pmu->sys_reg[2]); + tpl_entry(); +} + +void board_init_f(ulong dummy) +{ +#define EARLY_UART + /* Example code showing how to enable the debug UART on RK3188 */ +#ifdef EARLY_UART +#include <asm/arch/grf_rk3188.h> + /* Enable early UART on the RK3188 */ +#define GRF_BASE 0x20008000 + struct rk3188_grf * const grf = (void *)GRF_BASE; + + rk_clrsetreg(&grf->gpio1b_iomux, + GPIO1B1_MASK << GPIO1B1_SHIFT | + GPIO1B0_MASK << GPIO1B0_SHIFT, + GPIO1B1_UART2_SOUT << GPIO1B1_SHIFT | + GPIO1B0_UART2_SIN << GPIO1B0_SHIFT); + /* + * Debug UART can be used from here if required: + * + * debug_uart_init(); + * printch('a'); + * printhex8(0x1234); + * printascii("string"); + */ + debug_uart_init(); + + printch('t'); + printch('p'); + printch('l'); + printch('-'); + printch(rk3188_num_entries + 1 + '0'); + printch('\n'); +#endif + + rk3188_num_entries++; + + if (rk3188_num_entries == 1) { + /* + * The original loader did some very basic integrity + * checking at this point, but the remaining few bytes + * could be used for any improvement making sense + * really early on. + */ + + back_to_bootrom(); + } else { + /* + * TPL part of the loader should now wait for us + * at offset 0xC00 in the sram. Should never return + * from there. + */ + jump_to_tpl(); + } +} diff --git a/arch/arm/mach-rockchip/rk3188-board.c b/arch/arm/mach-rockchip/rk3188-board.c new file mode 100644 index 0000000000..16f38559af --- /dev/null +++ b/arch/arm/mach-rockchip/rk3188-board.c @@ -0,0 +1,71 @@ +/* + * (C) Copyright 2015 Google, Inc + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <clk.h> +#include <dm.h> +#include <ram.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/clock.h> +#include <asm/arch/periph.h> +#include <asm/arch/pmu_rk3288.h> +#include <asm/arch/boot_mode.h> +#include <asm/gpio.h> +#include <dm/pinctrl.h> + +DECLARE_GLOBAL_DATA_PTR; + +int board_init(void) +{ +#if defined(CONFIG_ROCKCHIP_SPL_BACK_TO_BROM) + struct udevice *pinctrl; + int ret; + + /* + * We need to implement sdcard iomux here for the further + * initialization, otherwise, it'll hit sdcard command sending + * timeout exception. + */ + ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); + if (ret) { + debug("%s: Cannot find pinctrl device\n", __func__); + goto err; + } + ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_SDCARD); + if (ret) { + debug("%s: Failed to set up SD card\n", __func__); + goto err; + } + + return 0; +err: + printf("board_init: Error %d\n", ret); + + /* No way to report error here */ + hang(); + + return -1; +#else + return 0; +#endif +} + +int dram_init(void) +{ + /* FIXME: read back ram size from sys_reg2 */ + gd->ram_size = 0x40000000; + + return 0; +} + +#ifndef CONFIG_SYS_DCACHE_OFF +void enable_caches(void) +{ + /* Enable D-cache. I-cache is already enabled in start.S */ + dcache_enable(); +} +#endif