[U-Boot] [PATCH 1/5] ARM64: poplar: add device tree bindings
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org --- arch/arm/dts/hi3798cv200-poplar.dts | 169 +++++++++++++ arch/arm/dts/hi3798cv200.dtsi | 413 ++++++++++++++++++++++++++++++++ include/dt-bindings/clock/histb-clock.h | 66 +++++ include/dt-bindings/reset/ti-syscon.h | 38 +++ 4 files changed, 686 insertions(+) create mode 100644 arch/arm/dts/hi3798cv200-poplar.dts create mode 100644 arch/arm/dts/hi3798cv200.dtsi create mode 100644 include/dt-bindings/clock/histb-clock.h create mode 100644 include/dt-bindings/reset/ti-syscon.h
diff --git a/arch/arm/dts/hi3798cv200-poplar.dts b/arch/arm/dts/hi3798cv200-poplar.dts new file mode 100644 index 0000000..4e2b1d1 --- /dev/null +++ b/arch/arm/dts/hi3798cv200-poplar.dts @@ -0,0 +1,169 @@ +/* + * DTS File for HiSilicon Poplar Development Board + * + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +/dts-v1/; + +#include <dt-bindings/gpio/gpio.h> +#include "hi3798cv200.dtsi" + +/ { + model = "HiSilicon Poplar Development Board"; + compatible = "hisilicon,hi3798cv200-poplar", "hisilicon,hi3798cv200"; + + aliases { + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory { + device_type = "memory"; + reg = <0x000000000 0x00000000 0x00000000 0x80000000>; + }; + + soc { + leds { + compatible = "gpio-leds"; + + user-led0 { + label = "USER-LED0"; + gpios = <&gpio6 3 GPIO_ACTIVE_LOW>; + linux,default-trigger = "heartbeat"; + default-state = "off"; + }; + + user-led1 { + label = "USER-LED1"; + gpios = <&gpio5 1 GPIO_ACTIVE_LOW>; + linux,default-trigger = "mmc0"; + default-state = "off"; + }; + + user-led2 { + label = "USER-LED2"; + gpios = <&gpio5 2 GPIO_ACTIVE_LOW>; + linux,default-trigger = "none"; + default-state = "off"; + }; + + user-led3 { + label = "USER-LED3"; + gpios = <&gpio10 6 GPIO_ACTIVE_LOW>; + linux,default-trigger = "cpu0"; + default-state = "off"; + }; + }; + }; +}; + +&uart0 { + status = "ok"; +}; + +&uart2 { + status = "ok"; + label = "LS-UART0"; +}; +/* No optional LS-UART1 on Low Speed Expansion Connector. */ + +&i2c0 { + status = "ok"; + label = "LS-I2C0"; +}; + +&i2c2 { + status = "ok"; + label = "LS-I2C1"; +}; + +&spi0 { + status = "ok"; + label = "LS-SPI0"; +}; + +&gpio1 { + status = "ok"; + gpio-line-names = "LS-GPIO-E", "", + "", "", + "", "LS-GPIO-F", + "", "LS-GPIO-J"; +}; + +&gpio2 { + status = "ok"; + gpio-line-names = "LS-GPIO-H", "LS-GPIO-I", + "LS-GPIO-L", "LS-GPIO-G", + "LS-GPIO-K", "", + "", ""; +}; + +&gpio3 { + status = "ok"; + gpio-line-names = "", "", + "", "", + "LS-GPIO-C", "", + "", "LS-GPIO-B"; +}; + +&gpio4 { + status = "ok"; + gpio-line-names = "", "", + "", "", + "", "LS-GPIO-D", + "", ""; +}; + +&gpio5 { + status = "ok"; + gpio-line-names = "", "USER-LED-1", + "USER-LED-2", "", + "", "LS-GPIO-A", + "", ""; +}; + +&gpio6 { + status = "ok"; + gpio-line-names = "", "", + "", "USER-LED-0", + "", "", + "", ""; +}; + +&gpio10 { + status = "ok"; + gpio-line-names = "", "", + "", "", + "", "", + "USER-LED-3", ""; +}; + +&gmac0 { + #address-cells = <1>; + #size-cells = <0>; + phy-handle = <ð_phy1>; + phy-mode = "rgmii"; + hisilicon,phy-reset-delays-us = <10000 10000 30000>; + status = "ok"; + + eth_phy1: phy@3{ + reg = <3>; + }; +}; diff --git a/arch/arm/dts/hi3798cv200.dtsi b/arch/arm/dts/hi3798cv200.dtsi new file mode 100644 index 0000000..4757eb1 --- /dev/null +++ b/arch/arm/dts/hi3798cv200.dtsi @@ -0,0 +1,413 @@ +/* + * DTS File for HiSilicon Hi3798cv200 SOC. + * + * Copyright (c) 2016-2017 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/clock/histb-clock.h> +#include <dt-bindings/reset/ti-syscon.h> + +/ { + compatible = "hisilicon,hi3798cv200"; + interrupt-parent = <&gic>; + #address-cells = <2>; + #size-cells = <2>; + + psci { + compatible = "arm,psci-0.2"; + method = "smc"; + }; + + cpus { + #address-cells = <2>; + #size-cells = <0>; + + cpu@0 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x0>; + enable-method = "psci"; + }; + + cpu@1 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x1>; + enable-method = "psci"; + }; + + cpu@2 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x2>; + enable-method = "psci"; + }; + + cpu@3 { + compatible = "arm,cortex-a53"; + device_type = "cpu"; + reg = <0x0 0x3>; + enable-method = "psci"; + }; + }; + + gic: interrupt-controller@f1001000 { + compatible = "arm,gic-400"; + reg = <0x0 0xf1001000 0x0 0x1000>, /*GICD*/ + <0x0 0xf1002000 0x0 0x100>; /*GICC*/ + #address-cells = <0>; + #interrupt-cells = <3>; + interrupt-controller; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + }; + + soc { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0x0 0x00000000 0x0 0xffffffff>; + + crg: clock-reset-controller@f8a22000 { + compatible = "hisilicon,hi3798cv200-crg", "simple-mfd"; + reg = <0xf8a22000 0x1000>; + #clock-cells = <1>; + #reset-cells = <2>; + + gmacphyrst: reset-controller { + compatible = "ti,syscon-reset"; + reset-cells = <1>; + ti,reset-bits = < + 0xcc 12 0xcc 12 0 0 (ASSERT_CLEAR|DEASSERT_SET|STATUS_NONE) /* 0: gmac0-phy-rst */ + 0xcc 13 0xcc 13 0 0 (ASSERT_CLEAR|DEASSERT_SET|STATUS_NONE) /* 1: gmac1-phy-rst */ + >; + }; + }; + + sysctrl: system-controller@f8000000 { + compatible = "hisilicon,hi3798cv200-sysctrl", "syscon"; + reg = <0xf8000000 0x1000>; + #clock-cells = <1>; + #reset-cells = <2>; + }; + + uart0: serial@f8b00000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xf8b00000 0x1000>; + interrupts = <GIC_SPI 49 IRQ_TYPE_LEVEL_HIGH>; + clock = <75000000>; + clocks = <&sysctrl HISTB_UART0_CLK>; + clock-names = "uartclk", "apb_pclk"; + }; + + uart2: serial@f8b02000 { + compatible = "arm,pl011", "arm,primecell"; + reg = <0xf8b02000 0x1000>; + interrupts = <GIC_SPI 51 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_UART2_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + i2c0: i2c@f8b10000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xf8b10000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 38 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C0_CLK>; + status = "disabled"; + }; + + i2c1: i2c@f8b11000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xf8b11000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 39 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C1_CLK>; + status = "disabled"; + }; + + i2c2: i2c@f8b12000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xf8b12000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 40 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C2_CLK>; + status = "disabled"; + }; + + i2c3: i2c@f8b13000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xf8b13000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C3_CLK>; + status = "disabled"; + }; + + i2c4: i2c@f8b14000 { + compatible = "hisilicon,hix5hd2-i2c"; + reg = <0xf8b14000 0x1000>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 42 IRQ_TYPE_LEVEL_HIGH>; + clock-frequency = <400000>; + clocks = <&crg HISTB_I2C4_CLK>; + status = "disabled"; + }; + + spi0: spi@f8b1a000 { + compatible = "arm,pl022", "arm,primecell"; + reg = <0xf8b1a000 0x1000>; + interrupts = <GIC_SPI 45 IRQ_TYPE_LEVEL_HIGH>; + num-cs = <1>; + cs-gpios = <&gpio7 1 0>; + clocks = <&crg HISTB_SPI0_CLK>; + clock-names = "apb_pclk"; + #address-cells = <1>; + #size-cells = <0>; + status = "disabled"; + }; + + emmc: mmc@f9830000 { + compatible = "snps,dw-mshc"; + reg = <0xf9830000 0x10000>; + interrupts = <GIC_SPI 35 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_MMC_CIU_CLK>, + <&crg HISTB_MMC_BIU_CLK>; + clock-names = "ciu", "biu"; + }; + + gpio0: gpio@f8b20000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b20000 0x1000>; + interrupts = <GIC_SPI 108 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio1: gpio@f8b21000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b21000 0x1000>; + interrupts = <GIC_SPI 109 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio2: gpio@f8b22000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b22000 0x1000>; + interrupts = <GIC_SPI 110 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio3: gpio@f8b23000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b23000 0x1000>; + interrupts = <GIC_SPI 111 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio4: gpio@f8b24000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b24000 0x1000>; + interrupts = <GIC_SPI 112 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio5: gpio@f8004000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8004000 0x1000>; + interrupts = <GIC_SPI 113 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio6: gpio@f8b26000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b26000 0x1000>; + interrupts = <GIC_SPI 114 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio7: gpio@f8b27000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b27000 0x1000>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio8: gpio@f8b28000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b28000 0x1000>; + interrupts = <GIC_SPI 116 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio9: gpio@f8b29000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b29000 0x1000>; + interrupts = <GIC_SPI 117 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio10: gpio@f8b2a000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b2a000 0x1000>; + interrupts = <GIC_SPI 118 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio11: gpio@f8b2b000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b2b000 0x1000>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gpio12: gpio@f8b2c000 { + compatible = "arm,pl061", "arm,primecell"; + reg = <0xf8b2c000 0x1000>; + interrupts = <GIC_SPI 120 IRQ_TYPE_LEVEL_HIGH>; + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + clocks = <&crg HISTB_APB_CLK>; + clock-names = "apb_pclk"; + status = "disabled"; + }; + + gmac0: ethernet@f9840000 { + compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; + reg = <0xf9840000 0x1000>, + <0xf984300c 0x4>; + interrupts = <GIC_SPI 71 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_ETH0_MAC_CLK>, + <&crg HISTB_ETH0_MACIF_CLK>; + clock-names = "mac_core", "mac_ifc"; + resets = <&crg 0xcc 8>, + <&crg 0xcc 10>, + <&gmacphyrst 0>; + reset-names = "mac_core", "mac_ifc", "phy"; + }; + + gmac1: ethernet@f9841000 { + compatible = "hisilicon,hi3798cv200-gmac", "hisilicon,hisi-gmac-v2"; + reg = <0xf9841000 0x1000>, + <0xf9843010 0x4>; + interrupts = <GIC_SPI 72 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&crg HISTB_ETH1_MAC_CLK>, + <&crg HISTB_ETH1_MACIF_CLK>; + clock-names = "mac_core", "mac_ifc"; + resets = <&crg 0xcc 9>, + <&crg 0xcc 11>, + <&gmacphyrst 1>; + reset-names = "mac_core", "mac_ifc", "phy"; + }; + + ir: ir@f8001000 { + compatible = "hisilicon,hix5hd2-ir"; + reg = <0xf8001000 0x1000>; + interrupts = <GIC_SPI 47 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&sysctrl HISTB_IR_CLK>; + }; + }; +}; diff --git a/include/dt-bindings/clock/histb-clock.h b/include/dt-bindings/clock/histb-clock.h new file mode 100644 index 0000000..181c0f0 --- /dev/null +++ b/include/dt-bindings/clock/histb-clock.h @@ -0,0 +1,66 @@ +/* + * Copyright (c) 2016 HiSilicon Technologies Co., Ltd. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +#ifndef __DTS_HISTB_CLOCK_H +#define __DTS_HISTB_CLOCK_H + +/* clocks provided by core CRG */ +#define HISTB_OSC_CLK 0 +#define HISTB_APB_CLK 1 +#define HISTB_AHB_CLK 2 +#define HISTB_UART1_CLK 3 +#define HISTB_UART2_CLK 4 +#define HISTB_UART3_CLK 5 +#define HISTB_I2C0_CLK 6 +#define HISTB_I2C1_CLK 7 +#define HISTB_I2C2_CLK 8 +#define HISTB_I2C3_CLK 9 +#define HISTB_I2C4_CLK 10 +#define HISTB_I2C5_CLK 11 +#define HISTB_SPI0_CLK 12 +#define HISTB_SPI1_CLK 13 +#define HISTB_SPI2_CLK 14 +#define HISTB_SCI_CLK 15 +#define HISTB_FMC_CLK 16 +#define HISTB_MMC_BIU_CLK 17 +#define HISTB_MMC_CIU_CLK 18 +#define HISTB_MMC_DRV_CLK 19 +#define HISTB_MMC_SAMPLE_CLK 20 +#define HISTB_SDIO0_BIU_CLK 21 +#define HISTB_SDIO0_CIU_CLK 22 +#define HISTB_SDIO0_DRV_CLK 23 +#define HISTB_SDIO0_SAMPLE_CLK 24 +#define HISTB_PCIE_AUX_CLK 25 +#define HISTB_PCIE_PIPE_CLK 26 +#define HISTB_PCIE_SYS_CLK 27 +#define HISTB_PCIE_BUS_CLK 28 +#define HISTB_ETH0_MAC_CLK 29 +#define HISTB_ETH0_MACIF_CLK 30 +#define HISTB_ETH1_MAC_CLK 31 +#define HISTB_ETH1_MACIF_CLK 32 +#define HISTB_COMBPHY1_CLK 33 + + +/* clocks provided by mcu CRG */ +#define HISTB_MCE_CLK 1 +#define HISTB_IR_CLK 2 +#define HISTB_TIMER01_CLK 3 +#define HISTB_LEDC_CLK 4 +#define HISTB_UART0_CLK 5 +#define HISTB_LSADC_CLK 6 + +#endif /* __DTS_HISTB_CLOCK_H */ diff --git a/include/dt-bindings/reset/ti-syscon.h b/include/dt-bindings/reset/ti-syscon.h new file mode 100644 index 0000000..884fd91 --- /dev/null +++ b/include/dt-bindings/reset/ti-syscon.h @@ -0,0 +1,38 @@ +/* + * TI Syscon Reset definitions + * + * Copyright (C) 2015-2016 Texas Instruments Incorporated - http://www.ti.com/ + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + */ + +#ifndef __DT_BINDINGS_RESET_TI_SYSCON_H__ +#define __DT_BINDINGS_RESET_TI_SYSCON_H__ + +/* + * The reset does not support the feature and corresponding + * values are not valid + */ +#define ASSERT_NONE (1 << 0) +#define DEASSERT_NONE (1 << 1) +#define STATUS_NONE (1 << 2) + +/* When set this function is activated by setting(vs clearing) this bit */ +#define ASSERT_SET (1 << 3) +#define DEASSERT_SET (1 << 4) +#define STATUS_SET (1 << 5) + +/* The following are the inverse of the above and are added for consistency */ +#define ASSERT_CLEAR (0 << 3) +#define DEASSERT_CLEAR (0 << 4) +#define STATUS_CLEAR (0 << 5) + +#endif
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org --- .../arm/include/asm/arch-hi3798cv200/hi3798cv200.h | 93 ++++++++++ drivers/usb/host/Kconfig | 6 + drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-hi3798cv200.c | 196 +++++++++++++++++++++ 4 files changed, 296 insertions(+) create mode 100644 arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h create mode 100644 drivers/usb/host/ehci-hi3798cv200.c
diff --git a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h new file mode 100644 index 0000000..c67fda1 --- /dev/null +++ b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h @@ -0,0 +1,93 @@ +/* + * (C) Copyright 2017 Linaro + * Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef __HI3798cv200_H__ +#define __HI3798cv200_H__ + +#define REG_BASE_CRG 0xF8A22000 +#define REG_BASE_SCTL 0xF8000000 +#define REG_BASE_CRG 0xF8A22000 +#define REG_BASE_PERI_CTRL 0xF8A20000 + +/* DEVICES */ +#define REG_BASE_UART0 0xF8B00000 +#define REG_BASE_EHCI 0XF9890000 +#define REG_BASE_MCI 0xF9830000 +#define REG_BASE_MMC0 0xF9830000 + +/* SC */ +#define REG_SC_CTRL 0x0000 +#define REG_SC_SYSRES 0x0004 +#define REG_SC_GEN0 0x0080 +#define REG_SC_GEN1 0x0084 +#define REG_SC_GEN2 0x0088 +#define REG_SC_GEN12 0x00B0 + +/* USB EHCI driver */ +#define PERI_USB0 (0xF8A20000 + 0x120) +#define PERI_USB1 (0xF8A20000 + 0x124) +#define PERI_USB3 (0xF8A20000 + 0x12c) +#define PERI_USB4 (0xF8A20000 + 0x130) + +#define WORDINTERFACE (1 << 0) +#define ULPI_BYPASS_EN_PORT0 (1 << 3) +#define SS_BURST16_EN (1 << 9) +#define TEST_WRDATA (0x4) +#define TEST_ADDR (0x6 << 8) +#define TEST_WREN (1 << 21) +#define TEST_CLK (1 << 22) +#define TEST_RSTN (1 << 23) + +#define PERI_CRG46 (0xF8A22000 + 0xb8) +#define USB2_BUS_CKEN (1<<0) +#define USB2_OHCI48M_CKEN (1<<1) +#define USB2_OHCI12M_CKEN (1<<2) +#define USB2_OTG_UTMI_CKEN (1<<3) +#define USB2_HST_PHY_CKEN (1<<4) +#define USB2_UTMI0_CKEN (1<<5) +#define USB2_BUS_SRST_REQ (1<<12) +#define USB2_UTMI0_SRST_REQ (1<<13) +#define USB2_HST_PHY_SYST_REQ (1<<16) +#define USB2_OTG_PHY_SYST_REQ (1<<17) +#define USB2_CLK48_SEL (1<<20) + +#define PERI_CRG47 (0xF8A22000 + 0xbc) +#define USB2_PHY01_REF_CKEN (1 << 0) +#define USB2_PHY2_REF_CKEN (1 << 2) +#define USB2_PHY01_SRST_REQ (1 << 4) +#define USB2_PHY2_SRST_REQ (1 << 6) +#define USB2_PHY01_SRST_TREQ0 (1 << 8) +#define USB2_PHY01_SRST_TREQ1 (1 << 9) +#define USB2_PHY2_SRST_TREQ (1 << 10) +#define USB2_PHY01_REFCLK_SEL (1 << 12) +#define USB2_PHY2_REFCLK_SEL (1 << 14) + +#define REG_START_MODE 0x0000 +#define REG_PERI_STAT 0x0004 +#define REG_PERI_CTRL 0x0008 +#define REG_PERI_CRG26 0x00A8 +#define NF_BOOTBW_MASK (1<<12) + +#define HI3798CV200_EHCI_CTRL (PERI_USB0) + +/* Generate padding data ranges with unique identifiers. */ +#define ___cat(a,b) a##b +#define __cat(a,b) ___cat(a,b) +#define __padding(__words) struct { __u32 __cat(__pad, __COUNTER__)[__words]; } + +struct hi3798cv200_ehci_ctrl_regs { + u32 peri_usb0; + u32 peri_usb1; + u32 peri_usb2; + u32 peri_usb3; + u32 peri_usb4; + __padding(0x7e1); + u32 peri_crg46; + u32 peri_crg47; +}; + +#endif diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 0bf8274..a749d0e 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -128,6 +128,12 @@ config USB_EHCI_ZYNQ ---help--- Enable support for Zynq on-chip EHCI USB controller
+config USB_EHCI_POPLAR + bool "Support for HI3798cv200 EHCI USB controller" + default y + ---help--- + Enable support for Poplar on-chip EHCI USB controller + config USB_EHCI_GENERIC bool "Support for generic EHCI USB controller" depends on OF_CONTROL diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 58c0cf5..3661636 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o +obj-$(CONFIG_USB_EHCI_POPLAR) += ehci-hi3798cv200.o
# xhci obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o diff --git a/drivers/usb/host/ehci-hi3798cv200.c b/drivers/usb/host/ehci-hi3798cv200.c new file mode 100644 index 0000000..c535de1 --- /dev/null +++ b/drivers/usb/host/ehci-hi3798cv200.c @@ -0,0 +1,196 @@ +/* + * (C) Copyright 2017 Linaro + * Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/hi3798cv200.h> +#include <asm/io.h> + +#include "ehci.h" + +static struct hi3798cv200_ehci_ctrl_regs *ctrl = (void *) HI3798CV200_EHCI_CTRL; + +static void inno_phy_config_2p_1(void) +{ + u32 reg; + /* write 0x4 to addr 0x06 + * config 2P PHY clk output + * delay 1ms for waiting PLL stable + */ + reg = TEST_WRDATA|TEST_ADDR|TEST_WREN|TEST_RSTN; + writel(reg, &ctrl->peri_usb0); + reg = TEST_WRDATA|TEST_ADDR|TEST_WREN|TEST_RSTN|TEST_CLK; + writel(reg, &ctrl->peri_usb0); + reg = TEST_WRDATA|TEST_ADDR|TEST_WREN|TEST_RSTN; + writel(reg, &ctrl->peri_usb0); + mdelay(1); + + /* write 0x1c to addr 0x00 + * 0x00[0] = 0 : close EOP pre-emphasis + * 0x00[2] = 1 : open Data pre-emphasis + */ + writel(0xa1001c, &ctrl->peri_usb0); + writel(0xe1001c, &ctrl->peri_usb0); + writel(0xa1001c, &ctrl->peri_usb0); + udelay(20); + + /* write 0x07 to 0x06 + * {0x06[1:0],0x05[7]} = 110 : Rcomp = 150mV , increase DC level + */ + writel(0xa00607, &ctrl->peri_usb0); + writel(0xe00607, &ctrl->peri_usb0); + writel(0xa00607, &ctrl->peri_usb0); + udelay(20); + + /* write 0x00 to addr 0x07 + * 0x07[1] = 0 : Keep Rcomp working + */ + writel(0xa10700, &ctrl->peri_usb0); + writel(0xe10700, &ctrl->peri_usb0); + writel(0xa10700, &ctrl->peri_usb0); + udelay(20); + + /* write 0xab to 0x0a + * 0x0a[7:5] = 101 : Icomp = 212mV , increase current drive + */ + writel(0xa00aab, &ctrl->peri_usb0); + writel(0xe00aab, &ctrl->peri_usb0); + writel(0xa00aab, &ctrl->peri_usb0); + udelay(20); + + /* write 0x40 to addr 0x11 + * 0x11[6:5] = 10 : sovle EMI problem, rx_active will + * not stay at 1 when error packets received + */ + writel(0xa11140, &ctrl->peri_usb0); + writel(0xe11140, &ctrl->peri_usb0); + writel(0xa11140, &ctrl->peri_usb0); + udelay(20); + + /* write 0x41 to addr 0x10 + * 0x10[0] = 1 : Comp Mode Select + */ + writel(0xa11041, &ctrl->peri_usb0); + writel(0xe11041, &ctrl->peri_usb0); + writel(0xa11041, &ctrl->peri_usb0); + udelay(20); + + /* + * {0x00a[0],0x009[7:6]} = 110 : Eye Diagram Adjust + * {0x10a[0],0x109[7:6]} = 000 : Eye Diagram Adjust + */ + writel(0xa0098c, &ctrl->peri_usb0); + writel(0xe0098c, &ctrl->peri_usb0); + writel(0xa0098c, &ctrl->peri_usb0); + writel(0xa10a0a, &ctrl->peri_usb0); + writel(0xe10a0a, &ctrl->peri_usb0); + writel(0xa10a0a, &ctrl->peri_usb0); + udelay(20); +} + +#ifndef CONFIG_DM_USB +int ehci_hcd_init(int index, enum usb_init_type init, + struct ehci_hccr **hccr, struct ehci_hcor **hcor) +{ + int reg; + + *hccr = (struct ehci_hccr *) REG_BASE_EHCI; + *hcor = (struct ehci_hcor *)( (void *) REG_BASE_EHCI + + HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase))); + + /* reset controller bus/utmi/roothub */ + reg = readl(&ctrl->peri_crg46); + reg |= (USB2_BUS_SRST_REQ + | USB2_UTMI0_SRST_REQ + | USB2_HST_PHY_SYST_REQ + | USB2_OTG_PHY_SYST_REQ); + writel(reg, &ctrl->peri_crg46); + udelay(200); + + /* reset phy por/utmi */ + reg = readl(&ctrl->peri_crg47); + reg |= (USB2_PHY01_SRST_REQ + | USB2_PHY01_SRST_TREQ1); + writel(reg, &ctrl->peri_crg47); + udelay(200); + + reg = readl(&ctrl->peri_usb3); + reg |= ULPI_BYPASS_EN_PORT0; + reg &= ~(WORDINTERFACE); + reg &= ~(SS_BURST16_EN); + writel(reg, &ctrl->peri_usb3); + udelay(100); + + /* open ref clk */ + reg = readl(&ctrl->peri_crg47); + reg |= (USB2_PHY01_REF_CKEN); + writel(reg, &ctrl->peri_crg47); + udelay(300); + + /* cancel power on reset */ + reg = readl(&ctrl->peri_crg47); + reg &= ~(USB2_PHY01_SRST_REQ); + writel(reg, &ctrl->peri_crg47); + udelay(500); + + inno_phy_config_2p_1(); + + /* cancel port reset + * delay 10ms for waiting comp circuit stable + */ + reg = readl(&ctrl->peri_crg47); + reg &= ~(USB2_PHY01_SRST_TREQ1); + writel(reg, &ctrl->peri_crg47); + mdelay(10); + + /* open controller clk */ + reg = readl(&ctrl->peri_crg46); + reg |= (USB2_BUS_CKEN + | USB2_OHCI48M_CKEN + | USB2_OHCI12M_CKEN + | USB2_OTG_UTMI_CKEN + | USB2_HST_PHY_CKEN + | USB2_UTMI0_CKEN); + writel(reg, &ctrl->peri_crg46); + udelay(200); + + /* cancel control reset */ + reg = readl(&ctrl->peri_crg46); + reg &= ~(USB2_BUS_SRST_REQ + | USB2_UTMI0_SRST_REQ + | USB2_HST_PHY_SYST_REQ + | USB2_OTG_PHY_SYST_REQ); + writel(reg, &ctrl->peri_crg46); + udelay(200); + + + return 0; +} + +int ehci_hcd_stop(int index) +{ + int reg; + + reg = readl(&ctrl->peri_crg46); + reg |= (USB2_BUS_SRST_REQ + | USB2_UTMI0_SRST_REQ + | USB2_HST_PHY_SYST_REQ); + writel(reg, &ctrl->peri_crg46); + + udelay(200); + + reg = readl(&ctrl->peri_crg47); + reg |= (USB2_PHY01_SRST_REQ + | USB2_PHY01_SRST_TREQ1); + writel(reg, &ctrl->peri_crg47); + + udelay(100); + + return 0; +} +#else +error "CONFIG_DM_USB not supported for hi3798cv200" +#endif
On Thu, May 04, 2017 at 03:47:07PM +0200, Jorge Ramirez-Ortiz wrote:
CC'ing Marek...
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
.../arm/include/asm/arch-hi3798cv200/hi3798cv200.h | 93 ++++++++++ drivers/usb/host/Kconfig | 6 + drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-hi3798cv200.c | 196 +++++++++++++++++++++ 4 files changed, 296 insertions(+) create mode 100644 arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h create mode 100644 drivers/usb/host/ehci-hi3798cv200.c
diff --git a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h new file mode 100644 index 0000000..c67fda1 --- /dev/null +++ b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h @@ -0,0 +1,93 @@ +/*
- (C) Copyright 2017 Linaro
- Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __HI3798cv200_H__ +#define __HI3798cv200_H__
+#define REG_BASE_CRG 0xF8A22000 +#define REG_BASE_SCTL 0xF8000000 +#define REG_BASE_CRG 0xF8A22000 +#define REG_BASE_PERI_CTRL 0xF8A20000
+/* DEVICES */ +#define REG_BASE_UART0 0xF8B00000 +#define REG_BASE_EHCI 0XF9890000 +#define REG_BASE_MCI 0xF9830000 +#define REG_BASE_MMC0 0xF9830000
+/* SC */ +#define REG_SC_CTRL 0x0000 +#define REG_SC_SYSRES 0x0004 +#define REG_SC_GEN0 0x0080 +#define REG_SC_GEN1 0x0084 +#define REG_SC_GEN2 0x0088 +#define REG_SC_GEN12 0x00B0
+/* USB EHCI driver */ +#define PERI_USB0 (0xF8A20000 + 0x120) +#define PERI_USB1 (0xF8A20000 + 0x124) +#define PERI_USB3 (0xF8A20000 + 0x12c) +#define PERI_USB4 (0xF8A20000 + 0x130)
+#define WORDINTERFACE (1 << 0) +#define ULPI_BYPASS_EN_PORT0 (1 << 3) +#define SS_BURST16_EN (1 << 9) +#define TEST_WRDATA (0x4) +#define TEST_ADDR (0x6 << 8) +#define TEST_WREN (1 << 21) +#define TEST_CLK (1 << 22) +#define TEST_RSTN (1 << 23)
+#define PERI_CRG46 (0xF8A22000 + 0xb8) +#define USB2_BUS_CKEN (1<<0) +#define USB2_OHCI48M_CKEN (1<<1) +#define USB2_OHCI12M_CKEN (1<<2) +#define USB2_OTG_UTMI_CKEN (1<<3) +#define USB2_HST_PHY_CKEN (1<<4) +#define USB2_UTMI0_CKEN (1<<5) +#define USB2_BUS_SRST_REQ (1<<12) +#define USB2_UTMI0_SRST_REQ (1<<13) +#define USB2_HST_PHY_SYST_REQ (1<<16) +#define USB2_OTG_PHY_SYST_REQ (1<<17) +#define USB2_CLK48_SEL (1<<20)
+#define PERI_CRG47 (0xF8A22000 + 0xbc) +#define USB2_PHY01_REF_CKEN (1 << 0) +#define USB2_PHY2_REF_CKEN (1 << 2) +#define USB2_PHY01_SRST_REQ (1 << 4) +#define USB2_PHY2_SRST_REQ (1 << 6) +#define USB2_PHY01_SRST_TREQ0 (1 << 8) +#define USB2_PHY01_SRST_TREQ1 (1 << 9) +#define USB2_PHY2_SRST_TREQ (1 << 10) +#define USB2_PHY01_REFCLK_SEL (1 << 12) +#define USB2_PHY2_REFCLK_SEL (1 << 14)
+#define REG_START_MODE 0x0000 +#define REG_PERI_STAT 0x0004 +#define REG_PERI_CTRL 0x0008 +#define REG_PERI_CRG26 0x00A8 +#define NF_BOOTBW_MASK (1<<12)
+#define HI3798CV200_EHCI_CTRL (PERI_USB0)
+/* Generate padding data ranges with unique identifiers. */ +#define ___cat(a,b) a##b +#define __cat(a,b) ___cat(a,b) +#define __padding(__words) struct { __u32 __cat(__pad, __COUNTER__)[__words]; }
+struct hi3798cv200_ehci_ctrl_regs {
- u32 peri_usb0;
- u32 peri_usb1;
- u32 peri_usb2;
- u32 peri_usb3;
- u32 peri_usb4;
- __padding(0x7e1);
- u32 peri_crg46;
- u32 peri_crg47;
+};
+#endif diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 0bf8274..a749d0e 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -128,6 +128,12 @@ config USB_EHCI_ZYNQ ---help--- Enable support for Zynq on-chip EHCI USB controller
+config USB_EHCI_POPLAR
- bool "Support for HI3798cv200 EHCI USB controller"
- default y
- ---help---
Enable support for Poplar on-chip EHCI USB controllerconfig USB_EHCI_GENERIC bool "Support for generic EHCI USB controller" depends on OF_CONTROL diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 58c0cf5..3661636 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o +obj-$(CONFIG_USB_EHCI_POPLAR) += ehci-hi3798cv200.o
# xhci obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o diff --git a/drivers/usb/host/ehci-hi3798cv200.c b/drivers/usb/host/ehci-hi3798cv200.c new file mode 100644 index 0000000..c535de1 --- /dev/null +++ b/drivers/usb/host/ehci-hi3798cv200.c @@ -0,0 +1,196 @@ +/*
- (C) Copyright 2017 Linaro
- Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/arch/hi3798cv200.h> +#include <asm/io.h>
+#include "ehci.h"
+static struct hi3798cv200_ehci_ctrl_regs *ctrl = (void *) HI3798CV200_EHCI_CTRL;
+static void inno_phy_config_2p_1(void) +{
- u32 reg;
- /* write 0x4 to addr 0x06
- config 2P PHY clk output
- delay 1ms for waiting PLL stable
- */
- reg = TEST_WRDATA|TEST_ADDR|TEST_WREN|TEST_RSTN;
- writel(reg, &ctrl->peri_usb0);
- reg = TEST_WRDATA|TEST_ADDR|TEST_WREN|TEST_RSTN|TEST_CLK;
- writel(reg, &ctrl->peri_usb0);
- reg = TEST_WRDATA|TEST_ADDR|TEST_WREN|TEST_RSTN;
- writel(reg, &ctrl->peri_usb0);
- mdelay(1);
- /* write 0x1c to addr 0x00
- 0x00[0] = 0 : close EOP pre-emphasis
- 0x00[2] = 1 : open Data pre-emphasis
- */
- writel(0xa1001c, &ctrl->peri_usb0);
- writel(0xe1001c, &ctrl->peri_usb0);
- writel(0xa1001c, &ctrl->peri_usb0);
- udelay(20);
- /* write 0x07 to 0x06
- {0x06[1:0],0x05[7]} = 110 : Rcomp = 150mV , increase DC level
- */
- writel(0xa00607, &ctrl->peri_usb0);
- writel(0xe00607, &ctrl->peri_usb0);
- writel(0xa00607, &ctrl->peri_usb0);
- udelay(20);
- /* write 0x00 to addr 0x07
- 0x07[1] = 0 : Keep Rcomp working
- */
- writel(0xa10700, &ctrl->peri_usb0);
- writel(0xe10700, &ctrl->peri_usb0);
- writel(0xa10700, &ctrl->peri_usb0);
- udelay(20);
- /* write 0xab to 0x0a
- 0x0a[7:5] = 101 : Icomp = 212mV , increase current drive
- */
- writel(0xa00aab, &ctrl->peri_usb0);
- writel(0xe00aab, &ctrl->peri_usb0);
- writel(0xa00aab, &ctrl->peri_usb0);
- udelay(20);
- /* write 0x40 to addr 0x11
- 0x11[6:5] = 10 : sovle EMI problem, rx_active will
- not stay at 1 when error packets received
- */
- writel(0xa11140, &ctrl->peri_usb0);
- writel(0xe11140, &ctrl->peri_usb0);
- writel(0xa11140, &ctrl->peri_usb0);
- udelay(20);
- /* write 0x41 to addr 0x10
- 0x10[0] = 1 : Comp Mode Select
- */
- writel(0xa11041, &ctrl->peri_usb0);
- writel(0xe11041, &ctrl->peri_usb0);
- writel(0xa11041, &ctrl->peri_usb0);
- udelay(20);
- /*
- {0x00a[0],0x009[7:6]} = 110 : Eye Diagram Adjust
- {0x10a[0],0x109[7:6]} = 000 : Eye Diagram Adjust
- */
- writel(0xa0098c, &ctrl->peri_usb0);
- writel(0xe0098c, &ctrl->peri_usb0);
- writel(0xa0098c, &ctrl->peri_usb0);
- writel(0xa10a0a, &ctrl->peri_usb0);
- writel(0xe10a0a, &ctrl->peri_usb0);
- writel(0xa10a0a, &ctrl->peri_usb0);
- udelay(20);
+}
+#ifndef CONFIG_DM_USB +int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)+{
- int reg;
- *hccr = (struct ehci_hccr *) REG_BASE_EHCI;
- *hcor = (struct ehci_hcor *)( (void *) REG_BASE_EHCI +
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));- /* reset controller bus/utmi/roothub */
- reg = readl(&ctrl->peri_crg46);
- reg |= (USB2_BUS_SRST_REQ
| USB2_UTMI0_SRST_REQ| USB2_HST_PHY_SYST_REQ| USB2_OTG_PHY_SYST_REQ);- writel(reg, &ctrl->peri_crg46);
- udelay(200);
- /* reset phy por/utmi */
- reg = readl(&ctrl->peri_crg47);
- reg |= (USB2_PHY01_SRST_REQ
| USB2_PHY01_SRST_TREQ1);- writel(reg, &ctrl->peri_crg47);
- udelay(200);
- reg = readl(&ctrl->peri_usb3);
- reg |= ULPI_BYPASS_EN_PORT0;
- reg &= ~(WORDINTERFACE);
- reg &= ~(SS_BURST16_EN);
- writel(reg, &ctrl->peri_usb3);
- udelay(100);
- /* open ref clk */
- reg = readl(&ctrl->peri_crg47);
- reg |= (USB2_PHY01_REF_CKEN);
- writel(reg, &ctrl->peri_crg47);
- udelay(300);
- /* cancel power on reset */
- reg = readl(&ctrl->peri_crg47);
- reg &= ~(USB2_PHY01_SRST_REQ);
- writel(reg, &ctrl->peri_crg47);
- udelay(500);
- inno_phy_config_2p_1();
- /* cancel port reset
* delay 10ms for waiting comp circuit stable- */
- reg = readl(&ctrl->peri_crg47);
- reg &= ~(USB2_PHY01_SRST_TREQ1);
- writel(reg, &ctrl->peri_crg47);
- mdelay(10);
- /* open controller clk */
- reg = readl(&ctrl->peri_crg46);
- reg |= (USB2_BUS_CKEN
| USB2_OHCI48M_CKEN| USB2_OHCI12M_CKEN| USB2_OTG_UTMI_CKEN| USB2_HST_PHY_CKEN| USB2_UTMI0_CKEN);- writel(reg, &ctrl->peri_crg46);
- udelay(200);
- /* cancel control reset */
- reg = readl(&ctrl->peri_crg46);
- reg &= ~(USB2_BUS_SRST_REQ
| USB2_UTMI0_SRST_REQ| USB2_HST_PHY_SYST_REQ| USB2_OTG_PHY_SYST_REQ);- writel(reg, &ctrl->peri_crg46);
- udelay(200);
- return 0;
+}
+int ehci_hcd_stop(int index) +{
- int reg;
- reg = readl(&ctrl->peri_crg46);
- reg |= (USB2_BUS_SRST_REQ
| USB2_UTMI0_SRST_REQ| USB2_HST_PHY_SYST_REQ);- writel(reg, &ctrl->peri_crg46);
- udelay(200);
- reg = readl(&ctrl->peri_crg47);
- reg |= (USB2_PHY01_SRST_REQ
| USB2_PHY01_SRST_TREQ1);- writel(reg, &ctrl->peri_crg47);
- udelay(100);
- return 0;
+} +#else +error "CONFIG_DM_USB not supported for hi3798cv200"
+#endif
2.7.4
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
On 05/05/2017 04:32 PM, Tom Rini wrote:
On Thu, May 04, 2017 at 03:47:07PM +0200, Jorge Ramirez-Ortiz wrote:
CC'ing Marek...
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
.../arm/include/asm/arch-hi3798cv200/hi3798cv200.h | 93 ++++++++++ drivers/usb/host/Kconfig | 6 + drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-hi3798cv200.c | 196 +++++++++++++++++++++ 4 files changed, 296 insertions(+) create mode 100644 arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h create mode 100644 drivers/usb/host/ehci-hi3798cv200.c
diff --git a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h new file mode 100644 index 0000000..c67fda1 --- /dev/null +++ b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h @@ -0,0 +1,93 @@ +/*
- (C) Copyright 2017 Linaro
- Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __HI3798cv200_H__ +#define __HI3798cv200_H__
This should be a separate patch ..
+#define REG_BASE_CRG 0xF8A22000 +#define REG_BASE_SCTL 0xF8000000 +#define REG_BASE_CRG 0xF8A22000 +#define REG_BASE_PERI_CTRL 0xF8A20000
+/* DEVICES */ +#define REG_BASE_UART0 0xF8B00000 +#define REG_BASE_EHCI 0XF9890000 +#define REG_BASE_MCI 0xF9830000 +#define REG_BASE_MMC0 0xF9830000
+/* SC */ +#define REG_SC_CTRL 0x0000 +#define REG_SC_SYSRES 0x0004 +#define REG_SC_GEN0 0x0080 +#define REG_SC_GEN1 0x0084 +#define REG_SC_GEN2 0x0088 +#define REG_SC_GEN12 0x00B0
+/* USB EHCI driver */ +#define PERI_USB0 (0xF8A20000 + 0x120) +#define PERI_USB1 (0xF8A20000 + 0x124) +#define PERI_USB3 (0xF8A20000 + 0x12c) +#define PERI_USB4 (0xF8A20000 + 0x130)
+#define WORDINTERFACE (1 << 0)
Use BIT()
+#define ULPI_BYPASS_EN_PORT0 (1 << 3) +#define SS_BURST16_EN (1 << 9) +#define TEST_WRDATA (0x4) +#define TEST_ADDR (0x6 << 8) +#define TEST_WREN (1 << 21) +#define TEST_CLK (1 << 22) +#define TEST_RSTN (1 << 23)
+#define PERI_CRG46 (0xF8A22000 + 0xb8) +#define USB2_BUS_CKEN (1<<0) +#define USB2_OHCI48M_CKEN (1<<1) +#define USB2_OHCI12M_CKEN (1<<2) +#define USB2_OTG_UTMI_CKEN (1<<3) +#define USB2_HST_PHY_CKEN (1<<4) +#define USB2_UTMI0_CKEN (1<<5) +#define USB2_BUS_SRST_REQ (1<<12) +#define USB2_UTMI0_SRST_REQ (1<<13) +#define USB2_HST_PHY_SYST_REQ (1<<16) +#define USB2_OTG_PHY_SYST_REQ (1<<17) +#define USB2_CLK48_SEL (1<<20)
+#define PERI_CRG47 (0xF8A22000 + 0xbc) +#define USB2_PHY01_REF_CKEN (1 << 0) +#define USB2_PHY2_REF_CKEN (1 << 2) +#define USB2_PHY01_SRST_REQ (1 << 4) +#define USB2_PHY2_SRST_REQ (1 << 6) +#define USB2_PHY01_SRST_TREQ0 (1 << 8) +#define USB2_PHY01_SRST_TREQ1 (1 << 9) +#define USB2_PHY2_SRST_TREQ (1 << 10) +#define USB2_PHY01_REFCLK_SEL (1 << 12) +#define USB2_PHY2_REFCLK_SEL (1 << 14)
+#define REG_START_MODE 0x0000 +#define REG_PERI_STAT 0x0004 +#define REG_PERI_CTRL 0x0008 +#define REG_PERI_CRG26 0x00A8 +#define NF_BOOTBW_MASK (1<<12)
+#define HI3798CV200_EHCI_CTRL (PERI_USB0)
Superfluous parenthesis.
+/* Generate padding data ranges with unique identifiers. */ +#define ___cat(a,b) a##b +#define __cat(a,b) ___cat(a,b) +#define __padding(__words) struct { __u32 __cat(__pad, __COUNTER__)[__words]; }
Uh what ? Needed ?
+struct hi3798cv200_ehci_ctrl_regs {
- u32 peri_usb0;
- u32 peri_usb1;
- u32 peri_usb2;
- u32 peri_usb3;
- u32 peri_usb4;
- __padding(0x7e1);
- u32 peri_crg46;
- u32 peri_crg47;
Just use #define FOO_REG_BAR 0xf00 , drop this structure stuff ...
+};
+#endif diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 0bf8274..a749d0e 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -128,6 +128,12 @@ config USB_EHCI_ZYNQ ---help--- Enable support for Zynq on-chip EHCI USB controller
+config USB_EHCI_POPLAR
- bool "Support for HI3798cv200 EHCI USB controller"
Does HI stand for Hitachi ?
- default y
- ---help---
Enable support for Poplar on-chip EHCI USB controllerconfig USB_EHCI_GENERIC bool "Support for generic EHCI USB controller" depends on OF_CONTROL diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 58c0cf5..3661636 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o +obj-$(CONFIG_USB_EHCI_POPLAR) += ehci-hi3798cv200.o
# xhci obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o diff --git a/drivers/usb/host/ehci-hi3798cv200.c b/drivers/usb/host/ehci-hi3798cv200.c new file mode 100644 index 0000000..c535de1 --- /dev/null +++ b/drivers/usb/host/ehci-hi3798cv200.c @@ -0,0 +1,196 @@ +/*
- (C) Copyright 2017 Linaro
- Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/arch/hi3798cv200.h> +#include <asm/io.h>
+#include "ehci.h"
+static struct hi3798cv200_ehci_ctrl_regs *ctrl = (void *) HI3798CV200_EHCI_CTRL;
This should use DM
+static void inno_phy_config_2p_1(void) +{
- u32 reg;
- /* write 0x4 to addr 0x06
- config 2P PHY clk output
- delay 1ms for waiting PLL stable
- */
- reg = TEST_WRDATA|TEST_ADDR|TEST_WREN|TEST_RSTN;
- writel(reg, &ctrl->peri_usb0);
- reg = TEST_WRDATA|TEST_ADDR|TEST_WREN|TEST_RSTN|TEST_CLK;
- writel(reg, &ctrl->peri_usb0);
- reg = TEST_WRDATA|TEST_ADDR|TEST_WREN|TEST_RSTN;
- writel(reg, &ctrl->peri_usb0);
- mdelay(1);
- /* write 0x1c to addr 0x00
- 0x00[0] = 0 : close EOP pre-emphasis
- 0x00[2] = 1 : open Data pre-emphasis
- */
- writel(0xa1001c, &ctrl->peri_usb0);
- writel(0xe1001c, &ctrl->peri_usb0);
- writel(0xa1001c, &ctrl->peri_usb0);
- udelay(20);
- /* write 0x07 to 0x06
- {0x06[1:0],0x05[7]} = 110 : Rcomp = 150mV , increase DC level
- */
- writel(0xa00607, &ctrl->peri_usb0);
- writel(0xe00607, &ctrl->peri_usb0);
- writel(0xa00607, &ctrl->peri_usb0);
- udelay(20);
- /* write 0x00 to addr 0x07
- 0x07[1] = 0 : Keep Rcomp working
- */
- writel(0xa10700, &ctrl->peri_usb0);
- writel(0xe10700, &ctrl->peri_usb0);
- writel(0xa10700, &ctrl->peri_usb0);
- udelay(20);
- /* write 0xab to 0x0a
- 0x0a[7:5] = 101 : Icomp = 212mV , increase current drive
- */
- writel(0xa00aab, &ctrl->peri_usb0);
- writel(0xe00aab, &ctrl->peri_usb0);
- writel(0xa00aab, &ctrl->peri_usb0);
- udelay(20);
- /* write 0x40 to addr 0x11
- 0x11[6:5] = 10 : sovle EMI problem, rx_active will
- not stay at 1 when error packets received
- */
- writel(0xa11140, &ctrl->peri_usb0);
- writel(0xe11140, &ctrl->peri_usb0);
- writel(0xa11140, &ctrl->peri_usb0);
- udelay(20);
- /* write 0x41 to addr 0x10
- 0x10[0] = 1 : Comp Mode Select
- */
- writel(0xa11041, &ctrl->peri_usb0);
- writel(0xe11041, &ctrl->peri_usb0);
- writel(0xa11041, &ctrl->peri_usb0);
- udelay(20);
- /*
- {0x00a[0],0x009[7:6]} = 110 : Eye Diagram Adjust
- {0x10a[0],0x109[7:6]} = 000 : Eye Diagram Adjust
- */
- writel(0xa0098c, &ctrl->peri_usb0);
- writel(0xe0098c, &ctrl->peri_usb0);
- writel(0xa0098c, &ctrl->peri_usb0);
- writel(0xa10a0a, &ctrl->peri_usb0);
- writel(0xe10a0a, &ctrl->peri_usb0);
- writel(0xa10a0a, &ctrl->peri_usb0);
- udelay(20);
+}
+#ifndef CONFIG_DM_USB +int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)+{
- int reg;
- *hccr = (struct ehci_hccr *) REG_BASE_EHCI;
- *hcor = (struct ehci_hcor *)( (void *) REG_BASE_EHCI +
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));- /* reset controller bus/utmi/roothub */
- reg = readl(&ctrl->peri_crg46);
- reg |= (USB2_BUS_SRST_REQ
| USB2_UTMI0_SRST_REQ| USB2_HST_PHY_SYST_REQ| USB2_OTG_PHY_SYST_REQ);- writel(reg, &ctrl->peri_crg46);
- udelay(200);
Can the ulpi-phy code we have help here ? Also, clrsetbits_le32() and co ...
- /* reset phy por/utmi */
- reg = readl(&ctrl->peri_crg47);
- reg |= (USB2_PHY01_SRST_REQ
| USB2_PHY01_SRST_TREQ1);- writel(reg, &ctrl->peri_crg47);
- udelay(200);
- reg = readl(&ctrl->peri_usb3);
- reg |= ULPI_BYPASS_EN_PORT0;
- reg &= ~(WORDINTERFACE);
- reg &= ~(SS_BURST16_EN);
- writel(reg, &ctrl->peri_usb3);
- udelay(100);
- /* open ref clk */
- reg = readl(&ctrl->peri_crg47);
- reg |= (USB2_PHY01_REF_CKEN);
- writel(reg, &ctrl->peri_crg47);
- udelay(300);
- /* cancel power on reset */
- reg = readl(&ctrl->peri_crg47);
- reg &= ~(USB2_PHY01_SRST_REQ);
- writel(reg, &ctrl->peri_crg47);
- udelay(500);
- inno_phy_config_2p_1();
- /* cancel port reset
* delay 10ms for waiting comp circuit stable- */
- reg = readl(&ctrl->peri_crg47);
- reg &= ~(USB2_PHY01_SRST_TREQ1);
- writel(reg, &ctrl->peri_crg47);
- mdelay(10);
- /* open controller clk */
- reg = readl(&ctrl->peri_crg46);
- reg |= (USB2_BUS_CKEN
| USB2_OHCI48M_CKEN| USB2_OHCI12M_CKEN| USB2_OTG_UTMI_CKEN| USB2_HST_PHY_CKEN| USB2_UTMI0_CKEN);- writel(reg, &ctrl->peri_crg46);
- udelay(200);
- /* cancel control reset */
- reg = readl(&ctrl->peri_crg46);
- reg &= ~(USB2_BUS_SRST_REQ
| USB2_UTMI0_SRST_REQ| USB2_HST_PHY_SYST_REQ| USB2_OTG_PHY_SYST_REQ);- writel(reg, &ctrl->peri_crg46);
- udelay(200);
- return 0;
+}
+int ehci_hcd_stop(int index) +{
- int reg;
- reg = readl(&ctrl->peri_crg46);
- reg |= (USB2_BUS_SRST_REQ
| USB2_UTMI0_SRST_REQ| USB2_HST_PHY_SYST_REQ);- writel(reg, &ctrl->peri_crg46);
- udelay(200);
- reg = readl(&ctrl->peri_crg47);
- reg |= (USB2_PHY01_SRST_REQ
| USB2_PHY01_SRST_TREQ1);- writel(reg, &ctrl->peri_crg47);
- udelay(100);
- return 0;
+} +#else +error "CONFIG_DM_USB not supported for hi3798cv200"
+#endif
2.7.4
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
On 05/05/2017 05:34 PM, Marek Vasut wrote:
On 05/05/2017 04:32 PM, Tom Rini wrote:
On Thu, May 04, 2017 at 03:47:07PM +0200, Jorge Ramirez-Ortiz wrote:
CC'ing Marek...
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
.../arm/include/asm/arch-hi3798cv200/hi3798cv200.h | 93 ++++++++++ drivers/usb/host/Kconfig | 6 + drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-hi3798cv200.c | 196 +++++++++++++++++++++ 4 files changed, 296 insertions(+) create mode 100644 arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h create mode 100644 drivers/usb/host/ehci-hi3798cv200.c
diff --git a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h new file mode 100644 index 0000000..c67fda1 --- /dev/null +++ b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h @@ -0,0 +1,93 @@ +/*
- (C) Copyright 2017 Linaro
- Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __HI3798cv200_H__ +#define __HI3798cv200_H__
This should be a separate patch ..
hi Marek
to be clear, are you asking a single patch containing hi3798cv200.h?
+#define REG_BASE_CRG 0xF8A22000 +#define REG_BASE_SCTL 0xF8000000 +#define REG_BASE_CRG 0xF8A22000 +#define REG_BASE_PERI_CTRL 0xF8A20000
+/* DEVICES */ +#define REG_BASE_UART0 0xF8B00000 +#define REG_BASE_EHCI 0XF9890000 +#define REG_BASE_MCI 0xF9830000 +#define REG_BASE_MMC0 0xF9830000
+/* SC */ +#define REG_SC_CTRL 0x0000 +#define REG_SC_SYSRES 0x0004 +#define REG_SC_GEN0 0x0080 +#define REG_SC_GEN1 0x0084 +#define REG_SC_GEN2 0x0088 +#define REG_SC_GEN12 0x00B0
+/* USB EHCI driver */ +#define PERI_USB0 (0xF8A20000 + 0x120) +#define PERI_USB1 (0xF8A20000 + 0x124) +#define PERI_USB3 (0xF8A20000 + 0x12c) +#define PERI_USB4 (0xF8A20000 + 0x130)
+#define WORDINTERFACE (1 << 0)
Use BIT()
ack
+#define ULPI_BYPASS_EN_PORT0 (1 << 3) +#define SS_BURST16_EN (1 << 9) +#define TEST_WRDATA (0x4) +#define TEST_ADDR (0x6 << 8) +#define TEST_WREN (1 << 21) +#define TEST_CLK (1 << 22) +#define TEST_RSTN (1 << 23)
+#define PERI_CRG46 (0xF8A22000 + 0xb8) +#define USB2_BUS_CKEN (1<<0) +#define USB2_OHCI48M_CKEN (1<<1) +#define USB2_OHCI12M_CKEN (1<<2) +#define USB2_OTG_UTMI_CKEN (1<<3) +#define USB2_HST_PHY_CKEN (1<<4) +#define USB2_UTMI0_CKEN (1<<5) +#define USB2_BUS_SRST_REQ (1<<12) +#define USB2_UTMI0_SRST_REQ (1<<13) +#define USB2_HST_PHY_SYST_REQ (1<<16) +#define USB2_OTG_PHY_SYST_REQ (1<<17) +#define USB2_CLK48_SEL (1<<20)
+#define PERI_CRG47 (0xF8A22000 + 0xbc) +#define USB2_PHY01_REF_CKEN (1 << 0) +#define USB2_PHY2_REF_CKEN (1 << 2) +#define USB2_PHY01_SRST_REQ (1 << 4) +#define USB2_PHY2_SRST_REQ (1 << 6) +#define USB2_PHY01_SRST_TREQ0 (1 << 8) +#define USB2_PHY01_SRST_TREQ1 (1 << 9) +#define USB2_PHY2_SRST_TREQ (1 << 10) +#define USB2_PHY01_REFCLK_SEL (1 << 12) +#define USB2_PHY2_REFCLK_SEL (1 << 14)
+#define REG_START_MODE 0x0000 +#define REG_PERI_STAT 0x0004 +#define REG_PERI_CTRL 0x0008 +#define REG_PERI_CRG26 0x00A8 +#define NF_BOOTBW_MASK (1<<12)
+#define HI3798CV200_EHCI_CTRL (PERI_USB0)
Superfluous parenthesis.
ack
+/* Generate padding data ranges with unique identifiers. */ +#define ___cat(a,b) a##b +#define __cat(a,b) ___cat(a,b) +#define __padding(__words) struct { __u32 __cat(__pad, __COUNTER__)[__words]; }
Uh what ? Needed ?
nope....will remove the silly structure :)
+struct hi3798cv200_ehci_ctrl_regs {
- u32 peri_usb0;
- u32 peri_usb1;
- u32 peri_usb2;
- u32 peri_usb3;
- u32 peri_usb4;
- __padding(0x7e1);
- u32 peri_crg46;
- u32 peri_crg47;
Just use #define FOO_REG_BAR 0xf00 , drop this structure stuff ...
100% in agreement.
+};
+#endif diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 0bf8274..a749d0e 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -128,6 +128,12 @@ config USB_EHCI_ZYNQ ---help--- Enable support for Zynq on-chip EHCI USB controller
+config USB_EHCI_POPLAR
- bool "Support for HI3798cv200 EHCI USB controller"
Does HI stand for Hitachi ?
Hisilicon
- default y
- ---help---
Enable support for Poplar on-chip EHCI USB controller- config USB_EHCI_GENERIC bool "Support for generic EHCI USB controller" depends on OF_CONTROL
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 58c0cf5..3661636 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o +obj-$(CONFIG_USB_EHCI_POPLAR) += ehci-hi3798cv200.o
# xhci obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o diff --git a/drivers/usb/host/ehci-hi3798cv200.c b/drivers/usb/host/ehci-hi3798cv200.c new file mode 100644 index 0000000..c535de1 --- /dev/null +++ b/drivers/usb/host/ehci-hi3798cv200.c @@ -0,0 +1,196 @@ +/*
- (C) Copyright 2017 Linaro
- Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/arch/hi3798cv200.h> +#include <asm/io.h>
+#include "ehci.h"
+static struct hi3798cv200_ehci_ctrl_regs *ctrl = (void *) HI3798CV200_EHCI_CTRL;
This should use DM
it there a strong requirement for this? there a number of ehci drivers like this one already in the tree so I am just wondering if i would be possible to merge it as (just so we can focus in the network driver next).
otherwise - if you think this will be a maintenance issue for you - sure I'll start looking into it.
+static void inno_phy_config_2p_1(void) +{
- u32 reg;
- /* write 0x4 to addr 0x06
- config 2P PHY clk output
- delay 1ms for waiting PLL stable
- */
- reg = TEST_WRDATA|TEST_ADDR|TEST_WREN|TEST_RSTN;
- writel(reg, &ctrl->peri_usb0);
- reg = TEST_WRDATA|TEST_ADDR|TEST_WREN|TEST_RSTN|TEST_CLK;
- writel(reg, &ctrl->peri_usb0);
- reg = TEST_WRDATA|TEST_ADDR|TEST_WREN|TEST_RSTN;
- writel(reg, &ctrl->peri_usb0);
- mdelay(1);
- /* write 0x1c to addr 0x00
- 0x00[0] = 0 : close EOP pre-emphasis
- 0x00[2] = 1 : open Data pre-emphasis
- */
- writel(0xa1001c, &ctrl->peri_usb0);
- writel(0xe1001c, &ctrl->peri_usb0);
- writel(0xa1001c, &ctrl->peri_usb0);
- udelay(20);
- /* write 0x07 to 0x06
- {0x06[1:0],0x05[7]} = 110 : Rcomp = 150mV , increase DC level
- */
- writel(0xa00607, &ctrl->peri_usb0);
- writel(0xe00607, &ctrl->peri_usb0);
- writel(0xa00607, &ctrl->peri_usb0);
- udelay(20);
- /* write 0x00 to addr 0x07
- 0x07[1] = 0 : Keep Rcomp working
- */
- writel(0xa10700, &ctrl->peri_usb0);
- writel(0xe10700, &ctrl->peri_usb0);
- writel(0xa10700, &ctrl->peri_usb0);
- udelay(20);
- /* write 0xab to 0x0a
- 0x0a[7:5] = 101 : Icomp = 212mV , increase current drive
- */
- writel(0xa00aab, &ctrl->peri_usb0);
- writel(0xe00aab, &ctrl->peri_usb0);
- writel(0xa00aab, &ctrl->peri_usb0);
- udelay(20);
- /* write 0x40 to addr 0x11
- 0x11[6:5] = 10 : sovle EMI problem, rx_active will
- not stay at 1 when error packets received
- */
- writel(0xa11140, &ctrl->peri_usb0);
- writel(0xe11140, &ctrl->peri_usb0);
- writel(0xa11140, &ctrl->peri_usb0);
- udelay(20);
- /* write 0x41 to addr 0x10
- 0x10[0] = 1 : Comp Mode Select
- */
- writel(0xa11041, &ctrl->peri_usb0);
- writel(0xe11041, &ctrl->peri_usb0);
- writel(0xa11041, &ctrl->peri_usb0);
- udelay(20);
- /*
- {0x00a[0],0x009[7:6]} = 110 : Eye Diagram Adjust
- {0x10a[0],0x109[7:6]} = 000 : Eye Diagram Adjust
- */
- writel(0xa0098c, &ctrl->peri_usb0);
- writel(0xe0098c, &ctrl->peri_usb0);
- writel(0xa0098c, &ctrl->peri_usb0);
- writel(0xa10a0a, &ctrl->peri_usb0);
- writel(0xe10a0a, &ctrl->peri_usb0);
- writel(0xa10a0a, &ctrl->peri_usb0);
- udelay(20);
+}
+#ifndef CONFIG_DM_USB +int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)+{
- int reg;
- *hccr = (struct ehci_hccr *) REG_BASE_EHCI;
- *hcor = (struct ehci_hcor *)( (void *) REG_BASE_EHCI +
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));- /* reset controller bus/utmi/roothub */
- reg = readl(&ctrl->peri_crg46);
- reg |= (USB2_BUS_SRST_REQ
| USB2_UTMI0_SRST_REQ| USB2_HST_PHY_SYST_REQ| USB2_OTG_PHY_SYST_REQ);- writel(reg, &ctrl->peri_crg46);
- udelay(200);
Can the ulpi-phy code we have help here ? Also, clrsetbits_le32() and co ...
ack for the bit instructions. will fix. the usb-2 controller doest seem to have a ULPI phy (I couldn't find it in the device tree or in the docs but I might be wrong..I'll find out to be sure)
- /* reset phy por/utmi */
- reg = readl(&ctrl->peri_crg47);
- reg |= (USB2_PHY01_SRST_REQ
| USB2_PHY01_SRST_TREQ1);- writel(reg, &ctrl->peri_crg47);
- udelay(200);
- reg = readl(&ctrl->peri_usb3);
- reg |= ULPI_BYPASS_EN_PORT0;
- reg &= ~(WORDINTERFACE);
- reg &= ~(SS_BURST16_EN);
- writel(reg, &ctrl->peri_usb3);
- udelay(100);
- /* open ref clk */
- reg = readl(&ctrl->peri_crg47);
- reg |= (USB2_PHY01_REF_CKEN);
- writel(reg, &ctrl->peri_crg47);
- udelay(300);
- /* cancel power on reset */
- reg = readl(&ctrl->peri_crg47);
- reg &= ~(USB2_PHY01_SRST_REQ);
- writel(reg, &ctrl->peri_crg47);
- udelay(500);
- inno_phy_config_2p_1();
- /* cancel port reset
* delay 10ms for waiting comp circuit stable- */
- reg = readl(&ctrl->peri_crg47);
- reg &= ~(USB2_PHY01_SRST_TREQ1);
- writel(reg, &ctrl->peri_crg47);
- mdelay(10);
- /* open controller clk */
- reg = readl(&ctrl->peri_crg46);
- reg |= (USB2_BUS_CKEN
| USB2_OHCI48M_CKEN| USB2_OHCI12M_CKEN| USB2_OTG_UTMI_CKEN| USB2_HST_PHY_CKEN| USB2_UTMI0_CKEN);- writel(reg, &ctrl->peri_crg46);
- udelay(200);
- /* cancel control reset */
- reg = readl(&ctrl->peri_crg46);
- reg &= ~(USB2_BUS_SRST_REQ
| USB2_UTMI0_SRST_REQ| USB2_HST_PHY_SYST_REQ| USB2_OTG_PHY_SYST_REQ);- writel(reg, &ctrl->peri_crg46);
- udelay(200);
- return 0;
+}
+int ehci_hcd_stop(int index) +{
- int reg;
- reg = readl(&ctrl->peri_crg46);
- reg |= (USB2_BUS_SRST_REQ
| USB2_UTMI0_SRST_REQ| USB2_HST_PHY_SYST_REQ);- writel(reg, &ctrl->peri_crg46);
- udelay(200);
- reg = readl(&ctrl->peri_crg47);
- reg |= (USB2_PHY01_SRST_REQ
| USB2_PHY01_SRST_TREQ1);- writel(reg, &ctrl->peri_crg47);
- udelay(100);
- return 0;
+} +#else +error "CONFIG_DM_USB not supported for hi3798cv200"
+#endif
2.7.4
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
On 05/05/2017 07:55 PM, Jorge Ramirez wrote:
On 05/05/2017 05:34 PM, Marek Vasut wrote:
On 05/05/2017 04:32 PM, Tom Rini wrote:
On Thu, May 04, 2017 at 03:47:07PM +0200, Jorge Ramirez-Ortiz wrote:
CC'ing Marek...
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
.../arm/include/asm/arch-hi3798cv200/hi3798cv200.h | 93 ++++++++++ drivers/usb/host/Kconfig | 6 + drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-hi3798cv200.c | 196 +++++++++++++++++++++ 4 files changed, 296 insertions(+) create mode 100644 arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h create mode 100644 drivers/usb/host/ehci-hi3798cv200.c
diff --git a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h new file mode 100644 index 0000000..c67fda1 --- /dev/null +++ b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h @@ -0,0 +1,93 @@ +/*
- (C) Copyright 2017 Linaro
- Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __HI3798cv200_H__ +#define __HI3798cv200_H__
This should be a separate patch ..
hi Marek
to be clear, are you asking a single patch containing hi3798cv200.h?
Yes, this is arch stuff and is not in any way part of the USB driver IMO.
[...]
+};
+#endif diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 0bf8274..a749d0e 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -128,6 +128,12 @@ config USB_EHCI_ZYNQ ---help--- Enable support for Zynq on-chip EHCI USB controller +config USB_EHCI_POPLAR
- bool "Support for HI3798cv200 EHCI USB controller"
Does HI stand for Hitachi ?
Hisilicon
Don't we already have some hisilicon stuff in the tree ? Maybe some 96board ?
In fact, could this driver be replaced by ehci-generic ?
- default y
- ---help---
Enable support for Poplar on-chip EHCI USB controller- config USB_EHCI_GENERIC bool "Support for generic EHCI USB controller" depends on OF_CONTROL
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 58c0cf5..3661636 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o +obj-$(CONFIG_USB_EHCI_POPLAR) += ehci-hi3798cv200.o # xhci obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o diff --git a/drivers/usb/host/ehci-hi3798cv200.c b/drivers/usb/host/ehci-hi3798cv200.c new file mode 100644 index 0000000..c535de1 --- /dev/null +++ b/drivers/usb/host/ehci-hi3798cv200.c @@ -0,0 +1,196 @@ +/*
- (C) Copyright 2017 Linaro
- Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/arch/hi3798cv200.h> +#include <asm/io.h>
+#include "ehci.h"
+static struct hi3798cv200_ehci_ctrl_regs *ctrl = (void *) HI3798CV200_EHCI_CTRL;
This should use DM
it there a strong requirement for this?
Yes, USB is huge which means your system had enough resources. Adding DM to it doesn't hurt and makes things easier.
there a number of ehci drivers like this one already in the tree so I am just wondering if i would be possible to merge it as (just so we can focus in the network driver next).
No.
otherwise - if you think this will be a maintenance issue for you - sure I'll start looking into it.
Should be pretty easy to convert.
+static void inno_phy_config_2p_1(void) +{
- u32 reg;
- /* write 0x4 to addr 0x06
- config 2P PHY clk output
- delay 1ms for waiting PLL stable
- */
- reg = TEST_WRDATA|TEST_ADDR|TEST_WREN|TEST_RSTN;
- writel(reg, &ctrl->peri_usb0);
- reg = TEST_WRDATA|TEST_ADDR|TEST_WREN|TEST_RSTN|TEST_CLK;
- writel(reg, &ctrl->peri_usb0);
- reg = TEST_WRDATA|TEST_ADDR|TEST_WREN|TEST_RSTN;
- writel(reg, &ctrl->peri_usb0);
- mdelay(1);
- /* write 0x1c to addr 0x00
- 0x00[0] = 0 : close EOP pre-emphasis
- 0x00[2] = 1 : open Data pre-emphasis
- */
- writel(0xa1001c, &ctrl->peri_usb0);
- writel(0xe1001c, &ctrl->peri_usb0);
- writel(0xa1001c, &ctrl->peri_usb0);
- udelay(20);
- /* write 0x07 to 0x06
- {0x06[1:0],0x05[7]} = 110 : Rcomp = 150mV , increase DC level
- */
- writel(0xa00607, &ctrl->peri_usb0);
- writel(0xe00607, &ctrl->peri_usb0);
- writel(0xa00607, &ctrl->peri_usb0);
- udelay(20);
- /* write 0x00 to addr 0x07
- 0x07[1] = 0 : Keep Rcomp working
- */
- writel(0xa10700, &ctrl->peri_usb0);
- writel(0xe10700, &ctrl->peri_usb0);
- writel(0xa10700, &ctrl->peri_usb0);
- udelay(20);
- /* write 0xab to 0x0a
- 0x0a[7:5] = 101 : Icomp = 212mV , increase current drive
- */
- writel(0xa00aab, &ctrl->peri_usb0);
- writel(0xe00aab, &ctrl->peri_usb0);
- writel(0xa00aab, &ctrl->peri_usb0);
- udelay(20);
- /* write 0x40 to addr 0x11
- 0x11[6:5] = 10 : sovle EMI problem, rx_active will
- not stay at 1 when error packets received
- */
- writel(0xa11140, &ctrl->peri_usb0);
- writel(0xe11140, &ctrl->peri_usb0);
- writel(0xa11140, &ctrl->peri_usb0);
- udelay(20);
- /* write 0x41 to addr 0x10
- 0x10[0] = 1 : Comp Mode Select
- */
- writel(0xa11041, &ctrl->peri_usb0);
- writel(0xe11041, &ctrl->peri_usb0);
- writel(0xa11041, &ctrl->peri_usb0);
- udelay(20);
- /*
- {0x00a[0],0x009[7:6]} = 110 : Eye Diagram Adjust
- {0x10a[0],0x109[7:6]} = 000 : Eye Diagram Adjust
- */
- writel(0xa0098c, &ctrl->peri_usb0);
- writel(0xe0098c, &ctrl->peri_usb0);
- writel(0xa0098c, &ctrl->peri_usb0);
- writel(0xa10a0a, &ctrl->peri_usb0);
- writel(0xe10a0a, &ctrl->peri_usb0);
- writel(0xa10a0a, &ctrl->peri_usb0);
- udelay(20);
+}
+#ifndef CONFIG_DM_USB +int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)+{
- int reg;
- *hccr = (struct ehci_hccr *) REG_BASE_EHCI;
- *hcor = (struct ehci_hcor *)( (void *) REG_BASE_EHCI +
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));- /* reset controller bus/utmi/roothub */
- reg = readl(&ctrl->peri_crg46);
- reg |= (USB2_BUS_SRST_REQ
| USB2_UTMI0_SRST_REQ| USB2_HST_PHY_SYST_REQ| USB2_OTG_PHY_SYST_REQ);- writel(reg, &ctrl->peri_crg46);
- udelay(200);
Can the ulpi-phy code we have help here ? Also, clrsetbits_le32() and co ...
ack for the bit instructions. will fix. the usb-2 controller doest seem to have a ULPI phy (I couldn't find it in the device tree or in the docs but I might be wrong..I'll find out to be sure)
Please re-check , this init sequence looks weird.
- /* reset phy por/utmi */
- reg = readl(&ctrl->peri_crg47);
- reg |= (USB2_PHY01_SRST_REQ
| USB2_PHY01_SRST_TREQ1);- writel(reg, &ctrl->peri_crg47);
- udelay(200);
- reg = readl(&ctrl->peri_usb3);
- reg |= ULPI_BYPASS_EN_PORT0;
- reg &= ~(WORDINTERFACE);
- reg &= ~(SS_BURST16_EN);
- writel(reg, &ctrl->peri_usb3);
- udelay(100);
- /* open ref clk */
- reg = readl(&ctrl->peri_crg47);
- reg |= (USB2_PHY01_REF_CKEN);
- writel(reg, &ctrl->peri_crg47);
- udelay(300);
- /* cancel power on reset */
- reg = readl(&ctrl->peri_crg47);
- reg &= ~(USB2_PHY01_SRST_REQ);
- writel(reg, &ctrl->peri_crg47);
- udelay(500);
- inno_phy_config_2p_1();
- /* cancel port reset
* delay 10ms for waiting comp circuit stable- */
- reg = readl(&ctrl->peri_crg47);
- reg &= ~(USB2_PHY01_SRST_TREQ1);
- writel(reg, &ctrl->peri_crg47);
- mdelay(10);
- /* open controller clk */
- reg = readl(&ctrl->peri_crg46);
- reg |= (USB2_BUS_CKEN
| USB2_OHCI48M_CKEN| USB2_OHCI12M_CKEN| USB2_OTG_UTMI_CKEN| USB2_HST_PHY_CKEN| USB2_UTMI0_CKEN);- writel(reg, &ctrl->peri_crg46);
- udelay(200);
- /* cancel control reset */
- reg = readl(&ctrl->peri_crg46);
- reg &= ~(USB2_BUS_SRST_REQ
| USB2_UTMI0_SRST_REQ| USB2_HST_PHY_SYST_REQ| USB2_OTG_PHY_SYST_REQ);- writel(reg, &ctrl->peri_crg46);
- udelay(200);
- return 0;
+}
+int ehci_hcd_stop(int index) +{
- int reg;
- reg = readl(&ctrl->peri_crg46);
- reg |= (USB2_BUS_SRST_REQ
| USB2_UTMI0_SRST_REQ| USB2_HST_PHY_SYST_REQ);- writel(reg, &ctrl->peri_crg46);
- udelay(200);
- reg = readl(&ctrl->peri_crg47);
- reg |= (USB2_PHY01_SRST_REQ
| USB2_PHY01_SRST_TREQ1);- writel(reg, &ctrl->peri_crg47);
- udelay(100);
- return 0;
+} +#else +error "CONFIG_DM_USB not supported for hi3798cv200"
+#endif
2.7.4
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
On 05/06/2017 01:05 AM, Marek Vasut wrote:
On 05/05/2017 07:55 PM, Jorge Ramirez wrote:
On 05/05/2017 05:34 PM, Marek Vasut wrote:
On 05/05/2017 04:32 PM, Tom Rini wrote:
On Thu, May 04, 2017 at 03:47:07PM +0200, Jorge Ramirez-Ortiz wrote:
CC'ing Marek...
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
.../arm/include/asm/arch-hi3798cv200/hi3798cv200.h | 93 ++++++++++ drivers/usb/host/Kconfig | 6 + drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-hi3798cv200.c | 196 +++++++++++++++++++++ 4 files changed, 296 insertions(+) create mode 100644 arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h create mode 100644 drivers/usb/host/ehci-hi3798cv200.c
diff --git a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h new file mode 100644 index 0000000..c67fda1 --- /dev/null +++ b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h @@ -0,0 +1,93 @@ +/*
- (C) Copyright 2017 Linaro
- Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __HI3798cv200_H__ +#define __HI3798cv200_H__
This should be a separate patch ..
hi Marek
to be clear, are you asking a single patch containing hi3798cv200.h?
Yes, this is arch stuff and is not in any way part of the USB driver IMO.
sure. I suppose that what are really saying is that the usb driver has to be upstreamed after the architecture and not before if such a dependency exists (ie not using the device tree)
ok
[...]
+};
+#endif diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 0bf8274..a749d0e 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -128,6 +128,12 @@ config USB_EHCI_ZYNQ ---help--- Enable support for Zynq on-chip EHCI USB controller +config USB_EHCI_POPLAR
- bool "Support for HI3798cv200 EHCI USB controller"
Does HI stand for Hitachi ?
Hisilicon
Don't we already have some hisilicon stuff in the tree ? Maybe some 96board ?
In fact, could this driver be replaced by ehci-generic ?
yes I think so. the driver is basically platform initialization code and the generic driver. the problem I have is that there is not usb host support in the kernel for it so we dont have a device node in the tree.
should I commit the linux kernel device tree (first patch in the series) and then add the node when I push the DM usb driver?
- default y
- ---help---
Enable support for Poplar on-chip EHCI USB controller- config USB_EHCI_GENERIC bool "Support for generic EHCI USB controller" depends on OF_CONTROL
diff --git a/drivers/usb/host/Makefile b/drivers/usb/host/Makefile index 58c0cf5..3661636 100644 --- a/drivers/usb/host/Makefile +++ b/drivers/usb/host/Makefile @@ -52,6 +52,7 @@ obj-$(CONFIG_USB_EHCI_VCT) += ehci-vct.o obj-$(CONFIG_USB_EHCI_VF) += ehci-vf.o obj-$(CONFIG_USB_EHCI_RMOBILE) += ehci-rmobile.o obj-$(CONFIG_USB_EHCI_ZYNQ) += ehci-zynq.o +obj-$(CONFIG_USB_EHCI_POPLAR) += ehci-hi3798cv200.o # xhci obj-$(CONFIG_USB_XHCI_HCD) += xhci.o xhci-mem.o xhci-ring.o diff --git a/drivers/usb/host/ehci-hi3798cv200.c b/drivers/usb/host/ehci-hi3798cv200.c new file mode 100644 index 0000000..c535de1 --- /dev/null +++ b/drivers/usb/host/ehci-hi3798cv200.c @@ -0,0 +1,196 @@ +/*
- (C) Copyright 2017 Linaro
- Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <common.h> +#include <asm/arch/hi3798cv200.h> +#include <asm/io.h>
+#include "ehci.h"
+static struct hi3798cv200_ehci_ctrl_regs *ctrl = (void *) HI3798CV200_EHCI_CTRL;
This should use DM
it there a strong requirement for this?
Yes, USB is huge which means your system had enough resources. Adding DM to it doesn't hurt and makes things easier.
ok
there a number of ehci drivers like this one already in the tree so I am just wondering if i would be possible to merge it as (just so we can focus in the network driver next).
No.
otherwise - if you think this will be a maintenance issue for you - sure I'll start looking into it.
Should be pretty easy to convert.
yeah I think it is just adding a node in the tree
+static void inno_phy_config_2p_1(void) +{
- u32 reg;
- /* write 0x4 to addr 0x06
- config 2P PHY clk output
- delay 1ms for waiting PLL stable
- */
- reg = TEST_WRDATA|TEST_ADDR|TEST_WREN|TEST_RSTN;
- writel(reg, &ctrl->peri_usb0);
- reg = TEST_WRDATA|TEST_ADDR|TEST_WREN|TEST_RSTN|TEST_CLK;
- writel(reg, &ctrl->peri_usb0);
- reg = TEST_WRDATA|TEST_ADDR|TEST_WREN|TEST_RSTN;
- writel(reg, &ctrl->peri_usb0);
- mdelay(1);
- /* write 0x1c to addr 0x00
- 0x00[0] = 0 : close EOP pre-emphasis
- 0x00[2] = 1 : open Data pre-emphasis
- */
- writel(0xa1001c, &ctrl->peri_usb0);
- writel(0xe1001c, &ctrl->peri_usb0);
- writel(0xa1001c, &ctrl->peri_usb0);
- udelay(20);
- /* write 0x07 to 0x06
- {0x06[1:0],0x05[7]} = 110 : Rcomp = 150mV , increase DC level
- */
- writel(0xa00607, &ctrl->peri_usb0);
- writel(0xe00607, &ctrl->peri_usb0);
- writel(0xa00607, &ctrl->peri_usb0);
- udelay(20);
- /* write 0x00 to addr 0x07
- 0x07[1] = 0 : Keep Rcomp working
- */
- writel(0xa10700, &ctrl->peri_usb0);
- writel(0xe10700, &ctrl->peri_usb0);
- writel(0xa10700, &ctrl->peri_usb0);
- udelay(20);
- /* write 0xab to 0x0a
- 0x0a[7:5] = 101 : Icomp = 212mV , increase current drive
- */
- writel(0xa00aab, &ctrl->peri_usb0);
- writel(0xe00aab, &ctrl->peri_usb0);
- writel(0xa00aab, &ctrl->peri_usb0);
- udelay(20);
- /* write 0x40 to addr 0x11
- 0x11[6:5] = 10 : sovle EMI problem, rx_active will
- not stay at 1 when error packets received
- */
- writel(0xa11140, &ctrl->peri_usb0);
- writel(0xe11140, &ctrl->peri_usb0);
- writel(0xa11140, &ctrl->peri_usb0);
- udelay(20);
- /* write 0x41 to addr 0x10
- 0x10[0] = 1 : Comp Mode Select
- */
- writel(0xa11041, &ctrl->peri_usb0);
- writel(0xe11041, &ctrl->peri_usb0);
- writel(0xa11041, &ctrl->peri_usb0);
- udelay(20);
- /*
- {0x00a[0],0x009[7:6]} = 110 : Eye Diagram Adjust
- {0x10a[0],0x109[7:6]} = 000 : Eye Diagram Adjust
- */
- writel(0xa0098c, &ctrl->peri_usb0);
- writel(0xe0098c, &ctrl->peri_usb0);
- writel(0xa0098c, &ctrl->peri_usb0);
- writel(0xa10a0a, &ctrl->peri_usb0);
- writel(0xe10a0a, &ctrl->peri_usb0);
- writel(0xa10a0a, &ctrl->peri_usb0);
- udelay(20);
+}
+#ifndef CONFIG_DM_USB +int ehci_hcd_init(int index, enum usb_init_type init,
struct ehci_hccr **hccr, struct ehci_hcor **hcor)+{
- int reg;
- *hccr = (struct ehci_hccr *) REG_BASE_EHCI;
- *hcor = (struct ehci_hcor *)( (void *) REG_BASE_EHCI +
HC_LENGTH(ehci_readl(&(*hccr)->cr_capbase)));- /* reset controller bus/utmi/roothub */
- reg = readl(&ctrl->peri_crg46);
- reg |= (USB2_BUS_SRST_REQ
| USB2_UTMI0_SRST_REQ| USB2_HST_PHY_SYST_REQ| USB2_OTG_PHY_SYST_REQ);- writel(reg, &ctrl->peri_crg46);
- udelay(200);
Can the ulpi-phy code we have help here ? Also, clrsetbits_le32() and co ...
ack for the bit instructions. will fix. the usb-2 controller doest seem to have a ULPI phy (I couldn't find it in the device tree or in the docs but I might be wrong..I'll find out to be sure)
Please re-check , this init sequence looks weird.
ok thanks for the review
- /* reset phy por/utmi */
- reg = readl(&ctrl->peri_crg47);
- reg |= (USB2_PHY01_SRST_REQ
| USB2_PHY01_SRST_TREQ1);- writel(reg, &ctrl->peri_crg47);
- udelay(200);
- reg = readl(&ctrl->peri_usb3);
- reg |= ULPI_BYPASS_EN_PORT0;
- reg &= ~(WORDINTERFACE);
- reg &= ~(SS_BURST16_EN);
- writel(reg, &ctrl->peri_usb3);
- udelay(100);
- /* open ref clk */
- reg = readl(&ctrl->peri_crg47);
- reg |= (USB2_PHY01_REF_CKEN);
- writel(reg, &ctrl->peri_crg47);
- udelay(300);
- /* cancel power on reset */
- reg = readl(&ctrl->peri_crg47);
- reg &= ~(USB2_PHY01_SRST_REQ);
- writel(reg, &ctrl->peri_crg47);
- udelay(500);
- inno_phy_config_2p_1();
- /* cancel port reset
* delay 10ms for waiting comp circuit stable- */
- reg = readl(&ctrl->peri_crg47);
- reg &= ~(USB2_PHY01_SRST_TREQ1);
- writel(reg, &ctrl->peri_crg47);
- mdelay(10);
- /* open controller clk */
- reg = readl(&ctrl->peri_crg46);
- reg |= (USB2_BUS_CKEN
| USB2_OHCI48M_CKEN| USB2_OHCI12M_CKEN| USB2_OTG_UTMI_CKEN| USB2_HST_PHY_CKEN| USB2_UTMI0_CKEN);- writel(reg, &ctrl->peri_crg46);
- udelay(200);
- /* cancel control reset */
- reg = readl(&ctrl->peri_crg46);
- reg &= ~(USB2_BUS_SRST_REQ
| USB2_UTMI0_SRST_REQ| USB2_HST_PHY_SYST_REQ| USB2_OTG_PHY_SYST_REQ);- writel(reg, &ctrl->peri_crg46);
- udelay(200);
- return 0;
+}
+int ehci_hcd_stop(int index) +{
- int reg;
- reg = readl(&ctrl->peri_crg46);
- reg |= (USB2_BUS_SRST_REQ
| USB2_UTMI0_SRST_REQ| USB2_HST_PHY_SYST_REQ);- writel(reg, &ctrl->peri_crg46);
- udelay(200);
- reg = readl(&ctrl->peri_crg47);
- reg |= (USB2_PHY01_SRST_REQ
| USB2_PHY01_SRST_TREQ1);- writel(reg, &ctrl->peri_crg47);
- udelay(100);
- return 0;
+} +#else +error "CONFIG_DM_USB not supported for hi3798cv200"
+#endif
2.7.4
U-Boot mailing list U-Boot@lists.denx.de https://lists.denx.de/listinfo/u-boot
On 05/07/2017 12:56 PM, Jorge Ramirez wrote:
On 05/06/2017 01:05 AM, Marek Vasut wrote:
On 05/05/2017 07:55 PM, Jorge Ramirez wrote:
On 05/05/2017 05:34 PM, Marek Vasut wrote:
On 05/05/2017 04:32 PM, Tom Rini wrote:
On Thu, May 04, 2017 at 03:47:07PM +0200, Jorge Ramirez-Ortiz wrote:
CC'ing Marek...
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
.../arm/include/asm/arch-hi3798cv200/hi3798cv200.h | 93 ++++++++++ drivers/usb/host/Kconfig | 6 + drivers/usb/host/Makefile | 1 + drivers/usb/host/ehci-hi3798cv200.c | 196 +++++++++++++++++++++ 4 files changed, 296 insertions(+) create mode 100644 arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h create mode 100644 drivers/usb/host/ehci-hi3798cv200.c
diff --git a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h new file mode 100644 index 0000000..c67fda1 --- /dev/null +++ b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h @@ -0,0 +1,93 @@ +/*
- (C) Copyright 2017 Linaro
- Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef __HI3798cv200_H__ +#define __HI3798cv200_H__
This should be a separate patch ..
hi Marek
to be clear, are you asking a single patch containing hi3798cv200.h?
Yes, this is arch stuff and is not in any way part of the USB driver IMO.
sure. I suppose that what are really saying is that the usb driver has to be upstreamed after the architecture and not before if such a dependency exists (ie not using the device tree)
Yes, you can be asked to change stuff in the arch code , at which point you might have to modify the (dead, but accepted) usb code.
If you can move arch stuff to arch code, even better. Then you might even be able to use ehci-generic.
[...]
+};
+#endif diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig index 0bf8274..a749d0e 100644 --- a/drivers/usb/host/Kconfig +++ b/drivers/usb/host/Kconfig @@ -128,6 +128,12 @@ config USB_EHCI_ZYNQ ---help--- Enable support for Zynq on-chip EHCI USB controller +config USB_EHCI_POPLAR
- bool "Support for HI3798cv200 EHCI USB controller"
Does HI stand for Hitachi ?
Hisilicon
Don't we already have some hisilicon stuff in the tree ? Maybe some 96board ?
In fact, could this driver be replaced by ehci-generic ?
yes I think so. the driver is basically platform initialization code and the generic driver. the problem I have is that there is not usb host support in the kernel for it so we dont have a device node in the tree.
should I commit the linux kernel device tree (first patch in the series) and then add the node when I push the DM usb driver?
Ideally check the bindings with Rob Herring, otherwise I don't care. If you contribute to kernel too, awesome.
[...]
On 05/07/2017 02:34 PM, Marek Vasut wrote:
On 05/07/2017 12:56 PM, Jorge Ramirez wrote:
On 05/06/2017 01:05 AM, Marek Vasut wrote:
On 05/05/2017 07:55 PM, Jorge Ramirez wrote:
On 05/05/2017 05:34 PM, Marek Vasut wrote:
On 05/05/2017 04:32 PM, Tom Rini wrote:
On Thu, May 04, 2017 at 03:47:07PM +0200, Jorge Ramirez-Ortiz wrote:
CC'ing Marek...
> Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org > --- > .../arm/include/asm/arch-hi3798cv200/hi3798cv200.h | 93 > ++++++++++ > drivers/usb/host/Kconfig | 6 + > drivers/usb/host/Makefile | 1 + > drivers/usb/host/ehci-hi3798cv200.c | 196 > +++++++++++++++++++++ > 4 files changed, 296 insertions(+) > create mode 100644 > arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h > create mode 100644 drivers/usb/host/ehci-hi3798cv200.c > > diff --git a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h > b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h > new file mode 100644 > index 0000000..c67fda1 > --- /dev/null > +++ b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h > @@ -0,0 +1,93 @@ > +/* > + * (C) Copyright 2017 Linaro > + * Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org > + * > + * SPDX-License-Identifier: GPL-2.0+ > + */ > + > +#ifndef __HI3798cv200_H__ > +#define __HI3798cv200_H__
This should be a separate patch ..
hi Marek
to be clear, are you asking a single patch containing hi3798cv200.h?
Yes, this is arch stuff and is not in any way part of the USB driver IMO.
sure. I suppose that what are really saying is that the usb driver has to be upstreamed after the architecture and not before if such a dependency exists (ie not using the device tree)
Yes, you can be asked to change stuff in the arch code , at which point you might have to modify the (dead, but accepted) usb code.
If you can move arch stuff to arch code, even better. Then you might even be able to use ehci-generic.
yes, that is what I ended up doing. thanks for the suggestion.
[...]
> +}; > + > +#endif > diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig > index 0bf8274..a749d0e 100644 > --- a/drivers/usb/host/Kconfig > +++ b/drivers/usb/host/Kconfig > @@ -128,6 +128,12 @@ config USB_EHCI_ZYNQ > ---help--- > Enable support for Zynq on-chip EHCI USB controller > +config USB_EHCI_POPLAR > + bool "Support for HI3798cv200 EHCI USB controller"
Does HI stand for Hitachi ?
Hisilicon
Don't we already have some hisilicon stuff in the tree ? Maybe some 96board ?
In fact, could this driver be replaced by ehci-generic ?
yes I think so. the driver is basically platform initialization code and the generic driver. the problem I have is that there is not usb host support in the kernel for it so we dont have a device node in the tree.
should I commit the linux kernel device tree (first patch in the series) and then add the node when I push the DM usb driver?
Ideally check the bindings with Rob Herring, otherwise I don't care. If you contribute to kernel too, awesome.
in v2 I pushed the bindings to allow me to use the ehci-generic driver.
the kernel team working on this platform will push a more detailed node definition to korg - usb host is still under development - at which point I'll merge it back. I hope that this is acceptable?
[...]
On 05/08/2017 11:15 AM, Jorge Ramirez wrote:
On 05/07/2017 02:34 PM, Marek Vasut wrote:
On 05/07/2017 12:56 PM, Jorge Ramirez wrote:
On 05/06/2017 01:05 AM, Marek Vasut wrote:
On 05/05/2017 07:55 PM, Jorge Ramirez wrote:
On 05/05/2017 05:34 PM, Marek Vasut wrote:
On 05/05/2017 04:32 PM, Tom Rini wrote: > On Thu, May 04, 2017 at 03:47:07PM +0200, Jorge Ramirez-Ortiz wrote: > > CC'ing Marek... > >> Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org >> --- >> .../arm/include/asm/arch-hi3798cv200/hi3798cv200.h | 93 >> ++++++++++ >> drivers/usb/host/Kconfig | 6 + >> drivers/usb/host/Makefile | 1 + >> drivers/usb/host/ehci-hi3798cv200.c | 196 >> +++++++++++++++++++++ >> 4 files changed, 296 insertions(+) >> create mode 100644 >> arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h >> create mode 100644 drivers/usb/host/ehci-hi3798cv200.c >> >> diff --git a/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h >> b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h >> new file mode 100644 >> index 0000000..c67fda1 >> --- /dev/null >> +++ b/arch/arm/include/asm/arch-hi3798cv200/hi3798cv200.h >> @@ -0,0 +1,93 @@ >> +/* >> + * (C) Copyright 2017 Linaro >> + * Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org >> + * >> + * SPDX-License-Identifier: GPL-2.0+ >> + */ >> + >> +#ifndef __HI3798cv200_H__ >> +#define __HI3798cv200_H__ This should be a separate patch ..
hi Marek
to be clear, are you asking a single patch containing hi3798cv200.h?
Yes, this is arch stuff and is not in any way part of the USB driver IMO.
sure. I suppose that what are really saying is that the usb driver has to be upstreamed after the architecture and not before if such a dependency exists (ie not using the device tree)
Yes, you can be asked to change stuff in the arch code , at which point you might have to modify the (dead, but accepted) usb code.
If you can move arch stuff to arch code, even better. Then you might even be able to use ehci-generic.
yes, that is what I ended up doing. thanks for the suggestion.
[...]
>> +}; >> + >> +#endif >> diff --git a/drivers/usb/host/Kconfig b/drivers/usb/host/Kconfig >> index 0bf8274..a749d0e 100644 >> --- a/drivers/usb/host/Kconfig >> +++ b/drivers/usb/host/Kconfig >> @@ -128,6 +128,12 @@ config USB_EHCI_ZYNQ >> ---help--- >> Enable support for Zynq on-chip EHCI USB controller >> +config USB_EHCI_POPLAR >> + bool "Support for HI3798cv200 EHCI USB controller" Does HI stand for Hitachi ?
Hisilicon
Don't we already have some hisilicon stuff in the tree ? Maybe some 96board ?
In fact, could this driver be replaced by ehci-generic ?
yes I think so. the driver is basically platform initialization code and the generic driver. the problem I have is that there is not usb host support in the kernel for it so we dont have a device node in the tree.
should I commit the linux kernel device tree (first patch in the series) and then add the node when I push the DM usb driver?
Ideally check the bindings with Rob Herring, otherwise I don't care. If you contribute to kernel too, awesome.
in v2 I pushed the bindings to allow me to use the ehci-generic driver.
the kernel team working on this platform will push a more detailed node definition to korg - usb host is still under development - at which point I'll merge it back. I hope that this is acceptable?
Works for me if you don't invent weird stuff in the bindings and keep them reasonably in sync. Thanks
This driver is used in another board; remove board information from the driver debug log.
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org --- drivers/mmc/hi6220_dw_mmc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/drivers/mmc/hi6220_dw_mmc.c b/drivers/mmc/hi6220_dw_mmc.c index fdaf1e4..d795198 100644 --- a/drivers/mmc/hi6220_dw_mmc.c +++ b/drivers/mmc/hi6220_dw_mmc.c @@ -20,7 +20,7 @@
static int hi6220_dwmci_core_init(struct dwmci_host *host, int index) { - host->name = "HiKey DWMMC"; + host->name = "Hisilicon DWMMC";
host->dev_index = index;
On Thu, May 04, 2017 at 03:47:08PM +0200, Jorge Ramirez-Ortiz wrote:
This driver is used in another board; remove board information from the driver debug log.
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
Reviewed-by: Tom Rini trini@konsulko.com
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org --- arch/arm/include/asm/mach-types.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 9f82efe..db06923 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -5057,4 +5057,6 @@ #define MACH_TYPE_NASM25 5112 #define MACH_TYPE_TOMATO 5113 #define MACH_TYPE_OMAP3_MRC3D 5114 +#define MACH_TYPE_HI6220_HIKEY 5115 +#define MACH_TYPE_HI3798CV200_POPLAR 5116 #endif
On Thu, May 04, 2017 at 03:47:09PM +0200, Jorge Ramirez-Ortiz wrote:
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
arch/arm/include/asm/mach-types.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 9f82efe..db06923 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -5057,4 +5057,6 @@ #define MACH_TYPE_NASM25 5112 #define MACH_TYPE_TOMATO 5113 #define MACH_TYPE_OMAP3_MRC3D 5114 +#define MACH_TYPE_HI6220_HIKEY 5115 +#define MACH_TYPE_HI3798CV200_POPLAR 5116 #endif
NAK. We've recently re-synced the mach type list and there's certainly no non-DT kernel support for this board.
On 05/05/2017 04:32 PM, Tom Rini wrote:
On Thu, May 04, 2017 at 03:47:09PM +0200, Jorge Ramirez-Ortiz wrote:
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
arch/arm/include/asm/mach-types.h | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/arch/arm/include/asm/mach-types.h b/arch/arm/include/asm/mach-types.h index 9f82efe..db06923 100644 --- a/arch/arm/include/asm/mach-types.h +++ b/arch/arm/include/asm/mach-types.h @@ -5057,4 +5057,6 @@ #define MACH_TYPE_NASM25 5112 #define MACH_TYPE_TOMATO 5113 #define MACH_TYPE_OMAP3_MRC3D 5114 +#define MACH_TYPE_HI6220_HIKEY 5115 +#define MACH_TYPE_HI3798CV200_POPLAR 5116 #endif
NAK. We've recently re-synced the mach type list and there's certainly no non-DT kernel support for this board.
OK
This port adds support for: 1) Serial 2) eMMC 3) USB
It has been tested with ARM TRUSTED FIRMWARE running u-boot as the BL33 executable [see board's README]
eMMC has been tested for reading and booting the loader[1] and linux kernels as well as saving the u-boot environment.
USB has been tested with ASIX networking adapter and SanDisk 7.4GB drive.
PSCI has been tested via the reset call.
The firwmare upgrade process has been tested via TFTP and USB FAT filesystem containing the fastboot.bin image in one of the partitions.
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org --- arch/arm/Kconfig | 11 ++ arch/arm/include/asm/arch-hi3798cv200/dwmmc.h | 13 ++ board/hisilicon/poplar/Kconfig | 15 ++ board/hisilicon/poplar/MAINTAINERS | 6 + board/hisilicon/poplar/Makefile | 7 + board/hisilicon/poplar/README | 232 ++++++++++++++++++++++++++ board/hisilicon/poplar/poplar.c | 88 ++++++++++ configs/poplar_defconfig | 25 +++ include/configs/poplar.h | 113 +++++++++++++ 9 files changed, 510 insertions(+) create mode 100644 arch/arm/include/asm/arch-hi3798cv200/dwmmc.h create mode 100644 board/hisilicon/poplar/Kconfig create mode 100644 board/hisilicon/poplar/MAINTAINERS create mode 100644 board/hisilicon/poplar/Makefile create mode 100644 board/hisilicon/poplar/README create mode 100644 board/hisilicon/poplar/poplar.c create mode 100644 configs/poplar_defconfig create mode 100644 include/configs/poplar.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index 1df6b36..d4eba7c 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -816,6 +816,16 @@ config TARGET_HIKEY Support for HiKey 96boards platform. It features a HI6220 SoC, with 8xA53 CPU, mali450 gpu, and 1GB RAM.
+config TARGET_POPLAR + bool "Support Poplar 96boards Enterprise Edition Platform" + select ARM64 + select DM + select DM_SERIAL + select OF_CONTROL + help + Support for Poplar 96boards platform. It features a HI3798cv200 + SoC, with 4xA53 CPU, MaliT720 GPU, and 1GB RAM. + config TARGET_LS1012AQDS bool "Support ls1012aqds" select ARCH_LS1012A @@ -1145,6 +1155,7 @@ source "board/grinn/chiliboard/Kconfig" source "board/gumstix/pepper/Kconfig" source "board/h2200/Kconfig" source "board/hisilicon/hikey/Kconfig" +source "board/hisilicon/poplar/Kconfig" source "board/imx31_phycore/Kconfig" source "board/isee/igep0033/Kconfig" source "board/olimex/mx23_olinuxino/Kconfig" diff --git a/arch/arm/include/asm/arch-hi3798cv200/dwmmc.h b/arch/arm/include/asm/arch-hi3798cv200/dwmmc.h new file mode 100644 index 0000000..1060d94 --- /dev/null +++ b/arch/arm/include/asm/arch-hi3798cv200/dwmmc.h @@ -0,0 +1,13 @@ +/* + * (C) Copyright 2017 Linaro + * Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _HI3798cv200_DWMMC_H_ +#define _HI3798cv200_DWMMC_H_ + +int hi6220_dwmci_add_port(int index, u32 regbase, int bus_width); + +#endif /* _HI3798cv200_DWMMC_H_ */ diff --git a/board/hisilicon/poplar/Kconfig b/board/hisilicon/poplar/Kconfig new file mode 100644 index 0000000..3397295 --- /dev/null +++ b/board/hisilicon/poplar/Kconfig @@ -0,0 +1,15 @@ +if TARGET_POPLAR + +config SYS_BOARD + default "poplar" + +config SYS_VENDOR + default "hisilicon" + +config SYS_SOC + default "hi3798cv200" + +config SYS_CONFIG_NAME + default "poplar" + +endif diff --git a/board/hisilicon/poplar/MAINTAINERS b/board/hisilicon/poplar/MAINTAINERS new file mode 100644 index 0000000..0cc01c8 --- /dev/null +++ b/board/hisilicon/poplar/MAINTAINERS @@ -0,0 +1,6 @@ +Poplar BOARD +M: Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org +S: Maintained +F: board/hisilicon/poplar +F: include/configs/poplar.h +F: configs/poplar_defconfig diff --git a/board/hisilicon/poplar/Makefile b/board/hisilicon/poplar/Makefile new file mode 100644 index 0000000..101545d --- /dev/null +++ b/board/hisilicon/poplar/Makefile @@ -0,0 +1,7 @@ +# +# (C) Copyright 2017 Linaro +# Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org +# +# SPDX-License-Identifier: GPL-2.0+ +# +obj-y := poplar.o diff --git a/board/hisilicon/poplar/README b/board/hisilicon/poplar/README new file mode 100644 index 0000000..015eef6 --- /dev/null +++ b/board/hisilicon/poplar/README @@ -0,0 +1,232 @@ +================================================================================ + Board Information +================================================================================ + +Developed by HiSilicon, the board features the Hi3798C V200 with an +integrated quad-core 64-bit ARM Cortex A53 processor and high +performance Mali T720 GPU, making it capable of running any commercial +set-top solution based on Linux or Android. Its high performance +specification also supports a premium user experience with up to H.265 +HEVC decoding of 4K video at 60 frames per second. + +SOC Hisilicon Hi3798CV200 +CPU Quad-core ARM Cortex-A53 64 bit +DRAM DDR3/3L/4 SDRAM interface, maximum 32-bit data width 2 GB +USB Two USB 2.0 ports One USB 3.0 ports +CONSOLE USB-micro port for console support +ETHERNET 1 GBe Ethernet +PCIE One PCIe 2.0 interfaces +JTAG 8-Pin JTAG +EXPANSION INTERFACE Linaro 96Boards Low Speed Expansion slot +DIMENSION Standard 160×120 mm 96Boards Enterprice Edition form factor +WIFI 802.11AC 2*2 with Bluetooth +CONNECTORS One connector for Smart Card One connector for TSI + + +================================================================================ + BUILD INSTRUCTIONS +================================================================================ + +Compile from source: +==================== + +Get all the sources + + > mkdir -p ~/poplar/src ~/poplar/bin + > cd ~/poplar/src + > git clone ssh://git@dev-private-git.linaro.org/aspen/staging/l-loader.git l-loader + > git clone ssh://git@dev-private-git.linaro.org/aspen/staging/arm-trusted-firmware.git atf + > git clone ssh://git@dev-private-git.linaro.org/aspen/staging/u-boot.git u-boot + > git clone ssh://git@dev-private-git.linaro.org/aspen/tools.git + +Compile U-Boot: +=============== + + Prerequisite: + # sudo apt-get install device-tree-compiler + + > cd ~/poplar/src/u-boot + > make CROSS_COMPILE=aarch64-linux-gnu- poplar_defconfig + > make CROSS_COMPILE=aarch64-linux-gnu- + > cp u-boot.bin ~/poplar/bin + +Compile ARM Trusted Firmware (ATF): +=================================== + + > cd ~/poplar/src/atf + > make CROSS_COMPILE=aarch64-linux-gnu- all fip \ + SPD=none BL33=~/poplar/bin/u-boot.bin DEBUG=1 PLAT=hi3798cv200 + +Copy resulting binaries + > cp build/hi3798cv200/debug/bl1.bin ~/poplar/src/l-loader/atf/ + > cp build/hi3798cv200/debug/fip.bin ~/poplar/src/l-loader/atf/ + +Compile l-loader: +================= + + > cd ~/poplar/src/l-loader + > make clean + > make CROSS_COMPILE=arm-linux-gnueabi- + + Due to BootROM requiremets, rename l-loader.bin to fastboot.bin: + > cp l-loader.bin ~/poplar/bin/fastboot.bin + + +================================================================================ + FLASH INSTRUCTIONS +================================================================================ + +Two methods: + +Using USB debrick support: + Copy fastboot.bin to a FAT partition on the USB drive and reboot the + poplar board while pressing S3(usb_boot). + + The system will execute the new u-boot and boot into a shell which you + can then use to write to eMMC. + +Using U-BOOT from shell: + 1) using AXIS usb ethernet dongle and tftp + 2) using FAT formated USB drive + + +1. TFTP (USB ethernet dongle) +============================= + +Plug a USB AXIS ethernet dongle on any of the USB2 ports on the Poplar board. +Copy fastboot.bin to your tftp server. +In u-boot make sure your network is properly setup. + +Then + +=> tftp 0x30000000 fastboot.bin +starting USB... +USB0: USB EHCI 1.00 +scanning bus 0 for devices... 1 USB Device(s) found +USB1: USB EHCI 1.00 +scanning bus 1 for devices... 3 USB Device(s) found + scanning usb for storage devices... 0 Storage Device(s) found + scanning usb for ethernet devices... 1 Ethernet Device(s) found +Waiting for Ethernet connection... done. +Using asx0 device +TFTP from server 192.168.1.4; our IP address is 192.168.1.10 +Filename 'poplar/fastboot.bin'. +Load address: 0x30000000 +Loading: ################################################################# + ################################################################# + ############################################################### + 2 MiB/s +done +Bytes transferred = 983040 (f0000 hex) + +=> mmc write 0x30000000 0 0x780 + +MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK +=> reset + + +2. USING USB FAT DRIVE +======================= + +Copy fastboot.bin to any partition on a FAT32 formated usb flash drive. +Enter the uboot prompt + +=> fatls usb 0:2 + 983040 fastboot.bin + +1 file(s), 0 dir(s) + +=> fatload usb 0:2 0x30000000 fastboot.bin +reading fastboot.bin +983040 bytes read in 44 ms (21.3 MiB/s) + +=> mmc write 0x30000000 0 0x780 + +MMC write: dev # 0, block # 0, count 1920 ... 1920 blocks written: OK + + +================================================================================ + BOOT TRACE +================================================================================ + +Bootrom start +Boot Media: eMMC +Decrypt auxiliary code ...OK + +lsadc voltage min: 000000FE, max: 000000FF, aver: 000000FE, index: 00000000 + +Entry boot auxiliary code + +Auxiliary code - v1.00 +DDR code - V1.1.2 20160205 +Build: Mar 24 2016 - 17:09:44 +Reg Version: v134 +Reg Time: 2016/03/18 09:44:55 +Reg Name: hi3798cv2dmb_hi3798cv200_ddr3_2gbyte_8bitx4_4layers.reg + +Boot auxiliary code success +Bootrom success + +LOADER: Switched to aarch64 mode +LOADER: Entering ARM TRUSTED FIRMWARE +LOADER: CPU0 executes at 0x000ce000 + +INFO: BL1: 0xe1000 - 0xe7000 [size = 24576] +NOTICE: Booting Trusted Firmware +NOTICE: BL1: v1.3(debug):v1.3-372-g1ba9c60 +NOTICE: BL1: Built : 17:51:33, Apr 30 2017 +INFO: BL1: RAM 0xe1000 - 0xe7000 +INFO: BL1: Loading BL2 +INFO: Loading image id=1 at address 0xe9000 +INFO: Image id=1 loaded at address 0xe9000, size = 0x5008 +NOTICE: BL1: Booting BL2 +INFO: Entry point address = 0xe9000 +INFO: SPSR = 0x3c5 +NOTICE: BL2: v1.3(debug):v1.3-372-g1ba9c60 +NOTICE: BL2: Built : 17:51:33, Apr 30 2017 +INFO: BL2: Loading BL31 +INFO: Loading image id=3 at address 0x129000 +INFO: Image id=3 loaded at address 0x129000, size = 0x8038 +INFO: BL2: Loading BL33 +INFO: Loading image id=5 at address 0x37000000 +INFO: Image id=5 loaded at address 0x37000000, size = 0x58f17 +NOTICE: BL1: Booting BL31 +INFO: Entry point address = 0x129000 +INFO: SPSR = 0x3cd +INFO: Boot bl33 from 0x37000000 for 364311 Bytes +NOTICE: BL31: v1.3(debug):v1.3-372-g1ba9c60 +NOTICE: BL31: Built : 17:51:33, Apr 30 2017 +INFO: BL31: Initializing runtime services +INFO: BL31: Preparing for EL3 exit to normal world +INFO: Entry point address = 0x37000000 +INFO: SPSR = 0x3c9 + + +U-Boot 2017.05-rc2-00130-gd2255b0 (Apr 30 2017 - 17:51:28 +0200)poplar + +Model: HiSilicon Poplar Development Board +BOARD: Hisilicon HI3798cv200 Poplar +DRAM: 1 GiB +MMC: Hisilicon DWMMC: 0 +In: serial@f8b00000 +Out: serial@f8b00000 +Err: serial@f8b00000 +Net: Net Initialization Skipped +No ethernet found. + +Hit any key to stop autoboot: 0 +starting USB... +USB0: USB EHCI 1.00 +scanning bus 0 for devices... 1 USB Device(s) found +USB1: USB EHCI 1.00 +scanning bus 1 for devices... 4 USB Device(s) found + scanning usb for storage devices... 1 Storage Device(s) found + scanning usb for ethernet devices... 1 Ethernet Device(s) found + +USB device 0: + Device 0: Vendor: SanDisk Rev: 1.00 Prod: Cruzer Blade + Type: Removable Hard Disk + Capacity: 7632.0 MB = 7.4 GB (15630336 x 512) +... is now current device +Scanning usb 0:1... +=> diff --git a/board/hisilicon/poplar/poplar.c b/board/hisilicon/poplar/poplar.c new file mode 100644 index 0000000..448e99d --- /dev/null +++ b/board/hisilicon/poplar/poplar.c @@ -0,0 +1,88 @@ +/* + * (C) Copyright 2017 Linaro + * Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <asm/arch/hi3798cv200.h> +#include <linux/arm-smccc.h> +#include <asm/arch/dwmmc.h> +#include <asm/armv8/mmu.h> +#include <asm/io.h> +#include <usb.h> + +DECLARE_GLOBAL_DATA_PTR; + +static struct mm_region poplar_mem_map[] = { + { + .virt = 0x0UL, + .phys = 0x0UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + .virt = 0x80000000UL, + .phys = 0x80000000UL, + .size = 0x80000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + 0, + } +}; + +struct mm_region *mem_map = poplar_mem_map; + +int checkboard(void) +{ + puts("BOARD: Hisilicon HI3798cv200 Poplar\n"); + + return 0; +} + +void reset_cpu(ulong addr) +{ + psci_system_reset(); +} + +int dram_init(void) +{ + gd->ram_size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +int dram_init_banksize(void) +{ + const size_t len = DRAM_BANK_SIZE; + int i; + + for (i = 0; i < CONFIG_NR_DRAM_BANKS; i++) { + gd->bd->bi_dram[i].start = PHYS_SDRAM_1 + i * len; + gd->bd->bi_dram[i].size = len; + } + + return 0; +} + +int board_mmc_init(bd_t *bis) +{ + int ret; + + ret = hi6220_dwmci_add_port(0, REG_BASE_MMC0, 8); + if (ret) + printf("mmc init error (%d)\n", ret); + + return ret; +} + +int board_init(void) +{ + gd->bd->bi_arch_number = MACH_TYPE_HI3798CV200_POPLAR; + + return 0; +} + diff --git a/configs/poplar_defconfig b/configs/poplar_defconfig new file mode 100644 index 0000000..5bce3e8 --- /dev/null +++ b/configs/poplar_defconfig @@ -0,0 +1,25 @@ +CONFIG_ARM=y +CONFIG_TARGET_POPLAR=y +CONFIG_IDENT_STRING="poplar" +CONFIG_DEFAULT_DEVICE_TREE="hi3798cv200-poplar" +CONFIG_DISTRO_DEFAULTS=y +CONFIG_DISPLAY_CPUINFO=n +CONFIG_DISPLAY_BOARDINFO=y +CONFIG_ISO_PARTITION=n +CONFIG_MMC_DW=y +CONFIG_MMC_DW_K3=y +CONFIG_PL011_SERIAL=y +CONFIG_PSCI_RESET=y +CONFIG_USB=y +CONFIG_USB_EHCI=y +CONFIG_USB_STORAGE=y +CONFIG_USB_EHCI_HCD=y +CONFIG_USB_EHCI_POPLAR=y +CONFIG_NET=y +# CONFIG_CMD_IMLS is not set +# CONFIG_DM_USB is not set +# CONFIG_DM_GPIO is not set +CONFIG_LIB_RAND=y +CONFIG_CMD_UNZIP=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y diff --git a/include/configs/poplar.h b/include/configs/poplar.h new file mode 100644 index 0000000..fb0ca19 --- /dev/null +++ b/include/configs/poplar.h @@ -0,0 +1,113 @@ +/* + * (C) Copyright 2017 Linaro + * + * Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org + * + * Configuration for Poplar 96boards CE. Parts were derived from other ARM + * configurations. + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _POPLAR_H_ +#define _POPLAR_H_ + +#include <linux/sizes.h> + +/* network config */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_PHY_GIGE 1 +#define CONFIG_ARP_TIMEOUT 500000L +#define CONFIG_NET_RETRY_COUNT 50 +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 +#define CONFIG_SYS_RX_ETH_BUFFER 16 +#define CONFIG_NET_RANDOM_ETHADDR + +/* memory */ +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_1_SIZE 0x40000000 +#define CONFIG_NR_DRAM_BANKS 4 +#define DRAM_BANK_SIZE 0x10000000 + +/* sys */ +#define CONFIG_SYS_BOOTM_LEN 0x1400000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + 0x200000) +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x800000) +#define CONFIG_SYS_MALLOC_LEN (PHYS_SDRAM_1 + SZ_8M) + +/* must match bl33.bin load address */ +#define CONFIG_SYS_TEXT_BASE 0x37000000 + +/* generic gimer */ +#define COUNTER_FREQUENCY 19000000 + +/* generic interrupt controller definitions */ +#define GICD_BASE 0xF1001000 +#define GICC_BASE 0xF1002000 + +/* serial port PL010/PL011 */ +#define CONFIG_PL01X_SERIAL + +/* USB configuration */ +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_SYS_USB_EVENT_POLL +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX + +/* SD/MMC configuration */ +#define CONFIG_BOUNCE_BUFFER +/***************************************************************************** + * Initial environment variables + *****************************************************************************/ + +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.1.4 +#define CONFIG_GATEWAYIP 192.168.1.1 + +#define BOOT_TARGET_DEVICES(func) \ + func(USB, usb, 0) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) + +#ifndef CONFIG_SPL_BUILD +#include <config_distro_defaults.h> +#include <config_distro_bootcmd.h> +#endif + + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "loader_mmc_blknum=0x0\0" \ + "loader_mmc_nblks=0x780\0" \ + "env_mmc_blknum=0xF0000\0" \ + "env_mmc_nblks=0x80\0" \ + "kernel_addr_r=0x30000000\0" \ + "pxefile_addr_r=0x32000000\0" \ + "scriptaddr=0x32000000\0" \ + "fdt_addr_r=0x32200000\0" \ + "ramdisk_addr_r=0x32400000\0" \ + BOOTENV + + +/* Command line configuration */ +#define CONFIG_ENV_IS_IN_MMC 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_OFFSET 0xF0000 /* env_mmc_blknum */ +#define CONFIG_ENV_SIZE 0x10000 /* env_mmc_nblks bytes */ +#define CONFIG_CMD_ENV +#define CONFIG_FAT_WRITE +#define CONFIG_ENV_VARS_UBOOT_CONFIG + +/* Monitor Command Prompt */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#endif /* _POPLAR_H_ */
On 04/05/17 14:47, Jorge Ramirez-Ortiz wrote:
diff --git a/include/configs/poplar.h b/include/configs/poplar.h new file mode 100644 index 0000000..fb0ca19 --- /dev/null +++ b/include/configs/poplar.h @@ -0,0 +1,113 @@ +/*
- (C) Copyright 2017 Linaro
- Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
- Configuration for Poplar 96boards CE. Parts were derived from other ARM
- configurations.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _POPLAR_H_ +#define _POPLAR_H_
+#include <linux/sizes.h>
+/* network config */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_PHY_GIGE 1 +#define CONFIG_ARP_TIMEOUT 500000L +#define CONFIG_NET_RETRY_COUNT 50 +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 +#define CONFIG_SYS_RX_ETH_BUFFER 16 +#define CONFIG_NET_RANDOM_ETHADDR
+/* memory */ +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_1_SIZE 0x40000000 +#define CONFIG_NR_DRAM_BANKS 4 +#define DRAM_BANK_SIZE 0x10000000
+/* sys */ +#define CONFIG_SYS_BOOTM_LEN 0x1400000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + 0x200000) +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x800000) +#define CONFIG_SYS_MALLOC_LEN (PHYS_SDRAM_1 + SZ_8M)
+/* must match bl33.bin load address */ +#define CONFIG_SYS_TEXT_BASE 0x37000000
+/* generic gimer */ +#define COUNTER_FREQUENCY 19000000
+/* generic interrupt controller definitions */ +#define GICD_BASE 0xF1001000 +#define GICC_BASE 0xF1002000
+/* serial port PL010/PL011 */ +#define CONFIG_PL01X_SERIAL
+/* USB configuration */ +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_SYS_USB_EVENT_POLL +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX
+/* SD/MMC configuration */ +#define CONFIG_BOUNCE_BUFFER +/*****************************************************************************
- Initial environment variables
- *****************************************************************************/
+#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.1.4 +#define CONFIG_GATEWAYIP 192.168.1.1
+#define BOOT_TARGET_DEVICES(func) \
func(USB, usb, 0) \func(MMC, mmc, 0) \func(DHCP, dhcp, na)+#ifndef CONFIG_SPL_BUILD +#include <config_distro_defaults.h> +#include <config_distro_bootcmd.h> +#endif
+#define CONFIG_EXTRA_ENV_SETTINGS \
"loader_mmc_blknum=0x0\0" \"loader_mmc_nblks=0x780\0" \"env_mmc_blknum=0xF0000\0" \
Shouldn't this be 0x780 (i.e. a blknum rather than bytes)
"env_mmc_nblks=0x80\0" \"kernel_addr_r=0x30000000\0" \"pxefile_addr_r=0x32000000\0" \"scriptaddr=0x32000000\0" \"fdt_addr_r=0x32200000\0" \"ramdisk_addr_r=0x32400000\0" \- BOOTENV
+/* Command line configuration */ +#define CONFIG_ENV_IS_IN_MMC 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_OFFSET 0xF0000 /* env_mmc_blknum */ +#define CONFIG_ENV_SIZE 0x10000 /* env_mmc_nblks bytes */
Possibly express these are (0x780 * 512) to make absolutely explicit the relationship to the blknum/nblks values?
+#define CONFIG_CMD_ENV +#define CONFIG_FAT_WRITE +#define CONFIG_ENV_VARS_UBOOT_CONFIG
+/* Monitor Command Prompt */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#endif /* _POPLAR_H_ */
On 05/04/2017 03:59 PM, Daniel Thompson wrote:
On 04/05/17 14:47, Jorge Ramirez-Ortiz wrote:
diff --git a/include/configs/poplar.h b/include/configs/poplar.h new file mode 100644 index 0000000..fb0ca19 --- /dev/null +++ b/include/configs/poplar.h @@ -0,0 +1,113 @@ +/*
- (C) Copyright 2017 Linaro
- Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
- Configuration for Poplar 96boards CE. Parts were derived from
other ARM
- configurations.
- SPDX-License-Identifier: GPL-2.0+
- */
+#ifndef _POPLAR_H_ +#define _POPLAR_H_
+#include <linux/sizes.h>
+/* network config */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_PHY_GIGE 1 +#define CONFIG_ARP_TIMEOUT 500000L +#define CONFIG_NET_RETRY_COUNT 50 +#define CONFIG_SYS_FAULT_ECHO_LINK_DOWN 1 +#define CONFIG_SYS_RX_ETH_BUFFER 16 +#define CONFIG_NET_RANDOM_ETHADDR
+/* memory */ +#define PHYS_SDRAM_1 0x00000000 +#define PHYS_SDRAM_1_SIZE 0x40000000 +#define CONFIG_NR_DRAM_BANKS 4 +#define DRAM_BANK_SIZE 0x10000000
+/* sys */ +#define CONFIG_SYS_BOOTM_LEN 0x1400000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x100000 +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (PHYS_SDRAM_1 + 0x200000) +#define CONFIG_SYS_LOAD_ADDR (PHYS_SDRAM_1 + 0x800000) +#define CONFIG_SYS_MALLOC_LEN (PHYS_SDRAM_1 + SZ_8M)
+/* must match bl33.bin load address */ +#define CONFIG_SYS_TEXT_BASE 0x37000000
+/* generic gimer */ +#define COUNTER_FREQUENCY 19000000
+/* generic interrupt controller definitions */ +#define GICD_BASE 0xF1001000 +#define GICC_BASE 0xF1002000
+/* serial port PL010/PL011 */ +#define CONFIG_PL01X_SERIAL
+/* USB configuration */ +#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 3 +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_SYS_USB_EVENT_POLL +#define CONFIG_USB_ETHER_SMSC95XX +#define CONFIG_USB_HOST_ETHER +#define CONFIG_USB_ETHER_ASIX
+/* SD/MMC configuration */ +#define CONFIG_BOUNCE_BUFFER +/*****************************************************************************
- Initial environment variables
*****************************************************************************/
+#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_SERVERIP 192.168.1.4 +#define CONFIG_GATEWAYIP 192.168.1.1
+#define BOOT_TARGET_DEVICES(func) \
func(USB, usb, 0) \func(MMC, mmc, 0) \func(DHCP, dhcp, na)+#ifndef CONFIG_SPL_BUILD +#include <config_distro_defaults.h> +#include <config_distro_bootcmd.h> +#endif
+#define CONFIG_EXTRA_ENV_SETTINGS \
"loader_mmc_blknum=0x0\0" \"loader_mmc_nblks=0x780\0" \"env_mmc_blknum=0xF0000\0" \Shouldn't this be 0x780 (i.e. a blknum rather than bytes)
yes!
- "env_mmc_nblks=0x80\0" \
"kernel_addr_r=0x30000000\0" \"pxefile_addr_r=0x32000000\0" \"scriptaddr=0x32000000\0" \"fdt_addr_r=0x32200000\0" \"ramdisk_addr_r=0x32400000\0" \- BOOTENV
+/* Command line configuration */ +#define CONFIG_ENV_IS_IN_MMC 1 +#define CONFIG_SYS_MMC_ENV_DEV 0 +#define CONFIG_ENV_OFFSET 0xF0000 /* env_mmc_blknum */ +#define CONFIG_ENV_SIZE 0x10000 /* env_mmc_nblks bytes */
Possibly express these are (0x780 * 512) to make absolutely explicit the relationship to the blknum/nblks values?
OK.
+#define CONFIG_CMD_ENV +#define CONFIG_FAT_WRITE +#define CONFIG_ENV_VARS_UBOOT_CONFIG
+/* Monitor Command Prompt */ +#define CONFIG_CMDLINE_EDITING +#define CONFIG_SYS_LONGHELP +#define CONFIG_SYS_CBSIZE 512 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
sizeof(CONFIG_SYS_PROMPT) + 16)+#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
+#endif /* _POPLAR_H_ */
On Thu, May 04, 2017 at 03:47:10PM +0200, Jorge Ramirez-Ortiz wrote:
[snip]
These are private repositories, no one else can clone from them. Please push this somewhere public.
+int dram_init(void) +{
- gd->ram_size = PHYS_SDRAM_1_SIZE;
Please use get_ram_size(...) here. Thanks!
On 05/05/2017 04:32 PM, Tom Rini wrote:
On Thu, May 04, 2017 at 03:47:10PM +0200, Jorge Ramirez-Ortiz wrote:
[snip]
These are private repositories, no one else can clone from them. Please push this somewhere public.
ACK
+int dram_init(void) +{
- gd->ram_size = PHYS_SDRAM_1_SIZE;
Please use get_ram_size(...) here. Thanks!
yeah, much nicer. thanks!
On Thu, May 04, 2017 at 03:47:06PM +0200, Jorge Ramirez-Ortiz wrote:
Signed-off-by: Jorge Ramirez-Ortiz jorge.ramirez-ortiz@linaro.org
arch/arm/dts/hi3798cv200-poplar.dts | 169 +++++++++++++ arch/arm/dts/hi3798cv200.dtsi | 413 ++++++++++++++++++++++++++++++++ include/dt-bindings/clock/histb-clock.h | 66 +++++ include/dt-bindings/reset/ti-syscon.h | 38 +++ 4 files changed, 686 insertions(+) create mode 100644 arch/arm/dts/hi3798cv200-poplar.dts create mode 100644 arch/arm/dts/hi3798cv200.dtsi create mode 100644 include/dt-bindings/clock/histb-clock.h create mode 100644 include/dt-bindings/reset/ti-syscon.h
Is this just a straight copy from the Linux Kernel? If so, what release / tag? Thanks!
participants (5)
-
Daniel Thompson -
Jorge Ramirez -
Jorge Ramirez-Ortiz
-
Marek Vasut -
Tom Rini