[U-Boot] [PATCH 1/2] ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S
From: Wang Dongsheng dongsheng.wang@freescale.com
timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted completely into a reusable armv7 generic timer. LS1021A will use it as well.
Signed-off-by: Wang Dongsheng dongsheng.wang@freescale.com
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S index d4cb51e..4ff46e4 100644 --- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S +++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S @@ -18,6 +18,8 @@ */
#include <config.h> + +#include <asm/arch-armv7/generictimer.h> #include <asm/gic.h> #include <asm/macro.h> #include <asm/psci.h> @@ -43,26 +45,6 @@ #define GICD_BASE 0x1c81000 #define GICC_BASE 0x1c82000
-.macro timer_wait reg, ticks - @ Program CNTP_TVAL - movw \reg, #(\ticks & 0xffff) - movt \reg, #(\ticks >> 16) - mcr p15, 0, \reg, c14, c2, 0 - isb - @ Enable physical timer, mask interrupt - mov \reg, #3 - mcr p15, 0, \reg, c14, c2, 1 - @ Poll physical timer until ISTATUS is on -1: isb - mrc p15, 0, \reg, c14, c2, 1 - ands \reg, \reg, #4 - bne 1b - @ Disable timer - mov \reg, #0 - mcr p15, 0, \reg, c14, c2, 1 - isb -.endm - .globl psci_fiq_enter psci_fiq_enter: push {r0-r12} diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S index bbfeec8..e15d587 100644 --- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S +++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S @@ -18,6 +18,8 @@ */
#include <config.h> + +#include <asm/arch-armv7/generictimer.h> #include <asm/gic.h> #include <asm/macro.h> #include <asm/psci.h> @@ -43,26 +45,6 @@ #define GICD_BASE 0x1c81000 #define GICC_BASE 0x1c82000
-.macro timer_wait reg, ticks - @ Program CNTP_TVAL - movw \reg, #(\ticks & 0xffff) - movt \reg, #(\ticks >> 16) - mcr p15, 0, \reg, c14, c2, 0 - isb - @ Enable physical timer, mask interrupt - mov \reg, #3 - mcr p15, 0, \reg, c14, c2, 1 - @ Poll physical timer until ISTATUS is on -1: isb - mrc p15, 0, \reg, c14, c2, 1 - ands \reg, \reg, #4 - bne 1b - @ Disable timer - mov \reg, #0 - mcr p15, 0, \reg, c14, c2, 1 - isb -.endm - .globl psci_fiq_enter psci_fiq_enter: push {r0-r12} diff --git a/arch/arm/include/asm/arch-armv7/generictimer.h b/arch/arm/include/asm/arch-armv7/generictimer.h new file mode 100644 index 0000000..0956d7c --- /dev/null +++ b/arch/arm/include/asm/arch-armv7/generictimer.h @@ -0,0 +1,50 @@ +/* + * Copyright (C) 2013 - ARM Ltd + * Author: Marc Zyngier marc.zyngier@arm.com + * + * Based on code by Carl van Schaik carl@ok-labs.com. + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License version 2 as + * published by the Free Software Foundation. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program. If not, see http://www.gnu.org/licenses/. + */ + +#ifndef _GENERICTIMER_H_ +#define _GENERICTIMER_H_ + +#ifdef __ASSEMBLY__ + +/* + * This macro provide a physical timer that can be used for delay in the code. + * The macro is moved from sunxi/psci_sun7i.S + * + * reg: is used in this macro. + * ticks: The freq is based on generic timer. + */ +.macro timer_wait reg, ticks + movw \reg, #(\ticks & 0xffff) + movt \reg, #(\ticks >> 16) + mcr p15, 0, \reg, c14, c2, 0 + isb + mov \reg, #3 + mcr p15, 0, \reg, c14, c2, 1 +1 : isb + mrc p15, 0, \reg, c14, c2, 1 + ands \reg, \reg, #4 + bne 1b + mov \reg, #0 + mcr p15, 0, \reg, c14, c2, 1 + isb +.endm + +#endif /* __ASSEMBLY__ */ + +#endif /* _GENERICTIMER_H_ */
From: Wang Dongsheng dongsheng.wang@freescale.com
Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform.
Tested on LS1021AQDS, LS1021ATWR. Test CPU hotplug times: 60K Test kernel boot times: 1.2K
Signed-off-by: Wang Dongsheng dongsheng.wang@freescale.com
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index 2e6a207..2d55782 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -12,3 +12,7 @@ obj-y += fsl_epu.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o obj-$(CONFIG_SPL) += spl.o + +ifdef CONFIG_ARMV7_PSCI +obj-y += psci.o +endif diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S new file mode 100644 index 0000000..cf5cd48 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/psci.S @@ -0,0 +1,126 @@ +/* + * Copyright 2015 Freescale Semiconductor, Inc. + * Author: Wang Dongsheng dongsheng.wang@freescale.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <config.h> +#include <linux/linkage.h> + +#include <asm/armv7.h> +#include <asm/arch-armv7/generictimer.h> +#include <asm/psci.h> + +#define SCFG_CORE0_SFT_RST 0x130 +#define SCFG_CORESRENCR 0x204 + +#define DCFG_CCSR_BRR 0x0E4 +#define DCFG_CCSR_SCRATCHRW1 0x200 + + .pushsection ._secure.text, "ax" + + .arch_extension sec + +#define ONE_MS (GENERIC_TIMER_CLK / 1000) +#define RESET_WAIT (30 * ONE_MS) + + @ r1 = target CPU + @ r2 = target PC +.globl psci_cpu_on +psci_cpu_on: + push {lr} + + @ Clear and Get the correct CPU number + @ r1 = 0xf01 + and r1, r1, #0xff + + mov r0, r1 + bl psci_get_cpu_stack_top + str r2, [r0] + dsb + + @ Get DCFG base address + movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff) + movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16) + + @ Detect target CPU state + ldr r2, [r4, #DCFG_CCSR_BRR] + rev r2, r2 + lsr r2, r2, r1 + ands r2, r2, #1 + beq holdoff_release + + @ Reset target CPU + @ Get SCFG base address + movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff) + movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16) + + @ Enable CORE Soft Reset + movw r5, #0 + movt r5, #(1 << 15) + rev r5, r5 + str r5, [r0, #SCFG_CORESRENCR] + + @ Get CPUx offset register + mov r6, #0x4 + mul r6, r6, r1 + add r2, r0, r6 + + @ Do reset on target CPU + movw r5, #0 + movt r5, #(1 << 15) + rev r5, r5 + str r5, [r2, #SCFG_CORE0_SFT_RST] + + @ Wait target CPU up + timer_wait r2, RESET_WAIT + + @ Disable CORE soft reset + mov r5, #0 + str r5, [r0, #SCFG_CORESRENCR] + +holdoff_release: + @ Release on target CPU + ldr r2, [r4, #DCFG_CCSR_BRR] + mov r6, #1 + lsl r6, r6, r1 @ 32 bytes per CPU + + rev r6, r6 + orr r2, r2, r6 + str r2, [r4, #DCFG_CCSR_BRR] + + @ Set secondary boot entry + ldr r6, =psci_cpu_entry + rev r6, r6 + str r6, [r4, #DCFG_CCSR_SCRATCHRW1] + + isb + dsb + + @ Return + mov r0, #ARM_PSCI_RET_SUCCESS + + pop {lr} + bx lr + +.globl psci_cpu_off +psci_cpu_off: + bl psci_cpu_off_common + +1: wfi + b 1b + +.globl psci_arch_init +psci_arch_init: + mov r6, lr + + bl psci_get_cpu_id + bl psci_get_cpu_stack_top + mov sp, r0 + + bx r6 + + .globl psci_text_end +psci_text_end: + .popsection diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index ca913b0..7232cd9 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -11,6 +11,8 @@
#define CONFIG_LS102XA
+#define CONFIG_ARMV7_PSCI + #define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 6b6f2ba..b618be5 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -11,6 +11,8 @@
#define CONFIG_LS102XA
+#define CONFIG_ARMV7_PSCI + #define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_CPUINFO
Should be marked for V2 version.
*V2*: Nothing has changed.
Regards, -Dongsheng
-----Original Message----- From: Dongsheng Wang [mailto:dongsheng.wang@freescale.com] Sent: Thursday, June 04, 2015 12:01 PM To: Sun York-R58495 Cc: ijc@hellion.org.uk; hdegoede@redhat.com; albert.u.boot@aribaud.net; jan.kiszka@siemens.com; Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui- B35336; u-boot@lists.denx.de; Wang Dongsheng-B40534 Subject: [PATCH 2/2] arm/ls102xa: Add PSCI support for ls102xa
From: Wang Dongsheng dongsheng.wang@freescale.com
Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform.
Tested on LS1021AQDS, LS1021ATWR. Test CPU hotplug times: 60K Test kernel boot times: 1.2K
Signed-off-by: Wang Dongsheng dongsheng.wang@freescale.com
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index 2e6a207..2d55782 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -12,3 +12,7 @@ obj-y += fsl_epu.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o obj-$(CONFIG_SPL) += spl.o
+ifdef CONFIG_ARMV7_PSCI +obj-y += psci.o +endif diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S new file mode 100644 index 0000000..cf5cd48 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/psci.S @@ -0,0 +1,126 @@ +/*
- Copyright 2015 Freescale Semiconductor, Inc.
- Author: Wang Dongsheng dongsheng.wang@freescale.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <config.h> +#include <linux/linkage.h>
+#include <asm/armv7.h> +#include <asm/arch-armv7/generictimer.h> #include <asm/psci.h>
+#define SCFG_CORE0_SFT_RST 0x130 +#define SCFG_CORESRENCR 0x204
+#define DCFG_CCSR_BRR 0x0E4 +#define DCFG_CCSR_SCRATCHRW1 0x200
- .pushsection ._secure.text, "ax"
- .arch_extension sec
+#define ONE_MS (GENERIC_TIMER_CLK / 1000) +#define RESET_WAIT (30 * ONE_MS)
- @ r1 = target CPU
- @ r2 = target PC
+.globl psci_cpu_on +psci_cpu_on:
- push {lr}
- @ Clear and Get the correct CPU number
- @ r1 = 0xf01
- and r1, r1, #0xff
- mov r0, r1
- bl psci_get_cpu_stack_top
- str r2, [r0]
- dsb
- @ Get DCFG base address
- movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
- movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
- @ Detect target CPU state
- ldr r2, [r4, #DCFG_CCSR_BRR]
- rev r2, r2
- lsr r2, r2, r1
- ands r2, r2, #1
- beq holdoff_release
- @ Reset target CPU
- @ Get SCFG base address
- movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
- movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
- @ Enable CORE Soft Reset
- movw r5, #0
- movt r5, #(1 << 15)
- rev r5, r5
- str r5, [r0, #SCFG_CORESRENCR]
- @ Get CPUx offset register
- mov r6, #0x4
- mul r6, r6, r1
- add r2, r0, r6
- @ Do reset on target CPU
- movw r5, #0
- movt r5, #(1 << 15)
- rev r5, r5
- str r5, [r2, #SCFG_CORE0_SFT_RST]
- @ Wait target CPU up
- timer_wait r2, RESET_WAIT
- @ Disable CORE soft reset
- mov r5, #0
- str r5, [r0, #SCFG_CORESRENCR]
+holdoff_release:
- @ Release on target CPU
- ldr r2, [r4, #DCFG_CCSR_BRR]
- mov r6, #1
- lsl r6, r6, r1 @ 32 bytes per CPU
- rev r6, r6
- orr r2, r2, r6
- str r2, [r4, #DCFG_CCSR_BRR]
- @ Set secondary boot entry
- ldr r6, =psci_cpu_entry
- rev r6, r6
- str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
- isb
- dsb
- @ Return
- mov r0, #ARM_PSCI_RET_SUCCESS
- pop {lr}
- bx lr
+.globl psci_cpu_off +psci_cpu_off:
- bl psci_cpu_off_common
+1: wfi
- b 1b
+.globl psci_arch_init +psci_arch_init:
- mov r6, lr
- bl psci_get_cpu_id
- bl psci_get_cpu_stack_top
- mov sp, r0
- bx r6
- .globl psci_text_end
+psci_text_end:
- .popsection
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index ca913b0..7232cd9 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -11,6 +11,8 @@
#define CONFIG_LS102XA
+#define CONFIG_ARMV7_PSCI
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 6b6f2ba..b618be5 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -11,6 +11,8 @@
#define CONFIG_LS102XA
+#define CONFIG_ARMV7_PSCI
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_CPUINFO
2.1.0.27.g96db324
Hi York,
Could you ACK this patch?
Regards, -Dongsheng
-----Original Message----- From: Wang Dongsheng-B40534 Sent: Thursday, June 04, 2015 12:18 PM To: Wang Dongsheng-B40534; Sun York-R58495 Cc: ijc@hellion.org.uk; hdegoede@redhat.com; albert.u.boot@aribaud.net; jan.kiszka@siemens.com; Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui- B35336; u-boot@lists.denx.de Subject: RE: [PATCH 2/2] arm/ls102xa: Add PSCI support for ls102xa
Should be marked for V2 version.
*V2*: Nothing has changed.
Regards, -Dongsheng
-----Original Message----- From: Dongsheng Wang [mailto:dongsheng.wang@freescale.com] Sent: Thursday, June 04, 2015 12:01 PM To: Sun York-R58495 Cc: ijc@hellion.org.uk; hdegoede@redhat.com; albert.u.boot@aribaud.net; jan.kiszka@siemens.com; Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui- B35336; u-boot@lists.denx.de; Wang Dongsheng-B40534 Subject: [PATCH 2/2] arm/ls102xa: Add PSCI support for ls102xa
From: Wang Dongsheng dongsheng.wang@freescale.com
Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform.
Tested on LS1021AQDS, LS1021ATWR. Test CPU hotplug times: 60K Test kernel boot times: 1.2K
Signed-off-by: Wang Dongsheng dongsheng.wang@freescale.com
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index 2e6a207..2d55782 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -12,3 +12,7 @@ obj-y += fsl_epu.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o obj-$(CONFIG_SPL) += spl.o
+ifdef CONFIG_ARMV7_PSCI +obj-y += psci.o +endif diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S new file mode 100644 index 0000000..cf5cd48 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/psci.S @@ -0,0 +1,126 @@ +/*
- Copyright 2015 Freescale Semiconductor, Inc.
- Author: Wang Dongsheng dongsheng.wang@freescale.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <config.h> +#include <linux/linkage.h>
+#include <asm/armv7.h> +#include <asm/arch-armv7/generictimer.h> #include <asm/psci.h>
+#define SCFG_CORE0_SFT_RST 0x130 +#define SCFG_CORESRENCR 0x204
+#define DCFG_CCSR_BRR 0x0E4 +#define DCFG_CCSR_SCRATCHRW1 0x200
- .pushsection ._secure.text, "ax"
- .arch_extension sec
+#define ONE_MS (GENERIC_TIMER_CLK / 1000) +#define RESET_WAIT (30 * ONE_MS)
- @ r1 = target CPU
- @ r2 = target PC
+.globl psci_cpu_on +psci_cpu_on:
- push {lr}
- @ Clear and Get the correct CPU number
- @ r1 = 0xf01
- and r1, r1, #0xff
- mov r0, r1
- bl psci_get_cpu_stack_top
- str r2, [r0]
- dsb
- @ Get DCFG base address
- movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
- movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
- @ Detect target CPU state
- ldr r2, [r4, #DCFG_CCSR_BRR]
- rev r2, r2
- lsr r2, r2, r1
- ands r2, r2, #1
- beq holdoff_release
- @ Reset target CPU
- @ Get SCFG base address
- movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
- movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
- @ Enable CORE Soft Reset
- movw r5, #0
- movt r5, #(1 << 15)
- rev r5, r5
- str r5, [r0, #SCFG_CORESRENCR]
- @ Get CPUx offset register
- mov r6, #0x4
- mul r6, r6, r1
- add r2, r0, r6
- @ Do reset on target CPU
- movw r5, #0
- movt r5, #(1 << 15)
- rev r5, r5
- str r5, [r2, #SCFG_CORE0_SFT_RST]
- @ Wait target CPU up
- timer_wait r2, RESET_WAIT
- @ Disable CORE soft reset
- mov r5, #0
- str r5, [r0, #SCFG_CORESRENCR]
+holdoff_release:
- @ Release on target CPU
- ldr r2, [r4, #DCFG_CCSR_BRR]
- mov r6, #1
- lsl r6, r6, r1 @ 32 bytes per CPU
- rev r6, r6
- orr r2, r2, r6
- str r2, [r4, #DCFG_CCSR_BRR]
- @ Set secondary boot entry
- ldr r6, =psci_cpu_entry
- rev r6, r6
- str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
- isb
- dsb
- @ Return
- mov r0, #ARM_PSCI_RET_SUCCESS
- pop {lr}
- bx lr
+.globl psci_cpu_off +psci_cpu_off:
- bl psci_cpu_off_common
+1: wfi
- b 1b
+.globl psci_arch_init +psci_arch_init:
- mov r6, lr
- bl psci_get_cpu_id
- bl psci_get_cpu_stack_top
- mov sp, r0
- bx r6
- .globl psci_text_end
+psci_text_end:
- .popsection
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index ca913b0..7232cd9 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -11,6 +11,8 @@
#define CONFIG_LS102XA
+#define CONFIG_ARMV7_PSCI
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 6b6f2ba..b618be5 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -11,6 +11,8 @@
#define CONFIG_LS102XA
+#define CONFIG_ARMV7_PSCI
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_CPUINFO
2.1.0.27.g96db324
Hi Alison,
Could you ACK this patch? If there is not feedback.
Regards, -Dongsheng
-----Original Message----- From: U-Boot [mailto:u-boot-bounces@lists.denx.de] On Behalf Of Wang Dongsheng Sent: Tuesday, July 14, 2015 3:14 PM To: Sun York-R58495 Cc: Wang Huan-B18965; u-boot@lists.denx.de; jan.kiszka@siemens.com; ijc@hellion.org.uk Subject: Re: [U-Boot] [PATCH 2/2] arm/ls102xa: Add PSCI support for ls102xa
Hi York,
Could you ACK this patch?
Regards, -Dongsheng
-----Original Message----- From: Wang Dongsheng-B40534 Sent: Thursday, June 04, 2015 12:18 PM To: Wang Dongsheng-B40534; Sun York-R58495 Cc: ijc@hellion.org.uk; hdegoede@redhat.com; albert.u.boot@aribaud.net; jan.kiszka@siemens.com; Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui- B35336; u-boot@lists.denx.de Subject: RE: [PATCH 2/2] arm/ls102xa: Add PSCI support for ls102xa
Should be marked for V2 version.
*V2*: Nothing has changed.
Regards, -Dongsheng
-----Original Message----- From: Dongsheng Wang [mailto:dongsheng.wang@freescale.com] Sent: Thursday, June 04, 2015 12:01 PM To: Sun York-R58495 Cc: ijc@hellion.org.uk; hdegoede@redhat.com; albert.u.boot@aribaud.net; jan.kiszka@siemens.com; Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui- B35336; u-boot@lists.denx.de; Wang Dongsheng-B40534 Subject: [PATCH 2/2] arm/ls102xa: Add PSCI support for ls102xa
From: Wang Dongsheng dongsheng.wang@freescale.com
Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform.
Tested on LS1021AQDS, LS1021ATWR. Test CPU hotplug times: 60K Test kernel boot times: 1.2K
Signed-off-by: Wang Dongsheng dongsheng.wang@freescale.com
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index 2e6a207..2d55782 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -12,3 +12,7 @@ obj-y += fsl_epu.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o ls102xa_serdes.o obj-$(CONFIG_SPL) += spl.o
+ifdef CONFIG_ARMV7_PSCI +obj-y += psci.o +endif diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S new file mode 100644 index 0000000..cf5cd48 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/psci.S @@ -0,0 +1,126 @@ +/*
- Copyright 2015 Freescale Semiconductor, Inc.
- Author: Wang Dongsheng dongsheng.wang@freescale.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <config.h> +#include <linux/linkage.h>
+#include <asm/armv7.h> +#include <asm/arch-armv7/generictimer.h> #include <asm/psci.h>
+#define SCFG_CORE0_SFT_RST 0x130 +#define SCFG_CORESRENCR 0x204
+#define DCFG_CCSR_BRR 0x0E4 +#define DCFG_CCSR_SCRATCHRW1 0x200
- .pushsection ._secure.text, "ax"
- .arch_extension sec
+#define ONE_MS (GENERIC_TIMER_CLK / 1000) +#define RESET_WAIT (30 * ONE_MS)
- @ r1 = target CPU
- @ r2 = target PC
+.globl psci_cpu_on +psci_cpu_on:
- push {lr}
- @ Clear and Get the correct CPU number
- @ r1 = 0xf01
- and r1, r1, #0xff
- mov r0, r1
- bl psci_get_cpu_stack_top
- str r2, [r0]
- dsb
- @ Get DCFG base address
- movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
- movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
- @ Detect target CPU state
- ldr r2, [r4, #DCFG_CCSR_BRR]
- rev r2, r2
- lsr r2, r2, r1
- ands r2, r2, #1
- beq holdoff_release
- @ Reset target CPU
- @ Get SCFG base address
- movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
- movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
- @ Enable CORE Soft Reset
- movw r5, #0
- movt r5, #(1 << 15)
- rev r5, r5
- str r5, [r0, #SCFG_CORESRENCR]
- @ Get CPUx offset register
- mov r6, #0x4
- mul r6, r6, r1
- add r2, r0, r6
- @ Do reset on target CPU
- movw r5, #0
- movt r5, #(1 << 15)
- rev r5, r5
- str r5, [r2, #SCFG_CORE0_SFT_RST]
- @ Wait target CPU up
- timer_wait r2, RESET_WAIT
- @ Disable CORE soft reset
- mov r5, #0
- str r5, [r0, #SCFG_CORESRENCR]
+holdoff_release:
- @ Release on target CPU
- ldr r2, [r4, #DCFG_CCSR_BRR]
- mov r6, #1
- lsl r6, r6, r1 @ 32 bytes per CPU
- rev r6, r6
- orr r2, r2, r6
- str r2, [r4, #DCFG_CCSR_BRR]
- @ Set secondary boot entry
- ldr r6, =psci_cpu_entry
- rev r6, r6
- str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
- isb
- dsb
- @ Return
- mov r0, #ARM_PSCI_RET_SUCCESS
- pop {lr}
- bx lr
+.globl psci_cpu_off +psci_cpu_off:
- bl psci_cpu_off_common
+1: wfi
- b 1b
+.globl psci_arch_init +psci_arch_init:
- mov r6, lr
- bl psci_get_cpu_id
- bl psci_get_cpu_stack_top
- mov sp, r0
- bx r6
- .globl psci_text_end
+psci_text_end:
- .popsection
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index ca913b0..7232cd9 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -11,6 +11,8 @@
#define CONFIG_LS102XA
+#define CONFIG_ARMV7_PSCI
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 6b6f2ba..b618be5 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -11,6 +11,8 @@
#define CONFIG_LS102XA
+#define CONFIG_ARMV7_PSCI
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_CPUINFO
2.1.0.27.g96db324
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Hi, dongsheng,
It looks ok for me.
Acked-by: Alison Wang alison.wang@freescale.com
Best Regards, Alison Wang
-----Original Message----- From: Wang Dongsheng-B40534 Sent: Wednesday, July 15, 2015 10:11 AM To: Wang Huan-B18965; Kushwaha Prabhakar-B32579 Cc: Wang Huan-B18965; u-boot@lists.denx.de; jan.kiszka@siemens.com; ijc@hellion.org.uk; Sun York-R58495 Subject: RE: [PATCH 2/2] arm/ls102xa: Add PSCI support for ls102xa
Hi Alison,
Could you ACK this patch? If there is not feedback.
Regards, -Dongsheng
-----Original Message----- From: U-Boot [mailto:u-boot-bounces@lists.denx.de] On Behalf Of Wang Dongsheng Sent: Tuesday, July 14, 2015 3:14 PM To: Sun York-R58495 Cc: Wang Huan-B18965; u-boot@lists.denx.de; jan.kiszka@siemens.com; ijc@hellion.org.uk Subject: Re: [U-Boot] [PATCH 2/2] arm/ls102xa: Add PSCI support for ls102xa
Hi York,
Could you ACK this patch?
Regards, -Dongsheng
-----Original Message----- From: Wang Dongsheng-B40534 Sent: Thursday, June 04, 2015 12:18 PM To: Wang Dongsheng-B40534; Sun York-R58495 Cc: ijc@hellion.org.uk; hdegoede@redhat.com; albert.u.boot@aribaud.net; jan.kiszka@siemens.com; Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui- B35336; u-boot@lists.denx.de Subject: RE: [PATCH 2/2] arm/ls102xa: Add PSCI support for ls102xa
Should be marked for V2 version.
*V2*: Nothing has changed.
Regards, -Dongsheng
-----Original Message----- From: Dongsheng Wang [mailto:dongsheng.wang@freescale.com] Sent: Thursday, June 04, 2015 12:01 PM To: Sun York-R58495 Cc: ijc@hellion.org.uk; hdegoede@redhat.com; albert.u.boot@aribaud.net; jan.kiszka@siemens.com; Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui- B35336; u-boot@lists.denx.de; Wang Dongsheng-B40534 Subject: [PATCH 2/2] arm/ls102xa: Add PSCI support for ls102xa
From: Wang Dongsheng dongsheng.wang@freescale.com
Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa
platform.
Tested on LS1021AQDS, LS1021ATWR. Test CPU hotplug times: 60K Test kernel boot times: 1.2K
Signed-off-by: Wang Dongsheng dongsheng.wang@freescale.com
diff --git a/arch/arm/cpu/armv7/ls102xa/Makefile b/arch/arm/cpu/armv7/ls102xa/Makefile index 2e6a207..2d55782 100644 --- a/arch/arm/cpu/armv7/ls102xa/Makefile +++ b/arch/arm/cpu/armv7/ls102xa/Makefile @@ -12,3 +12,7 @@ obj-y += fsl_epu.o obj-$(CONFIG_OF_LIBFDT) += fdt.o obj-$(CONFIG_SYS_HAS_SERDES) += fsl_ls1_serdes.o
ls102xa_serdes.o
obj-$(CONFIG_SPL) += spl.o
+ifdef CONFIG_ARMV7_PSCI +obj-y += psci.o +endif diff --git a/arch/arm/cpu/armv7/ls102xa/psci.S b/arch/arm/cpu/armv7/ls102xa/psci.S new file mode 100644 index 0000000..cf5cd48 --- /dev/null +++ b/arch/arm/cpu/armv7/ls102xa/psci.S @@ -0,0 +1,126 @@ +/*
- Copyright 2015 Freescale Semiconductor, Inc.
- Author: Wang Dongsheng dongsheng.wang@freescale.com
- SPDX-License-Identifier: GPL-2.0+
- */
+#include <config.h> +#include <linux/linkage.h>
+#include <asm/armv7.h> +#include <asm/arch-armv7/generictimer.h> #include <asm/psci.h>
+#define SCFG_CORE0_SFT_RST 0x130 +#define SCFG_CORESRENCR 0x204
+#define DCFG_CCSR_BRR 0x0E4 +#define DCFG_CCSR_SCRATCHRW1 0x200
- .pushsection ._secure.text, "ax"
- .arch_extension sec
+#define ONE_MS (GENERIC_TIMER_CLK / 1000) +#define RESET_WAIT (30 * ONE_MS)
- @ r1 = target CPU
- @ r2 = target PC
+.globl psci_cpu_on +psci_cpu_on:
- push {lr}
- @ Clear and Get the correct CPU number
- @ r1 = 0xf01
- and r1, r1, #0xff
- mov r0, r1
- bl psci_get_cpu_stack_top
- str r2, [r0]
- dsb
- @ Get DCFG base address
- movw r4, #(CONFIG_SYS_FSL_GUTS_ADDR & 0xffff)
- movt r4, #(CONFIG_SYS_FSL_GUTS_ADDR >> 16)
- @ Detect target CPU state
- ldr r2, [r4, #DCFG_CCSR_BRR]
- rev r2, r2
- lsr r2, r2, r1
- ands r2, r2, #1
- beq holdoff_release
- @ Reset target CPU
- @ Get SCFG base address
- movw r0, #(CONFIG_SYS_FSL_SCFG_ADDR & 0xffff)
- movt r0, #(CONFIG_SYS_FSL_SCFG_ADDR >> 16)
- @ Enable CORE Soft Reset
- movw r5, #0
- movt r5, #(1 << 15)
- rev r5, r5
- str r5, [r0, #SCFG_CORESRENCR]
- @ Get CPUx offset register
- mov r6, #0x4
- mul r6, r6, r1
- add r2, r0, r6
- @ Do reset on target CPU
- movw r5, #0
- movt r5, #(1 << 15)
- rev r5, r5
- str r5, [r2, #SCFG_CORE0_SFT_RST]
- @ Wait target CPU up
- timer_wait r2, RESET_WAIT
- @ Disable CORE soft reset
- mov r5, #0
- str r5, [r0, #SCFG_CORESRENCR]
+holdoff_release:
- @ Release on target CPU
- ldr r2, [r4, #DCFG_CCSR_BRR]
- mov r6, #1
- lsl r6, r6, r1 @ 32 bytes per CPU
- rev r6, r6
- orr r2, r2, r6
- str r2, [r4, #DCFG_CCSR_BRR]
- @ Set secondary boot entry
- ldr r6, =psci_cpu_entry
- rev r6, r6
- str r6, [r4, #DCFG_CCSR_SCRATCHRW1]
- isb
- dsb
- @ Return
- mov r0, #ARM_PSCI_RET_SUCCESS
- pop {lr}
- bx lr
+.globl psci_cpu_off +psci_cpu_off:
- bl psci_cpu_off_common
+1: wfi
- b 1b
+.globl psci_arch_init +psci_arch_init:
- mov r6, lr
- bl psci_get_cpu_id
- bl psci_get_cpu_stack_top
- mov sp, r0
- bx r6
- .globl psci_text_end
+psci_text_end:
- .popsection
diff --git a/include/configs/ls1021aqds.h b/include/configs/ls1021aqds.h index ca913b0..7232cd9 100644 --- a/include/configs/ls1021aqds.h +++ b/include/configs/ls1021aqds.h @@ -11,6 +11,8 @@
#define CONFIG_LS102XA
+#define CONFIG_ARMV7_PSCI
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_CPUINFO diff --git a/include/configs/ls1021atwr.h b/include/configs/ls1021atwr.h index 6b6f2ba..b618be5 100644 --- a/include/configs/ls1021atwr.h +++ b/include/configs/ls1021atwr.h @@ -11,6 +11,8 @@
#define CONFIG_LS102XA
+#define CONFIG_ARMV7_PSCI
#define CONFIG_SYS_GENERIC_BOARD
#define CONFIG_DISPLAY_CPUINFO
2.1.0.27.g96db324
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
On 06/03/2015 09:01 PM, Dongsheng Wang wrote:
From: Wang Dongsheng dongsheng.wang@freescale.com
Base on PSCI services, implement CPU_ON/CPU_OFF for ls102xa platform.
Tested on LS1021AQDS, LS1021ATWR. Test CPU hotplug times: 60K Test kernel boot times: 1.2K
Signed-off-by: Wang Dongsheng dongsheng.wang@freescale.com
Applied to u-boot-fsl-qoriq master branch.
York
Hi all,
Sorry I was too busy recently, and I forgot to tag version information.
The patches should be marked for V2 version.
*V2*: 1. Retain the original author's Copyright. 2. Based on Chen-Yu Tsai's patch rebase this patch, factor out time_wait Macro from psci_sun7i.S and psci_sun6i.S.
Regards, -Dongsheng
-----Original Message----- From: Dongsheng Wang [mailto:dongsheng.wang@freescale.com] Sent: Thursday, June 04, 2015 12:01 PM To: Sun York-R58495 Cc: ijc@hellion.org.uk; hdegoede@redhat.com; albert.u.boot@aribaud.net; jan.kiszka@siemens.com; Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui- B35336; u-boot@lists.denx.de; Wang Dongsheng-B40534 Subject: [PATCH 1/2] ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S
From: Wang Dongsheng dongsheng.wang@freescale.com
timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted completely into a reusable armv7 generic timer. LS1021A will use it as well.
Signed-off-by: Wang Dongsheng dongsheng.wang@freescale.com
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S index d4cb51e..4ff46e4 100644 --- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S +++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S @@ -18,6 +18,8 @@ */
#include <config.h>
+#include <asm/arch-armv7/generictimer.h> #include <asm/gic.h> #include <asm/macro.h> #include <asm/psci.h> @@ -43,26 +45,6 @@ #define GICD_BASE 0x1c81000 #define GICC_BASE 0x1c82000
-.macro timer_wait reg, ticks
- @ Program CNTP_TVAL
- movw \reg, #(\ticks & 0xffff)
- movt \reg, #(\ticks >> 16)
- mcr p15, 0, \reg, c14, c2, 0
- isb
- @ Enable physical timer, mask interrupt
- mov \reg, #3
- mcr p15, 0, \reg, c14, c2, 1
- @ Poll physical timer until ISTATUS is on
-1: isb
- mrc p15, 0, \reg, c14, c2, 1
- ands \reg, \reg, #4
- bne 1b
- @ Disable timer
- mov \reg, #0
- mcr p15, 0, \reg, c14, c2, 1
- isb
-.endm
.globl psci_fiq_enter psci_fiq_enter: push {r0-r12} diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S index bbfeec8..e15d587 100644 --- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S +++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S @@ -18,6 +18,8 @@ */
#include <config.h>
+#include <asm/arch-armv7/generictimer.h> #include <asm/gic.h> #include <asm/macro.h> #include <asm/psci.h> @@ -43,26 +45,6 @@ #define GICD_BASE 0x1c81000 #define GICC_BASE 0x1c82000
-.macro timer_wait reg, ticks
- @ Program CNTP_TVAL
- movw \reg, #(\ticks & 0xffff)
- movt \reg, #(\ticks >> 16)
- mcr p15, 0, \reg, c14, c2, 0
- isb
- @ Enable physical timer, mask interrupt
- mov \reg, #3
- mcr p15, 0, \reg, c14, c2, 1
- @ Poll physical timer until ISTATUS is on
-1: isb
- mrc p15, 0, \reg, c14, c2, 1
- ands \reg, \reg, #4
- bne 1b
- @ Disable timer
- mov \reg, #0
- mcr p15, 0, \reg, c14, c2, 1
- isb
-.endm
.globl psci_fiq_enter psci_fiq_enter: push {r0-r12} diff --git a/arch/arm/include/asm/arch-armv7/generictimer.h b/arch/arm/include/asm/arch-armv7/generictimer.h new file mode 100644 index 0000000..0956d7c --- /dev/null +++ b/arch/arm/include/asm/arch-armv7/generictimer.h @@ -0,0 +1,50 @@ +/*
- Copyright (C) 2013 - ARM Ltd
- Author: Marc Zyngier marc.zyngier@arm.com
- Based on code by Carl van Schaik carl@ok-labs.com.
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License version 2 as
- published by the Free Software Foundation.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program. If not, see http://www.gnu.org/licenses/.
- */
+#ifndef _GENERICTIMER_H_ +#define _GENERICTIMER_H_
+#ifdef __ASSEMBLY__
+/*
- This macro provide a physical timer that can be used for delay in the code.
- The macro is moved from sunxi/psci_sun7i.S
- reg: is used in this macro.
- ticks: The freq is based on generic timer.
- */
+.macro timer_wait reg, ticks
- movw \reg, #(\ticks & 0xffff)
- movt \reg, #(\ticks >> 16)
- mcr p15, 0, \reg, c14, c2, 0
- isb
- mov \reg, #3
- mcr p15, 0, \reg, c14, c2, 1
+1 : isb
- mrc p15, 0, \reg, c14, c2, 1
- ands \reg, \reg, #4
- bne 1b
- mov \reg, #0
- mcr p15, 0, \reg, c14, c2, 1
- isb
+.endm
+#endif /* __ASSEMBLY__ */
+#endif /* _GENERICTIMER_H_ */
2.1.0.27.g96db324
Hi,
On 04-06-15 06:01, Dongsheng Wang wrote:
From: Wang Dongsheng dongsheng.wang@freescale.com
timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted completely into a reusable armv7 generic timer. LS1021A will use it as well.
Signed-off-by: Wang Dongsheng dongsheng.wang@freescale.com
Thanks for rebasing this, looks good:
Reviewed-by: Hans de Goede hdegoede@redhat.com
As for upstreaming this, it is probably best for the entire set to go upstream through the same tree, although if people want I can upstream this one through the sunxi tree.
In the mean time I'll add this to the sunxi-wip branch of my personal repo so that it sees some testing (not that I'm expecting any issues).
Regards,
Hans
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S index d4cb51e..4ff46e4 100644 --- a/arch/arm/cpu/armv7/sunxi/psci_sun6i.S +++ b/arch/arm/cpu/armv7/sunxi/psci_sun6i.S @@ -18,6 +18,8 @@ */
#include <config.h>
+#include <asm/arch-armv7/generictimer.h> #include <asm/gic.h> #include <asm/macro.h> #include <asm/psci.h> @@ -43,26 +45,6 @@ #define GICD_BASE 0x1c81000 #define GICC_BASE 0x1c82000
-.macro timer_wait reg, ticks
- @ Program CNTP_TVAL
- movw \reg, #(\ticks & 0xffff)
- movt \reg, #(\ticks >> 16)
- mcr p15, 0, \reg, c14, c2, 0
- isb
- @ Enable physical timer, mask interrupt
- mov \reg, #3
- mcr p15, 0, \reg, c14, c2, 1
- @ Poll physical timer until ISTATUS is on
-1: isb
- mrc p15, 0, \reg, c14, c2, 1
- ands \reg, \reg, #4
- bne 1b
- @ Disable timer
- mov \reg, #0
- mcr p15, 0, \reg, c14, c2, 1
- isb
-.endm
- .globl psci_fiq_enter psci_fiq_enter: push {r0-r12}
diff --git a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S index bbfeec8..e15d587 100644 --- a/arch/arm/cpu/armv7/sunxi/psci_sun7i.S +++ b/arch/arm/cpu/armv7/sunxi/psci_sun7i.S @@ -18,6 +18,8 @@ */
#include <config.h>
+#include <asm/arch-armv7/generictimer.h> #include <asm/gic.h> #include <asm/macro.h> #include <asm/psci.h> @@ -43,26 +45,6 @@ #define GICD_BASE 0x1c81000 #define GICC_BASE 0x1c82000
-.macro timer_wait reg, ticks
- @ Program CNTP_TVAL
- movw \reg, #(\ticks & 0xffff)
- movt \reg, #(\ticks >> 16)
- mcr p15, 0, \reg, c14, c2, 0
- isb
- @ Enable physical timer, mask interrupt
- mov \reg, #3
- mcr p15, 0, \reg, c14, c2, 1
- @ Poll physical timer until ISTATUS is on
-1: isb
- mrc p15, 0, \reg, c14, c2, 1
- ands \reg, \reg, #4
- bne 1b
- @ Disable timer
- mov \reg, #0
- mcr p15, 0, \reg, c14, c2, 1
- isb
-.endm
- .globl psci_fiq_enter psci_fiq_enter: push {r0-r12}
diff --git a/arch/arm/include/asm/arch-armv7/generictimer.h b/arch/arm/include/asm/arch-armv7/generictimer.h new file mode 100644 index 0000000..0956d7c --- /dev/null +++ b/arch/arm/include/asm/arch-armv7/generictimer.h @@ -0,0 +1,50 @@ +/*
- Copyright (C) 2013 - ARM Ltd
- Author: Marc Zyngier marc.zyngier@arm.com
- Based on code by Carl van Schaik carl@ok-labs.com.
- This program is free software; you can redistribute it and/or modify
- it under the terms of the GNU General Public License version 2 as
- published by the Free Software Foundation.
- This program is distributed in the hope that it will be useful,
- but WITHOUT ANY WARRANTY; without even the implied warranty of
- MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
- GNU General Public License for more details.
- You should have received a copy of the GNU General Public License
- along with this program. If not, see http://www.gnu.org/licenses/.
- */
+#ifndef _GENERICTIMER_H_ +#define _GENERICTIMER_H_
+#ifdef __ASSEMBLY__
+/*
- This macro provide a physical timer that can be used for delay in the code.
- The macro is moved from sunxi/psci_sun7i.S
- reg: is used in this macro.
- ticks: The freq is based on generic timer.
- */
+.macro timer_wait reg, ticks
- movw \reg, #(\ticks & 0xffff)
- movt \reg, #(\ticks >> 16)
- mcr p15, 0, \reg, c14, c2, 0
- isb
- mov \reg, #3
- mcr p15, 0, \reg, c14, c2, 1
+1 : isb
- mrc p15, 0, \reg, c14, c2, 1
- ands \reg, \reg, #4
- bne 1b
- mov \reg, #0
- mcr p15, 0, \reg, c14, c2, 1
- isb
+.endm
+#endif /* __ASSEMBLY__ */
+#endif /* _GENERICTIMER_H_ */
Hi,
-----Original Message----- From: Hans de Goede [mailto:hdegoede@redhat.com] Sent: Thursday, June 04, 2015 6:15 PM To: Wang Dongsheng-B40534; Sun York-R58495 Cc: ijc@hellion.org.uk; albert.u.boot@aribaud.net; jan.kiszka@siemens.com; Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui-B35336; u-boot@lists.denx.de Subject: Re: [PATCH 1/2] ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S
Hi,
On 04-06-15 06:01, Dongsheng Wang wrote:
From: Wang Dongsheng dongsheng.wang@freescale.com
timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted completely into a reusable armv7 generic timer. LS1021A will use it as well.
Signed-off-by: Wang Dongsheng dongsheng.wang@freescale.com
Thanks for rebasing this, looks good:
Reviewed-by: Hans de Goede hdegoede@redhat.com
As for upstreaming this, it is probably best for the entire set to go upstream through the same tree, although if people want I can upstream this one through the sunxi tree.
In the mean time I'll add this to the sunxi-wip branch of my personal repo so that it sees some testing (not that I'm expecting any issues).
Thanks for your review.
Sorry, I'm confused in your comments. I based on git://git.denx.de/u-boot.git, master branch. Need I change the tree? Or ?
Regards, -Dongsheng
Hi,
On 05-06-15 10:41, Wang Dongsheng wrote:
Hi,
-----Original Message----- From: Hans de Goede [mailto:hdegoede@redhat.com] Sent: Thursday, June 04, 2015 6:15 PM To: Wang Dongsheng-B40534; Sun York-R58495 Cc: ijc@hellion.org.uk; albert.u.boot@aribaud.net; jan.kiszka@siemens.com; Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui-B35336; u-boot@lists.denx.de Subject: Re: [PATCH 1/2] ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S
Hi,
On 04-06-15 06:01, Dongsheng Wang wrote:
From: Wang Dongsheng dongsheng.wang@freescale.com
timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted completely into a reusable armv7 generic timer. LS1021A will use it as well.
Signed-off-by: Wang Dongsheng dongsheng.wang@freescale.com
Thanks for rebasing this, looks good:
Reviewed-by: Hans de Goede hdegoede@redhat.com
As for upstreaming this, it is probably best for the entire set to go upstream through the same tree, although if people want I can upstream this one through the sunxi tree.
In the mean time I'll add this to the sunxi-wip branch of my personal repo so that it sees some testing (not that I'm expecting any issues).
Thanks for your review.
Sorry, I'm confused in your comments. I based on git://git.denx.de/u-boot.git, master branch. Need I change the tree? Or ?
No everything is fine.
What I'm trying to say is that these patches should probably be merged by the ls102xa maintainer.
Regards,
Hans
Hi Hans,
Thanks.
Regards, -Dongsheng
-----Original Message----- From: Hans de Goede [mailto:hdegoede@redhat.com] Sent: Friday, June 05, 2015 5:35 PM To: Wang Dongsheng-B40534; Sun York-R58495 Cc: ijc@hellion.org.uk; albert.u.boot@aribaud.net; jan.kiszka@siemens.com; Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui-B35336; u-boot@lists.denx.de Subject: Re: [PATCH 1/2] ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S
Hi,
On 05-06-15 10:41, Wang Dongsheng wrote:
Hi,
-----Original Message----- From: Hans de Goede [mailto:hdegoede@redhat.com] Sent: Thursday, June 04, 2015 6:15 PM To: Wang Dongsheng-B40534; Sun York-R58495 Cc: ijc@hellion.org.uk; albert.u.boot@aribaud.net; jan.kiszka@siemens.com; Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui-B35336; u-boot@lists.denx.de Subject: Re: [PATCH 1/2] ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S
Hi,
On 04-06-15 06:01, Dongsheng Wang wrote:
From: Wang Dongsheng dongsheng.wang@freescale.com
timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted completely into a reusable armv7 generic timer. LS1021A will use it as well.
Signed-off-by: Wang Dongsheng dongsheng.wang@freescale.com
Thanks for rebasing this, looks good:
Reviewed-by: Hans de Goede hdegoede@redhat.com
As for upstreaming this, it is probably best for the entire set to go upstream through the same tree, although if people want I can upstream this one through the sunxi tree.
In the mean time I'll add this to the sunxi-wip branch of my personal repo so that it sees some testing (not that I'm expecting any issues).
Thanks for your review.
Sorry, I'm confused in your comments. I based on git://git.denx.de/u-boot.git, master branch. Need I change the tree?
Or ?
No everything is fine.
What I'm trying to say is that these patches should probably be merged by the ls102xa maintainer.
Regards,
Hans
On 06/05/2015 02:39 AM, Wang Dongsheng-B40534 wrote:
Hi Hans,
Thanks.
Regards, -Dongsheng
-----Original Message----- From: Hans de Goede [mailto:hdegoede@redhat.com] Sent: Friday, June 05, 2015 5:35 PM To: Wang Dongsheng-B40534; Sun York-R58495 Cc: ijc@hellion.org.uk; albert.u.boot@aribaud.net; jan.kiszka@siemens.com; Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui-B35336; u-boot@lists.denx.de Subject: Re: [PATCH 1/2] ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S
Hi,
On 05-06-15 10:41, Wang Dongsheng wrote:
Hi,
-----Original Message----- From: Hans de Goede [mailto:hdegoede@redhat.com] Sent: Thursday, June 04, 2015 6:15 PM To: Wang Dongsheng-B40534; Sun York-R58495 Cc: ijc@hellion.org.uk; albert.u.boot@aribaud.net; jan.kiszka@siemens.com; Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui-B35336; u-boot@lists.denx.de Subject: Re: [PATCH 1/2] ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S
Hi,
On 04-06-15 06:01, Dongsheng Wang wrote:
From: Wang Dongsheng dongsheng.wang@freescale.com
timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted completely into a reusable armv7 generic timer. LS1021A will use it as well.
Signed-off-by: Wang Dongsheng dongsheng.wang@freescale.com
Thanks for rebasing this, looks good:
Reviewed-by: Hans de Goede hdegoede@redhat.com
As for upstreaming this, it is probably best for the entire set to go upstream through the same tree, although if people want I can upstream this one through the sunxi tree.
In the mean time I'll add this to the sunxi-wip branch of my personal repo so that it sees some testing (not that I'm expecting any issues).
Thanks for your review.
Sorry, I'm confused in your comments. I based on git://git.denx.de/u-boot.git, master branch. Need I change the tree?
Or ?
No everything is fine.
What I'm trying to say is that these patches should probably be merged by the ls102xa maintainer.
I can take this set into fsl-qoriq.
York
Hi,
On 05-06-15 17:11, York Sun wrote:
On 06/05/2015 02:39 AM, Wang Dongsheng-B40534 wrote:
Hi Hans,
Thanks.
Regards, -Dongsheng
-----Original Message----- From: Hans de Goede [mailto:hdegoede@redhat.com] Sent: Friday, June 05, 2015 5:35 PM To: Wang Dongsheng-B40534; Sun York-R58495 Cc: ijc@hellion.org.uk; albert.u.boot@aribaud.net; jan.kiszka@siemens.com; Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui-B35336; u-boot@lists.denx.de Subject: Re: [PATCH 1/2] ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S
Hi,
On 05-06-15 10:41, Wang Dongsheng wrote:
Hi,
-----Original Message----- From: Hans de Goede [mailto:hdegoede@redhat.com] Sent: Thursday, June 04, 2015 6:15 PM To: Wang Dongsheng-B40534; Sun York-R58495 Cc: ijc@hellion.org.uk; albert.u.boot@aribaud.net; jan.kiszka@siemens.com; Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui-B35336; u-boot@lists.denx.de Subject: Re: [PATCH 1/2] ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S
Hi,
On 04-06-15 06:01, Dongsheng Wang wrote:
From: Wang Dongsheng dongsheng.wang@freescale.com
timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted completely into a reusable armv7 generic timer. LS1021A will use it as well.
Signed-off-by: Wang Dongsheng dongsheng.wang@freescale.com
Thanks for rebasing this, looks good:
Reviewed-by: Hans de Goede hdegoede@redhat.com
As for upstreaming this, it is probably best for the entire set to go upstream through the same tree, although if people want I can upstream this one through the sunxi tree.
In the mean time I'll add this to the sunxi-wip branch of my personal repo so that it sees some testing (not that I'm expecting any issues).
Thanks for your review.
Sorry, I'm confused in your comments. I based on git://git.denx.de/u-boot.git, master branch. Need I change the tree?
Or ?
No everything is fine.
What I'm trying to say is that these patches should probably be merged by the ls102xa maintainer.
I can take this set into fsl-qoriq.
That is fine with me.
Regards,
Hans
Hi York,
Could you apply this patch?
Regards, -Dongsheng
-----Original Message----- From: Hans de Goede [mailto:hdegoede@redhat.com] Sent: Saturday, June 06, 2015 3:18 AM To: Sun York-R58495; Wang Dongsheng-B40534 Cc: ijc@hellion.org.uk; albert.u.boot@aribaud.net; jan.kiszka@siemens.com; Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui-B35336; u-boot@lists.denx.de Subject: Re: [PATCH 1/2] ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S
Hi,
On 05-06-15 17:11, York Sun wrote:
On 06/05/2015 02:39 AM, Wang Dongsheng-B40534 wrote:
Hi Hans,
Thanks.
Regards, -Dongsheng
-----Original Message----- From: Hans de Goede [mailto:hdegoede@redhat.com] Sent: Friday, June 05, 2015 5:35 PM To: Wang Dongsheng-B40534; Sun York-R58495 Cc: ijc@hellion.org.uk; albert.u.boot@aribaud.net; jan.kiszka@siemens.com; Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui-B35336; u-boot@lists.denx.de Subject: Re: [PATCH 1/2] ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S
Hi,
On 05-06-15 10:41, Wang Dongsheng wrote:
Hi,
-----Original Message----- From: Hans de Goede [mailto:hdegoede@redhat.com] Sent: Thursday, June 04, 2015 6:15 PM To: Wang Dongsheng-B40534; Sun York-R58495 Cc: ijc@hellion.org.uk; albert.u.boot@aribaud.net; jan.kiszka@siemens.com; Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui-B35336; u-boot@lists.denx.de Subject: Re: [PATCH 1/2] ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S
Hi,
On 04-06-15 06:01, Dongsheng Wang wrote: > From: Wang Dongsheng dongsheng.wang@freescale.com > > timer_wait is moved from sunxi/psci_sun7i.S, and it can be > converted completely into a reusable armv7 generic timer. LS1021A > will use it as well. > > Signed-off-by: Wang Dongsheng dongsheng.wang@freescale.com
Thanks for rebasing this, looks good:
Reviewed-by: Hans de Goede hdegoede@redhat.com
As for upstreaming this, it is probably best for the entire set to go upstream through the same tree, although if people want I can upstream this one through the sunxi tree.
In the mean time I'll add this to the sunxi-wip branch of my personal repo so that it sees some testing (not that I'm expecting any
issues).
Thanks for your review.
Sorry, I'm confused in your comments. I based on git://git.denx.de/u-boot.git, master branch. Need I change the
tree?
Or ?
No everything is fine.
What I'm trying to say is that these patches should probably be merged by the ls102xa maintainer.
I can take this set into fsl-qoriq.
That is fine with me.
Regards,
Hans
On 06/03/2015 09:01 PM, Dongsheng Wang wrote:
From: Wang Dongsheng dongsheng.wang@freescale.com
timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted completely into a reusable armv7 generic timer. LS1021A will use it as well.
Signed-off-by: Wang Dongsheng dongsheng.wang@freescale.com
Applied to u-boot-fsl-qoriq master branch.
York
Thanks. :)
Regards, -Dongsheng
-----Original Message----- From: Sun York-R58495 Sent: Tuesday, July 21, 2015 5:14 AM To: Wang Dongsheng-B40534 Cc: ijc@hellion.org.uk; hdegoede@redhat.com; albert.u.boot@aribaud.net; jan.kiszka@siemens.com; Jin Zhengxiong-R64188; Wang Huan-B18965; Zhao Chenhui- B35336; u-boot@lists.denx.de Subject: Re: [PATCH 1/2] ARMv7: Factor out reusable timer_wait from sunxi/psci_sun7i.S
On 06/03/2015 09:01 PM, Dongsheng Wang wrote:
From: Wang Dongsheng dongsheng.wang@freescale.com
timer_wait is moved from sunxi/psci_sun7i.S, and it can be converted completely into a reusable armv7 generic timer. LS1021A will use it as well.
Signed-off-by: Wang Dongsheng dongsheng.wang@freescale.com
Applied to u-boot-fsl-qoriq master branch.
York
participants (5)
-
Dongsheng Wang -
Hans de Goede -
Huan Wang -
Wang Dongsheng
-
York Sun