[U-Boot] [PATCH] mx5: Add clock config interface
From: Jason Liu jason.hui@linaro.org
mx5: Add clock config interface
Add clock config interface support, so that we can configure CPU or DDR clock in the later init
Signed-off-by: Jason Liu jason.hui@linaro.org Signed-off-by: Eric Miao eric.miao@linaro.org ---
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index e92f106..c7613f0 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -24,6 +24,7 @@ */
#include <common.h> +#include <div64.h> #include <asm/io.h> #include <asm/errno.h> #include <asm/arch/imx-regs.h> @@ -48,6 +49,39 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = { #endif };
+#define AHB_CLK_ROOT 133333333 +#define SZ_DEC_1M 1000000 +#define PLL_PD_MAX 16 /* Actual pd+1 */ +#define PLL_MFI_MAX 15 +#define PLL_MFI_MIN 5 +#define ARM_DIV_MAX 8 +#define IPG_DIV_MAX 4 +#define AHB_DIV_MAX 8 +#define EMI_DIV_MAX 8 +#define NFC_DIV_MAX 8 + +struct fixed_pll_mfd { + u32 ref_clk_hz; + u32 mfd; +}; + +const struct fixed_pll_mfd fixed_mfd[] = { + {CONFIG_SYS_MX5_HCLK, 24 * 16}, +}; + +struct pll_param { + u32 pd; + u32 mfi; + u32 mfn; + u32 mfd; +}; + +#define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX) +#define PLL_FREQ_MIN(ref_clk) \ + ((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX) +#define MAX_DDR_CLK 420000000 +#define NFC_CLK_MAX 34000000 + struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
void set_usboh3_clk(void) @@ -212,20 +246,13 @@ static u32 get_periph_clk(void) /* NOTREACHED */ }
-/* - * Get the rate of ahb clock. - */ static u32 get_ahb_clk(void) { - uint32_t freq, div, reg; + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + u32 pdf = (cbcdr & MXC_CCM_CBCDR_AHB_PODF_MASK) \ + >> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
- freq = get_periph_clk(); - - reg = __raw_readl(&mxc_ccm->cbcdr); - div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >> - MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1; - - return freq / div; + return get_periph_clk() / (pdf + 1); }
/* @@ -306,7 +333,7 @@ static u32 get_uart_clk(void) /* * This function returns the low power audio clock. */ -u32 get_lp_apm(void) +static u32 get_lp_apm(void) { u32 ret_val = 0; u32 ccsr = __raw_readl(&mxc_ccm->ccsr); @@ -322,7 +349,7 @@ u32 get_lp_apm(void) /* * get cspi clock rate. */ -u32 imx_get_cspiclk(void) +static u32 get_cspi_clk(void) { u32 ret_val = 0, pdf, pre_pdf, clk_sel; u32 cscmr1 = __raw_readl(&mxc_ccm->cscmr1); @@ -359,6 +386,85 @@ u32 imx_get_cspiclk(void) return ret_val; }
+static u32 get_axi_a_clk(void) +{ + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \ + >> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET; + + return get_periph_clk() / (pdf + 1); +} + +static u32 get_axi_b_clk(void) +{ + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \ + >> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET; + + return get_periph_clk() / (pdf + 1); +} + +static u32 get_emi_slow_clk(void) +{ + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL; + u32 pdf = (cbcdr & MXC_CCM_CBCDR_EMI_PODF_MASK) \ + >> MXC_CCM_CBCDR_EMI_PODF_OFFSET; + + if (emi_clk_sel) + return get_ahb_clk() / (pdf + 1); + + return get_periph_clk() / (pdf + 1); +} + +static u32 get_nfc_clk(void) +{ + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + u32 pdf = (cbcdr & MXC_CCM_CBCDR_NFC_PODF_MASK) \ + >> MXC_CCM_CBCDR_NFC_PODF_OFFSET; + + return get_emi_slow_clk() / (pdf + 1); +} + +static u32 get_ddr_clk(void) +{ + u32 ret_val = 0; + u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr); + u32 ddr_clk_sel = (cbcmr & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) \ + >> MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET; +#ifdef CONFIG_MX51 + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) { + u32 ddr_clk_podf = (cbcdr & MXC_CCM_CBCDR_DDR_PODF_MASK) >> \ + MXC_CCM_CBCDR_DDR_PODF_OFFSET; + + ret_val = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK); + ret_val /= ddr_clk_podf + 1; + + return ret_val; + } +#endif + switch (ddr_clk_sel) { + case 0: + ret_val = get_axi_a_clk(); + break; + case 1: + ret_val = get_axi_b_clk(); + break; + case 2: + ret_val = get_emi_slow_clk(); + break; + case 3: + ret_val = get_ahb_clk(); + break; + default: + break; + } + + return ret_val; +} + + /* * The API of get mxc clockes. */ @@ -376,10 +482,12 @@ unsigned int mxc_get_clock(enum mxc_clock clk) case MXC_UART_CLK: return get_uart_clk(); case MXC_CSPI_CLK: - return imx_get_cspiclk(); + return get_cspi_clk(); case MXC_FEC_CLK: return decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK); + case MXC_DDR_CLK: + return get_ddr_clk(); default: break; } @@ -398,6 +506,424 @@ u32 imx_get_fecclk(void) }
/* + * Clock config code start here + */ + +/* precondition: m>0 and n>0. Let g=gcd(m,n). */ +static int gcd(int m, int n) +{ + int t; + while (m > 0) { + if (n > m) { + t = m; + m = n; + n = t; + } /* swap */ + m -= n; + } + return n; +} + +/* + * This is to calculate various parameters based on reference clock and + * targeted clock based on the equation: + * t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1) + * This calculation is based on a fixed MFD value for simplicity. + * + * @param ref reference clock freq in Hz + * @param target targeted clock in Hz + * @param pll pll_param structure. + * + * @return 0 if successful; non-zero otherwise. + */ +static int calc_pll_params(u32 ref, u32 target, struct pll_param *pll) +{ + u64 pd, mfi = 1, mfn, mfd, t1; + u32 n_target = target; + u32 n_ref = ref, i; + + /* + * Make sure targeted freq is in the valid range. + * Otherwise the following calculation might be wrong!!! + */ + if (n_target < PLL_FREQ_MIN(ref) || + n_target > PLL_FREQ_MAX(ref)) { + printf("Targeted peripheral clock should be" + "within [%d - %d]\n", + PLL_FREQ_MIN(ref) / SZ_DEC_1M, + PLL_FREQ_MAX(ref) / SZ_DEC_1M); + return -1; + } + + for (i = 0; i < ARRAY_SIZE(fixed_mfd); i++) { + if (fixed_mfd[i].ref_clk_hz == ref) { + mfd = fixed_mfd[i].mfd; + break; + } + } + + if (i == ARRAY_SIZE(fixed_mfd)) + return -1; + + /* Use n_target and n_ref to avoid overflow */ + for (pd = 1; pd <= PLL_PD_MAX; pd++) { + t1 = n_target * pd; + do_div(t1, (4 * n_ref)); + mfi = t1; + if (mfi > PLL_MFI_MAX) + return -1; + else if (mfi < 5) + continue; + break; + } + /* Now got pd and mfi already */ + /* + mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref; + */ + t1 = n_target * pd; + do_div(t1, 4); + t1 -= n_ref * mfi; + t1 *= mfd; + do_div(t1, n_ref); + mfn = t1; +#ifdef CMD_CLOCK_DEBUG + printf("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n", + ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd); +#endif + i = 1; + if (mfn != 0) + i = gcd(mfd, mfn); + pll->pd = (u32)pd; + pll->mfi = (u32)mfi; + do_div(mfn, i); + pll->mfn = (u32)mfn; + do_div(mfd, i); + pll->mfd = (u32)mfd; + + return 0; +} + +#define calc_div(tgt_clk, src_clk, limit) ({ \ + u32 v = 0; \ + if (((src_clk) % (tgt_clk)) <= 100) \ + v = (src_clk) / (tgt_clk); \ + else \ + v = ((src_clk) / (tgt_clk)) + 1;\ + if (v > limit) \ + v = limit; \ + (v - 1); \ + }) + +static u32 calc_per_cbcdr_val(u32 per_clk) +{ + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + u32 tmp_clk = 0, div = 0, clk_sel = 0; + + cbcdr &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL; + + /* emi_slow_podf divider */ + tmp_clk = get_emi_slow_clk(); + clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL; + if (clk_sel) { + div = calc_div(tmp_clk, per_clk, 8); + cbcdr &= ~MXC_CCM_CBCDR_EMI_PODF_MASK; + cbcdr |= (div << MXC_CCM_CBCDR_EMI_PODF_OFFSET); + } + + /* axi_b_podf divider */ + tmp_clk = get_axi_b_clk(); + div = calc_div(tmp_clk, per_clk, 8); + cbcdr &= ~MXC_CCM_CBCDR_AXI_B_PODF_MASK; + cbcdr |= (div << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET); + + /* axi_b_podf divider */ + tmp_clk = get_axi_a_clk(); + div = calc_div(tmp_clk, per_clk, 8); + cbcdr &= ~MXC_CCM_CBCDR_AXI_A_PODF_MASK; + cbcdr |= (div << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET); + + /* ahb podf divider */ + tmp_clk = AHB_CLK_ROOT; + div = calc_div(tmp_clk, per_clk, 8); + cbcdr &= ~MXC_CCM_CBCDR_AHB_PODF_MASK; + cbcdr |= (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET); + + return cbcdr; +} + +#define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \ + { \ + __raw_writel(0x1232, &pll->ctrl); \ + __raw_writel(0x2, &pll->config); \ + __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \ + &pll->op); \ + __raw_writel(fn, &(pll->mfn)); \ + __raw_writel((fd) - 1, &pll->mfd); \ + __raw_writel((((pd) - 1) << 0) | ((fi) << 4), \ + &pll->hfs_op); \ + __raw_writel(fn, &pll->hfs_mfn); \ + __raw_writel((fd) - 1, &pll->hfs_mfd); \ + __raw_writel(0x1232, &pll->ctrl); \ + while (!__raw_readl(&pll->ctrl) & 0x1) \ + ;\ + } + +static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param) +{ + u32 ccsr = __raw_readl(&mxc_ccm->ccsr); + struct mxc_pll_reg *pll = mxc_plls[index]; + + switch (index) { + case PLL1_CLOCK: + /* Switch ARM to PLL2 clock */ + __raw_writel(ccsr | 0x4, &mxc_ccm->ccsr); + CHANGE_PLL_SETTINGS(pll, pll_param->pd, + pll_param->mfi, pll_param->mfn, + pll_param->mfd); + /* Switch back */ + __raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr); + break; + case PLL2_CLOCK: + /* Switch to pll2 bypass clock */ + __raw_writel(ccsr | 0x2, &mxc_ccm->ccsr); + CHANGE_PLL_SETTINGS(pll, pll_param->pd, + pll_param->mfi, pll_param->mfn, + pll_param->mfd); + /* Switch back */ + __raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr); + break; + case PLL3_CLOCK: + /* Switch to pll3 bypass clock */ + __raw_writel(ccsr | 0x1, &mxc_ccm->ccsr); + CHANGE_PLL_SETTINGS(pll, pll_param->pd, + pll_param->mfi, pll_param->mfn, + pll_param->mfd); + /* Switch back */ + __raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr); + break; + case PLL4_CLOCK: + /* Switch to pll4 bypass clock */ + __raw_writel(ccsr | 0x20, &mxc_ccm->ccsr); + CHANGE_PLL_SETTINGS(pll, pll_param->pd, + pll_param->mfi, pll_param->mfn, + pll_param->mfd); + /* Switch back */ + __raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr); + break; + default: + return -1; + } + + return 0; +} + +/* Config CPU clock */ +static int config_core_clk(u32 ref, u32 freq) +{ + int ret = 0; + struct pll_param pll_param; + + memset(&pll_param, 0, sizeof(struct pll_param)); + + /* The case that periph uses PLL1 is not considered here */ + ret = calc_pll_params(ref, freq, &pll_param); + if (ret != 0) { + printf("Error:Can't find pll parameters: %d\n", ret); + return ret; + } + + return config_pll_clk(PLL1_CLOCK, &pll_param); +} + +static int config_nfc_clk(u32 nfc_clk) +{ + u32 reg; + u32 parent_rate = get_emi_slow_clk(); + u32 div = parent_rate / nfc_clk; + + if (nfc_clk <= 0) + return -1; + if (div == 0) + div++; + if (parent_rate / div > NFC_CLK_MAX) + div++; + reg = __raw_readl(&mxc_ccm->cbcdr); + reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK; + reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET; + __raw_writel(reg, &mxc_ccm->cbcdr); + while (__raw_readl(&mxc_ccm->cdhipr) != 0) + ; + return 0; +} + +/* Config main_bus_clock for periphs */ +static int config_periph_clk(u32 ref, u32 freq) +{ + int ret = 0; + struct pll_param pll_param; + + memset(&pll_param, 0, sizeof(struct pll_param)); + + if (__raw_readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) { + ret = calc_pll_params(ref, freq, &pll_param); + if (ret != 0) { + printf("Error:Can't find pll parameters: %d\n", + ret); + return ret; + } + switch ((__raw_readl(&mxc_ccm->cbcmr) & \ + MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> \ + MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) { + case 0: + return config_pll_clk(PLL1_CLOCK, &pll_param); + break; + case 1: + return config_pll_clk(PLL3_CLOCK, &pll_param); + break; + default: + return -1; + } + } else { + u32 old_cbcmr = __raw_readl(&mxc_ccm->cbcmr); + u32 new_cbcdr = calc_per_cbcdr_val(freq); + u32 old_nfc = get_nfc_clk(); + + /* Switch peripheral to PLL3 */ + __raw_writel(0x00015154, &mxc_ccm->cbcmr); + __raw_writel(0x02888945, &mxc_ccm->cbcdr); + + /* Make sure change is effective */ + while (__raw_readl(&mxc_ccm->cdhipr) != 0) + ; + + /* Setup PLL2 */ + ret = calc_pll_params(ref, freq, &pll_param); + if (ret != 0) { + printf("Error:Can't find pll parameters: %d\n", + ret); + return ret; + } + config_pll_clk(PLL2_CLOCK, &pll_param); + + /* Switch peripheral back */ + __raw_writel(new_cbcdr, &mxc_ccm->cbcdr); + __raw_writel(old_cbcmr, &mxc_ccm->cbcmr); + + /* Make sure change is effective */ + while (__raw_readl(&mxc_ccm->cdhipr) != 0) + ; + /* restore to old NFC clock */ + config_nfc_clk(old_nfc); + } + + return 0; +} + +static int config_ddr_clk(u32 emi_clk) +{ + u32 clk_src; + s32 shift = 0, clk_sel, div = 1; + u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr); + u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr); + + if (emi_clk > MAX_DDR_CLK) { + printf("Warning:DDR clock should not exceed %d MHz\n", + MAX_DDR_CLK / SZ_DEC_1M); + emi_clk = MAX_DDR_CLK; + } + + clk_src = get_periph_clk(); + /* Find DDR clock input */ + clk_sel = (cbcmr >> 10) & 0x3; + switch (clk_sel) { + case 0: + shift = 16; + break; + case 1: + shift = 19; + break; + case 2: + shift = 22; + break; + case 3: + shift = 10; + break; + default: + return -1; + } + + if ((clk_src % emi_clk) < 10000000) + div = clk_src / emi_clk; + else + div = (clk_src / emi_clk) + 1; + if (div > 8) + div = 8; + + cbcdr = cbcdr & ~(0x7 << shift); + cbcdr |= ((div - 1) << shift); + __raw_writel(cbcdr, &mxc_ccm->cbcdr); + while (__raw_readl(&mxc_ccm->cdhipr) != 0) + ; + __raw_writel(0x0, &mxc_ccm->ccdr); + + return 0; +} + +/*! + * This function assumes the expected core clock has to be changed by + * modifying the PLL. This is NOT true always but for most of the times, + * it is. So it assumes the PLL output freq is the same as the expected + * core clock (presc=1) unless the core clock is less than PLL_FREQ_MIN. + * In the latter case, it will try to increase the presc value until + * (presc*core_clk) is greater than PLL_FREQ_MIN. It then makes call to + * calc_pll_params() and obtains the values of PD, MFI,MFN, MFD based + * on the targeted PLL and reference input clock to the PLL. Lastly, + * it sets the register based on these values along with the dividers. + * Note 1) There is no value checking for the passed-in divider values + * so the caller has to make sure those values are sensible. + * 2) Also adjust the NFC divider such that the NFC clock doesn't + * exceed NFC_CLK_MAX. + * 3) IPU HSP clock is independent of AHB clock. Even it can go up to + * 177MHz for higher voltage, this function fixes the max to 133MHz. + * 4) This function should not have allowed diag_printf() calls since + * the serial driver has been stoped. But leave then here to allow + * easy debugging by NOT calling the cyg_hal_plf_serial_stop(). + * + * @param ref pll input reference clock (24MHz) + * @param freq core clock in Hz + * @param clk clock type, e.g CPU_CLK, DDR_CLK, etc. + * @return 0 if successful; non-zero otherwise + */ +int mxc_set_clock(u32 ref, u32 freq, enum mxc_clock clk) +{ + freq *= SZ_DEC_1M; + + switch (clk) { + case MXC_ARM_CLK: + if (config_core_clk(ref, freq)) + return -1; + break; + case MXC_PERIPH_CLK: + if (config_periph_clk(ref, freq)) + return -1; + break; + case MXC_DDR_CLK: + if (config_ddr_clk(freq)) + return -1; + break; + case MXC_NFC_CLK: + if (config_nfc_clk(freq)) + return -1; + break; + default: + printf("Warning:Unsupported or invalid clock type\n"); + } + + return 0; +} + + +/* * Dump some core clockes. */ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -414,12 +940,11 @@ int do_mx5_showclocks(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) freq = decode_pll(mxc_plls[PLL4_CLOCK], CONFIG_SYS_MX5_HCLK); printf("PLL4 %8d MHz\n", freq / 1000000); #endif - printf("\n"); printf("AHB %8d kHz\n", mxc_get_clock(MXC_AHB_CLK) / 1000); printf("IPG %8d kHz\n", mxc_get_clock(MXC_IPG_CLK) / 1000); printf("IPG PERCLK %8d kHz\n", mxc_get_clock(MXC_IPG_PERCLK) / 1000); - + printf("DDR %8d kHz\n", mxc_get_clock(MXC_DDR_CLK) / 1000); return 0; }
diff --git a/arch/arm/include/asm/arch-mx5/clock.h b/arch/arm/include/asm/arch-mx5/clock.h index ea972a3..3840975 100644 --- a/arch/arm/include/asm/arch-mx5/clock.h +++ b/arch/arm/include/asm/arch-mx5/clock.h @@ -32,6 +32,9 @@ enum mxc_clock { MXC_UART_CLK, MXC_CSPI_CLK, MXC_FEC_CLK, + MXC_DDR_CLK, + MXC_NFC_CLK, + MXC_PERIPH_CLK, };
unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); @@ -39,6 +42,7 @@ unsigned int imx_decode_pll(unsigned int pll, unsigned int f_ref); u32 imx_get_uartclk(void); u32 imx_get_fecclk(void); unsigned int mxc_get_clock(enum mxc_clock clk); +int mxc_set_clock(u32 ref, u32 freq, u32 clk_type);
void set_usb_phy2_clk(void); void enable_usb_phy2_clk(unsigned char enable); diff --git a/arch/arm/include/asm/arch-mx5/crm_regs.h b/arch/arm/include/asm/arch-mx5/crm_regs.h index bdeafbc..4e0fc1b 100644 --- a/arch/arm/include/asm/arch-mx5/crm_regs.h +++ b/arch/arm/include/asm/arch-mx5/crm_regs.h @@ -76,6 +76,9 @@ struct mxc_ccm_reg { u32 CCGR4; u32 CCGR5; u32 CCGR6; /* 0x0080 */ +#ifdef CONFIG_MX53 + u32 CCGR7; /* 0x0084 */ +#endif u32 cmeor; };
@@ -84,6 +87,9 @@ struct mxc_ccm_reg { #define MXC_CCM_CACRR_ARM_PODF_MASK 0x7
/* Define the bits in register CBCDR */ +#define MXC_CCM_CBCDR_DDR_HIFREQ_SEL (0x1 << 30) +#define MXC_CCM_CBCDR_DDR_PODF_MASK (0x7 << 27) +#define MXC_CCM_CBCDR_DDR_PODF_OFFSET 27 #define MXC_CCM_CBCDR_EMI_CLK_SEL (0x1 << 26) #define MXC_CCM_CBCDR_PERIPH_CLK_SEL (0x1 << 25) #define MXC_CCM_CBCDR_EMI_PODF_OFFSET 22
Add Dialog DA9053 PMIC support and bump the mx53 CPU frequency to 1GHz.
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com --- This depends on the previous "mx5: Add clock config interface" patch I have just submitted.
When doing a "clock" command I do see that the frequency has changed to 1GHz:
MX53LOCO U-Boot > clock PLL1 1000 MHz PLL2 400 MHz PLL3 216 MHz PLL4 595 MHz
AHB 133333 kHz IPG 66666 kHz IPG PERCLK 40000 kHz DDR 400000 kHz
Originally it was:
MX53LOCO U-Boot > clock PLL1 800 MHz PLL2 333 MHz PLL3 216 MHz PLL4 595 MHz
AHB 111000 kHz IPG 55500 kHz IPG PERCLK 33300 kHz
However, when the board boots I still see:
CPU: Freescale i.MX53 family rev2.1 at 800 MHz
I think this is due to the fact that the clock_init is called inside board_late_init, hence it will take effect after the CPU clock is printed during boot.
I would be glad to receive some suggestion in order to get the 1GHz frequency printed during the initial boot log.
Also, still needs to support the other variant of mx53qsb with the mc34708 PMIC.
board/freescale/mx53loco/mx53loco.c | 78 +++++++++++++++++++++++++++++++++++ drivers/misc/Makefile | 1 + include/configs/mx53loco.h | 14 ++++++ 3 files changed, 93 insertions(+), 0 deletions(-)
diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index d736141..47bdf27 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -35,6 +35,8 @@ #include <mmc.h> #include <fsl_esdhc.h> #include <asm/gpio.h> +#include <pmic.h> +#include <dialog_pmic.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -290,6 +292,70 @@ int board_mmc_init(bd_t *bis) } #endif
+static void setup_iomux_i2c(void) +{ + /* I2C1 SDA */ + mxc_request_iomux(MX53_PIN_CSI0_D8, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_CSI0_D8, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + /* I2C1 SCL */ + mxc_request_iomux(MX53_PIN_CSI0_D9, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_CSI0_D9, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | + PAD_CTL_ODE_OPENDRAIN_ENABLE); +} + +static void power_init(void) +{ + unsigned int val, ret; + struct pmic *p; + + pmic_init(); + p = get_pmic(); + + /* Set VDDA to 1.25V */ + val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; + ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val); + if (!ret) + return; + + pmic_reg_read(p, DA9053_SUPPLY_REG, &val); + val |= DA9052_SUPPLY_VBCOREGO; + pmic_reg_write(p, DA9053_SUPPLY_REG, val); + /* Set Vcc peripheral to 1.35V */ + pmic_reg_write(p, 0x2f, 0x62); + pmic_reg_write(p, 0x3c, 0x62); +} + +static void clock_init(void) +{ + int ret; + u32 ref_clk = CONFIG_SYS_MX5_HCLK; + /* + * After increasing voltage to 1.25V, we can switch + * CPU clock to 1GHz and DDR to 400MHz safely + */ + ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); + if (ret) + printf("CPU: Switch CPU clock to 1GHZ failed\n"); + + ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); + ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); + if (ret) + printf("CPU: Switch DDR clock to 400MHz failed\n"); +} + int board_early_init_f(void) { setup_iomux_uart(); @@ -305,6 +371,18 @@ int board_init(void) return 0; }
+#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_I2C_MXC + setup_iomux_i2c(); + power_init(); + clock_init(); +#endif + return 0; +} +#endif + int checkboard(void) { puts("Board: MX53 LOCO\n"); diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index a709707..6511713 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -39,6 +39,7 @@ COBJS-$(CONFIG_PMIC_FSL) += pmic_fsl.o COBJS-$(CONFIG_PMIC_I2C) += pmic_i2c.o COBJS-$(CONFIG_PMIC_SPI) += pmic_spi.o COBJS-$(CONFIG_PMIC_MAX8998) += pmic_max8998.o +COBJS-$(CONFIG_DIALOG_PMIC) += pmic_dialog.o
COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 34a4edd..b58c999 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -42,6 +42,7 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT #define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART @@ -85,6 +86,19 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0
+/* I2C Configs */ +#define CONFIG_HARD_I2C +#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C_MX53_PORT1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + +/* PMIC Controller */ +#define CONFIG_PMIC +#define CONFIG_PMIC_I2C +#define CONFIG_DIALOG_PMIC +#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1
On Fri, Mar 16, 2012 at 5:21 PM, Fabio Estevam festevam@gmail.com wrote:
I would be glad to receive some suggestion in order to get the 1GHz frequency printed during the initial boot log.
If I print the frequency inside board_late_init() then I see the correct reported CPU frequency:
U-Boot 2011.12-07170-g536d7cc-dirty (Mar 16 2012 - 17:53:26)
Board: MX53 LOCO I2C: ready DRAM: 1 GiB WARNING: Caches not enabled MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial CPU: Freescale i.MX53 family rev2.1 at 1000 MHz Reset cause: POR Net: FEC Warning: failed to set MAC address
Hit any key to stop autoboot: 0 MX53LOCO U-Boot >
And the patch now looks like:
diff --git a/arch/arm/cpu/armv7/imx-common/cpu.c b/arch/arm/cpu/armv7/imx-common/cpu.c index 1e30ae5..1df29aa 100644 --- a/arch/arm/cpu/armv7/imx-common/cpu.c +++ b/arch/arm/cpu/armv7/imx-common/cpu.c @@ -34,7 +34,7 @@ #include <fsl_esdhc.h> #endif
-static char *get_reset_cause(void) +char *get_reset_cause(void) { u32 cause; struct src *src_regs = (struct src *)SRC_BASE_ADDR; diff --git a/arch/arm/include/asm/arch-mx5/sys_proto.h b/arch/arm/include/asm/arch-mx5/sys_proto.h index 13d12ee..54a8918 100644 --- a/arch/arm/include/asm/arch-mx5/sys_proto.h +++ b/arch/arm/include/asm/arch-mx5/sys_proto.h @@ -35,5 +35,6 @@ void set_chipselect_size(int const); */
int fecmxc_initialize(bd_t *bis); +char *get_reset_cause(void);
#endif diff --git a/board/freescale/mx53loco/mx53loco.c b/board/freescale/mx53loco/mx53loco.c index d736141..fbb2d63 100644 --- a/board/freescale/mx53loco/mx53loco.c +++ b/board/freescale/mx53loco/mx53loco.c @@ -35,6 +35,8 @@ #include <mmc.h> #include <fsl_esdhc.h> #include <asm/gpio.h> +#include <pmic.h> +#include <dialog_pmic.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -290,6 +292,70 @@ int board_mmc_init(bd_t *bis) } #endif
+static void setup_iomux_i2c(void) +{ + /* I2C1 SDA */ + mxc_request_iomux(MX53_PIN_CSI0_D8, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MX53_I2C1_IPP_SDA_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_CSI0_D8, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | + PAD_CTL_ODE_OPENDRAIN_ENABLE); + /* I2C1 SCL */ + mxc_request_iomux(MX53_PIN_CSI0_D9, + IOMUX_CONFIG_ALT5 | IOMUX_CONFIG_SION); + mxc_iomux_set_input(MX53_I2C1_IPP_SCL_IN_SELECT_INPUT, + INPUT_CTL_PATH0); + mxc_iomux_set_pad(MX53_PIN_CSI0_D9, + PAD_CTL_SRE_FAST | PAD_CTL_DRV_HIGH | + PAD_CTL_100K_PU | PAD_CTL_PKE_ENABLE | + PAD_CTL_PUE_PULL | + PAD_CTL_ODE_OPENDRAIN_ENABLE); +} + +static void power_init(void) +{ + unsigned int val, ret; + struct pmic *p; + + pmic_init(); + p = get_pmic(); + + /* Set VDDA to 1.25V */ + val = DA9052_BUCKCORE_BCOREEN | DA_BUCKCORE_VBCORE_1_250V; + ret = pmic_reg_write(p, DA9053_BUCKCORE_REG, val); + if (!ret) + return; + + pmic_reg_read(p, DA9053_SUPPLY_REG, &val); + val |= DA9052_SUPPLY_VBCOREGO; + pmic_reg_write(p, DA9053_SUPPLY_REG, val); + /* Set Vcc peripheral to 1.35V */ + pmic_reg_write(p, 0x2f, 0x62); + pmic_reg_write(p, 0x3c, 0x62); +} + +static void clock_init(void) +{ + int ret; + u32 ref_clk = CONFIG_SYS_MX5_HCLK; + /* + * After increasing voltage to 1.25V, we can switch + * CPU clock to 1GHz and DDR to 400MHz safely + */ + ret = mxc_set_clock(ref_clk, 1000, MXC_ARM_CLK); + if (ret) + printf("CPU: Switch CPU clock to 1GHZ failed\n"); + + ret = mxc_set_clock(ref_clk, 400, MXC_PERIPH_CLK); + ret |= mxc_set_clock(ref_clk, 400, MXC_DDR_CLK); + if (ret) + printf("CPU: Switch DDR clock to 400MHz failed\n"); +} + int board_early_init_f(void) { setup_iomux_uart(); @@ -305,6 +371,33 @@ int board_init(void) return 0; }
+int print_cpuinfo(void) +{ + u32 cpurev; + + cpurev = get_cpu_rev(); + printf("CPU: Freescale i.MX%x family rev%d.%d at %d MHz\n", + (cpurev & 0xFF000) >> 12, + (cpurev & 0x000F0) >> 4, + (cpurev & 0x0000F) >> 0, + mxc_get_clock(MXC_ARM_CLK) / 1000000); + printf("Reset cause: %s\n", get_reset_cause()); + return 0; +} + +#ifdef CONFIG_BOARD_LATE_INIT +int board_late_init(void) +{ +#ifdef CONFIG_I2C_MXC + setup_iomux_i2c(); + power_init(); + clock_init(); +#endif + print_cpuinfo(); + return 0; +} +#endif + int checkboard(void) { puts("Board: MX53 LOCO\n"); diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile index a709707..6511713 100644 --- a/drivers/misc/Makefile +++ b/drivers/misc/Makefile @@ -39,6 +39,7 @@ COBJS-$(CONFIG_PMIC_FSL) += pmic_fsl.o COBJS-$(CONFIG_PMIC_I2C) += pmic_i2c.o COBJS-$(CONFIG_PMIC_SPI) += pmic_spi.o COBJS-$(CONFIG_PMIC_MAX8998) += pmic_max8998.o +COBJS-$(CONFIG_DIALOG_PMIC) += pmic_dialog.o
COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/include/configs/mx53loco.h b/include/configs/mx53loco.h index 34a4edd..143b078 100644 --- a/include/configs/mx53loco.h +++ b/include/configs/mx53loco.h @@ -27,7 +27,6 @@
#define CONFIG_SYS_MX5_HCLK 24000000 #define CONFIG_SYS_MX5_CLK32 32768 -#define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO
#define CONFIG_MACH_TYPE MACH_TYPE_MX53_LOCO @@ -42,6 +41,7 @@ #define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + 2 * 1024 * 1024)
#define CONFIG_BOARD_EARLY_INIT_F +#define CONFIG_BOARD_LATE_INIT #define CONFIG_MXC_GPIO
#define CONFIG_MXC_UART @@ -85,6 +85,19 @@ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0
+/* I2C Configs */ +#define CONFIG_HARD_I2C +#define CONFIG_I2C_MXC +#define CONFIG_SYS_I2C_MX53_PORT1 +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0xfe + +/* PMIC Controller */ +#define CONFIG_PMIC +#define CONFIG_PMIC_I2C +#define CONFIG_DIALOG_PMIC +#define CONFIG_SYS_DIALOG_PMIC_I2C_ADDR 0x48 + /* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE #define CONFIG_CONS_INDEX 1
Am 16/03/2012 22:01, schrieb Fabio Estevam:
On Fri, Mar 16, 2012 at 5:21 PM, Fabio Estevam festevam@gmail.com wrote:
I would be glad to receive some suggestion in order to get the 1GHz frequency printed during the initial boot log.
If I print the frequency inside board_late_init() then I see the correct reported CPU frequency:
U-Boot 2011.12-07170-g536d7cc-dirty (Mar 16 2012 - 17:53:26)
Board: MX53 LOCO I2C: ready DRAM: 1 GiB WARNING: Caches not enabled MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial CPU: Freescale i.MX53 family rev2.1 at 1000 MHz Reset cause: POR Net: FEC Warning: failed to set MAC address
Hit any key to stop autoboot: 0 MX53LOCO U-Boot >
And the patch now looks like:
I do not see pmic_dialog.c and where the constants for dialog are definded. Have I missed another patch ?
Stefano
On Sat, Mar 17, 2012 at 5:23 AM, stefano babic sbabic@denx.de wrote:
I do not see pmic_dialog.c and where the constants for dialog are definded. Have I missed another patch ?
Sorry, I missed to do "git add" for these files. On this RFC I am mainly interested in getting feedback about the reported CPU frequency.
Would it be OK to delay printing the CPU info like that?
U-Boot 2011.12-07170-g536d7cc-dirty (Mar 16 2012 - 17:53:26)
Board: MX53 LOCO I2C: ready DRAM: 1 GiB WARNING: Caches not enabled MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial CPU: Freescale i.MX53 family rev2.1 at 1000 MHz Reset cause: POR Net: FEC Warning: failed to set MAC address
I am printing CPU frequency inside board_late_init because in order to run at 1GHz we need to setup the proper voltages for 1GHz operation, change the ARM CPU clock to 1GHz and then print ut.
Let me know if this is OK and I will submita new version of this patch.
Thanks,
Fabio Estevam
Am 17/03/2012 15:30, schrieb Fabio Estevam:
On Sat, Mar 17, 2012 at 5:23 AM, stefano babic sbabic@denx.de wrote:
Hi Fabio,
I do not see pmic_dialog.c and where the constants for dialog are definded. Have I missed another patch ?
Sorry, I missed to do "git add" for these files. On this RFC I am mainly interested in getting feedback about the reported CPU frequency.
Would it be OK to delay printing the CPU info like that?
Personally, I think it is more important that the printed values *are* correct rather than the output has always the same format. IMHO it is ok if the CPU info is printed later, as you suggest. And we cannot do as usual because we need I2C to set the CPU voltage, and I2C is not initialized before relocation.
However, this is an exception in U-Boot, and I have added Wolfgang in CC to let him know we want to change slightly the default output format, at least for this board.
U-Boot 2011.12-07170-g536d7cc-dirty (Mar 16 2012 - 17:53:26)
Board: MX53 LOCO I2C: ready DRAM: 1 GiB WARNING: Caches not enabled MMC: FSL_SDHC: 0, FSL_SDHC: 1 In: serial Out: serial Err: serial CPU: Freescale i.MX53 family rev2.1 at 1000 MHz Reset cause: POR Net: FEC Warning: failed to set MAC address
I am printing CPU frequency inside board_late_init because in order to run at 1GHz we need to setup the proper voltages for 1GHz operation, change the ARM CPU clock to 1GHz and then print ut.
Let me know if this is OK and I will submita new version of this patch.
No problem on my side, and we are fixing a real issue (CPU working with 800 instead of 1000 Mhz).
Best regards, Stefano Babic
On 16/03/2012 21:21, Fabio Estevam wrote:
From: Jason Liu jason.hui@linaro.org
mx5: Add clock config interface
Hi Fabio,
Add clock config interface support, so that we can configure CPU or DDR clock in the later init
Signed-off-by: Jason Liu jason.hui@linaro.org Signed-off-by: Eric Miao eric.miao@linaro.org
My personal quote: this seems to introduce several changes as the clocks are computed - my personal feeling is that this patch will go into the -next branch.
diff --git a/arch/arm/cpu/armv7/mx5/clock.c b/arch/arm/cpu/armv7/mx5/clock.c index e92f106..c7613f0 100644 --- a/arch/arm/cpu/armv7/mx5/clock.c +++ b/arch/arm/cpu/armv7/mx5/clock.c @@ -24,6 +24,7 @@ */
#include <common.h> +#include <div64.h> #include <asm/io.h> #include <asm/errno.h> #include <asm/arch/imx-regs.h> @@ -48,6 +49,39 @@ struct mxc_pll_reg *mxc_plls[PLL_CLOCKS] = { #endif };
+#define AHB_CLK_ROOT 133333333 +#define SZ_DEC_1M 1000000 +#define PLL_PD_MAX 16 /* Actual pd+1 */ +#define PLL_MFI_MAX 15 +#define PLL_MFI_MIN 5 +#define ARM_DIV_MAX 8 +#define IPG_DIV_MAX 4 +#define AHB_DIV_MAX 8 +#define EMI_DIV_MAX 8 +#define NFC_DIV_MAX 8
+struct fixed_pll_mfd {
- u32 ref_clk_hz;
- u32 mfd;
+};
+const struct fixed_pll_mfd fixed_mfd[] = {
- {CONFIG_SYS_MX5_HCLK, 24 * 16},
+};
+struct pll_param {
- u32 pd;
- u32 mfi;
- u32 mfn;
- u32 mfd;
+};
+#define PLL_FREQ_MAX(ref_clk) (4 * (ref_clk) * PLL_MFI_MAX) +#define PLL_FREQ_MIN(ref_clk) \
((2 * (ref_clk) * (PLL_MFI_MIN - 1)) / PLL_PD_MAX)+#define MAX_DDR_CLK 420000000 +#define NFC_CLK_MAX 34000000
struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)MXC_CCM_BASE;
void set_usboh3_clk(void) @@ -212,20 +246,13 @@ static u32 get_periph_clk(void) /* NOTREACHED */ }
-/*
- Get the rate of ahb clock.
- */
static u32 get_ahb_clk(void) {
- uint32_t freq, div, reg;
- u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
- u32 pdf = (cbcdr & MXC_CCM_CBCDR_AHB_PODF_MASK) \
>> MXC_CCM_CBCDR_AHB_PODF_OFFSET;
- freq = get_periph_clk();
- reg = __raw_readl(&mxc_ccm->cbcdr);
- div = ((reg & MXC_CCM_CBCDR_AHB_PODF_MASK) >>
MXC_CCM_CBCDR_AHB_PODF_OFFSET) + 1;- return freq / div;
- return get_periph_clk() / (pdf + 1);
A good occasion to factorize with mx6 code. What about to move the function into arch/arm/cpu/armv7/imx-common/ ?
}
/* @@ -306,7 +333,7 @@ static u32 get_uart_clk(void) /*
- This function returns the low power audio clock.
*/ -u32 get_lp_apm(void) +static u32 get_lp_apm(void)
Right, all internal functions should be static - thanks for fixing it.
+static u32 get_axi_a_clk(void) +{
- u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
- u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_A_PODF_MASK) \
>> MXC_CCM_CBCDR_AXI_A_PODF_OFFSET;- return get_periph_clk() / (pdf + 1);
+}
+static u32 get_axi_b_clk(void) +{
- u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
- u32 pdf = (cbcdr & MXC_CCM_CBCDR_AXI_B_PODF_MASK) \
>> MXC_CCM_CBCDR_AXI_B_PODF_OFFSET;- return get_periph_clk() / (pdf + 1);
+}
+static u32 get_emi_slow_clk(void) +{
- u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
- u32 emi_clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
- u32 pdf = (cbcdr & MXC_CCM_CBCDR_EMI_PODF_MASK) \
>> MXC_CCM_CBCDR_EMI_PODF_OFFSET;- if (emi_clk_sel)
return get_ahb_clk() / (pdf + 1);- return get_periph_clk() / (pdf + 1);
+}
+static u32 get_nfc_clk(void) +{
- u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
- u32 pdf = (cbcdr & MXC_CCM_CBCDR_NFC_PODF_MASK) \
>> MXC_CCM_CBCDR_NFC_PODF_OFFSET;- return get_emi_slow_clk() / (pdf + 1);
+}
+static u32 get_ddr_clk(void) +{
- u32 ret_val = 0;
- u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
- u32 ddr_clk_sel = (cbcmr & MXC_CCM_CBCMR_DDR_CLK_SEL_MASK) \
>> MXC_CCM_CBCMR_DDR_CLK_SEL_OFFSET;+#ifdef CONFIG_MX51
- u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
- if (cbcdr & MXC_CCM_CBCDR_DDR_HIFREQ_SEL) {
u32 ddr_clk_podf = (cbcdr & MXC_CCM_CBCDR_DDR_PODF_MASK) >> \MXC_CCM_CBCDR_DDR_PODF_OFFSET;ret_val = decode_pll(mxc_plls[PLL1_CLOCK], CONFIG_SYS_MX5_HCLK);ret_val /= ddr_clk_podf + 1;return ret_val;- }
+#endif
- switch (ddr_clk_sel) {
- case 0:
ret_val = get_axi_a_clk();break;- case 1:
ret_val = get_axi_b_clk();break;- case 2:
ret_val = get_emi_slow_clk();break;- case 3:
ret_val = get_ahb_clk();break;- default:
break;- }
- return ret_val;
+}
/*
- The API of get mxc clockes.
*/ @@ -376,10 +482,12 @@ unsigned int mxc_get_clock(enum mxc_clock clk) case MXC_UART_CLK: return get_uart_clk(); case MXC_CSPI_CLK:
return imx_get_cspiclk();
return get_cspi_clk();- case MXC_DDR_CLK:
return get_ddr_clk();@@ -398,6 +506,424 @@ u32 imx_get_fecclk(void) }
/*
- Clock config code start here
- */
+/* precondition: m>0 and n>0. Let g=gcd(m,n). */ +static int gcd(int m, int n) +{
- int t;
- while (m > 0) {
if (n > m) {t = m;m = n;n = t;} /* swap */m -= n;- }
- return n;
+}
+/*
- This is to calculate various parameters based on reference clock and
- targeted clock based on the equation:
t_clk = 2*ref_freq*(mfi + mfn/(mfd+1))/(pd+1)
- This calculation is based on a fixed MFD value for simplicity.
- @param ref reference clock freq in Hz
- @param target targeted clock in Hz
- @param pll pll_param structure.
We have not doxygen in all u-boot code and this function remains an exception. So you can drop all @statements. This should be fixed globally.
- }
- /* Now got pd and mfi already */
- /*
- mfn = (((n_target * pd) / 4 - n_ref * mfi) * mfd) / n_ref;
- */
Dead code ?
- t1 = n_target * pd;
- do_div(t1, 4);
- t1 -= n_ref * mfi;
- t1 *= mfd;
- do_div(t1, n_ref);
- mfn = t1;
+#ifdef CMD_CLOCK_DEBUG
- printf("ref=%d, target=%d, pd=%d," "mfi=%d,mfn=%d, mfd=%d\n",
ref, n_target, (u32)pd, (u32)mfi, (u32)mfn, (u32)mfd);
What is CMD_CLOCK_DEBUG ? I think it is enough if you replace printf() with debug()
+static u32 calc_per_cbcdr_val(u32 per_clk) +{
- u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
- u32 tmp_clk = 0, div = 0, clk_sel = 0;
- cbcdr &= ~MXC_CCM_CBCDR_PERIPH_CLK_SEL;
- /* emi_slow_podf divider */
- tmp_clk = get_emi_slow_clk();
- clk_sel = cbcdr & MXC_CCM_CBCDR_EMI_CLK_SEL;
- if (clk_sel) {
div = calc_div(tmp_clk, per_clk, 8);cbcdr &= ~MXC_CCM_CBCDR_EMI_PODF_MASK;cbcdr |= (div << MXC_CCM_CBCDR_EMI_PODF_OFFSET);- }
- /* axi_b_podf divider */
- tmp_clk = get_axi_b_clk();
- div = calc_div(tmp_clk, per_clk, 8);
- cbcdr &= ~MXC_CCM_CBCDR_AXI_B_PODF_MASK;
- cbcdr |= (div << MXC_CCM_CBCDR_AXI_B_PODF_OFFSET);
- /* axi_b_podf divider */
- tmp_clk = get_axi_a_clk();
- div = calc_div(tmp_clk, per_clk, 8);
- cbcdr &= ~MXC_CCM_CBCDR_AXI_A_PODF_MASK;
- cbcdr |= (div << MXC_CCM_CBCDR_AXI_A_PODF_OFFSET);
- /* ahb podf divider */
- tmp_clk = AHB_CLK_ROOT;
- div = calc_div(tmp_clk, per_clk, 8);
- cbcdr &= ~MXC_CCM_CBCDR_AHB_PODF_MASK;
- cbcdr |= (div << MXC_CCM_CBCDR_AHB_PODF_OFFSET);
- return cbcdr;
+}
+#define CHANGE_PLL_SETTINGS(pll, pd, fi, fn, fd) \
- { \
__raw_writel(0x1232, &pll->ctrl); \__raw_writel(0x2, &pll->config); \__raw_writel((((pd) - 1) << 0) | ((fi) << 4), \&pll->op); \__raw_writel(fn, &(pll->mfn)); \__raw_writel((fd) - 1, &pll->mfd); \__raw_writel((((pd) - 1) << 0) | ((fi) << 4), \&pll->hfs_op); \__raw_writel(fn, &pll->hfs_mfn); \__raw_writel((fd) - 1, &pll->hfs_mfd); \__raw_writel(0x1232, &pll->ctrl); \while (!__raw_readl(&pll->ctrl) & 0x1) \;\- }
+static int config_pll_clk(enum pll_clocks index, struct pll_param *pll_param) +{
- u32 ccsr = __raw_readl(&mxc_ccm->ccsr);
- struct mxc_pll_reg *pll = mxc_plls[index];
- switch (index) {
- case PLL1_CLOCK:
/* Switch ARM to PLL2 clock */__raw_writel(ccsr | 0x4, &mxc_ccm->ccsr);CHANGE_PLL_SETTINGS(pll, pll_param->pd,pll_param->mfi, pll_param->mfn,pll_param->mfd);/* Switch back */__raw_writel(ccsr & ~0x4, &mxc_ccm->ccsr);break;- case PLL2_CLOCK:
/* Switch to pll2 bypass clock */__raw_writel(ccsr | 0x2, &mxc_ccm->ccsr);CHANGE_PLL_SETTINGS(pll, pll_param->pd,pll_param->mfi, pll_param->mfn,pll_param->mfd);/* Switch back */__raw_writel(ccsr & ~0x2, &mxc_ccm->ccsr);break;- case PLL3_CLOCK:
/* Switch to pll3 bypass clock */__raw_writel(ccsr | 0x1, &mxc_ccm->ccsr);CHANGE_PLL_SETTINGS(pll, pll_param->pd,pll_param->mfi, pll_param->mfn,pll_param->mfd);/* Switch back */__raw_writel(ccsr & ~0x1, &mxc_ccm->ccsr);break;- case PLL4_CLOCK:
/* Switch to pll4 bypass clock */__raw_writel(ccsr | 0x20, &mxc_ccm->ccsr);CHANGE_PLL_SETTINGS(pll, pll_param->pd,pll_param->mfi, pll_param->mfn,pll_param->mfd);/* Switch back */__raw_writel(ccsr & ~0x20, &mxc_ccm->ccsr);break;- default:
return -1;- }
- return 0;
+}
+/* Config CPU clock */ +static int config_core_clk(u32 ref, u32 freq) +{
- int ret = 0;
- struct pll_param pll_param;
- memset(&pll_param, 0, sizeof(struct pll_param));
- /* The case that periph uses PLL1 is not considered here */
- ret = calc_pll_params(ref, freq, &pll_param);
- if (ret != 0) {
printf("Error:Can't find pll parameters: %d\n", ret);return ret;- }
- return config_pll_clk(PLL1_CLOCK, &pll_param);
+}
+static int config_nfc_clk(u32 nfc_clk) +{
- u32 reg;
- u32 parent_rate = get_emi_slow_clk();
- u32 div = parent_rate / nfc_clk;
- if (nfc_clk <= 0)
return -1;- if (div == 0)
div++;- if (parent_rate / div > NFC_CLK_MAX)
div++;- reg = __raw_readl(&mxc_ccm->cbcdr);
- reg &= ~MXC_CCM_CBCDR_NFC_PODF_MASK;
- reg |= (div - 1) << MXC_CCM_CBCDR_NFC_PODF_OFFSET;
- __raw_writel(reg, &mxc_ccm->cbcdr);
- while (__raw_readl(&mxc_ccm->cdhipr) != 0)
;- return 0;
+}
+/* Config main_bus_clock for periphs */ +static int config_periph_clk(u32 ref, u32 freq) +{
- int ret = 0;
- struct pll_param pll_param;
- memset(&pll_param, 0, sizeof(struct pll_param));
- if (__raw_readl(&mxc_ccm->cbcdr) & MXC_CCM_CBCDR_PERIPH_CLK_SEL) {
ret = calc_pll_params(ref, freq, &pll_param);if (ret != 0) {printf("Error:Can't find pll parameters: %d\n",ret);return ret;}switch ((__raw_readl(&mxc_ccm->cbcmr) & \MXC_CCM_CBCMR_PERIPH_CLK_SEL_MASK) >> \MXC_CCM_CBCMR_PERIPH_CLK_SEL_OFFSET) {case 0:return config_pll_clk(PLL1_CLOCK, &pll_param);break;case 1:return config_pll_clk(PLL3_CLOCK, &pll_param);break;default:return -1;}- } else {
u32 old_cbcmr = __raw_readl(&mxc_ccm->cbcmr);u32 new_cbcdr = calc_per_cbcdr_val(freq);u32 old_nfc = get_nfc_clk();/* Switch peripheral to PLL3 */__raw_writel(0x00015154, &mxc_ccm->cbcmr);__raw_writel(0x02888945, &mxc_ccm->cbcdr);
Can we set constants for these ?
/* Make sure change is effective */while (__raw_readl(&mxc_ccm->cdhipr) != 0);/* Setup PLL2 */ret = calc_pll_params(ref, freq, &pll_param);if (ret != 0) {printf("Error:Can't find pll parameters: %d\n",ret);return ret;}config_pll_clk(PLL2_CLOCK, &pll_param);/* Switch peripheral back */__raw_writel(new_cbcdr, &mxc_ccm->cbcdr);__raw_writel(old_cbcmr, &mxc_ccm->cbcmr);/* Make sure change is effective */while (__raw_readl(&mxc_ccm->cdhipr) != 0);/* restore to old NFC clock */config_nfc_clk(old_nfc);- }
- return 0;
+}
+static int config_ddr_clk(u32 emi_clk) +{
- u32 clk_src;
- s32 shift = 0, clk_sel, div = 1;
- u32 cbcmr = __raw_readl(&mxc_ccm->cbcmr);
- u32 cbcdr = __raw_readl(&mxc_ccm->cbcdr);
- if (emi_clk > MAX_DDR_CLK) {
printf("Warning:DDR clock should not exceed %d MHz\n",MAX_DDR_CLK / SZ_DEC_1M);emi_clk = MAX_DDR_CLK;- }
- clk_src = get_periph_clk();
- /* Find DDR clock input */
- clk_sel = (cbcmr >> 10) & 0x3;
- switch (clk_sel) {
- case 0:
shift = 16;break;- case 1:
shift = 19;break;- case 2:
shift = 22;break;- case 3:
shift = 10;break;- default:
return -1;- }
- if ((clk_src % emi_clk) < 10000000)
div = clk_src / emi_clk;- else
div = (clk_src / emi_clk) + 1;- if (div > 8)
div = 8;- cbcdr = cbcdr & ~(0x7 << shift);
- cbcdr |= ((div - 1) << shift);
- __raw_writel(cbcdr, &mxc_ccm->cbcdr);
- while (__raw_readl(&mxc_ccm->cdhipr) != 0)
;- __raw_writel(0x0, &mxc_ccm->ccdr);
- return 0;
+}
+/*!
Drop the "!"
Best regards, Stefano Babic
participants (3)
-
Fabio Estevam -
Stefano Babic -
stefano babic