[PATCH 0/2] Add MNT Reform 2 board support
The MNT Reform 2 is a modular DIY laptop. In its initial version it is based on the BoundaryDevices i.MX8MQ SoM. Some parts have been lifted from BoundaryDevices official U-Boot downstream project.
The device tree has not yet been merged into mainline Linux, but it's already available as v4 on the Linux ARM Kernel Architecture mailing list, which hopefully will now be merged as is.
This U-Boot patchset supports the serial console, the SD card and eMMC, and Gigabit Ethernet.
Best regards, Patrick
Patrick Wildt (2): arm: dts: imx8mq: add MNT Reform 2 board: mntre: imx8mq: Add MNT Reform 2 board support
arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi | 11 + arch/arm/dts/imx8mq-mnt-reform2.dts | 164 +++ arch/arm/dts/imx8mq-nitrogen-som.dtsi | 275 +++++ arch/arm/mach-imx/imx8m/Kconfig | 6 + board/mntre/imx8mq_reform2/Kconfig | 12 + board/mntre/imx8mq_reform2/MAINTAINERS | 7 + board/mntre/imx8mq_reform2/Makefile | 12 + board/mntre/imx8mq_reform2/imx8mq_reform2.c | 215 ++++ board/mntre/imx8mq_reform2/lpddr4_timing.c | 1014 +++++++++++++++++ .../mntre/imx8mq_reform2/lpddr4_timing_ch2.h | 95 ++ board/mntre/imx8mq_reform2/spl.c | 260 +++++ configs/imx8mq_reform2_defconfig | 56 + include/configs/imx8mq_reform2.h | 149 +++ 14 files changed, 2277 insertions(+) create mode 100644 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi create mode 100644 arch/arm/dts/imx8mq-mnt-reform2.dts create mode 100644 arch/arm/dts/imx8mq-nitrogen-som.dtsi create mode 100644 board/mntre/imx8mq_reform2/Kconfig create mode 100644 board/mntre/imx8mq_reform2/MAINTAINERS create mode 100644 board/mntre/imx8mq_reform2/Makefile create mode 100644 board/mntre/imx8mq_reform2/imx8mq_reform2.c create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing.c create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h create mode 100644 board/mntre/imx8mq_reform2/spl.c create mode 100644 configs/imx8mq_reform2_defconfig create mode 100644 include/configs/imx8mq_reform2.h
Device tree taken from v4 of the MNT Reform 2 series on the Linux ARM Kernel Architecture mailing list:
https://patchwork.kernel.org/project/linux-arm-kernel/list/?series=500045
Signed-off-by: Patrick Wildt patrick@blueri.se --- arch/arm/dts/Makefile | 1 + arch/arm/dts/imx8mq-mnt-reform2.dts | 164 +++++++++++++++ arch/arm/dts/imx8mq-nitrogen-som.dtsi | 275 ++++++++++++++++++++++++++ 3 files changed, 440 insertions(+) create mode 100644 arch/arm/dts/imx8mq-mnt-reform2.dts create mode 100644 arch/arm/dts/imx8mq-nitrogen-som.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 59d8078558..e01924c797 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -873,6 +873,7 @@ dtb-$(CONFIG_ARCH_IMX8M) += \ imx8mq-evk.dtb \ imx8mm-beacon-kit.dtb \ imx8mn-beacon-kit.dtb \ + imx8mq-mnt-reform2.dtb \ imx8mq-phanbell.dtb \ imx8mp-evk.dtb \ imx8mp-phyboard-pollux-rdk.dtb \ diff --git a/arch/arm/dts/imx8mq-mnt-reform2.dts b/arch/arm/dts/imx8mq-mnt-reform2.dts new file mode 100644 index 0000000000..099b0472db --- /dev/null +++ b/arch/arm/dts/imx8mq-mnt-reform2.dts @@ -0,0 +1,164 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) + +/* + * Copyright 2019-2021 MNT Research GmbH + * Copyright 2021 Lucas Stach dev@lynxeye.de + */ + +/dts-v1/; + +#include "imx8mq-nitrogen-som.dtsi" + +/ { + model = "MNT Reform 2"; + compatible = "mntre,reform2", "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq"; + + pcie1_refclk: clock-pcie1-refclk { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <100000000>; + }; + + reg_main_5v: regulator-main-5v { + compatible = "regulator-fixed"; + regulator-name = "5V"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_main_3v3: regulator-main-3v3 { + compatible = "regulator-fixed"; + regulator-name = "3V3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + + reg_main_usb: regulator-main-usb { + compatible = "regulator-fixed"; + regulator-name = "USB_PWR"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + vin-supply = <®_main_5v>; + }; +}; + +&fec1 { + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + rtc@68 { + compatible = "nxp,pcf8523"; + reg = <0x68>; + }; +}; + +&pcie1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pcie1>; + reset-gpio = <&gpio3 23 GPIO_ACTIVE_LOW>; + clocks = <&clk IMX8MQ_CLK_PCIE2_ROOT>, + <&clk IMX8MQ_CLK_PCIE2_AUX>, + <&clk IMX8MQ_CLK_PCIE2_PHY>, + <&pcie1_refclk>; + clock-names = "pcie", "pcie_aux", "pcie_phy", "pcie_bus"; + status = "okay"; +}; + +®_1p8v { + vin-supply = <®_main_5v>; +}; + +®_snvs { + vin-supply = <®_main_5v>; +}; + +®_arm_dram { + vin-supply = <®_main_5v>; +}; + +®_dram_1p1v { + vin-supply = <®_main_5v>; +}; + +®_soc_gpu_vpu { + vin-supply = <®_main_5v>; +}; + +&snvs_rtc { + status = "disabled"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&usb3_phy0 { + vbus-supply = <®_main_usb>; + status = "okay"; +}; + +&usb3_phy1 { + vbus-supply = <®_main_usb>; + status = "okay"; +}; + +&usb_dwc3_0 { + dr_mode = "host"; + status = "okay"; +}; + +&usb_dwc3_1 { + dr_mode = "host"; + status = "okay"; +}; + +&usdhc2 { + assigned-clocks = <&clk IMX8MQ_CLK_USDHC2>; + assigned-clock-rates = <200000000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + vqmmc-supply = <®_main_3v3>; + vmmc-supply = <®_main_3v3>; + bus-width = <4>; + status = "okay"; +}; + +&iomuxc { + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C3_SCL_I2C3_SCL 0x4000007f + MX8MQ_IOMUXC_I2C3_SDA_I2C3_SDA 0x4000007f + >; + }; + + pinctrl_pcie1: pcie1grp { + fsl,pins = < + MX8MQ_IOMUXC_SAI5_RXD2_GPIO3_IO23 0x16 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX8MQ_IOMUXC_UART2_RXD_UART2_DCE_RX 0x45 + MX8MQ_IOMUXC_UART2_TXD_UART2_DCE_TX 0x45 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX8MQ_IOMUXC_SD2_CLK_USDHC2_CLK 0x83 + MX8MQ_IOMUXC_SD2_CMD_USDHC2_CMD 0xc3 + MX8MQ_IOMUXC_SD2_DATA0_USDHC2_DATA0 0xc3 + MX8MQ_IOMUXC_SD2_DATA1_USDHC2_DATA1 0xc3 + MX8MQ_IOMUXC_SD2_DATA2_USDHC2_DATA2 0xc3 + MX8MQ_IOMUXC_SD2_DATA3_USDHC2_DATA3 0xc3 + >; + }; +}; diff --git a/arch/arm/dts/imx8mq-nitrogen-som.dtsi b/arch/arm/dts/imx8mq-nitrogen-som.dtsi new file mode 100644 index 0000000000..36fc428ebe --- /dev/null +++ b/arch/arm/dts/imx8mq-nitrogen-som.dtsi @@ -0,0 +1,275 @@ +// SPDX-License-Identifier: (GPL-2.0+ OR MIT) +/* + * Copyright 2018 Boundary Devices + * Copyright 2021 Lucas Stach dev@lynxeye.de + */ + +#include "imx8mq.dtsi" + +/ { + model = "Boundary Devices i.MX8MQ Nitrogen8M"; + compatible = "boundary,imx8mq-nitrogen8m-som", "fsl,imx8mq"; + + chosen { + stdout-path = &uart1; + }; + + reg_1p8v: regulator-fixed-1v8 { + compatible = "regulator-fixed"; + regulator-name = "1P8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + reg_snvs: regulator-fixed-snvs { + compatible = "regulator-fixed"; + regulator-name = "VDD_SNVS"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; +}; + +&{/opp-table/opp-800000000} { + opp-microvolt = <1000000>; +}; + +&{/opp-table/opp-1000000000} { + opp-microvolt = <1000000>; +}; + +&A53_0 { + cpu-supply = <®_arm_dram>; +}; + +&A53_1 { + cpu-supply = <®_arm_dram>; +}; + +&A53_2 { + cpu-supply = <®_arm_dram>; +}; + +&A53_3 { + cpu-supply = <®_arm_dram>; +}; + +&fec1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_fec1>; + phy-mode = "rgmii-id"; + phy-handle = <ðphy0>; + fsl,magic-packet; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + + ethphy0: ethernet-phy@4 { + compatible = "ethernet-phy-ieee802.3-c22"; + reg = <4>; + interrupt-parent = <&gpio1>; + interrupts = <11 IRQ_TYPE_LEVEL_LOW>; + }; + }; +}; + +&i2c1 { + clock-frequency = <400000>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + i2c-mux@70 { + compatible = "nxp,pca9546"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1_pca9546>; + reg = <0x70>; + reset-gpios = <&gpio1 8 GPIO_ACTIVE_LOW>; + #address-cells = <1>; + #size-cells = <0>; + + i2c1a: i2c@0 { + reg = <0>; + #address-cells = <1>; + #size-cells = <0>; + + reg_arm_dram: regulator@60 { + compatible = "fcs,fan53555"; + reg = <0x60>; + regulator-name = "VDD_ARM_DRAM_1V"; + regulator-min-microvolt = <1000000>; + regulator-max-microvolt = <1000000>; + regulator-always-on; + }; + }; + + i2c1b: i2c@1 { + reg = <1>; + #address-cells = <1>; + #size-cells = <0>; + + reg_dram_1p1v: regulator@60 { + compatible = "fcs,fan53555"; + reg = <0x60>; + regulator-name = "NVCC_DRAM_1P1V"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + regulator-always-on; + }; + }; + + i2c1c: i2c@2 { + reg = <2>; + #address-cells = <1>; + #size-cells = <0>; + + reg_soc_gpu_vpu: regulator@60 { + compatible = "fcs,fan53555"; + reg = <0x60>; + regulator-name = "VDD_SOC_GPU_VPU"; + regulator-min-microvolt = <900000>; + regulator-max-microvolt = <900000>; + regulator-always-on; + }; + }; + + i2c1d: i2c@3 { + reg = <3>; + #address-cells = <1>; + #size-cells = <0>; + }; + }; +}; + +&pgc_gpu { + power-supply = <®_soc_gpu_vpu>; +}; + +&pgc_vpu { + power-supply = <®_soc_gpu_vpu>; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + status = "okay"; +}; + +&usdhc1 { + assigned-clocks = <&clk IMX8MQ_CLK_USDHC1>; + assigned-clock-rates = <400000000>; + pinctrl-names = "default", "state_100mhz", "state_200mhz"; + pinctrl-0 = <&pinctrl_usdhc1>; + pinctrl-1 = <&pinctrl_usdhc1_100mhz>; + pinctrl-2 = <&pinctrl_usdhc1_200mhz>; + vqmmc-supply = <®_1p8v>; + vmmc-supply = <®_snvs>; + bus-width = <8>; + non-removable; + no-mmc-hs400; + no-sdio; + no-sd; + status = "okay"; +}; + +&wdog1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_wdog>; + fsl,ext-reset-output; + status = "okay"; +}; + +&iomuxc { + pinctrl_fec1: fec1grp { + fsl,pins = < + MX8MQ_IOMUXC_ENET_MDC_ENET1_MDC 0x3 + MX8MQ_IOMUXC_ENET_MDIO_ENET1_MDIO 0x23 + MX8MQ_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL 0x1f + MX8MQ_IOMUXC_ENET_TXC_ENET1_RGMII_TXC 0x1f + MX8MQ_IOMUXC_ENET_TD0_ENET1_RGMII_TD0 0x1f + MX8MQ_IOMUXC_ENET_TD1_ENET1_RGMII_TD1 0x1f + MX8MQ_IOMUXC_ENET_TD2_ENET1_RGMII_TD2 0x1f + MX8MQ_IOMUXC_ENET_TD3_ENET1_RGMII_TD3 0x1f + MX8MQ_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL 0x91 + MX8MQ_IOMUXC_ENET_RXC_ENET1_RGMII_RXC 0x91 + MX8MQ_IOMUXC_ENET_RD0_ENET1_RGMII_RD0 0x91 + MX8MQ_IOMUXC_ENET_RD1_ENET1_RGMII_RD1 0x91 + MX8MQ_IOMUXC_ENET_RD2_ENET1_RGMII_RD2 0x91 + MX8MQ_IOMUXC_ENET_RD3_ENET1_RGMII_RD3 0x91 + MX8MQ_IOMUXC_GPIO1_IO09_GPIO1_IO9 0x19 + MX8MQ_IOMUXC_GPIO1_IO11_GPIO1_IO11 0x59 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX8MQ_IOMUXC_I2C1_SCL_I2C1_SCL 0x4000007f + MX8MQ_IOMUXC_I2C1_SDA_I2C1_SDA 0x4000007f + >; + }; + + pinctrl_i2c1_pca9546: i2c1-pca9546grp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO08_GPIO1_IO8 0x49 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX8MQ_IOMUXC_UART1_RXD_UART1_DCE_RX 0x45 + MX8MQ_IOMUXC_UART1_TXD_UART1_DCE_TX 0x45 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x83 + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xc3 + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xc3 + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xc3 + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xc3 + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xc3 + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xc3 + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xc3 + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xc3 + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xc3 + MX8MQ_IOMUXC_SD1_RESET_B_USDHC1_RESET_B 0xc1 + >; + }; + + pinctrl_usdhc1_100mhz: usdhc1-100mhzgrp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x8d + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xcd + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xcd + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xcd + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xcd + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xcd + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xcd + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xcd + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xcd + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xcd + >; + }; + + pinctrl_usdhc1_200mhz: usdhc1-200mhzgrp { + fsl,pins = < + MX8MQ_IOMUXC_SD1_CLK_USDHC1_CLK 0x9f + MX8MQ_IOMUXC_SD1_CMD_USDHC1_CMD 0xdf + MX8MQ_IOMUXC_SD1_DATA0_USDHC1_DATA0 0xdf + MX8MQ_IOMUXC_SD1_DATA1_USDHC1_DATA1 0xdf + MX8MQ_IOMUXC_SD1_DATA2_USDHC1_DATA2 0xdf + MX8MQ_IOMUXC_SD1_DATA3_USDHC1_DATA3 0xdf + MX8MQ_IOMUXC_SD1_DATA4_USDHC1_DATA4 0xdf + MX8MQ_IOMUXC_SD1_DATA5_USDHC1_DATA5 0xdf + MX8MQ_IOMUXC_SD1_DATA6_USDHC1_DATA6 0xdf + MX8MQ_IOMUXC_SD1_DATA7_USDHC1_DATA7 0xdf + >; + }; + + pinctrl_wdog: wdoggrp { + fsl,pins = < + MX8MQ_IOMUXC_GPIO1_IO02_WDOG1_WDOG_B 0xc6 + >; + }; +};
The MNT Reform 2 is a modular DIY laptop. In its initial version it is based on the BoundaryDevices i.MX8MQ SoM. Some parts have been lifted from BoundaryDevices official U-Boot downstream project.
Signed-off-by: Patrick Wildt patrick@blueri.se --- arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi | 11 + arch/arm/mach-imx/imx8m/Kconfig | 6 + board/mntre/imx8mq_reform2/Kconfig | 12 + board/mntre/imx8mq_reform2/MAINTAINERS | 7 + board/mntre/imx8mq_reform2/Makefile | 12 + board/mntre/imx8mq_reform2/imx8mq_reform2.c | 215 ++++ board/mntre/imx8mq_reform2/lpddr4_timing.c | 1014 +++++++++++++++++ .../mntre/imx8mq_reform2/lpddr4_timing_ch2.h | 95 ++ board/mntre/imx8mq_reform2/spl.c | 260 +++++ configs/imx8mq_reform2_defconfig | 56 + include/configs/imx8mq_reform2.h | 149 +++ 11 files changed, 1837 insertions(+) create mode 100644 arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi create mode 100644 board/mntre/imx8mq_reform2/Kconfig create mode 100644 board/mntre/imx8mq_reform2/MAINTAINERS create mode 100644 board/mntre/imx8mq_reform2/Makefile create mode 100644 board/mntre/imx8mq_reform2/imx8mq_reform2.c create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing.c create mode 100644 board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h create mode 100644 board/mntre/imx8mq_reform2/spl.c create mode 100644 configs/imx8mq_reform2_defconfig create mode 100644 include/configs/imx8mq_reform2.h
diff --git a/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi new file mode 100644 index 0000000000..7e928e875b --- /dev/null +++ b/arch/arm/dts/imx8mq-mnt-reform2-u-boot.dtsi @@ -0,0 +1,11 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) + +&usdhc1 { + mmc-hs400-1_8v; +}; + +&usdhc2 { + cd-gpios = <&gpio2 12 GPIO_ACTIVE_LOW>; + sd-uhs-sdr104; + sd-uhs-ddr50; +}; diff --git a/arch/arm/mach-imx/imx8m/Kconfig b/arch/arm/mach-imx/imx8m/Kconfig index 0669363c0f..623c852ae4 100644 --- a/arch/arm/mach-imx/imx8m/Kconfig +++ b/arch/arm/mach-imx/imx8m/Kconfig @@ -44,6 +44,11 @@ config TARGET_IMX8MQ_PHANBELL select IMX8MQ select IMX8M_LPDDR4
+config TARGET_IMX8MQ_REFORM2 + bool "imx8mq_reform2" + select IMX8MQ + select IMX8M_LPDDR4 + config TARGET_IMX8MM_EVK bool "imx8mm LPDDR4 EVK board" select BINMAN @@ -149,6 +154,7 @@ source "board/freescale/imx8mn_evk/Kconfig" source "board/freescale/imx8mp_evk/Kconfig" source "board/gateworks/venice/Kconfig" source "board/google/imx8mq_phanbell/Kconfig" +source "board/mntre/imx8mq_reform2/Kconfig" source "board/phytec/phycore_imx8mm/Kconfig" source "board/phytec/phycore_imx8mp/Kconfig" source "board/ronetix/imx8mq-cm/Kconfig" diff --git a/board/mntre/imx8mq_reform2/Kconfig b/board/mntre/imx8mq_reform2/Kconfig new file mode 100644 index 0000000000..8070ef377b --- /dev/null +++ b/board/mntre/imx8mq_reform2/Kconfig @@ -0,0 +1,12 @@ +if TARGET_IMX8MQ_REFORM2 + +config SYS_BOARD + default "imx8mq_reform2" + +config SYS_VENDOR + default "mntre" + +config SYS_CONFIG_NAME + default "imx8mq_reform2" + +endif diff --git a/board/mntre/imx8mq_reform2/MAINTAINERS b/board/mntre/imx8mq_reform2/MAINTAINERS new file mode 100644 index 0000000000..946f287ecf --- /dev/null +++ b/board/mntre/imx8mq_reform2/MAINTAINERS @@ -0,0 +1,7 @@ +REFORM2 IMX8MQ BOARD +M: Lukas F. Hartmann lukas@mntre.com +M: Patrick Wildt patrick@blueri.se +S: Maintained +F: board/mntre/imx8mq_reform2/ +F: include/configs/imx8mq_reform2.h +F: configs/imx8mq_reform2_defconfig diff --git a/board/mntre/imx8mq_reform2/Makefile b/board/mntre/imx8mq_reform2/Makefile new file mode 100644 index 0000000000..2efd56bb4a --- /dev/null +++ b/board/mntre/imx8mq_reform2/Makefile @@ -0,0 +1,12 @@ +# +# Copyright 2017 NXP +# +# SPDX-License-Identifier: GPL-2.0+ +# + +obj-y += imx8mq_reform2.o + +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-$(CONFIG_IMX8M_LPDDR4) += lpddr4_timing.o +endif diff --git a/board/mntre/imx8mq_reform2/imx8mq_reform2.c b/board/mntre/imx8mq_reform2/imx8mq_reform2.c new file mode 100644 index 0000000000..c46af349eb --- /dev/null +++ b/board/mntre/imx8mq_reform2/imx8mq_reform2.c @@ -0,0 +1,215 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * Copyright (C) 2018, Boundary Devices info@boundarydevices.com + */ + +#include <common.h> +#include <env.h> +#include <init.h> +#include <malloc.h> +#include <errno.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <miiphy.h> +#include <netdev.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm-generic/gpio.h> +#include <fsl_esdhc_imx.h> +#include <mmc.h> +#include <asm/arch/imx8mq_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/mach-imx/gpio.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <asm/arch/clock.h> +#include <spl.h> +#include <linux/bitops.h> +#include <linux/delay.h> +#include <power/pmic.h> + +DECLARE_GLOBAL_DATA_PTR; + +#define UART_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_FSEL1) + +#define WDOG_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) + +static iomux_v3_cfg_t const wdog_pads[] = { + IMX8MQ_PAD_GPIO1_IO02__WDOG1_WDOG_B | MUX_PAD_CTRL(WDOG_PAD_CTRL), +}; + +static iomux_v3_cfg_t const uart_pads[] = { + IMX8MQ_PAD_UART1_RXD__UART1_RX | MUX_PAD_CTRL(UART_PAD_CTRL), + IMX8MQ_PAD_UART1_TXD__UART1_TX | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +int board_early_init_f(void) +{ + struct wdog_regs *wdog = (struct wdog_regs *)WDOG1_BASE_ADDR; + + imx_iomux_v3_setup_multiple_pads(wdog_pads, ARRAY_SIZE(wdog_pads)); + set_wdog_reset(wdog); + + imx_iomux_v3_setup_multiple_pads(uart_pads, ARRAY_SIZE(uart_pads)); + + return 0; +} + +/* Make sure we're not using addresses >32-bit for I/O */ +ulong board_get_usable_ram_top(ulong total_size) +{ + return (1ULL << 32); +} + +#ifdef CONFIG_FEC_MXC + +#define PHY_RESET IMX_GPIO_NR(1, 9) +#define PHY_RX_CTL IMX_GPIO_NR(1, 24) +#define PHY_RXC IMX_GPIO_NR(1, 25) +#define PHY_RD0 IMX_GPIO_NR(1, 26) +#define PHY_RD1 IMX_GPIO_NR(1, 27) +#define PHY_RD2 IMX_GPIO_NR(1, 28) +#define PHY_RD3 IMX_GPIO_NR(1, 29) + +#define STRAP_AR8035 (0x28) // 0010 1000 + +static const iomux_v3_cfg_t enet_ar8035_gpio_pads[] = { + IMX8MQ_PAD_GPIO1_IO09__GPIO1_IO9 | MUX_PAD_CTRL(PAD_CTL_DSE6), + IMX8MQ_PAD_ENET_RD0__GPIO1_IO26 | MUX_PAD_CTRL(0x91), + IMX8MQ_PAD_ENET_RD1__GPIO1_IO27 | MUX_PAD_CTRL(0x91), + IMX8MQ_PAD_ENET_RD2__GPIO1_IO28 | MUX_PAD_CTRL(0x91), + IMX8MQ_PAD_ENET_RD3__GPIO1_IO29 | MUX_PAD_CTRL(0xd1), + IMX8MQ_PAD_ENET_RX_CTL__GPIO1_IO24 | MUX_PAD_CTRL(0x91), + /* 1.8V(1)/1.5V select(0) */ + IMX8MQ_PAD_ENET_RXC__GPIO1_IO25 | MUX_PAD_CTRL(0xd1), +}; + +static const iomux_v3_cfg_t enet_ar8035_pads[] = { + IMX8MQ_PAD_ENET_RD0__ENET_RGMII_RD0 | MUX_PAD_CTRL(0x91), + IMX8MQ_PAD_ENET_RD1__ENET_RGMII_RD1 | MUX_PAD_CTRL(0x91), + IMX8MQ_PAD_ENET_RD2__ENET_RGMII_RD2 | MUX_PAD_CTRL(0x91), + IMX8MQ_PAD_ENET_RD3__ENET_RGMII_RD3 | MUX_PAD_CTRL(0x91), + IMX8MQ_PAD_ENET_RX_CTL__ENET_RGMII_RX_CTL | MUX_PAD_CTRL(0x91), + IMX8MQ_PAD_ENET_RXC__ENET_RGMII_RXC | MUX_PAD_CTRL(0x91), +}; + +static void setup_fec(void) +{ + struct iomuxc_gpr_base_regs *gpr = + (struct iomuxc_gpr_base_regs *)IOMUXC_GPR_BASE_ADDR; + + /* Pull PHY into reset */ + gpio_request(PHY_RESET, "fec_rst"); + gpio_direction_output(PHY_RESET, 0); + + /* Configure ethernet pins value as GPIOs */ + gpio_request(PHY_RD0, "fec_rd0"); + gpio_direction_output(PHY_RD0, 0); + gpio_request(PHY_RD1, "fec_rd1"); + gpio_direction_output(PHY_RD1, 0); + gpio_request(PHY_RD2, "fec_rd2"); + gpio_direction_output(PHY_RD2, 0); + gpio_request(PHY_RD3, "fec_rd3"); + gpio_direction_output(PHY_RD3, 1); + gpio_request(PHY_RX_CTL, "fec_rx_ctl"); + gpio_direction_output(PHY_RX_CTL, 0); + gpio_request(PHY_RXC, "fec_rxc"); + gpio_direction_output(PHY_RXC, 1); + + /* Set ethernet pins to GPIO to bootstrap PHY */ + imx_iomux_v3_setup_multiple_pads(enet_ar8035_gpio_pads, + ARRAY_SIZE(enet_ar8035_gpio_pads)); + + /* Use 125M anatop REF_CLK1 for ENET1, not from external */ + clrsetbits_le32(&gpr->gpr[1], BIT(13) | BIT(17), 0); + /* Enable RGMII TX clk output */ + setbits_le32(&gpr->gpr[1], BIT(22)); + set_clk_enet(ENET_125MHZ); + + /* 1 ms minimum reset pulse for ar8035 */ + mdelay(1); + + /* Release PHY from reset */ + gpio_set_value(PHY_RESET, 1); + + /* strap hold time for AR8035, 5 fails, 6 works, so 12 should be safe */ + udelay(12); + + /* Change ethernet pins back to normal function */ + imx_iomux_v3_setup_multiple_pads(enet_ar8035_pads, + ARRAY_SIZE(enet_ar8035_pads)); +} + +int board_phy_config(struct phy_device *phydev) +{ + int val; + + /* + * Ar803x phy SmartEEE feature cause link status generates glitch, + * which cause ethernet link down/up issue, so disable SmartEEE + */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x3); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x805d); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4003); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val & ~(1 << 8)); + + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x0007); + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, 0x8016); + phy_write(phydev, MDIO_DEVAD_NONE, 0xd, 0x4007); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0xe); + val &= ~0x11c; + val |= 0x80; /* 1/2 drive strength */ + val |= 0x18; /* 125 MHz */ + phy_write(phydev, MDIO_DEVAD_NONE, 0xe, val); + + /* rgmii tx clock delay enable */ + phy_write(phydev, MDIO_DEVAD_NONE, 0x1d, 0x05); + val = phy_read(phydev, MDIO_DEVAD_NONE, 0x1e); + phy_write(phydev, MDIO_DEVAD_NONE, 0x1e, val | 0x0100); + + phydev->supported = phydev->drv->features; + + if (phydev->drv->config) + phydev->drv->config(phydev); + return 0; +} +#endif + +#define USB1_HUB_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) +#define USB1_HUB_RESET IMX_GPIO_NR(1, 14) + +static void setup_usb(void) +{ + imx_iomux_v3_setup_pad(IMX8MQ_PAD_GPIO1_IO14__GPIO1_IO14 | + MUX_PAD_CTRL(USB1_HUB_PAD_CTRL)); + gpio_request(USB1_HUB_RESET, "usb1_rst"); + gpio_direction_output(USB1_HUB_RESET, 0); + mdelay(10); + gpio_set_value(USB1_HUB_RESET, 1); +} + +int board_init(void) +{ +#ifdef CONFIG_FEC_MXC + setup_fec(); +#endif + + setup_usb(); + + return 0; +} + +int board_mmc_get_env_dev(int devno) +{ + return devno; +} + +int board_late_init(void) +{ +#ifdef CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + env_set("board_name", "Reform2"); + env_set("board_rev", "iMX8MQ"); +#endif + + return 0; +} diff --git a/board/mntre/imx8mq_reform2/lpddr4_timing.c b/board/mntre/imx8mq_reform2/lpddr4_timing.c new file mode 100644 index 0000000000..e5303db0f8 --- /dev/null +++ b/board/mntre/imx8mq_reform2/lpddr4_timing.c @@ -0,0 +1,1014 @@ +/* + * Copyright 2019 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + * + * Generated code from MX8M_DDR_tool + * Align with uboot version: + * imx_v2018.03_4.14.78_1.0.0_ga ~ imx_v2018.04_4.19.35_1.0.0_ga + */ +#include "lpddr4_timing_ch2.h" + +static struct dram_cfg_param lpddr4_ddrc_cfg[] = { + /** Initialize DDRC registers **/ + { DDRC_DBG1(0), 1 }, + /* selfref_en=1, SDRAM enter self-refresh state */ + { DDRC_PWRCTL(0), 1 }, + { DDRC_MSTR(0), 0xa0080020 | (CH2_LPDDR4_CS << 24) }, + { DDRC_MSTR2(0), 0 }, + { DDRC_DERATEEN(0), 0x0203 }, + { DDRC_DERATEINT(0), 0x0003e800 }, + { DDRC_RFSHTMG(0), 0x006100e0 }, + { DDRC_INIT0(0), 0xc003061c }, + { DDRC_INIT1(0), 0x009e0000 }, + { DDRC_INIT3(0), 0x00d4002d }, + { DDRC_INIT4(0), CH2_VAL_INIT4 }, + { DDRC_INIT6(0), 0x0066004a }, + { DDRC_INIT7(0), 0x0016004a }, + { DDRC_DRAMTMG0(0), 0x1a201b22 }, + { DDRC_DRAMTMG1(0), 0x00060633 }, + { DDRC_DRAMTMG3(0), 0x00c0c000 }, + { DDRC_DRAMTMG4(0), 0x0f04080f }, + { DDRC_DRAMTMG5(0), 0x02040c0c }, + { DDRC_DRAMTMG6(0), 0x01010007 }, + { DDRC_DRAMTMG7(0), 0x0401 }, + { DDRC_DRAMTMG12(0), 0x00020600 }, + { DDRC_DRAMTMG13(0), 0x0c100002 }, + { DDRC_DRAMTMG14(0), 0xe6 }, + { DDRC_DRAMTMG17(0), 0x00a00050 }, + { DDRC_ZQCTL0(0), 0xc3200018 }, + { DDRC_ZQCTL1(0), 0x028061a8 }, + { DDRC_ZQCTL2(0), 0 }, + { DDRC_DFITMG0(0), 0x0497820a }, + { DDRC_DFITMG1(0), 0x00080303 }, + { DDRC_DFIUPD0(0), 0xe0400018 }, + { DDRC_DFIUPD1(0), 0x00df00e4 }, + { DDRC_DFIUPD2(0), 0x80000000 }, + { DDRC_DFIMISC(0), 0x11 }, + { DDRC_DFITMG2(0), 0x170a }, + { DDRC_DBICTL(0), 1 }, + { DDRC_DFIPHYMSTR(0), 1 }, + { DDRC_RANKCTL(0), 0x0639 }, + { DDRC_DRAMTMG2(0), 0x070e1617 }, + + /* address mapping */ + { DDRC_ADDRMAP0(0), CH2_VAL_DDRC_ADDRMAP0 }, + { DDRC_ADDRMAP3(0), 0 }, + /* addrmap_col_b10 and addrmap_col_b11 set to de-activated (5-bit width) */ + { DDRC_ADDRMAP4(0), 0x1f1f }, + /* bank interleave */ + /* addrmap_bank_b2, addrmap_bank_b1, addrmap_bank_b0 */ + { DDRC_ADDRMAP1(0), 0x00080808 }, + /* addrmap_row_b11, addrmap_row_b10_b2, addrmap_row_b1, addrmap_row_b0 */ + { DDRC_ADDRMAP5(0), 0x07070707 }, + /* addrmap_row_b15, addrmap_row_b14, addrmap_row_b13, addrmap_row_b12 */ + { DDRC_ADDRMAP6(0), CH2_VAL_DDRC_ADDRMAP6 }, + { DDRC_ADDRMAP7(0), 0x0f0f }, + { DDRC_FREQ1_DERATEEN(0), 1 }, + { DDRC_FREQ1_DERATEINT(0), 0xd0c0 }, + { DDRC_FREQ1_RFSHCTL0(0), 0x0020d040 }, + { DDRC_FREQ1_RFSHTMG(0), 0x0014002f }, + { DDRC_FREQ1_INIT3(0), 0x00940009 }, + { DDRC_FREQ1_INIT4(0), CH2_VAL_INIT4 }, + { DDRC_FREQ1_INIT6(0), 0x0066004a }, + { DDRC_FREQ1_INIT7(0), 0x0016004a }, + { DDRC_FREQ1_DRAMTMG0(0), 0x0b070508 }, + { DDRC_FREQ1_DRAMTMG1(0), 0x0003040b }, + { DDRC_FREQ1_DRAMTMG2(0), 0x0305090c }, + { DDRC_FREQ1_DRAMTMG3(0), 0x00505000 }, + { DDRC_FREQ1_DRAMTMG4(0), 0x04040204 }, + { DDRC_FREQ1_DRAMTMG5(0), 0x02030303 }, + { DDRC_FREQ1_DRAMTMG6(0), 0x01010004 }, + { DDRC_FREQ1_DRAMTMG7(0), 0x0301 }, + { DDRC_FREQ1_DRAMTMG12(0), 0x00020300 }, + { DDRC_FREQ1_DRAMTMG13(0), 0x0a100002 }, + { DDRC_FREQ1_DRAMTMG14(0), 0x31 }, + { DDRC_FREQ1_DRAMTMG17(0), 0x00220011 }, + { DDRC_FREQ1_ZQCTL0(0), 0xc0a70006 }, + { DDRC_FREQ1_DFITMG0(0), 0x03858202 }, + { DDRC_FREQ1_DFITMG1(0), 0x00080303 }, + { DDRC_FREQ1_DFITMG2(0), 0x0502 }, + { DDRC_ODTMAP(0), 0 }, + { DDRC_SCHED(0), 0x29001505 }, + { DDRC_SCHED1(0), 0x2c }, + { DDRC_PERFHPR1(0), 0x5900575b }, + { DDRC_PERFLPR1(0), 0x90000096 }, + { DDRC_PERFWR1(0), 0x1000012c }, + { DDRC_DBG0(0), 0x16 }, + { DDRC_DBG1(0), 0 }, + { DDRC_DBGCMD(0), 0 }, + { DDRC_SWCTL(0), 1 }, + { DDRC_POISONCFG(0), 0x11 }, + { DDRC_PCCFG(0), 0x0111 }, + { DDRC_PCFGR_0(0), 0x10f3 }, + { DDRC_PCFGW_0(0), 0x72ff }, + { DDRC_PCTRL_0(0), 1 }, + { DDRC_PCFGQOS0_0(0), 0x0e00 }, + { DDRC_PCFGQOS1_0(0), 0x0062ffff }, + { DDRC_PCFGWQOS0_0(0), 0x0e00 }, + { DDRC_PCFGWQOS1_0(0), 0xffff }, +}; + +/* PHY Initialize Configuration */ +static struct dram_cfg_param lpddr4_ddrphy_cfg[] = { + { 0x100a0, 0 }, + { 0x100a1, 1 }, + { 0x100a2, 2 }, + { 0x100a3, 3 }, + { 0x100a4, 4 }, + { 0x100a5, 5 }, + { 0x100a6, 6 }, + { 0x100a7, 7 }, + { 0x110a0, 0 }, + { 0x110a1, 1 }, + { 0x110a2, 2 }, + { 0x110a3, 3 }, + { 0x110a4, 4 }, + { 0x110a5, 5 }, + { 0x110a6, 6 }, + { 0x110a7, 7 }, + { 0x120a0, 0 }, + { 0x120a1, 1 }, + { 0x120a2, 2 }, + { 0x120a3, 3 }, + { 0x120a4, 4 }, + { 0x120a5, 5 }, + { 0x120a6, 6 }, + { 0x120a7, 7 }, + { 0x130a0, 0 }, + { 0x130a1, 1 }, + { 0x130a2, 2 }, + { 0x130a3, 3 }, + { 0x130a4, 4 }, + { 0x130a5, 5 }, + { 0x130a6, 6 }, + { 0x130a7, 7 }, + { 0x1005f, 0x01ff }, + { 0x1015f, 0x01ff }, + { 0x1105f, 0x01ff }, + { 0x1115f, 0x01ff }, + { 0x1205f, 0x01ff }, + { 0x1215f, 0x01ff }, + { 0x1305f, 0x01ff }, + { 0x1315f, 0x01ff }, + { 0x11005f, 0x01ff }, + { 0x11015f, 0x01ff }, + { 0x11105f, 0x01ff }, + { 0x11115f, 0x01ff }, + { 0x11205f, 0x01ff }, + { 0x11215f, 0x01ff }, + { 0x11305f, 0x01ff }, + { 0x11315f, 0x01ff }, + { 0x0055, 0x01ff }, + { 0x1055, 0x01ff }, + { 0x2055, 0x01ff }, + { 0x3055, 0x01ff }, + { 0x4055, 0x01ff }, + { 0x5055, 0x01ff }, + { 0x6055, 0x01ff }, + { 0x7055, 0x01ff }, + { 0x8055, 0x01ff }, + { 0x9055, 0x01ff }, + { 0x200c5, 0x19 }, + { 0x1200c5, 7 }, + { 0x2002e, 2 }, + { 0x12002e, 1 }, + { 0x90204, 0 }, + { 0x190204, 0 }, + { 0x20024, 0x01ab }, + { 0x2003a, 0 }, + { 0x120024, 0x01ab }, + { 0x2003a, 0 }, + { 0x20056, 3 }, + { 0x120056, 3 }, + { 0x1004d, 0x0e00 }, + { 0x1014d, 0x0e00 }, + { 0x1104d, 0x0e00 }, + { 0x1114d, 0x0e00 }, + { 0x1204d, 0x0e00 }, + { 0x1214d, 0x0e00 }, + { 0x1304d, 0x0e00 }, + { 0x1314d, 0x0e00 }, + { 0x11004d, 0x0e00 }, + { 0x11014d, 0x0e00 }, + { 0x11104d, 0x0e00 }, + { 0x11114d, 0x0e00 }, + { 0x11204d, 0x0e00 }, + { 0x11214d, 0x0e00 }, + { 0x11304d, 0x0e00 }, + { 0x11314d, 0x0e00 }, + { 0x10049, 0x0eba }, + { 0x10149, 0x0eba }, + { 0x11049, 0x0eba }, + { 0x11149, 0x0eba }, + { 0x12049, 0x0eba }, + { 0x12149, 0x0eba }, + { 0x13049, 0x0eba }, + { 0x13149, 0x0eba }, + { 0x110049, 0x0eba }, + { 0x110149, 0x0eba }, + { 0x111049, 0x0eba }, + { 0x111149, 0x0eba }, + { 0x112049, 0x0eba }, + { 0x112149, 0x0eba }, + { 0x113049, 0x0eba }, + { 0x113149, 0x0eba }, + { 0x0043, 0x63 }, + { 0x1043, 0x63 }, + { 0x2043, 0x63 }, + { 0x3043, 0x63 }, + { 0x4043, 0x63 }, + { 0x5043, 0x63 }, + { 0x6043, 0x63 }, + { 0x7043, 0x63 }, + { 0x8043, 0x63 }, + { 0x9043, 0x63 }, + { 0x20018, 3 }, + { 0x20075, 4 }, + { 0x20050, 0 }, + { 0x20008, 0x0320 }, + { 0x120008, 0xa7 }, + { 0x20088, 9 }, + { 0x200b2, 0xdc }, + { 0x10043, 0x05a1 }, + { 0x10143, 0x05a1 }, + { 0x11043, 0x05a1 }, + { 0x11143, 0x05a1 }, + { 0x12043, 0x05a1 }, + { 0x12143, 0x05a1 }, + { 0x13043, 0x05a1 }, + { 0x13143, 0x05a1 }, + { 0x1200b2, 0xdc }, + { 0x110043, 0x05a1 }, + { 0x110143, 0x05a1 }, + { 0x111043, 0x05a1 }, + { 0x111143, 0x05a1 }, + { 0x112043, 0x05a1 }, + { 0x112143, 0x05a1 }, + { 0x113043, 0x05a1 }, + { 0x113143, 0x05a1 }, + { 0x200fa, 1 }, + { 0x1200fa, 1 }, + { 0x20019, 1 }, + { 0x120019, 1 }, + { 0x200f0, 0 }, + { 0x200f1, 0 }, + { 0x200f2, 0x4444 }, + { 0x200f3, 0x8888 }, + { 0x200f4, 0x5555 }, + { 0x200f5, 0 }, + { 0x200f6, 0 }, + { 0x200f7, 0xf000 }, + { 0x20025, 0 }, + { 0x2002d, 0 }, + { 0x12002d, 0 }, + { 0x200c7, 0x80 }, + { 0x1200c7, 0x80 }, + { 0x200ca, 0x0106 }, + { 0x1200ca, 0x0106 }, + { 0x20110, 2 }, + { 0x20111, 3 }, + { 0x20112, 4 }, + { 0x20113, 5 }, + { 0x20114, 0 }, + { 0x20115, 1 }, +}; + +/* P0 message block parameter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_cfg[] = { + { 0xd0000, 0 }, + { 0x54003, 0x0c80 }, + { 0x54004, 2 }, + { 0x54005, 0x2228 }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54008, 0x131f }, + { 0x54009, LPDDR4_HDT_CTL_3200_1D }, + { 0x5400b, 2 }, + { 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4a66 }, + { 0x5401c, 0x4a08 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4a66 }, + { 0x54022, 0x4a08 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, CH2_LPDDR4_CS }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x084a }, + { 0x54036, 0x4a }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x084a }, + { 0x5403c, 0x4a }, + { 0x5403d, 0x1600 }, + { 0xd0000, 1 }, +}; + + +/* P1 message block parameter for training firmware */ +static struct dram_cfg_param lpddr4_fsp1_cfg[] = { + { 0xd0000, 0 }, + { 0x54002, 1 }, + { 0x54003, 0x029c }, + { 0x54004, 2 }, + { 0x54005, 0x2228 }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54008, 0x121f }, + { 0x54009, LPDDR4_HDT_CTL_3200_1D }, + { 0x5400b, 2 }, + { 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) }, + { 0x54019, 0x0994 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4a66 }, + { 0x5401c, 0x4a08 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x0994 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4a66 }, + { 0x54022, 0x4a08 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, CH2_LPDDR4_CS }, + { 0x54032, 0x9400 }, + { 0x54033, 0x3109 }, + { 0x54034, 0x6600 }, + { 0x54035, 0x084a }, + { 0x54036, 0x4a }, + { 0x54037, 0x1600 }, + { 0x54038, 0x9400 }, + { 0x54039, 0x3109 }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x084a }, + { 0x5403c, 0x4a }, + { 0x5403d, 0x1600 }, + { 0xd0000, 1 }, +}; + + +/* P0 2D message block parameter for training firmware */ +static struct dram_cfg_param lpddr4_fsp0_2d_cfg[] = { + { 0xd0000, 0 }, + { 0x54003, 0x0c80 }, + { 0x54004, 2 }, + { 0x54005, 0x2228 }, + { 0x54006, LPDDR4_PHY_VREF_VALUE }, + { 0x54008, 0x61 }, + { 0x54009, LPDDR4_HDT_CTL_3200_1D }, + { 0x5400b, 2 }, + { 0x5400d, 0x0100 }, + { 0x5400f, 0x0100 }, + { 0x54010, 0x1f7f }, + { 0x54012, 0x10 | (CH2_LPDDR4_CS << 8) }, + { 0x54019, 0x2dd4 }, + { 0x5401a, 0x31 }, + { 0x5401b, 0x4a66 }, + { 0x5401c, 0x4a08 }, + { 0x5401e, 0x16 }, + { 0x5401f, 0x2dd4 }, + { 0x54020, 0x31 }, + { 0x54021, 0x4a66 }, + { 0x54022, 0x4a08 }, + { 0x54024, 0x16 }, + { 0x5402b, 0x1000 }, + { 0x5402c, CH2_LPDDR4_CS }, + { 0x54032, 0xd400 }, + { 0x54033, 0x312d }, + { 0x54034, 0x6600 }, + { 0x54035, 0x084a }, + { 0x54036, 0x4a }, + { 0x54037, 0x1600 }, + { 0x54038, 0xd400 }, + { 0x54039, 0x312d }, + { 0x5403a, 0x6600 }, + { 0x5403b, 0x084a }, + { 0x5403c, 0x4a }, + { 0x5403d, 0x1600 }, + { 0xd0000, 1 }, +}; + +/* DRAM PHY init engine image */ +static struct dram_cfg_param lpddr4_phy_pie[] = { + { 0xd0000, 0 }, + { 0x90000, 0x10 }, + { 0x90001, 0x0400 }, + { 0x90002, 0x010e }, + { 0x90003, 0 }, + { 0x90004, 0 }, + { 0x90005, 8 }, + { 0x90029, 0x0b }, + { 0x9002a, 0x0480 }, + { 0x9002b, 0x0109 }, + { 0x9002c, 8 }, + { 0x9002d, 0x0448 }, + { 0x9002e, 0x0139 }, + { 0x9002f, 8 }, + { 0x90030, 0x0478 }, + { 0x90031, 0x0109 }, + { 0x90032, 0 }, + { 0x90033, 0xe8 }, + { 0x90034, 0x0109 }, + { 0x90035, 2 }, + { 0x90036, 0x10 }, + { 0x90037, 0x0139 }, + { 0x90038, 0x0f }, + { 0x90039, 0x07c0 }, + { 0x9003a, 0x0139 }, + { 0x9003b, 0x44 }, + { 0x9003c, 0x0630 }, + { 0x9003d, 0x0159 }, + { 0x9003e, 0x014f }, + { 0x9003f, 0x0630 }, + { 0x90040, 0x0159 }, + { 0x90041, 0x47 }, + { 0x90042, 0x0630 }, + { 0x90043, 0x0149 }, + { 0x90044, 0x4f }, + { 0x90045, 0x0630 }, + { 0x90046, 0x0179 }, + { 0x90047, 8 }, + { 0x90048, 0xe0 }, + { 0x90049, 0x0109 }, + { 0x9004a, 0 }, + { 0x9004b, 0x07c8 }, + { 0x9004c, 0x0109 }, + { 0x9004d, 0 }, + { 0x9004e, 1 }, + { 0x9004f, 8 }, + { 0x90050, 0 }, + { 0x90051, 0x045a }, + { 0x90052, 9 }, + { 0x90053, 0 }, + { 0x90054, 0x0448 }, + { 0x90055, 0x0109 }, + { 0x90056, 0x40 }, + { 0x90057, 0x0630 }, + { 0x90058, 0x0179 }, + { 0x90059, 1 }, + { 0x9005a, 0x0618 }, + { 0x9005b, 0x0109 }, + { 0x9005c, 0x40c0 }, + { 0x9005d, 0x0630 }, + { 0x9005e, 0x0149 }, + { 0x9005f, 8 }, + { 0x90060, 4 }, + { 0x90061, 0x48 }, + { 0x90062, 0x4040 }, + { 0x90063, 0x0630 }, + { 0x90064, 0x0149 }, + { 0x90065, 0 }, + { 0x90066, 4 }, + { 0x90067, 0x48 }, + { 0x90068, 0x40 }, + { 0x90069, 0x0630 }, + { 0x9006a, 0x0149 }, + { 0x9006b, 0x10 }, + { 0x9006c, 4 }, + { 0x9006d, 0x18 }, + { 0x9006e, 0 }, + { 0x9006f, 4 }, + { 0x90070, 0x78 }, + { 0x90071, 0x0549 }, + { 0x90072, 0x0630 }, + { 0x90073, 0x0159 }, + { 0x90074, 0x0d49 }, + { 0x90075, 0x0630 }, + { 0x90076, 0x0159 }, + { 0x90077, 0x094a }, + { 0x90078, 0x0630 }, + { 0x90079, 0x0159 }, + { 0x9007a, 0x0441 }, + { 0x9007b, 0x0630 }, + { 0x9007c, 0x0149 }, + { 0x9007d, 0x42 }, + { 0x9007e, 0x0630 }, + { 0x9007f, 0x0149 }, + { 0x90080, 1 }, + { 0x90081, 0x0630 }, + { 0x90082, 0x0149 }, + { 0x90083, 0 }, + { 0x90084, 0xe0 }, + { 0x90085, 0x0109 }, + { 0x90086, 0x0a }, + { 0x90087, 0x10 }, + { 0x90088, 0x0109 }, + { 0x90089, 9 }, + { 0x9008a, 0x03c0 }, + { 0x9008b, 0x0149 }, + { 0x9008c, 9 }, + { 0x9008d, 0x03c0 }, + { 0x9008e, 0x0159 }, + { 0x9008f, 0x18 }, + { 0x90090, 0x10 }, + { 0x90091, 0x0109 }, + { 0x90092, 0 }, + { 0x90093, 0x03c0 }, + { 0x90094, 0x0109 }, + { 0x90095, 0x18 }, + { 0x90096, 4 }, + { 0x90097, 0x48 }, + { 0x90098, 0x18 }, + { 0x90099, 4 }, + { 0x9009a, 0x58 }, + { 0x9009b, 0x0a }, + { 0x9009c, 0x10 }, + { 0x9009d, 0x0109 }, + { 0x9009e, 2 }, + { 0x9009f, 0x10 }, + { 0x900a0, 0x0109 }, + { 0x900a1, 5 }, + { 0x900a2, 0x07c0 }, + { 0x900a3, 0x0109 }, + { 0x900a4, 0x10 }, + { 0x900a5, 0x10 }, + { 0x900a6, 0x0109 }, + { 0x40000, 0x0811 }, + { 0x40020, 0x0880 }, + { 0x40040, 0 }, + { 0x40060, 0 }, + { 0x40001, 0x4008 }, + { 0x40021, 0x83 }, + { 0x40041, 0x4f }, + { 0x40061, 0 }, + { 0x40002, 0x4040 }, + { 0x40022, 0x83 }, + { 0x40042, 0x51 }, + { 0x40062, 0 }, + { 0x40003, 0x0811 }, + { 0x40023, 0x0880 }, + { 0x40043, 0 }, + { 0x40063, 0 }, + { 0x40004, 0x0720 }, + { 0x40024, 0x0f }, + { 0x40044, 0x1740 }, + { 0x40064, 0 }, + { 0x40005, 0x16 }, + { 0x40025, 0x83 }, + { 0x40045, 0x4b }, + { 0x40065, 0 }, + { 0x40006, 0x0716 }, + { 0x40026, 0x0f }, + { 0x40046, 0x2001 }, + { 0x40066, 0 }, + { 0x40007, 0x0716 }, + { 0x40027, 0x0f }, + { 0x40047, 0x2800 }, + { 0x40067, 0 }, + { 0x40008, 0x0716 }, + { 0x40028, 0x0f }, + { 0x40048, 0x0f00 }, + { 0x40068, 0 }, + { 0x40009, 0x0720 }, + { 0x40029, 0x0f }, + { 0x40049, 0x1400 }, + { 0x40069, 0 }, + { 0x4000a, 0x0e08 }, + { 0x4002a, 0x0c15 }, + { 0x4004a, 0 }, + { 0x4006a, 0 }, + { 0x4000b, 0x0623 }, + { 0x4002b, 0x15 }, + { 0x4004b, 0 }, + { 0x4006b, 0 }, + { 0x4000c, 0x4028 }, + { 0x4002c, 0x80 }, + { 0x4004c, 0 }, + { 0x4006c, 0 }, + { 0x4000d, 0x0e08 }, + { 0x4002d, 0x0c1a }, + { 0x4004d, 0 }, + { 0x4006d, 0 }, + { 0x4000e, 0x0623 }, + { 0x4002e, 0x1a }, + { 0x4004e, 0 }, + { 0x4006e, 0 }, + { 0x4000f, 0x4040 }, + { 0x4002f, 0x80 }, + { 0x4004f, 0 }, + { 0x4006f, 0 }, + { 0x40010, 0x2604 }, + { 0x40030, 0x15 }, + { 0x40050, 0 }, + { 0x40070, 0 }, + { 0x40011, 0x0708 }, + { 0x40031, 5 }, + { 0x40051, 0 }, + { 0x40071, 0x2002 }, + { 0x40012, 8 }, + { 0x40032, 0x80 }, + { 0x40052, 0 }, + { 0x40072, 0 }, + { 0x40013, 0x2604 }, + { 0x40033, 0x1a }, + { 0x40053, 0 }, + { 0x40073, 0 }, + { 0x40014, 0x0708 }, + { 0x40034, 0x0a }, + { 0x40054, 0 }, + { 0x40074, 0x2002 }, + { 0x40015, 0x4040 }, + { 0x40035, 0x80 }, + { 0x40055, 0 }, + { 0x40075, 0 }, + { 0x40016, 0x060a }, + { 0x40036, 0x15 }, + { 0x40056, 0x1200 }, + { 0x40076, 0 }, + { 0x40017, 0x061a }, + { 0x40037, 0x15 }, + { 0x40057, 0x1300 }, + { 0x40077, 0 }, + { 0x40018, 0x060a }, + { 0x40038, 0x1a }, + { 0x40058, 0x1200 }, + { 0x40078, 0 }, + { 0x40019, 0x0642 }, + { 0x40039, 0x1a }, + { 0x40059, 0x1300 }, + { 0x40079, 0 }, + { 0x4001a, 0x4808 }, + { 0x4003a, 0x0880 }, + { 0x4005a, 0 }, + { 0x4007a, 0 }, + { 0x900a7, 0 }, + { 0x900a8, 0x0790 }, + { 0x900a9, 0x011a }, + { 0x900aa, 8 }, + { 0x900ab, 0x07aa }, + { 0x900ac, 0x2a }, + { 0x900ad, 0x10 }, + { 0x900ae, 0x07b2 }, + { 0x900af, 0x2a }, + { 0x900b0, 0 }, + { 0x900b1, 0x07c8 }, + { 0x900b2, 0x0109 }, + { 0x900b3, 0x10 }, + { 0x900b4, 0x02a8 }, + { 0x900b5, 0x0129 }, + { 0x900b6, 8 }, + { 0x900b7, 0x0370 }, + { 0x900b8, 0x0129 }, + { 0x900b9, 0x0a }, + { 0x900ba, 0x03c8 }, + { 0x900bb, 0x01a9 }, + { 0x900bc, 0x0c }, + { 0x900bd, 0x0408 }, + { 0x900be, 0x0199 }, + { 0x900bf, 0x14 }, + { 0x900c0, 0x0790 }, + { 0x900c1, 0x011a }, + { 0x900c2, 8 }, + { 0x900c3, 4 }, + { 0x900c4, 0x18 }, + { 0x900c5, 0x0e }, + { 0x900c6, 0x0408 }, + { 0x900c7, 0x0199 }, + { 0x900c8, 8 }, + { 0x900c9, 0x8568 }, + { 0x900ca, 0x0108 }, + { 0x900cb, 0x18 }, + { 0x900cc, 0x0790 }, + { 0x900cd, 0x016a }, + { 0x900ce, 8 }, + { 0x900cf, 0x01d8 }, + { 0x900d0, 0x0169 }, + { 0x900d1, 0x10 }, + { 0x900d2, 0x8558 }, + { 0x900d3, 0x0168 }, + { 0x900d4, 0x70 }, + { 0x900d5, 0x0788 }, + { 0x900d6, 0x016a }, + { 0x900d7, 0x1ff8 }, + { 0x900d8, 0x85a8 }, + { 0x900d9, 0x01e8 }, + { 0x900da, 0x50 }, + { 0x900db, 0x0798 }, + { 0x900dc, 0x016a }, + { 0x900dd, 0x60 }, + { 0x900de, 0x07a0 }, + { 0x900df, 0x016a }, + { 0x900e0, 8 }, + { 0x900e1, 0x8310 }, + { 0x900e2, 0x0168 }, + { 0x900e3, 8 }, + { 0x900e4, 0xa310 }, + { 0x900e5, 0x0168 }, + { 0x900e6, 0x0a }, + { 0x900e7, 0x0408 }, + { 0x900e8, 0x0169 }, + { 0x900e9, 0x6e }, + { 0x900ea, 0 }, + { 0x900eb, 0x68 }, + { 0x900ec, 0 }, + { 0x900ed, 0x0408 }, + { 0x900ee, 0x0169 }, + { 0x900ef, 0 }, + { 0x900f0, 0x8310 }, + { 0x900f1, 0x0168 }, + { 0x900f2, 0 }, + { 0x900f3, 0xa310 }, + { 0x900f4, 0x0168 }, + { 0x900f5, 0x1ff8 }, + { 0x900f6, 0x85a8 }, + { 0x900f7, 0x01e8 }, + { 0x900f8, 0x68 }, + { 0x900f9, 0x0798 }, + { 0x900fa, 0x016a }, + { 0x900fb, 0x78 }, + { 0x900fc, 0x07a0 }, + { 0x900fd, 0x016a }, + { 0x900fe, 0x68 }, + { 0x900ff, 0x0790 }, + { 0x90100, 0x016a }, + { 0x90101, 8 }, + { 0x90102, 0x8b10 }, + { 0x90103, 0x0168 }, + { 0x90104, 8 }, + { 0x90105, 0xab10 }, + { 0x90106, 0x0168 }, + { 0x90107, 0x0a }, + { 0x90108, 0x0408 }, + { 0x90109, 0x0169 }, + { 0x9010a, 0x58 }, + { 0x9010b, 0 }, + { 0x9010c, 0x68 }, + { 0x9010d, 0 }, + { 0x9010e, 0x0408 }, + { 0x9010f, 0x0169 }, + { 0x90110, 0 }, + { 0x90111, 0x8b10 }, + { 0x90112, 0x0168 }, + { 0x90113, 0 }, + { 0x90114, 0xab10 }, + { 0x90115, 0x0168 }, + { 0x90116, 0 }, + { 0x90117, 0x01d8 }, + { 0x90118, 0x0169 }, + { 0x90119, 0x80 }, + { 0x9011a, 0x0790 }, + { 0x9011b, 0x016a }, + { 0x9011c, 0x18 }, + { 0x9011d, 0x07aa }, + { 0x9011e, 0x6a }, + { 0x9011f, 0x0a }, + { 0x90120, 0 }, + { 0x90121, 0x01e9 }, + { 0x90122, 8 }, + { 0x90123, 0x8080 }, + { 0x90124, 0x0108 }, + { 0x90125, 0x0f }, + { 0x90126, 0x0408 }, + { 0x90127, 0x0169 }, + { 0x90128, 0x0c }, + { 0x90129, 0 }, + { 0x9012a, 0x68 }, + { 0x9012b, 9 }, + { 0x9012c, 0 }, + { 0x9012d, 0x01a9 }, + { 0x9012e, 0 }, + { 0x9012f, 0x0408 }, + { 0x90130, 0x0169 }, + { 0x90131, 0 }, + { 0x90132, 0x8080 }, + { 0x90133, 0x0108 }, + { 0x90134, 8 }, + { 0x90135, 0x07aa }, + { 0x90136, 0x6a }, + { 0x90137, 0 }, + { 0x90138, 0x8568 }, + { 0x90139, 0x0108 }, + { 0x9013a, 0xb7 }, + { 0x9013b, 0x0790 }, + { 0x9013c, 0x016a }, + { 0x9013d, 0x1f }, + { 0x9013e, 0 }, + { 0x9013f, 0x68 }, + { 0x90140, 8 }, + { 0x90141, 0x8558 }, + { 0x90142, 0x0168 }, + { 0x90143, 0x0f }, + { 0x90144, 0x0408 }, + { 0x90145, 0x0169 }, + { 0x90146, 0x0c }, + { 0x90147, 0 }, + { 0x90148, 0x68 }, + { 0x90149, 0 }, + { 0x9014a, 0x0408 }, + { 0x9014b, 0x0169 }, + { 0x9014c, 0 }, + { 0x9014d, 0x8558 }, + { 0x9014e, 0x0168 }, + { 0x9014f, 8 }, + { 0x90150, 0x03c8 }, + { 0x90151, 0x01a9 }, + { 0x90152, 3 }, + { 0x90153, 0x0370 }, + { 0x90154, 0x0129 }, + { 0x90155, 0x20 }, + { 0x90156, 0x02aa }, + { 0x90157, 9 }, + { 0x90158, 0 }, + { 0x90159, 0x0400 }, + { 0x9015a, 0x010e }, + { 0x9015b, 8 }, + { 0x9015c, 0xe8 }, + { 0x9015d, 0x0109 }, + { 0x9015e, 0 }, + { 0x9015f, 0x8140 }, + { 0x90160, 0x010c }, + { 0x90161, 0x10 }, + { 0x90162, 0x8138 }, + { 0x90163, 0x010c }, + { 0x90164, 8 }, + { 0x90165, 0x07c8 }, + { 0x90166, 0x0101 }, + { 0x90167, 8 }, + { 0x90168, 0 }, + { 0x90169, 8 }, + { 0x9016a, 8 }, + { 0x9016b, 0x0448 }, + { 0x9016c, 0x0109 }, + { 0x9016d, 0x0f }, + { 0x9016e, 0x07c0 }, + { 0x9016f, 0x0109 }, + { 0x90170, 0 }, + { 0x90171, 0xe8 }, + { 0x90172, 0x0109 }, + { 0x90173, 0x47 }, + { 0x90174, 0x0630 }, + { 0x90175, 0x0109 }, + { 0x90176, 8 }, + { 0x90177, 0x0618 }, + { 0x90178, 0x0109 }, + { 0x90179, 8 }, + { 0x9017a, 0xe0 }, + { 0x9017b, 0x0109 }, + { 0x9017c, 0 }, + { 0x9017d, 0x07c8 }, + { 0x9017e, 0x0109 }, + { 0x9017f, 8 }, + { 0x90180, 0x8140 }, + { 0x90181, 0x010c }, + { 0x90182, 0 }, + { 0x90183, 1 }, + { 0x90184, 8 }, + { 0x90185, 8 }, + { 0x90186, 4 }, + { 0x90187, 8 }, + { 0x90188, 8 }, + { 0x90189, 0x07c8 }, + { 0x9018a, 0x0101 }, + { 0x90006, 0 }, + { 0x90007, 0 }, + { 0x90008, 8 }, + { 0x90009, 0 }, + { 0x9000a, 0 }, + { 0x9000b, 0 }, + { 0xd00e7, 0x0400 }, + { 0x90017, 0 }, + { 0x9001f, 0x2a }, + { 0x90026, 0x6a }, + { 0x400d0, 0 }, + { 0x400d1, 0x0101 }, + { 0x400d2, 0x0105 }, + { 0x400d3, 0x0107 }, + { 0x400d4, 0x010f }, + { 0x400d5, 0x0202 }, + { 0x400d6, 0x020a }, + { 0x400d7, 0x020b }, + { 0x2003a, 2 }, + { 0x2000b, 0x64 }, + { 0x2000c, 0xc8 }, + { 0x2000d, 0x07d0 }, + { 0x2000e, 0x2c }, + { 0x12000b, 0x14 }, + { 0x12000c, 0x29 }, + { 0x12000d, 0x01a1 }, + { 0x12000e, 0x10 }, + { 0x9000c, 0 }, + { 0x9000d, 0x0173 }, + { 0x9000e, 0x60 }, + { 0x9000f, 0x6110 }, + { 0x90010, 0x2152 }, + { 0x90011, 0xdfbd }, + { 0x90012, 0x60 }, + { 0x90013, 0x6152 }, + { 0x20010, 0x5a }, + { 0x20011, 3 }, + { 0x40080, 0xe0 }, + { 0x40081, 0x12 }, + { 0x40082, 0xe0 }, + { 0x40083, 0x12 }, + { 0x40084, 0xe0 }, + { 0x40085, 0x12 }, + { 0x140080, 0xe0 }, + { 0x140081, 0x12 }, + { 0x140082, 0xe0 }, + { 0x140083, 0x12 }, + { 0x140084, 0xe0 }, + { 0x140085, 0x12 }, + { 0x400fd, 0x0f }, + { 0x10011, 1 }, + { 0x10012, 1 }, + { 0x10013, 0x0180 }, + { 0x10018, 1 }, + { 0x10002, 0x6209 }, + { 0x100b2, 1 }, + { 0x101b4, 1 }, + { 0x102b4, 1 }, + { 0x103b4, 1 }, + { 0x104b4, 1 }, + { 0x105b4, 1 }, + { 0x106b4, 1 }, + { 0x107b4, 1 }, + { 0x108b4, 1 }, + { 0x11011, 1 }, + { 0x11012, 1 }, + { 0x11013, 0x0180 }, + { 0x11018, 1 }, + { 0x11002, 0x6209 }, + { 0x110b2, 1 }, + { 0x111b4, 1 }, + { 0x112b4, 1 }, + { 0x113b4, 1 }, + { 0x114b4, 1 }, + { 0x115b4, 1 }, + { 0x116b4, 1 }, + { 0x117b4, 1 }, + { 0x118b4, 1 }, + { 0x12011, 1 }, + { 0x12012, 1 }, + { 0x12013, 0x0180 }, + { 0x12018, 1 }, + { 0x12002, 0x6209 }, + { 0x120b2, 1 }, + { 0x121b4, 1 }, + { 0x122b4, 1 }, + { 0x123b4, 1 }, + { 0x124b4, 1 }, + { 0x125b4, 1 }, + { 0x126b4, 1 }, + { 0x127b4, 1 }, + { 0x128b4, 1 }, + { 0x13011, 1 }, + { 0x13012, 1 }, + { 0x13013, 0x0180 }, + { 0x13018, 1 }, + { 0x13002, 0x6209 }, + { 0x130b2, 1 }, + { 0x131b4, 1 }, + { 0x132b4, 1 }, + { 0x133b4, 1 }, + { 0x134b4, 1 }, + { 0x135b4, 1 }, + { 0x136b4, 1 }, + { 0x137b4, 1 }, + { 0x138b4, 1 }, + { 0x2003a, 2 }, + { 0xc0080, 2 }, + { 0xd0000, 1 } +}; + +static struct dram_fsp_msg lpddr4_dram_fsp_msg[] = { + { + /* P0 3200mts 1D */ + .drate = 3200, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp0_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_cfg), + }, + { + /* P1 667mts 1D */ + .drate = 667, + .fw_type = FW_1D_IMAGE, + .fsp_cfg = lpddr4_fsp1_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp1_cfg), + }, + { + /* P0 3200mts 2D */ + .drate = 3200, + .fw_type = FW_2D_IMAGE, + .fsp_cfg = lpddr4_fsp0_2d_cfg, + .fsp_cfg_num = ARRAY_SIZE(lpddr4_fsp0_2d_cfg), + }, +}; + +/* ddr timing config params */ +struct dram_timing_info dram_timing_ch2 = { + .ddrc_cfg = lpddr4_ddrc_cfg, + .ddrc_cfg_num = ARRAY_SIZE(lpddr4_ddrc_cfg), + .ddrphy_cfg = lpddr4_ddrphy_cfg, + .ddrphy_cfg_num = ARRAY_SIZE(lpddr4_ddrphy_cfg), + .fsp_msg = lpddr4_dram_fsp_msg, + .fsp_msg_num = ARRAY_SIZE(lpddr4_dram_fsp_msg), + .ddrphy_pie = lpddr4_phy_pie, + .ddrphy_pie_num = ARRAY_SIZE(lpddr4_phy_pie), + .fsp_table = { 3200, 667, }, +}; diff --git a/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h b/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h new file mode 100644 index 0000000000..7dcc9a7db7 --- /dev/null +++ b/board/mntre/imx8mq_reform2/lpddr4_timing_ch2.h @@ -0,0 +1,95 @@ +/* + * Copyright Boundary Devices + * + * SPDX-License-Identifier: GPL-2.0+ + */ +#include <config.h> +#include <linux/kernel.h> +#include <asm/arch/ddr.h> +#include <asm/arch/lpddr4_define.h> + +/* MNT Reform2 */ +#define CONFIG_DDR_MB 4096 +#define CONFIG_DDR_RANK_BITS 1 +#define CONFIG_DDR_CHANNEL_CNT 2 + +#ifdef WR_POST_EXT_3200 +#define CH2_VAL_INIT4 ((LPDDR4_MR3 << 16) | 0x00020008) +#else +#define CH2_VAL_INIT4 ((LPDDR4_MR3 << 16) | 8) +#endif + +#if CONFIG_DDR_MB == 1024 + /* Address map is from MSB 28: r14, r13-r0, b2-b0, c9-c0 */ +#define CH2_VAL_DDRC_ADDRMAP0_R0 0x0000001F +#define CH2_VAL_DDRC_ADDRMAP6_R0 0x0F070707 + +#elif CONFIG_DDR_MB == 2048 + /* Address map is from MSB 28: r15, r14, r13-r0, b2-b0, c9-c0 */ +#define CH2_VAL_DDRC_ADDRMAP0_R0 0x0000001F +#define CH2_VAL_DDRC_ADDRMAP6_R0 0x07070707 + /* Address map is from MSB 28: cs, r14, r13-r0, b2-b0, c9-c0 */ +#define CH2_VAL_DDRC_ADDRMAP0_R1 0x00000016 +#define CH2_VAL_DDRC_ADDRMAP6_R1 0x0F070707 + +#elif CONFIG_DDR_MB == 3072 + /* Address map is from MSB 29: r15, r14, cs, r13-r0, b2-b0, c9-c0 */ +#define CH2_VAL_DDRC_ADDRMAP0_R1 0x00000015 +#define CH2_VAL_DDRC_ADDRMAP6_R1 0x48080707 + +#elif CONFIG_DDR_MB == 4096 + /* Address map is from MSB 29: cs, r15, r14, r13-r0, b2-b0, c9-c0 */ +#define CH2_VAL_DDRC_ADDRMAP0_R1 0x00000017 +#define CH2_VAL_DDRC_ADDRMAP6_R1 0x07070707 +#else +#error unsupported memory size +#endif + +#define LPDDR4_CS_R0 0x1 /* 0 rank bits, 1 chip select */ +#define LPDDR4_CS_R1 0x3 /* 1 rank bit, 2 chip selects */ + +#if (CONFIG_DDR_RANK_BITS == 0) || !defined(CH2_VAL_DDRC_ADDRMAP0_R1) +#ifdef CH2_VAL_DDRC_ADDRMAP0_R0 +#define CH2_LPDDR4_CS LPDDR4_CS_R0 +#define CH2_VAL_DDRC_ADDRMAP0 CH2_VAL_DDRC_ADDRMAP0_R0 +#define CH2_VAL_DDRC_ADDRMAP6 CH2_VAL_DDRC_ADDRMAP6_R0 +#else +#error unsupported memory rank/size +#endif +/* + * rank0 will succeed, even if really rank 1, so we need + * to probe memory if rank0 succeeds + */ +#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1) +#define CH2_LPDDR4_CS_NEW LPDDR4_CS_R1 +#define CH2_VAL_DDRC_ADDRMAP0_NEW CH2_VAL_DDRC_ADDRMAP0_R1 +#define CH2_VAL_DDRC_ADDRMAP6_NEW CH2_VAL_DDRC_ADDRMAP6_R1 +#endif + +#elif (CONFIG_DDR_RANK_BITS == 1) || !defined(CH2_VAL_DDRC_ADDRMAP0_R0) +#ifdef CH2_VAL_DDRC_ADDRMAP0_R1 +#define CH2_LPDDR4_CS LPDDR4_CS_R1 +#define CH2_VAL_DDRC_ADDRMAP0 CH2_VAL_DDRC_ADDRMAP0_R1 +#define CH2_VAL_DDRC_ADDRMAP6 CH2_VAL_DDRC_ADDRMAP6_R1 +#else +#error unsupported memory rank/size +#endif + +#if defined(CH2_VAL_DDRC_ADDRMAP0_R0) && defined(CH2_VAL_DDRC_ADDRMAP0_R1) +#define CH2_LPDDR4_CS_NEW LPDDR4_CS_R0 +#define CH2_VAL_DDRC_ADDRMAP0_NEW CH2_VAL_DDRC_ADDRMAP0_R0 +#define CH2_VAL_DDRC_ADDRMAP6_NEW CH2_VAL_DDRC_ADDRMAP6_R0 +#endif + +#else +#error unsupported rank bits +#endif + +#if (CONFIG_DDR_CHANNEL_CNT == 2) +#if (CONFIG_DDR_RANK_BITS == 0) && !defined(CH2_VAL_DDRC_ADDRMAP0_R0) +#error unsupported options +#endif +#if (CONFIG_DDR_RANK_BITS == 1) && !defined(CH2_VAL_DDRC_ADDRMAP0_R1) +#error unsupported options +#endif +#endif diff --git a/board/mntre/imx8mq_reform2/spl.c b/board/mntre/imx8mq_reform2/spl.c new file mode 100644 index 0000000000..c0885e422c --- /dev/null +++ b/board/mntre/imx8mq_reform2/spl.c @@ -0,0 +1,260 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright 2018 NXP + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <common.h> +#include <hang.h> +#include <image.h> +#include <init.h> +#include <log.h> +#include <asm/global_data.h> +#include <asm/io.h> +#include <errno.h> +#include <asm/io.h> +#include <asm/arch/ddr.h> +#include <asm/arch/imx8mq_pins.h> +#include <asm/arch/sys_proto.h> +#include <asm/arch/clock.h> +#include <asm/mach-imx/iomux-v3.h> +#include <asm/mach-imx/gpio.h> +#include <asm/mach-imx/mxc_i2c.h> +#include <fsl_esdhc_imx.h> +#include <mmc.h> +#include <linux/delay.h> +#include <power/pmic.h> +#include <spl.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern struct dram_timing_info dram_timing_ch2; + +static void spl_dram_init(void) +{ + ddr_init(&dram_timing_ch2); +} + +#define I2C_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE) +#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) +static struct i2c_pads_info i2c_pad_info1 = { + .scl = { + .i2c_mode = IMX8MQ_PAD_I2C1_SCL__I2C1_SCL | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SCL__GPIO5_IO14 | PC, + .gp = IMX_GPIO_NR(5, 14), + }, + .sda = { + .i2c_mode = IMX8MQ_PAD_I2C1_SDA__I2C1_SDA | PC, + .gpio_mode = IMX8MQ_PAD_I2C1_SDA__GPIO5_IO15 | PC, + .gp = IMX_GPIO_NR(5, 15), + }, +}; + +#define USDHC2_VSEL IMX_GPIO_NR(1, 8) +#define USDHC2_CD_GPIO IMX_GPIO_NR(2, 12) +#define USDHC1_PWR_GPIO IMX_GPIO_NR(2, 10) + +int board_mmc_getcd(struct mmc *mmc) +{ + struct fsl_esdhc_cfg *cfg = (struct fsl_esdhc_cfg *)mmc->priv; + int ret = 0; + + switch (cfg->esdhc_base) { + case USDHC1_BASE_ADDR: + ret = 1; + break; + case USDHC2_BASE_ADDR: + ret = !gpio_get_value(USDHC2_CD_GPIO); + return ret; + } + + return 1; +} + +#define USDHC_PAD_CTRL (PAD_CTL_DSE6 | PAD_CTL_HYS | PAD_CTL_PUE | \ + PAD_CTL_FSEL2) +#define USDHC_GPIO_PAD_CTRL (PAD_CTL_PUE | PAD_CTL_DSE1) + +static iomux_v3_cfg_t const usdhc1_pads[] = { + IMX8MQ_PAD_SD1_CLK__USDHC1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_CMD__USDHC1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA0__USDHC1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA1__USDHC1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA2__USDHC1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA3__USDHC1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA4__USDHC1_DATA4 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA5__USDHC1_DATA5 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA6__USDHC1_DATA6 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_DATA7__USDHC1_DATA7 | MUX_PAD_CTRL(USDHC_PAD_CTRL), + IMX8MQ_PAD_SD1_RESET_B__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const usdhc2_pads[] = { + IMX8MQ_PAD_SD2_CLK__USDHC2_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CMD__USDHC2_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA0__USDHC2_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA1__USDHC2_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_DATA2__USDHC2_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0x16 */ + IMX8MQ_PAD_SD2_DATA3__USDHC2_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), /* 0xd6 */ + IMX8MQ_PAD_SD2_CD_B__GPIO2_IO12 | MUX_PAD_CTRL(USDHC_GPIO_PAD_CTRL), + IMX8MQ_PAD_GPIO1_IO08__GPIO1_IO8 | MUX_PAD_CTRL(0x91), +}; + +static struct fsl_esdhc_cfg usdhc_cfg[2] = { + {USDHC1_BASE_ADDR, 0, 8}, + {USDHC2_BASE_ADDR, 0, 4}, +}; + +int board_mmc_init(struct bd_info *bis) +{ + int i, ret; + /* + * According to the board_mmc_init() the following map is done: + * (U-Boot device node) (Physical Port) + * mmc0 USDHC1 + * mmc1 USDHC2 + */ + for (i = 0; i < CONFIG_SYS_FSL_USDHC_NUM; i++) { + switch (i) { + case 0: + init_clk_usdhc(0); + usdhc_cfg[0].sdhc_clk = mxc_get_clock(USDHC1_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads(usdhc1_pads, + ARRAY_SIZE(usdhc1_pads)); + gpio_request(USDHC1_PWR_GPIO, "usdhc1_reset"); + gpio_direction_output(USDHC1_PWR_GPIO, 0); + udelay(500); + gpio_direction_output(USDHC1_PWR_GPIO, 1); + break; + case 1: + init_clk_usdhc(1); + usdhc_cfg[1].sdhc_clk = mxc_get_clock(USDHC2_CLK_ROOT); + imx_iomux_v3_setup_multiple_pads(usdhc2_pads, + ARRAY_SIZE(usdhc2_pads)); + gpio_request(USDHC2_VSEL, "usdhc2_vsel"); + gpio_direction_output(USDHC2_VSEL, 0); + break; + default: + printf("Warning: you configured more USDHC controllers(%d) than supported by the board\n", i + 1); + return -EINVAL; + } + + ret = fsl_esdhc_initialize(bis, &usdhc_cfg[i]); + if (ret) + return ret; + } + + return 0; +} + +#define I2C1_PCA9546_RESET IMX_GPIO_NR(1, 4) +#define ARM_DRAM_VSEL IMX_GPIO_NR(3, 24) +#define DRAM_1P1_VSEL IMX_GPIO_NR(2, 11) +#define SOC_GPU_VPU_VSEL IMX_GPIO_NR(2, 20) + +#define I2C_MUX_ADDR 0x70 +#define I2C_FAN53555_ADDR 0x60 + +static iomux_v3_cfg_t const power_pads[] = { + IMX8MQ_PAD_GPIO1_IO04__GPIO1_IO4 | MUX_PAD_CTRL(0x46), +}; + +int power_init_board(void) +{ + uint8_t val; + + imx_iomux_v3_setup_multiple_pads(power_pads, + ARRAY_SIZE(usdhc2_pads)); + + /* Release I2C multiplexer reset */ + gpio_request(I2C1_PCA9546_RESET, "pca9546_reset"); + gpio_direction_output(I2C1_PCA9546_RESET, 1); + + /* Select VSEL0 on voltage regulators */ + gpio_request(ARM_DRAM_VSEL, "arm_dram_vsel"); + gpio_direction_output(ARM_DRAM_VSEL, 0); + gpio_request(DRAM_1P1_VSEL, "dram_1p1_vsel"); + gpio_direction_output(DRAM_1P1_VSEL, 0); + gpio_request(SOC_GPU_VPU_VSEL, "soc_gpu_vpu_vsel"); + gpio_direction_output(SOC_GPU_VPU_VSEL, 0); + + /* Set mux to target ARM/DRAM regulator */ + i2c_write(I2C_MUX_ADDR, 1, 1, NULL, 0); + /* .6 + .40 = 1.00 */ + val = 0x80 + 40; + i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1); + i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1); + + /* Set mux to target DRAM regulator */ + i2c_write(I2C_MUX_ADDR, 2, 1, NULL, 0); + /* .6 + .50 = 1.10 */ + val = 0x80 + 50; + i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1); + i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1); + + /* Set mux to target SoC/GPU/VPU regulator */ + i2c_write(I2C_MUX_ADDR, 4, 1, NULL, 0); + /* .6 + .30 = .90 */ + val = 0x80 + 30; + i2c_write(I2C_FAN53555_ADDR, 0, 1, &val, 1); + i2c_write(I2C_FAN53555_ADDR, 1, 1, &val, 1); + + /* Set mux to target peripherals */ + i2c_write(I2C_MUX_ADDR, 8, 1, NULL, 0); + + return 0; +} + +void spl_board_init(void) +{ + puts("Normal Boot\n"); +} + +#ifdef CONFIG_SPL_LOAD_FIT +int board_fit_config_name_match(const char *name) +{ + /* Just empty function now - can't decide what to choose */ + debug("%s: %s\n", __func__, name); + + return 0; +} +#endif + +void board_init_f(ulong dummy) +{ + int ret; + + /* Clear global data */ + memset((void *)gd, 0, sizeof(gd_t)); + + arch_cpu_init(); + + init_uart_clk(0); + + board_early_init_f(); + + timer_init(); + + preloader_console_init(); + + /* Clear the BSS. */ + memset(__bss_start, 0, __bss_end - __bss_start); + + ret = spl_init(); + if (ret) { + debug("spl_init() failed: %d\n", ret); + hang(); + } + + enable_tzc380(); + + setup_i2c(0, CONFIG_SYS_I2C_SPEED, 0x7f, &i2c_pad_info1); + + power_init_board(); + + /* DDR initialization */ + spl_dram_init(); + + board_init_r(NULL, 0); +} diff --git a/configs/imx8mq_reform2_defconfig b/configs/imx8mq_reform2_defconfig new file mode 100644 index 0000000000..2e91a08cc7 --- /dev/null +++ b/configs/imx8mq_reform2_defconfig @@ -0,0 +1,56 @@ +CONFIG_ARM=y +CONFIG_ARCH_IMX8M=y +CONFIG_SYS_TEXT_BASE=0x40200000 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x400000 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="imx8mq-mnt-reform2" +CONFIG_SPL_TEXT_BASE=0x7E1000 +CONFIG_TARGET_IMX8MQ_REFORM2=y +CONFIG_SPL_SERIAL_SUPPORT=y +CONFIG_SPL=y +CONFIG_DISTRO_DEFAULTS=y +CONFIG_FIT=y +CONFIG_FIT_EXTERNAL_OFFSET=0x3000 +CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_FIT_GENERATOR="arch/arm/mach-imx/mkimage_fit_atf.sh" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=arch/arm/mach-imx/imx8m/imximage.cfg" +CONFIG_DEFAULT_FDT_FILE="imx8mq-mnt-reform2.dtb" +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_BOARD_LATE_INIT=y +CONFIG_SPL_BOARD_INIT=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_CMD_EXPORTENV is not set +# CONFIG_CMD_IMPORTENV is not set +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_FUSE=y +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_MDIO is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_OF_CONTROL=y +CONFIG_ENV_OVERWRITE=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_SYS_MMC_ENV_DEV=1 +CONFIG_SAVED_DRAM_TIMING_BASE=0x40000000 +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MXC=y +CONFIG_SUPPORT_EMMC_BOOT=y +CONFIG_FSL_USDHC=y +CONFIG_PHYLIB=y +CONFIG_PHY_ATHEROS=y +CONFIG_DM_ETH=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX8M=y +CONFIG_POWER_DOMAIN=y +CONFIG_IMX8M_POWER_DOMAIN=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_DM_RESET=y +CONFIG_MXC_UART=y +CONFIG_DM_THERMAL=y diff --git a/include/configs/imx8mq_reform2.h b/include/configs/imx8mq_reform2.h new file mode 100644 index 0000000000..b8bfe62337 --- /dev/null +++ b/include/configs/imx8mq_reform2.h @@ -0,0 +1,149 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright 2018 NXP + */ + +#ifndef __IMX8M_REFORM2_H +#define __IMX8M_REFORM2_H + +#include <linux/sizes.h> +#include <linux/stringify.h> +#include <asm/arch/imx-regs.h> + +#define CONFIG_SYS_BOOTM_LEN (32 * SZ_1M) + +#define CONFIG_SPL_MAX_SIZE (124 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 + +#ifdef CONFIG_SPL_BUILD +/*#define CONFIG_ENABLE_DDR_TRAINING_DEBUG*/ +#define CONFIG_SPL_WATCHDOG_SUPPORT +#define CONFIG_SPL_DRIVERS_MISC_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv8/u-boot-spl.lds" +#define CONFIG_SPL_STACK 0x187FF0 +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_GPIO_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_BSS_START_ADDR 0x00180000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x2000 /* 8 KB */ +#define CONFIG_SYS_SPL_MALLOC_START 0x42200000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x80000 /* 512 KB */ +#define CONFIG_SYS_SPL_PTE_RAM_BASE 0x41580000 + +/* malloc f used before GD_FLG_FULL_MALLOC_INIT set */ +#define CONFIG_MALLOC_F_ADDR 0x182000 +/* For RAW image gives a error info not panic */ +#define CONFIG_SPL_ABORT_ON_RAW_IMAGE + +#undef CONFIG_DM_MMC +#undef CONFIG_DM_PMIC +#undef CONFIG_DM_PMIC_PFUZE100 + +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ +#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ +#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ + +#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG + +#define CONFIG_POWER +#define CONFIG_POWER_I2C +#endif + +#define CONFIG_REMAKE_ELF + +/* ENET Config */ +/* ENET1 */ +#if defined(CONFIG_CMD_NET) +#define CONFIG_MII +#define CONFIG_ETHPRIME "FEC" + +#define CONFIG_FEC_MXC +#define CONFIG_FEC_XCV_TYPE RGMII +#define CONFIG_FEC_MXC_PHYADDR 4 +#define FEC_QUIRK_ENET_MAC + +#define CONFIG_PHY_GIGE +#define IMX_FEC_BASE 0x30BE0000 +#endif + +#ifndef CONFIG_SPL_BUILD +#define BOOT_TARGET_DEVICES(func) \ + func(MMC, mmc, 1) \ + func(MMC, mmc, 0) \ + func(DHCP, dhcp, na) + +#include <config_distro_bootcmd.h> +#endif + +/* Initial environment variables */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + BOOTENV \ + "scriptaddr=" __stringify(CONFIG_LOADADDR) "\0" \ + "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ + "image=Image\0" \ + "console=ttymxc0,115200\0" \ + "fdt_addr_r=0x43000000\0" \ + "boot_fdt=try\0" \ + "fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \ + "initrd_addr=0x43800000\0" \ + "bootm_size=0x10000000\0" \ + "mmcpart=" __stringify(CONFIG_SYS_MMC_IMG_LOAD_PART) "\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + +/* Link Definitions */ +#define CONFIG_LOADADDR 0x40480000 + +#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR + +#define CONFIG_SYS_INIT_RAM_ADDR 0x40000000 +#define CONFIG_SYS_INIT_RAM_SIZE 0x80000 +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_MMCROOT "/dev/mmcblk1p2" /* USDHC2 */ + +/* Size of malloc() pool */ +#define CONFIG_SYS_MALLOC_LEN ((CONFIG_ENV_SIZE + (2 * 1024)) * 1024) + +#define CONFIG_SYS_SDRAM_BASE 0x40000000 +#define PHYS_SDRAM 0x40000000 +#define PHYS_SDRAM_SIZE 0x100000000 /* 4GB DDR */ + +#define CONFIG_MXC_UART_BASE UART1_BASE_ADDR + +/* Monitor Command Prompt */ +#undef CONFIG_SYS_PROMPT +#define CONFIG_SYS_PROMPT "u-boot=> " +#define CONFIG_SYS_CBSIZE 1024 +#define CONFIG_SYS_MAXARGS 64 +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ + sizeof(CONFIG_SYS_PROMPT) + 16) + +#define CONFIG_IMX_BOOTAUX + +#define CONFIG_SYS_FSL_USDHC_NUM 2 +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define CONFIG_SYS_MMC_IMG_LOAD_PART 1 + +#define CONFIG_MXC_GPIO + +/* I2C Configs */ +#define CONFIG_SYS_I2C_SPEED 100000 + +#define CONFIG_OF_SYSTEM_SETUP + +#ifndef CONFIG_SPL_BUILD +#define CONFIG_DM_PMIC +#endif + +#endif
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Patrick Wildt