[U-Boot] [PATCH 0/2] am43xx: Enable QUAD mode and DMA support for QSPI
This patchset enables QUAD mode and DMA support for qspi read on am437x. This increases the througput to 4 MB/s.
Tested on am437x-sk and am437x-idk evm.
Vignesh R (2): spi: ti_qspi: Add dummy readl for bus sync ARM: am437xx: Enable QUAD read and EDMA support for ti_qspi
arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 3 +++ drivers/spi/ti_qspi.c | 2 ++ include/configs/am43xx_evm.h | 2 ++ 3 files changed, 7 insertions(+)
Add dummy readl after invalidating cmd field of QSPI_CMD_REG to ensure bus sync. Without this device's CS is not deactivated reliably leading to failure to enumerate flash or failure to set quad enable bit on Macronix flash present on am437x-sk and am437x-idk evms.
Signed-off-by: Vignesh R vigneshr@ti.com --- drivers/spi/ti_qspi.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index bd63db8a2acc..ba2da017c21a 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -170,6 +170,8 @@ void spi_cs_deactivate(struct spi_slave *slave) debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd); + /* dummy readl to ensure bus sync */ + readl(&qslave->base->cmd); }
void spi_init(void)
On Tuesday 10 November 2015 11:52 AM, Vignesh R wrote:
Add dummy readl after invalidating cmd field of QSPI_CMD_REG to ensure bus sync. Without this device's CS is not deactivated reliably leading to failure to enumerate flash or failure to set quad enable bit on Macronix flash present on am437x-sk and am437x-idk evms.
Signed-off-by: Vignesh R vigneshr@ti.com
Reviewed-by: Mugunthan V N mugunthanvnm@ti.com
Regards Mugunthan V N
On 10 November 2015 at 11:52, Vignesh R vigneshr@ti.com wrote:
Add dummy readl after invalidating cmd field of QSPI_CMD_REG to ensure bus sync. Without this device's CS is not deactivated reliably leading to failure to enumerate flash or failure to set quad enable bit on Macronix flash present on am437x-sk and am437x-idk evms.
Signed-off-by: Vignesh R vigneshr@ti.com
drivers/spi/ti_qspi.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index bd63db8a2acc..ba2da017c21a 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -170,6 +170,8 @@ void spi_cs_deactivate(struct spi_slave *slave) debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd);
/* dummy readl to ensure bus sync */readl(&qslave->base->cmd);
Isn't effect anything for non-quad case? and dummy bytes might changed based on quad and quadio does this single dummy readl is same for those cases as well?
thanks!
On 11/17/2015 11:33 AM, Jagan Teki wrote:
On 10 November 2015 at 11:52, Vignesh R vigneshr@ti.com wrote:
Add dummy readl after invalidating cmd field of QSPI_CMD_REG to ensure bus sync. Without this device's CS is not deactivated reliably leading to failure to enumerate flash or failure to set quad enable bit on Macronix flash present on am437x-sk and am437x-idk evms.
Signed-off-by: Vignesh R vigneshr@ti.com
drivers/spi/ti_qspi.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index bd63db8a2acc..ba2da017c21a 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -170,6 +170,8 @@ void spi_cs_deactivate(struct spi_slave *slave) debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd);
/* dummy readl to ensure bus sync */readl(&qslave->base->cmd);Isn't effect anything for non-quad case? and dummy bytes might changed based on quad and quadio does this single dummy readl is same for those cases as well?
No, this dummy readl is not related as dummy bytes used in QUAD mode.
In ti_qspi controller, in order to end a read/write request (ie to deassert ChipSelect) invalid cmd(0x4) needs to be written to CMD field of QSPI_CMD_REG (which is done by above function) in all modes. Sometimes, this write may have been flushed out of ARM but may not have reached the QSPI IP yet (ie bus/interconnect is not flushed yet) hence ChipSelect is not deactivated. Therefore, the successive write/read operation may overlaps resulting in wrong data being read from flash. Reading back QSPI_CMD_REG makes sure that the bus/interconnect is flushed and register write is affected making sure CS is deactivated.
On 17 November 2015 at 11:57, Vignesh R vigneshr@ti.com wrote:
On 11/17/2015 11:33 AM, Jagan Teki wrote:
On 10 November 2015 at 11:52, Vignesh R vigneshr@ti.com wrote:
Add dummy readl after invalidating cmd field of QSPI_CMD_REG to ensure bus sync. Without this device's CS is not deactivated reliably leading to failure to enumerate flash or failure to set quad enable bit on Macronix flash present on am437x-sk and am437x-idk evms.
Signed-off-by: Vignesh R vigneshr@ti.com
drivers/spi/ti_qspi.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index bd63db8a2acc..ba2da017c21a 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -170,6 +170,8 @@ void spi_cs_deactivate(struct spi_slave *slave) debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd);
/* dummy readl to ensure bus sync */readl(&qslave->base->cmd);Isn't effect anything for non-quad case? and dummy bytes might changed based on quad and quadio does this single dummy readl is same for those cases as well?
No, this dummy readl is not related as dummy bytes used in QUAD mode.
In ti_qspi controller, in order to end a read/write request (ie to deassert ChipSelect) invalid cmd(0x4) needs to be written to CMD field of QSPI_CMD_REG (which is done by above function) in all modes. Sometimes, this write may have been flushed out of ARM but may not have reached the QSPI IP yet (ie bus/interconnect is not flushed yet) hence ChipSelect is not deactivated. Therefore, the successive write/read operation may overlaps resulting in wrong data being read from flash. Reading back QSPI_CMD_REG makes sure that the bus/interconnect is flushed and register write is affected making sure CS is deactivated.
Thanks for the info.
Reviewed-by: Jagan Teki jteki@openedev.com
On 17 November 2015 at 12:16, Jagan Teki jteki@openedev.com wrote:
On 17 November 2015 at 11:57, Vignesh R vigneshr@ti.com wrote:
On 11/17/2015 11:33 AM, Jagan Teki wrote:
On 10 November 2015 at 11:52, Vignesh R vigneshr@ti.com wrote:
Add dummy readl after invalidating cmd field of QSPI_CMD_REG to ensure bus sync. Without this device's CS is not deactivated reliably leading to failure to enumerate flash or failure to set quad enable bit on Macronix flash present on am437x-sk and am437x-idk evms.
Signed-off-by: Vignesh R vigneshr@ti.com
drivers/spi/ti_qspi.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/spi/ti_qspi.c b/drivers/spi/ti_qspi.c index bd63db8a2acc..ba2da017c21a 100644 --- a/drivers/spi/ti_qspi.c +++ b/drivers/spi/ti_qspi.c @@ -170,6 +170,8 @@ void spi_cs_deactivate(struct spi_slave *slave) debug("spi_cs_deactivate: 0x%08x\n", (u32)slave);
writel(qslave->cmd | QSPI_INVAL, &qslave->base->cmd);
/* dummy readl to ensure bus sync */readl(&qslave->base->cmd);Isn't effect anything for non-quad case? and dummy bytes might changed based on quad and quadio does this single dummy readl is same for those cases as well?
No, this dummy readl is not related as dummy bytes used in QUAD mode.
In ti_qspi controller, in order to end a read/write request (ie to deassert ChipSelect) invalid cmd(0x4) needs to be written to CMD field of QSPI_CMD_REG (which is done by above function) in all modes. Sometimes, this write may have been flushed out of ARM but may not have reached the QSPI IP yet (ie bus/interconnect is not flushed yet) hence ChipSelect is not deactivated. Therefore, the successive write/read operation may overlaps resulting in wrong data being read from flash. Reading back QSPI_CMD_REG makes sure that the bus/interconnect is flushed and register write is affected making sure CS is deactivated.
Thanks for the info.
Reviewed-by: Jagan Teki jteki@openedev.com
Applied to u-boot-spi/master
thanks!
Enable TI_EDMA3 and QUAD read support for ti_qspi on am43xx, this increases read performance to 4 MB/s.
Signed-off-by: Vignesh R vigneshr@ti.com --- arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 3 +++ include/configs/am43xx_evm.h | 2 ++ 2 files changed, 5 insertions(+)
diff --git a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h index 479893e47ea1..a7da6b5cfde6 100644 --- a/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h +++ b/arch/arm/include/asm/arch-am33xx/hardware_am43xx.h @@ -98,4 +98,7 @@
#define NUM_CRYSTAL_FREQ 0x4
+/* EDMA3 Base Address */ +#define EDMA3_BASE 0x49000000 + #endif /* __AM43XX_HARDWARE_AM43XX_H */ diff --git a/include/configs/am43xx_evm.h b/include/configs/am43xx_evm.h index d93e3e7619d9..e235fd9a0e79 100644 --- a/include/configs/am43xx_evm.h +++ b/include/configs/am43xx_evm.h @@ -220,6 +220,8 @@ #define CONFIG_QSPI_SEL_GPIO 48 #define CONFIG_SF_DEFAULT_SPEED 48000000 #define CONFIG_DEFAULT_SPI_MODE SPI_MODE_3 +#define CONFIG_QSPI_QUAD_SUPPORT +#define CONFIG_TI_EDMA3
/* Enhance our eMMC support / experience. */ #define CONFIG_CMD_GPT
On Tuesday 10 November 2015 11:52 AM, Vignesh R wrote:
Enable TI_EDMA3 and QUAD read support for ti_qspi on am43xx, this increases read performance to 4 MB/s.
Signed-off-by: Vignesh R vigneshr@ti.com
Reviewed-by: Mugunthan V N mugunthanvnm@ti.com
Regards Mugunthan V N
On 12 November 2015 at 15:17, Mugunthan V N mugunthanvnm@ti.com wrote:
On Tuesday 10 November 2015 11:52 AM, Vignesh R wrote:
Enable TI_EDMA3 and QUAD read support for ti_qspi on am43xx, this increases read performance to 4 MB/s.
Signed-off-by: Vignesh R vigneshr@ti.com
Reviewed-by: Mugunthan V N mugunthanvnm@ti.com
Reviewed-by: Jagan Teki jteki@openedev.com
thanks!
On 17 November 2015 at 11:29, Jagan Teki jteki@openedev.com wrote:
On 12 November 2015 at 15:17, Mugunthan V N mugunthanvnm@ti.com wrote:
On Tuesday 10 November 2015 11:52 AM, Vignesh R wrote:
Enable TI_EDMA3 and QUAD read support for ti_qspi on am43xx, this increases read performance to 4 MB/s.
Signed-off-by: Vignesh R vigneshr@ti.com
Reviewed-by: Mugunthan V N mugunthanvnm@ti.com
Reviewed-by: Jagan Teki jteki@openedev.com
Applied to u-boot-spi/master
thanks!
On 11/10/2015 11:52 AM, Vignesh R wrote:
This patchset enables QUAD mode and DMA support for qspi read on am437x. This increases the througput to 4 MB/s.
Tested on am437x-sk and am437x-idk evm.
Vignesh R (2): spi: ti_qspi: Add dummy readl for bus sync ARM: am437xx: Enable QUAD read and EDMA support for ti_qspi
arch/arm/include/asm/arch-am33xx/hardware_am43xx.h | 3 +++ drivers/spi/ti_qspi.c | 2 ++ include/configs/am43xx_evm.h | 2 ++ 3 files changed, 7 insertions(+)
Gentle ping on the series...
participants (3)
-
Jagan Teki -
Mugunthan V N -
Vignesh R