[U-Boot] [PATCH 1/3] armv8: fsl-layerscape: SPL size reduction
Using changes in this patch we were able to reduce approx 4k size of u-boot-spl.bin image. Following is breif description of changes to reduce SPL size: 1. Compile-off mp.c and libfdt.c in case of SPL build. 2. Keep MMU and DCACHE specific variable and functions under CONFIG_SYS_DCACHE_OFF macro. 3. Compile-off IFC specific funtion call "init_early_memctl_regs" in case of SPL build.
Signed-off-by: Sumit Garg sumit.garg@nxp.com ---
Dependent on ls1088 base SD boot target. Also dependent on ls1088 QPSI secure boot target.
arch/arm/cpu/armv8/fsl-layerscape/Makefile | 2 ++ arch/arm/cpu/armv8/fsl-layerscape/cpu.c | 6 ++++++ arch/arm/cpu/armv8/fsl-layerscape/soc.c | 2 ++ 3 files changed, 10 insertions(+)
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/Makefile b/arch/arm/cpu/armv8/fsl-layerscape/Makefile index 115c3fc..0cb6d4e 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/Makefile +++ b/arch/arm/cpu/armv8/fsl-layerscape/Makefile @@ -7,8 +7,10 @@ obj-y += cpu.o obj-y += lowlevel.o obj-y += soc.o +ifndef CONFIG_SPL_BUILD obj-$(CONFIG_MP) += mp.o obj-$(CONFIG_OF_LIBFDT) += fdt.o +endif obj-$(CONFIG_SPL) += spl.o obj-$(CONFIG_$(SPL_)FSL_LS_PPA) += ppa.o
diff --git a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c index 3c9a5ed..3ce51af 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/cpu.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/cpu.c @@ -32,7 +32,9 @@
DECLARE_GLOBAL_DATA_PTR;
+#ifndef CONFIG_SYS_DCACHE_OFF struct mm_region *mem_map = early_map; +#endif
void cpu_name(char *name) { @@ -824,6 +826,7 @@ void efi_add_known_memory(void) } #endif
+#ifndef CONFIG_SYS_DCACHE_OFF /* * Before DDR size is known, early MMU table have DDR mapped as device memory * to avoid speculative access. To relocate U-Boot to DDR, "normal memory" @@ -888,14 +891,17 @@ void update_early_mmu_table(void) } } } +#endif
__weak int dram_init(void) { fsl_initdram(); +#ifndef CONFIG_SYS_DCACHE_OFF #if !defined(CONFIG_SPL) || defined(CONFIG_SPL_BUILD) /* This will break-before-make MMU for DDR */ update_early_mmu_table(); #endif +#endif
return 0; } diff --git a/arch/arm/cpu/armv8/fsl-layerscape/soc.c b/arch/arm/cpu/armv8/fsl-layerscape/soc.c index 2075c96..7c26953 100644 --- a/arch/arm/cpu/armv8/fsl-layerscape/soc.c +++ b/arch/arm/cpu/armv8/fsl-layerscape/soc.c @@ -329,7 +329,9 @@ void bypass_smmu(void) void fsl_lsch3_early_init_f(void) { erratum_rcw_src(); +#ifndef CONFIG_SPL_BUILD init_early_memctl_regs(); /* tighten IFC timing */ +#endif #ifdef CONFIG_SYS_FSL_ERRATUM_A009203 erratum_a009203(); #endif
Using changes in this patch we were able to reduce approx 8k size of u-boot-spl.bin image. Following is breif description of changes to reduce SPL size: 1. Changes in board/freescale/ls1088a/Makefile to remove compilation of eth.c and cpld.c in case of SPL build. 2. Changes in board/freescale/ls1088a/ls1088a.c to keep board_early_init_f funcations in case of SPL build. 3. Changes in ls1088a_common.h & ls1088ardb.h to remove driver specific macros due to which static data was being compiled in case of SPL build. 4. Enable CONFIG_SYS_DCACHE_OFF in case of SPL build as DCACHE is not being enabled in case of SPL image but was compiled in to add redundant code.
Signed-off-by: Sumit Garg sumit.garg@nxp.com ---
Dependent on ls1088 base SD boot target. Also dependent on ls1088 QPSI secure boot target.
board/freescale/ls1088a/Makefile | 4 +++- board/freescale/ls1088a/ls1088a.c | 14 ++++++++------ include/configs/ls1088a_common.h | 20 ++++++++++++++++++++ include/configs/ls1088ardb.h | 20 ++++++++++++++++++++ 4 files changed, 51 insertions(+), 7 deletions(-)
diff --git a/board/freescale/ls1088a/Makefile b/board/freescale/ls1088a/Makefile index bdcce9e..0e15031 100644 --- a/board/freescale/ls1088a/Makefile +++ b/board/freescale/ls1088a/Makefile @@ -5,6 +5,8 @@ #
obj-y += ls1088a.o +obj-y += ddr.o +ifndef CONFIG_SPL_BUILD obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o -obj-y += ddr.o +endif diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 1860f9c..1c28ab4 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -24,6 +24,13 @@
DECLARE_GLOBAL_DATA_PTR;
+int board_early_init_f(void) +{ + fsl_lsch3_early_init_f(); + return 0; +} + +#if !defined(CONFIG_SPL_BUILD) unsigned long long get_qixis_addr(void) { unsigned long long addr; @@ -324,12 +331,6 @@ int board_init(void) return 0; }
-int board_early_init_f(void) -{ - fsl_lsch3_early_init_f(); - return 0; -} - void detail_board_ddr_info(void) { puts("\nDDR "); @@ -404,3 +405,4 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } #endif +#endif /* defined(CONFIG_SPL_BUILD) */ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 63b69f8..fb4c852 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -7,6 +7,20 @@ #ifndef __LS1088_COMMON_H #define __LS1088_COMMON_H
+/* SPL build */ +#ifdef CONFIG_SPL_BUILD +#define SPL_NO_BOARDINFO +#define SPL_NO_QIXIS +#define SPL_NO_PCI +#define SPL_NO_ENV +#define SPL_NO_RTC +#define SPL_NO_USB +#define SPL_NO_SATA +#define SPL_NO_QSPI +#define SPL_NO_IFC +#define CONFIG_SYS_DCACHE_OFF +#undef CONFIG_DISPLAY_CPUINFO +#endif
#define CONFIG_REMAKE_ELF #define CONFIG_FSL_LAYERSCAPE @@ -70,8 +84,10 @@ #define CONFIG_BAUDRATE 115200 #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
+#ifndef SPL_NO_IFC /* IFC */ #define CONFIG_FSL_IFC +#endif
/* * During booting, IFC is mapped at the region of 0x30000000. @@ -154,6 +170,7 @@ unsigned long long get_qixis_addr(void);
/* #define CONFIG_DISPLAY_CPUINFO */
+#ifndef SPL_NO_ENV /* Allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE
@@ -192,6 +209,7 @@ unsigned long long get_qixis_addr(void); " cp.b $kernel_start $kernel_load" \ " $kernel_size && bootm $kernel_load" #endif +#endif
/* Monitor Command Prompt */ #define CONFIG_SYS_CBSIZE 512 /* Console I/O Buffer Size */ @@ -200,7 +218,9 @@ unsigned long long get_qixis_addr(void); #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot args buffer */ #define CONFIG_SYS_LONGHELP +#ifndef SPL_NO_ENV #define CONFIG_CMDLINE_EDITING 1 +#endif #define CONFIG_AUTO_COMPLETE #define CONFIG_SYS_MAXARGS 64 /* max command args */
diff --git a/include/configs/ls1088ardb.h b/include/configs/ls1088ardb.h index 1d2dd4f..913252d 100644 --- a/include/configs/ls1088ardb.h +++ b/include/configs/ls1088ardb.h @@ -9,7 +9,9 @@
#include "ls1088a_common.h"
+#ifndef SPL_NO_BOARDINFO #define CONFIG_DISPLAY_BOARDINFO_LATE +#endif
#if defined(CONFIG_QSPI_BOOT) #define CONFIG_ENV_IS_IN_SPI_FLASH @@ -29,7 +31,9 @@ #endif
#if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) +#ifndef CONFIG_SPL_BUILD #define CONFIG_QIXIS_I2C_ACCESS +#endif #define SYS_NO_FLASH #undef CONFIG_CMD_IMLS #endif @@ -97,7 +101,11 @@ #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } #endif #endif + +#ifndef SPL_NO_IFC #define CONFIG_NAND_FSL_IFC +#endif + #define CONFIG_SYS_NAND_MAX_ECCPOS 256 #define CONFIG_SYS_NAND_MAX_OOBFREE 2
@@ -139,7 +147,10 @@
#define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024)
+#ifndef SPL_NO_QIXIS #define CONFIG_FSL_QIXIS +#endif + #define CONFIG_SYS_I2C_FPGA_ADDR 0x66 #define QIXIS_LBMAP_SWITCH 2 #define QIXIS_QMAP_MASK 0xe0 @@ -223,6 +234,8 @@ #define I2C_RETIMER_ADDR 0x18 #define I2C_MUX_CH_DEFAULT 0x8 #define I2C_MUX_CH5 0xD + +#ifndef SPL_NO_RTC /* * RTC configuration */ @@ -230,6 +243,7 @@ #define CONFIG_RTC_PCF8563 1 #define CONFIG_SYS_I2C_RTC_ADDR 0x51 /* Channel 3*/ #define CONFIG_CMD_DATE +#endif
/* EEPROM */ #define CONFIG_ID_EEPROM @@ -240,6 +254,7 @@ #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 5
+#ifndef SPL_NO_QSPI /* QSPI device */ #if defined(CONFIG_QSPI_BOOT) || defined(CONFIG_SD_BOOT_QSPI) #define CONFIG_FSL_QSPI @@ -247,6 +262,7 @@ #define FSL_QSPI_FLASH_SIZE (1 << 26) #define FSL_QSPI_FLASH_NUM 2 #endif +#endif
#define CONFIG_CMD_MEMINFO #define CONFIG_CMD_MEMTEST @@ -260,6 +276,7 @@ #endif #define CONFIG_FSL_MEMAC
+#ifndef SPL_NO_ENV /* Initial environment variables */ #ifdef CONFIG_SECURE_BOOT #undef CONFIG_EXTRA_ENV_SETTINGS @@ -342,6 +359,7 @@ #define CONFIG_ETHPRIME "DPMAC1@xgmii" #define CONFIG_PHY_GIGE #endif +#endif
/* MMC */ #ifdef CONFIG_MMC @@ -349,6 +367,7 @@ #define CONFIG_SYS_FSL_MMC_HAS_CAPBLT_VS33 #endif
+#ifndef SPL_NO_ENV #undef CONFIG_CMDLINE_EDITING #include <config_distro_defaults.h>
@@ -358,6 +377,7 @@ func(SCSI, scsi, 0) \ func(DHCP, dhcp, na) #include <config_distro_bootcmd.h> +#endif
#include <asm/fsl_secure_boot.h>
On 08/29/2017 12:02 AM, Sumit Garg wrote:
Using changes in this patch we were able to reduce approx 8k size of u-boot-spl.bin image. Following is breif description of changes to reduce SPL size:
- Changes in board/freescale/ls1088a/Makefile to remove compilation of eth.c and cpld.c in case of SPL build.
- Changes in board/freescale/ls1088a/ls1088a.c to keep board_early_init_f funcations in case of SPL build.
- Changes in ls1088a_common.h & ls1088ardb.h to remove driver specific macros due to which static data was being compiled in case of SPL build.
- Enable CONFIG_SYS_DCACHE_OFF in case of SPL build as DCACHE is not being enabled in case of SPL image but was compiled in to add redundant code.
Signed-off-by: Sumit Garg sumit.garg@nxp.com
Dependent on ls1088 base SD boot target. Also dependent on ls1088 QPSI secure boot target.
board/freescale/ls1088a/Makefile | 4 +++- board/freescale/ls1088a/ls1088a.c | 14 ++++++++------ include/configs/ls1088a_common.h | 20 ++++++++++++++++++++ include/configs/ls1088ardb.h | 20 ++++++++++++++++++++ 4 files changed, 51 insertions(+), 7 deletions(-)
diff --git a/board/freescale/ls1088a/Makefile b/board/freescale/ls1088a/Makefile index bdcce9e..0e15031 100644 --- a/board/freescale/ls1088a/Makefile +++ b/board/freescale/ls1088a/Makefile @@ -5,6 +5,8 @@ #
obj-y += ls1088a.o +obj-y += ddr.o +ifndef CONFIG_SPL_BUILD obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o -obj-y += ddr.o +endif diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 1860f9c..1c28ab4 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -24,6 +24,13 @@
DECLARE_GLOBAL_DATA_PTR;
+int board_early_init_f(void) +{
- fsl_lsch3_early_init_f();
- return 0;
+}
+#if !defined(CONFIG_SPL_BUILD) unsigned long long get_qixis_addr(void) { unsigned long long addr; @@ -324,12 +331,6 @@ int board_init(void) return 0; }
-int board_early_init_f(void) -{
- fsl_lsch3_early_init_f();
- return 0;
-}
- void detail_board_ddr_info(void) { puts("\nDDR ");
@@ -404,3 +405,4 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } #endif +#endif /* defined(CONFIG_SPL_BUILD) */ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 63b69f8..fb4c852 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -7,6 +7,20 @@ #ifndef __LS1088_COMMON_H #define __LS1088_COMMON_H
+/* SPL build */ +#ifdef CONFIG_SPL_BUILD +#define SPL_NO_BOARDINFO +#define SPL_NO_QIXIS +#define SPL_NO_PCI +#define SPL_NO_ENV +#define SPL_NO_RTC +#define SPL_NO_USB +#define SPL_NO_SATA +#define SPL_NO_QSPI +#define SPL_NO_IFC +#define CONFIG_SYS_DCACHE_OFF
How much space can you save with data cache off? I prefer to leave the cache on. Cache is used if PPA is loaded in SPL stage for boost booting speed.
York
-----Original Message----- From: York Sun Sent: Tuesday, August 29, 2017 9:25 PM To: Sumit Garg sumit.garg@nxp.com; u-boot@lists.denx.de Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Ruchika Gupta ruchika.gupta@nxp.com Subject: Re: [u-boot-release] [PATCH 2/3] armv8: ls1088a: SPL size reduction
On 08/29/2017 12:02 AM, Sumit Garg wrote:
Using changes in this patch we were able to reduce approx 8k size of u-boot-spl.bin image. Following is breif description of changes to reduce SPL size:
- Changes in board/freescale/ls1088a/Makefile to remove compilation of eth.c and cpld.c in case of SPL build.
- Changes in board/freescale/ls1088a/ls1088a.c to keep board_early_init_f funcations in case of SPL build.
- Changes in ls1088a_common.h & ls1088ardb.h to remove driver specific macros due to which static data was being compiled in case of SPL build.
- Enable CONFIG_SYS_DCACHE_OFF in case of SPL build as DCACHE is not being enabled in case of SPL image but was compiled in to add redundant code.
Signed-off-by: Sumit Garg sumit.garg@nxp.com
Dependent on ls1088 base SD boot target. Also dependent on ls1088 QPSI secure boot target.
board/freescale/ls1088a/Makefile | 4 +++- board/freescale/ls1088a/ls1088a.c | 14 ++++++++------ include/configs/ls1088a_common.h | 20 ++++++++++++++++++++ include/configs/ls1088ardb.h | 20 ++++++++++++++++++++ 4 files changed, 51 insertions(+), 7 deletions(-)
diff --git a/board/freescale/ls1088a/Makefile b/board/freescale/ls1088a/Makefile index bdcce9e..0e15031 100644 --- a/board/freescale/ls1088a/Makefile +++ b/board/freescale/ls1088a/Makefile @@ -5,6 +5,8 @@ #
obj-y += ls1088a.o +obj-y += ddr.o +ifndef CONFIG_SPL_BUILD obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o -obj-y += ddr.o +endif diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 1860f9c..1c28ab4 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -24,6 +24,13 @@
DECLARE_GLOBAL_DATA_PTR;
+int board_early_init_f(void) +{
- fsl_lsch3_early_init_f();
- return 0;
+}
+#if !defined(CONFIG_SPL_BUILD) unsigned long long get_qixis_addr(void) { unsigned long long addr; @@ -324,12 +331,6 @@ int board_init(void) return 0; }
-int board_early_init_f(void) -{
- fsl_lsch3_early_init_f();
- return 0;
-}
- void detail_board_ddr_info(void) { puts("\nDDR ");
@@ -404,3 +405,4 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } #endif +#endif /* defined(CONFIG_SPL_BUILD) */ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 63b69f8..fb4c852 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -7,6 +7,20 @@ #ifndef __LS1088_COMMON_H #define __LS1088_COMMON_H
+/* SPL build */ +#ifdef CONFIG_SPL_BUILD +#define SPL_NO_BOARDINFO +#define SPL_NO_QIXIS +#define SPL_NO_PCI +#define SPL_NO_ENV +#define SPL_NO_RTC +#define SPL_NO_USB +#define SPL_NO_SATA +#define SPL_NO_QSPI +#define SPL_NO_IFC +#define CONFIG_SYS_DCACHE_OFF
How much space can you save with data cache off? I prefer to leave the cache on. Cache is used if PPA is loaded in SPL stage for boost booting speed.
York
As we discussed earlier too, dcache was not enabled in SPL for our layerscape platforms. I have just removed redundant dcache specific code from SPL. I do save 2KB memory by removing redundant dcache specific code.
Also we do need more space (approx.. 6KB) on OCRAM for header. As currently we are only supporting single key in header (Max Size: 4KB) for validation. But actual use-case requires SRK table (8 keys) in header (Size: 10KB).
Total Available OCRAM for SPL image and header: 88KB
Current SPL image size with GCC 5.4.1 tool-chain: 84KB Current SPL header size with GCC 5.4.1 tool-chain: 4KB
Required SPL header size with GCC 5.4.1 tool-chain: 10KB
So we need to reduce SPL image size by 6KB more.
Sumit
On 08/29/2017 10:36 AM, Sumit Garg wrote:
-----Original Message----- From: York Sun Sent: Tuesday, August 29, 2017 9:25 PM To: Sumit Garg sumit.garg@nxp.com; u-boot@lists.denx.de Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Ruchika Gupta ruchika.gupta@nxp.com Subject: Re: [u-boot-release] [PATCH 2/3] armv8: ls1088a: SPL size reduction
On 08/29/2017 12:02 AM, Sumit Garg wrote:
Using changes in this patch we were able to reduce approx 8k size of u-boot-spl.bin image. Following is breif description of changes to reduce SPL size:
- Changes in board/freescale/ls1088a/Makefile to remove compilation of eth.c and cpld.c in case of SPL build.
- Changes in board/freescale/ls1088a/ls1088a.c to keep board_early_init_f funcations in case of SPL build.
- Changes in ls1088a_common.h & ls1088ardb.h to remove driver specific macros due to which static data was being compiled in case of SPL build.
- Enable CONFIG_SYS_DCACHE_OFF in case of SPL build as DCACHE is not being enabled in case of SPL image but was compiled in to add redundant code.
Signed-off-by: Sumit Garg sumit.garg@nxp.com
Dependent on ls1088 base SD boot target. Also dependent on ls1088 QPSI secure boot target.
board/freescale/ls1088a/Makefile | 4 +++- board/freescale/ls1088a/ls1088a.c | 14 ++++++++------ include/configs/ls1088a_common.h | 20 ++++++++++++++++++++ include/configs/ls1088ardb.h | 20 ++++++++++++++++++++ 4 files changed, 51 insertions(+), 7 deletions(-)
diff --git a/board/freescale/ls1088a/Makefile b/board/freescale/ls1088a/Makefile index bdcce9e..0e15031 100644 --- a/board/freescale/ls1088a/Makefile +++ b/board/freescale/ls1088a/Makefile @@ -5,6 +5,8 @@ #
obj-y += ls1088a.o +obj-y += ddr.o +ifndef CONFIG_SPL_BUILD obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o -obj-y += ddr.o +endif diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 1860f9c..1c28ab4 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -24,6 +24,13 @@
DECLARE_GLOBAL_DATA_PTR;
+int board_early_init_f(void) +{
- fsl_lsch3_early_init_f();
- return 0;
+}
+#if !defined(CONFIG_SPL_BUILD) unsigned long long get_qixis_addr(void) { unsigned long long addr; @@ -324,12 +331,6 @@ int board_init(void) return 0; }
-int board_early_init_f(void) -{
- fsl_lsch3_early_init_f();
- return 0;
-}
- void detail_board_ddr_info(void) { puts("\nDDR ");
@@ -404,3 +405,4 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } #endif +#endif /* defined(CONFIG_SPL_BUILD) */ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 63b69f8..fb4c852 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -7,6 +7,20 @@ #ifndef __LS1088_COMMON_H #define __LS1088_COMMON_H
+/* SPL build */ +#ifdef CONFIG_SPL_BUILD +#define SPL_NO_BOARDINFO +#define SPL_NO_QIXIS +#define SPL_NO_PCI +#define SPL_NO_ENV +#define SPL_NO_RTC +#define SPL_NO_USB +#define SPL_NO_SATA +#define SPL_NO_QSPI +#define SPL_NO_IFC +#define CONFIG_SYS_DCACHE_OFF
How much space can you save with data cache off? I prefer to leave the cache on. Cache is used if PPA is loaded in SPL stage for boost booting speed.
York
As we discussed earlier too, dcache was not enabled in SPL for our layerscape platforms.
That was a mistake when SPL targets were added. It should be enabled. As I said, if you load PPA in SPL, cache will be enabled for EL2. You didn't do it because booting performance is not a concern. If you enable falcon boot, this is required.
Also we do need more space (approx.. 6KB) on OCRAM for header. As currently we are only supporting single key in header (Max Size: 4KB) for validation. But actual use-case requires SRK table (8 keys) in header (Size: 10KB).
Total Available OCRAM for SPL image and header: 88KB
Current SPL image size with GCC 5.4.1 tool-chain: 84KB Current SPL header size with GCC 5.4.1 tool-chain: 4KB
Required SPL header size with GCC 5.4.1 tool-chain: 10KB
So we need to reduce SPL image size by 6KB more.
I understand the difficulty to fit secure boot into OCRAM. Please try GCC 6. It has better optimization.
York
< snip >
On 08/29/2017 12:02 AM, Sumit Garg wrote:
Using changes in this patch we were able to reduce approx 8k size of u-boot-spl.bin image. Following is breif description of changes to reduce SPL size:
- Changes in board/freescale/ls1088a/Makefile to remove compilation of eth.c and cpld.c in case of SPL build.
- Changes in board/freescale/ls1088a/ls1088a.c to keep board_early_init_f funcations in case of SPL build.
- Changes in ls1088a_common.h & ls1088ardb.h to remove driver specific macros due to which static data was being compiled in case of SPL build.
- Enable CONFIG_SYS_DCACHE_OFF in case of SPL build as DCACHE is not being enabled in case of SPL image but was compiled in to add redundant code.
Signed-off-by: Sumit Garg sumit.garg@nxp.com
Dependent on ls1088 base SD boot target. Also dependent on ls1088 QPSI secure boot target.
board/freescale/ls1088a/Makefile | 4 +++- board/freescale/ls1088a/ls1088a.c | 14 ++++++++------ include/configs/ls1088a_common.h | 20 ++++++++++++++++++++ include/configs/ls1088ardb.h | 20 ++++++++++++++++++++ 4 files changed, 51 insertions(+), 7 deletions(-)
diff --git a/board/freescale/ls1088a/Makefile b/board/freescale/ls1088a/Makefile index bdcce9e..0e15031 100644 --- a/board/freescale/ls1088a/Makefile +++ b/board/freescale/ls1088a/Makefile @@ -5,6 +5,8 @@ #
obj-y += ls1088a.o +obj-y += ddr.o +ifndef CONFIG_SPL_BUILD obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o -obj-y += ddr.o +endif diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 1860f9c..1c28ab4 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -24,6 +24,13 @@
DECLARE_GLOBAL_DATA_PTR;
+int board_early_init_f(void) +{
- fsl_lsch3_early_init_f();
- return 0;
+}
+#if !defined(CONFIG_SPL_BUILD) unsigned long long get_qixis_addr(void) { unsigned long long addr; @@ -324,12 +331,6 @@ int board_init(void) return 0; }
-int board_early_init_f(void) -{
- fsl_lsch3_early_init_f();
- return 0;
-}
- void detail_board_ddr_info(void) { puts("\nDDR ");
@@ -404,3 +405,4 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } #endif +#endif /* defined(CONFIG_SPL_BUILD) */ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 63b69f8..fb4c852 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -7,6 +7,20 @@ #ifndef __LS1088_COMMON_H #define __LS1088_COMMON_H
+/* SPL build */ +#ifdef CONFIG_SPL_BUILD +#define SPL_NO_BOARDINFO +#define SPL_NO_QIXIS +#define SPL_NO_PCI +#define SPL_NO_ENV +#define SPL_NO_RTC +#define SPL_NO_USB +#define SPL_NO_SATA +#define SPL_NO_QSPI +#define SPL_NO_IFC +#define CONFIG_SYS_DCACHE_OFF
How much space can you save with data cache off? I prefer to leave the cache on. Cache is used if PPA is loaded in SPL stage for boost booting
speed.
York
As we discussed earlier too, dcache was not enabled in SPL for our layerscape
platforms.
That was a mistake when SPL targets were added. It should be enabled. As I said, if you load PPA in SPL, cache will be enabled for EL2. You didn't do it because booting performance is not a concern. If you enable falcon boot, this is required.
Ok. BTW, do you think latest PPA which claims whole of OCRAM could work with SPL. I saw crashes in SPL on ls1043ardb with latest PPA enabled in SPL upstream u-boot.
As per my understanding, shouldn't we enable cache as part of main u-boot image running in EL2? Also in case of SD, it uses DMA to copy main u-boot image or kernel in case of falcon boot to DDR. I am not sure how much booting performance gain can we get by enabling dcache in SPL.
Also we do need more space (approx.. 6KB) on OCRAM for header. As currently we are only supporting single key in header (Max Size: 4KB) for validation. But actual use-case requires SRK table (8 keys) in header (Size:
10KB).
Total Available OCRAM for SPL image and header: 88KB
Current SPL image size with GCC 5.4.1 tool-chain: 84KB Current SPL header size with GCC 5.4.1 tool-chain: 4KB
Required SPL header size with GCC 5.4.1 tool-chain: 10KB
So we need to reduce SPL image size by 6KB more.
I understand the difficulty to fit secure boot into OCRAM. Please try GCC 6. It has better optimization.
York
Sure I will use GCC 6 for upstream. But for LSDK, we have to stick with GCCC 5.4.1 for now.
Sumit
On 08/30/2017 01:53 AM, Sumit Garg wrote:
< snip >
On 08/29/2017 12:02 AM, Sumit Garg wrote:
Using changes in this patch we were able to reduce approx 8k size of u-boot-spl.bin image. Following is breif description of changes to reduce SPL size:
- Changes in board/freescale/ls1088a/Makefile to remove compilation of eth.c and cpld.c in case of SPL build.
- Changes in board/freescale/ls1088a/ls1088a.c to keep board_early_init_f funcations in case of SPL build.
- Changes in ls1088a_common.h & ls1088ardb.h to remove driver specific macros due to which static data was being compiled in case of SPL build.
- Enable CONFIG_SYS_DCACHE_OFF in case of SPL build as DCACHE is not being enabled in case of SPL image but was compiled in to add redundant code.
Signed-off-by: Sumit Garg sumit.garg@nxp.com
Dependent on ls1088 base SD boot target. Also dependent on ls1088 QPSI secure boot target.
board/freescale/ls1088a/Makefile | 4 +++- board/freescale/ls1088a/ls1088a.c | 14 ++++++++------ include/configs/ls1088a_common.h | 20 ++++++++++++++++++++ include/configs/ls1088ardb.h | 20 ++++++++++++++++++++ 4 files changed, 51 insertions(+), 7 deletions(-)
diff --git a/board/freescale/ls1088a/Makefile b/board/freescale/ls1088a/Makefile index bdcce9e..0e15031 100644 --- a/board/freescale/ls1088a/Makefile +++ b/board/freescale/ls1088a/Makefile @@ -5,6 +5,8 @@ #
obj-y += ls1088a.o +obj-y += ddr.o +ifndef CONFIG_SPL_BUILD obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o -obj-y += ddr.o +endif diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 1860f9c..1c28ab4 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -24,6 +24,13 @@
DECLARE_GLOBAL_DATA_PTR;
+int board_early_init_f(void) +{
- fsl_lsch3_early_init_f();
- return 0;
+}
+#if !defined(CONFIG_SPL_BUILD) unsigned long long get_qixis_addr(void) { unsigned long long addr; @@ -324,12 +331,6 @@ int board_init(void) return 0; }
-int board_early_init_f(void) -{
- fsl_lsch3_early_init_f();
- return 0;
-}
- void detail_board_ddr_info(void) { puts("\nDDR ");
@@ -404,3 +405,4 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } #endif +#endif /* defined(CONFIG_SPL_BUILD) */ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 63b69f8..fb4c852 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -7,6 +7,20 @@ #ifndef __LS1088_COMMON_H #define __LS1088_COMMON_H
+/* SPL build */ +#ifdef CONFIG_SPL_BUILD +#define SPL_NO_BOARDINFO +#define SPL_NO_QIXIS +#define SPL_NO_PCI +#define SPL_NO_ENV +#define SPL_NO_RTC +#define SPL_NO_USB +#define SPL_NO_SATA +#define SPL_NO_QSPI +#define SPL_NO_IFC +#define CONFIG_SYS_DCACHE_OFF
How much space can you save with data cache off? I prefer to leave the cache on. Cache is used if PPA is loaded in SPL stage for boost booting
speed.
York
As we discussed earlier too, dcache was not enabled in SPL for our layerscape
platforms.
That was a mistake when SPL targets were added. It should be enabled. As I said, if you load PPA in SPL, cache will be enabled for EL2. You didn't do it because booting performance is not a concern. If you enable falcon boot, this is required.
Ok. BTW, do you think latest PPA which claims whole of OCRAM could work with SPL. I saw crashes in SPL on ls1043ardb with latest PPA enabled in SPL upstream u-boot.
Sumit,
PPA has been fixed to not claim OCRAM. Please rework your patch.
York
-----Original Message----- From: York Sun Sent: Friday, January 05, 2018 9:26 PM To: Sumit Garg sumit.garg@nxp.com; u-boot@lists.denx.de Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Ruchika Gupta ruchika.gupta@nxp.com Subject: Re: [u-boot-release] [PATCH 2/3] armv8: ls1088a: SPL size reduction
On 08/30/2017 01:53 AM, Sumit Garg wrote:
< snip >
On 08/29/2017 12:02 AM, Sumit Garg wrote:
Using changes in this patch we were able to reduce approx 8k size of u-boot-spl.bin image. Following is breif description of changes to reduce SPL size:
- Changes in board/freescale/ls1088a/Makefile to remove compilation of eth.c and cpld.c in case of SPL build.
- Changes in board/freescale/ls1088a/ls1088a.c to keep board_early_init_f funcations in case of SPL build.
- Changes in ls1088a_common.h & ls1088ardb.h to remove driver specific macros due to which static data was being compiled in case of SPL build.
- Enable CONFIG_SYS_DCACHE_OFF in case of SPL build as DCACHE is not being enabled in case of SPL image but was compiled in to add redundant code.
Signed-off-by: Sumit Garg sumit.garg@nxp.com
Dependent on ls1088 base SD boot target. Also dependent on ls1088 QPSI secure boot target.
board/freescale/ls1088a/Makefile | 4 +++- board/freescale/ls1088a/ls1088a.c | 14 ++++++++------ include/configs/ls1088a_common.h | 20 ++++++++++++++++++++ include/configs/ls1088ardb.h | 20 ++++++++++++++++++++ 4 files changed, 51 insertions(+), 7 deletions(-)
diff --git a/board/freescale/ls1088a/Makefile b/board/freescale/ls1088a/Makefile index bdcce9e..0e15031 100644 --- a/board/freescale/ls1088a/Makefile +++ b/board/freescale/ls1088a/Makefile @@ -5,6 +5,8 @@ #
obj-y += ls1088a.o +obj-y += ddr.o +ifndef CONFIG_SPL_BUILD obj-$(CONFIG_TARGET_LS1088ARDB) += eth_ls1088ardb.o obj-$(CONFIG_TARGET_LS1088AQDS) += eth_ls1088aqds.o -obj-y += ddr.o +endif diff --git a/board/freescale/ls1088a/ls1088a.c b/board/freescale/ls1088a/ls1088a.c index 1860f9c..1c28ab4 100644 --- a/board/freescale/ls1088a/ls1088a.c +++ b/board/freescale/ls1088a/ls1088a.c @@ -24,6 +24,13 @@
DECLARE_GLOBAL_DATA_PTR;
+int board_early_init_f(void) +{
- fsl_lsch3_early_init_f();
- return 0;
+}
+#if !defined(CONFIG_SPL_BUILD) unsigned long long get_qixis_addr(void) { unsigned long long addr; @@ -324,12 +331,6 @@ int board_init(void) return 0; }
-int board_early_init_f(void) -{
- fsl_lsch3_early_init_f();
- return 0;
-}
- void detail_board_ddr_info(void) { puts("\nDDR ");
@@ -404,3 +405,4 @@ int ft_board_setup(void *blob, bd_t *bd) return 0; } #endif +#endif /* defined(CONFIG_SPL_BUILD) */ diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index 63b69f8..fb4c852 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -7,6 +7,20 @@ #ifndef __LS1088_COMMON_H #define __LS1088_COMMON_H
+/* SPL build */ +#ifdef CONFIG_SPL_BUILD +#define SPL_NO_BOARDINFO +#define SPL_NO_QIXIS +#define SPL_NO_PCI +#define SPL_NO_ENV +#define SPL_NO_RTC +#define SPL_NO_USB +#define SPL_NO_SATA +#define SPL_NO_QSPI +#define SPL_NO_IFC +#define CONFIG_SYS_DCACHE_OFF
How much space can you save with data cache off? I prefer to leave the cache on. Cache is used if PPA is loaded in SPL stage for boost booting
speed.
York
As we discussed earlier too, dcache was not enabled in SPL for our layerscape
platforms.
That was a mistake when SPL targets were added. It should be enabled. As I said, if you load PPA in SPL, cache will be enabled for EL2. You didn't do it because booting performance is not a concern. If you enable falcon boot, this is required.
Ok. BTW, do you think latest PPA which claims whole of OCRAM could work
with SPL.
I saw crashes in SPL on ls1043ardb with latest PPA enabled in SPL upstream u-
boot.
Sumit,
PPA has been fixed to not claim OCRAM. Please rework your patch.
York
York,
I have just sent reworked patches without removing dcache cache code. It's been working only with toolchain above GCC 6 that reduces SPL size.
https://patchwork.ozlabs.org/patch/856095/ https://patchwork.ozlabs.org/patch/856097/ https://patchwork.ozlabs.org/patch/856096/
Sumit
On 01/05/2018 08:07 AM, Sumit Garg wrote:
<snip>
Sumit,
PPA has been fixed to not claim OCRAM. Please rework your patch.
York
York,
I have just sent reworked patches without removing dcache cache code. It's been working only with toolchain above GCC 6 that reduces SPL size.
Thanks. What do you mean "working only with toolchain above GCC 6"? Do you mean the size would be too large using older toolchain?
York
-----Original Message----- From: York Sun Sent: Friday, January 05, 2018 9:40 PM To: Sumit Garg sumit.garg@nxp.com; u-boot@lists.denx.de Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Ruchika Gupta ruchika.gupta@nxp.com Subject: Re: [u-boot-release] [PATCH 2/3] armv8: ls1088a: SPL size reduction
On 01/05/2018 08:07 AM, Sumit Garg wrote:
<snip>
Sumit,
PPA has been fixed to not claim OCRAM. Please rework your patch.
York
York,
I have just sent reworked patches without removing dcache cache code. It's been working only with toolchain above GCC 6 that reduces SPL size.
Thanks. What do you mean "working only with toolchain above GCC 6"? Do you mean the size would be too large using older toolchain?
York
Yes for LSDK, tool-chain being used is GCC 5.4.1. Following is analysis with LSDK too-chain:
SPL size for Secure boot image without dcache code: 83K Available max OCRAM memory size for SPL image: 84K SPL size for Secure boot image with dcache code: 85K
So for LSDK we have remove dcache code for Secure boot to work with current SPL size reduction.
-Sumit
On 01/05/2018 08:22 AM, Sumit Garg wrote:
-----Original Message----- From: York Sun Sent: Friday, January 05, 2018 9:40 PM To: Sumit Garg sumit.garg@nxp.com; u-boot@lists.denx.de Cc: Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Ruchika Gupta ruchika.gupta@nxp.com Subject: Re: [u-boot-release] [PATCH 2/3] armv8: ls1088a: SPL size reduction
On 01/05/2018 08:07 AM, Sumit Garg wrote:
<snip>
Sumit,
PPA has been fixed to not claim OCRAM. Please rework your patch.
York
York,
I have just sent reworked patches without removing dcache cache code. It's been working only with toolchain above GCC 6 that reduces SPL size.
Thanks. What do you mean "working only with toolchain above GCC 6"? Do you mean the size would be too large using older toolchain?
York
Yes for LSDK, tool-chain being used is GCC 5.4.1. Following is analysis with LSDK too-chain:
SPL size for Secure boot image without dcache code: 83K Available max OCRAM memory size for SPL image: 84K SPL size for Secure boot image with dcache code: 85K
So for LSDK we have remove dcache code for Secure boot to work with current SPL size reduction.
If you are out of space for LSDK, go ahead to remove the dcache code. For upstream U-Boot, I want to keep those code for falcon boot. We are going with GCC 6 anyway.
York
Signed-off-by: Udit Agarwal udit.agarwal@nxp.com Signed-off-by: Sumit Garg sumit.garg@nxp.com ---
Dependent on ls1088 base SD boot target. Also dependent on ls1088 QPSI secure boot target.
arch/arm/include/asm/fsl_secure_boot.h | 16 ++++----- board/freescale/ls1088a/MAINTAINERS | 5 +++ .../ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig | 39 ++++++++++++++++++++++ include/configs/ls1088a_common.h | 15 ++++++++- 4 files changed, 66 insertions(+), 9 deletions(-) create mode 100644 configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig
diff --git a/arch/arm/include/asm/fsl_secure_boot.h b/arch/arm/include/asm/fsl_secure_boot.h index 5ebe0cf..aa48024 100644 --- a/arch/arm/include/asm/fsl_secure_boot.h +++ b/arch/arm/include/asm/fsl_secure_boot.h @@ -26,6 +26,14 @@
#define CONFIG_KEY_REVOCATION
+#if defined(CONFIG_FSL_LAYERSCAPE) +/* + * For fsl layerscape based platforms, ESBC image Address in Header + * is 64 bit. + */ +#define CONFIG_ESBC_ADDR_64BIT +#endif + #ifndef CONFIG_SPL_BUILD #ifndef CONFIG_SYS_RAMBOOT /* The key used for verification of next level images @@ -42,14 +50,6 @@
#endif
-#if defined(CONFIG_FSL_LAYERSCAPE) -/* - * For fsl layerscape based platforms, ESBC image Address in Header - * is 64 bit. - */ -#define CONFIG_ESBC_ADDR_64BIT -#endif - #ifdef CONFIG_ARCH_LS2080A #define CONFIG_EXTRA_ENV \ "setenv fdt_high 0xa0000000;" \ diff --git a/board/freescale/ls1088a/MAINTAINERS b/board/freescale/ls1088a/MAINTAINERS index b3d5c38..de8a770 100644 --- a/board/freescale/ls1088a/MAINTAINERS +++ b/board/freescale/ls1088a/MAINTAINERS @@ -15,3 +15,8 @@ F: board/freescale/ls1088a/ F: include/configs/ls1088aqds.h F: configs/ls1088aqds_qspi_defconfig F: configs/ls1088aqds_sdcard_qspi_defconfig + +LS1088A_SECURE_BOOT BOARD +M: Sumit Garg sumit.garg@nxp.com +S: Maintained +F: configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig diff --git a/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig new file mode 100644 index 0000000..746637d --- /dev/null +++ b/configs/ls1088ardb_sdcard_qspi_SECURE_BOOT_defconfig @@ -0,0 +1,39 @@ +CONFIG_ARM=y +CONFIG_TARGET_LS1088ARDB=y +# CONFIG_SYS_MALLOC_F is not set +CONFIG_DM_SPI=y +CONFIG_DM_SPI_FLASH=y +CONFIG_DEFAULT_DEVICE_TREE="fsl-ls1088a-rdb" +CONFIG_FIT=y +CONFIG_FIT_VERBOSE=y +CONFIG_OF_BOARD_SETUP=y +CONFIG_SYS_EXTRA_OPTIONS="SD_BOOT_QSPI" +CONFIG_SECURE_BOOT=y +CONFIG_SD_BOOT=y +CONFIG_SPL=y +CONFIG_HUSH_PARSER=y +CONFIG_CMD_MMC=y +CONFIG_CMD_SF=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_SETEXPR is not set +CONFIG_CMD_DHCP=y +CONFIG_CMD_PING=y +CONFIG_OF_CONTROL=y +CONFIG_NET_RANDOM_ETHADDR=y +CONFIG_DM=y +CONFIG_SPL_DM=y +CONFIG_SPI_FLASH=y +CONFIG_NETDEVICES=y +CONFIG_E1000=y +CONFIG_SYS_NS16550=y +CONFIG_FSL_DSPI=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_USE_SECTOR=y +CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR=0x8b0 +CONFIG_FSL_LS_PPA=y +CONFIG_SPL_BUILD=y +CONFIG_PARTITIONS=y +CONFIG_RSA=y +CONFIG_SPL_RSA=y +CONFIG_SPL_CRYPTO_SUPPORT=y +CONFIG_SPL_HASH_SUPPORT=y +# CONFIG_DISPLAY_BOARDINFO is not set diff --git a/include/configs/ls1088a_common.h b/include/configs/ls1088a_common.h index fb4c852..38d4643 100644 --- a/include/configs/ls1088a_common.h +++ b/include/configs/ls1088a_common.h @@ -248,7 +248,20 @@ unsigned long long get_qixis_addr(void);
#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00100000 #define CONFIG_SYS_SPL_MALLOC_START 0x80200000 -#define CONFIG_SYS_MONITOR_LEN (512 * 1024) + +#ifdef CONFIG_SECURE_BOOT +#define CONFIG_U_BOOT_HDR_SIZE (16 << 10) +/* + * HDR would be appended at end of image and copied to DDR along + * with U-Boot image. Here u-boot max. size is 512K. So if binary + * size increases then increase this size in case of secure boot as + * it uses raw u-boot image instead of fit image. + */ +#define CONFIG_SYS_MONITOR_LEN (0x100000 + CONFIG_U_BOOT_HDR_SIZE) +#else +#define CONFIG_SYS_MONITOR_LEN 0x100000 +#endif /* ifdef CONFIG_SECURE_BOOT */ + #endif #define CONFIG_SYS_BOOTM_LEN (64 << 20) /* Increase max gunzip size */
On 08/29/2017 12:01 AM, Sumit Garg wrote:
Using changes in this patch we were able to reduce approx 4k size of u-boot-spl.bin image. Following is breif description of changes to reduce SPL size:
- Compile-off mp.c and libfdt.c in case of SPL build.
- Keep MMU and DCACHE specific variable and functions under CONFIG_SYS_DCACHE_OFF macro.
- Compile-off IFC specific funtion call "init_early_memctl_regs" in case of SPL build.
Signed-off-by: Sumit Garg sumit.garg@nxp.com
Dependent on ls1088 base SD boot target. Also dependent on ls1088 QPSI secure boot target.
I don't agree D-cache should be off for SPL boot. Please find other way to reduce SPL image size.
York
-----Original Message----- From: York Sun Sent: Friday, September 15, 2017 2:08 AM To: Sumit Garg sumit.garg@nxp.com; u-boot@lists.denx.de Cc: Ruchika Gupta ruchika.gupta@nxp.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCH 1/3] armv8: fsl-layerscape: SPL size reduction
On 08/29/2017 12:01 AM, Sumit Garg wrote:
Using changes in this patch we were able to reduce approx 4k size of u-boot-spl.bin image. Following is breif description of changes to reduce SPL size:
- Compile-off mp.c and libfdt.c in case of SPL build.
- Keep MMU and DCACHE specific variable and functions under CONFIG_SYS_DCACHE_OFF macro.
- Compile-off IFC specific funtion call "init_early_memctl_regs" in case of SPL build.
Signed-off-by: Sumit Garg sumit.garg@nxp.com
Dependent on ls1088 base SD boot target. Also dependent on ls1088 QPSI secure boot target.
I don't agree D-cache should be off for SPL boot. Please find other way to reduce SPL image size.
York
Sure, let me use GCC 6.2 to reduce SPL image size in upstream rather than compiling-off D-cache code.
But I still don't see ls1088ardb sd boot support in upstream.
Ashish,
By when can I expect ls1088ardb sd boot support in upstream?
Sumit
On 10/03/2017 03:51 AM, Sumit Garg wrote:
-----Original Message----- From: York Sun Sent: Friday, September 15, 2017 2:08 AM To: Sumit Garg sumit.garg@nxp.com; u-boot@lists.denx.de Cc: Ruchika Gupta ruchika.gupta@nxp.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCH 1/3] armv8: fsl-layerscape: SPL size reduction
On 08/29/2017 12:01 AM, Sumit Garg wrote:
Using changes in this patch we were able to reduce approx 4k size of u-boot-spl.bin image. Following is breif description of changes to reduce SPL size:
- Compile-off mp.c and libfdt.c in case of SPL build.
- Keep MMU and DCACHE specific variable and functions under CONFIG_SYS_DCACHE_OFF macro.
- Compile-off IFC specific funtion call "init_early_memctl_regs" in case of SPL build.
Signed-off-by: Sumit Garg sumit.garg@nxp.com
Dependent on ls1088 base SD boot target. Also dependent on ls1088 QPSI secure boot target.
I don't agree D-cache should be off for SPL boot. Please find other way to reduce SPL image size.
York
Sure, let me use GCC 6.2 to reduce SPL image size in upstream rather than compiling-off D-cache code.
But I still don't see ls1088ardb sd boot support in upstream.
Ashish,
By when can I expect ls1088ardb sd boot support in upstream?
Sumit,
SD boot is not completed. I don't see RCW in the final image. Pending Ashish's investigation.
York
-----Original Message----- From: York Sun Sent: Thursday, October 05, 2017 12:12 AM To: Sumit Garg sumit.garg@nxp.com; u-boot@lists.denx.de Cc: Ruchika Gupta ruchika.gupta@nxp.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Ashish Kumar ashish.kumar@nxp.com Subject: Re: [PATCH 1/3] armv8: fsl-layerscape: SPL size reduction
On 10/03/2017 03:51 AM, Sumit Garg wrote:
-----Original Message----- From: York Sun Sent: Friday, September 15, 2017 2:08 AM To: Sumit Garg sumit.garg@nxp.com; u-boot@lists.denx.de Cc: Ruchika Gupta ruchika.gupta@nxp.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com Subject: Re: [PATCH 1/3] armv8: fsl-layerscape: SPL size reduction
On 08/29/2017 12:01 AM, Sumit Garg wrote:
Using changes in this patch we were able to reduce approx 4k size of u-boot-spl.bin image. Following is breif description of changes to reduce SPL size:
- Compile-off mp.c and libfdt.c in case of SPL build.
- Keep MMU and DCACHE specific variable and functions under CONFIG_SYS_DCACHE_OFF macro.
- Compile-off IFC specific funtion call "init_early_memctl_regs" in case of SPL build.
Signed-off-by: Sumit Garg sumit.garg@nxp.com
Dependent on ls1088 base SD boot target. Also dependent on ls1088 QPSI secure boot target.
I don't agree D-cache should be off for SPL boot. Please find other way to reduce SPL image size.
York
Sure, let me use GCC 6.2 to reduce SPL image size in upstream rather than compiling-off D-cache code.
But I still don't see ls1088ardb sd boot support in upstream.
Ashish,
By when can I expect ls1088ardb sd boot support in upstream?
Sumit,
SD boot is not completed. I don't see RCW in the final image. Pending Ashish's investigation.
York
I will wait for SD boot patches to be accepted in upstream. As reducing SPL size for ls1088ardb in upstream does only makes sense once we have base platform support merged in upstream.
Sumit
-----Original Message----- From: York Sun Sent: Thursday, November 30, 2017 12:07 AM To: Sumit Garg sumit.garg@nxp.com; u-boot@lists.denx.de Cc: Ruchika Gupta ruchika.gupta@nxp.com; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; Ashish Kumar ashish.kumar@nxp.com Subject: Re: [PATCH 1/3] armv8: fsl-layerscape: SPL size reduction
On 10/05/2017 12:55 AM, Sumit Garg wrote:
I will wait for SD boot patches to be accepted in upstream. As reducing SPL size for ls1088ardb in upstream does only makes sense once we have base platform support merged in upstream.
Please rework this patch set.
York
Sure, I will pick it up. Actually I am currently occupied in some other work.
Sumit
participants (2)
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Sumit Garg -
York Sun