[PATCH 01/14] firmware: scmi: fix description of an API function
Correct inline comment describing API function devm_scmi_process_msg().
Signed-off-by: Etienne Carriere etienne.carriere@linaro.org --- include/scmi_agent.h | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/scmi_agent.h b/include/scmi_agent.h index f1be9ff209..ed40c7360a 100644 --- a/include/scmi_agent.h +++ b/include/scmi_agent.h @@ -45,9 +45,9 @@ struct scmi_msg { }
/** - * scmi_send_and_process_msg() - send and process a SCMI message + * devm_scmi_process_msg() - Send and process an SCMI message * - * Send a message to a SCMI server through a target SCMI agent device. + * Send a message to an SCMI server through a target SCMI agent device. * Caller sets scmi_msg::out_msg_sz to the output message buffer size. * On return, scmi_msg::out_msg_sz stores the response payload size. *
Correct scmi mailbox probe function that can't free the scmi channel instance since its auto-allocated by the device model framework.
Signed-off-by: Etienne Carriere etienne.carriere@linaro.org --- drivers/firmware/scmi/mailbox_agent.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-)
diff --git a/drivers/firmware/scmi/mailbox_agent.c b/drivers/firmware/scmi/mailbox_agent.c index ea35e7e09e..eb841d692b 100644 --- a/drivers/firmware/scmi/mailbox_agent.c +++ b/drivers/firmware/scmi/mailbox_agent.c @@ -72,17 +72,13 @@ int scmi_mbox_probe(struct udevice *dev) ret = mbox_get_by_index(dev, 0, &chan->mbox); if (ret) { dev_err(dev, "Failed to find mailbox: %d\n", ret); - goto out; + return ret; }
ret = scmi_dt_get_smt_buffer(dev, &chan->smt); if (ret) dev_err(dev, "Failed to get shm resources: %d\n", ret);
-out: - if (ret) - devm_kfree(dev, chan); - return ret; }
Change SCMI mailbox transport drivers to use platform data rather than private data for channel reference since it only stores platform data retrieved from the DT. Consequently the probe handler is replaced with a of_to_plat handler.
Signed-off-by: Etienne Carriere etienne.carriere@linaro.org --- drivers/firmware/scmi/mailbox_agent.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/firmware/scmi/mailbox_agent.c b/drivers/firmware/scmi/mailbox_agent.c index eb841d692b..8e4af0c8fa 100644 --- a/drivers/firmware/scmi/mailbox_agent.c +++ b/drivers/firmware/scmi/mailbox_agent.c @@ -33,7 +33,7 @@ struct scmi_mbox_channel {
static int scmi_mbox_process_msg(struct udevice *dev, struct scmi_msg *msg) { - struct scmi_mbox_channel *chan = dev_get_priv(dev); + struct scmi_mbox_channel *chan = dev_get_plat(dev); int ret;
ret = scmi_write_msg_to_smt(dev, &chan->smt, msg); @@ -62,9 +62,9 @@ out: return ret; }
-int scmi_mbox_probe(struct udevice *dev) +int scmi_mbox_of_to_plat(struct udevice *dev) { - struct scmi_mbox_channel *chan = dev_get_priv(dev); + struct scmi_mbox_channel *chan = dev_get_plat(dev); int ret;
chan->timeout_us = TIMEOUT_US_10MS; @@ -95,7 +95,7 @@ U_BOOT_DRIVER(scmi_mbox) = { .name = "scmi-over-mailbox", .id = UCLASS_SCMI_AGENT, .of_match = scmi_mbox_ids, - .priv_auto = sizeof(struct scmi_mbox_channel), - .probe = scmi_mbox_probe, + .plat_auto = sizeof(struct scmi_mbox_channel), + .of_to_plat = scmi_mbox_of_to_plat, .ops = &scmi_mbox_ops, };
Change SCMI smccc transport drivers to use platform data rather than private data for channel reference since it only stores platform data retrieved from the DT. Consequently the probe handler is replaced with a of_to_plat handler.
Signed-off-by: Etienne Carriere etienne.carriere@linaro.org --- drivers/firmware/scmi/smccc_agent.c | 10 +++++----- 1 file changed, 5 insertions(+), 5 deletions(-)
diff --git a/drivers/firmware/scmi/smccc_agent.c b/drivers/firmware/scmi/smccc_agent.c index f185891e8f..f0477b91dc 100644 --- a/drivers/firmware/scmi/smccc_agent.c +++ b/drivers/firmware/scmi/smccc_agent.c @@ -32,7 +32,7 @@ struct scmi_smccc_channel {
static int scmi_smccc_process_msg(struct udevice *dev, struct scmi_msg *msg) { - struct scmi_smccc_channel *chan = dev_get_priv(dev); + struct scmi_smccc_channel *chan = dev_get_plat(dev); struct arm_smccc_res res; int ret;
@@ -51,9 +51,9 @@ static int scmi_smccc_process_msg(struct udevice *dev, struct scmi_msg *msg) return ret; }
-static int scmi_smccc_probe(struct udevice *dev) +static int scmi_smccc_of_to_plat(struct udevice *dev) { - struct scmi_smccc_channel *chan = dev_get_priv(dev); + struct scmi_smccc_channel *chan = dev_get_plat(dev); u32 func_id; int ret;
@@ -86,7 +86,7 @@ U_BOOT_DRIVER(scmi_smccc) = { .name = "scmi-over-smccc", .id = UCLASS_SCMI_AGENT, .of_match = scmi_smccc_ids, - .priv_auto = sizeof(struct scmi_smccc_channel), - .probe = scmi_smccc_probe, + .plat_auto = sizeof(struct scmi_smccc_channel), + .of_to_plat = scmi_smccc_of_to_plat, .ops = &scmi_smccc_ops, };
Minor simplification in scmi_smccc_probe() exit sequence.
Signed-off-by: Etienne Carriere etienne.carriere@linaro.org --- drivers/firmware/scmi/smccc_agent.c | 6 ++---- 1 file changed, 2 insertions(+), 4 deletions(-)
diff --git a/drivers/firmware/scmi/smccc_agent.c b/drivers/firmware/scmi/smccc_agent.c index f0477b91dc..5e166ca93e 100644 --- a/drivers/firmware/scmi/smccc_agent.c +++ b/drivers/firmware/scmi/smccc_agent.c @@ -65,12 +65,10 @@ static int scmi_smccc_of_to_plat(struct udevice *dev) chan->func_id = func_id;
ret = scmi_dt_get_smt_buffer(dev, &chan->smt); - if (ret) { + if (ret) dev_err(dev, "Failed to get smt resources: %d\n", ret); - return ret; - }
- return 0; + return ret; }
static const struct udevice_id scmi_smccc_ids[] = {
Increase malloc heap needed before relocation to invoke OP-TEE and eventually print some early debug traces.
Change-Id: I23837c8c879ce5a080b23cb3ac5033d5ba73fb0d Signed-off-by: Etienne Carriere etienne.carriere@linaro.org --- configs/stm32mp15_trusted_defconfig | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index b4ed090e3f..48efdec657 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_STM32MP=y CONFIG_TFABOOT=y -CONFIG_SYS_MALLOC_F_LEN=0x3000 +CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_SYS_MEMTEST_START=0xc0000000 CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_ENV_OFFSET=0x280000
Enable CONFIG_DM_REGULATOR_SCMI for stm32mp15_trusted_defconfig to access voltage regulators exposed by SCMI server.
Signed-off-by: Etienne Carriere etienne.carriere@linaro.org --- configs/stm32mp15_trusted_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index 48efdec657..dc1f48c518 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -116,6 +116,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_DM_REGULATOR_GPIO=y CONFIG_DM_REGULATOR_STM32_VREFBUF=y CONFIG_DM_REGULATOR_STPMIC1=y +CONFIG_DM_REGULATOR_SCMI=y CONFIG_REMOTEPROC_STM32_COPRO=y CONFIG_RESET_SCMI=y CONFIG_DM_RNG=y
Define stm32mp15 voltage domain DT bindings IDs.
Signed-off-by: Etienne Carriere etienne.carriere@linaro.org --- .../regulator/st,stm32mp15-regulator.h | 29 +++++++++++++++++++ 1 file changed, 29 insertions(+) create mode 100644 include/dt-bindings/regulator/st,stm32mp15-regulator.h
diff --git a/include/dt-bindings/regulator/st,stm32mp15-regulator.h b/include/dt-bindings/regulator/st,stm32mp15-regulator.h new file mode 100644 index 0000000000..96eb578c00 --- /dev/null +++ b/include/dt-bindings/regulator/st,stm32mp15-regulator.h @@ -0,0 +1,29 @@ +/* SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) */ +/* + * Copyright (C) 2020, STMicroelectronics - All Rights Reserved + */ + +#ifndef __DT_BINDINGS_REGULATOR_ST_STM32MP15_REGULATOR_H +#define __DT_BINDINGS_REGULATOR_ST_STM32MP15_REGULATOR_H + +/* SCMI voltage domain identifiers */ + +#define VOLTD_SCMI0_REG11 0 +#define VOLTD_SCMI0_REG18 1 +#define VOLTD_SCMI0_USB33 2 +#define VOLTD_SCMI0_STPMIC1_BUCK1 3 +#define VOLTD_SCMI0_STPMIC1_BUCK2 4 +#define VOLTD_SCMI0_STPMIC1_BUCK3 5 +#define VOLTD_SCMI0_STPMIC1_BUCK4 6 +#define VOLTD_SCMI0_STPMIC1_LDO1 7 +#define VOLTD_SCMI0_STPMIC1_LDO2 8 +#define VOLTD_SCMI0_STPMIC1_LDO3 9 +#define VOLTD_SCMI0_STPMIC1_LDO4 10 +#define VOLTD_SCMI0_STPMIC1_LDO5 11 +#define VOLTD_SCMI0_STPMIC1_LDO6 12 +#define VOLTD_SCMI0_STPMIC1_VREFDDR 13 +#define VOLTD_SCMI0_STPMIC1_BOOST 14 +#define VOLTD_SCMI0_STPMIC1_PWR_SW1 15 +#define VOLTD_SCMI0_STPMIC1_PWR_SW2 16 + +#endif /*__DT_BINDINGS_REGULATOR_ST_STM32MP15_REGULATOR_H */
Enable OP-TEE resources and SMCI over OP-TEE on STM32MP15xx-EV1/DK2 boards.
Signed-off-by: Etienne Carriere etienne.carriere@linaro.org --- arch/arm/dts/stm32mp15-u-boot.dtsi | 81 +++++------ arch/arm/dts/stm32mp151.dtsi | 145 ++++++++++++-------- arch/arm/dts/stm32mp153.dtsi | 6 +- arch/arm/dts/stm32mp157.dtsi | 2 +- arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi | 114 +-------------- arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi | 40 ++++++ arch/arm/dts/stm32mp157c-dk2.dts | 9 ++ arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi | 99 +------------ arch/arm/dts/stm32mp157c-ed1.dts | 5 + arch/arm/dts/stm32mp157c-odyssey.dts | 14 ++ arch/arm/dts/stm32mp15xc.dtsi | 4 +- include/dt-bindings/clock/stm32mp1-clks.h | 27 ++++ include/dt-bindings/reset/stm32mp1-resets.h | 14 ++ 13 files changed, 248 insertions(+), 312 deletions(-)
diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi index 43a7909978..6fd204c635 100644 --- a/arch/arm/dts/stm32mp15-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi @@ -21,23 +21,11 @@ pinctrl1 = &pinctrl_z; };
- clocks { - u-boot,dm-pre-reloc; - }; - /* need PSCI for sysreset during board_f */ psci { u-boot,dm-pre-proper; };
- reboot { - u-boot,dm-pre-reloc; - compatible = "syscon-reboot"; - regmap = <&rcc>; - offset = <0x404>; - mask = <0x1>; - }; - soc { u-boot,dm-pre-reloc;
@@ -72,36 +60,6 @@ u-boot,dm-pre-reloc; };
-&clk_csi { - u-boot,dm-pre-reloc; -}; - -&clk_hsi { - u-boot,dm-pre-reloc; -}; - -&clk_hse { - u-boot,dm-pre-reloc; -}; - -&clk_lsi { - u-boot,dm-pre-reloc; -}; - -&clk_lse { - u-boot,dm-pre-reloc; -}; - -&cpu0_opp_table { - u-boot,dm-spl; - opp-650000000 { - u-boot,dm-spl; - }; - opp-800000000 { - u-boot,dm-spl; - }; -}; - &gpioa { u-boot,dm-pre-reloc; }; @@ -161,8 +119,8 @@
/* temp = waiting kernel update */ &m4_rproc { - resets = <&rcc MCU_R>, - <&rcc MCU_HOLD_BOOT_R>; + resets = <&scmi0_reset RST_SCMI0_MCU>, + <&scmi0_reset RST_SCMI0_MCU_HOLD_BOOT>; reset-names = "mcu_rst", "hold_boot"; };
@@ -174,6 +132,7 @@ u-boot,dm-pre-reloc; };
+// TODO: remove once PWR under SCMI &pwr_regulators { u-boot,dm-pre-reloc; }; @@ -184,6 +143,38 @@ #size-cells = <0>; };
+&scmi0 { + u-boot,dm-pre-reloc; +}; + +&scmi0_clk { + u-boot,dm-pre-reloc; +}; + +&scmi0_reset { + u-boot,dm-pre-reloc; +}; + +&scmi0_shm { + u-boot,dm-pre-reloc; +}; + +&scmi1 { + u-boot,dm-pre-reloc; +}; + +&scmi1_clk { + u-boot,dm-pre-reloc; +}; + +&scmi1_shm { + u-boot,dm-pre-reloc; +}; + +&scmi_sram { + u-boot,dm-pre-reloc; +}; + &sdmmc1 { compatible = "st,stm32-sdmmc2", "arm,pl18x", "arm,primecell"; }; @@ -197,7 +188,7 @@ };
&usart1 { - resets = <&rcc USART1_R>; + resets = <&scmi0_reset RST_SCMI0_USART1>; };
&usart2 { diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index 8e0a0bc1dd..db48077375 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -48,6 +48,69 @@ interrupt-parent = <&intc>; };
+ scmi_sram: sram@2ffff000 { + compatible = "mmio-sram"; + reg = <0x2ffff000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0x2ffff000 0x1000>; + + scmi0_shm: scmi_shm@0 { + reg = <0 0x80>; + }; + + scmi1_shm: scmi_shm@200 { + reg = <0x200 0x80>; + }; + }; + + firmware { + optee: optee { + compatible = "linaro,optee-tz"; + method = "smc"; + status = "disabled"; + }; + + scmi0: scmi0 { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + /* Supply properties for arm,scmi-smc compatible */ + arm,smc-id = <0x82002000>; + shmem = <&scmi0_shm>; + /* Enable only if stm32mp15x RCC[TZEN]=1 */ + status = "disabled"; + + scmi0_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi0_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + + scmi1: scmi1 { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <1>; + /* Supply properties for arm,scmi-smc compatible */ + arm,smc-id = <0x82002001>; + shmem = <&scmi1_shm>; + /* Enable only if stm32mp15x RCC[MCKPROT]=1 */ + status = "disabled"; + + scmi1_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + }; + }; + psci { compatible = "arm,psci-1.0"; method = "smc"; @@ -70,38 +133,6 @@ interrupt-parent = <&intc>; };
- clocks { - clk_hse: clk-hse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <24000000>; - }; - - clk_hsi: clk-hsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <64000000>; - }; - - clk_lse: clk-lse { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32768>; - }; - - clk_lsi: clk-lsi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <32000>; - }; - - clk_csi: clk-csi { - #clock-cells = <0>; - compatible = "fixed-clock"; - clock-frequency = <4000000>; - }; - }; - thermal-zones { cpu_thermal: cpu-thermal { polling-delay-passive = <0>; @@ -571,7 +602,7 @@ compatible = "st,stm32-cec"; reg = <0x40016000 0x400>; interrupts = <GIC_SPI 94 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc CEC_K>, <&clk_lse>; + clocks = <&rcc CEC_K>, <&scmi0_clk CK_SCMI0_LSE>; clock-names = "cec", "hdmi-cec"; status = "disabled"; }; @@ -1143,16 +1174,19 @@ };
rcc: rcc@50000000 { - compatible = "st,stm32mp1-rcc", "syscon"; + compatible = "st,stm32mp1-rcc-secure", "st,stm32mp1-rcc", "syscon"; reg = <0x50000000 0x1000>; #clock-cells = <1>; #reset-cells = <1>; - clock-names = "hse", "hsi", "csi", "lse", "lsi"; - clocks = <&clk_hse>, <&clk_hsi>, <&clk_csi>, - <&clk_lse>, <&clk_lsi>; + clocks = <&scmi0_clk CK_SCMI0_HSE>, + <&scmi0_clk CK_SCMI0_HSI>, + <&scmi0_clk CK_SCMI0_CSI>, + <&scmi0_clk CK_SCMI0_LSE>, + <&scmi0_clk CK_SCMI0_LSI>; };
+ // TODO: remove once under SCMI pwr_regulators: pwr@50001000 { compatible = "st,stm32mp1,pwr-reg"; reg = <0x50001000 0x10>; @@ -1333,8 +1367,8 @@ compatible = "st,stm32f756-hash"; reg = <0x54002000 0x400>; interrupts = <GIC_SPI 80 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc HASH1>; - resets = <&rcc HASH1_R>; + clocks = <&scmi0_clk CK_SCMI0_HASH1>; + resets = <&scmi0_reset RST_SCMI0_HASH1>; dmas = <&mdma1 31 0x2 0x1000A02 0x0 0x0>; dma-names = "in"; dma-maxburst = <2>; @@ -1344,8 +1378,8 @@ rng1: rng@54003000 { compatible = "st,stm32-rng"; reg = <0x54003000 0x400>; - clocks = <&rcc RNG1_K>; - resets = <&rcc RNG1_R>; + clocks = <&scmi0_clk CK_SCMI0_RNG1>; + resets = <&scmi0_reset RST_SCMI0_RNG1>; status = "disabled"; };
@@ -1354,7 +1388,7 @@ reg = <0x58000000 0x1000>; interrupts = <GIC_SPI 122 IRQ_TYPE_LEVEL_HIGH>; clocks = <&rcc MDMA>; - resets = <&rcc MDMA_R>; + resets = <&scmi0_reset RST_SCMI0_MDMA>; #dma-cells = <5>; dma-channels = <32>; dma-requests = <48>; @@ -1517,7 +1551,7 @@ iwdg2: watchdog@5a002000 { compatible = "st,stm32mp1-iwdg"; reg = <0x5a002000 0x400>; - clocks = <&rcc IWDG2>, <&rcc CK_LSI>; + clocks = <&rcc IWDG2>, <&scmi0_clk CK_SCMI0_LSI>; clock-names = "pclk", "lsi"; status = "disabled"; }; @@ -1549,7 +1583,7 @@ compatible = "st,stm32h7-uart"; reg = <0x5c000000 0x400>; interrupts-extended = <&exti 26 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc USART1_K>; + clocks = <&scmi0_clk CK_SCMI0_USART1>; wakeup-source; status = "disabled"; }; @@ -1560,8 +1594,8 @@ compatible = "st,stm32h7-spi"; reg = <0x5c001000 0x400>; interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc SPI6_K>; - resets = <&rcc SPI6_R>; + clocks = <&scmi0_clk CK_SCMI0_SPI6>; + resets = <&scmi0_reset RST_SCMI0_SPI6>; dmas = <&mdma1 34 0x0 0x40008 0x0 0x0>, <&mdma1 35 0x0 0x40002 0x0 0x0>; dma-names = "rx", "tx"; @@ -1574,8 +1608,8 @@ interrupt-names = "event", "error"; interrupts = <GIC_SPI 95 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C4_K>; - resets = <&rcc I2C4_R>; + clocks = <&scmi0_clk CK_SCMI0_I2C4>; + resets = <&scmi0_reset RST_SCMI0_I2C4>; #address-cells = <1>; #size-cells = <0>; st,syscfg-fmp = <&syscfg 0x4 0x8>; @@ -1587,7 +1621,8 @@ rtc: rtc@5c004000 { compatible = "st,stm32mp1-rtc"; reg = <0x5c004000 0x400>; - clocks = <&rcc RTCAPB>, <&rcc RTC>; + clocks = <&scmi0_clk CK_SCMI0_RTCAPB>, + <&scmi0_clk CK_SCMI0_RTC>; clock-names = "pclk", "rtc_ck"; interrupts = <GIC_SPI 3 IRQ_TYPE_LEVEL_HIGH>; status = "disabled"; @@ -1615,8 +1650,8 @@ interrupt-names = "event", "error"; interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc I2C6_K>; - resets = <&rcc I2C6_R>; + clocks = <&scmi0_clk CK_SCMI0_I2C6>; + resets = <&scmi0_reset RST_SCMI0_I2C6>; #address-cells = <1>; #size-cells = <0>; st,syscfg-fmp = <&syscfg 0x4 0x20>; @@ -1782,7 +1817,7 @@ interrupt-controller; #interrupt-cells = <2>; reg = <0 0x400>; - clocks = <&rcc GPIOZ>; + clocks = <&scmi0_clk CK_SCMI0_GPIOZ>; st,bank-name = "GPIOZ"; st,bank-ioport = <11>; status = "disabled"; @@ -1804,9 +1839,9 @@ reg = <0x10000000 0x40000>, <0x30000000 0x40000>, <0x38000000 0x10000>; - resets = <&rcc MCU_R>; - st,syscfg-holdboot = <&rcc 0x10C 0x1>; - st,syscfg-tz = <&rcc 0x000 0x1>; + resets = <&scmi0_reset RST_SCMI0_MCU>, + <&scmi0_reset RST_SCMI0_MCU_HOLD_BOOT>; + reset-names = "mcu_rst", "hold_boot"; st,syscfg-pdds = <&pwr_mcu 0x0 0x1>; st,syscfg-rsc-tbl = <&tamp 0x144 0xFFFFFFFF>; st,syscfg-m4-state = <&tamp 0x148 0xFFFFFFFF>; diff --git a/arch/arm/dts/stm32mp153.dtsi b/arch/arm/dts/stm32mp153.dtsi index 1c1889b194..e9ba6a9f30 100644 --- a/arch/arm/dts/stm32mp153.dtsi +++ b/arch/arm/dts/stm32mp153.dtsi @@ -13,6 +13,8 @@ clock-frequency = <650000000>; device_type = "cpu"; reg = <1>; + clocks = <&scmi0_clk CK_SCMI0_MPU>; + clock-names = "cpu"; }; };
@@ -30,7 +32,7 @@ interrupts = <GIC_SPI 19 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 21 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; - clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x0 0 0 32 0 0 2 2>; status = "disabled"; @@ -43,7 +45,7 @@ interrupts = <GIC_SPI 20 IRQ_TYPE_LEVEL_HIGH>, <GIC_SPI 22 IRQ_TYPE_LEVEL_HIGH>; interrupt-names = "int0", "int1"; - clocks = <&rcc CK_HSE>, <&rcc FDCAN_K>; + clocks = <&scmi0_clk CK_SCMI0_HSE>, <&rcc FDCAN_K>; clock-names = "hclk", "cclk"; bosch,mram-cfg = <0x1400 0 0 32 0 0 2 2>; status = "disabled"; diff --git a/arch/arm/dts/stm32mp157.dtsi b/arch/arm/dts/stm32mp157.dtsi index 54e73ccea4..7b06c08e3a 100644 --- a/arch/arm/dts/stm32mp157.dtsi +++ b/arch/arm/dts/stm32mp157.dtsi @@ -20,7 +20,7 @@ dsi: dsi@5a000000 { compatible = "st,stm32-dsi"; reg = <0x5a000000 0x800>; - clocks = <&rcc DSI_K>, <&clk_hse>, <&rcc DSI_PX>; + clocks = <&rcc DSI_K>, <&scmi0_clk CK_SCMI0_HSE>, <&rcc DSI_PX>; clock-names = "pclk", "ref", "px_clk"; resets = <&rcc DSI_R>; reset-names = "apb"; diff --git a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi index 15a04ae927..9e1c9c0329 100644 --- a/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157a-dk1-u-boot.dtsi @@ -31,6 +31,7 @@ /* only needed for boot with TF-A, witout FIP support */ firmware { optee { + u-boot,dm-pre-reloc; compatible = "linaro,optee-tz"; method = "smc"; }; @@ -38,8 +39,10 @@
reserved-memory { u-boot,dm-spl; + u-boot,dm-pre-reloc;
optee@de000000 { + u-boot,dm-pre-reloc; reg = <0xde000000 0x02000000>; no-map; u-boot,dm-spl; @@ -61,117 +64,6 @@ status = "okay"; };
-&clk_hse { - st,digbypass; -}; - -&i2c4 { - u-boot,dm-pre-reloc; -}; - -&i2c4_pins_a { - u-boot,dm-pre-reloc; - pins { - u-boot,dm-pre-reloc; - }; -}; - -&pmic { - u-boot,dm-pre-reloc; -}; - -&rcc { - st,clksrc = < - CLK_MPU_PLL1P - CLK_AXI_PLL2P - CLK_MCU_PLL3P - CLK_PLL12_HSE - CLK_PLL3_HSE - CLK_PLL4_HSE - CLK_RTC_LSE - CLK_MCO1_DISABLED - CLK_MCO2_DISABLED - >; - - st,clkdiv = < - 1 /*MPU*/ - 0 /*AXI*/ - 0 /*MCU*/ - 1 /*APB1*/ - 1 /*APB2*/ - 1 /*APB3*/ - 1 /*APB4*/ - 2 /*APB5*/ - 23 /*RTC*/ - 0 /*MCO1*/ - 0 /*MCO2*/ - >; - - st,pkcs = < - CLK_CKPER_HSE - CLK_FMC_ACLK - CLK_QSPI_ACLK - CLK_ETH_DISABLED - CLK_SDMMC12_PLL4P - CLK_DSI_DSIPLL - CLK_STGEN_HSE - CLK_USBPHY_HSE - CLK_SPI2S1_PLL3Q - CLK_SPI2S23_PLL3Q - CLK_SPI45_HSI - CLK_SPI6_HSI - CLK_I2C46_HSI - CLK_SDMMC3_PLL4P - CLK_USBO_USBPHY - CLK_ADC_CKPER - CLK_CEC_LSE - CLK_I2C12_HSI - CLK_I2C35_HSI - CLK_UART1_HSI - CLK_UART24_HSI - CLK_UART35_HSI - CLK_UART6_HSI - CLK_UART78_HSI - CLK_SPDIF_PLL4P - CLK_FDCAN_PLL4R - CLK_SAI1_PLL3Q - CLK_SAI2_PLL3Q - CLK_SAI3_PLL3Q - CLK_SAI4_PLL3Q - CLK_RNG1_LSI - CLK_RNG2_LSI - CLK_LPTIM1_PCLK1 - CLK_LPTIM23_PCLK3 - CLK_LPTIM45_LSE - >; - - /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ - pll2: st,pll@1 { - compatible = "st,stm32mp1-pll"; - reg = <1>; - cfg = < 2 65 1 0 0 PQR(1,1,1) >; - frac = < 0x1400 >; - u-boot,dm-pre-reloc; - }; - - /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ - pll3: st,pll@2 { - compatible = "st,stm32mp1-pll"; - reg = <2>; - cfg = < 1 33 1 16 36 PQR(1,1,1) >; - frac = < 0x1a04 >; - u-boot,dm-pre-reloc; - }; - - /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ - pll4: st,pll@3 { - compatible = "st,stm32mp1-pll"; - reg = <3>; - cfg = < 3 98 5 7 7 PQR(1,1,1) >; - u-boot,dm-pre-reloc; - }; -}; - &sdmmc1 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi b/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi index 06ef3a4095..9f9979dc5f 100644 --- a/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-dk2-u-boot.dtsi @@ -4,3 +4,43 @@ */
#include "stm32mp157a-dk1-u-boot.dtsi" + +&optee { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&scmi0 { + status = "okay"; + u-boot,dm-pre-reloc; +}; + +&scmi0_clk { + u-boot,dm-pre-reloc; +}; + +&scmi0_reset { + u-boot,dm-pre-reloc; +}; + +&scmi0_shm { + u-boot,dm-pre-reloc; +}; + +&scmi1 { + status = "disabled"; + u-boot,dm-pre-reloc; +}; + +&scmi1_clk { + u-boot,dm-pre-reloc; +}; + +&scmi1_shm { + u-boot,dm-pre-reloc; +}; + +&scmi_sram { + status = "okay"; + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts index 2bc92ef3ae..fb9300fcb1 100644 --- a/arch/arm/dts/stm32mp157c-dk2.dts +++ b/arch/arm/dts/stm32mp157c-dk2.dts @@ -99,3 +99,12 @@ pinctrl-2 = <&usart2_idle_pins_c>; status = "disabled"; }; + +&optee { + status = "okay"; +}; + +&scmi0 { + compatible = "linaro,scmi-optee"; + status = "okay"; +}; diff --git a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi index 408abaf52f..e2e1769d97 100644 --- a/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi +++ b/arch/arm/dts/stm32mp157c-ed1-u-boot.dtsi @@ -32,6 +32,8 @@ optee { compatible = "linaro,optee-tz"; method = "smc"; + u-boot,dm-pre-reloc; + status = "okay"; }; };
@@ -39,6 +41,7 @@ optee@fe000000 { reg = <0xfe000000 0x02000000>; no-map; + u-boot,dm-pre-reloc; }; }; #endif @@ -53,10 +56,6 @@ }; };
-&clk_hse { - st,digbypass; -}; - &i2c4 { u-boot,dm-pre-reloc; }; @@ -72,98 +71,6 @@ u-boot,dm-pre-reloc; };
-&rcc { - st,clksrc = < - CLK_MPU_PLL1P - CLK_AXI_PLL2P - CLK_MCU_PLL3P - CLK_PLL12_HSE - CLK_PLL3_HSE - CLK_PLL4_HSE - CLK_RTC_LSE - CLK_MCO1_DISABLED - CLK_MCO2_DISABLED - >; - - st,clkdiv = < - 1 /*MPU*/ - 0 /*AXI*/ - 0 /*MCU*/ - 1 /*APB1*/ - 1 /*APB2*/ - 1 /*APB3*/ - 1 /*APB4*/ - 2 /*APB5*/ - 23 /*RTC*/ - 0 /*MCO1*/ - 0 /*MCO2*/ - >; - - st,pkcs = < - CLK_CKPER_HSE - CLK_FMC_ACLK - CLK_QSPI_ACLK - CLK_ETH_DISABLED - CLK_SDMMC12_PLL4P - CLK_DSI_DSIPLL - CLK_STGEN_HSE - CLK_USBPHY_HSE - CLK_SPI2S1_PLL3Q - CLK_SPI2S23_PLL3Q - CLK_SPI45_HSI - CLK_SPI6_HSI - CLK_I2C46_HSI - CLK_SDMMC3_PLL4P - CLK_USBO_USBPHY - CLK_ADC_CKPER - CLK_CEC_LSE - CLK_I2C12_HSI - CLK_I2C35_HSI - CLK_UART1_HSI - CLK_UART24_HSI - CLK_UART35_HSI - CLK_UART6_HSI - CLK_UART78_HSI - CLK_SPDIF_PLL4P - CLK_FDCAN_PLL4R - CLK_SAI1_PLL3Q - CLK_SAI2_PLL3Q - CLK_SAI3_PLL3Q - CLK_SAI4_PLL3Q - CLK_RNG1_LSI - CLK_RNG2_LSI - CLK_LPTIM1_PCLK1 - CLK_LPTIM23_PCLK3 - CLK_LPTIM45_LSE - >; - - /* VCO = 1066.0 MHz => P = 266 (AXI), Q = 533 (GPU), R = 533 (DDR) */ - pll2: st,pll@1 { - compatible = "st,stm32mp1-pll"; - reg = <1>; - cfg = < 2 65 1 0 0 PQR(1,1,1) >; - frac = < 0x1400 >; - u-boot,dm-pre-reloc; - }; - - /* VCO = 417.8 MHz => P = 209, Q = 24, R = 11 */ - pll3: st,pll@2 { - compatible = "st,stm32mp1-pll"; - reg = <2>; - cfg = < 1 33 1 16 36 PQR(1,1,1) >; - frac = < 0x1a04 >; - u-boot,dm-pre-reloc; - }; - - /* VCO = 594.0 MHz => P = 99, Q = 74, R = 74 */ - pll4: st,pll@3 { - compatible = "st,stm32mp1-pll"; - reg = <3>; - cfg = < 3 98 5 7 7 PQR(1,1,1) >; - u-boot,dm-pre-reloc; - }; -}; - &sdmmc1 { u-boot,dm-spl; }; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index 6e89f88a17..eabf00f1fe 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -341,6 +341,11 @@ status = "okay"; };
+&scmi0 { + compatible = "linaro,scmi-optee"; + status = "okay"; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a &sdmmc1_dir_pins_a>; diff --git a/arch/arm/dts/stm32mp157c-odyssey.dts b/arch/arm/dts/stm32mp157c-odyssey.dts index 0e725498dd..9823d5d5ca 100644 --- a/arch/arm/dts/stm32mp157c-odyssey.dts +++ b/arch/arm/dts/stm32mp157c-odyssey.dts @@ -21,6 +21,20 @@ stdout-path = "serial0:115200n8"; };
+ clocks { + clk_hse: clk-hse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <24000000>; + }; + + clk_lse: clk-lse { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <32768>; + }; + }; + led { compatible = "gpio-leds"; blue { diff --git a/arch/arm/dts/stm32mp15xc.dtsi b/arch/arm/dts/stm32mp15xc.dtsi index b06a55a2fa..435846883f 100644 --- a/arch/arm/dts/stm32mp15xc.dtsi +++ b/arch/arm/dts/stm32mp15xc.dtsi @@ -10,8 +10,8 @@ compatible = "st,stm32mp1-cryp"; reg = <0x54001000 0x400>; interrupts = <GIC_SPI 79 IRQ_TYPE_LEVEL_HIGH>; - clocks = <&rcc CRYP1>; - resets = <&rcc CRYP1_R>; + clocks = <&scmi0_clk CK_SCMI0_CRYP1>; + resets = <&scmi0_reset RST_SCMI0_CRYP1>; status = "disabled"; }; }; diff --git a/include/dt-bindings/clock/stm32mp1-clks.h b/include/dt-bindings/clock/stm32mp1-clks.h index 4cdaf13582..e02770b98e 100644 --- a/include/dt-bindings/clock/stm32mp1-clks.h +++ b/include/dt-bindings/clock/stm32mp1-clks.h @@ -248,4 +248,31 @@
#define STM32MP1_LAST_CLK 232
+/* SCMI clock identifiers */ +#define CK_SCMI0_HSE 0 +#define CK_SCMI0_HSI 1 +#define CK_SCMI0_CSI 2 +#define CK_SCMI0_LSE 3 +#define CK_SCMI0_LSI 4 +#define CK_SCMI0_PLL2_Q 5 +#define CK_SCMI0_PLL2_R 6 +#define CK_SCMI0_MPU 7 +#define CK_SCMI0_AXI 8 +#define CK_SCMI0_BSEC 9 +#define CK_SCMI0_CRYP1 10 +#define CK_SCMI0_GPIOZ 11 +#define CK_SCMI0_HASH1 12 +#define CK_SCMI0_I2C4 13 +#define CK_SCMI0_I2C6 14 +#define CK_SCMI0_IWDG1 15 +#define CK_SCMI0_RNG1 16 +#define CK_SCMI0_RTC 17 +#define CK_SCMI0_RTCAPB 18 +#define CK_SCMI0_SPI6 19 +#define CK_SCMI0_USART1 20 + +#define CK_SCMI1_PLL3_Q 0 +#define CK_SCMI1_PLL3_R 1 +#define CK_SCMI1_MCU 2 + #endif /* _DT_BINDINGS_STM32MP1_CLKS_H_ */ diff --git a/include/dt-bindings/reset/stm32mp1-resets.h b/include/dt-bindings/reset/stm32mp1-resets.h index 702da37a2e..f3a0ed3178 100644 --- a/include/dt-bindings/reset/stm32mp1-resets.h +++ b/include/dt-bindings/reset/stm32mp1-resets.h @@ -106,4 +106,18 @@ #define GPIOJ_R 19785 #define GPIOK_R 19786
+/* SCMI reset domain identifiers */ +#define RST_SCMI0_SPI6 0 +#define RST_SCMI0_I2C4 1 +#define RST_SCMI0_I2C6 2 +#define RST_SCMI0_USART1 3 +#define RST_SCMI0_STGEN 4 +#define RST_SCMI0_GPIOZ 5 +#define RST_SCMI0_CRYP1 6 +#define RST_SCMI0_HASH1 7 +#define RST_SCMI0_RNG1 8 +#define RST_SCMI0_MDMA 9 +#define RST_SCMI0_MCU 10 +#define RST_SCMI0_MCU_HOLD_BOOT 11 + #endif /* _DT_BINDINGS_STM32MP1_RESET_H_ */
Signed-off-by: Etienne Carriere etienne.carriere@linaro.org --- arch/arm/dts/stm32mp151.dtsi | 40 +++++++++- arch/arm/dts/stm32mp15xx-dkx.dtsi | 122 +++++++++++++++++++++++++----- 2 files changed, 138 insertions(+), 24 deletions(-)
diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index db48077375..cb6a14ec0c 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -5,6 +5,7 @@ */ #include <dt-bindings/interrupt-controller/arm-gic.h> #include <dt-bindings/clock/stm32mp1-clks.h> +#include <dt-bindings/regulator/st,stm32mp15-regulator.h> #include <dt-bindings/reset/stm32mp1-resets.h>
/ { @@ -91,6 +92,37 @@ reg = <0x16>; #reset-cells = <1>; }; + + scmi0_voltd: protocol@17 { + reg = <0x17>; + + scmi0_reguls: regulators { + #address-cells = <1>; + #size-cells = <0>; + + reg11: reg11 { + reg = <VOLTD_SCMI0_REG11>; + regulator-name = "reg11"; + regulator-min-microvolt = <1100000>; + regulator-max-microvolt = <1100000>; + }; + + reg18: reg18 { + voltd-name = "reg18"; + reg = <VOLTD_SCMI0_REG18>; + regulator-name = "reg18"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + + usb33: usb33 { + reg = <VOLTD_SCMI0_USB33>; + regulator-name = "usb33"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + }; + }; + }; };
scmi1: scmi1 { @@ -1190,20 +1222,22 @@ pwr_regulators: pwr@50001000 { compatible = "st,stm32mp1,pwr-reg"; reg = <0x50001000 0x10>; + status = "disabled"; + secure-status = "okay";
- reg11: reg11 { + pwr_reg11: reg11 { regulator-name = "reg11"; regulator-min-microvolt = <1100000>; regulator-max-microvolt = <1100000>; };
- reg18: reg18 { + pwr_reg18: reg18 { regulator-name = "reg18"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; };
- usb33: usb33 { + pwr_usb33: usb33 { regulator-name = "usb33"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; diff --git a/arch/arm/dts/stm32mp15xx-dkx.dtsi b/arch/arm/dts/stm32mp15xx-dkx.dtsi index 68987f64c5..ba196c7a45 100644 --- a/arch/arm/dts/stm32mp15xx-dkx.dtsi +++ b/arch/arm/dts/stm32mp15xx-dkx.dtsi @@ -6,6 +6,7 @@
#include <dt-bindings/gpio/gpio.h> #include <dt-bindings/mfd/st,stpmic1.h> +#include <dt-bindings/regulator/st,stm32mp15-regulator.h>
/ { memory@c0000000 { @@ -261,7 +262,7 @@ interrupt-parent = <&gpioi>; pinctrl-names = "default"; pinctrl-0 = <&stusb1600_pins_a>; - status = "okay"; + status = "disabled"; vdd-supply = <&vin>;
connector { @@ -284,7 +285,8 @@ interrupts-extended = <&gpioa 0 IRQ_TYPE_EDGE_FALLING>; interrupt-controller; #interrupt-cells = <2>; - status = "okay"; + status = "disabled"; + secure-status = "okay";
regulators { compatible = "st,stpmic1-regulators"; @@ -292,18 +294,18 @@ buck2-supply = <&vin>; buck3-supply = <&vin>; buck4-supply = <&vin>; - ldo1-supply = <&v3v3>; + ldo1-supply = <&secure_v3v3>; ldo2-supply = <&vin>; - ldo3-supply = <&vdd_ddr>; + ldo3-supply = <&secure_vdd_ddr>; ldo4-supply = <&vin>; ldo5-supply = <&vin>; - ldo6-supply = <&v3v3>; + ldo6-supply = <&secure_v3v3>; vref_ddr-supply = <&vin>; boost-supply = <&vin>; - pwr_sw1-supply = <&bst_out>; - pwr_sw2-supply = <&bst_out>; + pwr_sw1-supply = <&secure_bst_out>; + pwr_sw2-supply = <&secure_bst_out>;
- vddcore: buck1 { + secure_vddcore: buck1 { regulator-name = "vddcore"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1350000>; @@ -312,7 +314,7 @@ regulator-over-current-protection; };
- vdd_ddr: buck2 { + secure_vdd_ddr: buck2 { regulator-name = "vdd_ddr"; regulator-min-microvolt = <1350000>; regulator-max-microvolt = <1350000>; @@ -321,7 +323,7 @@ regulator-over-current-protection; };
- vdd: buck3 { + secure_vdd: buck3 { regulator-name = "vdd"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -331,7 +333,7 @@ regulator-over-current-protection; };
- v3v3: buck4 { + secure_v3v3: buck4 { regulator-name = "v3v3"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -340,7 +342,7 @@ regulator-initial-mode = <0>; };
- v1v8_audio: ldo1 { + secure_v1v8_audio: ldo1 { regulator-name = "v1v8_audio"; regulator-min-microvolt = <1800000>; regulator-max-microvolt = <1800000>; @@ -348,7 +350,7 @@ interrupts = <IT_CURLIM_LDO1 0>; };
- v3v3_hdmi: ldo2 { + secure_v3v3_hdmi: ldo2 { regulator-name = "v3v3_hdmi"; regulator-min-microvolt = <3300000>; regulator-max-microvolt = <3300000>; @@ -356,7 +358,7 @@ interrupts = <IT_CURLIM_LDO2 0>; };
- vtt_ddr: ldo3 { + secure_vtt_ddr: ldo3 { regulator-name = "vtt_ddr"; regulator-min-microvolt = <500000>; regulator-max-microvolt = <750000>; @@ -364,12 +366,12 @@ regulator-over-current-protection; };
- vdd_usb: ldo4 { + secure_vdd_usb: ldo4 { regulator-name = "vdd_usb"; interrupts = <IT_CURLIM_LDO4 0>; };
- vdda: ldo5 { + secure_vdda: ldo5 { regulator-name = "vdda"; regulator-min-microvolt = <2900000>; regulator-max-microvolt = <2900000>; @@ -377,7 +379,7 @@ regulator-boot-on; };
- v1v2_hdmi: ldo6 { + secure_v1v2_hdmi: ldo6 { regulator-name = "v1v2_hdmi"; regulator-min-microvolt = <1200000>; regulator-max-microvolt = <1200000>; @@ -385,22 +387,22 @@ interrupts = <IT_CURLIM_LDO6 0>; };
- vref_ddr: vref_ddr { + secure_vref_ddr: vref_ddr { regulator-name = "vref_ddr"; regulator-always-on; };
- bst_out: boost { + secure_bst_out: boost { regulator-name = "bst_out"; interrupts = <IT_OCP_BOOST 0>; };
- vbus_otg: pwr_sw1 { + secure_vbus_otg: pwr_sw1 { regulator-name = "vbus_otg"; interrupts = <IT_OCP_OTG 0>; };
- vbus_sw: pwr_sw2 { + secure_vbus_sw: pwr_sw2 { regulator-name = "vbus_sw"; interrupts = <IT_OCP_SWOUT 0>; regulator-active-discharge = <1>; @@ -543,6 +545,84 @@ }; };
+&scmi0_reguls { + vddcore: scmi-vddcore { + reg = <VOLTD_SCMI0_STPMIC1_BUCK1>; + regulator-name = "vddcore"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1350000>; + regulator-always-on; + }; + + vdd: scmi-vdd { + reg = <VOLTD_SCMI0_STPMIC1_BUCK3>; + regulator-name = "vdd"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v3v3: scmi-v3v3 { + reg = <VOLTD_SCMI0_STPMIC1_BUCK4>; + regulator-name = "v3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + v1v8_audio: scmi-v1v8-audio { + reg = <VOLTD_SCMI0_STPMIC1_LDO1>; + regulator-name = "v1v8_audio"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-always-on; + }; + + v3v3_hdmi: scmi-v3v3-hdmi { + reg = <VOLTD_SCMI0_STPMIC1_LDO2>; + regulator-name = "v3v3_hdmi"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + vdd_usb: scmi-vdd-usb { + reg = <VOLTD_SCMI0_STPMIC1_LDO4>; + regulator-name = "vdd_usb"; + }; + + vdda: scmi-vdda { + reg = <VOLTD_SCMI0_STPMIC1_LDO5>; + regulator-name = "vdda"; + regulator-min-microvolt = <2900000>; + regulator-max-microvolt = <2900000>; + regulator-boot-on; + }; + + v1v2_hdmi: scmi-v1v2-hdmi { + reg = <VOLTD_SCMI0_STPMIC1_LDO6>; + regulator-name = "v1v2_hdmi"; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + regulator-always-on; + }; + + bst_out: scmi-bst-out { + reg = <VOLTD_SCMI0_STPMIC1_BOOST>; + regulator-name = "bst_out"; + }; + + vbus_otg: scmi-vbus-otg { + reg = <VOLTD_SCMI0_STPMIC1_PWR_SW1>; + regulator-name = "vbus_otg"; + }; + + vbus_sw: scmi-vbus-sw { + reg = <VOLTD_SCMI0_STPMIC1_PWR_SW2>; + regulator-name = "vbus_sw"; + }; +}; + &sdmmc1 { pinctrl-names = "default", "opendrain", "sleep"; pinctrl-0 = <&sdmmc1_b4_pins_a>;
Requires OP-TEE OS to be built with CFG_STM32MP1_SCMI_SIP=y.
Signed-off-by: Etienne Carriere etienne.carriere@linaro.org --- arch/arm/dts/stm32mp151.dtsi | 5 +++-- arch/arm/dts/stm32mp157c-dk2.dts | 1 - arch/arm/dts/stm32mp157c-ed1.dts | 1 - 3 files changed, 3 insertions(+), 4 deletions(-)
diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index cb6a14ec0c..6eaf3760bc 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -73,10 +73,11 @@ };
scmi0: scmi0 { - compatible = "linaro,scmi-optee"; + //compatible = "linaro,scmi-optee"; + compatible = "arm,scmi-smc"; #address-cells = <1>; #size-cells = <0>; - linaro,optee-channel-id = <0>; + //linaro,optee-channel-id = <0>; /* Supply properties for arm,scmi-smc compatible */ arm,smc-id = <0x82002000>; shmem = <&scmi0_shm>; diff --git a/arch/arm/dts/stm32mp157c-dk2.dts b/arch/arm/dts/stm32mp157c-dk2.dts index fb9300fcb1..5f23dba3e3 100644 --- a/arch/arm/dts/stm32mp157c-dk2.dts +++ b/arch/arm/dts/stm32mp157c-dk2.dts @@ -105,6 +105,5 @@ };
&scmi0 { - compatible = "linaro,scmi-optee"; status = "okay"; }; diff --git a/arch/arm/dts/stm32mp157c-ed1.dts b/arch/arm/dts/stm32mp157c-ed1.dts index eabf00f1fe..26847b5c76 100644 --- a/arch/arm/dts/stm32mp157c-ed1.dts +++ b/arch/arm/dts/stm32mp157c-ed1.dts @@ -342,7 +342,6 @@ };
&scmi0 { - compatible = "linaro,scmi-optee"; status = "okay"; };
From: Etienne Carriere etienne.carriere@st.com
Basic mailbox inspired from https://patchwork.kernel.org/patch/11166071/.
When sending a message, the mailbox invokes the Cortex-A Arm Trustzone secure monitor with an SMC or HVC instruction providing a function identifier in register R0/X0 defined by the DTB.
Signed-off-by: Etienne Carriere etienne.carriere@st.com Signed-off-by: Etienne Carriere etienne.carriere@linaro.org --- drivers/mailbox/Kconfig | 8 +++ drivers/mailbox/Makefile | 1 + drivers/mailbox/arm-smc-mbox.c | 123 +++++++++++++++++++++++++++++++++ 3 files changed, 132 insertions(+) create mode 100644 drivers/mailbox/arm-smc-mbox.c
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig index dd4b0ac0c3..599d1df1ae 100644 --- a/drivers/mailbox/Kconfig +++ b/drivers/mailbox/Kconfig @@ -47,4 +47,12 @@ config ZYNQMP_IPI help This enables support for the Xilinx ZynqMP Inter Processor Interrupt communication controller. + +config ARM_SMC_MAILBOX + bool "Enable Arm SMC mailbox support" + depends on DM_MAILBOX && ARM_SMCCC + default y + help + Mailbox notification through an Arm SMC or HVC calls. + endmenu diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile index d2ace8cd21..7a56a454b8 100644 --- a/drivers/mailbox/Makefile +++ b/drivers/mailbox/Makefile @@ -3,6 +3,7 @@ # Copyright (c) 2016, NVIDIA CORPORATION. #
+obj-$(CONFIG_ARM_SMC_MAILBOX) += arm-smc-mbox.o obj-$(CONFIG_$(SPL_)DM_MAILBOX) += mailbox-uclass.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox.o obj-$(CONFIG_SANDBOX_MBOX) += sandbox-mbox-test.o diff --git a/drivers/mailbox/arm-smc-mbox.c b/drivers/mailbox/arm-smc-mbox.c new file mode 100644 index 0000000000..d379da490a --- /dev/null +++ b/drivers/mailbox/arm-smc-mbox.c @@ -0,0 +1,123 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2019, Linaro Limited + */ + +#define LOG_CATEGORY UCLASS_MAILBOX + +#include <common.h> +#include <dm.h> +#include <mailbox-uclass.h> +#include <dm/device.h> +#include <dm/device_compat.h> +#include <linux/arm-smccc.h> +#include <linux/compat.h> + +#define ARM_SMC_METHOD 0 +#define ARM_HVC_METHOD 1 + +typedef void (invoke_fn_t)(unsigned long); + +struct smc_pdata { + unsigned long func_id; + invoke_fn_t *invoke_fn; +}; + +/* Simple wrapper functions to be able to use a function pointer */ +static void smccc_smc(unsigned long a0) +{ + struct arm_smccc_res res; + + arm_smccc_smc(a0, 0, 0, 0, 0, 0, 0, 0, &res); +} + +static void smccc_hvc(unsigned long a0) +{ + struct arm_smccc_res res; + + arm_smccc_hvc(a0, 0, 0, 0, 0, 0, 0, 0, &res); +} + +static int smc_mbox_send(struct mbox_chan *chan, const void *data) +{ + struct smc_pdata *pdata = dev_get_plat(chan->dev); + + /* + * This mailbox invokes secure world for a channel event. + * Message is already in the channel's shared memory. + */ + pdata->invoke_fn(pdata->func_id); + + return 0; +} + +static int smc_mbox_recv(struct mbox_chan *chan, void *data) +{ + /* Mbox owner already got the return message from shared memory */ + return 0; +} + +static int smc_mbox_request(struct mbox_chan *chan) +{ + return 0; +} + +static int smc_mbox_rfree(struct mbox_chan *chan) +{ + return 0; +} + +static int smc_mbox_of_xlate(struct mbox_chan *chan, + struct ofnode_phandle_args *args) +{ + if (args->args_count) + dev_warn(chan->dev, "Expect no argument to smc-mbox cells\n"); + + chan->id = 0; + + return 0; +} + +static int smc_mbox_ofdata_to_platdata(struct udevice *dev) +{ + ulong compat_data = dev_get_driver_data(dev); + struct smc_pdata *pdata = dev_get_plat(dev); + u32 func_id; + + if (dev_read_u32(dev, "arm,func-id", &func_id)) { + dev_err(dev, "Missing property arm,func-id\n"); + return -EINVAL; + } + + pdata->func_id = func_id; + + if (compat_data == ARM_SMC_METHOD) + pdata->invoke_fn = smccc_smc; + else + pdata->invoke_fn = smccc_hvc; + + return 0; +} + +static const struct udevice_id smc_mbox_ids[] = { + { .compatible = "arm,smc-mbox", .data = ARM_SMC_METHOD, }, + { .compatible = "arm,hvc-mbox", .data = ARM_HVC_METHOD, }, + { } +}; + +struct mbox_ops smc_mbox_ops = { + .of_xlate = smc_mbox_of_xlate, + .request = smc_mbox_request, + .rfree = smc_mbox_rfree, + .send = smc_mbox_send, + .recv = smc_mbox_recv, +}; + +U_BOOT_DRIVER(smc_mbox) = { + .name = "arm_smc_mbox", + .id = UCLASS_MAILBOX, + .of_match = smc_mbox_ids, + .of_to_plat = smc_mbox_ofdata_to_platdata, + .plat_auto = sizeof(struct smc_pdata), + .ops = &smc_mbox_ops, +};
Signed-off-by: Etienne Carriere etienne.carriere@linaro.org --- arch/arm/dts/stm32mp15-u-boot.dtsi | 4 ++++ arch/arm/dts/stm32mp151.dtsi | 21 ++++++++++++++++----- 2 files changed, 20 insertions(+), 5 deletions(-)
diff --git a/arch/arm/dts/stm32mp15-u-boot.dtsi b/arch/arm/dts/stm32mp15-u-boot.dtsi index 6fd204c635..d69b2df419 100644 --- a/arch/arm/dts/stm32mp15-u-boot.dtsi +++ b/arch/arm/dts/stm32mp15-u-boot.dtsi @@ -151,6 +151,10 @@ u-boot,dm-pre-reloc; };
+&scmi0_mbox { + u-boot,dm-pre-reloc; +}; + &scmi0_reset { u-boot,dm-pre-reloc; }; diff --git a/arch/arm/dts/stm32mp151.dtsi b/arch/arm/dts/stm32mp151.dtsi index 6eaf3760bc..8fcce4aa2a 100644 --- a/arch/arm/dts/stm32mp151.dtsi +++ b/arch/arm/dts/stm32mp151.dtsi @@ -65,6 +65,12 @@ }; };
+ scmi0_mbox: mailbox-0 { + #mbox-cells = <0>; + compatible = "arm,smc-mbox"; + arm,func-id = <0x82002000>; + }; + firmware { optee: optee { compatible = "linaro,optee-tz"; @@ -73,17 +79,22 @@ };
scmi0: scmi0 { - //compatible = "linaro,scmi-optee"; - compatible = "arm,scmi-smc"; #address-cells = <1>; #size-cells = <0>; - //linaro,optee-channel-id = <0>; - /* Supply properties for arm,scmi-smc compatible */ - arm,smc-id = <0x82002000>; shmem = <&scmi0_shm>; /* Enable only if stm32mp15x RCC[TZEN]=1 */ status = "disabled";
+ //compatible = "linaro,scmi-optee"; + //linaro,optee-channel-id = <0>; + + //compatible = "arm,scmi-smc"; + //arm,smc-id = <0x82002000>; + + compatible = "arm,scmi"; + mboxes = <&scmi0_mbox>; + mbox-names = "txrx"; + scmi0_clk: protocol@14 { reg = <0x14>; #clock-cells = <1>;
Increase CONFIG_SYS_MALLOC_F_LEN for pre-reloc trace buffers and enable earlyprintk config for STM32.
Change-Id: Ibcfcff1f0e6af7eb73b5c53c717bfc6ea20881af Signed-off-by: Etienne Carriere etienne.carriere@linaro.org --- configs/stm32mp15_trusted_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index dc1f48c518..b5608bec42 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_STM32MP=y CONFIG_TFABOOT=y -CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SYS_MALLOC_F_LEN=0x40000 CONFIG_SYS_MEMTEST_START=0xc0000000 CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_ENV_OFFSET=0x280000 @@ -159,3 +159,5 @@ CONFIG_FDT_FIXUP_PARTITIONS=y # CONFIG_LMB_USE_MAX_REGIONS is not set CONFIG_LMB_MEMORY_REGIONS=2 CONFIG_LMB_RESERVED_REGIONS=16 +CONFIG_DEBUG_UART_STM32=y +CONFIG_DEBUG_UART=y
Dear ML,
My apologies for this series. I intended to post only the 5 first ones.
Please discard those 14 patches.
I'll close all of them through patchwork and will re-send a corrected series.
Regards, Etienne
On Thu, 4 Nov 2021 at 15:23, Etienne Carriere etienne.carriere@linaro.org wrote:
Increase CONFIG_SYS_MALLOC_F_LEN for pre-reloc trace buffers and enable earlyprintk config for STM32.
Change-Id: Ibcfcff1f0e6af7eb73b5c53c717bfc6ea20881af Signed-off-by: Etienne Carriere etienne.carriere@linaro.org
configs/stm32mp15_trusted_defconfig | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/configs/stm32mp15_trusted_defconfig b/configs/stm32mp15_trusted_defconfig index dc1f48c518..b5608bec42 100644 --- a/configs/stm32mp15_trusted_defconfig +++ b/configs/stm32mp15_trusted_defconfig @@ -1,7 +1,7 @@ CONFIG_ARM=y CONFIG_ARCH_STM32MP=y CONFIG_TFABOOT=y -CONFIG_SYS_MALLOC_F_LEN=0x10000 +CONFIG_SYS_MALLOC_F_LEN=0x40000 CONFIG_SYS_MEMTEST_START=0xc0000000 CONFIG_SYS_MEMTEST_END=0xc4000000 CONFIG_ENV_OFFSET=0x280000 @@ -159,3 +159,5 @@ CONFIG_FDT_FIXUP_PARTITIONS=y # CONFIG_LMB_USE_MAX_REGIONS is not set CONFIG_LMB_MEMORY_REGIONS=2 CONFIG_LMB_RESERVED_REGIONS=16 +CONFIG_DEBUG_UART_STM32=y
+CONFIG_DEBUG_UART=y
2.17.1
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Etienne Carriere