[PATCH v1 0/9] Add STM32MP2 SoCs and STM32MP257F-EV board support
Add STM32MP257F Evaluation board support, it embeds a STM32MP257FAI SoC, with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA, 1*USB2 typeC, SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...
Patrice Chotard (8): arm: caches: Make DCACHE_DEFAULT_OPTION accessible for ARM64 arch stm32mp: dram_init: Get RAM size from DT if no RAM driver found stm32mp: dram_init: Limit DDR usage under 4GB boundary for STM32MP stm32mp: bsec: Fix AARCH64 compilation warnings serial: stm32: Fix AARCH64 compilation warnings pinctrl: pinctrl_stm32: Add stm32mp2 support ARM: dts: stm32: Add STM32MP257F Evaluation board support stm32mp2: initial support
Patrick Delaunay (1): stm32mp: dram_init: Fix AARCH64 compilation warnings
arch/arm/Kconfig | 2 +- arch/arm/dts/Makefile | 3 + arch/arm/dts/stm32mp25-pinctrl.dtsi | 38 +++ arch/arm/dts/stm32mp25-u-boot.dtsi | 102 +++++++ arch/arm/dts/stm32mp251.dtsi | 285 ++++++++++++++++++ arch/arm/dts/stm32mp253.dtsi | 23 ++ arch/arm/dts/stm32mp255.dtsi | 9 + arch/arm/dts/stm32mp257.dtsi | 9 + arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi | 20 ++ arch/arm/dts/stm32mp257f-ev1.dts | 55 ++++ arch/arm/dts/stm32mp25xc.dtsi | 8 + arch/arm/dts/stm32mp25xf.dtsi | 8 + arch/arm/dts/stm32mp25xxai-pinctrl.dtsi | 83 +++++ arch/arm/dts/stm32mp25xxak-pinctrl.dtsi | 71 +++++ arch/arm/dts/stm32mp25xxal-pinctrl.dtsi | 71 +++++ arch/arm/include/asm/system.h | 16 +- arch/arm/mach-stm32mp/Kconfig | 26 +- arch/arm/mach-stm32mp/Kconfig.25x | 43 +++ arch/arm/mach-stm32mp/Makefile | 15 +- arch/arm/mach-stm32mp/bsec.c | 29 +- arch/arm/mach-stm32mp/dram_init.c | 17 +- arch/arm/mach-stm32mp/include/mach/stm32.h | 141 +++++---- .../arm/mach-stm32mp/include/mach/sys_proto.h | 26 ++ arch/arm/mach-stm32mp/stm32mp1/Makefile | 20 ++ arch/arm/mach-stm32mp/{ => stm32mp1}/cpu.c | 0 arch/arm/mach-stm32mp/{ => stm32mp1}/fdt.c | 0 arch/arm/mach-stm32mp/{ => stm32mp1}/psci.c | 0 .../{ => stm32mp1}/pwr_regulator.c | 0 arch/arm/mach-stm32mp/{ => stm32mp1}/spl.c | 0 .../mach-stm32mp/{ => stm32mp1}/stm32mp13x.c | 0 .../mach-stm32mp/{ => stm32mp1}/stm32mp15x.c | 0 arch/arm/mach-stm32mp/{ => stm32mp1}/tzc400.c | 0 arch/arm/mach-stm32mp/stm32mp2/Makefile | 9 + arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c | 68 +++++ arch/arm/mach-stm32mp/stm32mp2/cpu.c | 108 +++++++ arch/arm/mach-stm32mp/stm32mp2/fdt.c | 16 + arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c | 194 ++++++++++++ arch/arm/mach-stm32mp/syscon.c | 4 +- board/st/stm32mp2/Kconfig | 13 + board/st/stm32mp2/MAINTAINERS | 9 + board/st/stm32mp2/Makefile | 6 + board/st/stm32mp2/stm32mp2.c | 52 ++++ configs/stm32mp25_defconfig | 52 ++++ drivers/pinctrl/pinctrl_stm32.c | 2 + drivers/serial/serial_stm32.c | 23 +- drivers/serial/serial_stm32.h | 2 +- include/configs/stm32mp25_common.h | 24 ++ include/dt-bindings/pinctrl/stm32-pinfunc.h | 3 + 48 files changed, 1597 insertions(+), 108 deletions(-) create mode 100644 arch/arm/dts/stm32mp25-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32mp25-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp251.dtsi create mode 100644 arch/arm/dts/stm32mp253.dtsi create mode 100644 arch/arm/dts/stm32mp255.dtsi create mode 100644 arch/arm/dts/stm32mp257.dtsi create mode 100644 arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp257f-ev1.dts create mode 100644 arch/arm/dts/stm32mp25xc.dtsi create mode 100644 arch/arm/dts/stm32mp25xf.dtsi create mode 100644 arch/arm/dts/stm32mp25xxai-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32mp25xxak-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32mp25xxal-pinctrl.dtsi create mode 100644 arch/arm/mach-stm32mp/Kconfig.25x create mode 100644 arch/arm/mach-stm32mp/stm32mp1/Makefile rename arch/arm/mach-stm32mp/{ => stm32mp1}/cpu.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/fdt.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/psci.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/pwr_regulator.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/spl.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/stm32mp13x.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/stm32mp15x.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/tzc400.c (100%) create mode 100644 arch/arm/mach-stm32mp/stm32mp2/Makefile create mode 100644 arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c create mode 100644 arch/arm/mach-stm32mp/stm32mp2/cpu.c create mode 100644 arch/arm/mach-stm32mp/stm32mp2/fdt.c create mode 100644 arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c create mode 100644 board/st/stm32mp2/Kconfig create mode 100644 board/st/stm32mp2/MAINTAINERS create mode 100644 board/st/stm32mp2/Makefile create mode 100644 board/st/stm32mp2/stm32mp2.c create mode 100644 configs/stm32mp25_defconfig create mode 100644 include/configs/stm32mp25_common.h
This fixes the following compilation error in ARM64: arch/arm/mach-stm32mp/dram_init.c: In function ‘board_get_usable_ram_top’: arch/arm/mach-stm32mp/dram_init.c:59:45: error: ‘DCACHE_DEFAULT_OPTION’ undeclared (first use in this function) 59 | mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION); | ^~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com ---
arch/arm/include/asm/system.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 0eae857e73a..43f7503571d 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -513,14 +513,6 @@ enum dcache_option { }; #endif
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) -#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH -#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) -#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC -#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK) -#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK -#endif - /* Size of an MMU section */ enum { #ifdef CONFIG_ARMV7_LPAE @@ -578,6 +570,14 @@ void psci_system_reset(void);
#endif /* CONFIG_ARM64 */
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK +#endif + #ifndef __ASSEMBLY__ /** * save_boot_params() - Save boot parameters before starting reset sequence
Hi,
On 10/27/23 16:42, Patrice Chotard wrote:
This fixes the following compilation error in ARM64: arch/arm/mach-stm32mp/dram_init.c: In function ‘board_get_usable_ram_top’: arch/arm/mach-stm32mp/dram_init.c:59:45: error: ‘DCACHE_DEFAULT_OPTION’ undeclared (first use in this function) 59 | mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION); | ^~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com
arch/arm/include/asm/system.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 0eae857e73a..43f7503571d 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -513,14 +513,6 @@ enum dcache_option { }; #endif
-#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) -#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH -#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) -#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC -#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK) -#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK -#endif
- /* Size of an MMU section */ enum { #ifdef CONFIG_ARMV7_LPAE
@@ -578,6 +570,14 @@ void psci_system_reset(void);
#endif /* CONFIG_ARM64 */
+#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK +#endif
- #ifndef __ASSEMBLY__ /**
- save_boot_params() - Save boot parameters before starting reset sequence
Reviewed-by: Patrick Delaunay patrick.delaunay@foss.st.com
Thanks Patrick
On 11/9/23 10:11, Patrick DELAUNAY wrote:
Hi,
On 10/27/23 16:42, Patrice Chotard wrote:
This fixes the following compilation error in ARM64: arch/arm/mach-stm32mp/dram_init.c: In function ‘board_get_usable_ram_top’: arch/arm/mach-stm32mp/dram_init.c:59:45: error: ‘DCACHE_DEFAULT_OPTION’ undeclared (first use in this function) 59 | mmu_set_region_dcache_behaviour(reg, size, DCACHE_DEFAULT_OPTION); | ^~~~~~~~~~~~~~~~~~~~~
Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com
arch/arm/include/asm/system.h | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/arch/arm/include/asm/system.h b/arch/arm/include/asm/system.h index 0eae857e73a..43f7503571d 100644 --- a/arch/arm/include/asm/system.h +++ b/arch/arm/include/asm/system.h @@ -513,14 +513,6 @@ enum dcache_option { }; #endif -#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) -#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH -#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) -#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC -#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK) -#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK -#endif
/* Size of an MMU section */ enum { #ifdef CONFIG_ARMV7_LPAE @@ -578,6 +570,14 @@ void psci_system_reset(void); #endif /* CONFIG_ARM64 */ +#if defined(CONFIG_SYS_ARM_CACHE_WRITETHROUGH) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITETHROUGH +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEALLOC) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITEALLOC +#elif defined(CONFIG_SYS_ARM_CACHE_WRITEBACK) +#define DCACHE_DEFAULT_OPTION DCACHE_WRITEBACK +#endif
#ifndef __ASSEMBLY__ /** * save_boot_params() - Save boot parameters before starting reset sequence
Reviewed-by: Patrick Delaunay patrick.delaunay@foss.st.com
Thanks Patrick
Applied to u-boot-stm32/next
Thanks Patrice
From: Patrice Chotard patrice.chotard@st.com
In case there is no RAM driver retrieve RAM size from DT as fallback.
Signed-off-by: Patrice Chotard patrice.chotard@st.com Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com ---
arch/arm/mach-stm32mp/dram_init.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index 7f37b0d2aa2..a1e77a42e4f 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -24,8 +24,11 @@ int dram_init(void) int ret;
ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - log_debug("RAM init failed: %d\n", ret); + /* in case there is no RAM driver, retrieve DDR size from DT */ + if (ret == -ENODEV) { + return fdtdec_setup_mem_size_base(); + } else if (ret) { + log_err("RAM init failed: %d\n", ret); return ret; } ret = ram_get_info(dev, &ram);
Hi,
On 10/27/23 16:42, Patrice Chotard wrote:
From: Patrice Chotard patrice.chotard@st.com
In case there is no RAM driver retrieve RAM size from DT as fallback.
Signed-off-by: Patrice Chotard patrice.chotard@st.com Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com
arch/arm/mach-stm32mp/dram_init.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index 7f37b0d2aa2..a1e77a42e4f 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -24,8 +24,11 @@ int dram_init(void) int ret;
ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret) {
log_debug("RAM init failed: %d\n", ret);
- /* in case there is no RAM driver, retrieve DDR size from DT */
- if (ret == -ENODEV) {
return fdtdec_setup_mem_size_base();- } else if (ret) {
log_err("RAM init failed: %d\n", ret);
Reviewed-by: Patrick Delaunay patrick.delaunay@foss.st.com
Thanks Patrick
On 11/9/23 10:11, Patrick DELAUNAY wrote:
Hi,
On 10/27/23 16:42, Patrice Chotard wrote:
From: Patrice Chotard patrice.chotard@st.com
In case there is no RAM driver retrieve RAM size from DT as fallback.
Signed-off-by: Patrice Chotard patrice.chotard@st.com Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com
arch/arm/mach-stm32mp/dram_init.c | 7 +++++-- 1 file changed, 5 insertions(+), 2 deletions(-)
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index 7f37b0d2aa2..a1e77a42e4f 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -24,8 +24,11 @@ int dram_init(void) int ret; ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) { - log_debug("RAM init failed: %d\n", ret); + /* in case there is no RAM driver, retrieve DDR size from DT */ + if (ret == -ENODEV) { + return fdtdec_setup_mem_size_base(); + } else if (ret) { + log_err("RAM init failed: %d\n", ret); return ret; } ret = ram_get_info(dev, &ram);
Reviewed-by: Patrick Delaunay patrick.delaunay@foss.st.com
Thanks Patrick
Applied to u-boot-stm32/next
Thanks Patrice
From: Patrick Delaunay patrick.delaunay@foss.st.com
When building with AARCH64 defconfig, we got warnings for debug message - format '%x' expects argument of type 'unsigned int', but argument 3 has type 'size_t' {aka 'long unsigned int'}). - format '%lx' expects argument of type 'long unsigned int', but argument 2 has type 'phys_addr_t' {aka 'long long unsigned int'}
Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com ---
arch/arm/mach-stm32mp/dram_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index a1e77a42e4f..cb35ed60ca1 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -36,7 +36,7 @@ int dram_init(void) log_debug("Cannot get RAM size: %d\n", ret); return ret; } - log_debug("RAM init base=%lx, size=%x\n", ram.base, ram.size); + log_debug("RAM init base=%p, size=%zx\n", (void *)ram.base, ram.size);
gd->ram_size = ram.size;
Hi,
On 10/27/23 16:42, Patrice Chotard wrote:
From: Patrick Delaunay patrick.delaunay@foss.st.com
When building with AARCH64 defconfig, we got warnings for debug message
- format '%x' expects argument of type 'unsigned int', but argument 3 has type 'size_t' {aka 'long unsigned int'}).
- format '%lx' expects argument of type 'long unsigned int', but argument 2 has type 'phys_addr_t' {aka 'long long unsigned int'}
Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com
arch/arm/mach-stm32mp/dram_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index a1e77a42e4f..cb35ed60ca1 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -36,7 +36,7 @@ int dram_init(void) log_debug("Cannot get RAM size: %d\n", ret); return ret; }
- log_debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
log_debug("RAM init base=%p, size=%zx\n", (void *)ram.base, ram.size);
gd->ram_size = ram.size;
Reviewed-by: Patrick Delaunay patrick.delaunay@foss.st.com
Thanks Patrick
On 11/9/23 10:13, Patrick DELAUNAY wrote:
Hi,
On 10/27/23 16:42, Patrice Chotard wrote:
From: Patrick Delaunay patrick.delaunay@foss.st.com
When building with AARCH64 defconfig, we got warnings for debug message
- format '%x' expects argument of type 'unsigned int',
but argument 3 has type 'size_t' {aka 'long unsigned int'}).
- format '%lx' expects argument of type 'long unsigned int',
but argument 2 has type 'phys_addr_t' {aka 'long long unsigned int'}
Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com
arch/arm/mach-stm32mp/dram_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index a1e77a42e4f..cb35ed60ca1 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -36,7 +36,7 @@ int dram_init(void) log_debug("Cannot get RAM size: %d\n", ret); return ret; } - log_debug("RAM init base=%lx, size=%x\n", ram.base, ram.size); + log_debug("RAM init base=%p, size=%zx\n", (void *)ram.base, ram.size); gd->ram_size = ram.size;
Reviewed-by: Patrick Delaunay patrick.delaunay@foss.st.com
Thanks Patrick
Applied to u-boot-stm32/next
Thanks Patrice
On 10/27/23 16:42, Patrice Chotard wrote:
From: Patrick Delaunay patrick.delaunay@foss.st.com
When building with AARCH64 defconfig, we got warnings for debug message
- format '%x' expects argument of type 'unsigned int', but argument 3 has type 'size_t' {aka 'long unsigned int'}).
- format '%lx' expects argument of type 'long unsigned int', but argument 2 has type 'phys_addr_t' {aka 'long long unsigned int'}
Signed-off-by: Patrick Delaunay patrick.delaunay@foss.st.com Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com
arch/arm/mach-stm32mp/dram_init.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index a1e77a42e4f..cb35ed60ca1 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -36,7 +36,7 @@ int dram_init(void) log_debug("Cannot get RAM size: %d\n", ret); return ret; }
- log_debug("RAM init base=%lx, size=%x\n", ram.base, ram.size);
log_debug("RAM init base=%p, size=%zx\n", (void *)ram.base, ram.size);
gd->ram_size = ram.size;
Applied to u-boot-stm32/next
Thanks Patrice
Limit DDR usage under 4GB boundary on STM32MP regardless of memory size declared in device tree.
Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com ---
arch/arm/mach-stm32mp/dram_init.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index cb35ed60ca1..fb1208fc5d5 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -52,9 +52,15 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) if (!total_size) return gd->ram_top;
+ /* + * make sure U-Boot uses address space below 4GB boundaries even + * if the effective available memory is bigger + */ + gd->ram_top = clamp_val(gd->ram_top, 0, SZ_4G - 1); + /* found enough not-reserved memory to relocated U-Boot */ lmb_init(&lmb); - lmb_add(&lmb, gd->ram_base, get_effective_memsize()); + lmb_add(&lmb, gd->ram_base, gd->ram_top - gd->ram_base); boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob); /* add 8M for reserved memory for display, fdt, gd,... */ size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE),
Hi,
On 10/27/23 16:42, Patrice Chotard wrote:
Limit DDR usage under 4GB boundary on STM32MP regardless of memory size declared in device tree.
Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com
arch/arm/mach-stm32mp/dram_init.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index cb35ed60ca1..fb1208fc5d5 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -52,9 +52,15 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) if (!total_size) return gd->ram_top;
- /*
* make sure U-Boot uses address space below 4GB boundaries even* if the effective available memory is bigger*/- gd->ram_top = clamp_val(gd->ram_top, 0, SZ_4G - 1);
- /* found enough not-reserved memory to relocated U-Boot */ lmb_init(&lmb);
- lmb_add(&lmb, gd->ram_base, get_effective_memsize());
- lmb_add(&lmb, gd->ram_base, gd->ram_top - gd->ram_base); boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob); /* add 8M for reserved memory for display, fdt, gd,... */ size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE),
Reviewed-by: Patrick Delaunay patrick.delaunay@foss.st.com
Thanks Patrick
On 11/9/23 10:13, Patrick DELAUNAY wrote:
Hi,
On 10/27/23 16:42, Patrice Chotard wrote:
Limit DDR usage under 4GB boundary on STM32MP regardless of memory size declared in device tree.
Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com
arch/arm/mach-stm32mp/dram_init.c | 8 +++++++- 1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/arm/mach-stm32mp/dram_init.c b/arch/arm/mach-stm32mp/dram_init.c index cb35ed60ca1..fb1208fc5d5 100644 --- a/arch/arm/mach-stm32mp/dram_init.c +++ b/arch/arm/mach-stm32mp/dram_init.c @@ -52,9 +52,15 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) if (!total_size) return gd->ram_top; + /* + * make sure U-Boot uses address space below 4GB boundaries even + * if the effective available memory is bigger + */ + gd->ram_top = clamp_val(gd->ram_top, 0, SZ_4G - 1);
/* found enough not-reserved memory to relocated U-Boot */ lmb_init(&lmb); - lmb_add(&lmb, gd->ram_base, get_effective_memsize()); + lmb_add(&lmb, gd->ram_base, gd->ram_top - gd->ram_base); boot_fdt_add_mem_rsv_regions(&lmb, (void *)gd->fdt_blob); /* add 8M for reserved memory for display, fdt, gd,... */ size = ALIGN(SZ_8M + CONFIG_SYS_MALLOC_LEN + total_size, MMU_SECTION_SIZE),
Reviewed-by: Patrick Delaunay patrick.delaunay@foss.st.com
Thanks Patrick
Applied to u-boot-stm32/next
Thanks Patrice
When building with AARCH64 defconfig, we got warnings, fix them.
Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com ---
arch/arm/mach-stm32mp/bsec.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-)
diff --git a/arch/arm/mach-stm32mp/bsec.c b/arch/arm/mach-stm32mp/bsec.c index 599e63a93dd..28a8280b280 100644 --- a/arch/arm/mach-stm32mp/bsec.c +++ b/arch/arm/mach-stm32mp/bsec.c @@ -110,7 +110,7 @@ * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: true if locked else false */ -static bool bsec_read_lock(u32 address, u32 otp) +static bool bsec_read_lock(void __iomem *address, u32 otp) { u32 bit; u32 bank; @@ -118,7 +118,7 @@ static bool bsec_read_lock(u32 address, u32 otp) bit = 1 << (otp & OTP_LOCK_MASK); bank = ((otp >> OTP_LOCK_BANK_SHIFT) & OTP_LOCK_MASK) * sizeof(u32);
- return !!(readl(address + bank) & bit); + return !!(readl((address + bank)) & bit); }
/** @@ -127,7 +127,7 @@ static bool bsec_read_lock(u32 address, u32 otp) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: 0 if no error, -EAGAIN or -ENOTSUPP */ -static u32 bsec_check_error(u32 base, u32 otp) +static u32 bsec_check_error(void __iomem *base, u32 otp) { u32 bit; u32 bank; @@ -149,7 +149,7 @@ static u32 bsec_check_error(u32 base, u32 otp) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: true if locked else false */ -static bool bsec_read_SR_lock(u32 base, u32 otp) +static bool bsec_read_SR_lock(void __iomem *base, u32 otp) { return bsec_read_lock(base + BSEC_SRLOCK_OFF, otp); } @@ -160,7 +160,7 @@ static bool bsec_read_SR_lock(u32 base, u32 otp) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: true if locked else false */ -static bool bsec_read_SP_lock(u32 base, u32 otp) +static bool bsec_read_SP_lock(void __iomem *base, u32 otp) { return bsec_read_lock(base + BSEC_SPLOCK_OFF, otp); } @@ -171,7 +171,7 @@ static bool bsec_read_SP_lock(u32 base, u32 otp) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: true if locked else false */ -static bool bsec_read_SW_lock(u32 base, u32 otp) +static bool bsec_read_SW_lock(void __iomem *base, u32 otp) { return bsec_read_lock(base + BSEC_SWLOCK_OFF, otp); } @@ -182,7 +182,7 @@ static bool bsec_read_SW_lock(u32 base, u32 otp) * @power: true to power up , false to power down * Return: 0 if succeed */ -static int bsec_power_safmem(u32 base, bool power) +static int bsec_power_safmem(void __iomem *base, bool power) { u32 val; u32 mask; @@ -208,7 +208,7 @@ static int bsec_power_safmem(u32 base, bool power) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: 0 if no error */ -static int bsec_shadow_register(struct udevice *dev, u32 base, u32 otp) +static int bsec_shadow_register(struct udevice *dev, void __iomem *base, u32 otp) { u32 val; int ret; @@ -253,7 +253,8 @@ static int bsec_shadow_register(struct udevice *dev, u32 base, u32 otp) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: 0 if no error */ -static int bsec_read_shadow(struct udevice *dev, u32 base, u32 *val, u32 otp) +static int bsec_read_shadow(struct udevice *dev, void __iomem *base, u32 *val, + u32 otp) { *val = readl(base + BSEC_OTP_DATA_OFF + otp * sizeof(u32));
@@ -268,7 +269,7 @@ static int bsec_read_shadow(struct udevice *dev, u32 base, u32 *val, u32 otp) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: 0 if no error */ -static int bsec_write_shadow(struct udevice *dev, u32 base, u32 val, u32 otp) +static int bsec_write_shadow(struct udevice *dev, void __iomem *base, u32 val, u32 otp) { /* check if programming of otp is locked */ if (bsec_read_SW_lock(base, otp)) @@ -288,7 +289,7 @@ static int bsec_write_shadow(struct udevice *dev, u32 base, u32 val, u32 otp) * after the function the otp data is not refreshed in shadow * Return: 0 if no error */ -static int bsec_program_otp(struct udevice *dev, long base, u32 val, u32 otp) +static int bsec_program_otp(struct udevice *dev, void __iomem *base, u32 val, u32 otp) { u32 ret; bool power_up = false; @@ -338,7 +339,7 @@ static int bsec_program_otp(struct udevice *dev, long base, u32 val, u32 otp) * @otp: otp number (0 - BSEC_OTP_MAX_VALUE) * Return: 0 if no error */ -static int bsec_permanent_lock_otp(struct udevice *dev, long base, uint32_t otp) +static int bsec_permanent_lock_otp(struct udevice *dev, void __iomem *base, uint32_t otp) { int ret; bool power_up = false; @@ -392,7 +393,7 @@ static int bsec_permanent_lock_otp(struct udevice *dev, long base, uint32_t otp)
/* BSEC MISC driver *******************************************************/ struct stm32mp_bsec_plat { - u32 base; + void __iomem *base; };
struct stm32mp_bsec_priv { @@ -724,7 +725,7 @@ static int stm32mp_bsec_of_to_plat(struct udevice *dev) { struct stm32mp_bsec_plat *plat = dev_get_plat(dev);
- plat->base = (u32)dev_read_addr_ptr(dev); + plat->base = dev_read_addr_ptr(dev);
return 0; }
Hi,
On 10/27/23 16:43, Patrice Chotard wrote:
When building with AARCH64 defconfig, we got warnings, fix them.
Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com
arch/arm/mach-stm32mp/bsec.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-)
Reviewed-by: Patrick Delaunay patrick.delaunay@foss.st.com
Thanks Patrick
On 11/9/23 10:14, Patrick DELAUNAY wrote:
Hi,
On 10/27/23 16:43, Patrice Chotard wrote:
When building with AARCH64 defconfig, we got warnings, fix them.
Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com
arch/arm/mach-stm32mp/bsec.c | 29 +++++++++++++++-------------- 1 file changed, 15 insertions(+), 14 deletions(-)
Reviewed-by: Patrick Delaunay patrick.delaunay@foss.st.com
Thanks Patrick
Applied to u-boot-stm32/next
Thanks Patrice
From: Patrice Chotard patrice.chotard@st.com
When building with AARCH64 defconfig, we got warnings, fix them by using registers base address defined as void __iomem * instead of fdt_addr_t.
Signed-off-by: Patrice Chotard patrice.chotard@st.com Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com ---
drivers/serial/serial_stm32.c | 23 +++++++++++++---------- drivers/serial/serial_stm32.h | 2 +- 2 files changed, 14 insertions(+), 11 deletions(-)
diff --git a/drivers/serial/serial_stm32.c b/drivers/serial/serial_stm32.c index 23d476fba28..fb039546a41 100644 --- a/drivers/serial/serial_stm32.c +++ b/drivers/serial/serial_stm32.c @@ -30,7 +30,7 @@ */ #define ONE_BYTE_B115200_US 87
-static void _stm32_serial_setbrg(fdt_addr_t base, +static void _stm32_serial_setbrg(void __iomem *base, struct stm32_uart_info *uart_info, u32 clock_rate, int baudrate) @@ -75,7 +75,7 @@ static int stm32_serial_setconfig(struct udevice *dev, uint serial_config) struct stm32x7_serial_plat *plat = dev_get_plat(dev); bool stm32f4 = plat->uart_info->stm32f4; u8 uart_enable_bit = plat->uart_info->uart_enable_bit; - u32 cr1 = plat->base + CR1_OFFSET(stm32f4); + void __iomem *cr1 = plat->base + CR1_OFFSET(stm32f4); u32 config = 0; uint parity = SERIAL_GET_PARITY(serial_config); uint bits = SERIAL_GET_BITS(serial_config); @@ -122,7 +122,7 @@ static int stm32_serial_getc(struct udevice *dev) { struct stm32x7_serial_plat *plat = dev_get_plat(dev); bool stm32f4 = plat->uart_info->stm32f4; - fdt_addr_t base = plat->base; + void __iomem *base = plat->base; u32 isr = readl(base + ISR_OFFSET(stm32f4));
if ((isr & USART_ISR_RXNE) == 0) @@ -141,7 +141,7 @@ static int stm32_serial_getc(struct udevice *dev) return readl(base + RDR_OFFSET(stm32f4)); }
-static int _stm32_serial_putc(fdt_addr_t base, +static int _stm32_serial_putc(void __iomem *base, struct stm32_uart_info *uart_info, const char c) { @@ -166,7 +166,7 @@ static int stm32_serial_pending(struct udevice *dev, bool input) { struct stm32x7_serial_plat *plat = dev_get_plat(dev); bool stm32f4 = plat->uart_info->stm32f4; - fdt_addr_t base = plat->base; + void __iomem *base = plat->base;
if (input) return readl(base + ISR_OFFSET(stm32f4)) & @@ -176,7 +176,7 @@ static int stm32_serial_pending(struct udevice *dev, bool input) USART_ISR_TXE ? 0 : 1; }
-static void _stm32_serial_init(fdt_addr_t base, +static void _stm32_serial_init(void __iomem *base, struct stm32_uart_info *uart_info) { bool stm32f4 = uart_info->stm32f4; @@ -250,11 +250,14 @@ static const struct udevice_id stm32_serial_id[] = { static int stm32_serial_of_to_plat(struct udevice *dev) { struct stm32x7_serial_plat *plat = dev_get_plat(dev); + fdt_addr_t addr;
- plat->base = dev_read_addr(dev); - if (plat->base == FDT_ADDR_T_NONE) + addr = dev_read_addr(dev); + if (addr == FDT_ADDR_T_NONE) return -EINVAL;
+ plat->base = (void __iomem *)addr; + return 0; }
@@ -297,7 +300,7 @@ static inline struct stm32_uart_info *_debug_uart_info(void)
static inline void _debug_uart_init(void) { - fdt_addr_t base = CONFIG_VAL(DEBUG_UART_BASE); + void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); struct stm32_uart_info *uart_info = _debug_uart_info();
_stm32_serial_init(base, uart_info); @@ -308,7 +311,7 @@ static inline void _debug_uart_init(void)
static inline void _debug_uart_putc(int c) { - fdt_addr_t base = CONFIG_VAL(DEBUG_UART_BASE); + void __iomem *base = (void __iomem *)CONFIG_VAL(DEBUG_UART_BASE); struct stm32_uart_info *uart_info = _debug_uart_info();
while (_stm32_serial_putc(base, uart_info, c) == -EAGAIN) diff --git a/drivers/serial/serial_stm32.h b/drivers/serial/serial_stm32.h index b7e7a90b931..d2c92ba48ea 100644 --- a/drivers/serial/serial_stm32.h +++ b/drivers/serial/serial_stm32.h @@ -49,7 +49,7 @@ struct stm32_uart_info stm32h7_info = {
/* Information about a serial port */ struct stm32x7_serial_plat { - fdt_addr_t base; /* address of registers in physical memory */ + void __iomem *base; /* address of registers in physical memory */ struct stm32_uart_info *uart_info; unsigned long int clock_rate; };
Hi,
On 10/27/23 16:43, Patrice Chotard wrote:
From: Patrice Chotard patrice.chotard@st.com
When building with AARCH64 defconfig, we got warnings, fix them by using registers base address defined as void __iomem * instead of fdt_addr_t.
Signed-off-by: Patrice Chotard patrice.chotard@st.com Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com
drivers/serial/serial_stm32.c | 23 +++++++++++++---------- drivers/serial/serial_stm32.h | 2 +- 2 files changed, 14 insertions(+), 11 deletions(-)
Reviewed-by: Patrick Delaunay patrick.delaunay@foss.st.com
Thanks Patrick
On 11/9/23 10:15, Patrick DELAUNAY wrote:
Hi,
On 10/27/23 16:43, Patrice Chotard wrote:
From: Patrice Chotard patrice.chotard@st.com
When building with AARCH64 defconfig, we got warnings, fix them by using registers base address defined as void __iomem * instead of fdt_addr_t.
Signed-off-by: Patrice Chotard patrice.chotard@st.com Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com
drivers/serial/serial_stm32.c | 23 +++++++++++++---------- drivers/serial/serial_stm32.h | 2 +- 2 files changed, 14 insertions(+), 11 deletions(-)
Reviewed-by: Patrick Delaunay patrick.delaunay@foss.st.com
Thanks Patrick
Applied to u-boot-stm32/next
Thanks Patrice
Add stm32mp2 compatible.
Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com ---
drivers/pinctrl/pinctrl_stm32.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 8bb7588714a..7120b8edba0 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -505,6 +505,8 @@ static const struct udevice_id stm32_pinctrl_ids[] = { { .compatible = "st,stm32mp157-pinctrl" }, { .compatible = "st,stm32mp157-z-pinctrl" }, { .compatible = "st,stm32mp135-pinctrl" }, + { .compatible = "st,stm32mp257-pinctrl" }, + { .compatible = "st,stm32mp257-z-pinctrl" }, { } };
Hi,
On 10/27/23 16:43, Patrice Chotard wrote:
Add stm32mp2 compatible.
Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com
drivers/pinctrl/pinctrl_stm32.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 8bb7588714a..7120b8edba0 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -505,6 +505,8 @@ static const struct udevice_id stm32_pinctrl_ids[] = { { .compatible = "st,stm32mp157-pinctrl" }, { .compatible = "st,stm32mp157-z-pinctrl" }, { .compatible = "st,stm32mp135-pinctrl" },
- { .compatible = "st,stm32mp257-pinctrl" },
- { .compatible = "st,stm32mp257-z-pinctrl" }, { } };
Reviewed-by: Patrick Delaunay patrick.delaunay@foss.st.com
Thanks Patrick
On 11/9/23 10:16, Patrick DELAUNAY wrote:
Hi,
On 10/27/23 16:43, Patrice Chotard wrote:
Add stm32mp2 compatible.
Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com
drivers/pinctrl/pinctrl_stm32.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/drivers/pinctrl/pinctrl_stm32.c b/drivers/pinctrl/pinctrl_stm32.c index 8bb7588714a..7120b8edba0 100644 --- a/drivers/pinctrl/pinctrl_stm32.c +++ b/drivers/pinctrl/pinctrl_stm32.c @@ -505,6 +505,8 @@ static const struct udevice_id stm32_pinctrl_ids[] = { { .compatible = "st,stm32mp157-pinctrl" }, { .compatible = "st,stm32mp157-z-pinctrl" }, { .compatible = "st,stm32mp135-pinctrl" }, + { .compatible = "st,stm32mp257-pinctrl" }, + { .compatible = "st,stm32mp257-z-pinctrl" }, { } };
Reviewed-by: Patrick Delaunay patrick.delaunay@foss.st.com
Thanks Patrick
Applied to u-boot-stm32/next
Thanks Patrice
Add STM32MP257F Evaluation board support. It embeds a STM32MP257FAI SoC, with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA, 1*USB2 typeC, SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...
Sync device tree with kernel v6.6-rc1.
Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com ---
arch/arm/dts/Makefile | 3 + arch/arm/dts/stm32mp25-pinctrl.dtsi | 38 +++ arch/arm/dts/stm32mp25-u-boot.dtsi | 102 +++++++ arch/arm/dts/stm32mp251.dtsi | 285 ++++++++++++++++++++ arch/arm/dts/stm32mp253.dtsi | 23 ++ arch/arm/dts/stm32mp255.dtsi | 9 + arch/arm/dts/stm32mp257.dtsi | 9 + arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi | 20 ++ arch/arm/dts/stm32mp257f-ev1.dts | 55 ++++ arch/arm/dts/stm32mp25xc.dtsi | 8 + arch/arm/dts/stm32mp25xf.dtsi | 8 + arch/arm/dts/stm32mp25xxai-pinctrl.dtsi | 83 ++++++ arch/arm/dts/stm32mp25xxak-pinctrl.dtsi | 71 +++++ arch/arm/dts/stm32mp25xxal-pinctrl.dtsi | 71 +++++ include/dt-bindings/pinctrl/stm32-pinfunc.h | 3 + 15 files changed, 788 insertions(+) create mode 100644 arch/arm/dts/stm32mp25-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32mp25-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp251.dtsi create mode 100644 arch/arm/dts/stm32mp253.dtsi create mode 100644 arch/arm/dts/stm32mp255.dtsi create mode 100644 arch/arm/dts/stm32mp257.dtsi create mode 100644 arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp257f-ev1.dts create mode 100644 arch/arm/dts/stm32mp25xc.dtsi create mode 100644 arch/arm/dts/stm32mp25xf.dtsi create mode 100644 arch/arm/dts/stm32mp25xxai-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32mp25xxak-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32mp25xxal-pinctrl.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 96066a2b6b8..387e9f30378 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1348,6 +1348,9 @@ dtb-$(CONFIG_STM32MP15x) += \ stm32mp15xx-dhcor-drc-compact.dtb \ stm32mp15xx-dhcor-testbench.dtb
+dtb-$(CONFIG_STM32MP25X) += \ + stm32mp257f-ev1.dtb + dtb-$(CONFIG_SOC_K3_AM654) += \ k3-am654-base-board.dtb \ k3-am654-r5-base-board.dtb \ diff --git a/arch/arm/dts/stm32mp25-pinctrl.dtsi b/arch/arm/dts/stm32mp25-pinctrl.dtsi new file mode 100644 index 00000000000..d34a1d5e79c --- /dev/null +++ b/arch/arm/dts/stm32mp25-pinctrl.dtsi @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue alexandre.torgue@foss.st.com for STMicroelectronics. + */ +#include <dt-bindings/pinctrl/stm32-pinfunc.h> + +&pinctrl { + usart2_pins_a: usart2-0 { + pins1 { + pinmux = <STM32_PINMUX('A', 4, AF6)>; /* USART2_TX */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + pins2 { + pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_idle_pins_a: usart2-idle-0 { + pins1 { + pinmux = <STM32_PINMUX('A', 4, ANALOG)>; /* USART2_TX */ + }; + pins2 { + pinmux = <STM32_PINMUX('A', 8, AF8)>; /* USART2_RX */ + bias-disable; + }; + }; + + usart2_sleep_pins_a: usart2-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 4, ANALOG)>, /* USART2_TX */ + <STM32_PINMUX('A', 8, ANALOG)>; /* USART2_RX */ + }; + }; +}; diff --git a/arch/arm/dts/stm32mp25-u-boot.dtsi b/arch/arm/dts/stm32mp25-u-boot.dtsi new file mode 100644 index 00000000000..f4f26add2a4 --- /dev/null +++ b/arch/arm/dts/stm32mp25-u-boot.dtsi @@ -0,0 +1,102 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright : STMicroelectronics 2023 + */ + +/ { + aliases { + gpio0 = &gpioa; + gpio1 = &gpiob; + gpio2 = &gpioc; + gpio3 = &gpiod; + gpio4 = &gpioe; + gpio5 = &gpiof; + gpio6 = &gpiog; + gpio7 = &gpioh; + gpio8 = &gpioi; + gpio9 = &gpioj; + gpio10 = &gpiok; + gpio25 = &gpioz; + pinctrl0 = &pinctrl; + pinctrl1 = &pinctrl_z; + }; + + firmware { + optee { + bootph-all; + }; + }; + + /* need PSCI for sysreset during board_f */ + psci { + bootph-all; + }; + + soc@0 { + bootph-all; + }; +}; + +&gpioa { + bootph-all; +}; + +&gpiob { + bootph-all; +}; + +&gpioc { + bootph-all; +}; + +&gpiod { + bootph-all; +}; + +&gpioe { + bootph-all; +}; + +&gpiof { + bootph-all; +}; + +&gpiog { + bootph-all; +}; + +&gpioh { + bootph-all; +}; + +&gpioi { + bootph-all; +}; + +&gpioj { + bootph-all; +}; + +&gpiok { + bootph-all; +}; + +&gpioz { + bootph-all; +}; + +&pinctrl { + bootph-all; +}; + +&rifsc { + bootph-all; +}; + +&scmi_clk { + bootph-all; +}; + +&syscfg { + bootph-all; +}; diff --git a/arch/arm/dts/stm32mp251.dtsi b/arch/arm/dts/stm32mp251.dtsi new file mode 100644 index 00000000000..cf2f28dc158 --- /dev/null +++ b/arch/arm/dts/stm32mp251.dtsi @@ -0,0 +1,285 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue alexandre.torgue@foss.st.com for STMicroelectronics. + */ +#include <dt-bindings/interrupt-controller/arm-gic.h> + +/ { + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu0: cpu@0 { + compatible = "arm,cortex-a35"; + device_type = "cpu"; + reg = <0>; + enable-method = "psci"; + }; + }; + + arm-pmu { + compatible = "arm,cortex-a35-pmu"; + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>; + interrupt-parent = <&intc>; + }; + + arm_wdt: watchdog { + compatible = "arm,smc-wdt"; + arm,smc-id = <0xb200005a>; + status = "disabled"; + }; + + clocks { + ck_flexgen_08: ck-flexgen-08 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <100000000>; + }; + + ck_flexgen_51: ck-flexgen-51 { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + + ck_icn_ls_mcu: ck-icn-ls-mcu { + #clock-cells = <0>; + compatible = "fixed-clock"; + clock-frequency = <200000000>; + }; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + scmi { + compatible = "linaro,scmi-optee"; + #address-cells = <1>; + #size-cells = <0>; + linaro,optee-channel-id = <0>; + + scmi_clk: protocol@14 { + reg = <0x14>; + #clock-cells = <1>; + }; + + scmi_reset: protocol@16 { + reg = <0x16>; + #reset-cells = <1>; + }; + }; + }; + + intc: interrupt-controller@4ac00000 { + compatible = "arm,cortex-a7-gic"; + #interrupt-cells = <3>; + #address-cells = <1>; + interrupt-controller; + reg = <0x0 0x4ac10000 0x0 0x1000>, + <0x0 0x4ac20000 0x0 0x2000>, + <0x0 0x4ac40000 0x0 0x2000>, + <0x0 0x4ac60000 0x0 0x2000>; + }; + + psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + + timer { + compatible = "arm,armv8-timer"; + interrupt-parent = <&intc>; + interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 14 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 11 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>, + <GIC_PPI 10 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>; + always-on; + }; + + soc@0 { + compatible = "simple-bus"; + #address-cells = <1>; + #size-cells = <1>; + interrupt-parent = <&intc>; + ranges = <0x0 0x0 0x0 0x80000000>; + + rifsc: rifsc-bus@42080000 { + compatible = "simple-bus"; + reg = <0x42080000 0x1000>; + #address-cells = <1>; + #size-cells = <1>; + ranges; + + usart2: serial@400e0000 { + compatible = "st,stm32h7-uart"; + reg = <0x400e0000 0x400>; + interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&ck_flexgen_08>; + status = "disabled"; + }; + }; + + syscfg: syscon@44230000 { + compatible = "st,stm32mp25-syscfg", "syscon"; + reg = <0x44230000 0x10000>; + }; + + pinctrl: pinctrl@44240000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp257-pinctrl"; + ranges = <0 0x44240000 0xa0400>; + pins-are-numbered; + + gpioa: gpio@44240000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x0 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOA"; + status = "disabled"; + }; + + gpiob: gpio@44250000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x10000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOB"; + status = "disabled"; + }; + + gpioc: gpio@44260000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x20000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOC"; + status = "disabled"; + }; + + gpiod: gpio@44270000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x30000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOD"; + status = "disabled"; + }; + + gpioe: gpio@44280000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x40000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOE"; + status = "disabled"; + }; + + gpiof: gpio@44290000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x50000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOF"; + status = "disabled"; + }; + + gpiog: gpio@442a0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x60000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOG"; + status = "disabled"; + }; + + gpioh: gpio@442b0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x70000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOH"; + status = "disabled"; + }; + + gpioi: gpio@442c0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x80000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOI"; + status = "disabled"; + }; + + gpioj: gpio@442d0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0x90000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOJ"; + status = "disabled"; + }; + + gpiok: gpio@442e0000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0xa0000 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOK"; + status = "disabled"; + }; + }; + + pinctrl_z: pinctrl@46200000 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "st,stm32mp257-z-pinctrl"; + ranges = <0 0x46200000 0x400>; + pins-are-numbered; + + gpioz: gpio@46200000 { + gpio-controller; + #gpio-cells = <2>; + interrupt-controller; + #interrupt-cells = <2>; + reg = <0 0x400>; + clocks = <&ck_icn_ls_mcu>; + st,bank-name = "GPIOZ"; + st,bank-ioport = <11>; + status = "disabled"; + }; + + }; + }; +}; diff --git a/arch/arm/dts/stm32mp253.dtsi b/arch/arm/dts/stm32mp253.dtsi new file mode 100644 index 00000000000..af48e82efe8 --- /dev/null +++ b/arch/arm/dts/stm32mp253.dtsi @@ -0,0 +1,23 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue alexandre.torgue@foss.st.com for STMicroelectronics. + */ +#include "stm32mp251.dtsi" + +/ { + cpus { + cpu1: cpu@1 { + compatible = "arm,cortex-a35"; + device_type = "cpu"; + reg = <1>; + enable-method = "psci"; + }; + }; + + arm-pmu { + interrupts = <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH>; + interrupt-affinity = <&cpu0>, <&cpu1>; + }; +}; diff --git a/arch/arm/dts/stm32mp255.dtsi b/arch/arm/dts/stm32mp255.dtsi new file mode 100644 index 00000000000..e6fa596211f --- /dev/null +++ b/arch/arm/dts/stm32mp255.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue alexandre.torgue@foss.st.com for STMicroelectronics. + */ +#include "stm32mp253.dtsi" + +/ { +}; diff --git a/arch/arm/dts/stm32mp257.dtsi b/arch/arm/dts/stm32mp257.dtsi new file mode 100644 index 00000000000..5c5000d3d9d --- /dev/null +++ b/arch/arm/dts/stm32mp257.dtsi @@ -0,0 +1,9 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue alexandre.torgue@foss.st.com for STMicroelectronics. + */ +#include "stm32mp255.dtsi" + +/ { +}; diff --git a/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi new file mode 100644 index 00000000000..a35a9b90388 --- /dev/null +++ b/arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi @@ -0,0 +1,20 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + */ + +#include "stm32mp25-u-boot.dtsi" + +&usart2 { + bootph-all; +}; + +&usart2_pins_a { + bootph-all; + pins1 { + bootph-all; + }; + pins2 { + bootph-all; + }; +}; diff --git a/arch/arm/dts/stm32mp257f-ev1.dts b/arch/arm/dts/stm32mp257f-ev1.dts new file mode 100644 index 00000000000..a88494eed34 --- /dev/null +++ b/arch/arm/dts/stm32mp257f-ev1.dts @@ -0,0 +1,55 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue alexandre.torgue@foss.st.com for STMicroelectronics. + */ + +/dts-v1/; + +#include "stm32mp257.dtsi" +#include "stm32mp25xf.dtsi" +#include "stm32mp25-pinctrl.dtsi" +#include "stm32mp25xxai-pinctrl.dtsi" + +/ { + model = "STMicroelectronics STM32MP257F-EV1 Evaluation Board"; + compatible = "st,stm32mp257f-ev1", "st,stm32mp257"; + + aliases { + serial0 = &usart2; + }; + + chosen { + stdout-path = "serial0:115200n8"; + }; + + memory@80000000 { + device_type = "memory"; + reg = <0x0 0x80000000 0x1 0x0>; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + fw@80000000 { + compatible = "shared-dma-pool"; + reg = <0x0 0x80000000 0x0 0x4000000>; + no-map; + }; + }; +}; + +&arm_wdt { + timeout-sec = <32>; + status = "okay"; +}; + +&usart2 { + pinctrl-names = "default", "idle", "sleep"; + pinctrl-0 = <&usart2_pins_a>; + pinctrl-1 = <&usart2_idle_pins_a>; + pinctrl-2 = <&usart2_sleep_pins_a>; + status = "okay"; +}; diff --git a/arch/arm/dts/stm32mp25xc.dtsi b/arch/arm/dts/stm32mp25xc.dtsi new file mode 100644 index 00000000000..5e83a692648 --- /dev/null +++ b/arch/arm/dts/stm32mp25xc.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue alexandre.torgue@foss.st.com for STMicroelectronics. + */ + +/ { +}; diff --git a/arch/arm/dts/stm32mp25xf.dtsi b/arch/arm/dts/stm32mp25xf.dtsi new file mode 100644 index 00000000000..5e83a692648 --- /dev/null +++ b/arch/arm/dts/stm32mp25xf.dtsi @@ -0,0 +1,8 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue alexandre.torgue@foss.st.com for STMicroelectronics. + */ + +/ { +}; diff --git a/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi new file mode 100644 index 00000000000..abdbc7aebc7 --- /dev/null +++ b/arch/arm/dts/stm32mp25xxai-pinctrl.dtsi @@ -0,0 +1,83 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue alexandre.torgue@foss.st.com for STMicroelectronics. + */ + +&pinctrl { + st,package = <STM32MP_PKG_AI>; + + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 128 16>; + }; + + gpioj: gpio@442d0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 144 16>; + }; + + gpiok: gpio@442e0000 { + status = "okay"; + ngpios = <8>; + gpio-ranges = <&pinctrl 0 160 8>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +}; diff --git a/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi new file mode 100644 index 00000000000..2e0d4d349d1 --- /dev/null +++ b/arch/arm/dts/stm32mp25xxak-pinctrl.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue alexandre.torgue@foss.st.com for STMicroelectronics. + */ + +&pinctrl { + st,package = <STM32MP_PKG_AK>; + + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 0 128 12>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +}; diff --git a/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi b/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi new file mode 100644 index 00000000000..2406e972554 --- /dev/null +++ b/arch/arm/dts/stm32mp25xxal-pinctrl.dtsi @@ -0,0 +1,71 @@ +// SPDX-License-Identifier: (GPL-2.0-or-later OR BSD-3-Clause) +/* + * Copyright (C) STMicroelectronics 2023 - All Rights Reserved + * Author: Alexandre Torgue alexandre.torgue@foss.st.com for STMicroelectronics. + */ + +&pinctrl { + st,package = <STM32MP_PKG_AL>; + + gpioa: gpio@44240000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 0 16>; + }; + + gpiob: gpio@44250000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 16 16>; + }; + + gpioc: gpio@44260000 { + status = "okay"; + ngpios = <14>; + gpio-ranges = <&pinctrl 0 32 14>; + }; + + gpiod: gpio@44270000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 48 16>; + }; + + gpioe: gpio@44280000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 64 16>; + }; + + gpiof: gpio@44290000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 80 16>; + }; + + gpiog: gpio@442a0000 { + status = "okay"; + ngpios = <16>; + gpio-ranges = <&pinctrl 0 96 16>; + }; + + gpioh: gpio@442b0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 2 114 12>; + }; + + gpioi: gpio@442c0000 { + status = "okay"; + ngpios = <12>; + gpio-ranges = <&pinctrl 0 128 12>; + }; +}; + +&pinctrl_z { + gpioz: gpio@46200000 { + status = "okay"; + ngpios = <10>; + gpio-ranges = <&pinctrl_z 0 400 10>; + }; +}; diff --git a/include/dt-bindings/pinctrl/stm32-pinfunc.h b/include/dt-bindings/pinctrl/stm32-pinfunc.h index e6fb8ada3f4..28ad0235086 100644 --- a/include/dt-bindings/pinctrl/stm32-pinfunc.h +++ b/include/dt-bindings/pinctrl/stm32-pinfunc.h @@ -37,6 +37,9 @@ #define STM32MP_PKG_AB 0x2 #define STM32MP_PKG_AC 0x4 #define STM32MP_PKG_AD 0x8 +#define STM32MP_PKG_AI 0x100 +#define STM32MP_PKG_AK 0x400 +#define STM32MP_PKG_AL 0x800
#endif /* _DT_BINDINGS_STM32_PINFUNC_H */
Hi,
On 10/27/23 16:43, Patrice Chotard wrote:
Add STM32MP257F Evaluation board support. It embeds a STM32MP257FAI SoC, with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA, 1*USB2 typeC, SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...
Sync device tree with kernel v6.6-rc1.
Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com
arch/arm/dts/Makefile | 3 + arch/arm/dts/stm32mp25-pinctrl.dtsi | 38 +++ arch/arm/dts/stm32mp25-u-boot.dtsi | 102 +++++++ arch/arm/dts/stm32mp251.dtsi | 285 ++++++++++++++++++++ arch/arm/dts/stm32mp253.dtsi | 23 ++ arch/arm/dts/stm32mp255.dtsi | 9 + arch/arm/dts/stm32mp257.dtsi | 9 + arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi | 20 ++ arch/arm/dts/stm32mp257f-ev1.dts | 55 ++++ arch/arm/dts/stm32mp25xc.dtsi | 8 + arch/arm/dts/stm32mp25xf.dtsi | 8 + arch/arm/dts/stm32mp25xxai-pinctrl.dtsi | 83 ++++++ arch/arm/dts/stm32mp25xxak-pinctrl.dtsi | 71 +++++ arch/arm/dts/stm32mp25xxal-pinctrl.dtsi | 71 +++++ include/dt-bindings/pinctrl/stm32-pinfunc.h | 3 + 15 files changed, 788 insertions(+) create mode 100644 arch/arm/dts/stm32mp25-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32mp25-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp251.dtsi create mode 100644 arch/arm/dts/stm32mp253.dtsi create mode 100644 arch/arm/dts/stm32mp255.dtsi create mode 100644 arch/arm/dts/stm32mp257.dtsi create mode 100644 arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp257f-ev1.dts create mode 100644 arch/arm/dts/stm32mp25xc.dtsi create mode 100644 arch/arm/dts/stm32mp25xf.dtsi create mode 100644 arch/arm/dts/stm32mp25xxai-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32mp25xxak-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32mp25xxal-pinctrl.dtsi
Reviewed-by: Patrick Delaunay patrick.delaunay@foss.st.com
Thanks Patrick
On 11/9/23 10:17, Patrick DELAUNAY wrote:
Hi,
On 10/27/23 16:43, Patrice Chotard wrote:
Add STM32MP257F Evaluation board support. It embeds a STM32MP257FAI SoC, with 4GB of DDR4, TSN switch (2+1 ports), 2*USB typeA, 1*USB2 typeC, SNOR OctoSPI, mini PCIe, STPMIC2 for power distribution ...
Sync device tree with kernel v6.6-rc1.
Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com
arch/arm/dts/Makefile | 3 + arch/arm/dts/stm32mp25-pinctrl.dtsi | 38 +++ arch/arm/dts/stm32mp25-u-boot.dtsi | 102 +++++++ arch/arm/dts/stm32mp251.dtsi | 285 ++++++++++++++++++++ arch/arm/dts/stm32mp253.dtsi | 23 ++ arch/arm/dts/stm32mp255.dtsi | 9 + arch/arm/dts/stm32mp257.dtsi | 9 + arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi | 20 ++ arch/arm/dts/stm32mp257f-ev1.dts | 55 ++++ arch/arm/dts/stm32mp25xc.dtsi | 8 + arch/arm/dts/stm32mp25xf.dtsi | 8 + arch/arm/dts/stm32mp25xxai-pinctrl.dtsi | 83 ++++++ arch/arm/dts/stm32mp25xxak-pinctrl.dtsi | 71 +++++ arch/arm/dts/stm32mp25xxal-pinctrl.dtsi | 71 +++++ include/dt-bindings/pinctrl/stm32-pinfunc.h | 3 + 15 files changed, 788 insertions(+) create mode 100644 arch/arm/dts/stm32mp25-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32mp25-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp251.dtsi create mode 100644 arch/arm/dts/stm32mp253.dtsi create mode 100644 arch/arm/dts/stm32mp255.dtsi create mode 100644 arch/arm/dts/stm32mp257.dtsi create mode 100644 arch/arm/dts/stm32mp257f-ev1-u-boot.dtsi create mode 100644 arch/arm/dts/stm32mp257f-ev1.dts create mode 100644 arch/arm/dts/stm32mp25xc.dtsi create mode 100644 arch/arm/dts/stm32mp25xf.dtsi create mode 100644 arch/arm/dts/stm32mp25xxai-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32mp25xxak-pinctrl.dtsi create mode 100644 arch/arm/dts/stm32mp25xxal-pinctrl.dtsi
Reviewed-by: Patrick Delaunay patrick.delaunay@foss.st.com
Thanks Patrick
Applied to u-boot-stm32/next
Thanks Patrice
Add initial support for STM32MP2 SoCs family.
SoCs information are available here : https://www.st.com/content/st_com/en/campaigns/microprocessor-stm32mp2.html
Migrate all MP1 related code into stm32mp1/ directory Create stm32mp2 directory dedicated for STM32MP2 SoCs.
Common code to MP1, MP13 and MP25 is kept into arch/arm/mach-stm32/mach-stm32mp directory : - boot_params.c - bsec - cmd_stm32key - cmd_stm32prog - dram_init.c - syscon.c - ecdsa_romapi.c
For STM32MP2, it also : - adds memory region description needed for ARMv8 MMU. - enables early data cache before relocation. During the transition before/after relocation, the MMU, initially setup at the beginning of DDR, must be setup again at a correct address after relocation. This is done in enables_caches() by disabling cache, force arch.tlb_fillptr to NULL which will force the MMU to be setup again but with a new value for gd->arch.tlb_addr. gd->arch.tlb_addr has been updated after relocation in arm_reserve_mmu().
Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com ---
arch/arm/Kconfig | 2 +- arch/arm/mach-stm32mp/Kconfig | 26 ++- arch/arm/mach-stm32mp/Kconfig.25x | 43 ++++ arch/arm/mach-stm32mp/Makefile | 15 +- arch/arm/mach-stm32mp/include/mach/stm32.h | 141 ++++++++----- .../arm/mach-stm32mp/include/mach/sys_proto.h | 26 +++ arch/arm/mach-stm32mp/stm32mp1/Makefile | 20 ++ arch/arm/mach-stm32mp/{ => stm32mp1}/cpu.c | 0 arch/arm/mach-stm32mp/{ => stm32mp1}/fdt.c | 0 arch/arm/mach-stm32mp/{ => stm32mp1}/psci.c | 0 .../{ => stm32mp1}/pwr_regulator.c | 0 arch/arm/mach-stm32mp/{ => stm32mp1}/spl.c | 0 .../mach-stm32mp/{ => stm32mp1}/stm32mp13x.c | 0 .../mach-stm32mp/{ => stm32mp1}/stm32mp15x.c | 0 arch/arm/mach-stm32mp/{ => stm32mp1}/tzc400.c | 0 arch/arm/mach-stm32mp/stm32mp2/Makefile | 9 + arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c | 68 ++++++ arch/arm/mach-stm32mp/stm32mp2/cpu.c | 108 ++++++++++ arch/arm/mach-stm32mp/stm32mp2/fdt.c | 16 ++ arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c | 194 ++++++++++++++++++ arch/arm/mach-stm32mp/syscon.c | 4 +- board/st/stm32mp2/Kconfig | 13 ++ board/st/stm32mp2/MAINTAINERS | 9 + board/st/stm32mp2/Makefile | 6 + board/st/stm32mp2/stm32mp2.c | 52 +++++ configs/stm32mp25_defconfig | 52 +++++ include/configs/stm32mp25_common.h | 24 +++ 27 files changed, 757 insertions(+), 71 deletions(-) create mode 100644 arch/arm/mach-stm32mp/Kconfig.25x create mode 100644 arch/arm/mach-stm32mp/stm32mp1/Makefile rename arch/arm/mach-stm32mp/{ => stm32mp1}/cpu.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/fdt.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/psci.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/pwr_regulator.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/spl.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/stm32mp13x.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/stm32mp15x.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/tzc400.c (100%) create mode 100644 arch/arm/mach-stm32mp/stm32mp2/Makefile create mode 100644 arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c create mode 100644 arch/arm/mach-stm32mp/stm32mp2/cpu.c create mode 100644 arch/arm/mach-stm32mp/stm32mp2/fdt.c create mode 100644 arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c create mode 100644 board/st/stm32mp2/Kconfig create mode 100644 board/st/stm32mp2/MAINTAINERS create mode 100644 board/st/stm32mp2/Makefile create mode 100644 board/st/stm32mp2/stm32mp2.c create mode 100644 configs/stm32mp25_defconfig create mode 100644 include/configs/stm32mp25_common.h
diff --git a/arch/arm/Kconfig b/arch/arm/Kconfig index d812685c984..77f960de5c3 100644 --- a/arch/arm/Kconfig +++ b/arch/arm/Kconfig @@ -1945,7 +1945,7 @@ config ARCH_STM32MP select REGMAP select SYSCON select SYSRESET - select SYS_THUMB_BUILD + select SYS_THUMB_BUILD if !ARM64 imply SPL_SYSRESET imply CMD_DM imply CMD_POWEROFF diff --git a/arch/arm/mach-stm32mp/Kconfig b/arch/arm/mach-stm32mp/Kconfig index db47baba6d1..5fc92d07fe6 100644 --- a/arch/arm/mach-stm32mp/Kconfig +++ b/arch/arm/mach-stm32mp/Kconfig @@ -76,6 +76,30 @@ config STM32MP15x STM32MP157, STM32MP153 or STM32MP151 STMicroelectronics MPU with core ARMv7 dual core A7 for STM32MP157/3, monocore for STM32MP151 + +config STM32MP25X + bool "Support STMicroelectronics STM32MP25x Soc" + select ARM64 + select CLK_STM32MP25 + select OF_BOARD + select PINCTRL_STM32 + select STM32_RCC + select STM32_RESET + select STM32_SERIAL + select SYS_ARCH_TIMER + select TFABOOT + imply CLK_SCMI + imply CMD_NVEDIT_INFO + imply DM_REGULATOR + imply DM_REGULATOR_SCMI + imply OPTEE + imply RESET_SCMI + imply SYSRESET_PSCI + imply TEE + imply VERSION_VARIABLE + help + Support of STMicroelectronics SOC STM32MP25x family + STMicroelectronics MPU with 2 * A53 core and 1 M33 core endchoice
config NR_DRAM_BANKS @@ -128,6 +152,6 @@ config CMD_STM32KEY
source "arch/arm/mach-stm32mp/Kconfig.13x" source "arch/arm/mach-stm32mp/Kconfig.15x" - +source "arch/arm/mach-stm32mp/Kconfig.25x" source "arch/arm/mach-stm32mp/cmd_stm32prog/Kconfig" endif diff --git a/arch/arm/mach-stm32mp/Kconfig.25x b/arch/arm/mach-stm32mp/Kconfig.25x new file mode 100644 index 00000000000..2c0f691f8b5 --- /dev/null +++ b/arch/arm/mach-stm32mp/Kconfig.25x @@ -0,0 +1,43 @@ +if STM32MP25X + +choice + prompt "STM32MP25x board select" + optional + +config TARGET_ST_STM32MP25X + bool "STMicroelectronics STM32MP25x boards" + imply BOOTSTAGE + imply CMD_BOOTSTAGE + help + target the STMicroelectronics board with SOC STM32MP25x + managed by board/st/stm32mp2 + The difference between board are managed with devicetree + +endchoice + +config TEXT_BASE + default 0x84000000 + +config PRE_CON_BUF_ADDR + default 0x84800000 + +config PRE_CON_BUF_SZ + default 4096 + +config BOOTSTAGE_STASH_ADDR + default 0x87000000 + +if DEBUG_UART + +config DEBUG_UART_BOARD_INIT + default y + +# debug on USART2 by default +config DEBUG_UART_BASE + default 0x400e0000 + +endif + +source "board/st/stm32mp2/Kconfig" + +endif diff --git a/arch/arm/mach-stm32mp/Makefile b/arch/arm/mach-stm32mp/Makefile index a19b2797c8b..00dc25bb275 100644 --- a/arch/arm/mach-stm32mp/Makefile +++ b/arch/arm/mach-stm32mp/Makefile @@ -3,24 +3,17 @@ # Copyright (C) 2018, STMicroelectronics - All Rights Reserved #
-obj-y += cpu.o obj-y += dram_init.o obj-y += syscon.o obj-y += bsec.o
-obj-$(CONFIG_STM32MP13x) += stm32mp13x.o -obj-$(CONFIG_STM32MP15x) += stm32mp15x.o +obj-$(CONFIG_STM32MP15x) += stm32mp1/ +obj-$(CONFIG_STM32MP13x) += stm32mp1/ +obj-$(CONFIG_STM32MP25X) += stm32mp2/
obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o -ifdef CONFIG_SPL_BUILD -obj-y += spl.o -obj-y += tzc400.o -else +ifndef CONFIG_SPL_BUILD obj-y += cmd_stm32prog/ obj-$(CONFIG_CMD_STM32KEY) += cmd_stm32key.o -obj-$(CONFIG_ARMV7_PSCI) += psci.o obj-$(CONFIG_TFABOOT) += boot_params.o endif - -obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o -obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o diff --git a/arch/arm/mach-stm32mp/include/mach/stm32.h b/arch/arm/mach-stm32mp/include/mach/stm32.h index 1cdc5e3b186..ce9d795651b 100644 --- a/arch/arm/mach-stm32mp/include/mach/stm32.h +++ b/arch/arm/mach-stm32mp/include/mach/stm32.h @@ -8,12 +8,66 @@
#ifndef __ASSEMBLY__ #include <linux/bitops.h> + +enum boot_device { + BOOT_FLASH_SD = 0x10, + BOOT_FLASH_SD_1 = 0x11, + BOOT_FLASH_SD_2 = 0x12, + BOOT_FLASH_SD_3 = 0x13, + + BOOT_FLASH_EMMC = 0x20, + BOOT_FLASH_EMMC_1 = 0x21, + BOOT_FLASH_EMMC_2 = 0x22, + BOOT_FLASH_EMMC_3 = 0x23, + + BOOT_FLASH_NAND = 0x30, + BOOT_FLASH_NAND_FMC = 0x31, + + BOOT_FLASH_NOR = 0x40, + BOOT_FLASH_NOR_QSPI = 0x41, + + BOOT_SERIAL_UART = 0x50, + BOOT_SERIAL_UART_1 = 0x51, + BOOT_SERIAL_UART_2 = 0x52, + BOOT_SERIAL_UART_3 = 0x53, + BOOT_SERIAL_UART_4 = 0x54, + BOOT_SERIAL_UART_5 = 0x55, + BOOT_SERIAL_UART_6 = 0x56, + BOOT_SERIAL_UART_7 = 0x57, + BOOT_SERIAL_UART_8 = 0x58, + + BOOT_SERIAL_USB = 0x60, + BOOT_SERIAL_USB_OTG = 0x62, + + BOOT_FLASH_SPINAND = 0x70, + BOOT_FLASH_SPINAND_1 = 0x71, +}; + +#define TAMP_BOOT_MODE_MASK GENMASK(15, 8) +#define TAMP_BOOT_MODE_SHIFT 8 +#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) +#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) +#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0) +#define TAMP_BOOT_DEBUG_ON BIT(16) + +enum forced_boot_mode { + BOOT_NORMAL = 0x00, + BOOT_FASTBOOT = 0x01, + BOOT_RECOVERY = 0x02, + BOOT_STM32PROG = 0x03, + BOOT_UMS_MMC0 = 0x10, + BOOT_UMS_MMC1 = 0x11, + BOOT_UMS_MMC2 = 0x12, +}; + #endif
/* * Peripheral memory map * only address used before device tree parsing */ + +#if defined(CONFIG_STM32MP15x) || defined(CONFIG_STM32MP13x) #define STM32_RCC_BASE 0x50000000 #define STM32_PWR_BASE 0x50001000 #define STM32_SYSCFG_BASE 0x50020000 @@ -58,12 +112,6 @@ #define STM32_DDR_SIZE SZ_1G
#ifndef __ASSEMBLY__ -/* enumerated used to identify the SYSCON driver instance */ -enum { - STM32MP_SYSCON_UNKNOWN, - STM32MP_SYSCON_SYSCFG, -}; - /* * enumerated for boot interface from Bootrom, used in TAMP_BOOT_CONTEXT * - boot device = bit 8:4 @@ -74,40 +122,6 @@ enum { #define BOOT_INSTANCE_MASK 0x0F #define BOOT_INSTANCE_SHIFT 0
-enum boot_device { - BOOT_FLASH_SD = 0x10, - BOOT_FLASH_SD_1 = 0x11, - BOOT_FLASH_SD_2 = 0x12, - BOOT_FLASH_SD_3 = 0x13, - - BOOT_FLASH_EMMC = 0x20, - BOOT_FLASH_EMMC_1 = 0x21, - BOOT_FLASH_EMMC_2 = 0x22, - BOOT_FLASH_EMMC_3 = 0x23, - - BOOT_FLASH_NAND = 0x30, - BOOT_FLASH_NAND_FMC = 0x31, - - BOOT_FLASH_NOR = 0x40, - BOOT_FLASH_NOR_QSPI = 0x41, - - BOOT_SERIAL_UART = 0x50, - BOOT_SERIAL_UART_1 = 0x51, - BOOT_SERIAL_UART_2 = 0x52, - BOOT_SERIAL_UART_3 = 0x53, - BOOT_SERIAL_UART_4 = 0x54, - BOOT_SERIAL_UART_5 = 0x55, - BOOT_SERIAL_UART_6 = 0x56, - BOOT_SERIAL_UART_7 = 0x57, - BOOT_SERIAL_UART_8 = 0x58, - - BOOT_SERIAL_USB = 0x60, - BOOT_SERIAL_USB_OTG = 0x62, - - BOOT_FLASH_SPINAND = 0x70, - BOOT_FLASH_SPINAND_1 = 0x71, -}; - /* TAMP registers */ #define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * x)
@@ -123,7 +137,6 @@ enum boot_device { #define TAMP_FWU_BOOT_IDX_MASK GENMASK(3, 0)
#define TAMP_FWU_BOOT_IDX_OFFSET 0 - #define TAMP_COPRO_STATE_OFF 0 #define TAMP_COPRO_STATE_INIT 1 #define TAMP_COPRO_STATE_CRUN 2 @@ -137,21 +150,23 @@ enum boot_device { #define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(30) #endif
-#define TAMP_BOOT_MODE_MASK GENMASK(15, 8) -#define TAMP_BOOT_MODE_SHIFT 8 -#define TAMP_BOOT_DEVICE_MASK GENMASK(7, 4) -#define TAMP_BOOT_INSTANCE_MASK GENMASK(3, 0) -#define TAMP_BOOT_FORCED_MASK GENMASK(7, 0) +#endif /* __ASSEMBLY__ */ +#endif /* CONFIG_STM32MP15X || CONFIG_STM32MP13X */
-enum forced_boot_mode { - BOOT_NORMAL = 0x00, - BOOT_FASTBOOT = 0x01, - BOOT_RECOVERY = 0x02, - BOOT_STM32PROG = 0x03, - BOOT_UMS_MMC0 = 0x10, - BOOT_UMS_MMC1 = 0x11, - BOOT_UMS_MMC2 = 0x12, -}; +#if CONFIG_STM32MP25X +#define STM32_RCC_BASE 0x44200000 +#define STM32_TAMP_BASE 0x46010000 + +#define STM32_DDR_BASE 0x80000000 + +#define STM32_DDR_SIZE SZ_4G + +/* TAMP registers x = 0 to 127 : hardcoded description, waiting NVMEM node in DT */ +#define TAMP_BACKUP_REGISTER(x) (STM32_TAMP_BASE + 0x100 + 4 * (x)) + +/* TAMP registers zone 3 RIF 1 (RW) at 96*/ +#define TAMP_BOOT_CONTEXT TAMP_BACKUP_REGISTER(96) +#endif /* STM32MP25X */
/* offset used for BSEC driver: misc_read and misc_write */ #define STM32_BSEC_SHADOW_OFFSET 0x0 @@ -175,6 +190,20 @@ enum forced_boot_mode { #define BSEC_OTP_MAC 57 #define BSEC_OTP_BOARD 60 #endif +#ifdef CONFIG_STM32MP25X +#define BSEC_OTP_SERIAL 5 +#define BSEC_OTP_RPN 9 +#define BSEC_OTP_PKG 246 +#endif + +#ifndef __ASSEMBLY__ +#include <asm/types.h> + +/* enumerated used to identify the SYSCON driver instance */ +enum { + STM32MP_SYSCON_UNKNOWN, + STM32MP_SYSCON_SYSCFG, +}; +#endif /* __ASSEMBLY__*/
-#endif /* __ASSEMBLY__ */ #endif /* _MACH_STM32_H_ */ diff --git a/arch/arm/mach-stm32mp/include/mach/sys_proto.h b/arch/arm/mach-stm32mp/include/mach/sys_proto.h index 83fb32a45fc..7b2df09a33c 100644 --- a/arch/arm/mach-stm32mp/include/mach/sys_proto.h +++ b/arch/arm/mach-stm32mp/include/mach/sys_proto.h @@ -30,11 +30,30 @@ #define CPU_STM32MP131Fxx 0x05010EC8 #define CPU_STM32MP131Dxx 0x05010EC9
+/* ID for STM32MP25x = Device Part Number (RPN) (bit31:0) */ +#define CPU_STM32MP257Cxx 0x00002000 +#define CPU_STM32MP255Cxx 0x00082000 +#define CPU_STM32MP253Cxx 0x000B2004 +#define CPU_STM32MP251Cxx 0x000B3065 +#define CPU_STM32MP257Axx 0x40002E00 +#define CPU_STM32MP255Axx 0x40082E00 +#define CPU_STM32MP253Axx 0x400B2E04 +#define CPU_STM32MP251Axx 0x400B3E65 +#define CPU_STM32MP257Fxx 0x80002000 +#define CPU_STM32MP255Fxx 0x80082000 +#define CPU_STM32MP253Fxx 0x800B2004 +#define CPU_STM32MP251Fxx 0x800B3065 +#define CPU_STM32MP257Dxx 0xC0002E00 +#define CPU_STM32MP255Dxx 0xC0082E00 +#define CPU_STM32MP253Dxx 0xC00B2E04 +#define CPU_STM32MP251Dxx 0xC00B3E65 + /* return CPU_STMP32MP...Xxx constants */ u32 get_cpu_type(void);
#define CPU_DEV_STM32MP15 0x500 #define CPU_DEV_STM32MP13 0x501 +#define CPU_DEV_STM32MP25 0x505
/* return CPU_DEV constants */ u32 get_cpu_dev(void); @@ -59,6 +78,13 @@ u32 get_cpu_package(void); #define STM32MP15_PKG_AD_TFBGA257 1 #define STM32MP15_PKG_UNKNOWN 0
+/* package used for STM32MP25x */ +#define STM32MP25_PKG_CUSTOM 0 +#define STM32MP25_PKG_AL_TBGA361 3 +#define STM32MP25_PKG_AK_TBGA424 4 +#define STM32MP25_PKG_AI_TBGA436 5 +#define STM32MP25_PKG_UNKNOWN 7 + /* Get SOC name */ #define SOC_NAME_SIZE 20 void get_soc_name(char name[SOC_NAME_SIZE]); diff --git a/arch/arm/mach-stm32mp/stm32mp1/Makefile b/arch/arm/mach-stm32mp/stm32mp1/Makefile new file mode 100644 index 00000000000..94c7724127e --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp1/Makefile @@ -0,0 +1,20 @@ +# SPDX-License-Identifier: GPL-2.0+ +# +# Copyright (C) 2018, STMicroelectronics - All Rights Reserved +# + +obj-y += cpu.o + +obj-$(CONFIG_STM32MP13x) += stm32mp13x.o +obj-$(CONFIG_STM32MP15x) += stm32mp15x.o + +obj-$(CONFIG_STM32_ECDSA_VERIFY) += ecdsa_romapi.o +ifdef CONFIG_SPL_BUILD +obj-y += spl.o +obj-y += tzc400.o +else +obj-$(CONFIG_ARMV7_PSCI) += psci.o +endif + +obj-$(CONFIG_$(SPL_)STM32MP15_PWR) += pwr_regulator.o +obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o diff --git a/arch/arm/mach-stm32mp/cpu.c b/arch/arm/mach-stm32mp/stm32mp1/cpu.c similarity index 100% rename from arch/arm/mach-stm32mp/cpu.c rename to arch/arm/mach-stm32mp/stm32mp1/cpu.c diff --git a/arch/arm/mach-stm32mp/fdt.c b/arch/arm/mach-stm32mp/stm32mp1/fdt.c similarity index 100% rename from arch/arm/mach-stm32mp/fdt.c rename to arch/arm/mach-stm32mp/stm32mp1/fdt.c diff --git a/arch/arm/mach-stm32mp/psci.c b/arch/arm/mach-stm32mp/stm32mp1/psci.c similarity index 100% rename from arch/arm/mach-stm32mp/psci.c rename to arch/arm/mach-stm32mp/stm32mp1/psci.c diff --git a/arch/arm/mach-stm32mp/pwr_regulator.c b/arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c similarity index 100% rename from arch/arm/mach-stm32mp/pwr_regulator.c rename to arch/arm/mach-stm32mp/stm32mp1/pwr_regulator.c diff --git a/arch/arm/mach-stm32mp/spl.c b/arch/arm/mach-stm32mp/stm32mp1/spl.c similarity index 100% rename from arch/arm/mach-stm32mp/spl.c rename to arch/arm/mach-stm32mp/stm32mp1/spl.c diff --git a/arch/arm/mach-stm32mp/stm32mp13x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c similarity index 100% rename from arch/arm/mach-stm32mp/stm32mp13x.c rename to arch/arm/mach-stm32mp/stm32mp1/stm32mp13x.c diff --git a/arch/arm/mach-stm32mp/stm32mp15x.c b/arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c similarity index 100% rename from arch/arm/mach-stm32mp/stm32mp15x.c rename to arch/arm/mach-stm32mp/stm32mp1/stm32mp15x.c diff --git a/arch/arm/mach-stm32mp/tzc400.c b/arch/arm/mach-stm32mp/stm32mp1/tzc400.c similarity index 100% rename from arch/arm/mach-stm32mp/tzc400.c rename to arch/arm/mach-stm32mp/stm32mp1/tzc400.c diff --git a/arch/arm/mach-stm32mp/stm32mp2/Makefile b/arch/arm/mach-stm32mp/stm32mp2/Makefile new file mode 100644 index 00000000000..b579ce5a800 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/Makefile @@ -0,0 +1,9 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +# +# Copyright (C) 2023, STMicroelectronics - All Rights Reserved +# + +obj-y += cpu.o +obj-y += arm64-mmu.o +obj-$(CONFIG_OF_SYSTEM_SETUP) += fdt.o +obj-$(CONFIG_STM32MP25X) += stm32mp25x.o diff --git a/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c b/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c new file mode 100644 index 00000000000..a203eebdc59 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c @@ -0,0 +1,68 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#include <common.h> +#include <asm/system.h> +#include <asm/armv8/mmu.h> + +#define MP2_MEM_MAP_MAX 10 + +#if (CONFIG_TEXT_BASE < STM32_DDR_BASE) || \ + (CONFIG_TEXT_BASE > (STM32_DDR_BASE + STM32_DDR_SIZE)) +#error "invalid CONFIG_TEXT_BASE value" +#endif + +struct mm_region stm32mp2_mem_map[MP2_MEM_MAP_MAX] = { + { + /* PCIe */ + .virt = 0x10000000UL, + .phys = 0x10000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* LPSRAMs, VDERAM, RETRAM, SRAMs, SYSRAM: alias1 */ + .virt = 0x20000000UL, + .phys = 0x20000000UL, + .size = 0x00200000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* Peripherals: alias1 */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x10000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* OSPI and FMC: memory-map area */ + .virt = 0x60000000UL, + .phys = 0x60000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + /* + * DDR = STM32_DDR_BASE / STM32_DDR_SIZE + * the beginning of DDR (before CONFIG_TEXT_BASE) is not + * mapped, protected by RIF and reserved for other firmware + * (OP-TEE / TF-M / Cube M33) + */ + .virt = CONFIG_TEXT_BASE, + .phys = CONFIG_TEXT_BASE, + .size = STM32_DDR_SIZE - (CONFIG_TEXT_BASE - STM32_DDR_BASE), + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | + PTE_BLOCK_INNER_SHARE + }, { + /* List terminator */ + 0, + } +}; + +struct mm_region *mem_map = stm32mp2_mem_map; diff --git a/arch/arm/mach-stm32mp/stm32mp2/cpu.c b/arch/arm/mach-stm32mp/stm32mp2/cpu.c new file mode 100644 index 00000000000..5bfeab17ab7 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/cpu.c @@ -0,0 +1,108 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include <common.h> +#include <clk.h> +#include <cpu_func.h> +#include <debug_uart.h> +#include <env_internal.h> +#include <init.h> +#include <misc.h> +#include <wdt.h> +#include <asm/io.h> +#include <asm/arch/stm32.h> +#include <asm/arch/sys_proto.h> +#include <asm/system.h> +#include <dm/device.h> +#include <dm/lists.h> +#include <dm/uclass.h> + +/* + * early TLB into the .data section so that it not get cleared + * with 16kB alignment + */ +#define EARLY_TLB_SIZE 0xA000 +u8 early_tlb[EARLY_TLB_SIZE] __section(".data") __aligned(0x4000); + +/* + * initialize the MMU and activate cache in U-Boot pre-reloc stage + * MMU/TLB is updated in enable_caches() for U-Boot after relocation + */ +static void early_enable_caches(void) +{ + if (CONFIG_IS_ENABLED(SYS_DCACHE_OFF)) + return; + + if (!(CONFIG_IS_ENABLED(SYS_ICACHE_OFF) && CONFIG_IS_ENABLED(SYS_DCACHE_OFF))) { + gd->arch.tlb_size = EARLY_TLB_SIZE; + gd->arch.tlb_addr = (unsigned long)&early_tlb; + } + /* enable MMU (default configuration) */ + dcache_enable(); +} + +/* + * Early system init + */ +int arch_cpu_init(void) +{ + icache_enable(); + early_enable_caches(); + + return 0; +} + +void enable_caches(void) +{ + /* deactivate the data cache, early enabled in arch_cpu_init() */ + dcache_disable(); + /* + * Force the call of setup_all_pgtables() in mmu_setup() by clearing tlb_fillptr + * to update the TLB location udpated in board_f.c::reserve_mmu + */ + gd->arch.tlb_fillptr = 0; + dcache_enable(); +} + +/* used when CONFIG_DISPLAY_CPUINFO is activated */ +int print_cpuinfo(void) +{ + char name[SOC_NAME_SIZE]; + + get_soc_name(name); + printf("CPU: %s\n", name); + + return 0; +} + +int arch_misc_init(void) +{ + return 0; +} + +/* + * Force data-section, as .bss will not be valid + * when save_boot_params is invoked. + */ +static uintptr_t nt_fw_dtb __section(".data"); + +uintptr_t get_stm32mp_bl2_dtb(void) +{ + return nt_fw_dtb; +} + +/* + * Save the FDT address provided by TF-A in r2 at boot time + * This function is called from start.S + */ +void save_boot_params(unsigned long r0, unsigned long r1, unsigned long r2, + unsigned long r3) +{ + nt_fw_dtb = r2; + + save_boot_params_ret(); +} diff --git a/arch/arm/mach-stm32mp/stm32mp2/fdt.c b/arch/arm/mach-stm32mp/stm32mp2/fdt.c new file mode 100644 index 00000000000..ee570863bb7 --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/fdt.c @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#include <common.h> + +/* + * This function is called right before the kernel is booted. "blob" is the + * device tree that will be passed to the kernel. + */ +int ft_system_setup(void *blob, struct bd_info *bd) +{ + return 0; +} + diff --git a/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c b/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c new file mode 100644 index 00000000000..7d2dab2201d --- /dev/null +++ b/arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c @@ -0,0 +1,194 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_ARCH + +#include <common.h> +#include <log.h> +#include <syscon.h> +#include <asm/io.h> +#include <asm/arch/stm32.h> +#include <asm/arch/sys_proto.h> + +/* SYSCFG register */ +#define SYSCFG_DEVICEID_OFFSET 0x6400 +#define SYSCFG_DEVICEID_DEV_ID_MASK GENMASK(11, 0) +#define SYSCFG_DEVICEID_DEV_ID_SHIFT 0 +#define SYSCFG_DEVICEID_REV_ID_MASK GENMASK(31, 16) +#define SYSCFG_DEVICEID_REV_ID_SHIFT 16 + +/* Device Part Number (RPN) = OTP9 */ +#define RPN_SHIFT 0 +#define RPN_MASK GENMASK(31, 0) + +/* Package = bit 0:2 of OTP122 => STM32MP25_PKG defines + * - 000: Custom package + * - 011: TFBGA361 => AL = 10x10, 361 balls pith 0.5mm + * - 100: TFBGA424 => AK = 14x14, 424 balls pith 0.5mm + * - 101: TFBGA436 => AI = 18x18, 436 balls pith 0.5mm + * - others: Reserved + */ +#define PKG_SHIFT 0 +#define PKG_MASK GENMASK(2, 0) + +static u32 read_deviceid(void) +{ + void *syscfg = syscon_get_first_range(STM32MP_SYSCON_SYSCFG); + + return readl(syscfg + SYSCFG_DEVICEID_OFFSET); +} + +u32 get_cpu_dev(void) +{ + return (read_deviceid() & SYSCFG_DEVICEID_DEV_ID_MASK) >> SYSCFG_DEVICEID_DEV_ID_SHIFT; +} + +u32 get_cpu_rev(void) +{ + return (read_deviceid() & SYSCFG_DEVICEID_REV_ID_MASK) >> SYSCFG_DEVICEID_REV_ID_SHIFT; +} + +/* Get Device Part Number (RPN) from OTP */ +u32 get_cpu_type(void) +{ + return get_otp(BSEC_OTP_RPN, RPN_SHIFT, RPN_MASK); +} + +/* Get Package options from OTP */ +u32 get_cpu_package(void) +{ + return get_otp(BSEC_OTP_PKG, PKG_SHIFT, PKG_MASK); +} + +int get_eth_nb(void) +{ + int nb_eth; + + switch (get_cpu_type()) { + case CPU_STM32MP257Fxx: + fallthrough; + case CPU_STM32MP257Dxx: + fallthrough; + case CPU_STM32MP257Cxx: + fallthrough; + case CPU_STM32MP257Axx: + nb_eth = 5; /* dual ETH with TSN support */ + break; + case CPU_STM32MP253Fxx: + fallthrough; + case CPU_STM32MP253Dxx: + fallthrough; + case CPU_STM32MP253Cxx: + fallthrough; + case CPU_STM32MP253Axx: + nb_eth = 2; /* dual ETH */ + break; + case CPU_STM32MP251Fxx: + fallthrough; + case CPU_STM32MP251Dxx: + fallthrough; + case CPU_STM32MP251Cxx: + fallthrough; + case CPU_STM32MP251Axx: + nb_eth = 1; /* single ETH */ + break; + default: + nb_eth = 0; + break; + } + + return nb_eth; +} + +void get_soc_name(char name[SOC_NAME_SIZE]) +{ + char *cpu_s, *cpu_r, *package; + + cpu_s = "????"; + cpu_r = "?"; + package = "??"; + if (get_cpu_dev() == CPU_DEV_STM32MP25) { + switch (get_cpu_type()) { + case CPU_STM32MP257Fxx: + cpu_s = "257F"; + break; + case CPU_STM32MP257Dxx: + cpu_s = "257D"; + break; + case CPU_STM32MP257Cxx: + cpu_s = "257C"; + break; + case CPU_STM32MP257Axx: + cpu_s = "257A"; + break; + case CPU_STM32MP255Fxx: + cpu_s = "255F"; + break; + case CPU_STM32MP255Dxx: + cpu_s = "255D"; + break; + case CPU_STM32MP255Cxx: + cpu_s = "255C"; + break; + case CPU_STM32MP255Axx: + cpu_s = "255A"; + break; + case CPU_STM32MP253Fxx: + cpu_s = "253F"; + break; + case CPU_STM32MP253Dxx: + cpu_s = "253D"; + break; + case CPU_STM32MP253Cxx: + cpu_s = "253C"; + break; + case CPU_STM32MP253Axx: + cpu_s = "253A"; + break; + case CPU_STM32MP251Fxx: + cpu_s = "251F"; + break; + case CPU_STM32MP251Dxx: + cpu_s = "251D"; + break; + case CPU_STM32MP251Cxx: + cpu_s = "251C"; + break; + case CPU_STM32MP251Axx: + cpu_s = "251A"; + break; + default: + cpu_s = "25??"; + break; + } + /* REVISION */ + switch (get_cpu_rev()) { + case CPU_REV1: + cpu_r = "A"; + break; + default: + break; + } + /* PACKAGE */ + switch (get_cpu_package()) { + case STM32MP25_PKG_CUSTOM: + package = "XX"; + break; + case STM32MP25_PKG_AL_TBGA361: + package = "AL"; + break; + case STM32MP25_PKG_AK_TBGA424: + package = "AK"; + break; + case STM32MP25_PKG_AI_TBGA436: + package = "AI"; + break; + default: + break; + } + } + + snprintf(name, SOC_NAME_SIZE, "STM32MP%s%s Rev.%s", cpu_s, package, cpu_r); +} diff --git a/arch/arm/mach-stm32mp/syscon.c b/arch/arm/mach-stm32mp/syscon.c index a0e8e1dfdc5..a2e351d74a7 100644 --- a/arch/arm/mach-stm32mp/syscon.c +++ b/arch/arm/mach-stm32mp/syscon.c @@ -10,8 +10,8 @@ #include <asm/arch/stm32.h>
static const struct udevice_id stm32mp_syscon_ids[] = { - { .compatible = "st,stm32mp157-syscfg", - .data = STM32MP_SYSCON_SYSCFG }, + { .compatible = "st,stm32mp157-syscfg", .data = STM32MP_SYSCON_SYSCFG }, + { .compatible = "st,stm32mp25-syscfg", .data = STM32MP_SYSCON_SYSCFG}, { } };
diff --git a/board/st/stm32mp2/Kconfig b/board/st/stm32mp2/Kconfig new file mode 100644 index 00000000000..89039f068a2 --- /dev/null +++ b/board/st/stm32mp2/Kconfig @@ -0,0 +1,13 @@ +if TARGET_ST_STM32MP25X + +config SYS_BOARD + default "stm32mp2" + +config SYS_VENDOR + default "st" + +config SYS_CONFIG_NAME + default "stm32mp25_common" + +source "board/st/common/Kconfig" +endif diff --git a/board/st/stm32mp2/MAINTAINERS b/board/st/stm32mp2/MAINTAINERS new file mode 100644 index 00000000000..e6bea910f92 --- /dev/null +++ b/board/st/stm32mp2/MAINTAINERS @@ -0,0 +1,9 @@ +STM32MP2 BOARD +M: Patrice Chotard patrice.chotard@st.com +M: Patrick Delaunay patrick.delaunay@st.com +L: uboot-stm32@st-md-mailman.stormreply.com (moderated for non-subscribers) +S: Maintained +F: arch/arm/dts/stm32mp25* +F: board/st/stm32mp2/ +F: configs/stm32mp25_defconfig +F: include/configs/stm32mp25_common.h diff --git a/board/st/stm32mp2/Makefile b/board/st/stm32mp2/Makefile new file mode 100644 index 00000000000..50352fb71b4 --- /dev/null +++ b/board/st/stm32mp2/Makefile @@ -0,0 +1,6 @@ +# SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +# +# Copyright (C) 2023, STMicroelectronics - All Rights Reserved +# + +obj-y += stm32mp2.o diff --git a/board/st/stm32mp2/stm32mp2.c b/board/st/stm32mp2/stm32mp2.c new file mode 100644 index 00000000000..132c511ce96 --- /dev/null +++ b/board/st/stm32mp2/stm32mp2.c @@ -0,0 +1,52 @@ +// SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + */ + +#define LOG_CATEGORY LOGC_BOARD + +#include <common.h> +#include <config.h> +#include <env.h> +#include <fdt_support.h> +#include <asm/global_data.h> +#include <asm/arch/sys_proto.h> + +/* + * Get a global data pointer + */ +DECLARE_GLOBAL_DATA_PTR; + +/* board dependent setup after realloc */ +int board_init(void) +{ + return 0; +} + +int board_late_init(void) +{ + const void *fdt_compat; + int fdt_compat_len; + char dtb_name[256]; + int buf_len; + + if (IS_ENABLED(CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG)) { + fdt_compat = fdt_getprop(gd->fdt_blob, 0, "compatible", + &fdt_compat_len); + if (fdt_compat && fdt_compat_len) { + if (strncmp(fdt_compat, "st,", 3) != 0) { + env_set("board_name", fdt_compat); + } else { + env_set("board_name", fdt_compat + 3); + + buf_len = sizeof(dtb_name); + strlcpy(dtb_name, fdt_compat + 3, buf_len); + buf_len -= strlen(fdt_compat + 3); + strlcat(dtb_name, ".dtb", buf_len); + env_set("fdtfile", dtb_name); + } + } + } + + return 0; +} diff --git a/configs/stm32mp25_defconfig b/configs/stm32mp25_defconfig new file mode 100644 index 00000000000..4d5ac6f64ea --- /dev/null +++ b/configs/stm32mp25_defconfig @@ -0,0 +1,52 @@ +CONFIG_ARM=y +CONFIG_ARCH_STM32MP=y +CONFIG_SYS_MALLOC_F_LEN=0x400000 +CONFIG_CUSTOM_SYS_INIT_SP_ADDR=0x90000000 +CONFIG_DEFAULT_DEVICE_TREE="stm32mp257f-ev1" +CONFIG_STM32MP25X=y +CONFIG_DDR_CACHEABLE_SIZE=0x10000000 +CONFIG_TARGET_ST_STM32MP25X=y +CONFIG_SYS_LOAD_ADDR=0x84000000 +CONFIG_SYS_MEMTEST_START=0x84000000 +CONFIG_SYS_MEMTEST_END=0x88000000 +CONFIG_FIT=y +CONFIG_BOOTDELAY=1 +CONFIG_LAST_STAGE_INIT=y +CONFIG_SYS_PROMPT="STM32MP> " +# CONFIG_CMD_BDI is not set +CONFIG_CMD_BOOTZ=y +CONFIG_SYS_BOOTM_LEN=0x2000000 +CONFIG_CMD_ADTIMG=y +# CONFIG_CMD_ELF is not set +CONFIG_CMD_MEMINFO=y +CONFIG_CMD_MEMTEST=y +CONFIG_CMD_CLK=y +CONFIG_CMD_GPIO=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_NET is not set +CONFIG_CMD_CACHE=y +CONFIG_CMD_TIME=y +CONFIG_CMD_RNG=y +CONFIG_CMD_TIMER=y +CONFIG_CMD_REGULATOR=y +CONFIG_CMD_LOG=y +CONFIG_OF_LIVE=y +CONFIG_GPIO_HOG=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_STM32F7=y +# CONFIG_MMC is not set +CONFIG_PINCONF=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_REGULATOR_GPIO=y +CONFIG_RAM=y +# CONFIG_STM32MP1_DDR is not set +CONFIG_DM_RNG=y +CONFIG_SERIAL_RX_BUFFER=y +# CONFIG_OPTEE_TA_AVB is not set +CONFIG_WDT=y +CONFIG_WDT_STM32MP=y +CONFIG_WDT_ARM_SMC=y +CONFIG_ERRNO_STR=y +# CONFIG_LMB_USE_MAX_REGIONS is not set +CONFIG_LMB_MEMORY_REGIONS=2 +CONFIG_LMB_RESERVED_REGIONS=32 diff --git a/include/configs/stm32mp25_common.h b/include/configs/stm32mp25_common.h new file mode 100644 index 00000000000..ec980eea856 --- /dev/null +++ b/include/configs/stm32mp25_common.h @@ -0,0 +1,24 @@ +/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-3-Clause */ +/* + * Copyright (C) 2023, STMicroelectronics - All Rights Reserved + * + * Configuration settings for the STM32MP25x CPU + */ + +#ifndef __CONFIG_STM32MP25_COMMMON_H +#define __CONFIG_STM32MP25_COMMMON_H +#include <linux/sizes.h> +#include <asm/arch/stm32.h> + +/* + * Configuration of the external SRAM memory used by U-Boot + */ +#define CFG_SYS_SDRAM_BASE STM32_DDR_BASE + +/* + * For booting Linux, use the first 256 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_SYS_BOOTMAPSZ SZ_256M + +#endif /* __CONFIG_STM32MP25_COMMMON_H */
Hi,
On 10/27/23 16:43, Patrice Chotard wrote:
Add initial support for STM32MP2 SoCs family.
SoCs information are available here : https://www.st.com/content/st_com/en/campaigns/microprocessor-stm32mp2.html
Migrate all MP1 related code into stm32mp1/ directory
Minor:
MP1 => STM32MP1 series
Create stm32mp2 directory dedicated for STM32MP2 SoCs.
Common code to MP1, MP13 and MP25 is kept into
Minor
MP1 => STM32MP15
MP13 => STM32MP13
MP25 => STM32MP25
arch/arm/mach-stm32/mach-stm32mp directory :
- boot_params.c
- bsec
- cmd_stm32key
- cmd_stm32prog
- dram_init.c
- syscon.c
- ecdsa_romapi.c
For STM32MP2, it also :
- adds memory region description needed for ARMv8 MMU.
- enables early data cache before relocation. During the transition before/after relocation, the MMU, initially setup at the beginning of DDR, must be setup again at a correct address after relocation. This is done in enables_caches() by disabling cache, force arch.tlb_fillptr to NULL which will force the MMU to be setup again but with a new value for gd->arch.tlb_addr. gd->arch.tlb_addr has been updated after relocation in arm_reserve_mmu().
Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com
arch/arm/Kconfig | 2 +- arch/arm/mach-stm32mp/Kconfig | 26 ++- arch/arm/mach-stm32mp/Kconfig.25x | 43 ++++ arch/arm/mach-stm32mp/Makefile | 15 +- arch/arm/mach-stm32mp/include/mach/stm32.h | 141 ++++++++----- .../arm/mach-stm32mp/include/mach/sys_proto.h | 26 +++ arch/arm/mach-stm32mp/stm32mp1/Makefile | 20 ++ arch/arm/mach-stm32mp/{ => stm32mp1}/cpu.c | 0 arch/arm/mach-stm32mp/{ => stm32mp1}/fdt.c | 0 arch/arm/mach-stm32mp/{ => stm32mp1}/psci.c | 0 .../{ => stm32mp1}/pwr_regulator.c | 0 arch/arm/mach-stm32mp/{ => stm32mp1}/spl.c | 0 .../mach-stm32mp/{ => stm32mp1}/stm32mp13x.c | 0 .../mach-stm32mp/{ => stm32mp1}/stm32mp15x.c | 0 arch/arm/mach-stm32mp/{ => stm32mp1}/tzc400.c | 0 arch/arm/mach-stm32mp/stm32mp2/Makefile | 9 + arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c | 68 ++++++ arch/arm/mach-stm32mp/stm32mp2/cpu.c | 108 ++++++++++ arch/arm/mach-stm32mp/stm32mp2/fdt.c | 16 ++ arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c | 194 ++++++++++++++++++ arch/arm/mach-stm32mp/syscon.c | 4 +- board/st/stm32mp2/Kconfig | 13 ++ board/st/stm32mp2/MAINTAINERS | 9 + board/st/stm32mp2/Makefile | 6 + board/st/stm32mp2/stm32mp2.c | 52 +++++ configs/stm32mp25_defconfig | 52 +++++ include/configs/stm32mp25_common.h | 24 +++ 27 files changed, 757 insertions(+), 71 deletions(-) create mode 100644 arch/arm/mach-stm32mp/Kconfig.25x create mode 100644 arch/arm/mach-stm32mp/stm32mp1/Makefile rename arch/arm/mach-stm32mp/{ => stm32mp1}/cpu.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/fdt.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/psci.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/pwr_regulator.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/spl.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/stm32mp13x.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/stm32mp15x.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/tzc400.c (100%) create mode 100644 arch/arm/mach-stm32mp/stm32mp2/Makefile create mode 100644 arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c create mode 100644 arch/arm/mach-stm32mp/stm32mp2/cpu.c create mode 100644 arch/arm/mach-stm32mp/stm32mp2/fdt.c create mode 100644 arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c create mode 100644 board/st/stm32mp2/Kconfig create mode 100644 board/st/stm32mp2/MAINTAINERS create mode 100644 board/st/stm32mp2/Makefile create mode 100644 board/st/stm32mp2/stm32mp2.c create mode 100644 configs/stm32mp25_defconfig create mode 100644 include/configs/stm32mp25_common.h
with the minor remark on commit message
Reviewed-by: Patrick Delaunay patrick.delaunay@foss.st.com
Thanks Patrick
On 11/9/23 10:41, Patrick DELAUNAY wrote:
Hi,
On 10/27/23 16:43, Patrice Chotard wrote:
Add initial support for STM32MP2 SoCs family.
SoCs information are available here : https://www.st.com/content/st_com/en/campaigns/microprocessor-stm32mp2.html
Migrate all MP1 related code into stm32mp1/ directory
Minor:
MP1 => STM32MP1 series
Create stm32mp2 directory dedicated for STM32MP2 SoCs.
Common code to MP1, MP13 and MP25 is kept into
Minor
MP1 => STM32MP15
MP13 => STM32MP13
MP25 => STM32MP25
arch/arm/mach-stm32/mach-stm32mp directory : - boot_params.c - bsec - cmd_stm32key - cmd_stm32prog - dram_init.c - syscon.c - ecdsa_romapi.c
For STM32MP2, it also : - adds memory region description needed for ARMv8 MMU. - enables early data cache before relocation. During the transition before/after relocation, the MMU, initially setup at the beginning of DDR, must be setup again at a correct address after relocation. This is done in enables_caches() by disabling cache, force arch.tlb_fillptr to NULL which will force the MMU to be setup again but with a new value for gd->arch.tlb_addr. gd->arch.tlb_addr has been updated after relocation in arm_reserve_mmu().
Signed-off-by: Patrice Chotard patrice.chotard@foss.st.com
arch/arm/Kconfig | 2 +- arch/arm/mach-stm32mp/Kconfig | 26 ++- arch/arm/mach-stm32mp/Kconfig.25x | 43 ++++ arch/arm/mach-stm32mp/Makefile | 15 +- arch/arm/mach-stm32mp/include/mach/stm32.h | 141 ++++++++----- .../arm/mach-stm32mp/include/mach/sys_proto.h | 26 +++ arch/arm/mach-stm32mp/stm32mp1/Makefile | 20 ++ arch/arm/mach-stm32mp/{ => stm32mp1}/cpu.c | 0 arch/arm/mach-stm32mp/{ => stm32mp1}/fdt.c | 0 arch/arm/mach-stm32mp/{ => stm32mp1}/psci.c | 0 .../{ => stm32mp1}/pwr_regulator.c | 0 arch/arm/mach-stm32mp/{ => stm32mp1}/spl.c | 0 .../mach-stm32mp/{ => stm32mp1}/stm32mp13x.c | 0 .../mach-stm32mp/{ => stm32mp1}/stm32mp15x.c | 0 arch/arm/mach-stm32mp/{ => stm32mp1}/tzc400.c | 0 arch/arm/mach-stm32mp/stm32mp2/Makefile | 9 + arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c | 68 ++++++ arch/arm/mach-stm32mp/stm32mp2/cpu.c | 108 ++++++++++ arch/arm/mach-stm32mp/stm32mp2/fdt.c | 16 ++ arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c | 194 ++++++++++++++++++ arch/arm/mach-stm32mp/syscon.c | 4 +- board/st/stm32mp2/Kconfig | 13 ++ board/st/stm32mp2/MAINTAINERS | 9 + board/st/stm32mp2/Makefile | 6 + board/st/stm32mp2/stm32mp2.c | 52 +++++ configs/stm32mp25_defconfig | 52 +++++ include/configs/stm32mp25_common.h | 24 +++ 27 files changed, 757 insertions(+), 71 deletions(-) create mode 100644 arch/arm/mach-stm32mp/Kconfig.25x create mode 100644 arch/arm/mach-stm32mp/stm32mp1/Makefile rename arch/arm/mach-stm32mp/{ => stm32mp1}/cpu.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/fdt.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/psci.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/pwr_regulator.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/spl.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/stm32mp13x.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/stm32mp15x.c (100%) rename arch/arm/mach-stm32mp/{ => stm32mp1}/tzc400.c (100%) create mode 100644 arch/arm/mach-stm32mp/stm32mp2/Makefile create mode 100644 arch/arm/mach-stm32mp/stm32mp2/arm64-mmu.c create mode 100644 arch/arm/mach-stm32mp/stm32mp2/cpu.c create mode 100644 arch/arm/mach-stm32mp/stm32mp2/fdt.c create mode 100644 arch/arm/mach-stm32mp/stm32mp2/stm32mp25x.c create mode 100644 board/st/stm32mp2/Kconfig create mode 100644 board/st/stm32mp2/MAINTAINERS create mode 100644 board/st/stm32mp2/Makefile create mode 100644 board/st/stm32mp2/stm32mp2.c create mode 100644 configs/stm32mp25_defconfig create mode 100644 include/configs/stm32mp25_common.h
with the minor remark on commit message
Reviewed-by: Patrick Delaunay patrick.delaunay@foss.st.com
Thanks Patrick
Applied to u-boot-stm32/next
Thanks Patrice
participants (3)
-
Patrice CHOTARD -
Patrice Chotard
-
Patrick DELAUNAY