[PATCH v3 0/8] Inline ECC Series
Hello,
This series is to:
Add support for Inline ECC in DDR for AM64X, AM62X, AM62AX, AM62PX, J721S2 and J784S4 devices.
(1/8) Enable ECC priming with BIST engine (2/8) Add a function to store base address and size of RAM's banks in a 64-bit device private data (3/8) Setup the ECC region start and range (4/8) Enable ECC 1-bit error, 2-bit error and multiple-bit error interrupts (5/8) Add CONFIG_K3_INLINE_ECC (6/8) Set NR_DRAM_BANKS to 2 (7/8) Pull Redundant DDR functions to a common location and Fixup DDR size when ECC is enabled (8/8) Add ss_cfg reg entry
Changes since v2: Removed 'default n' in Kconfig as that is default setting
v2: https://lore.kernel.org/u-boot/20240510084707.1903133-1-s-k6@ti.com/
Changes since v1: Add support for J7* devices.
v1: https://lore.kernel.org/u-boot/20240131060213.1128024-1-s-k6@ti.com/
Test Results: https://gist.github.com/santhosh21/53c6f285640c4b6dfb3420d84975d12a
This series contains changes that grab the memory node from the DTS to set/modify DRAM bank sizes. A kernel patch has been sent [1] setting the required nodes to be available at bootloader stage. This patch series can be merged only after the DTS changes have been reflected in U-Boot either via OF_UPSTREAM (for devices that have moved to it) or via a sync to U-Boot patch.
[1] https://lore.kernel.org/all/20240506110203.3230255-1-n-francis@ti.com/
Thanks and Regards, Santhosh.
Georgi Vlaev (1): ram: k3-ddrss: Use the DDR controller BIST engine for ECC priming
Neha Malcom Francis (2): drivers: ram: Kconfig: Add CONFIG_K3_INLINE_ECC configs: j7*_evm_r5_defconfig: Set NR_DRAM_BANKS to 2
Santhosh Kumar K (5): ram: k3-ddrss: Add k3_ddrss_ddr_bank_base_size_calc() to solve 'calculations restricted to 32 bits' issue ram: k3-ddrss: Setup ECC region start and range ram: k3-ddrss: Enable ECC interrupts board: ti: Pull redundant DDR functions to a common location and Fixup DDR size when ECC is enabled arm: dts: k3-*-ddr: Add ss_cfg reg entry
arch/arm/dts/k3-am62a-ddr.dtsi | 7 +- arch/arm/dts/k3-j721s2-ddr.dtsi | 12 +- arch/arm/dts/k3-j784s4-ddr.dtsi | 24 ++-- board/ti/am62ax/evm.c | 17 +-- board/ti/am62px/evm.c | 18 +-- board/ti/am62x/evm.c | 63 ++-------- board/ti/am64x/evm.c | 73 ++--------- board/ti/am65x/evm.c | 29 +---- board/ti/common/Makefile | 1 + board/ti/common/k3-ddr-init.c | 89 +++++++++++++ board/ti/common/k3-ddr-init.h | 15 +++ board/ti/j721e/evm.c | 29 +---- board/ti/j721s2/evm.c | 35 ++---- board/ti/j784s4/evm.c | 17 +-- configs/j7200_evm_r5_defconfig | 1 + configs/j721e_evm_r5_defconfig | 1 + configs/j721s2_evm_r5_defconfig | 1 + configs/j784s4_evm_r5_defconfig | 1 + drivers/ram/Kconfig | 10 ++ drivers/ram/k3-ddrss/k3-ddrss.c | 214 +++++++++++++++++++++++++++----- 20 files changed, 390 insertions(+), 267 deletions(-) create mode 100644 board/ti/common/k3-ddr-init.c create mode 100644 board/ti/common/k3-ddr-init.h
From: Georgi Vlaev g-vlaev@ti.com
The 1-bit inline ECC support in TI's DDRSS bridge requires the configured memory regions to be preloaded with a pattern before use. This is done by the k3-ddrss driver from the R5 SPL in a 'for' loop. It takes around 10 seconds to fill 2GB of memory, for example. Memset can cut the time in half and using DMA currently yields a similar result.
The BIST engine of DDR controller provides support for initializing any memory region with a pattern. This bypasses the DDRSS bridge, so the required inline ECC data is not computed and populated in the memory. For some values like zero, the computed ECC syndrome is also zero and we can use these values to preload the memory from the DDR controller, without the assistance of the bridge.
The registers involved in the process are described in the 'DDR controller registers' topic in [1] AM62 and [2] J721E reference manuals.
The patch replaces the 'for' loop memory fill function with the BIST memory initialization procedure. This cuts the time to preload the 2GB memory from 10 seconds down to 1 second. The bist preload function uses the lpddr4 APIs in the k3-ddrss, so this is compatible with devices with both 16-bit LPDDR4 and 32-bit LPDDR4 interfaces (e.g J721E).
[1] AM62x: https://www.ti.com/lit/pdf/spruiv7 [2] DRA829/TDA4VM: https://www.ti.com/lit/zip/spruil1
Signed-off-by: Georgi Vlaev g-vlaev@ti.com Signed-off-by: Santhosh Kumar K s-k6@ti.com --- drivers/ram/k3-ddrss/k3-ddrss.c | 122 +++++++++++++++++++++++++++++--- 1 file changed, 114 insertions(+), 8 deletions(-)
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index a5c9b82cf1da..b656721e8e5b 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -7,6 +7,7 @@
#include <common.h> #include <config.h> +#include <time.h> #include <clk.h> #include <div64.h> #include <dm.h> @@ -554,14 +555,118 @@ static void k3_ddrss_set_ecc_range_r0(u32 base, u32 start_address, u32 size) writel((start_address + size - 1) >> 16, base + DDRSS_ECC_R0_END_ADDR_REG); }
-static void k3_ddrss_preload_ecc_mem_region(u32 *addr, u32 size, u32 word) +#define BIST_MODE_MEM_INIT 4 +#define BIST_MEM_INIT_TIMEOUT 10000 /* 1msec loops per block = 10s */ +static void k3_lpddr4_bist_init_mem_region(struct k3_ddrss_desc *ddrss, + u64 addr, u64 size, + u32 pattern) { - int i; + lpddr4_obj *driverdt = ddrss->driverdt; + lpddr4_privatedata *pd = &ddrss->pd; + u32 status, offset, regval; + bool int_status; + int i = 0; + + /* Set BIST_START_ADDR_0 [31:0] */ + regval = (u32)(addr & TH_FLD_MASK(LPDDR4__BIST_START_ADDRESS_0__FLD)); + TH_OFFSET_FROM_REG(LPDDR4__BIST_START_ADDRESS_0__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Set BIST_START_ADDR_1 [32 or 34:32] */ + regval = (u32)(addr >> TH_FLD_WIDTH(LPDDR4__BIST_START_ADDRESS_0__FLD)); + regval &= TH_FLD_MASK(LPDDR4__BIST_START_ADDRESS_1__FLD); + TH_OFFSET_FROM_REG(LPDDR4__BIST_START_ADDRESS_1__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Set ADDR_SPACE = log2(size) */ + regval = (u32)(ilog2(size) << TH_FLD_SHIFT(LPDDR4__ADDR_SPACE__FLD)); + TH_OFFSET_FROM_REG(LPDDR4__ADDR_SPACE__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Enable the BIST data check. On 32bit lpddr4 (e.g J7) this shares a + * register with ADDR_SPACE and BIST_GO. + */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_DATA_CHECK__REG, CTL_SHIFT, offset); + driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val); + regval |= TH_FLD_MASK(LPDDR4__BIST_DATA_CHECK__FLD); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + /* Clear the address check bit */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_ADDR_CHECK__REG, CTL_SHIFT, offset); + driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val); + regval &= ~TH_FLD_MASK(LPDDR4__BIST_ADDR_CHECK__FLD); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Set BIST_TEST_MODE[2:0] to memory initialize (4) */ + regval = BIST_MODE_MEM_INIT; + TH_OFFSET_FROM_REG(LPDDR4__BIST_TEST_MODE__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Set BIST_DATA_PATTERN[31:0] */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_DATA_PATTERN_0__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, pattern); + + /* Set BIST_DATA_PATTERN[63:32] */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_DATA_PATTERN_1__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, pattern); + + udelay(1000); + + /* Enable the programmed BIST operation - BIST_GO = 1 */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_GO__REG, CTL_SHIFT, offset); + driverdt->readreg(pd, LPDDR4_CTL_REGS, offset, ®val); + regval |= TH_FLD_MASK(LPDDR4__BIST_GO__FLD); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, regval); + + /* Wait for the BIST_DONE interrupt */ + while (i < BIST_MEM_INIT_TIMEOUT) { + status = driverdt->checkctlinterrupt(pd, LPDDR4_INTR_BIST_DONE, + &int_status); + if (!status & int_status) { + /* Clear LPDDR4_INTR_BIST_DONE */ + driverdt->ackctlinterrupt(pd, LPDDR4_INTR_BIST_DONE); + break; + } + udelay(1000); + i++; + }
- printf("ECC is enabled, priming DDR which will take several seconds.\n"); + /* Before continuing we have to stop BIST - BIST_GO = 0 */ + TH_OFFSET_FROM_REG(LPDDR4__BIST_GO__REG, CTL_SHIFT, offset); + driverdt->writereg(pd, LPDDR4_CTL_REGS, offset, 0); + + /* Timeout hit while priming the memory. We can't continue, + * since the memory is not fully initialized and we most + * likely get an uncorrectable error exception while booting. + */ + if (i == BIST_MEM_INIT_TIMEOUT) { + printf("ERROR: Timeout while priming the memory.\n"); + hang(); + } +}
- for (i = 0; i < (size / 4); i++) - addr[i] = word; +static void k3_ddrss_lpddr4_preload_full_mem(struct k3_ddrss_desc *ddrss, + u64 total_size, u32 pattern) +{ + u32 done, max_size2; + + /* Get the max size (log2) supported in this config (16/32 lpddr4) + * from the start_addess width - 16bit: 8G, 32bit: 32G + */ + max_size2 = TH_FLD_WIDTH(LPDDR4__BIST_START_ADDRESS_0__FLD) + + TH_FLD_WIDTH(LPDDR4__BIST_START_ADDRESS_1__FLD) + 1; + + /* ECC is enabled in dt but we can't preload the memory if + * the memory configuration is recognized and supported. + */ + if (!total_size || total_size > (1ull << max_size2) || + total_size & (total_size - 1)) { + printf("ECC: the memory configuration is not supported\n"); + hang(); + } + printf("ECC is enabled, priming DDR which will take several seconds.\n"); + done = get_timer(0); + k3_lpddr4_bist_init_mem_region(ddrss, 0, total_size, pattern); + printf("ECC: priming DDR completed in %lu msec\n", get_timer(done)); }
static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss) @@ -589,9 +694,10 @@ static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss) writel(DDRSS_ECC_CTRL_REG_ECC_EN | DDRSS_ECC_CTRL_REG_RMW_EN | DDRSS_ECC_CTRL_REG_WR_ALLOC, base + DDRSS_ECC_CTRL_REG);
- /* Preload ECC Mem region with 0's */ - k3_ddrss_preload_ecc_mem_region((u32 *)ecc_region_start, ecc_range, - 0x00000000); + /* Preload the full memory with 0's using the BIST engine of + * the LPDDR4 controller. + */ + k3_ddrss_lpddr4_preload_full_mem(ddrss, gd->ram_size, 0);
/* Clear Error Count Register */ writel(0x1, base + DDRSS_ECC_1B_ERR_CNT_REG);
As R5 is a 32 bit processor, the RAM banks' base and size calculation is restricted to 32 bits, which results in wrong values if bank's base is greater than 32 bits or bank's size is greater than or equal to 4GB.
So, add k3_ddrss_ddr_bank_base_size_calc() to get the base address and size of RAM's banks from the device tree memory node, and store in a 64 bit device private data which can be used for ECC reserved memory calculation, Setting ECC range and Fixing up bank size in device tree when ECC is enabled.
Signed-off-by: Santhosh Kumar K s-k6@ti.com --- drivers/ram/k3-ddrss/k3-ddrss.c | 72 ++++++++++++++++++++++++++------- 1 file changed, 57 insertions(+), 15 deletions(-)
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index b656721e8e5b..06c4dba4b857 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -148,6 +148,9 @@ struct k3_ddrss_desc { struct k3_ddrss_ecc_region ecc_regions[K3_DDRSS_MAX_ECC_REGIONS]; u64 ecc_reserved_space; bool ti_ecc_enabled; + unsigned long long ddr_bank_base[CONFIG_NR_DRAM_BANKS]; + unsigned long long ddr_bank_size[CONFIG_NR_DRAM_BANKS]; + unsigned long long ddr_ram_size; };
struct reginitdata { @@ -669,11 +672,54 @@ static void k3_ddrss_lpddr4_preload_full_mem(struct k3_ddrss_desc *ddrss, printf("ECC: priming DDR completed in %lu msec\n", get_timer(done)); }
+static void k3_ddrss_ddr_bank_base_size_calc(struct k3_ddrss_desc *ddrss) +{ + int bank, na, ns, len, parent; + const fdt32_t *ptr, *end; + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + ddrss->ddr_bank_base[bank] = 0; + ddrss->ddr_bank_size[bank] = 0; + } + + ofnode mem = ofnode_null(); + + do { + mem = ofnode_by_prop_value(mem, "device_type", "memory", 7); + } while (!ofnode_is_enabled(mem)); + + const void *fdt = ofnode_to_fdt(mem); + int node = ofnode_to_offset(mem); + const char *property = "reg"; + + parent = fdt_parent_offset(fdt, node); + na = fdt_address_cells(fdt, parent); + ns = fdt_size_cells(fdt, parent); + ptr = fdt_getprop(fdt, node, property, &len); + end = ptr + len / sizeof(*ptr); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + if (ptr + na + ns <= end) { + if (CONFIG_IS_ENABLED(OF_TRANSLATE)) + ddrss->ddr_bank_base[bank] = fdt_translate_address(fdt, node, ptr); + else + ddrss->ddr_bank_base[bank] = fdtdec_get_number(ptr, na); + + ddrss->ddr_bank_size[bank] = fdtdec_get_number(&ptr[na], ns); + } + + ptr += na + ns; + } + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) + ddrss->ddr_ram_size += ddrss->ddr_bank_size[bank]; +} + static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss) { fdtdec_setup_mem_size_base_lowest();
- ddrss->ecc_reserved_space = gd->ram_size; + ddrss->ecc_reserved_space = ddrss->ddr_ram_size; do_div(ddrss->ecc_reserved_space, 9);
/* Round to clean number */ @@ -697,7 +743,7 @@ static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss) /* Preload the full memory with 0's using the BIST engine of * the LPDDR4 controller. */ - k3_ddrss_lpddr4_preload_full_mem(ddrss, gd->ram_size, 0); + k3_ddrss_lpddr4_preload_full_mem(ddrss, ddrss->ddr_ram_size, 0);
/* Clear Error Count Register */ writel(0x1, base + DDRSS_ECC_1B_ERR_CNT_REG); @@ -742,6 +788,8 @@ static int k3_ddrss_probe(struct udevice *dev)
k3_lpddr4_start(ddrss);
+ k3_ddrss_ddr_bank_base_size_calc(ddrss); + if (ddrss->ti_ecc_enabled) { if (!ddrss->ddrss_ss_cfg) { printf("%s: ss_cfg is required if ecc is enabled but not provided.", @@ -762,30 +810,24 @@ static int k3_ddrss_probe(struct udevice *dev)
int k3_ddrss_ddr_fdt_fixup(struct udevice *dev, void *blob, struct bd_info *bd) { - struct k3_ddrss_desc *ddrss = dev_get_priv(dev); - u64 start[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; int bank; + struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
if (ddrss->ecc_reserved_space == 0) return 0;
for (bank = CONFIG_NR_DRAM_BANKS - 1; bank >= 0; bank--) { - if (ddrss->ecc_reserved_space > bd->bi_dram[bank].size) { - ddrss->ecc_reserved_space -= bd->bi_dram[bank].size; - bd->bi_dram[bank].size = 0; + if (ddrss->ecc_reserved_space > ddrss->ddr_bank_size[bank]) { + ddrss->ecc_reserved_space -= ddrss->ddr_bank_size[bank]; + ddrss->ddr_bank_size[bank] = 0; } else { - bd->bi_dram[bank].size -= ddrss->ecc_reserved_space; + ddrss->ddr_bank_size[bank] -= ddrss->ecc_reserved_space; break; } }
- for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = bd->bi_dram[bank].start; - size[bank] = bd->bi_dram[bank].size; - } - - return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS); + return fdt_fixup_memory_banks(blob, ddrss->ddr_bank_base, + ddrss->ddr_bank_size, CONFIG_NR_DRAM_BANKS); }
static int k3_ddrss_get_info(struct udevice *dev, struct ram_info *info)
Setup the ECC region's start and range using the device private data, ddrss->ddr_bank_base[0] and ddrss->ddr_ram_size. Also, move start and range of ECC regions from 32 bits to 64 bits to accommodate for DDR greater than or equal to 4GB.
Signed-off-by: Santhosh Kumar K s-k6@ti.com --- drivers/ram/k3-ddrss/k3-ddrss.c | 16 ++++++++-------- 1 file changed, 8 insertions(+), 8 deletions(-)
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 06c4dba4b857..6cf680972808 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -122,8 +122,8 @@ struct k3_msmc { #define K3_DDRSS_MAX_ECC_REGIONS 3
struct k3_ddrss_ecc_region { - u32 start; - u32 range; + u64 start; + u64 range; };
struct k3_ddrss_desc { @@ -552,7 +552,7 @@ void k3_lpddr4_start(struct k3_ddrss_desc *ddrss) } }
-static void k3_ddrss_set_ecc_range_r0(u32 base, u32 start_address, u32 size) +static void k3_ddrss_set_ecc_range_r0(u32 base, u64 start_address, u64 size) { writel((start_address) >> 16, base + DDRSS_ECC_R0_STR_ADDR_REG); writel((start_address + size - 1) >> 16, base + DDRSS_ECC_R0_END_ADDR_REG); @@ -728,13 +728,13 @@ static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss)
static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss) { - u32 ecc_region_start = ddrss->ecc_regions[0].start; - u32 ecc_range = ddrss->ecc_regions[0].range; + u64 ecc_region_start = ddrss->ecc_regions[0].start; + u64 ecc_range = ddrss->ecc_regions[0].range; u32 base = (u32)ddrss->ddrss_ss_cfg; u32 val;
/* Only Program region 0 which covers full ddr space */ - k3_ddrss_set_ecc_range_r0(base, ecc_region_start - gd->ram_base, ecc_range); + k3_ddrss_set_ecc_range_r0(base, ecc_region_start - ddrss->ddr_bank_base[0], ecc_range);
/* Enable ECC, RMW, WR_ALLOC */ writel(DDRSS_ECC_CTRL_REG_ECC_EN | DDRSS_ECC_CTRL_REG_RMW_EN | @@ -800,8 +800,8 @@ static int k3_ddrss_probe(struct udevice *dev) k3_ddrss_lpddr4_ecc_calc_reserved_mem(ddrss);
/* Always configure one region that covers full DDR space */ - ddrss->ecc_regions[0].start = gd->ram_base; - ddrss->ecc_regions[0].range = gd->ram_size - ddrss->ecc_reserved_space; + ddrss->ecc_regions[0].start = ddrss->ddr_bank_base[0]; + ddrss->ecc_regions[0].range = ddrss->ddr_ram_size - ddrss->ecc_reserved_space; k3_ddrss_lpddr4_ecc_init(ddrss); }
Enable ECC 1-bit error, 2-bit error, multiple 1-bit error interrupts by setting the respective bits in the DDRSS_V2A_INT_SET_REG register.
Signed-off-by: Santhosh Kumar K s-k6@ti.com --- drivers/ram/k3-ddrss/k3-ddrss.c | 8 ++++++++ 1 file changed, 8 insertions(+)
diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c index 6cf680972808..5bc625fc2db6 100644 --- a/drivers/ram/k3-ddrss/k3-ddrss.c +++ b/drivers/ram/k3-ddrss/k3-ddrss.c @@ -46,6 +46,11 @@ #define DDRSS_ECC_R2_STR_ADDR_REG 0x0140 #define DDRSS_ECC_R2_END_ADDR_REG 0x0144 #define DDRSS_ECC_1B_ERR_CNT_REG 0x0150 +#define DDRSS_V2A_INT_SET_REG 0x00a8 + +#define DDRSS_V2A_INT_SET_REG_ECC1BERR_EN BIT(3) +#define DDRSS_V2A_INT_SET_REG_ECC2BERR_EN BIT(4) +#define DDRSS_V2A_INT_SET_REG_ECCM1BERR_EN BIT(5)
#define SINGLE_DDR_SUBSYSTEM 0x1 #define MULTI_DDR_SUBSYSTEM 0x2 @@ -748,6 +753,9 @@ static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss) /* Clear Error Count Register */ writel(0x1, base + DDRSS_ECC_1B_ERR_CNT_REG);
+ writel(DDRSS_V2A_INT_SET_REG_ECC1BERR_EN | DDRSS_V2A_INT_SET_REG_ECC2BERR_EN | + DDRSS_V2A_INT_SET_REG_ECCM1BERR_EN, base + DDRSS_V2A_INT_SET_REG); + /* Enable ECC Check */ val = readl(base + DDRSS_ECC_CTRL_REG); val |= DDRSS_ECC_CTRL_REG_ECC_CK;
From: Neha Malcom Francis n-francis@ti.com
Add CONFIG_K3_INLINE_ECC so that ECC functions can be compiled into R5 SPL only when the config has been enabled.
Signed-off-by: Neha Malcom Francis n-francis@ti.com --- drivers/ram/Kconfig | 10 ++++++++++ 1 file changed, 10 insertions(+)
diff --git a/drivers/ram/Kconfig b/drivers/ram/Kconfig index 9838a2798f92..5cee93fe68c8 100644 --- a/drivers/ram/Kconfig +++ b/drivers/ram/Kconfig @@ -107,6 +107,16 @@ config IMXRT_SDRAM to support external memories like sdram, psram & nand. This driver is for the sdram memory interface with the SEMC.
+config K3_INLINE_ECC + bool "Enable TI Inline ECC support" + depends on K3_DDRSS + help + Enable Inline ECC support on K3 platforms. 1/9th of the SDRAM space + is used for ECC storage and the rest 8/9th is available for system + use. Enabling ECC increases boot time as the ECC protected regions + need to be primed with a predefined value prior to enabling ECC + check. + source "drivers/ram/aspeed/Kconfig" source "drivers/ram/cadence/Kconfig" source "drivers/ram/octeon/Kconfig"
From: Neha Malcom Francis n-francis@ti.com
Set CONFIG_NR_DRAM_BANKS to 2 as we have two banks described in the memory/ node for lower and higher addressible DDR regions.
This allows use of FDT functions from fdt_support.c to set up and fixup the memory/ node correctly.
Signed-off-by: Neha Malcom Francis n-francis@ti.com --- configs/j7200_evm_r5_defconfig | 1 + configs/j721e_evm_r5_defconfig | 1 + configs/j721s2_evm_r5_defconfig | 1 + configs/j784s4_evm_r5_defconfig | 1 + 4 files changed, 4 insertions(+)
diff --git a/configs/j7200_evm_r5_defconfig b/configs/j7200_evm_r5_defconfig index e023af24674a..6494136d735a 100644 --- a/configs/j7200_evm_r5_defconfig +++ b/configs/j7200_evm_r5_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x70000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 CONFIG_SOC_K3_J721E=y CONFIG_K3_EARLY_CONS=y CONFIG_TARGET_J7200_R5_EVM=y diff --git a/configs/j721e_evm_r5_defconfig b/configs/j721e_evm_r5_defconfig index cea48b26136c..1c575e278c90 100644 --- a/configs/j721e_evm_r5_defconfig +++ b/configs/j721e_evm_r5_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x70000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 CONFIG_SOC_K3_J721E=y CONFIG_K3_EARLY_CONS=y CONFIG_TARGET_J721E_R5_EVM=y diff --git a/configs/j721s2_evm_r5_defconfig b/configs/j721s2_evm_r5_defconfig index 5ef5247a3e00..a6c2d7276e07 100644 --- a/configs/j721s2_evm_r5_defconfig +++ b/configs/j721s2_evm_r5_defconfig @@ -5,6 +5,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 CONFIG_SOC_K3_J721S2=y CONFIG_K3_EARLY_CONS=y CONFIG_TARGET_J721S2_R5_EVM=y diff --git a/configs/j784s4_evm_r5_defconfig b/configs/j784s4_evm_r5_defconfig index f5fe7432206b..bdb4d10e2f84 100644 --- a/configs/j784s4_evm_r5_defconfig +++ b/configs/j784s4_evm_r5_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_MALLOC_F_LEN=0x10000 CONFIG_SPL_GPIO=y CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y +CONFIG_NR_DRAM_BANKS=2 CONFIG_SOC_K3_J784S4=y CONFIG_K3_EARLY_CONS=y CONFIG_TARGET_J784S4_R5_EVM=y
As there are few redundant functions in board/ti/*/evm.c files, pull them to a common location of access to reuse and include the common file to access the functions.
Call k3-ddrss driver through fixup_ddr_driver_for_ecc() to fixup the device tree and resize the available amount of DDR, if ECC is enabled. Otherwise, fixup the device tree using the regular fdt_fixup_memory_banks().
Also call dram_init_banksize() after every call to fixup_ddr_driver_for_ecc() is made so that gd->bd is populated correctly.
Ensure that fixup_ddr_driver_for_ecc() is agnostic to the number of DDR controllers present.
Signed-off-by: Santhosh Kumar K s-k6@ti.com Signed-off-by: Neha Malcom Francis n-francis@ti.com --- board/ti/am62ax/evm.c | 17 ++++--- board/ti/am62px/evm.c | 18 ++++--- board/ti/am62x/evm.c | 63 ++++--------------------- board/ti/am64x/evm.c | 73 +++------------------------- board/ti/am65x/evm.c | 29 +----------- board/ti/common/Makefile | 1 + board/ti/common/k3-ddr-init.c | 89 +++++++++++++++++++++++++++++++++++ board/ti/common/k3-ddr-init.h | 15 ++++++ board/ti/j721e/evm.c | 29 +----------- board/ti/j721s2/evm.c | 35 ++++---------- board/ti/j784s4/evm.c | 17 ++++--- 11 files changed, 163 insertions(+), 223 deletions(-) create mode 100644 board/ti/common/k3-ddr-init.c create mode 100644 board/ti/common/k3-ddr-init.h
diff --git a/board/ti/am62ax/evm.c b/board/ti/am62ax/evm.c index 62d3664936e7..3d7bd369a452 100644 --- a/board/ti/am62ax/evm.c +++ b/board/ti/am62ax/evm.c @@ -14,21 +14,24 @@ #include <spl.h>
#include "../common/fdt_ops.h" +#include "../common/k3-ddr-init.h"
int board_init(void) { return 0; }
-int dram_init(void) +#if defined(CONFIG_SPL_BUILD) +void spl_perform_fixups(struct spl_image_info *spl_image) { - return fdtdec_setup_mem_size_base(); -} - -int dram_init_banksize(void) -{ - return fdtdec_setup_memory_banksize(); + if (IS_ENABLED(CONFIG_K3_DDRSS)) { + if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) + fixup_ddr_driver_for_ecc(spl_image); + } else { + fixup_memory_node(spl_image); + } } +#endif
#ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) diff --git a/board/ti/am62px/evm.c b/board/ti/am62px/evm.c index 97a95ce8cc2d..aa7db61eb411 100644 --- a/board/ti/am62px/evm.c +++ b/board/ti/am62px/evm.c @@ -13,17 +13,21 @@ #include <fdt_support.h> #include <spl.h>
+#include "../common/k3-ddr-init.h" + int board_init(void) { return 0; }
-int dram_init(void) -{ - return fdtdec_setup_mem_size_base(); -} - -int dram_init_banksize(void) +#if defined(CONFIG_SPL_BUILD) +void spl_perform_fixups(struct spl_image_info *spl_image) { - return fdtdec_setup_memory_banksize(); + if (IS_ENABLED(CONFIG_K3_DDRSS)) { + if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) + fixup_ddr_driver_for_ecc(spl_image); + } else { + fixup_memory_node(spl_image); + } } +#endif diff --git a/board/ti/am62x/evm.c b/board/ti/am62x/evm.c index b3e8680dfab2..32ba37963212 100644 --- a/board/ti/am62x/evm.c +++ b/board/ti/am62x/evm.c @@ -21,6 +21,8 @@
#include "../common/fdt_ops.h"
+#include "../common/k3-ddr-init.h" + DECLARE_GLOBAL_DATA_PTR;
#if CONFIG_IS_ENABLED(SPLASH_SCREEN) @@ -51,11 +53,6 @@ int board_init(void) return 0; }
-int dram_init(void) -{ - return fdtdec_setup_mem_size_base(); -} - #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void) { @@ -64,11 +61,6 @@ int board_late_init(void) } #endif
-int dram_init_banksize(void) -{ - return fdtdec_setup_memory_banksize(); -} - #if defined(CONFIG_SPL_BUILD)
void spl_board_init(void) @@ -79,52 +71,13 @@ void spl_board_init(void)
}
-#if defined(CONFIG_K3_AM64_DDRSS) -static void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image) -{ - struct udevice *dev; - int ret; - - dram_init_banksize(); - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) - panic("Cannot get RAM device for ddr size fixup: %d\n", ret); - - ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd); - if (ret) - printf("Error fixing up ddr node for ECC use! %d\n", ret); -} -#else -static void fixup_memory_node(struct spl_image_info *spl_image) -{ - u64 start[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; - int bank; - int ret; - - dram_init(); - dram_init_banksize(); - - for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = gd->bd->bi_dram[bank].start; - size[bank] = gd->bd->bi_dram[bank].size; - } - - /* dram_init functions use SPL fdt, and we must fixup u-boot fdt */ - ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, - CONFIG_NR_DRAM_BANKS); - if (ret) - printf("Error fixing up memory node! %d\n", ret); -} -#endif - void spl_perform_fixups(struct spl_image_info *spl_image) { -#if defined(CONFIG_K3_AM64_DDRSS) - fixup_ddr_driver_for_ecc(spl_image); -#else - fixup_memory_node(spl_image); -#endif + if (IS_ENABLED(CONFIG_K3_DDRSS)) { + if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) + fixup_ddr_driver_for_ecc(spl_image); + } else { + fixup_memory_node(spl_image); + } } #endif diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c index b8de69da06c5..e63f2d028263 100644 --- a/board/ti/am64x/evm.c +++ b/board/ti/am64x/evm.c @@ -17,6 +17,7 @@
#include "../common/board_detect.h" #include "../common/fdt_ops.h" +#include "../common/k3-ddr-init.h"
#define board_is_am64x_gpevm() (board_ti_k3_is("AM64-GPEVM") || \ board_ti_k3_is("AM64-EVM") || \ @@ -32,28 +33,6 @@ int board_init(void) return 0; }
-int dram_init(void) -{ - s32 ret; - - ret = fdtdec_setup_mem_size_base(); - if (ret) - printf("Error setting up mem size and base. %d\n", ret); - - return ret; -} - -int dram_init_banksize(void) -{ - s32 ret; - - ret = fdtdec_setup_memory_banksize(); - if (ret) - printf("Error setting up memory banksize. %d\n", ret); - - return ret; -} - #if defined(CONFIG_SPL_LOAD_FIT) int board_fit_config_name_match(const char *name) { @@ -98,52 +77,14 @@ static int fixup_usb_boot(const void *fdt_blob) } #endif
-#if defined(CONFIG_K3_AM64_DDRSS) -static void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image) -{ - struct udevice *dev; - int ret; - - dram_init_banksize(); - - ret = uclass_get_device(UCLASS_RAM, 0, &dev); - if (ret) - panic("Cannot get RAM device for ddr size fixup: %d\n", ret); - - ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd); - if (ret) - printf("Error fixing up ddr node for ECC use! %d\n", ret); -} -#else -static void fixup_memory_node(struct spl_image_info *spl_image) -{ - u64 start[CONFIG_NR_DRAM_BANKS]; - u64 size[CONFIG_NR_DRAM_BANKS]; - int bank; - int ret; - - dram_init(); - dram_init_banksize(); - - for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { - start[bank] = gd->bd->bi_dram[bank].start; - size[bank] = gd->bd->bi_dram[bank].size; - } - - /* dram_init functions use SPL fdt, and we must fixup u-boot fdt */ - ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, CONFIG_NR_DRAM_BANKS); - if (ret) - printf("Error fixing up memory node! %d\n", ret); -} -#endif - void spl_perform_fixups(struct spl_image_info *spl_image) { -#if defined(CONFIG_K3_AM64_DDRSS) - fixup_ddr_driver_for_ecc(spl_image); -#else - fixup_memory_node(spl_image); -#endif + if (IS_ENABLED(CONFIG_K3_DDRSS)) { + if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) + fixup_ddr_driver_for_ecc(spl_image); + } else { + fixup_memory_node(spl_image); + }
#if CONFIG_IS_ENABLED(USB_STORAGE) fixup_usb_boot(spl_image->fdt_addr); diff --git a/board/ti/am65x/evm.c b/board/ti/am65x/evm.c index 07073a5940b1..ea60752d3719 100644 --- a/board/ti/am65x/evm.c +++ b/board/ti/am65x/evm.c @@ -23,6 +23,7 @@
#include "../common/board_detect.h" #include "../common/fdt_ops.h" +#include "../common/k3-ddr-init.h"
#define board_is_am65x_base_board() board_ti_is("AM6-COMPROCEVM")
@@ -49,17 +50,6 @@ int board_init(void) return 0; }
-int dram_init(void) -{ -#ifdef CONFIG_PHYS_64BIT - gd->ram_size = 0x100000000; -#else - gd->ram_size = 0x80000000; -#endif - - return 0; -} - phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_PHYS_64BIT @@ -71,23 +61,6 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) return gd->ram_top; }
-int dram_init_banksize(void) -{ - /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = 0x80000000; - gd->bd->bi_dram[0].size = 0x80000000; - gd->ram_size = 0x80000000; - -#ifdef CONFIG_PHYS_64BIT - /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = 0x880000000; - gd->bd->bi_dram[1].size = 0x80000000; - gd->ram_size = 0x100000000; -#endif - - return 0; -} - #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { diff --git a/board/ti/common/Makefile b/board/ti/common/Makefile index 5ac361ba7fcf..070dec3aebf5 100644 --- a/board/ti/common/Makefile +++ b/board/ti/common/Makefile @@ -4,3 +4,4 @@ obj-${CONFIG_TI_I2C_BOARD_DETECT} += board_detect.o obj-${CONFIG_CMD_EXTENSION} += cape_detect.o obj-${CONFIG_OF_LIBFDT} += fdt_ops.o +obj-${CONFIG_ARCH_K3} += k3-ddr-init.o diff --git a/board/ti/common/k3-ddr-init.c b/board/ti/common/k3-ddr-init.c new file mode 100644 index 000000000000..228b95774b97 --- /dev/null +++ b/board/ti/common/k3-ddr-init.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0+ +/* + * Copyright (C) 2023, Texas Instruments Incorporated - https://www.ti.com/ + */ + +#include <fdt_support.h> +#include <dm/uclass.h> +#include <k3-ddrss.h> +#include <spl.h> + +#include "k3-ddr-init.h" + +int dram_init(void) +{ + s32 ret; + + ret = fdtdec_setup_mem_size_base_lowest(); + if (ret) + printf("Error setting up mem size and base. %d\n", ret); + + return ret; +} + +int dram_init_banksize(void) +{ + s32 ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + printf("Error setting up memory banksize. %d\n", ret); + + return ret; +} + +#if defined(CONFIG_SPL_BUILD) + +void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image) +{ + struct udevice *dev; + int ret, ctr = 1; + + dram_init_banksize(); + + ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) + panic("Cannnot get RAM device for ddr size fixup: %d\n", ret); + + ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd); + if (ret) + printf("Error fixing up ddr node for ECC use! %d\n", ret); + + dram_init_banksize(); + + ret = uclass_next_device_err(&dev); + + while (!ret) { + ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd); + if (ret) + printf("Error fixing up ddr node %d for ECC use! %d\n", ctr, ret); + + dram_init_banksize(); + ret = uclass_next_device_err(&dev); + ctr++; + } +} + +void fixup_memory_node(struct spl_image_info *spl_image) +{ + u64 start[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + int bank; + int ret; + + dram_init(); + dram_init_banksize(); + + for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + start[bank] = gd->bd->bi_dram[bank].start; + size[bank] = gd->bd->bi_dram[bank].size; + } + + ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, + CONFIG_NR_DRAM_BANKS); + + if (ret) + printf("Error fixing up memory node! %d\n", ret); +} + +#endif diff --git a/board/ti/common/k3-ddr-init.h b/board/ti/common/k3-ddr-init.h new file mode 100644 index 000000000000..9d1826815dfd --- /dev/null +++ b/board/ti/common/k3-ddr-init.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Copyright (C) 2023, Texas Instruments Incorporated - https://www.ti.com/ + */ + +#ifndef __K3_DDR_INIT_H +#define __K3_DDR_INIT_H + +int dram_init(void); +int dram_init_banksize(void); + +void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image); +void fixup_memory_node(struct spl_image_info *spl_image); + +#endif /* __K3_DDR_INIT_H */ diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index 539eaf47186a..e0cd8529bc2b 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -17,6 +17,7 @@
#include "../common/board_detect.h" #include "../common/fdt_ops.h" +#include "../common/k3-ddr-init.h"
#define board_is_j721e_som() (board_ti_k3_is("J721EX-PM1-SOM") || \ board_ti_k3_is("J721EX-PM2-SOM")) @@ -37,17 +38,6 @@ int board_init(void) return 0; }
-int dram_init(void) -{ -#ifdef CONFIG_PHYS_64BIT - gd->ram_size = 0x100000000; -#else - gd->ram_size = 0x80000000; -#endif - - return 0; -} - phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_PHYS_64BIT @@ -59,23 +49,6 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) return gd->ram_top; }
-int dram_init_banksize(void) -{ - /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = 0x80000000; - gd->bd->bi_dram[0].size = 0x80000000; - gd->ram_size = 0x80000000; - -#ifdef CONFIG_PHYS_64BIT - /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = 0x880000000; - gd->bd->bi_dram[1].size = 0x80000000; - gd->ram_size = 0x100000000; -#endif - - return 0; -} - #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c index 5a0281d6b483..fca30107cddb 100644 --- a/board/ti/j721s2/evm.c +++ b/board/ti/j721s2/evm.c @@ -24,6 +24,7 @@
#include "../common/board_detect.h" #include "../common/fdt_ops.h" +#include "../common/k3-ddr-init.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -32,17 +33,6 @@ int board_init(void) return 0; }
-int dram_init(void) -{ -#ifdef CONFIG_PHYS_64BIT - gd->ram_size = 0x100000000; -#else - gd->ram_size = 0x80000000; -#endif - - return 0; -} - phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_PHYS_64BIT @@ -54,22 +44,17 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) return gd->ram_top; }
-int dram_init_banksize(void) +#if defined(CONFIG_SPL_BUILD) +void spl_perform_fixups(struct spl_image_info *spl_image) { - /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = 0x80000000; - gd->bd->bi_dram[0].size = 0x7fffffff; - gd->ram_size = 0x80000000; - -#ifdef CONFIG_PHYS_64BIT - /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = 0x880000000; - gd->bd->bi_dram[1].size = 0x37fffffff; - gd->ram_size = 0x400000000; -#endif - - return 0; + if (IS_ENABLED(CONFIG_K3_DDRSS)) { + if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) + fixup_ddr_driver_for_ecc(spl_image); + } else { + fixup_memory_node(spl_image); + } } +#endif
#ifdef CONFIG_TI_I2C_BOARD_DETECT /* diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c index aed0ea5b9495..73056a16dd5f 100644 --- a/board/ti/j784s4/evm.c +++ b/board/ti/j784s4/evm.c @@ -10,6 +10,7 @@ #include <init.h> #include <spl.h> #include "../common/fdt_ops.h" +#include "../common/k3-ddr-init.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -18,15 +19,17 @@ int board_init(void) return 0; }
-int dram_init(void) +#if defined(CONFIG_SPL_BUILD) +void spl_perform_fixups(struct spl_image_info *spl_image) { - return fdtdec_setup_mem_size_base(); -} - -int dram_init_banksize(void) -{ - return fdtdec_setup_memory_banksize(); + if (IS_ENABLED(CONFIG_K3_DDRSS)) { + if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) + fixup_ddr_driver_for_ecc(spl_image); + } else { + fixup_memory_node(spl_image); + } } +#endif
#ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void)
Hi Santhosh,
thanks for this series!
Am 23.05.24 um 07:04 schrieb Santhosh Kumar K:
As there are few redundant functions in board/ti/*/evm.c files, pull them to a common location of access to reuse and include the common file to access the functions.
Call k3-ddrss driver through fixup_ddr_driver_for_ecc() to fixup the device tree and resize the available amount of DDR, if ECC is enabled. Otherwise, fixup the device tree using the regular fdt_fixup_memory_banks().
Also call dram_init_banksize() after every call to fixup_ddr_driver_for_ecc() is made so that gd->bd is populated correctly.
Ensure that fixup_ddr_driver_for_ecc() is agnostic to the number of DDR controllers present.
Signed-off-by: Santhosh Kumar K s-k6@ti.com Signed-off-by: Neha Malcom Francis n-francis@ti.com
[...]
+++ b/board/ti/common/k3-ddr-init.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2023, Texas Instruments Incorporated - https://www.ti.com/
- */
+#include <fdt_support.h> +#include <dm/uclass.h> +#include <k3-ddrss.h> +#include <spl.h>
+#include "k3-ddr-init.h"
+int dram_init(void) +{
- s32 ret;
- ret = fdtdec_setup_mem_size_base_lowest();
- if (ret)
printf("Error setting up mem size and base. %d\n", ret);- return ret;
+}
+int dram_init_banksize(void) +{
- s32 ret;
- ret = fdtdec_setup_memory_banksize();
- if (ret)
printf("Error setting up memory banksize. %d\n", ret);- return ret;
+}
I'm wondering if we can generalize more.
What do you say if we keep dram_init() & dram_init_banksize() in the board code and move fixup_ddr_driver_for_ecc() & fixup_memory_node() to mach-k3 and make them available for all K3 based boards?
It looks like I will reuse the code for our boards and I assume other vendors too.
Regards, Wadim
+#if defined(CONFIG_SPL_BUILD)
+void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image) +{
- struct udevice *dev;
- int ret, ctr = 1;
- dram_init_banksize();
- ret = uclass_get_device(UCLASS_RAM, 0, &dev);
- if (ret)
panic("Cannnot get RAM device for ddr size fixup: %d\n", ret);- ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd);
- if (ret)
printf("Error fixing up ddr node for ECC use! %d\n", ret);- dram_init_banksize();
- ret = uclass_next_device_err(&dev);
- while (!ret) {
ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd);if (ret)printf("Error fixing up ddr node %d for ECC use! %d\n", ctr, ret);dram_init_banksize();ret = uclass_next_device_err(&dev);ctr++;- }
+}
+void fixup_memory_node(struct spl_image_info *spl_image) +{
- u64 start[CONFIG_NR_DRAM_BANKS];
- u64 size[CONFIG_NR_DRAM_BANKS];
- int bank;
- int ret;
- dram_init();
- dram_init_banksize();
- for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
start[bank] = gd->bd->bi_dram[bank].start;size[bank] = gd->bd->bi_dram[bank].size;- }
- ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size,
CONFIG_NR_DRAM_BANKS);- if (ret)
printf("Error fixing up memory node! %d\n", ret);+}
+#endif diff --git a/board/ti/common/k3-ddr-init.h b/board/ti/common/k3-ddr-init.h new file mode 100644 index 000000000000..9d1826815dfd --- /dev/null +++ b/board/ti/common/k3-ddr-init.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (C) 2023, Texas Instruments Incorporated - https://www.ti.com/
- */
+#ifndef __K3_DDR_INIT_H +#define __K3_DDR_INIT_H
+int dram_init(void); +int dram_init_banksize(void);
+void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image); +void fixup_memory_node(struct spl_image_info *spl_image);
+#endif /* __K3_DDR_INIT_H */ diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index 539eaf47186a..e0cd8529bc2b 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -17,6 +17,7 @@
#include "../common/board_detect.h" #include "../common/fdt_ops.h" +#include "../common/k3-ddr-init.h"
#define board_is_j721e_som() (board_ti_k3_is("J721EX-PM1-SOM") || \ board_ti_k3_is("J721EX-PM2-SOM")) @@ -37,17 +38,6 @@ int board_init(void) return 0; }
-int dram_init(void) -{ -#ifdef CONFIG_PHYS_64BIT
- gd->ram_size = 0x100000000;
-#else
- gd->ram_size = 0x80000000;
-#endif
- return 0;
-}
- phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_PHYS_64BIT
@@ -59,23 +49,6 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) return gd->ram_top; }
-int dram_init_banksize(void) -{
- /* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = 0x80000000;
- gd->bd->bi_dram[0].size = 0x80000000;
- gd->ram_size = 0x80000000;
-#ifdef CONFIG_PHYS_64BIT
- /* Bank 1 declares the memory available in the DDR high region */
- gd->bd->bi_dram[1].start = 0x880000000;
- gd->bd->bi_dram[1].size = 0x80000000;
- gd->ram_size = 0x100000000;
-#endif
- return 0;
-}
- #ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) {
diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c index 5a0281d6b483..fca30107cddb 100644 --- a/board/ti/j721s2/evm.c +++ b/board/ti/j721s2/evm.c @@ -24,6 +24,7 @@
#include "../common/board_detect.h" #include "../common/fdt_ops.h" +#include "../common/k3-ddr-init.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -32,17 +33,6 @@ int board_init(void) return 0; }
-int dram_init(void) -{ -#ifdef CONFIG_PHYS_64BIT
- gd->ram_size = 0x100000000;
-#else
- gd->ram_size = 0x80000000;
-#endif
- return 0;
-}
- phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_PHYS_64BIT
@@ -54,22 +44,17 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) return gd->ram_top; }
-int dram_init_banksize(void) +#if defined(CONFIG_SPL_BUILD) +void spl_perform_fixups(struct spl_image_info *spl_image) {
- /* Bank 0 declares the memory available in the DDR low region */
- gd->bd->bi_dram[0].start = 0x80000000;
- gd->bd->bi_dram[0].size = 0x7fffffff;
- gd->ram_size = 0x80000000;
-#ifdef CONFIG_PHYS_64BIT
- /* Bank 1 declares the memory available in the DDR high region */
- gd->bd->bi_dram[1].start = 0x880000000;
- gd->bd->bi_dram[1].size = 0x37fffffff;
- gd->ram_size = 0x400000000;
-#endif
- return 0;
- if (IS_ENABLED(CONFIG_K3_DDRSS)) {
if (IS_ENABLED(CONFIG_K3_INLINE_ECC))fixup_ddr_driver_for_ecc(spl_image);- } else {
fixup_memory_node(spl_image);- } }
+#endif
#ifdef CONFIG_TI_I2C_BOARD_DETECT /* diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c index aed0ea5b9495..73056a16dd5f 100644 --- a/board/ti/j784s4/evm.c +++ b/board/ti/j784s4/evm.c @@ -10,6 +10,7 @@ #include <init.h> #include <spl.h> #include "../common/fdt_ops.h" +#include "../common/k3-ddr-init.h"
DECLARE_GLOBAL_DATA_PTR;
@@ -18,15 +19,17 @@ int board_init(void) return 0; }
-int dram_init(void) +#if defined(CONFIG_SPL_BUILD) +void spl_perform_fixups(struct spl_image_info *spl_image) {
- return fdtdec_setup_mem_size_base();
-}
-int dram_init_banksize(void) -{
- return fdtdec_setup_memory_banksize();
- if (IS_ENABLED(CONFIG_K3_DDRSS)) {
if (IS_ENABLED(CONFIG_K3_INLINE_ECC))fixup_ddr_driver_for_ecc(spl_image);- } else {
fixup_memory_node(spl_image);- } }
+#endif
#ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void)
Hi, Wadim,
Thanks for the review.
On 30/05/24 17:48, Wadim Egorov wrote:
Hi Santhosh,
thanks for this series!
Am 23.05.24 um 07:04 schrieb Santhosh Kumar K:
As there are few redundant functions in board/ti/*/evm.c files, pull them to a common location of access to reuse and include the common file to access the functions.
Call k3-ddrss driver through fixup_ddr_driver_for_ecc() to fixup the device tree and resize the available amount of DDR, if ECC is enabled. Otherwise, fixup the device tree using the regular fdt_fixup_memory_banks().
Also call dram_init_banksize() after every call to fixup_ddr_driver_for_ecc() is made so that gd->bd is populated correctly.
Ensure that fixup_ddr_driver_for_ecc() is agnostic to the number of DDR controllers present.
Signed-off-by: Santhosh Kumar K s-k6@ti.com Signed-off-by: Neha Malcom Francis n-francis@ti.com
[...]
+++ b/board/ti/common/k3-ddr-init.c @@ -0,0 +1,89 @@ +// SPDX-License-Identifier: GPL-2.0+ +/*
- Copyright (C) 2023, Texas Instruments Incorporated -
- */
+#include <fdt_support.h> +#include <dm/uclass.h> +#include <k3-ddrss.h> +#include <spl.h>
+#include "k3-ddr-init.h"
+int dram_init(void) +{ + s32 ret;
+ ret = fdtdec_setup_mem_size_base_lowest(); + if (ret) + printf("Error setting up mem size and base. %d\n", ret);
+ return ret; +}
+int dram_init_banksize(void) +{ + s32 ret;
+ ret = fdtdec_setup_memory_banksize(); + if (ret) + printf("Error setting up memory banksize. %d\n", ret);
+ return ret; +}
I'm wondering if we can generalize more.
What do you say if we keep dram_init() & dram_init_banksize() in the board code and move fixup_ddr_driver_for_ecc() & fixup_memory_node() to mach-k3 and make them available for all K3 based boards?
It looks like I will reuse the code for our boards and I assume other vendors too.
Regards, Wadim
Yeah, makes sense, will work on it and post v4.
Regards, Santhosh.
+#if defined(CONFIG_SPL_BUILD)
+void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image) +{ + struct udevice *dev; + int ret, ctr = 1;
+ dram_init_banksize();
+ ret = uclass_get_device(UCLASS_RAM, 0, &dev); + if (ret) + panic("Cannnot get RAM device for ddr size fixup: %d\n", ret);
+ ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd); + if (ret) + printf("Error fixing up ddr node for ECC use! %d\n", ret);
+ dram_init_banksize();
+ ret = uclass_next_device_err(&dev);
+ while (!ret) { + ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd); + if (ret) + printf("Error fixing up ddr node %d for ECC use! %d\n", ctr, ret);
+ dram_init_banksize(); + ret = uclass_next_device_err(&dev); + ctr++; + } +}
+void fixup_memory_node(struct spl_image_info *spl_image) +{ + u64 start[CONFIG_NR_DRAM_BANKS]; + u64 size[CONFIG_NR_DRAM_BANKS]; + int bank; + int ret;
+ dram_init(); + dram_init_banksize();
+ for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) { + start[bank] = gd->bd->bi_dram[bank].start; + size[bank] = gd->bd->bi_dram[bank].size; + }
+ ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, + CONFIG_NR_DRAM_BANKS);
+ if (ret) + printf("Error fixing up memory node! %d\n", ret); +}
+#endif diff --git a/board/ti/common/k3-ddr-init.h b/board/ti/common/k3-ddr-init.h new file mode 100644 index 000000000000..9d1826815dfd --- /dev/null +++ b/board/ti/common/k3-ddr-init.h @@ -0,0 +1,15 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Copyright (C) 2023, Texas Instruments Incorporated -
- */
+#ifndef __K3_DDR_INIT_H +#define __K3_DDR_INIT_H
+int dram_init(void); +int dram_init_banksize(void);
+void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image); +void fixup_memory_node(struct spl_image_info *spl_image);
+#endif /* __K3_DDR_INIT_H */ diff --git a/board/ti/j721e/evm.c b/board/ti/j721e/evm.c index 539eaf47186a..e0cd8529bc2b 100644 --- a/board/ti/j721e/evm.c +++ b/board/ti/j721e/evm.c @@ -17,6 +17,7 @@ #include "../common/board_detect.h" #include "../common/fdt_ops.h" +#include "../common/k3-ddr-init.h" #define board_is_j721e_som() (board_ti_k3_is("J721EX-PM1-SOM") || \ board_ti_k3_is("J721EX-PM2-SOM")) @@ -37,17 +38,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ -#ifdef CONFIG_PHYS_64BIT - gd->ram_size = 0x100000000; -#else - gd->ram_size = 0x80000000; -#endif
- return 0; -}
phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_PHYS_64BIT @@ -59,23 +49,6 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) return gd->ram_top; } -int dram_init_banksize(void) -{ - /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = 0x80000000; - gd->bd->bi_dram[0].size = 0x80000000; - gd->ram_size = 0x80000000;
-#ifdef CONFIG_PHYS_64BIT - /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = 0x880000000; - gd->bd->bi_dram[1].size = 0x80000000; - gd->ram_size = 0x100000000; -#endif
- return 0; -}
#ifdef CONFIG_SPL_LOAD_FIT int board_fit_config_name_match(const char *name) { diff --git a/board/ti/j721s2/evm.c b/board/ti/j721s2/evm.c index 5a0281d6b483..fca30107cddb 100644 --- a/board/ti/j721s2/evm.c +++ b/board/ti/j721s2/evm.c @@ -24,6 +24,7 @@ #include "../common/board_detect.h" #include "../common/fdt_ops.h" +#include "../common/k3-ddr-init.h" DECLARE_GLOBAL_DATA_PTR; @@ -32,17 +33,6 @@ int board_init(void) return 0; } -int dram_init(void) -{ -#ifdef CONFIG_PHYS_64BIT - gd->ram_size = 0x100000000; -#else - gd->ram_size = 0x80000000; -#endif
- return 0; -}
phys_addr_t board_get_usable_ram_top(phys_size_t total_size) { #ifdef CONFIG_PHYS_64BIT @@ -54,22 +44,17 @@ phys_addr_t board_get_usable_ram_top(phys_size_t total_size) return gd->ram_top; } -int dram_init_banksize(void) +#if defined(CONFIG_SPL_BUILD) +void spl_perform_fixups(struct spl_image_info *spl_image) { - /* Bank 0 declares the memory available in the DDR low region */ - gd->bd->bi_dram[0].start = 0x80000000; - gd->bd->bi_dram[0].size = 0x7fffffff; - gd->ram_size = 0x80000000;
-#ifdef CONFIG_PHYS_64BIT - /* Bank 1 declares the memory available in the DDR high region */ - gd->bd->bi_dram[1].start = 0x880000000; - gd->bd->bi_dram[1].size = 0x37fffffff; - gd->ram_size = 0x400000000; -#endif
- return 0; + if (IS_ENABLED(CONFIG_K3_DDRSS)) { + if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) + fixup_ddr_driver_for_ecc(spl_image); + } else { + fixup_memory_node(spl_image); + } } +#endif #ifdef CONFIG_TI_I2C_BOARD_DETECT /* diff --git a/board/ti/j784s4/evm.c b/board/ti/j784s4/evm.c index aed0ea5b9495..73056a16dd5f 100644 --- a/board/ti/j784s4/evm.c +++ b/board/ti/j784s4/evm.c @@ -10,6 +10,7 @@ #include <init.h> #include <spl.h> #include "../common/fdt_ops.h" +#include "../common/k3-ddr-init.h" DECLARE_GLOBAL_DATA_PTR; @@ -18,15 +19,17 @@ int board_init(void) return 0; } -int dram_init(void) +#if defined(CONFIG_SPL_BUILD) +void spl_perform_fixups(struct spl_image_info *spl_image) { - return fdtdec_setup_mem_size_base(); -}
-int dram_init_banksize(void) -{ - return fdtdec_setup_memory_banksize(); + if (IS_ENABLED(CONFIG_K3_DDRSS)) { + if (IS_ENABLED(CONFIG_K3_INLINE_ECC)) + fixup_ddr_driver_for_ecc(spl_image); + } else { + fixup_memory_node(spl_image); + } } +#endif #ifdef CONFIG_BOARD_LATE_INIT int board_late_init(void)
Add ss_cfg memory region which maps the DDRSS configuration region for the memory controller node.
Signed-off-by: Santhosh Kumar K s-k6@ti.com Signed-off-by: Neha Malcom Francis n-francis@ti.com --- arch/arm/dts/k3-am62a-ddr.dtsi | 7 ++++--- arch/arm/dts/k3-j721s2-ddr.dtsi | 12 ++++++++---- arch/arm/dts/k3-j784s4-ddr.dtsi | 24 ++++++++++++++++-------- 3 files changed, 28 insertions(+), 15 deletions(-)
diff --git a/arch/arm/dts/k3-am62a-ddr.dtsi b/arch/arm/dts/k3-am62a-ddr.dtsi index 8629ea45b847..42e41f78505a 100644 --- a/arch/arm/dts/k3-am62a-ddr.dtsi +++ b/arch/arm/dts/k3-am62a-ddr.dtsi @@ -4,11 +4,12 @@ */
/ { - memorycontroller: memory-controller@f308000 { + memorycontroller: memory-controller@f300000 { compatible = "ti,am62a-ddrss"; reg = <0x00 0x0f308000 0x00 0x4000>, - <0x00 0x43014000 0x00 0x100>; - reg-names = "cfg", "ctrl_mmr_lp4"; + <0x00 0x43014000 0x00 0x100>, + <0x00 0x0f300000 0x00 0x200>; + reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; ti,ddr-freq1 = <DDRSS_PLL_FREQUENCY_1>; ti,ddr-freq2 = <DDRSS_PLL_FREQUENCY_2>; ti,ddr-fhs-cnt = <DDRSS_PLL_FHS_CNT>; diff --git a/arch/arm/dts/k3-j721s2-ddr.dtsi b/arch/arm/dts/k3-j721s2-ddr.dtsi index 345e2b84f9e8..9764085163c4 100644 --- a/arch/arm/dts/k3-j721s2-ddr.dtsi +++ b/arch/arm/dts/k3-j721s2-ddr.dtsi @@ -5,6 +5,8 @@
&main_navss { ranges = <0x00 0x00114000 0x00 0x00114000 0x00 0x00000100>, // ctrl_mmr_lpr + <0x00 0x02980000 0x00 0x02980000 0x00 0x00000200>, // ss cfg 0 + <0x00 0x029a0000 0x00 0x029a0000 0x00 0x00000200>, // ss cfg 1 <0x00 0x02990000 0x00 0x02990000 0x00 0x00004000>, // ddr0 cfg <0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>; @@ -24,8 +26,9 @@ memorycontroller0: memorycontroller@2990000 { compatible = "ti,j721s2-ddrss"; reg = <0x0 0x02990000 0x0 0x4000>, - <0x0 0x0114000 0x0 0x100>; - reg-names = "cfg", "ctrl_mmr_lp4"; + <0x0 0x0114000 0x0 0x100>, + <0x0 0x02980000 0x0 0x200>; + reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; power-domains = <&k3_pds 138 TI_SCI_PD_SHARED>, <&k3_pds 96 TI_SCI_PD_SHARED>; clocks = <&k3_clks 138 0>, <&k3_clks 43 2>; @@ -2232,8 +2235,9 @@ memorycontroller1: memorycontroller@29b0000 { compatible = "ti,j721s2-ddrss"; reg = <0x0 0x029b0000 0x0 0x4000>, - <0x0 0x0114000 0x0 0x100>; - reg-names = "cfg", "ctrl_mmr_lp4"; + <0x0 0x0114000 0x0 0x100>, + <0x0 0x029a0000 0x0 0x200>; + reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; power-domains = <&k3_pds 139 TI_SCI_PD_SHARED>, <&k3_pds 97 TI_SCI_PD_SHARED>; clocks = <&k3_clks 139 0>, <&k3_clks 43 2>; diff --git a/arch/arm/dts/k3-j784s4-ddr.dtsi b/arch/arm/dts/k3-j784s4-ddr.dtsi index 1c3242b0870c..fc74c539331e 100644 --- a/arch/arm/dts/k3-j784s4-ddr.dtsi +++ b/arch/arm/dts/k3-j784s4-ddr.dtsi @@ -9,6 +9,10 @@ <0x00 0x029b0000 0x00 0x029b0000 0x00 0x00004000>, // ddr1 cfg <0x00 0x029d0000 0x00 0x029d0000 0x00 0x00004000>, // ddr2 cfg <0x00 0x029f0000 0x00 0x029f0000 0x00 0x00004000>, // ddr3 cfg + <0x00 0x02980000 0x00 0x02980000 0x00 0x00000200>, // ss cfg 0 + <0x00 0x029a0000 0x00 0x029a0000 0x00 0x00000200>, // ss cfg 1 + <0x00 0x029c0000 0x00 0x029c0000 0x00 0x00000200>, // ss cfg 2 + <0x00 0x029e0000 0x00 0x029e0000 0x00 0x00000200>, // ss cfg 3 <0x00 0x30000000 0x00 0x30000000 0x00 0x0c400000>;
msmc0: msmc { @@ -26,8 +30,9 @@ memorycontroller0: memorycontroller@2990000 { compatible = "ti,j721s2-ddrss"; reg = <0x0 0x02990000 0x0 0x4000>, - <0x0 0x0114000 0x0 0x100>; - reg-names = "cfg", "ctrl_mmr_lp4"; + <0x0 0x0114000 0x0 0x100>, + <0x0 0x02980000 0x0 0x200>; + reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; power-domains = <&k3_pds 191 TI_SCI_PD_SHARED>, <&k3_pds 131 TI_SCI_PD_SHARED>; clocks = <&k3_clks 191 1>, <&k3_clks 78 2>; @@ -2234,8 +2239,9 @@ memorycontroller1: memorycontroller@29b0000 { compatible = "ti,j721s2-ddrss"; reg = <0x0 0x029b0000 0x0 0x4000>, - <0x0 0x0114000 0x0 0x100>; - reg-names = "cfg", "ctrl_mmr_lp4"; + <0x0 0x0114000 0x0 0x100>, + <0x0 0x029a0000 0x0 0x200>; + reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; power-domains = <&k3_pds 192 TI_SCI_PD_SHARED>, <&k3_pds 132 TI_SCI_PD_SHARED>; clocks = <&k3_clks 192 1>, <&k3_clks 78 2>; @@ -4442,8 +4448,9 @@ memorycontroller2: memorycontroller@29d0000 { compatible = "ti,j721s2-ddrss"; reg = <0x0 0x029d0000 0x0 0x4000>, - <0x0 0x0114000 0x0 0x100>; - reg-names = "cfg", "ctrl_mmr_lp4"; + <0x0 0x0114000 0x0 0x100>, + <0x0 0x029c0000 0x0 0x200>; + reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; power-domains = <&k3_pds 193 TI_SCI_PD_SHARED>, <&k3_pds 133 TI_SCI_PD_SHARED>; clocks = <&k3_clks 193 1>, <&k3_clks 78 2>; @@ -6650,8 +6657,9 @@ memorycontroller3: memorycontroller@29f0000 { compatible = "ti,j721s2-ddrss"; reg = <0x0 0x029f0000 0x0 0x4000>, - <0x0 0x0114000 0x0 0x100>; - reg-names = "cfg", "ctrl_mmr_lp4"; + <0x0 0x0114000 0x0 0x100>, + <0x0 0x29e0000 0x0 0x200>; + reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg"; power-domains = <&k3_pds 194 TI_SCI_PD_SHARED>, <&k3_pds 139 TI_SCI_PD_SHARED>; clocks = <&k3_clks 194 1>, <&k3_clks 78 2>;
participants (2)
-
Santhosh Kumar K -
Wadim Egorov