[PATCH v1 1/1] x86: tangier: Fix DMA controller IRQ polarity in CSRT
IRQ polarity in CSRT has the same definition as by ACPI specification chapter 19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)", i.e. ActiveHigh is 0, and ActiveLow is 1. On Intel Tangier the DMA controller IRQ polarity is ActiveHigh.
Note, in DSDT (see southcluster.asl) it's described correctly.
Fixes: 5e99fde34a77 ("x86: tangier: Populate CSRT for shared DMA controller") Signed-off-by: Andy Shevchenko andriy.shevchenko@linux.intel.com --- arch/x86/cpu/tangier/acpi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/arch/x86/cpu/tangier/acpi.c b/arch/x86/cpu/tangier/acpi.c index 41bd177e095f..82f4ce5a34a4 100644 --- a/arch/x86/cpu/tangier/acpi.c +++ b/arch/x86/cpu/tangier/acpi.c @@ -89,8 +89,8 @@ static u32 acpi_fill_csrt_dma(struct acpi_csrt_group *grp) si->mmio_base_low = 0xff192000; si->mmio_base_high = 0; si->gsi_interrupt = 32; - si->interrupt_polarity = 1; - si->interrupt_mode = 0; + si->interrupt_polarity = 0; /* Active High */ + si->interrupt_mode = 0; /* Level triggered */ si->num_channels = 8; si->dma_address_width = 32; si->base_request_line = 0;
On Sat, Jul 31, 2021 at 4:15 AM Andy Shevchenko andriy.shevchenko@linux.intel.com wrote:
IRQ polarity in CSRT has the same definition as by ACPI specification chapter 19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)", i.e. ActiveHigh is 0, and ActiveLow is 1. On Intel Tangier the DMA controller IRQ polarity is ActiveHigh.
Note, in DSDT (see southcluster.asl) it's described correctly.
Fixes: 5e99fde34a77 ("x86: tangier: Populate CSRT for shared DMA controller") Signed-off-by: Andy Shevchenko andriy.shevchenko@linux.intel.com
arch/x86/cpu/tangier/acpi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
On Sat, Jul 31, 2021 at 7:44 AM Bin Meng bmeng.cn@gmail.com wrote:
On Sat, Jul 31, 2021 at 4:15 AM Andy Shevchenko andriy.shevchenko@linux.intel.com wrote:
IRQ polarity in CSRT has the same definition as by ACPI specification chapter 19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)", i.e. ActiveHigh is 0, and ActiveLow is 1. On Intel Tangier the DMA controller IRQ polarity is ActiveHigh.
Note, in DSDT (see southcluster.asl) it's described correctly.
Fixes: 5e99fde34a77 ("x86: tangier: Populate CSRT for shared DMA controller") Signed-off-by: Andy Shevchenko andriy.shevchenko@linux.intel.com
arch/x86/cpu/tangier/acpi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Bin Meng bmeng.cn@gmail.com
applied to u-boot-x86, thanks!
On Fri, 30 Jul 2021 at 14:15, Andy Shevchenko andriy.shevchenko@linux.intel.com wrote:
IRQ polarity in CSRT has the same definition as by ACPI specification chapter 19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)", i.e. ActiveHigh is 0, and ActiveLow is 1. On Intel Tangier the DMA controller IRQ polarity is ActiveHigh.
Note, in DSDT (see southcluster.asl) it's described correctly.
Fixes: 5e99fde34a77 ("x86: tangier: Populate CSRT for shared DMA controller") Signed-off-by: Andy Shevchenko andriy.shevchenko@linux.intel.com
arch/x86/cpu/tangier/acpi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
Hi Simon,
On Sat, Jul 31, 2021 at 9:03 AM Simon Glass sjg@chromium.org wrote:
On Fri, 30 Jul 2021 at 14:15, Andy Shevchenko andriy.shevchenko@linux.intel.com wrote:
IRQ polarity in CSRT has the same definition as by ACPI specification chapter 19.6.64 "Interrupt (Interrupt Resource Descriptor Macro)", i.e. ActiveHigh is 0, and ActiveLow is 1. On Intel Tangier the DMA controller IRQ polarity is ActiveHigh.
Note, in DSDT (see southcluster.asl) it's described correctly.
Fixes: 5e99fde34a77 ("x86: tangier: Populate CSRT for shared DMA controller") Signed-off-by: Andy Shevchenko andriy.shevchenko@linux.intel.com
arch/x86/cpu/tangier/acpi.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
Reviewed-by: Simon Glass sjg@chromium.org
Oops, this was applied 1 minute earlier :-)
I've added your RB tag manually.
Regards, Bin
participants (3)
-
Andy Shevchenko -
Bin Meng -
Simon Glass