[U-Boot] [PATCHv2 00/47] powerpc: Enable PCIe DM drvier for some platforms
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Enable PCIe DM driver for some PowerPC platforms which has supported device tree.
Depends on the following 2 series: http://patchwork.ozlabs.org/project/uboot/list/?series=120960 http://patchwork.ozlabs.org/project/uboot/list/?series=115008
Hou Zhiqiang (47): powerpc: T208xRDB: Compile legacy PCIe routines conditionally powerpc: T208xRDB: Disable legacy PCIe driver when DM_PCI is enabled configs: T2080RDB: Enable PCIe driver powerpc: T4RDB: Compile legacy PCIe routines conditionally dm: pcie_fsl: Add T4240 PCIe support t4240: dts: Added PCIe DT nodes powerpc: T4240RDB: Disable legacy PCIe driver when DM_PCI is enabled configs: T4240RDB: Enable PCIe driver powerpc: T102xRDB: Compile legacy PCIe routines conditionally dm: pcie_fsl: Add T102x PCIe support t102x: dts: Added PCIe DT nodes powerpc: T102xRDB: Remove the useless macro CONFIG_ARCH_T1040 powerpc: T102xRDB: Disable legacy PCIe driver when DM_PCI is enabled configs: T1024RDB: Enable PCIe driver powerpc: T104xRDB: Compile legacy PCIe routines conditionally dm: pcie_fsl: Add T104x PCIe support t104x: dts: Added PCIe DT nodes powerpc: T104xRDB: Disable legacy PCIe driver when DM_PCI is enabled configs: T1042D4RDB: Enable PCIe driver powerpc: p1_p2_rdb: Compile legacy PCIe routines conditionally dm: pcie_fsl: Add PCIe support for P1 and P2 series SoCs P1020: dts: Added PCIe DT nodes powerpc: p1_p2_rdb: Disable legacy PCIe driver when DM_PCI is enabled configs: P1020RDB: Enable PCIe driver P2020: dts: Added PCIe DT nodes configs: P2020RDB: Enable PCIe driver powerpc: p_corenet: Compile legacy PCIe routines conditionally dm: pcie_fsl: Add P2041 PCIe support P2041: dts: Added PCIe DT nodes powerpc: P2041RDB: Disable legacy PCIe driver when DM_PCI is enabled configs: P2041RDB: Enable PCIe driver dm: pcie_fsl: Add P3041 PCIe support P3041: dts: Added PCIe DT nodes powerpc: corenet_ds: Disable legacy PCIe driver when DM_PCI is enabled configs: P3041DS: Enable PCIe driver dm: pcie_fsl: Add P4080 PCIe support P4080: dts: Added PCIe DT nodes configs: P4080DS: Enable PCIe driver dm: pcie_fsl: Add P5040 PCIe support P5040: dts: Added PCIe DT nodes configs: P5040DS: Enable PCIe driver powerpc: MPC8548CDS: Compile legacy PCIe routines conditionally powerpc: MPC85xxCDS: Disable legacy PCI fixup when DM_PCI is selected dm: pcie_fsl: Add MPC8548 PCIe support MPC8548: dts: Added PCIe DT node powerpc: MPC8548CDS: Disable legacy PCIe driver when DM_PCI is enabled configs: MPC8548CDS: Enable PCIe driver
arch/powerpc/dts/mpc8548-post.dtsi | 9 +++ arch/powerpc/dts/mpc8548cds.dts | 6 ++ arch/powerpc/dts/mpc8548cds_36b.dts | 6 ++ arch/powerpc/dts/p1020-post.dtsi | 20 +++++ arch/powerpc/dts/p1020rdb-pc.dts | 12 +++ arch/powerpc/dts/p1020rdb-pc_36b.dts | 12 +++ arch/powerpc/dts/p1020rdb-pd.dts | 12 +++ arch/powerpc/dts/p2020-post.dtsi | 30 ++++++++ arch/powerpc/dts/p2020rdb-pc.dts | 17 +++++ arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 +++++ arch/powerpc/dts/p2041.dtsi | 36 +++++++++ arch/powerpc/dts/p3041.dtsi | 48 ++++++++++++ arch/powerpc/dts/p4080.dtsi | 36 +++++++++ arch/powerpc/dts/p5040.dtsi | 36 +++++++++ arch/powerpc/dts/t102x.dtsi | 36 +++++++++ arch/powerpc/dts/t104x.dtsi | 48 ++++++++++++ arch/powerpc/dts/t4240.dtsi | 48 ++++++++++++ board/freescale/common/cds_pci_ft.c | 4 +- board/freescale/common/p_corenet/pci.c | 2 + board/freescale/mpc8548cds/mpc8548cds.c | 6 +- board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 4 +- board/freescale/t102xrdb/pci.c | 2 + board/freescale/t104xrdb/pci.c | 2 + board/freescale/t208xrdb/pci.c | 2 + board/freescale/t4rdb/pci.c | 2 + configs/MPC8548CDS_36BIT_defconfig | 4 + configs/MPC8548CDS_defconfig | 4 + configs/MPC8548CDS_legacy_defconfig | 4 + configs/P1020RDB-PC_36BIT_NAND_defconfig | 4 + configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 4 + configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 4 + configs/P1020RDB-PC_36BIT_defconfig | 4 + configs/P1020RDB-PC_NAND_defconfig | 4 + configs/P1020RDB-PC_SDCARD_defconfig | 4 + configs/P1020RDB-PC_SPIFLASH_defconfig | 4 + configs/P1020RDB-PC_defconfig | 4 + configs/P1020RDB-PD_NAND_defconfig | 4 + configs/P1020RDB-PD_SDCARD_defconfig | 4 + configs/P1020RDB-PD_SPIFLASH_defconfig | 4 + configs/P1020RDB-PD_defconfig | 4 + configs/P2020RDB-PC_36BIT_NAND_defconfig | 4 + configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 4 + configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 4 + configs/P2020RDB-PC_36BIT_defconfig | 4 + configs/P2020RDB-PC_NAND_defconfig | 4 + configs/P2020RDB-PC_SDCARD_defconfig | 4 + configs/P2020RDB-PC_SPIFLASH_defconfig | 4 + configs/P2020RDB-PC_defconfig | 4 + configs/P2041RDB_NAND_defconfig | 4 + configs/P2041RDB_SDCARD_defconfig | 4 + configs/P2041RDB_SPIFLASH_defconfig | 4 + configs/P2041RDB_defconfig | 4 + configs/P3041DS_NAND_defconfig | 4 + configs/P3041DS_SDCARD_defconfig | 4 + configs/P3041DS_SPIFLASH_defconfig | 4 + configs/P3041DS_defconfig | 4 + configs/P4080DS_SDCARD_defconfig | 4 + configs/P4080DS_SPIFLASH_defconfig | 4 + configs/P4080DS_defconfig | 4 + configs/P5040DS_NAND_defconfig | 4 + configs/P5040DS_SDCARD_defconfig | 4 + configs/P5040DS_SPIFLASH_defconfig | 4 + configs/P5040DS_defconfig | 4 + configs/T1024RDB_NAND_defconfig | 4 + configs/T1024RDB_SDCARD_defconfig | 4 + configs/T1024RDB_SPIFLASH_defconfig | 4 + configs/T1024RDB_defconfig | 4 + configs/T1042D4RDB_NAND_defconfig | 4 + configs/T1042D4RDB_SDCARD_defconfig | 4 + configs/T1042D4RDB_SPIFLASH_defconfig | 4 + configs/T1042D4RDB_defconfig | 4 + configs/T2080RDB_NAND_defconfig | 4 + configs/T2080RDB_SDCARD_defconfig | 4 + configs/T2080RDB_SPIFLASH_defconfig | 4 + configs/T2080RDB_defconfig | 4 + configs/T4240RDB_SDCARD_defconfig | 4 + configs/T4240RDB_defconfig | 4 + drivers/pci/pcie_fsl.c | 21 ++++++ include/configs/MPC8548CDS.h | 22 ++++-- include/configs/P2041RDB.h | 55 ++++---------- include/configs/T102xRDB.h | 78 ++++---------------- include/configs/T104xRDB.h | 38 +++++----- include/configs/T208xRDB.h | 36 ++++----- include/configs/T4240RDB.h | 35 +++++---- include/configs/corenet_ds.h | 63 +++++----------- include/configs/p1_p2_rdb_pc.h | 36 +++++---- 86 files changed, 822 insertions(+), 223 deletions(-)
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Compile the legacy PCIe initialization reoutines only when DM_PCI is not enabled.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
board/freescale/t208xrdb/pci.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/board/freescale/t208xrdb/pci.c b/board/freescale/t208xrdb/pci.c index 161b8cb403..adc128d924 100644 --- a/board/freescale/t208xrdb/pci.c +++ b/board/freescale/t208xrdb/pci.c @@ -11,6 +11,7 @@ #include <fdt_support.h> #include <asm/fsl_serdes.h>
+#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
include/configs/T208xRDB.h | 36 +++++++++++++++++++----------------- 1 file changed, 19 insertions(+), 17 deletions(-)
diff --git a/include/configs/T208xRDB.h b/include/configs/T208xRDB.h index ab92ca3b68..3d95c4afa2 100644 --- a/include/configs/T208xRDB.h +++ b/include/configs/T208xRDB.h @@ -433,49 +433,51 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE4 /* PCIE controller 4 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
/* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
#ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #define CONFIG_PCI_INDIRECT_BRIDGE +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Enable the DM PCIe driver in T2080RDB defconfig.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
configs/T2080RDB_NAND_defconfig | 4 ++++ configs/T2080RDB_SDCARD_defconfig | 4 ++++ configs/T2080RDB_SPIFLASH_defconfig | 4 ++++ configs/T2080RDB_defconfig | 4 ++++ 4 files changed, 16 insertions(+)
diff --git a/configs/T2080RDB_NAND_defconfig b/configs/T2080RDB_NAND_defconfig index dc2cc8b72d..a22c5bd061 100644 --- a/configs/T2080RDB_NAND_defconfig +++ b/configs/T2080RDB_NAND_defconfig @@ -60,6 +60,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y diff --git a/configs/T2080RDB_SDCARD_defconfig b/configs/T2080RDB_SDCARD_defconfig index 3e3ab3d51b..bcfbdf89c4 100644 --- a/configs/T2080RDB_SDCARD_defconfig +++ b/configs/T2080RDB_SDCARD_defconfig @@ -57,6 +57,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y diff --git a/configs/T2080RDB_SPIFLASH_defconfig b/configs/T2080RDB_SPIFLASH_defconfig index 32b94c4289..42b54738a5 100644 --- a/configs/T2080RDB_SPIFLASH_defconfig +++ b/configs/T2080RDB_SPIFLASH_defconfig @@ -58,6 +58,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y diff --git a/configs/T2080RDB_defconfig b/configs/T2080RDB_defconfig index c3388ce725..ad54f5ce83 100644 --- a/configs/T2080RDB_defconfig +++ b/configs/T2080RDB_defconfig @@ -44,6 +44,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Compile the legacy PCIe initialization reoutines only when DM_PCI is not enabled.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
board/freescale/t4rdb/pci.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/board/freescale/t4rdb/pci.c b/board/freescale/t4rdb/pci.c index 4100370e20..7d670e1a2f 100644 --- a/board/freescale/t4rdb/pci.c +++ b/board/freescale/t4rdb/pci.c @@ -11,6 +11,7 @@ #include <fdt_support.h> #include <asm/fsl_serdes.h>
+#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Add compatible string for T4240 PCIe.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
drivers/pci/pcie_fsl.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index d3d2c191e5..f15deb0495 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -618,6 +618,7 @@ static struct fsl_pcie_data t2080_data = {
static const struct udevice_id fsl_pcie_ids[] = { { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, + { .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data }, { } };
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
T4240 integrated 4 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 3.0, and this patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
arch/powerpc/dts/t4240.dtsi | 48 +++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+)
diff --git a/arch/powerpc/dts/t4240.dtsi b/arch/powerpc/dts/t4240.dtsi index 4d8fc7192e..fc34974c7f 100644 --- a/arch/powerpc/dts/t4240.dtsi +++ b/arch/powerpc/dts/t4240.dtsi @@ -99,4 +99,52 @@ clock-frequency = <0x0>; }; }; + + pcie@ffe240000 { + compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe240000 0x0 0x4000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe250000 { + compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe250000 0x0 0x4000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe260000 { + compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe260000 0x0 0x4000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe270000 { + compatible = "fsl,pcie-t4240", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe270000 0x0 0x4000>; /* registers */ + law_trgt_if = <3>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; };
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
include/configs/T4240RDB.h | 35 +++++++++++++++++++---------------- 1 file changed, 19 insertions(+), 16 deletions(-)
diff --git a/include/configs/T4240RDB.h b/include/configs/T4240RDB.h index 0accdc6119..57d8d171a7 100644 --- a/include/configs/T4240RDB.h +++ b/include/configs/T4240RDB.h @@ -61,7 +61,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE @@ -176,44 +175,48 @@
/* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
/* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* controller 4, Base address 203000 */ #define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
#ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #define CONFIG_PCI_INDIRECT_BRIDGE +#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Enable the DM PCIe driver in T4240RDB defconfig.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
configs/T4240RDB_SDCARD_defconfig | 4 ++++ configs/T4240RDB_defconfig | 4 ++++ 2 files changed, 8 insertions(+)
diff --git a/configs/T4240RDB_SDCARD_defconfig b/configs/T4240RDB_SDCARD_defconfig index 81a4bf0065..e1201fa4ab 100644 --- a/configs/T4240RDB_SDCARD_defconfig +++ b/configs/T4240RDB_SDCARD_defconfig @@ -51,6 +51,10 @@ CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y diff --git a/configs/T4240RDB_defconfig b/configs/T4240RDB_defconfig index 35c294a7f4..ad40baf4de 100644 --- a/configs/T4240RDB_defconfig +++ b/configs/T4240RDB_defconfig @@ -38,6 +38,10 @@ CONFIG_SPI_FLASH_SST=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Compile the legacy PCIe initialization reoutines only when DM_PCI is not enabled.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
board/freescale/t102xrdb/pci.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/board/freescale/t102xrdb/pci.c b/board/freescale/t102xrdb/pci.c index 161b8cb403..adc128d924 100644 --- a/board/freescale/t102xrdb/pci.c +++ b/board/freescale/t102xrdb/pci.c @@ -11,6 +11,7 @@ #include <fdt_support.h> #include <asm/fsl_serdes.h>
+#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Add compatible string for T102x PCIe.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
drivers/pci/pcie_fsl.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index f15deb0495..fd7aae59f7 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -617,6 +617,7 @@ static struct fsl_pcie_data t2080_data = { };
static const struct udevice_id fsl_pcie_ids[] = { + { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data }, { }
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
T102x integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
arch/powerpc/dts/t102x.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)
diff --git a/arch/powerpc/dts/t102x.dtsi b/arch/powerpc/dts/t102x.dtsi index 2393e316f8..c49fd21088 100644 --- a/arch/powerpc/dts/t102x.dtsi +++ b/arch/powerpc/dts/t102x.dtsi @@ -49,4 +49,40 @@ clock-frequency = <0x0>; }; }; + + pcie@ffe240000 { + compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe240000 0x0 0x1000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe250000 { + compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe260000 { + compatible = "fsl,pcie-t102x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; };
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Remove the macro CONFIG_ARCH_T1040 from the T102xRDB.h and the PCIE4 related macros, as there are only 3 PCIe controllers on T102x SoCs.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
include/configs/T102xRDB.h | 24 ------------------------ 1 file changed, 24 deletions(-)
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index 5ab51e3233..b76ce8d69f 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -494,9 +494,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#ifdef CONFIG_ARCH_T1040 -#define CONFIG_PCIE4 /* PCIE controller 4 */ -#endif #define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ #define CONFIG_PCI_INDIRECT_BRIDGE @@ -565,27 +562,6 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ #endif
-/* controller 4, Base address 203000, to be removed */ -#ifdef CONFIG_PCIE4 -#define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull -#else -#define CONFIG_SYS_PCIE4_MEM_BUS 0xb0000000 -#define CONFIG_SYS_PCIE4_MEM_PHYS 0xb0000000 -#endif -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ -#define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#else -#define CONFIG_SYS_PCIE4_IO_PHYS 0xf8030000 -#endif -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ -#endif - #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
include/configs/T102xRDB.h | 54 +++++++++++--------------------------- 1 file changed, 15 insertions(+), 39 deletions(-)
diff --git a/include/configs/T102xRDB.h b/include/configs/T102xRDB.h index b76ce8d69f..8c1434fb10 100644 --- a/include/configs/T102xRDB.h +++ b/include/configs/T102xRDB.h @@ -494,72 +494,48 @@ unsigned long get_board_ddr_clk(void); #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */ -#define CONFIG_PCI_INDIRECT_BRIDGE
#ifdef CONFIG_PCI /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #endif
/* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0x90000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ #endif
/* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 #endif + +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_PCI_INDIRECT_BRIDGE #endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Enable the DM PCIe driver in T1024RDB defconfig.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
configs/T1024RDB_NAND_defconfig | 4 ++++ configs/T1024RDB_SDCARD_defconfig | 4 ++++ configs/T1024RDB_SPIFLASH_defconfig | 4 ++++ configs/T1024RDB_defconfig | 4 ++++ 4 files changed, 16 insertions(+)
diff --git a/configs/T1024RDB_NAND_defconfig b/configs/T1024RDB_NAND_defconfig index e28e5cf8b3..de71aa86a2 100644 --- a/configs/T1024RDB_NAND_defconfig +++ b/configs/T1024RDB_NAND_defconfig @@ -64,6 +64,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y diff --git a/configs/T1024RDB_SDCARD_defconfig b/configs/T1024RDB_SDCARD_defconfig index f0ee09c6d4..519819c820 100644 --- a/configs/T1024RDB_SDCARD_defconfig +++ b/configs/T1024RDB_SDCARD_defconfig @@ -61,6 +61,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y diff --git a/configs/T1024RDB_SPIFLASH_defconfig b/configs/T1024RDB_SPIFLASH_defconfig index 2905613cd6..85f18058bb 100644 --- a/configs/T1024RDB_SPIFLASH_defconfig +++ b/configs/T1024RDB_SPIFLASH_defconfig @@ -62,6 +62,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y diff --git a/configs/T1024RDB_defconfig b/configs/T1024RDB_defconfig index 3d0219f092..5a9c8bc9da 100644 --- a/configs/T1024RDB_defconfig +++ b/configs/T1024RDB_defconfig @@ -48,6 +48,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_AQUANTIA=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Compile the legacy PCIe initialization reoutines only when DM_PCI is not enabled.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
board/freescale/t104xrdb/pci.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/board/freescale/t104xrdb/pci.c b/board/freescale/t104xrdb/pci.c index 9fd66594f4..6b666ba2d2 100644 --- a/board/freescale/t104xrdb/pci.c +++ b/board/freescale/t104xrdb/pci.c @@ -11,6 +11,7 @@ #include <fdt_support.h> #include <asm/fsl_serdes.h>
+#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Add compatible string for T104x PCIe.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
drivers/pci/pcie_fsl.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index fd7aae59f7..a085c0cab9 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -618,6 +618,7 @@ static struct fsl_pcie_data t2080_data = {
static const struct udevice_id fsl_pcie_ids[] = { { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data }, + { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t4240", .data = (ulong)&t2080_data }, { }
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
T104x integrated 4 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
arch/powerpc/dts/t104x.dtsi | 48 +++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+)
diff --git a/arch/powerpc/dts/t104x.dtsi b/arch/powerpc/dts/t104x.dtsi index ff0da9397e..59989677a2 100644 --- a/arch/powerpc/dts/t104x.dtsi +++ b/arch/powerpc/dts/t104x.dtsi @@ -59,4 +59,52 @@ clock-frequency = <0x0>; }; }; + + pcie@ffe240000 { + compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe240000 0x0 0x1000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe250000 { + compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe250000 0x0 0x1000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x10000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe260000 { + compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe260000 0x0 0x1000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; + + pcie@ffe270000 { + compatible = "fsl,pcie-t104x", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe270000 0x0 0x1000>; /* registers */ + law_trgt_if = <3>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x30000000 0x0 0x10000000>; /* non-prefetchable memory */ + }; };
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
include/configs/T104xRDB.h | 38 ++++++++++++++++++++------------------ 1 file changed, 20 insertions(+), 18 deletions(-)
diff --git a/include/configs/T104xRDB.h b/include/configs/T104xRDB.h index 56ddef07f5..53ee1484d0 100644 --- a/include/configs/T104xRDB.h +++ b/include/configs/T104xRDB.h @@ -145,13 +145,11 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg
#define CONFIG_SYS_FSL_CPC /* Corenet Platform Cache */ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS -#define CONFIG_PCI_INDIRECT_BRIDGE #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ #define CONFIG_PCIE4 /* PCIE controller 4 */
-#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE @@ -524,51 +522,55 @@ $(SRCTREE)/board/freescale/t104xrdb/t1042d4_sd_rcw.cfg /* controller 1, direct to uli, tgtid 3, Base address 20000 */ #ifdef CONFIG_PCIE1 #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ #endif
/* controller 2, Slot 2, tgtid 2, Base address 201000 */ #ifdef CONFIG_PCIE2 #define CONFIG_SYS_PCIE2_MEM_VIRT 0x90000000 -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc10000000ull -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ #endif
/* controller 3, Slot 1, tgtid 1, Base address 202000 */ #ifdef CONFIG_PCIE3 #define CONFIG_SYS_PCIE3_MEM_VIRT 0xa0000000 -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc20000000ull -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ #endif
/* controller 4, Base address 203000 */ #ifdef CONFIG_PCIE4 #define CONFIG_SYS_PCIE4_MEM_VIRT 0xb0000000 -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc30000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ #define CONFIG_SYS_PCIE4_IO_VIRT 0xf8030000 -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ #endif
+#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x10000000 /* 256M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#endif #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Enable the DM PCIe driver in T1042D4RDB defconfig.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
configs/T1042D4RDB_NAND_defconfig | 4 ++++ configs/T1042D4RDB_SDCARD_defconfig | 4 ++++ configs/T1042D4RDB_SPIFLASH_defconfig | 4 ++++ configs/T1042D4RDB_defconfig | 4 ++++ 4 files changed, 16 insertions(+)
diff --git a/configs/T1042D4RDB_NAND_defconfig b/configs/T1042D4RDB_NAND_defconfig index 2864ccc492..d3b3614a91 100644 --- a/configs/T1042D4RDB_NAND_defconfig +++ b/configs/T1042D4RDB_NAND_defconfig @@ -62,6 +62,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y diff --git a/configs/T1042D4RDB_SDCARD_defconfig b/configs/T1042D4RDB_SDCARD_defconfig index a8036e3079..d2139b6e20 100644 --- a/configs/T1042D4RDB_SDCARD_defconfig +++ b/configs/T1042D4RDB_SDCARD_defconfig @@ -59,6 +59,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y diff --git a/configs/T1042D4RDB_SPIFLASH_defconfig b/configs/T1042D4RDB_SPIFLASH_defconfig index 8c77ea6cef..95ef9fd694 100644 --- a/configs/T1042D4RDB_SPIFLASH_defconfig +++ b/configs/T1042D4RDB_SPIFLASH_defconfig @@ -60,6 +60,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y diff --git a/configs/T1042D4RDB_defconfig b/configs/T1042D4RDB_defconfig index b9b363afed..970450747c 100644 --- a/configs/T1042D4RDB_defconfig +++ b/configs/T1042D4RDB_defconfig @@ -46,6 +46,10 @@ CONFIG_SPI_FLASH_STMICRO=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Compile the legacy PCIe initialization reoutines for P1020, P1021, P1024, P1025 and P2020 RDB boards only when DM_PCI is not enabled.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c index a04a73528f..3649f16598 100644 --- a/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c +++ b/board/freescale/p1_p2_rdb_pc/p1_p2_rdb_pc.c @@ -278,7 +278,7 @@ int checkboard(void) return 0; }
-#ifdef CONFIG_PCI +#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -444,7 +444,9 @@ int ft_board_setup(void *blob, bd_t *bd)
fdt_fixup_memory(blob, (u64)base, (u64)size);
+#if !defined(CONFIG_DM_PCI) FT_FSL_PCI_SETUP; +#endif
#ifdef CONFIG_QE do_fixup_by_compat(blob, "fsl,qe", "status", "okay",
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Add compatible string for PCIe of P1020, P1021, P1024, P1025 and P2020 SoCs.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
drivers/pci/pcie_fsl.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index a085c0cab9..31cb5d25ad 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -610,6 +610,12 @@ static const struct dm_pci_ops fsl_pcie_ops = { .write_config = fsl_pcie_write_config, };
+static struct fsl_pcie_data p1_p2_data = { + .block_offset = 0xa000, + .block_offset_mask = 0xffff, + .stride = 0x1000, +}; + static struct fsl_pcie_data t2080_data = { .block_offset = 0x240000, .block_offset_mask = 0x3fffff, @@ -617,6 +623,7 @@ static struct fsl_pcie_data t2080_data = { };
static const struct udevice_id fsl_pcie_ids[] = { + { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data }, { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
P1020 integrated 2 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 1.0a, and this patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
arch/powerpc/dts/p1020-post.dtsi | 20 ++++++++++++++++++++ arch/powerpc/dts/p1020rdb-pc.dts | 12 ++++++++++++ arch/powerpc/dts/p1020rdb-pc_36b.dts | 12 ++++++++++++ arch/powerpc/dts/p1020rdb-pd.dts | 12 ++++++++++++ 4 files changed, 56 insertions(+)
diff --git a/arch/powerpc/dts/p1020-post.dtsi b/arch/powerpc/dts/p1020-post.dtsi index e1a4f500a6..1e5e67804b 100644 --- a/arch/powerpc/dts/p1020-post.dtsi +++ b/arch/powerpc/dts/p1020-post.dtsi @@ -25,3 +25,23 @@ last-interrupt-source = <255>; }; }; + +/* PCIe controller base address 0x9000 */ +&pci1 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; + +/* PCIe controller base address 0xa000 */ +&pci0 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; diff --git a/arch/powerpc/dts/p1020rdb-pc.dts b/arch/powerpc/dts/p1020rdb-pc.dts index fd68b8b440..7ebaa619df 100644 --- a/arch/powerpc/dts/p1020rdb-pc.dts +++ b/arch/powerpc/dts/p1020rdb-pc.dts @@ -18,6 +18,18 @@ soc: soc@ffe00000 { ranges = <0x0 0x0 0xffe00000 0x100000>; }; + + pci1: pcie@ffe09000 { + reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pci0: pcie@ffe0a000 { + reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; };
/include/ "p1020-post.dtsi" diff --git a/arch/powerpc/dts/p1020rdb-pc_36b.dts b/arch/powerpc/dts/p1020rdb-pc_36b.dts index a23d031eee..c0e5ef4cf4 100644 --- a/arch/powerpc/dts/p1020rdb-pc_36b.dts +++ b/arch/powerpc/dts/p1020rdb-pc_36b.dts @@ -18,6 +18,18 @@ soc: soc@fffe00000 { ranges = <0x0 0xf 0xffe00000 0x100000>; }; + + pci1: pcie@fffe09000 { + reg = <0xf 0xffe09000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pci0: pcie@fffe0a000 { + reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; };
/include/ "p1020-post.dtsi" diff --git a/arch/powerpc/dts/p1020rdb-pd.dts b/arch/powerpc/dts/p1020rdb-pd.dts index 81f25a3866..21174a09be 100644 --- a/arch/powerpc/dts/p1020rdb-pd.dts +++ b/arch/powerpc/dts/p1020rdb-pd.dts @@ -18,6 +18,18 @@ soc: soc@ffe00000 { ranges = <0x0 0x0 0xffe00000 0x100000>; }; + + pci1: pcie@ffe09000 { + reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pci0: pcie@ffe0a000 { + reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; };
/include/ "p1020-post.dtsi"
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled for P1020, P1021, P1024, P1025 and P2020 RDB boards.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
include/configs/p1_p2_rdb_pc.h | 36 ++++++++++++++++++++++------------ 1 file changed, 23 insertions(+), 13 deletions(-)
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h index e07d2a178f..1481d683e5 100644 --- a/include/configs/p1_p2_rdb_pc.h +++ b/include/configs/p1_p2_rdb_pc.h @@ -207,8 +207,6 @@
#define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #define CONFIG_PCIE2 /* PCIE controller 2 (slot 2) */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE @@ -572,44 +570,56 @@ */
/* controller 2, direct to uli, tgtid 2, Base address 9000 */ -#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xffc10000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xfffc10000ull #else #define CONFIG_SYS_PCIE2_IO_PHYS 0xffc10000 #endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 1, Slot 2, tgtid 1, Base address a000 */ -#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 #endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xffc00000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xfffc00000ull #else #define CONFIG_SYS_PCIE1_IO_PHYS 0xffc00000 #endif + +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_PCIE2_NAME "PCIe SLOT" +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE2_MEM_BUS 0xc0000000 +#else +#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ + +#define CONFIG_SYS_PCIE1_NAME "mini PCIe SLOT" +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Enable the DM PCIe driver in P1020RDB defconfig.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
configs/P1020RDB-PC_36BIT_NAND_defconfig | 4 ++++ configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 4 ++++ configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 4 ++++ configs/P1020RDB-PC_36BIT_defconfig | 4 ++++ configs/P1020RDB-PC_NAND_defconfig | 4 ++++ configs/P1020RDB-PC_SDCARD_defconfig | 4 ++++ configs/P1020RDB-PC_SPIFLASH_defconfig | 4 ++++ configs/P1020RDB-PC_defconfig | 4 ++++ configs/P1020RDB-PD_NAND_defconfig | 4 ++++ configs/P1020RDB-PD_SDCARD_defconfig | 4 ++++ configs/P1020RDB-PD_SPIFLASH_defconfig | 4 ++++ configs/P1020RDB-PD_defconfig | 4 ++++ 12 files changed, 48 insertions(+)
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig index 18032abe1f..2dfaaa7b20 100644 --- a/configs/P1020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig @@ -58,6 +58,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig index 1af8a52efb..456b7f5d1f 100644 --- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig @@ -53,6 +53,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig index cb65399b2e..5e042b3f53 100644 --- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig @@ -54,6 +54,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig index 7d7c55f28f..fea964dd53 100644 --- a/configs/P1020RDB-PC_36BIT_defconfig +++ b/configs/P1020RDB-PC_36BIT_defconfig @@ -42,6 +42,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig index 521ddaacf1..beeaced122 100644 --- a/configs/P1020RDB-PC_NAND_defconfig +++ b/configs/P1020RDB-PC_NAND_defconfig @@ -57,6 +57,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig index af5a3377a7..4e1e11df15 100644 --- a/configs/P1020RDB-PC_SDCARD_defconfig +++ b/configs/P1020RDB-PC_SDCARD_defconfig @@ -52,6 +52,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig index f7a7ec4c20..6f48aa477d 100644 --- a/configs/P1020RDB-PC_SPIFLASH_defconfig +++ b/configs/P1020RDB-PC_SPIFLASH_defconfig @@ -53,6 +53,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig index 595ff5fa2b..0a6f9742a8 100644 --- a/configs/P1020RDB-PC_defconfig +++ b/configs/P1020RDB-PC_defconfig @@ -41,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig index 5e60d18b36..9f7e1ef3db 100644 --- a/configs/P1020RDB-PD_NAND_defconfig +++ b/configs/P1020RDB-PD_NAND_defconfig @@ -61,6 +61,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig index 77c055b586..e9db62dc9a 100644 --- a/configs/P1020RDB-PD_SDCARD_defconfig +++ b/configs/P1020RDB-PD_SDCARD_defconfig @@ -56,6 +56,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig index 77466acab0..ace3fc0d42 100644 --- a/configs/P1020RDB-PD_SPIFLASH_defconfig +++ b/configs/P1020RDB-PD_SPIFLASH_defconfig @@ -57,6 +57,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig index 096355308c..db78cf4868 100644 --- a/configs/P1020RDB-PD_defconfig +++ b/configs/P1020RDB-PD_defconfig @@ -45,6 +45,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
P2020 integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 1.0a, and this patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
arch/powerpc/dts/p2020-post.dtsi | 30 ++++++++++++++++++++++++++++ arch/powerpc/dts/p2020rdb-pc.dts | 17 ++++++++++++++++ arch/powerpc/dts/p2020rdb-pc_36b.dts | 17 ++++++++++++++++ 3 files changed, 64 insertions(+)
diff --git a/arch/powerpc/dts/p2020-post.dtsi b/arch/powerpc/dts/p2020-post.dtsi index f20d1fa20d..f696f35960 100644 --- a/arch/powerpc/dts/p2020-post.dtsi +++ b/arch/powerpc/dts/p2020-post.dtsi @@ -25,3 +25,33 @@ last-interrupt-source = <255>; }; }; + +/* PCIe controller base address 0x8000 */ +&pci2 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; + +/* PCIe controller base address 0x9000 */ +&pci1 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; + +/* PCIe controller base address 0xa000 */ +&pci0 { + compatible = "fsl,pcie-p1_p2", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; diff --git a/arch/powerpc/dts/p2020rdb-pc.dts b/arch/powerpc/dts/p2020rdb-pc.dts index 4800b76c1c..08befd4c59 100644 --- a/arch/powerpc/dts/p2020rdb-pc.dts +++ b/arch/powerpc/dts/p2020rdb-pc.dts @@ -18,6 +18,23 @@ soc: soc@ffe00000 { ranges = <0x0 0x0 0xffe00000 0x100000>; }; + + pci2: pcie@ffe08000 { + reg = <0x0 0xffe08000 0x0 0x1000>; /* registers */ + status = "disabled"; + }; + + pci1: pcie@ffe09000 { + reg = <0x0 0xffe09000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc10000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pci0: pcie@ffe0a000 { + reg = <0x0 0xffe0a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xffc00000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0x80000000 0x0 0x80000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; };
/include/ "p2020-post.dtsi" diff --git a/arch/powerpc/dts/p2020rdb-pc_36b.dts b/arch/powerpc/dts/p2020rdb-pc_36b.dts index 8323b90e6d..04b2519e1a 100644 --- a/arch/powerpc/dts/p2020rdb-pc_36b.dts +++ b/arch/powerpc/dts/p2020rdb-pc_36b.dts @@ -18,6 +18,23 @@ soc: soc@fffe00000 { ranges = <0x0 0xf 0xffe00000 0x100000>; }; + + pci2: pcie@fffe08000 { + reg = <0xf 0xffe08000 0x0 0x1000>; /* registers */ + status = "disabled"; + }; + + pci1: pcie@fffe09000 { + reg = <0xf 0xffe09000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0xf 0xffc10000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xc0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pci0: pcie@fffe0a000 { + reg = <0xf 0xffe0a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0xf 0xffc00000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0x80000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; };
/include/ "p2020-post.dtsi"
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Enable the DM PCIe driver in P2020RDB defconfig.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
configs/P2020RDB-PC_36BIT_NAND_defconfig | 4 ++++ configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 4 ++++ configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 4 ++++ configs/P2020RDB-PC_36BIT_defconfig | 4 ++++ configs/P2020RDB-PC_NAND_defconfig | 4 ++++ configs/P2020RDB-PC_SDCARD_defconfig | 4 ++++ configs/P2020RDB-PC_SPIFLASH_defconfig | 4 ++++ configs/P2020RDB-PC_defconfig | 4 ++++ 8 files changed, 32 insertions(+)
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig index c392298616..6c50b28410 100644 --- a/configs/P2020RDB-PC_36BIT_NAND_defconfig +++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig @@ -63,6 +63,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig index 4977016698..4ecc7a5c00 100644 --- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig +++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig @@ -58,6 +58,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig index d5e176a9af..e35f250aac 100644 --- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig @@ -59,6 +59,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig index 79f4f3c9ac..bb5c6bdb2d 100644 --- a/configs/P2020RDB-PC_36BIT_defconfig +++ b/configs/P2020RDB-PC_36BIT_defconfig @@ -47,6 +47,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig index 5d4e9ea4df..6640e7e593 100644 --- a/configs/P2020RDB-PC_NAND_defconfig +++ b/configs/P2020RDB-PC_NAND_defconfig @@ -62,6 +62,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig index b92ce2fc0a..898fc52330 100644 --- a/configs/P2020RDB-PC_SDCARD_defconfig +++ b/configs/P2020RDB-PC_SDCARD_defconfig @@ -57,6 +57,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig index f80374fbae..ec23385b67 100644 --- a/configs/P2020RDB-PC_SPIFLASH_defconfig +++ b/configs/P2020RDB-PC_SPIFLASH_defconfig @@ -58,6 +58,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig index 40004597d1..b94c67e51f 100644 --- a/configs/P2020RDB-PC_defconfig +++ b/configs/P2020RDB-PC_defconfig @@ -46,6 +46,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_SYS_NS16550=y
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Compile the legacy PCIe initialization reoutines for P2041RDB, P3041, P4080, P5020 and P5040 DS boards only when DM_PCI is not enabled.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
board/freescale/common/p_corenet/pci.c | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/board/freescale/common/p_corenet/pci.c b/board/freescale/common/p_corenet/pci.c index a2df928fc5..a6abe66dc0 100644 --- a/board/freescale/common/p_corenet/pci.c +++ b/board/freescale/common/p_corenet/pci.c @@ -11,6 +11,7 @@ #include <fdt_support.h> #include <asm/fsl_serdes.h>
+#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { fsl_pcie_init_board(0); @@ -20,3 +21,4 @@ void pci_of_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP; } +#endif
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Add compatible string for P2041 PCIe.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
drivers/pci/pcie_fsl.c | 7 +++++++ 1 file changed, 7 insertions(+)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 31cb5d25ad..687947ed85 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -616,6 +616,12 @@ static struct fsl_pcie_data p1_p2_data = { .stride = 0x1000, };
+static struct fsl_pcie_data p2041_data = { + .block_offset = 0x200000, + .block_offset_mask = 0x3fffff, + .stride = 0x1000, +}; + static struct fsl_pcie_data t2080_data = { .block_offset = 0x240000, .block_offset_mask = 0x3fffff, @@ -624,6 +630,7 @@ static struct fsl_pcie_data t2080_data = {
static const struct udevice_id fsl_pcie_ids[] = { { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data }, + { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
P2041 integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
arch/powerpc/dts/p2041.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)
diff --git a/arch/powerpc/dts/p2041.dtsi b/arch/powerpc/dts/p2041.dtsi index 9aa0422821..55f7adc50e 100644 --- a/arch/powerpc/dts/p2041.dtsi +++ b/arch/powerpc/dts/p2041.dtsi @@ -60,4 +60,40 @@ clock-frequency = <0x0>; }; }; + + pcie@ffe200000 { + compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe201000 { + compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe202000 { + compatible = "fsl,pcie-p2041", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; };
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
include/configs/P2041RDB.h | 55 +++++++++++--------------------------- 1 file changed, 15 insertions(+), 40 deletions(-)
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h index e196f3ce33..f8cfef7b2d 100644 --- a/include/configs/P2041RDB.h +++ b/include/configs/P2041RDB.h @@ -37,7 +37,6 @@ #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ #define CONFIG_PCIE3 /* PCIE controller 3 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_SYS_SRIO @@ -354,60 +353,21 @@ unsigned long get_board_sys_clk(unsigned long dummy);
/* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
/* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 -#endif -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* Qman/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 @@ -483,7 +443,22 @@ unsigned long get_board_sys_clk(unsigned long dummy); #endif
#ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Enable the DM PCIe driver in P2041RDB defconfig.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
configs/P2041RDB_NAND_defconfig | 4 ++++ configs/P2041RDB_SDCARD_defconfig | 4 ++++ configs/P2041RDB_SPIFLASH_defconfig | 4 ++++ configs/P2041RDB_defconfig | 4 ++++ 4 files changed, 16 insertions(+)
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig index c173334869..b43f94e67e 100644 --- a/configs/P2041RDB_NAND_defconfig +++ b/configs/P2041RDB_NAND_defconfig @@ -41,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig index a6d6cd231f..33ca880849 100644 --- a/configs/P2041RDB_SDCARD_defconfig +++ b/configs/P2041RDB_SDCARD_defconfig @@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig index a7576f4674..bf551c8971 100644 --- a/configs/P2041RDB_SPIFLASH_defconfig +++ b/configs/P2041RDB_SPIFLASH_defconfig @@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig index 73ca6dc2b8..8168900a21 100644 --- a/configs/P2041RDB_defconfig +++ b/configs/P2041RDB_defconfig @@ -39,6 +39,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Add compatible string for P3041 PCIe.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
drivers/pci/pcie_fsl.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 687947ed85..9b60492fc5 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -631,6 +631,7 @@ static struct fsl_pcie_data t2080_data = { static const struct udevice_id fsl_pcie_ids[] = { { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data }, { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data }, + { .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
P3041 integrated 4 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
arch/powerpc/dts/p3041.dtsi | 48 +++++++++++++++++++++++++++++++++++++ 1 file changed, 48 insertions(+)
diff --git a/arch/powerpc/dts/p3041.dtsi b/arch/powerpc/dts/p3041.dtsi index 7d5c7134aa..197896d35a 100644 --- a/arch/powerpc/dts/p3041.dtsi +++ b/arch/powerpc/dts/p3041.dtsi @@ -60,4 +60,52 @@ clock-frequency = <0x0>; }; }; + + pcie@ffe200000 { + compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe201000 { + compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe202000 { + compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe203000 { + compatible = "fsl,pcie-p3041", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe203000 0x0 0x1000>; /* registers */ + law_trgt_if = <3>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8030000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x60000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; };
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
include/configs/corenet_ds.h | 63 +++++++++++------------------------- 1 file changed, 19 insertions(+), 44 deletions(-)
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h index e5c3a0c3f2..60e09c1939 100644 --- a/include/configs/corenet_ds.h +++ b/include/configs/corenet_ds.h @@ -54,7 +54,6 @@ #define CONFIG_SYS_NUM_CPC CONFIG_SYS_NUM_DDR_CTLRS #define CONFIG_PCIE1 /* PCIE controller 1 */ #define CONFIG_PCIE2 /* PCIE controller 2 */ -#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_SYS_PCI_64BIT /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE @@ -362,68 +361,25 @@
/* controller 1, direct to uli, tgtid 3, Base address 20000 */ #define CONFIG_SYS_PCIE1_MEM_VIRT 0x80000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc00000000ull -#else -#define CONFIG_SYS_PCIE1_MEM_BUS 0x80000000 -#define CONFIG_SYS_PCIE1_MEM_PHYS 0x80000000 -#endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xf8000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xff8000000ull -#else -#define CONFIG_SYS_PCIE1_IO_PHYS 0xf8000000 -#endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */
/* controller 2, Slot 2, tgtid 2, Base address 201000 */ #define CONFIG_SYS_PCIE2_MEM_VIRT 0xa0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE2_MEM_PHYS 0xc20000000ull -#else -#define CONFIG_SYS_PCIE2_MEM_BUS 0xa0000000 -#define CONFIG_SYS_PCIE2_MEM_PHYS 0xa0000000 -#endif -#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE2_IO_VIRT 0xf8010000 -#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE2_IO_PHYS 0xff8010000ull -#else -#define CONFIG_SYS_PCIE2_IO_PHYS 0xf8010000 -#endif -#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */
/* controller 3, Slot 1, tgtid 1, Base address 202000 */ #define CONFIG_SYS_PCIE3_MEM_VIRT 0xc0000000 -#ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE3_MEM_PHYS 0xc40000000ull -#else -#define CONFIG_SYS_PCIE3_MEM_BUS 0xc0000000 -#define CONFIG_SYS_PCIE3_MEM_PHYS 0xc0000000 -#endif -#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE3_IO_VIRT 0xf8020000 -#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 -#ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE3_IO_PHYS 0xff8020000ull -#else -#define CONFIG_SYS_PCIE3_IO_PHYS 0xf8020000 -#endif -#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */
/* controller 4, Base address 203000 */ -#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE4_MEM_PHYS 0xc60000000ull -#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ -#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 #define CONFIG_SYS_PCIE4_IO_PHYS 0xff8030000ull -#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */
/* Qman/Bman */ #define CONFIG_SYS_BMAN_NUM_PORTALS 10 @@ -499,7 +455,26 @@ #endif
#ifdef CONFIG_PCI +#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT /* Use common FSL init code */ #define CONFIG_PCI_INDIRECT_BRIDGE +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE2_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE2_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE2_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE2_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE3_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE3_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE3_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE3_IO_SIZE 0x00010000 /* 64k */ +#define CONFIG_SYS_PCIE4_MEM_BUS 0xe0000000 +#define CONFIG_SYS_PCIE4_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE4_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE4_IO_SIZE 0x00010000 /* 64k */ +#endif
#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ #endif /* CONFIG_PCI */
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Enable the DM PCIe driver in P3041DS defconfig.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
configs/P3041DS_NAND_defconfig | 4 ++++ configs/P3041DS_SDCARD_defconfig | 4 ++++ configs/P3041DS_SPIFLASH_defconfig | 4 ++++ configs/P3041DS_defconfig | 4 ++++ 4 files changed, 16 insertions(+)
diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig index d98feba522..2d50daad5f 100644 --- a/configs/P3041DS_NAND_defconfig +++ b/configs/P3041DS_NAND_defconfig @@ -41,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig index 7be9d882cd..b2dde80714 100644 --- a/configs/P3041DS_SDCARD_defconfig +++ b/configs/P3041DS_SDCARD_defconfig @@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig index 8d3eb0e449..602112c6ee 100644 --- a/configs/P3041DS_SPIFLASH_defconfig +++ b/configs/P3041DS_SPIFLASH_defconfig @@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig index 863a587d72..790807272d 100644 --- a/configs/P3041DS_defconfig +++ b/configs/P3041DS_defconfig @@ -39,6 +39,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Add compatible string for P4080 PCIe.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
drivers/pci/pcie_fsl.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 9b60492fc5..30fff1ede7 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -632,6 +632,7 @@ static const struct udevice_id fsl_pcie_ids[] = { { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data }, { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data }, + { .compatible = "fsl,pcie-p4080", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
P4080 integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
arch/powerpc/dts/p4080.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)
diff --git a/arch/powerpc/dts/p4080.dtsi b/arch/powerpc/dts/p4080.dtsi index 7c8dbae442..ab766803a3 100644 --- a/arch/powerpc/dts/p4080.dtsi +++ b/arch/powerpc/dts/p4080.dtsi @@ -80,4 +80,40 @@ clock-frequency = <0x0>; }; }; + + pcie@ffe200000 { + compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe201000 { + compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe202000 { + compatible = "fsl,pcie-p4080", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; };
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Enable the DM PCIe driver in P4080DS defconfig.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
configs/P4080DS_SDCARD_defconfig | 4 ++++ configs/P4080DS_SPIFLASH_defconfig | 4 ++++ configs/P4080DS_defconfig | 4 ++++ 3 files changed, 12 insertions(+)
diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig index 2aa6fc301a..0a2ebc99fe 100644 --- a/configs/P4080DS_SDCARD_defconfig +++ b/configs/P4080DS_SDCARD_defconfig @@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig index 5c8ca24d1d..10f29ef374 100644 --- a/configs/P4080DS_SPIFLASH_defconfig +++ b/configs/P4080DS_SPIFLASH_defconfig @@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig index d04820f9cf..182d9a7319 100644 --- a/configs/P4080DS_defconfig +++ b/configs/P4080DS_defconfig @@ -39,6 +39,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Add compatible string for P5040 PCIe.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
drivers/pci/pcie_fsl.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 30fff1ede7..199cec3e9b 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -633,6 +633,7 @@ static const struct udevice_id fsl_pcie_ids[] = { { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-p4080", .data = (ulong)&p2041_data }, + { .compatible = "fsl,pcie-p5040", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-t102x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t104x", .data = (ulong)&t2080_data }, { .compatible = "fsl,pcie-t2080", .data = (ulong)&t2080_data },
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
P5040 integrated 3 PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 2.0, and this patch is to add DT node for each PCIe controller.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
arch/powerpc/dts/p5040.dtsi | 36 ++++++++++++++++++++++++++++++++++++ 1 file changed, 36 insertions(+)
diff --git a/arch/powerpc/dts/p5040.dtsi b/arch/powerpc/dts/p5040.dtsi index b6f6c5dd58..8ab123dca4 100644 --- a/arch/powerpc/dts/p5040.dtsi +++ b/arch/powerpc/dts/p5040.dtsi @@ -59,4 +59,40 @@ clock-frequency = <0x0>; }; }; + + pcie@ffe200000 { + compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe200000 0x0 0x1000>; /* registers */ + law_trgt_if = <0>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8000000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x00000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe201000 { + compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe201000 0x0 0x1000>; /* registers */ + law_trgt_if = <1>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8010000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; + + pcie@ffe202000 { + compatible = "fsl,pcie-p5040", "fsl,pcie-fsl-qoriq"; + reg = <0xf 0xfe202000 0x0 0x1000>; /* registers */ + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; + ranges = <0x01000000 0x0 0x00000000 0xf 0xf8020000 0x0 0x00010000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x40000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; };
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Enable the DM PCIe driver in P5040DS defconfig.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
configs/P5040DS_NAND_defconfig | 4 ++++ configs/P5040DS_SDCARD_defconfig | 4 ++++ configs/P5040DS_SPIFLASH_defconfig | 4 ++++ configs/P5040DS_defconfig | 4 ++++ 4 files changed, 16 insertions(+)
diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig index b6e92036bd..64652900ed 100644 --- a/configs/P5040DS_NAND_defconfig +++ b/configs/P5040DS_NAND_defconfig @@ -42,6 +42,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NAND=y diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig index a81cea4817..e31d3e48f7 100644 --- a/configs/P5040DS_SDCARD_defconfig +++ b/configs/P5040DS_SDCARD_defconfig @@ -41,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_MMC=y diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig index 068a6f45d8..37d7b00bc4 100644 --- a/configs/P5040DS_SPIFLASH_defconfig +++ b/configs/P5040DS_SPIFLASH_defconfig @@ -41,6 +41,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_SPIFLASH=y diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig index 6f9588fffd..111b4d1b83 100644 --- a/configs/P5040DS_defconfig +++ b/configs/P5040DS_defconfig @@ -40,6 +40,10 @@ CONFIG_SPI_FLASH_SPANSION=y CONFIG_PHYLIB=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_FMAN_ENET=y CONFIG_MII=y CONFIG_SYS_QE_FMAN_FW_IN_NOR=y
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Compile the legacy PCIe initialization reoutines only when DM_PCI is not enabled.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
board/freescale/mpc8548cds/mpc8548cds.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 7d819d8df5..2799b5b5a4 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -164,7 +164,7 @@ void lbc_sdram_init(void) #endif /* enable SDRAM init */ }
-#if defined(CONFIG_PCI) || defined(CONFIG_PCI1) +#if (defined(CONFIG_PCI) || defined(CONFIG_PCI1)) && !defined(CONFIG_DM_PCI) /* For some reason the Tundra PCI bridge shows up on itself as a * different device. Work around that by refusing to configure it. */ @@ -189,6 +189,7 @@ static struct pci_config_table pci_mpc85xxcds_config_table[] = { static struct pci_controller pci1_hose; #endif /* CONFIG_PCI */
+#if !defined(CONFIG_DM_PCI) void pci_init_board(void) { volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); @@ -268,6 +269,7 @@ void pci_init_board(void)
fsl_pcie_init_board(first_free_busno); } +#endif
void configure_rgmii(void) { @@ -349,7 +351,7 @@ int board_eth_init(bd_t *bis) return pci_eth_init(bis); }
-#if defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_OF_BOARD_SETUP) && !defined(CONFIG_DM_PCI) void ft_pci_setup(void *blob, bd_t *bd) { FT_FSL_PCI_SETUP;
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Disable legacy PCI and PCIe fixup when CONFIG_DM_PCI is selected.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
board/freescale/common/cds_pci_ft.c | 4 +++- 1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/board/freescale/common/cds_pci_ft.c b/board/freescale/common/cds_pci_ft.c index 3ff2fa416b..fb2e5c7bf3 100644 --- a/board/freescale/common/cds_pci_ft.c +++ b/board/freescale/common/cds_pci_ft.c @@ -9,6 +9,7 @@ #include "cadmus.h"
#if defined(CONFIG_OF_BOARD_SETUP) +#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) static void cds_pci_fixup(void *blob) { int node; @@ -61,11 +62,12 @@ static void cds_pci_fixup(void *blob) } } } +#endif
int ft_board_setup(void *blob, bd_t *bd) { ft_cpu_setup(blob, bd); -#ifdef CONFIG_PCI +#if defined(CONFIG_PCI) && !defined(CONFIG_DM_PCI) ft_pci_setup(blob, bd); cds_pci_fixup(blob); #endif
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Add compatible string for MPC8548 PCIe.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
drivers/pci/pcie_fsl.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/drivers/pci/pcie_fsl.c b/drivers/pci/pcie_fsl.c index 199cec3e9b..ab25aeee73 100644 --- a/drivers/pci/pcie_fsl.c +++ b/drivers/pci/pcie_fsl.c @@ -629,6 +629,7 @@ static struct fsl_pcie_data t2080_data = { };
static const struct udevice_id fsl_pcie_ids[] = { + { .compatible = "fsl,pcie-mpc8548", .data = (ulong)&p1_p2_data }, { .compatible = "fsl,pcie-p1_p2", .data = (ulong)&p1_p2_data }, { .compatible = "fsl,pcie-p2041", .data = (ulong)&p2041_data }, { .compatible = "fsl,pcie-p3041", .data = (ulong)&p2041_data },
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
MPC8548 integrated a PCIe controllers, which is compatible with the PCI Express™ Base Specification, Revision 1.0a, and this patch is to add DT node for the PCIe controller.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
arch/powerpc/dts/mpc8548-post.dtsi | 9 +++++++++ arch/powerpc/dts/mpc8548cds.dts | 6 ++++++ arch/powerpc/dts/mpc8548cds_36b.dts | 6 ++++++ 3 files changed, 21 insertions(+)
diff --git a/arch/powerpc/dts/mpc8548-post.dtsi b/arch/powerpc/dts/mpc8548-post.dtsi index 5533a4b598..2206f2da9f 100644 --- a/arch/powerpc/dts/mpc8548-post.dtsi +++ b/arch/powerpc/dts/mpc8548-post.dtsi @@ -25,3 +25,12 @@ last-interrupt-source = <255>; }; }; + +&pcie { + compatible = "fsl,pcie-mpc8548", "fsl,pcie-fsl-qoriq"; + law_trgt_if = <2>; + #address-cells = <3>; + #size-cells = <2>; + device_type = "pci"; + bus-range = <0x0 0xff>; +}; diff --git a/arch/powerpc/dts/mpc8548cds.dts b/arch/powerpc/dts/mpc8548cds.dts index cceea345c8..3b927bd265 100644 --- a/arch/powerpc/dts/mpc8548cds.dts +++ b/arch/powerpc/dts/mpc8548cds.dts @@ -18,6 +18,12 @@ soc: soc8548@e0000000 { ranges = <0x0 0x0 0xe0000000 0x100000>; }; + + pcie: pcie@e000a000 { + reg = <0x0 0xe000a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0x0 0xe3000000 0x0 0x00100000 /* downstream I/O */ + 0x02000000 0x0 0xa0000000 0x0 0xa0000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; };
/include/ "mpc8548-post.dtsi" diff --git a/arch/powerpc/dts/mpc8548cds_36b.dts b/arch/powerpc/dts/mpc8548cds_36b.dts index faff35cc36..98d7c2410b 100644 --- a/arch/powerpc/dts/mpc8548cds_36b.dts +++ b/arch/powerpc/dts/mpc8548cds_36b.dts @@ -18,6 +18,12 @@ soc: soc8548@fe0000000 { ranges = <0x0 0xf 0xe0000000 0x100000>; }; + + pcie: pcie@fe000a000 { + reg = <0xf 0xe000a000 0x0 0x1000>; /* registers */ + ranges = <0x01000000 0x0 0x00000000 0xf 0xe3000000 0x0 0x00100000 /* downstream I/O */ + 0x02000000 0x0 0xe0000000 0xc 0x20000000 0x0 0x20000000>; /* non-prefetchable memory */ + }; };
/include/ "mpc8548-post.dtsi"
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Disable legacy PCIe driver and unused PCIe macros when DM_PCI enabled.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
include/configs/MPC8548CDS.h | 22 ++++++++++++++-------- 1 file changed, 14 insertions(+), 8 deletions(-)
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 4252fbeef9..4809bbdfa3 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -18,8 +18,6 @@ #define CONFIG_PCI1 /* PCI controller 1 */ #define CONFIG_PCIE1 /* PCIE controller 1 (slot 1) */ #undef CONFIG_PCI2 -#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ -#define CONFIG_PCI_INDIRECT_BRIDGE 1 /* indirect PCI bridge support */ #define CONFIG_SYS_PCI_64BIT 1 /* enable 64-bit PCI resources */
#define CONFIG_ENV_OVERWRITE @@ -343,24 +341,18 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_PCI1_IO_SIZE 0x00100000 /* 1M */
#ifdef CONFIG_PCIE1 -#define CONFIG_SYS_PCIE1_NAME "Slot" #define CONFIG_SYS_PCIE1_MEM_VIRT 0xa0000000 #ifdef CONFIG_PHYS_64BIT -#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xc20000000ull #else -#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 #define CONFIG_SYS_PCIE1_MEM_PHYS 0xa0000000 #endif -#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ #define CONFIG_SYS_PCIE1_IO_VIRT 0xe3000000 -#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 #ifdef CONFIG_PHYS_64BIT #define CONFIG_SYS_PCIE1_IO_PHYS 0xfe3000000ull #else #define CONFIG_SYS_PCIE1_IO_PHYS 0xe3000000 #endif -#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ #endif
/* @@ -386,6 +378,20 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_EEPRO100 #undef CONFIG_TULIP
+#if !defined(CONFIG_DM_PCI) +#define CONFIG_FSL_PCI_INIT 1 /* Use common FSL init code */ +#define CONFIG_PCI_INDIRECT_BRIDGE 1 +#define CONFIG_SYS_PCIE1_NAME "Slot" +#ifdef CONFIG_PHYS_64BIT +#define CONFIG_SYS_PCIE1_MEM_BUS 0xe0000000 +#else +#define CONFIG_SYS_PCIE1_MEM_BUS 0xa0000000 +#endif +#define CONFIG_SYS_PCIE1_MEM_SIZE 0x20000000 /* 512M */ +#define CONFIG_SYS_PCIE1_IO_BUS 0x00000000 +#define CONFIG_SYS_PCIE1_IO_SIZE 0x00100000 /* 1M */ +#endif + #define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
#endif /* CONFIG_PCI */
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Enable the DM PCIe driver in MPC8548CDS defconfig.
Signed-off-by: Hou Zhiqiang Zhiqiang.Hou@nxp.com Reviewed-by: Bin Meng bmeng.cn@gmail.com --- V2: - Rebased the patch.
configs/MPC8548CDS_36BIT_defconfig | 4 ++++ configs/MPC8548CDS_defconfig | 4 ++++ configs/MPC8548CDS_legacy_defconfig | 4 ++++ 3 files changed, 12 insertions(+)
diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig index f259f1992c..102716bc07 100644 --- a/configs/MPC8548CDS_36BIT_defconfig +++ b/configs/MPC8548CDS_36BIT_defconfig @@ -26,6 +26,10 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig index 72239da0c3..9cccb609e5 100644 --- a/configs/MPC8548CDS_defconfig +++ b/configs/MPC8548CDS_defconfig @@ -25,6 +25,10 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2 diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig index f2420c3ad2..782f8270c8 100644 --- a/configs/MPC8548CDS_legacy_defconfig +++ b/configs/MPC8548CDS_legacy_defconfig @@ -25,6 +25,10 @@ CONFIG_SYS_FLASH_CFI=y CONFIG_PHY_MARVELL=y CONFIG_PHY_GIGE=y CONFIG_E1000=y +CONFIG_DM=y +CONFIG_DM_PCI=y +CONFIG_DM_PCI_COMPAT=y +CONFIG_PCIE_FSL=y CONFIG_MII=y CONFIG_TSEC_ENET=y CONFIG_CONS_INDEX=2
-----Original Message----- From: Z.q. Hou Sent: Tuesday, August 27, 2019 4:33 PM To: u-boot@lists.denx.de; Prabhakar Kushwaha prabhakar.kushwaha@nxp.com; wd@denx.de; Priyanka Jain priyanka.jain@nxp.com; Shengzhou Liu shengzhou.liu@nxp.com; bmeng.cn@gmail.com Cc: Z.q. Hou zhiqiang.hou@nxp.com Subject: [PATCHv2 00/47] powerpc: Enable PCIe DM drvier for some platforms
From: Hou Zhiqiang Zhiqiang.Hou@nxp.com
Enable PCIe DM driver for some PowerPC platforms which has supported device tree.
Depends on the following 2 series: http://patchwork.ozlabs.org/project/uboot/list/?series=120960 http://patchwork.ozlabs.org/project/uboot/list/?series=115008
Hou Zhiqiang (47): powerpc: T208xRDB: Compile legacy PCIe routines conditionally powerpc: T208xRDB: Disable legacy PCIe driver when DM_PCI is enabled configs: T2080RDB: Enable PCIe driver powerpc: T4RDB: Compile legacy PCIe routines conditionally dm: pcie_fsl: Add T4240 PCIe support t4240: dts: Added PCIe DT nodes powerpc: T4240RDB: Disable legacy PCIe driver when DM_PCI is enabled configs: T4240RDB: Enable PCIe driver powerpc: T102xRDB: Compile legacy PCIe routines conditionally dm: pcie_fsl: Add T102x PCIe support t102x: dts: Added PCIe DT nodes powerpc: T102xRDB: Remove the useless macro CONFIG_ARCH_T1040 powerpc: T102xRDB: Disable legacy PCIe driver when DM_PCI is enabled configs: T1024RDB: Enable PCIe driver powerpc: T104xRDB: Compile legacy PCIe routines conditionally dm: pcie_fsl: Add T104x PCIe support t104x: dts: Added PCIe DT nodes powerpc: T104xRDB: Disable legacy PCIe driver when DM_PCI is enabled configs: T1042D4RDB: Enable PCIe driver powerpc: p1_p2_rdb: Compile legacy PCIe routines conditionally dm: pcie_fsl: Add PCIe support for P1 and P2 series SoCs P1020: dts: Added PCIe DT nodes powerpc: p1_p2_rdb: Disable legacy PCIe driver when DM_PCI is enabled configs: P1020RDB: Enable PCIe driver P2020: dts: Added PCIe DT nodes configs: P2020RDB: Enable PCIe driver powerpc: p_corenet: Compile legacy PCIe routines conditionally dm: pcie_fsl: Add P2041 PCIe support P2041: dts: Added PCIe DT nodes powerpc: P2041RDB: Disable legacy PCIe driver when DM_PCI is enabled configs: P2041RDB: Enable PCIe driver dm: pcie_fsl: Add P3041 PCIe support P3041: dts: Added PCIe DT nodes powerpc: corenet_ds: Disable legacy PCIe driver when DM_PCI is enabled configs: P3041DS: Enable PCIe driver dm: pcie_fsl: Add P4080 PCIe support P4080: dts: Added PCIe DT nodes configs: P4080DS: Enable PCIe driver dm: pcie_fsl: Add P5040 PCIe support P5040: dts: Added PCIe DT nodes configs: P5040DS: Enable PCIe driver powerpc: MPC8548CDS: Compile legacy PCIe routines conditionally powerpc: MPC85xxCDS: Disable legacy PCI fixup when DM_PCI is selected dm: pcie_fsl: Add MPC8548 PCIe support MPC8548: dts: Added PCIe DT node powerpc: MPC8548CDS: Disable legacy PCIe driver when DM_PCI is enabled configs: MPC8548CDS: Enable PCIe driver
This patch series has been applied to u-boot-mpc85xx, awaiting upstream.
--pk
participants (2)
-
Prabhakar Kushwaha -
Z.q. Hou