[U-Boot] [PATCH v1 00/29] convert aristainetos board to DM
This series converts the aristainetos to DM / DTS support and get rid of the compile warnings: ===================== WARNING ====================== This board does not use CONFIG_DM. CONFIG_DM will be compulsory starting with the v2020.01 release. Failure to update may result in board removal. See doc/driver-model/migration.rst for more info. ==================================================== ===================== WARNING ====================== This board does not use CONFIG_DM_MMC. Please update the board to use CONFIG_DM_MMC before the v2019.04 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. ==================================================== ===================== WARNING ====================== This board does not use CONFIG_DM_USB. Please update the board to use CONFIG_DM_USB before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. ==================================================== ===================== WARNING ====================== This board does not use CONFIG_DM_VIDEO Please update the board to use CONFIG_DM_VIDEO before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. ==================================================== ===================== WARNING ====================== This board does not use CONFIG_DM_SPI_FLASH. Please update the board to use CONFIG_SPI_FLASH before the v2019.07 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. ==================================================== ===================== WARNING ====================== This board does not use CONFIG_WDT (DM watchdog support). Please update the board to use CONFIG_WDT before the v2019.10 release. Failure to update by the deadline may result in board removal. See doc/driver-model/MIGRATION.txt for more info. ====================================================
The not used aristainetos board is removed. The aristianetos board versions 2b is removed, for easier DM convertion, and at the end of this series again added.
Also we add the board versions 2b_csl and 2c in this series.
The series is based on mainline commit 4b19b89ca4: ("Merge tag 'rpi-next-2020.01' of https://github.com/mbgg/u-boot")
the following patches are needed for working correct on board, but without them build is also clean.
(gpio seach for gpio label) http://patchwork.ozlabs.org/patch/1186638/ bdinfo: http://patchwork.ozlabs.org/patch/1192363/ support Env in SPI NOR before relocation. http://patchwork.ozlabs.org/patch/1195435/ http://patchwork.ozlabs.org/patch/1195436/
travis and azure uild: https://travis-ci.org/hsdenx/u-boot-test/builds/619145300 https://dev.azure.com/hs0298/hs/_build/results?buildId=7
Heiko Schocher (29): imx6: remove aristainetos board video: lg4573: convert to DM imx6: aristainetos: move defines to Kconfig imx6: aristainetos: remove 2b version imx6: aristainetos: disable gigabit support imx6: aristainetos: add device tree from linux imx6: aristainetos: add thumb build imx6: aristainetos: remove aristainetos-v2.c imx6: aristainetos: prepare dts for other board versions imx6: aristainetos: add DM_SERIAL support imx6: aristainetos: convert to DM_MMC imx6: aristainetos: convert gpio pins to DM and DTS imx6: aristainetos: convert to DM_USB imx6: aristainetos: convert CONFIG_DM_SPI imx6: aristainetos: enable DM_ETH imx6: aristainetos: add DM_VIDEO support imx6: aristainetos: add DM_I2C support imx6: aristainetos: convert to DM_PWM/DM_BACKLIGHT imx6: aristainetos: get rid of CONFIG_BOARDNAME imx6: aristainetos: add i2c eeprom support imx6: aristainetos: add AUTOBOOT_KEYED imx6: aristainetos: add version variable imx6: aristainetos: cleanup bootmode settings imx6: aristainetos: WDT DM conversion enable WDT reset imx6: aristainetos: cleanup default Environment imx6: aristainetos: enable HAB boot imx6: aristainetos: readd aristainetos 2b board imx6: aristainetos: add aristainetos 2b csl imx6: aristainetos: add support for rev C board
arch/arm/dts/Makefile | 8 + .../dts/imx6dl-aristainetos2_4-u-boot.dtsi | 13 + arch/arm/dts/imx6dl-aristainetos2_4.dts | 51 ++ arch/arm/dts/imx6dl-aristainetos2_4.dtsi | 84 +++ .../dts/imx6dl-aristainetos2_7-u-boot.dtsi | 19 + arch/arm/dts/imx6dl-aristainetos2_7.dts | 16 + arch/arm/dts/imx6dl-aristainetos2_7.dtsi | 58 ++ .../dts/imx6dl-aristainetos2b_4-u-boot.dtsi | 13 + arch/arm/dts/imx6dl-aristainetos2b_4.dts | 50 ++ .../dts/imx6dl-aristainetos2b_7-u-boot.dtsi | 19 + arch/arm/dts/imx6dl-aristainetos2b_7.dts | 16 + .../imx6dl-aristainetos2b_csl_4-u-boot.dtsi | 13 + arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts | 50 ++ .../imx6dl-aristainetos2b_csl_7-u-boot.dtsi | 19 + arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts | 16 + .../dts/imx6dl-aristainetos2c_4-u-boot.dtsi | 13 + arch/arm/dts/imx6dl-aristainetos2c_4.dts | 50 ++ .../dts/imx6dl-aristainetos2c_7-u-boot.dtsi | 19 + arch/arm/dts/imx6dl-aristainetos2c_7.dts | 16 + .../arm/dts/imx6qdl-aristainetos2-common.dtsi | 492 +++++++++++++ .../arm/dts/imx6qdl-aristainetos2-u-boot.dtsi | 101 +++ arch/arm/dts/imx6qdl-aristainetos2.dtsi | 244 +++++++ .../dts/imx6qdl-aristainetos2b-u-boot.dtsi | 77 ++ arch/arm/dts/imx6qdl-aristainetos2b.dtsi | 266 +++++++ .../imx6qdl-aristainetos2b_csl-u-boot.dtsi | 77 ++ arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi | 248 +++++++ .../dts/imx6qdl-aristainetos2c-u-boot.dtsi | 77 ++ arch/arm/dts/imx6qdl-aristainetos2c.dtsi | 228 ++++++ arch/arm/mach-imx/mx6/Kconfig | 39 +- board/aristainetos/Kconfig | 34 +- board/aristainetos/MAINTAINERS | 31 +- board/aristainetos/aristainetos-v1.c | 278 ------- board/aristainetos/aristainetos-v2.c | 686 ------------------ board/aristainetos/aristainetos.c | 592 +++++++++++---- board/aristainetos/aristainetos.cfg | 32 - board/aristainetos/aristainetos2.cfg | 3 + board/aristainetos/clocks.cfg | 23 - board/aristainetos/common/Kconfig | 35 + board/aristainetos/ddr-setup.cfg | 60 -- board/aristainetos/mt41j128M.cfg | 69 -- configs/aristainetos2_defconfig | 64 +- configs/aristainetos2b_defconfig | 66 +- configs/aristainetos2bcsl_defconfig | 115 +++ configs/aristainetos2c_defconfig | 115 +++ configs/aristainetos_defconfig | 68 -- drivers/video/lg4573.c | 175 ++++- include/configs/aristainetos-common.h | 195 ----- include/configs/aristainetos.h | 43 -- include/configs/aristainetos2.h | 445 +++++++++++- include/configs/aristainetos2b.h | 50 -- scripts/config_whitelist.txt | 3 - 51 files changed, 3840 insertions(+), 1734 deletions(-) create mode 100644 arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2_4.dts create mode 100644 arch/arm/dts/imx6dl-aristainetos2_4.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2_7.dts create mode 100644 arch/arm/dts/imx6dl-aristainetos2_7.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_4.dts create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_7.dts create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts create mode 100644 arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2c_4.dts create mode 100644 arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2c_7.dts create mode 100644 arch/arm/dts/imx6qdl-aristainetos2-common.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2b.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2c.dtsi delete mode 100644 board/aristainetos/aristainetos-v1.c delete mode 100644 board/aristainetos/aristainetos-v2.c delete mode 100644 board/aristainetos/aristainetos.cfg delete mode 100644 board/aristainetos/clocks.cfg create mode 100644 board/aristainetos/common/Kconfig delete mode 100644 board/aristainetos/ddr-setup.cfg delete mode 100644 board/aristainetos/mt41j128M.cfg create mode 100644 configs/aristainetos2bcsl_defconfig create mode 100644 configs/aristainetos2c_defconfig delete mode 100644 configs/aristainetos_defconfig delete mode 100644 include/configs/aristainetos-common.h delete mode 100644 include/configs/aristainetos.h delete mode 100644 include/configs/aristainetos2b.h
remove not anymore used aristainetos board.
Signed-off-by: Heiko Schocher hs@denx.de
---
arch/arm/mach-imx/mx6/Kconfig | 3 - board/aristainetos/Kconfig | 10 - board/aristainetos/MAINTAINERS | 2 - board/aristainetos/aristainetos-v1.c | 278 --------------------------- board/aristainetos/aristainetos.c | 4 +- board/aristainetos/aristainetos.cfg | 32 --- board/aristainetos/clocks.cfg | 23 --- board/aristainetos/ddr-setup.cfg | 60 ------ board/aristainetos/mt41j128M.cfg | 69 ------- configs/aristainetos_defconfig | 68 ------- include/configs/aristainetos.h | 43 ----- 11 files changed, 1 insertion(+), 591 deletions(-) delete mode 100644 board/aristainetos/aristainetos-v1.c delete mode 100644 board/aristainetos/aristainetos.cfg delete mode 100644 board/aristainetos/clocks.cfg delete mode 100644 board/aristainetos/ddr-setup.cfg delete mode 100644 board/aristainetos/mt41j128M.cfg delete mode 100644 configs/aristainetos_defconfig delete mode 100644 include/configs/aristainetos.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 607210520f..6c1a1120d8 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -125,9 +125,6 @@ config TARGET_APALIS_IMX6 imply CMD_DM imply CMD_SATA
-config TARGET_ARISTAINETOS - bool "aristainetos" - config TARGET_ARISTAINETOS2 bool "aristainetos2" select BOARD_LATE_INIT diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig index e416c9ac0d..0341bdfb28 100644 --- a/board/aristainetos/Kconfig +++ b/board/aristainetos/Kconfig @@ -1,13 +1,3 @@ -if TARGET_ARISTAINETOS - -config SYS_BOARD - default "aristainetos" - -config SYS_CONFIG_NAME - default "aristainetos" - -endif - if TARGET_ARISTAINETOS2
config SYS_BOARD diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS index b463f7b176..c9e05285df 100644 --- a/board/aristainetos/MAINTAINERS +++ b/board/aristainetos/MAINTAINERS @@ -2,8 +2,6 @@ ARISTAINETOS BOARD M: Heiko Schocher hs@denx.de S: Maintained F: board/aristainetos/ -F: include/configs/aristainetos.h -F: configs/aristainetos_defconfig F: include/configs/aristainetos2.h F: configs/aristainetos2_defconfig F: configs/aristainetos2b_defconfig diff --git a/board/aristainetos/aristainetos-v1.c b/board/aristainetos/aristainetos-v1.c deleted file mode 100644 index de1a018c1f..0000000000 --- a/board/aristainetos/aristainetos-v1.c +++ /dev/null @@ -1,278 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam fabio.estevam@freescale.com - */ - -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <linux/errno.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/mach-imx/video.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <miiphy.h> -#include <netdev.h> -#include <asm/arch/mxc_hdmi.h> -#include <asm/arch/crm_regs.h> -#include <linux/fb.h> -#include <ipu_pixfmt.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <pwm.h> - -struct i2c_pads_info i2c_pad_info3 = { - .scl = { - .i2c_mode = MX6_PAD_EIM_D17__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_EIM_D17__GPIO3_IO17 | PC, - .gp = IMX_GPIO_NR(3, 17) - }, - .sda = { - .i2c_mode = MX6_PAD_EIM_D18__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_EIM_D18__GPIO3_IO18 | PC, - .gp = IMX_GPIO_NR(3, 18) - } -}; - -iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const uart5_pads[] = { - MX6_PAD_CSI0_DAT14__UART5_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT15__UART5_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const gpio_pads[] = { - /* LED enable */ - MX6_PAD_SD4_DAT5__GPIO2_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* spi flash WP protect */ - MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* backlight enable */ - MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* LED yellow */ - MX6_PAD_GPIO_3__GPIO1_IO03 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* LED red */ - MX6_PAD_GPIO_4__GPIO1_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* LED green */ - MX6_PAD_GPIO_5__GPIO1_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* LED blue */ - MX6_PAD_GPIO_6__GPIO1_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* i2c4 scl */ - MX6_PAD_GPIO_7__GPIO1_IO07 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* i2c4 sda */ - MX6_PAD_GPIO_8__GPIO1_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* spi CS 1 */ - MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const misc_pads[] = { - MX6_PAD_GPIO_1__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), - /* OTG Power enable */ - MX6_PAD_EIM_D31__GPIO3_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_KEY_ROW4__GPIO4_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_GPIO_16__ENET_REF_CLK | MUX_PAD_CTRL(0x4001b0a8), - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_TXD0__ENET_TX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_TXD1__ENET_TX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_TX_EN__ENET_TX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_RX_ER__ENET_RX_ER | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_RXD0__ENET_RX_DATA0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_RXD1__ENET_RX_DATA1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_CRS_DV__ENET_RX_EN | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -static void setup_iomux_enet(void) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); - - /* set GPIO_16 as ENET_REF_CLK_OUT */ - setbits_le32(&iomux->gpr[1], IOMUXC_GPR1_ENET_CLK_SEL_MASK); -} - -static iomux_v3_cfg_t const backlight_pads[] = { - MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_SD4_DAT1__PWM3_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_GPIO_2__GPIO1_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -iomux_v3_cfg_t const ecspi4_pads[] = { - MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_EIM_D20__GPIO3_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const display_pads[] = { - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL), - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, - MX6_PAD_DI0_PIN4__GPIO4_IO20, - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, -}; - -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - return (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS) - ? (IMX_GPIO_NR(3, 20)) : -1; -} - -static void setup_spi(void) -{ - int i; - - imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads)); - for (i = 0; i < 3; i++) - enable_spi_clk(true, i); - - /* set cs1 to high */ - gpio_direction_output(ECSPI4_CS1, 1); -} - -static void setup_iomux_uart(void) -{ - imx_iomux_v3_setup_multiple_pads(uart5_pads, ARRAY_SIZE(uart5_pads)); -} - -int board_eth_init(bd_t *bis) -{ - struct iomuxc *iomuxc_regs = - (struct iomuxc *)IOMUXC_BASE_ADDR; - int ret; - - /* clear gpr1[14], gpr1[18:17] to select anatop clock */ - clrsetbits_le32(&iomuxc_regs->gpr[1], IOMUX_GPR1_FEC_MASK, 0); - - ret = enable_fec_anatop_clock(0, ENET_50MHZ); - if (ret) - return ret; - - setup_iomux_enet(); - return cpu_eth_init(bis); -} - -static void enable_lvds(struct display_info_t const *dev) -{ - imx_iomux_v3_setup_multiple_pads( - display_pads, - ARRAY_SIZE(display_pads)); - imx_iomux_v3_setup_multiple_pads( - backlight_pads, - ARRAY_SIZE(backlight_pads)); - - /* enable backlight PWM 3 */ - if (pwm_init(2, 0, 0)) - goto error; - /* duty cycle 500ns, period: 3000ns */ - if (pwm_config(2, 500, 3000)) - goto error; - if (pwm_enable(2)) - goto error; - return; - -error: - puts("error init pwm for backlight\n"); - return; -} - -static void setup_display(void) -{ - struct mxc_ccm_reg *mxc_ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - int reg; - - enable_ipu_clock(); - - reg = readl(&mxc_ccm->cs2cdr); - /* select pll 5 clock */ - reg &= MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK; - reg &= MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK; - writel(reg, &mxc_ccm->cs2cdr); - - imx_iomux_v3_setup_multiple_pads(backlight_pads, - ARRAY_SIZE(backlight_pads)); -} - -static void setup_iomux_gpio(void) -{ - imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - setup_iomux_gpio(); - - setup_display(); - return 0; -} - - -static void setup_i2c4(void) -{ - /* i2c4 not used, set it to gpio input */ - gpio_request(IMX_GPIO_NR(1, 7), "i2c4_scl"); - gpio_direction_input(IMX_GPIO_NR(1, 7)); - gpio_request(IMX_GPIO_NR(1, 8), "i2c4_sda"); - gpio_direction_input(IMX_GPIO_NR(1, 8)); -} - -static void setup_board_gpio(void) -{ - /* enable LED */ - gpio_request(IMX_GPIO_NR(2, 13), "LED ena"); - gpio_direction_output(IMX_GPIO_NR(2, 13), 0); - - gpio_request(IMX_GPIO_NR(1, 3), "LED yellow"); - gpio_direction_output(IMX_GPIO_NR(1, 3), 1); - gpio_request(IMX_GPIO_NR(1, 4), "LED red"); - gpio_direction_output(IMX_GPIO_NR(1, 4), 1); - gpio_request(IMX_GPIO_NR(1, 5), "LED green"); - gpio_direction_output(IMX_GPIO_NR(1, 5), 1); - gpio_request(IMX_GPIO_NR(1, 6), "LED blue"); - gpio_direction_output(IMX_GPIO_NR(1, 6), 1); -} - -static void setup_board_spi(void) -{ -} diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 9f744b30b3..873b354db8 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -58,9 +58,7 @@ DECLARE_GLOBAL_DATA_PTR;
#define ECSPI4_CS1 IMX_GPIO_NR(5, 2)
-#if (CONFIG_SYS_BOARD_VERSION == 1) -#include "./aristainetos-v1.c" -#elif ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3)) +#if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3)) #include "./aristainetos-v2.c" #endif
diff --git a/board/aristainetos/aristainetos.cfg b/board/aristainetos/aristainetos.cfg deleted file mode 100644 index fb746782ac..0000000000 --- a/board/aristainetos/aristainetos.cfg +++ /dev/null @@ -1,32 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2014 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * Copyright (C) 2013 Boundary Devices - * - * Refer doc/README.imximage for more details about how-to configure - * and create imximage boot image - * - * The syntax is taken as close as possible with the kwbimage - */ - -/* image version */ -IMAGE_VERSION 2 - -/* - * Boot Device : one of - * spi, sd - */ -BOOT_FROM spi - -#define __ASSEMBLY__ -#include <config.h> -#include "asm/arch/mx6-ddr.h" -#include "asm/arch/iomux.h" -#include "asm/arch/crm_regs.h" - -#include "ddr-setup.cfg" -#include "mt41j128M.cfg" -#include "clocks.cfg" diff --git a/board/aristainetos/clocks.cfg b/board/aristainetos/clocks.cfg deleted file mode 100644 index 58976e72b0..0000000000 --- a/board/aristainetos/clocks.cfg +++ /dev/null @@ -1,23 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* set the default clock gate to save power */ -DATA 4, CCM_CCGR0, 0x00c03f3f -DATA 4, CCM_CCGR1, 0x0030fcff -DATA 4, CCM_CCGR2, 0x0fffcfc0 -DATA 4, CCM_CCGR3, 0x3ff0300f -DATA 4, CCM_CCGR4, 0xfffff30c /* enable NAND/GPMI/BCH clocks */ -DATA 4, CCM_CCGR5, 0x0f0000c3 -DATA 4, CCM_CCGR6, 0x000003ff diff --git a/board/aristainetos/ddr-setup.cfg b/board/aristainetos/ddr-setup.cfg deleted file mode 100644 index d3ade356e5..0000000000 --- a/board/aristainetos/ddr-setup.cfg +++ /dev/null @@ -1,60 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - * - * Device Configuration Data (DCD) - * - * Each entry must have the format: - * Addr-type Address Value - * - * where: - * Addr-type register length (1,2 or 4 bytes) - * Address absolute address of the register - * value value to be stored in the register - */ - -/* DDR IO TYPE */ -DATA 4, MX6_IOM_GRP_DDR_TYPE, 0x000C0000 -DATA 4, MX6_IOM_GRP_DDRPKE, 0x00000000 -/* Clock */ -DATA 4, MX6_IOM_DRAM_SDCLK_0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDCLK_1, 0x00000030 -/* Address */ -DATA 4, MX6_IOM_DRAM_CAS, 0x00000030 -DATA 4, MX6_IOM_DRAM_RAS, 0x00000030 -DATA 4, MX6_IOM_GRP_ADDDS, 0x00000030 -/* Control */ -DATA 4, MX6_IOM_DRAM_RESET, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDCKE0, 0x00003000 -DATA 4, MX6_IOM_DRAM_SDCKE1, 0x00003000 -DATA 4, MX6_IOM_DRAM_SDBA2, 0x00000000 -DATA 4, MX6_IOM_DRAM_SDODT0, 0x00003030 -DATA 4, MX6_IOM_DRAM_SDODT1, 0x00003030 -DATA 4, MX6_IOM_GRP_CTLDS, 0x00000030 -/* Data Strobe */ -DATA 4, MX6_IOM_DDRMODE_CTL, 0x00020000 -DATA 4, MX6_IOM_DRAM_SDQS0, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS1, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS2, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS3, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS4, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS5, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS6, 0x00000030 -DATA 4, MX6_IOM_DRAM_SDQS7, 0x00000030 -DATA 4, MX6_IOM_GRP_DDRMODE, 0x00020000 -DATA 4, MX6_IOM_GRP_B0DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B1DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B2DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B3DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B4DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B5DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B6DS, 0x00000030 -DATA 4, MX6_IOM_GRP_B7DS, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM0, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM1, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM2, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM3, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM4, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM5, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM6, 0x00000030 -DATA 4, MX6_IOM_DRAM_DQM7, 0x00000030 diff --git a/board/aristainetos/mt41j128M.cfg b/board/aristainetos/mt41j128M.cfg deleted file mode 100644 index bb2684bc37..0000000000 --- a/board/aristainetos/mt41j128M.cfg +++ /dev/null @@ -1,69 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * Copyright (C) 2013 Boundary Devices - */ -/* ZQ Calibration */ -DATA 4, MX6_MMDC_P0_MPZQHWCTRL, 0xa1390003 -DATA 4, MX6_MMDC_P1_MPZQHWCTRL, 0xa1390003 -DATA 4, MX6_MMDC_P0_MPWLDECTRL0, 0x001F001F -DATA 4, MX6_MMDC_P0_MPWLDECTRL1, 0x001F001F -DATA 4, MX6_MMDC_P1_MPWLDECTRL0, 0x001F001F -DATA 4, MX6_MMDC_P1_MPWLDECTRL1, 0x001F001F -/* - * DQS gating, read delay, write delay calibration values - * based on calibration compare of 0x00ffff00 - */ -DATA 4, MX6_MMDC_P0_MPDGCTRL0, 0x420E020E -DATA 4, MX6_MMDC_P0_MPDGCTRL1, 0x02000200 -DATA 4, MX6_MMDC_P1_MPDGCTRL0, 0x42020202 -DATA 4, MX6_MMDC_P1_MPDGCTRL1, 0x01720172 -DATA 4, MX6_MMDC_P0_MPRDDLCTL, 0x494C4F4C -DATA 4, MX6_MMDC_P1_MPRDDLCTL, 0x4A4C4C49 -DATA 4, MX6_MMDC_P0_MPWRDLCTL, 0x3F3F3133 -DATA 4, MX6_MMDC_P1_MPWRDLCTL, 0x39373F2E -/* read data bit delay */ -DATA 4, MX6_MMDC_P0_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P0_MPRDDQBY3DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY0DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY1DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY2DL, 0x33333333 -DATA 4, MX6_MMDC_P1_MPRDDQBY3DL, 0x33333333 -/* Complete calibration by forced measurment */ -DATA 4, MX6_MMDC_P0_MPMUR0, 0x00000800 -DATA 4, MX6_MMDC_P1_MPMUR0, 0x00000800 -/* in DDR3, 64-bit mode, only MMDC0 is initiated */ -DATA 4, MX6_MMDC_P0_MDPDC, 0x0002002d -DATA 4, MX6_MMDC_P0_MDOTC, 0x00333030 -DATA 4, MX6_MMDC_P0_MDCFG0, 0x40445323 -DATA 4, MX6_MMDC_P0_MDCFG1, 0xb66e8c63 -DATA 4, MX6_MMDC_P0_MDCFG2, 0x01ff00db -DATA 4, MX6_MMDC_P0_MDMISC, 0x00081740 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008000 -DATA 4, MX6_MMDC_P0_MDRWD, 0x000026d2 -DATA 4, MX6_MMDC_P0_MDOR, 0x00440e21 -DATA 4, MX6_MMDC_P0_MDASP, 0x00000027 -DATA 4, MX6_MMDC_P0_MDCTL, 0x84190000 -/* MR2 */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008032 -DATA 4, MX6_MMDC_P0_MDSCR, 0x0400803a -/* MR3 */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x00008033 -DATA 4, MX6_MMDC_P0_MDSCR, 0x0000803b -/* MR1 */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x00428031 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00428039 -/* MR0 */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x07208030 -DATA 4, MX6_MMDC_P0_MDSCR, 0x07208038 -/* ZQ calibration */ -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008040 -DATA 4, MX6_MMDC_P0_MDSCR, 0x04008048 -/* final ddr setup */ -DATA 4, MX6_MMDC_P0_MDREF, 0x00005800 -DATA 4, MX6_MMDC_P0_MPODTCTRL, 0x00000007 -DATA 4, MX6_MMDC_P1_MPODTCTRL, 0x00000007 -DATA 4, MX6_MMDC_P0_MDPDC, 0x0002556d -DATA 4, MX6_MMDC_P1_MAPSR, 0x00011006 -DATA 4, MX6_MMDC_P0_MDSCR, 0x00000000 diff --git a/configs/aristainetos_defconfig b/configs/aristainetos_defconfig deleted file mode 100644 index a2baee764b..0000000000 --- a/configs/aristainetos_defconfig +++ /dev/null @@ -1,68 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_TARGET_ARISTAINETOS=y -CONFIG_ENV_SIZE=0x3000 -CONFIG_ENV_OFFSET=0xD0000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos.cfg,MX6DL" -CONFIG_BOOTDELAY=3 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_UBI=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_OFFSET_REDUND=0xE0000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_USDHC=y -CONFIG_NAND=y -CONFIG_NAND_MXS=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_BUS=3 -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_MTD=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ8XXX=y -CONFIG_MII=y -CONFIG_PWM_IMX=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO_IPUV3=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_IMX_WATCHDOG=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/aristainetos.h b/include/configs/aristainetos.h deleted file mode 100644 index 03e2a2bfbd..0000000000 --- a/include/configs/aristainetos.h +++ /dev/null @@ -1,43 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 - * (C) Copyright 2014 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6Q SabreSD board. - */ -#ifndef __ARISTAINETOS_CONFIG_H -#define __ARISTAINETOS_CONFIG_H - -#define CONFIG_SYS_BOARD_VERSION 1 -#define CONFIG_HOSTNAME "aristainetos" -#define CONFIG_BOARDNAME "aristainetos" - -#define CONFIG_MXC_UART_BASE UART5_BASE -#define CONSOLE_DEV "ttymxc4" - -#define CONFIG_FEC_XCV_TYPE RMII - -#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ - "board_type=aristainetos7@1\0" \ - "mtdids=nand0=gpmi-nand,nor0=spi3.0\0" \ - "mtdparts=mtdparts=spi3.0:832k(u-boot),64k(env),64k(env-red)," \ - "-(rescue-system);gpmi-nand:-(ubi)\0" \ - "addmisc=setenv bootargs ${bootargs} consoleblank=0\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "ubiargs=setenv bootargs console=${console},${baudrate} " \ - "ubi.mtd=0,2048 root=ubi0:rootfs rootfstype=ubifs\0 " \ - "ubifs_load_fit=sf probe;ubi part ubi 2048;ubifsmount ubi:rootfs;" \ - "ubifsload ${fit_addr_r} /boot/system.itb; " \ - "imi ${fit_addr_r}\0 " - -#define ARISTAINETOS_USB_OTG_PWR IMX_GPIO_NR(4, 15) -#define ARISTAINETOS_USB_H1_PWR IMX_GPIO_NR(3, 31) -#define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15) - -#include "aristainetos-common.h" - -#endif /* __ARISTAINETOS_CONFIG_H */
remove not anymore used aristainetos board. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
convert this driver to support DM.
Signed-off-by: Heiko Schocher hs@denx.de ---
drivers/video/lg4573.c | 175 +++++++++++++++++++++++++------- include/configs/aristainetos2.h | 2 - scripts/config_whitelist.txt | 2 - 3 files changed, 136 insertions(+), 43 deletions(-)
diff --git a/drivers/video/lg4573.c b/drivers/video/lg4573.c index 46d9ec83ce..997e854ef8 100644 --- a/drivers/video/lg4573.c +++ b/drivers/video/lg4573.c @@ -5,36 +5,40 @@ * */ #include <common.h> +#include <backlight.h> +#include <display.h> +#include <dm.h> +#include <dm/read.h> +#include <dm/uclass-internal.h> #include <errno.h> #include <spi.h> +#include <asm/gpio.h>
#define PWR_ON_DELAY_MSECS 120
-static int lb043wv_spi_write_u16(struct spi_slave *spi, u16 val) +static int lb043wv_spi_write_u16(struct spi_slave *slave, u16 val) { - unsigned long flags = SPI_XFER_BEGIN; unsigned short buf16 = htons(val); int ret = 0;
- flags |= SPI_XFER_END; - - ret = spi_xfer(spi, 16, &buf16, NULL, flags); + ret = spi_xfer(slave, 16, &buf16, NULL, + SPI_XFER_BEGIN | SPI_XFER_END); if (ret) debug("%s: Failed to send: %d\n", __func__, ret);
return ret; }
-static void lb043wv_spi_write_u16_array(struct spi_slave *spi, u16 *buff, +static void lb043wv_spi_write_u16_array(struct spi_slave *slave, u16 *buff, int size) { int i;
for (i = 0; i < size; i++) - lb043wv_spi_write_u16(spi, buff[i]); + lb043wv_spi_write_u16(slave, buff[i]); }
-static void lb043wv_display_mode_settings(struct spi_slave *spi) +static void lb043wv_display_mode_settings(struct spi_slave *slave) { static u16 display_mode_settings[] = { 0x703A, @@ -72,11 +76,11 @@ static void lb043wv_display_mode_settings(struct spi_slave *spi) };
debug("transfer display mode settings\n"); - lb043wv_spi_write_u16_array(spi, display_mode_settings, + lb043wv_spi_write_u16_array(slave, display_mode_settings, ARRAY_SIZE(display_mode_settings)); }
-static void lb043wv_power_settings(struct spi_slave *spi) +static void lb043wv_power_settings(struct spi_slave *slave) { static u16 power_settings[] = { 0x70C0, @@ -103,11 +107,11 @@ static void lb043wv_power_settings(struct spi_slave *spi) };
debug("transfer power settings\n"); - lb043wv_spi_write_u16_array(spi, power_settings, + lb043wv_spi_write_u16_array(slave, power_settings, ARRAY_SIZE(power_settings)); }
-static void lb043wv_gamma_settings(struct spi_slave *spi) +static void lb043wv_gamma_settings(struct spi_slave *slave) { static u16 gamma_settings[] = { 0x70D0, @@ -173,54 +177,57 @@ static void lb043wv_gamma_settings(struct spi_slave *spi) };
debug("transfer gamma settings\n"); - lb043wv_spi_write_u16_array(spi, gamma_settings, + lb043wv_spi_write_u16_array(slave, gamma_settings, ARRAY_SIZE(gamma_settings)); }
-static void lb043wv_display_on(struct spi_slave *spi) +static void lb043wv_display_on(struct spi_slave *slave) { static u16 sleep_out = 0x7011; static u16 display_on = 0x7029;
- lb043wv_spi_write_u16(spi, sleep_out); + lb043wv_spi_write_u16(slave, sleep_out); mdelay(PWR_ON_DELAY_MSECS); - lb043wv_spi_write_u16(spi, display_on); + lb043wv_spi_write_u16(slave, display_on); }
-int lg4573_spi_startup(unsigned int bus, unsigned int cs, - unsigned int max_hz, unsigned int spi_mode) +static int lg4573_spi_startup(struct spi_slave *slave) { - struct spi_slave *spi; int ret;
- spi = spi_setup_slave(bus, cs, max_hz, spi_mode); - if (!spi) { - debug("%s: Failed to set up slave\n", __func__); - return -1; - } - - ret = spi_claim_bus(spi); - if (ret) { - debug("%s: Failed to claim SPI bus: %d\n", __func__, ret); - goto err_claim_bus; - } + ret = spi_claim_bus(slave); + if (ret) + return ret;
- lb043wv_display_mode_settings(spi); - lb043wv_power_settings(spi); - lb043wv_gamma_settings(spi); + lb043wv_display_mode_settings(slave); + lb043wv_power_settings(slave); + lb043wv_gamma_settings(slave); + lb043wv_display_on(slave);
- lb043wv_display_on(spi); + spi_release_bus(slave); return 0; -err_claim_bus: - spi_free_slave(spi); - return -1; }
static int do_lgset(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) { - lg4573_spi_startup(CONFIG_LG4573_BUS, CONFIG_LG4573_CS, 10000000, - SPI_MODE_0); + struct spi_slave *slave; + struct udevice *dev; + int ret; + + ret = uclass_get_device_by_driver(UCLASS_DISPLAY, + DM_GET_DRIVER(lg4573_lcd), &dev); + if (ret) { + printf("%s: Could not get lg4573 device\n", __func__); + return ret; + } + slave = dev_get_parent_priv(dev); + if (!slave) { + printf("%s: No slave data\n", __func__); + return -ENODEV; + } + lg4573_spi_startup(slave); + return 0; }
@@ -229,3 +236,93 @@ U_BOOT_CMD( "set lgdisplay", "" ); + +static int lg4573_bind(struct udevice *dev) +{ + return 0; +} + +static int lg4573_probe(struct udevice *dev) +{ + return 0; +} + +static const struct udevice_id lg4573_ids[] = { + { .compatible = "lg,lg4573" }, + { } +}; + +struct lg4573_lcd_priv { + struct display_timing timing; + struct udevice *backlight; + struct gpio_desc enable; + int panel_bpp; + u32 power_on_delay; +}; + +static int lg4573_lcd_read_timing(struct udevice *dev, + struct display_timing *timing) +{ + struct lg4573_lcd_priv *priv = dev_get_priv(dev); + + memcpy(timing, &priv->timing, sizeof(struct display_timing)); + + return 0; +} + +static int lg4573_lcd_enable(struct udevice *dev, int bpp, + const struct display_timing *edid) +{ + struct spi_slave *slave = dev_get_parent_priv(dev); + struct lg4573_lcd_priv *priv = dev_get_priv(dev); + int ret = 0; + + dm_gpio_set_value(&priv->enable, 1); + ret = backlight_enable(priv->backlight); + + mdelay(priv->power_on_delay); + lg4573_spi_startup(slave); + + return ret; +}; + +static const struct dm_display_ops lg4573_lcd_ops = { + .read_timing = lg4573_lcd_read_timing, + .enable = lg4573_lcd_enable, +}; + +static int lg4573_ofdata_to_platdata(struct udevice *dev) +{ + struct lg4573_lcd_priv *priv = dev_get_priv(dev); + int ret; + + ret = uclass_get_device_by_phandle(UCLASS_PANEL_BACKLIGHT, dev, + "backlight", &priv->backlight); + if (ret) { + debug("%s: Cannot get backlight: ret=%d\n", __func__, ret); + return log_ret(ret); + } + ret = gpio_request_by_name(dev, "enable-gpios", 0, &priv->enable, + GPIOD_IS_OUT); + if (ret) { + debug("%s: Warning: cannot get enable GPIO: ret=%d\n", + __func__, ret); + if (ret != -ENOENT) + return log_ret(ret); + } + + priv->power_on_delay = dev_read_u32_default(dev, "power-on-delay", 10); + + return 0; +} + +U_BOOT_DRIVER(lg4573_lcd) = { + .name = "lg4573", + .id = UCLASS_DISPLAY, + .ops = &lg4573_lcd_ops, + .ofdata_to_platdata = lg4573_ofdata_to_platdata, + .of_match = lg4573_ids, + .bind = lg4573_bind, + .probe = lg4573_probe, + .priv_auto_alloc_size = sizeof(struct lg4573_lcd_priv), +}; diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 361e6ac654..d8858559d8 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -42,8 +42,6 @@ /* Framebuffer */ #define CONFIG_SYS_LDB_CLOCK 33246000 #define CONFIG_LG4573 -#define CONFIG_LG4573_BUS 0 -#define CONFIG_LG4573_CS 0
#include "aristainetos-common.h"
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index 7784922693..c8e5eebe00 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -1021,8 +1021,6 @@ CONFIG_LD9040 CONFIG_LEGACY CONFIG_LEGACY_BOOTCMD_ENV CONFIG_LG4573 -CONFIG_LG4573_BUS -CONFIG_LG4573_CS CONFIG_LINUX CONFIG_LINUX_RESET_VEC CONFIG_LITTLETON_LCD
convert this driver to support DM. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
move defines, which are already moved to Kconfig out of board config.
Signed-off-by: Heiko Schocher hs@denx.de ---
arch/arm/mach-imx/mx6/Kconfig | 9 +++++++ board/aristainetos/Kconfig | 15 ++++++++++- board/aristainetos/common/Kconfig | 38 +++++++++++++++++++++++++++ configs/aristainetos2_defconfig | 11 +++++--- configs/aristainetos2b_defconfig | 2 +- include/configs/aristainetos-common.h | 10 ------- include/configs/aristainetos2.h | 4 --- include/configs/aristainetos2b.h | 4 --- 8 files changed, 69 insertions(+), 24 deletions(-) create mode 100644 board/aristainetos/common/Kconfig
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 6c1a1120d8..90dc31a8dc 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -128,10 +128,19 @@ config TARGET_APALIS_IMX6 config TARGET_ARISTAINETOS2 bool "aristainetos2" select BOARD_LATE_INIT + select MX6DL + select SYS_I2C_MXC + select MXC_UART + select FEC_MXC + imply CMD_SATA
config TARGET_ARISTAINETOS2B bool "Support aristainetos2-revB" select BOARD_LATE_INIT + select MX6DL + select SYS_I2C_MXC + select MXC_UART + select FEC_MXC
config TARGET_CGTQMX6EVAL bool "cgtqmx6eval" diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig index 0341bdfb28..60ad69fa5b 100644 --- a/board/aristainetos/Kconfig +++ b/board/aristainetos/Kconfig @@ -1,19 +1,32 @@ if TARGET_ARISTAINETOS2
+source "board/aristainetos/common/Kconfig" + config SYS_BOARD default "aristainetos"
-config SYS_CONFIG_NAME +config SYS_BOARD_VERSION + default 2 + +config BOARDNAME default "aristainetos2"
endif
if TARGET_ARISTAINETOS2B
+source "board/aristainetos/common/Kconfig" + config SYS_BOARD default "aristainetos"
config SYS_CONFIG_NAME default "aristainetos2b"
+config SYS_BOARD_VERSION + default 3 + +config BOARDNAME + default "aristainetos2-revB" + endif diff --git a/board/aristainetos/common/Kconfig b/board/aristainetos/common/Kconfig new file mode 100644 index 0000000000..53a3f4d552 --- /dev/null +++ b/board/aristainetos/common/Kconfig @@ -0,0 +1,38 @@ +config BOARDNAME + string "name of the board" + help + set the name of the board. + +config SYS_BOARD_VERSION + int "select version of aristainetos board" + help + version of aristainetos board version + 2 version 2 + 3 version 2b + +config SYS_I2C_MXC_I2C1 + default y + +config SYS_I2C_MXC_I2C2 + default y + +config SYS_I2C_MXC_I2C3 + default y + +config SYS_I2C_MXC_I2C4 + default y + +config SYS_MALLOC_LEN + default 0x4000000 + +config ENV_SIZE + default 0x3000 + +config ENV_SECT_SIZE + default 0x10000 + +config ENV_OFFSET + default 0xd0000 + +config SYS_CONFIG_NAME + default "aristainetos2" diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 0c8958d57b..48e58e5be2 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -7,7 +7,7 @@ CONFIG_ENV_OFFSET=0xD0000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y @@ -17,12 +17,16 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set # CONFIG_CMD_FLASH is not set CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_SF=y +# CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y CONFIG_CMD_MII=y @@ -44,7 +48,6 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_FSL_USDHC=y CONFIG_NAND=y CONFIG_NAND_MXS=y -CONFIG_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=3 CONFIG_SF_DEFAULT_CS=1 CONFIG_SF_DEFAULT_MODE=0 @@ -66,4 +69,4 @@ CONFIG_VIDEO_IPUV3=y CONFIG_VIDEO=y # CONFIG_VIDEO_SW_CURSOR is not set CONFIG_IMX_WATCHDOG=y -CONFIG_OF_LIBFDT=y +# CONFIG_EFI_LOADER is not set diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig index c387009465..d64691df49 100644 --- a/configs/aristainetos2b_defconfig +++ b/configs/aristainetos2b_defconfig @@ -7,7 +7,7 @@ CONFIG_ENV_OFFSET=0xD0000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg,MX6DL" +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h index 1d84db5098..ab14a1a392 100644 --- a/include/configs/aristainetos-common.h +++ b/include/configs/aristainetos-common.h @@ -17,15 +17,9 @@ #define CONFIG_MACH_TYPE 4501 #define CONFIG_MMCROOT "/dev/mmcblk0p1"
-/* Size of malloc() pool */ -#define CONFIG_SYS_MALLOC_LEN (64 * SZ_1M) - -#define CONFIG_MXC_UART - /* MMC Configs */ #define CONFIG_SYS_FSL_ESDHC_ADDR 0
-#define CONFIG_FEC_MXC #define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_ETHPRIME "FEC" #define CONFIG_FEC_MXC_PHYADDR 0 @@ -151,10 +145,6 @@
/* I2C */ #define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_MXC -#define CONFIG_SYS_I2C_MXC_I2C1 /* enable I2C bus 1 */ -#define CONFIG_SYS_I2C_MXC_I2C2 /* enable I2C bus 2 */ -#define CONFIG_SYS_I2C_MXC_I2C3 /* enable I2C bus 3 */ #define CONFIG_SYS_I2C_SPEED 100000 #define CONFIG_SYS_I2C_SLAVE 0x7f #define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} } diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index d8858559d8..01998f0295 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -11,9 +11,7 @@ #ifndef __ARISTAINETOS2_CONFIG_H #define __ARISTAINETOS2_CONFIG_H
-#define CONFIG_SYS_BOARD_VERSION 2 #define CONFIG_HOSTNAME "aristainetos2" -#define CONFIG_BOARDNAME "aristainetos2"
#define CONFIG_MXC_UART_BASE UART2_BASE #define CONSOLE_DEV "ttymxc1" @@ -33,8 +31,6 @@ "ubifsload ${fit_addr_r} /boot/system.itb; " \ "imi ${fit_addr_r}\0 "
-#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ - #define ARISTAINETOS_USB_OTG_PWR IMX_GPIO_NR(4, 15) #define ARISTAINETOS_USB_H1_PWR IMX_GPIO_NR(1, 0) #define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15) diff --git a/include/configs/aristainetos2b.h b/include/configs/aristainetos2b.h index cdeb7a3b03..a7ba48e315 100644 --- a/include/configs/aristainetos2b.h +++ b/include/configs/aristainetos2b.h @@ -11,9 +11,7 @@ #ifndef __ARISTAINETOS2B_CONFIG_H #define __ARISTAINETOS2B_CONFIG_H
-#define CONFIG_SYS_BOARD_VERSION 3 #define CONFIG_HOSTNAME "aristainetos2" -#define CONFIG_BOARDNAME "aristainetos2-revB"
#define CONFIG_MXC_UART_BASE UART2_BASE #define CONSOLE_DEV "ttymxc1" @@ -33,8 +31,6 @@ "ubifsload ${fit_addr_r} /boot/system.itb; " \ "imi ${fit_addr_r}\0 " \
-#define CONFIG_SYS_I2C_MXC_I2C4 /* enable I2C bus 4 */ - #define ARISTAINETOS_USB_OTG_PWR IMX_GPIO_NR(4, 15) #define ARISTAINETOS_USB_H1_PWR IMX_GPIO_NR(1, 0) #define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15)
move defines, which are already moved to Kconfig out of board config. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
remove 2b version of aristainetos board, as it is easier to make the DM / DTS port and introduce the 2b board version again (also some more board version).
Signed-off-by: Heiko Schocher hs@denx.de ---
arch/arm/mach-imx/mx6/Kconfig | 8 ---- board/aristainetos/Kconfig | 18 --------- board/aristainetos/MAINTAINERS | 1 - board/aristainetos/common/Kconfig | 1 - configs/aristainetos2b_defconfig | 67 ------------------------------- include/configs/aristainetos2b.h | 46 --------------------- 6 files changed, 141 deletions(-) delete mode 100644 configs/aristainetos2b_defconfig delete mode 100644 include/configs/aristainetos2b.h
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 90dc31a8dc..3892d0a0e9 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -134,14 +134,6 @@ config TARGET_ARISTAINETOS2 select FEC_MXC imply CMD_SATA
-config TARGET_ARISTAINETOS2B - bool "Support aristainetos2-revB" - select BOARD_LATE_INIT - select MX6DL - select SYS_I2C_MXC - select MXC_UART - select FEC_MXC - config TARGET_CGTQMX6EVAL bool "cgtqmx6eval" select BOARD_LATE_INIT diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig index 60ad69fa5b..2bb12fce75 100644 --- a/board/aristainetos/Kconfig +++ b/board/aristainetos/Kconfig @@ -12,21 +12,3 @@ config BOARDNAME default "aristainetos2"
endif - -if TARGET_ARISTAINETOS2B - -source "board/aristainetos/common/Kconfig" - -config SYS_BOARD - default "aristainetos" - -config SYS_CONFIG_NAME - default "aristainetos2b" - -config SYS_BOARD_VERSION - default 3 - -config BOARDNAME - default "aristainetos2-revB" - -endif diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS index c9e05285df..7e9f38d174 100644 --- a/board/aristainetos/MAINTAINERS +++ b/board/aristainetos/MAINTAINERS @@ -4,4 +4,3 @@ S: Maintained F: board/aristainetos/ F: include/configs/aristainetos2.h F: configs/aristainetos2_defconfig -F: configs/aristainetos2b_defconfig diff --git a/board/aristainetos/common/Kconfig b/board/aristainetos/common/Kconfig index 53a3f4d552..16c1325889 100644 --- a/board/aristainetos/common/Kconfig +++ b/board/aristainetos/common/Kconfig @@ -8,7 +8,6 @@ config SYS_BOARD_VERSION help version of aristainetos board version 2 version 2 - 3 version 2b
config SYS_I2C_MXC_I2C1 default y diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig deleted file mode 100644 index d64691df49..0000000000 --- a/configs/aristainetos2b_defconfig +++ /dev/null @@ -1,67 +0,0 @@ -CONFIG_ARM=y -CONFIG_ARCH_MX6=y -CONFIG_SYS_TEXT_BASE=0x17800000 -CONFIG_TARGET_ARISTAINETOS2B=y -CONFIG_ENV_SIZE=0x3000 -CONFIG_ENV_OFFSET=0xD0000 -CONFIG_NR_DRAM_BANKS=1 -CONFIG_ENV_SECT_SIZE=0x10000 -CONFIG_FIT=y -CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" -CONFIG_BOOTDELAY=3 -# CONFIG_CONSOLE_MUX is not set -CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y -CONFIG_SUPPORT_RAW_INITRD=y -CONFIG_BOUNCE_BUFFER=y -CONFIG_BOARD_EARLY_INIT_F=y -CONFIG_HUSH_PARSER=y -CONFIG_CMD_BOOTZ=y -# CONFIG_CMD_FLASH is not set -CONFIG_CMD_GPIO=y -CONFIG_CMD_I2C=y -CONFIG_CMD_MMC=y -CONFIG_CMD_NAND_TRIMFFS=y -CONFIG_CMD_SF=y -CONFIG_CMD_USB=y -CONFIG_CMD_DHCP=y -CONFIG_CMD_MII=y -CONFIG_CMD_PING=y -CONFIG_CMD_BMP=y -CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y -CONFIG_CMD_EXT2=y -CONFIG_CMD_EXT4=y -CONFIG_CMD_EXT4_WRITE=y -CONFIG_CMD_FAT=y -CONFIG_CMD_FS_GENERIC=y -CONFIG_CMD_MTDPARTS=y -CONFIG_CMD_UBI=y -CONFIG_ENV_IS_IN_SPI_FLASH=y -CONFIG_SYS_REDUNDAND_ENVIRONMENT=y -CONFIG_ENV_OFFSET_REDUND=0xE0000 -CONFIG_SYS_RELOC_GD_ENV_ADDR=y -CONFIG_FSL_USDHC=y -CONFIG_NAND=y -CONFIG_NAND_MXS=y -CONFIG_SPI_FLASH=y -CONFIG_SF_DEFAULT_MODE=0 -CONFIG_SF_DEFAULT_SPEED=20000000 -CONFIG_SPI_FLASH_STMICRO=y -CONFIG_SPI_FLASH_MTD=y -CONFIG_MTD_UBI_FASTMAP=y -CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 -CONFIG_PHYLIB=y -CONFIG_PHY_MICREL=y -CONFIG_PHY_MICREL_KSZ90X1=y -CONFIG_MII=y -CONFIG_PWM_IMX=y -CONFIG_SPI=y -CONFIG_MXC_SPI=y -CONFIG_USB=y -CONFIG_USB_STORAGE=y -CONFIG_VIDEO_IPUV3=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set -CONFIG_IMX_WATCHDOG=y -CONFIG_OF_LIBFDT=y diff --git a/include/configs/aristainetos2b.h b/include/configs/aristainetos2b.h deleted file mode 100644 index a7ba48e315..0000000000 --- a/include/configs/aristainetos2b.h +++ /dev/null @@ -1,46 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6DL aristainetos2 board. - */ -#ifndef __ARISTAINETOS2B_CONFIG_H -#define __ARISTAINETOS2B_CONFIG_H - -#define CONFIG_HOSTNAME "aristainetos2" - -#define CONFIG_MXC_UART_BASE UART2_BASE -#define CONSOLE_DEV "ttymxc1" - -#define CONFIG_FEC_XCV_TYPE RGMII - -#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ - "board_type=aristainetos2_7@1\0" \ - "nor_bootdelay=-2\0" \ - "mtdids=nand0=gpmi-nand,nor0=spi0.0\0" \ - "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ - "-(rescue-system);gpmi-nand:-(ubi)\0" \ - "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0\0" \ - "ubiargs=setenv bootargs console=${console},${baudrate} " \ - "ubi.mtd=0,4096 root=ubi0:rootfs rootfstype=ubifs\0 " \ - "ubifs_load_fit=sf probe;ubi part ubi 4096;ubifsmount ubi:rootfs;" \ - "ubifsload ${fit_addr_r} /boot/system.itb; " \ - "imi ${fit_addr_r}\0 " \ - -#define ARISTAINETOS_USB_OTG_PWR IMX_GPIO_NR(4, 15) -#define ARISTAINETOS_USB_H1_PWR IMX_GPIO_NR(1, 0) -#define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15) - -/* Framebuffer */ -#define CONFIG_SYS_LDB_CLOCK 33246000 -#define CONFIG_LG4573 -#define CONFIG_LG4573_BUS 0 -#define CONFIG_LG4573_CS 1 - -#include "aristainetos-common.h" - -#endif /* __ARISTAINETOS2B_CONFIG_H */
remove 2b version of aristainetos board, as it is easier to make the DM / DTS port and introduce the 2b board version again (also some more board version). Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
gigabit support does not work on the aristainetos board, so disable it.
Signed-off-by: Heiko Schocher hs@denx.de ---
include/configs/aristainetos-common.h | 1 + 1 file changed, 1 insertion(+)
diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h index ab14a1a392..9a6c205c72 100644 --- a/include/configs/aristainetos-common.h +++ b/include/configs/aristainetos-common.h @@ -27,6 +27,7 @@ #define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
#define CONFIG_EXTRA_ENV_SETTINGS \ + "disable_giga=yes\0" \ "script=u-boot.scr\0" \ "fit_file=/boot/system.itb\0" \ "loadaddr=0x12000000\0" \
gigabit support does not work on the aristainetos board, so disable it. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
Add device trees from Linux in preparation for driver model conversions.
device tree files taken from Linux: 71ae5fc87c34: "Merge tag 'linux-kselftest-5.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest"
and added SPDX license identifier.
Signed-off-by: Heiko Schocher hs@denx.de ---
arch/arm/dts/Makefile | 2 + arch/arm/dts/imx6dl-aristainetos2_4.dts | 124 +++++ arch/arm/dts/imx6dl-aristainetos2_7.dts | 64 +++ arch/arm/dts/imx6qdl-aristainetos2.dtsi | 611 ++++++++++++++++++++++++ board/aristainetos/MAINTAINERS | 3 + 5 files changed, 804 insertions(+) create mode 100644 arch/arm/dts/imx6dl-aristainetos2_4.dts create mode 100644 arch/arm/dts/imx6dl-aristainetos2_7.dts create mode 100644 arch/arm/dts/imx6qdl-aristainetos2.dtsi
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index d8846df1bd..a2d673af4f 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -574,6 +574,8 @@ dtb-$(CONFIG_MX53) += imx53-cx9020.dtb \
ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),) dtb-y += \ + imx6dl-aristainetos2_4.dtb \ + imx6dl-aristainetos2_7.dtb \ imx6dl-brppt2.dtb \ imx6dl-dhcom-pdk2.dtb \ imx6dl-icore.dtb \ diff --git a/arch/arm/dts/imx6dl-aristainetos2_4.dts b/arch/arm/dts/imx6dl-aristainetos2_4.dts new file mode 100644 index 0000000000..0e28a70e78 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2_4.dts @@ -0,0 +1,124 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2 board + * + * Copyright (C) 2019 Heiko Schocher hs@denx.de + * Copyright (C) 2015 Heiko Schocher hs@denx.de + * + */ +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-aristainetos2.dtsi" + +/ { + model = "aristainetos2 i.MX6 Dual Lite Board 4"; + compatible = "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + display0: disp0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp>; + + port@0 { + reg = <0>; + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&ecspi1 { + lcd_panel: display@0 { + compatible = "lg,lg4573"; + spi-max-frequency = <10000000>; + reg = <0>; + power-on-delay = <10>; + + display-timings { + 480x800p57 { + native-mode; + clock-frequency = <27000027>; + hactive = <480>; + vactive = <800>; + hfront-porch = <10>; + hback-porch = <59>; + hsync-len = <10>; + vback-porch = <15>; + vfront-porch = <15>; + vsync-len = <15>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; +}; + +&i2c3 { + touch: touch@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + interrupt-parent = <&gpio2>; + interrupts = <9 8>; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&iomuxc { + pinctrl_ipu_disp: ipudisp1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x31 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xE1 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xE1 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xE1 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xE1 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xE1 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xE1 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xE1 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xE1 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xE1 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xE1 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xE1 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xE1 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xE1 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xE1 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xE1 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xe1 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xE1 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xE1 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xE1 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xE1 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xE1 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xE1 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xE1 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xE1 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xE1 + >; + }; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_7.dts b/arch/arm/dts/imx6dl-aristainetos2_7.dts new file mode 100644 index 0000000000..320dbcffaf --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2_7.dts @@ -0,0 +1,64 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2 board + * + * Copyright (C) 2019 Heiko Schocher hs@denx.de + * Copyright (C) 2015 Heiko Schocher hs@denx.de + * + */ +/dts-v1/; +#include "imx6dl.dtsi" +#include "imx6qdl-aristainetos2.dtsi" + +/ { + model = "aristainetos2 i.MX6 Dual Lite Board 7"; + compatible = "fsl,imx6dl"; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + panel: panel { + compatible = "lg,lb070wv8"; + backlight = <&backlight>; + enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&i2c3 { + touch: touch@4d { + compatible = "atmel,maxtouch"; + reg = <0x4d>; + interrupt-parent = <&gpio2>; + interrupts = <9 8>; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&ipu1_di0_lvds0>; + }; + }; + + port@4 { + reg = <4>; + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/dts/imx6qdl-aristainetos2.dtsi new file mode 100644 index 0000000000..da6ab63808 --- /dev/null +++ b/arch/arm/dts/imx6qdl-aristainetos2.dtsi @@ -0,0 +1,611 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2 board + * + * Copyright (C) 2019 Heiko Schocher hs@denx.de + * Copyright (C) 2015 Heiko Schocher hs@denx.de + * + */ +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/imx6qdl-clock.h> + +/ { + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + enable-gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbh1_vbus: regulator-usbh1-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_aristainetos2_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbotg_vbus: regulator-usbotg-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_aristainetos2_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&ecspi1 { + cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH + &gpio4 10 GPIO_ACTIVE_HIGH + &gpio4 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; +}; + +&ecspi2 { + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH &gpio2 27 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; +}; + +&ecspi4 { + cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + status = "okay"; + + flash: m25p80@1 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <1>; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + pmic@58 { + compatible = "dlg,da9063"; + reg = <0x58>; + interrupt-parent = <&gpio1>; + interrupts = <04 0x8>; + + regulators { + bcore1 { + regulator-name = "bcore1"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + bcore2 { + regulator-name = "bcore2"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + bpro { + regulator-name = "bpro"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + bperi { + regulator-name = "bperi"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + bmem { + regulator-name = "bmem"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo2 { + regulator-name = "ldo2"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1800000>; + }; + + ldo3 { + regulator-name = "ldo3"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo4 { + regulator-name = "ldo4"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo5 { + regulator-name = "ldo5"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6 { + regulator-name = "ldo6"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo7 { + regulator-name = "ldo7"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo8 { + regulator-name = "ldo8"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo9 { + regulator-name = "ldo9"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo10 { + regulator-name = "ldo10"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo11 { + regulator-name = "ldo11"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + bio { + regulator-name = "bio"; + regulator-always-on = <1>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + + tmp103: tmp103@71 { + compatible = "ti,tmp103"; + reg = <0x71>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + expander: tca6416@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + }; + + rtc@68 { + compatible = "dallas,m41t00"; + reg = <0x68>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + eeprom@50{ + compatible = "atmel,24c64"; + reg = <0x50>; + }; + + eeprom@57{ + compatible = "atmel,24c64"; + reg = <0x57>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + phy-reset-gpios = <&gpio7 18 GPIO_ACTIVE_LOW>; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + status = "okay"; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&pcie { + reset-gpio = <&gpio2 16 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usbh1_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "host"; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + no-1-8-v; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio>; + + pinctrl_audmux: audmux { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 + >; + }; + + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + MX6QDL_PAD_KEY_ROW1__GPIO4_IO09 0x100b1 /* SS0# */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 /* SS1# */ + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 /* SS2# */ + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 /* SS0# */ + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 /* SS1# */ + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + /* led enable */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + /* LCD power enable */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 + /* led yellow */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 + /* led red */ + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 + /* led green */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 + /* led blue */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 + /* Profibus IRQ */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + /* FPGA IRQ */ + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 + /* spi bus #2 SS driver enable */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 + /* RST_LOC# PHY reset input (has pull-down!)*/ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + /* USB_OTG_ID = GPIO1_24*/ + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x80000000 + /* Touchscreen IRQ */ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 + /* PCIe reset */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b0 + >; + }; + + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 + /* backlight enable */ + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_GPIO_1__USB_OTG_ID 0x17059 + >; + }; + + pinctrl_aristainetos2_usbh1_vbus: aristainetos-usbh1-vbus { + fsl,pins = <MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x130b0>; + }; + + pinctrl_aristainetos2_usbotg_vbus: aristainetos-usbotg-vbus { + fsl,pins = <MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x130b0>; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + /* SD1 card detect input */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 + /* SD1 write protect input */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 + /* SD2 level shifter output enable */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 + /* SD2 card detect input */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + /* SD2 write protect input */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 + >; + }; +}; diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS index 7e9f38d174..91c8ae0738 100644 --- a/board/aristainetos/MAINTAINERS +++ b/board/aristainetos/MAINTAINERS @@ -4,3 +4,6 @@ S: Maintained F: board/aristainetos/ F: include/configs/aristainetos2.h F: configs/aristainetos2_defconfig +F: arch/arm/dts/imx6dl-aristainetos2_4.dts +F: arch/arm/dts/imx6dl-aristainetos2_7.dts +F: arch/arm/dts/imx6qdl-aristainetos2.dtsi
Add device trees from Linux in preparation for driver model conversions. device tree files taken from Linux: 71ae5fc87c34: "Merge tag 'linux-kselftest-5.2-rc1' of git://git.kernel.org/pub/scm/linux/kernel/git/shuah/linux-kselftest" and added SPDX license identifier. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
add thumb build to aristainetos build to save binary space.
Signed-off-by: Heiko Schocher hs@denx.de ---
configs/aristainetos2_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 48e58e5be2..4434d92e74 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -1,4 +1,5 @@ CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 CONFIG_TARGET_ARISTAINETOS2=y
add thumb build to aristainetos build to save binary space. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
remove aristainetos-v2.c file, as we now want to switch to DM/DTS support and have all board specific code in one file. Goal is to setup differences through DT.
Signed-off-by: Heiko Schocher hs@denx.de ---
board/aristainetos/aristainetos-v2.c | 686 -------------------------- board/aristainetos/aristainetos.c | 648 +++++++++++++++++++++++- include/configs/aristainetos-common.h | 186 ------- include/configs/aristainetos2.h | 170 ++++++- 4 files changed, 815 insertions(+), 875 deletions(-) delete mode 100644 board/aristainetos/aristainetos-v2.c delete mode 100644 include/configs/aristainetos-common.h
diff --git a/board/aristainetos/aristainetos-v2.c b/board/aristainetos/aristainetos-v2.c deleted file mode 100644 index c0a2e41f02..0000000000 --- a/board/aristainetos/aristainetos-v2.c +++ /dev/null @@ -1,686 +0,0 @@ -// SPDX-License-Identifier: GPL-2.0+ -/* - * (C) Copyright 2015 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * - * Author: Fabio Estevam fabio.estevam@freescale.com - */ - -#include <asm/arch/clock.h> -#include <asm/arch/imx-regs.h> -#include <asm/arch/iomux.h> -#include <asm/arch/mx6-pins.h> -#include <env.h> -#include <linux/errno.h> -#include <asm/gpio.h> -#include <asm/mach-imx/iomux-v3.h> -#include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/mxc_i2c.h> -#include <asm/mach-imx/video.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> -#include <miiphy.h> -#include <netdev.h> -#include <asm/arch/mxc_hdmi.h> -#include <asm/arch/crm_regs.h> -#include <linux/fb.h> -#include <ipu_pixfmt.h> -#include <asm/io.h> -#include <asm/arch/sys_proto.h> -#include <pwm.h> -#include <micrel.h> -#include <spi.h> -#include <video.h> -#include <../drivers/video/imx/ipu.h> -#if defined(CONFIG_VIDEO_BMP_LOGO) - #include <bmp_logo.h> -#endif - -#define USDHC2_PAD_CTRL (PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - -#if (CONFIG_SYS_BOARD_VERSION == 2) - /* 4.3 display controller */ - #define ECSPI1_CS0 IMX_GPIO_NR(4, 9) - #define ECSPI4_CS0 IMX_GPIO_NR(3, 29) -#elif (CONFIG_SYS_BOARD_VERSION == 3) - #define ECSPI1_CS0 IMX_GPIO_NR(2, 30) /* NOR flash */ - /* 4.3 display controller */ - #define ECSPI1_CS1 IMX_GPIO_NR(4, 10) -#endif - -#define SOFT_RESET_GPIO IMX_GPIO_NR(7, 13) -#define SD2_DRIVER_ENABLE IMX_GPIO_NR(7, 8) - -struct i2c_pads_info i2c_pad_info3 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC, - .gp = IMX_GPIO_NR(1, 5) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, - .gp = IMX_GPIO_NR(1, 6) - } -}; - -struct i2c_pads_info i2c_pad_info4 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_7__I2C4_SCL | PC, - .gpio_mode = MX6_PAD_GPIO_7__GPIO1_IO07 | PC, - .gp = IMX_GPIO_NR(1, 7) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_8__I2C4_SDA | PC, - .gpio_mode = MX6_PAD_GPIO_8__GPIO1_IO08 | PC, - .gp = IMX_GPIO_NR(1, 8) - } -}; - -iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D19__UART1_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D20__UART1_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const uart3_pads[] = { - MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const gpio_pads[] = { - /* LED enable*/ - MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* LED yellow */ - MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* LED red */ -#if (CONFIG_SYS_BOARD_VERSION == 2) - MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), -#elif (CONFIG_SYS_BOARD_VERSION == 3) - MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), -#endif - /* LED green */ - MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* LED blue */ - MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* spi flash WP protect */ - MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* spi CS 0 */ - MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* spi bus #2 SS driver enable */ - MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* RST_LOC# PHY reset input (has pull-down!)*/ - MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* SD 2 level shifter output enable */ - MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* SD1 card detect input */ - MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* SD1 write protect input */ - MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* SD2 card detect input */ - MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* SD2 write protect input */ - MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* Touchscreen IRQ */ - MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const misc_pads[] = { - /* USB_OTG_ID = GPIO1_24*/ - MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), - /* H1 Power enable = GPIO1_0*/ - MX6_PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), - /* OTG Power enable = GPIO4_15*/ - MX6_PAD_KEY_ROW4__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - -static iomux_v3_cfg_t const backlight_pads[] = { - /* backlight PWM brightness control */ - MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), - /* backlight enable */ - MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* LCD power enable */ - MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - -static iomux_v3_cfg_t const ecspi1_pads[] = { - MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), -#if (CONFIG_SYS_BOARD_VERSION == 2) - MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(SPI_PAD_CTRL), -#elif (CONFIG_SYS_BOARD_VERSION == 3) - MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), -#endif -}; - -static void setup_iomux_enet(void) -{ - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); -} - -#if (CONFIG_SYS_BOARD_VERSION == 2) -iomux_v3_cfg_t const ecspi4_pads[] = { - MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; -#endif - -static iomux_v3_cfg_t const display_pads[] = { - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL), - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, -}; - -int board_spi_cs_gpio(unsigned bus, unsigned cs) -{ - if (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS) -#if (CONFIG_SYS_BOARD_VERSION == 2) - return IMX_GPIO_NR(5, 2); - - if (bus == 0 && cs == 0) - return IMX_GPIO_NR(4, 9); -#elif (CONFIG_SYS_BOARD_VERSION == 3) - return ECSPI1_CS0; - - if (bus == 0 && cs == 1) - return ECSPI1_CS1; -#endif - return -1; -} - -static void setup_spi(void) -{ - int i; - - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); - -#if (CONFIG_SYS_BOARD_VERSION == 2) - imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads)); -#endif - - for (i = 0; i < 4; i++) - enable_spi_clk(true, i); - - gpio_direction_output(ECSPI1_CS0, 1); -#if (CONFIG_SYS_BOARD_VERSION == 2) - gpio_direction_output(ECSPI4_CS1, 0); - /* set cs0 to high (second device on spi bus #4) */ - gpio_direction_output(ECSPI4_CS0, 1); -#elif (CONFIG_SYS_BOARD_VERSION == 3) - gpio_direction_output(ECSPI1_CS1, 1); -#endif -} - -static void setup_iomux_uart(void) -{ - switch (CONFIG_MXC_UART_BASE) { - case UART1_BASE: - imx_iomux_v3_setup_multiple_pads(uart1_pads, - ARRAY_SIZE(uart1_pads)); - break; - case UART2_BASE: - imx_iomux_v3_setup_multiple_pads(uart2_pads, - ARRAY_SIZE(uart2_pads)); - break; - case UART3_BASE: - imx_iomux_v3_setup_multiple_pads(uart3_pads, - ARRAY_SIZE(uart3_pads)); - break; - case UART4_BASE: - imx_iomux_v3_setup_multiple_pads(uart4_pads, - ARRAY_SIZE(uart4_pads)); - break; - } -} - -int board_phy_config(struct phy_device *phydev) -{ - /* control data pad skew - devaddr = 0x02, register = 0x04 */ - ksz9031_phy_extended_write(phydev, 0x02, - MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); - /* rx data pad skew - devaddr = 0x02, register = 0x05 */ - ksz9031_phy_extended_write(phydev, 0x02, - MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); - /* tx data pad skew - devaddr = 0x02, register = 0x06 */ - ksz9031_phy_extended_write(phydev, 0x02, - MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); - /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ - ksz9031_phy_extended_write(phydev, 0x02, - MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, - MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF); - - if (phydev->drv->config) - phydev->drv->config(phydev); - - return 0; -} - -int board_eth_init(bd_t *bis) -{ - setup_iomux_enet(); - return cpu_eth_init(bis); -} - -static int rotate_logo_one(unsigned char *out, unsigned char *in) -{ - int i, j; - - for (i = 0; i < BMP_LOGO_WIDTH; i++) - for (j = 0; j < BMP_LOGO_HEIGHT; j++) - out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] = - in[i * BMP_LOGO_WIDTH + j]; - return 0; -} - -/* - * Rotate the BMP_LOGO (only) - * Will only work, if the logo is square, as - * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables - */ -void rotate_logo(int rotations) -{ - unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT]; - unsigned char *in_logo; - int i, j; - - if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT) - return; - - in_logo = bmp_logo_bitmap; - - /* one 90 degree rotation */ - if (rotations == 1 || rotations == 2 || rotations == 3) - rotate_logo_one(out_logo, in_logo); - - /* second 90 degree rotation */ - if (rotations == 2 || rotations == 3) - rotate_logo_one(in_logo, out_logo); - - /* third 90 degree rotation */ - if (rotations == 3) - rotate_logo_one(out_logo, in_logo); - - /* copy result back to original array */ - if (rotations == 1 || rotations == 3) - for (i = 0; i < BMP_LOGO_WIDTH; i++) - for (j = 0; j < BMP_LOGO_HEIGHT; j++) - in_logo[i * BMP_LOGO_WIDTH + j] = - out_logo[i * BMP_LOGO_WIDTH + j]; -} - -static void enable_display_power(void) -{ - imx_iomux_v3_setup_multiple_pads(backlight_pads, - ARRAY_SIZE(backlight_pads)); - - /* backlight enable */ - gpio_direction_output(IMX_GPIO_NR(6, 31), 1); - /* LCD power enable */ - gpio_direction_output(IMX_GPIO_NR(6, 15), 1); - - /* enable backlight PWM 1 */ - if (pwm_init(0, 0, 0)) - goto error; - /* duty cycle 500ns, period: 3000ns */ - if (pwm_config(0, 50000, 300000)) - goto error; - if (pwm_enable(0)) - goto error; - return; - -error: - puts("error init pwm for backlight\n"); - return; -} - -static void enable_lvds(struct display_info_t const *dev) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - int reg; - s32 timeout = 100000; - - /* set PLL5 clock */ - reg = readl(&ccm->analog_pll_video); - reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN; - writel(reg, &ccm->analog_pll_video); - - /* set PLL5 to 232720000Hz */ - reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; - reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26); - reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; - reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0); - writel(reg, &ccm->analog_pll_video); - - writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238), - &ccm->analog_pll_video_num); - writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240), - &ccm->analog_pll_video_denom); - - reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; - writel(reg, &ccm->analog_pll_video); - - while (timeout--) - if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) - break; - if (timeout < 0) - printf("Warning: video pll lock timeout!\n"); - - reg = readl(&ccm->analog_pll_video); - reg |= BM_ANADIG_PLL_VIDEO_ENABLE; - reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; - writel(reg, &ccm->analog_pll_video); - - /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */ - reg = readl(&ccm->cs2cdr); - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK - | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); - reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) - | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); - writel(reg, &ccm->cs2cdr); - - reg = readl(&ccm->cscmr2); - reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; - writel(reg, &ccm->cscmr2); - - reg = readl(&ccm->chsccdr); - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 - << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); - writel(reg, &ccm->chsccdr); - - reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES - | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH - | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH - | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG - | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT - | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED - | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; - writel(reg, &iomux->gpr[2]); - - reg = readl(&iomux->gpr[3]); - reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) - | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 - << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); - writel(reg, &iomux->gpr[3]); - - return; -} - -static void enable_spi_display(struct display_info_t const *dev) -{ - struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; - struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; - int reg; - s32 timeout = 100000; - -#if defined(CONFIG_VIDEO_BMP_LOGO) - rotate_logo(3); /* portrait display in landscape mode */ -#endif - - /* - * set ldb clock to 28341000 Hz calculated through the formula: - * (XRES + LEFT_M + RIGHT_M + HSYNC_LEN) * - * (YRES + UPPER_M + LOWER_M + VSYNC_LEN) * REFRESH) - * see: - * https://community.freescale.com/thread/308170 - */ - ipu_set_ldb_clock(28341000); - - reg = readl(&ccm->cs2cdr); - - /* select pll 5 clock */ - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK - | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); - writel(reg, &ccm->cs2cdr); - - /* set PLL5 to 197994996Hz */ - reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; - reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21); - reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; - reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0); - writel(reg, &ccm->analog_pll_video); - - writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4), - &ccm->analog_pll_video_num); - writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240), - &ccm->analog_pll_video_denom); - - reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; - writel(reg, &ccm->analog_pll_video); - - while (timeout--) - if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) - break; - if (timeout < 0) - printf("Warning: video pll lock timeout!\n"); - - reg = readl(&ccm->analog_pll_video); - reg |= BM_ANADIG_PLL_VIDEO_ENABLE; - reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; - writel(reg, &ccm->analog_pll_video); - - /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */ - reg = readl(&ccm->cs2cdr); - reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK - | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); - reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) - | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); - writel(reg, &ccm->cs2cdr); - - reg = readl(&ccm->cscmr2); - reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; - writel(reg, &ccm->cscmr2); - - reg = readl(&ccm->chsccdr); - reg |= (CHSCCDR_CLK_SEL_LDB_DI0 - << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); - reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK; - reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET); - reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK; - reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); - writel(reg, &ccm->chsccdr); - - reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES - | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH - | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH - | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG - | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT - | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED - | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; - writel(reg, &iomux->gpr[2]); - - reg = readl(&iomux->gpr[3]); - reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) - | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 - << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); - writel(reg, &iomux->gpr[3]); - - imx_iomux_v3_setup_multiple_pads( - display_pads, - ARRAY_SIZE(display_pads)); - - return; -} -static void setup_display(void) -{ - enable_ipu_clock(); - enable_display_power(); -} - -static void setup_iomux_gpio(void) -{ - imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); -} - -static void set_gpr_register(void) -{ - struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; - - writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 | - IOMUXC_GPR1_EXC_MON_SLVE | - (2 << IOMUXC_GPR1_ADDRS0_OFFSET) | - IOMUXC_GPR1_ACT_CS0, - &iomuxc_regs->gpr[1]); - writel(0x0, &iomuxc_regs->gpr[8]); - writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN | - IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN, - &iomuxc_regs->gpr[12]); -} - -int board_early_init_f(void) -{ - setup_iomux_uart(); - setup_iomux_gpio(); - - gpio_direction_output(SOFT_RESET_GPIO, 1); - gpio_direction_output(SD2_DRIVER_ENABLE, 1); - setup_display(); - set_gpr_register(); - return 0; -} - -static void setup_i2c4(void) -{ - setup_i2c(3, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, - &i2c_pad_info4); -} - -static void setup_board_gpio(void) -{ - /* enable all LEDs */ - gpio_request(IMX_GPIO_NR(2, 13), "LED ena"); /* 25 */ - gpio_direction_output(IMX_GPIO_NR(1, 25), 0); - - /* switch off Status LEDs */ -#if (CONFIG_SYS_BOARD_VERSION == 2) - gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */ - gpio_direction_output(IMX_GPIO_NR(6, 16), 1); - gpio_request(IMX_GPIO_NR(2, 28), "LED red"); /* 60 */ - gpio_direction_output(IMX_GPIO_NR(2, 28), 1); - gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */ - gpio_direction_output(IMX_GPIO_NR(5, 4), 1); - gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */ - gpio_direction_output(IMX_GPIO_NR(2, 29), 1); -#elif (CONFIG_SYS_BOARD_VERSION == 3) - gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */ - gpio_direction_output(IMX_GPIO_NR(6, 16), 0); - gpio_request(IMX_GPIO_NR(5, 0), "LED red"); /* 128 */ - gpio_direction_output(IMX_GPIO_NR(5, 0), 0); - gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */ - gpio_direction_output(IMX_GPIO_NR(5, 4), 0); - gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */ - gpio_direction_output(IMX_GPIO_NR(2, 29), 0); -#endif -} - -static void setup_board_spi(void) -{ - /* enable spi bus #2 SS drivers (and spi bus #4 SS1 for rev2b) */ - gpio_direction_output(IMX_GPIO_NR(6, 6), 1); -} - -int board_late_init(void) -{ - char *my_bootdelay; - char bootmode = 0; - char const *panel = env_get("panel"); - - /* - * Check the boot-source. If booting from NOR Flash, - * disable bootdelay - */ - gpio_request(IMX_GPIO_NR(7, 6), "bootsel0"); - gpio_direction_input(IMX_GPIO_NR(7, 6)); - gpio_request(IMX_GPIO_NR(7, 7), "bootsel1"); - gpio_direction_input(IMX_GPIO_NR(7, 7)); - gpio_request(IMX_GPIO_NR(7, 1), "bootsel2"); - gpio_direction_input(IMX_GPIO_NR(7, 1)); - bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 6)) ? 1 : 0) << 0; - bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 7)) ? 1 : 0) << 1; - bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 1)) ? 1 : 0) << 2; - - if (bootmode == 7) { - my_bootdelay = env_get("nor_bootdelay"); - if (my_bootdelay != NULL) - env_set("bootdelay", my_bootdelay); - else - env_set("bootdelay", "-2"); - } - - /* if we have the lg panel, we can initialze it now */ - if (panel) - if (!strcmp(panel, displays[1].mode.name)) - lg4573_spi_startup(CONFIG_LG4573_BUS, - CONFIG_LG4573_CS, - 10000000, SPI_MODE_0); - - return 0; -} diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 873b354db8..11b64d08be 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -31,6 +31,14 @@ #include <asm/io.h> #include <asm/arch/sys_proto.h> #include <pwm.h> +#include <env.h> +#include <micrel.h> +#include <spi.h> +#include <video.h> +#include <../drivers/video/imx/ipu.h> +#if defined(CONFIG_VIDEO_BMP_LOGO) + #include <bmp_logo.h> +#endif
DECLARE_GLOBAL_DATA_PTR;
@@ -58,10 +66,646 @@ DECLARE_GLOBAL_DATA_PTR;
#define ECSPI4_CS1 IMX_GPIO_NR(5, 2)
-#if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3)) -#include "./aristainetos-v2.c" +#define USDHC2_PAD_CTRL (PAD_CTL_SPEED_LOW | \ + PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) + +#if (CONFIG_SYS_BOARD_VERSION == 2) + /* 4.3 display controller */ + #define ECSPI1_CS0 IMX_GPIO_NR(4, 9) + #define ECSPI4_CS0 IMX_GPIO_NR(3, 29) +#elif (CONFIG_SYS_BOARD_VERSION == 3) + #define ECSPI1_CS0 IMX_GPIO_NR(2, 30) /* NOR flash */ + /* 4.3 display controller */ + #define ECSPI1_CS1 IMX_GPIO_NR(4, 10) #endif
+#define SOFT_RESET_GPIO IMX_GPIO_NR(7, 13) +#define SD2_DRIVER_ENABLE IMX_GPIO_NR(7, 8) + +struct i2c_pads_info i2c_pad_info3 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC, + .gp = IMX_GPIO_NR(1, 5) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, + .gp = IMX_GPIO_NR(1, 6) + } +}; + +struct i2c_pads_info i2c_pad_info4 = { + .scl = { + .i2c_mode = MX6_PAD_GPIO_7__I2C4_SCL | PC, + .gpio_mode = MX6_PAD_GPIO_7__GPIO1_IO07 | PC, + .gp = IMX_GPIO_NR(1, 7) + }, + .sda = { + .i2c_mode = MX6_PAD_GPIO_8__I2C4_SDA | PC, + .gpio_mode = MX6_PAD_GPIO_8__GPIO1_IO08 | PC, + .gp = IMX_GPIO_NR(1, 8) + } +}; + +iomux_v3_cfg_t const uart1_pads[] = { + MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D19__UART1_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D20__UART1_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart2_pads[] = { + MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart3_pads[] = { + MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const uart4_pads[] = { + MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), + MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), +}; + +iomux_v3_cfg_t const gpio_pads[] = { + /* LED enable*/ + MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LED yellow */ + MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LED red */ +#if (CONFIG_SYS_BOARD_VERSION == 2) + MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), +#elif (CONFIG_SYS_BOARD_VERSION == 3) + MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), +#endif + /* LED green */ + MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LED blue */ + MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* spi flash WP protect */ + MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* spi CS 0 */ + MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* spi bus #2 SS driver enable */ + MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* RST_LOC# PHY reset input (has pull-down!)*/ + MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* SD 2 level shifter output enable */ + MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* SD1 card detect input */ + MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* SD1 write protect input */ + MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* SD2 card detect input */ + MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* SD2 write protect input */ + MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* Touchscreen IRQ */ + MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const misc_pads[] = { + /* USB_OTG_ID = GPIO1_24*/ + MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), + /* H1 Power enable = GPIO1_0*/ + MX6_PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), + /* OTG Power enable = GPIO4_15*/ + MX6_PAD_KEY_ROW4__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +iomux_v3_cfg_t const enet_pads[] = { + MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), + MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), +}; + +static iomux_v3_cfg_t const backlight_pads[] = { + /* backlight PWM brightness control */ + MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), + /* backlight enable */ + MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), + /* LCD power enable */ + MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; + +static iomux_v3_cfg_t const ecspi1_pads[] = { + MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), +#if (CONFIG_SYS_BOARD_VERSION == 2) + MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(SPI_PAD_CTRL), +#elif (CONFIG_SYS_BOARD_VERSION == 3) + MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL), + MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), +#endif +}; + +static void setup_iomux_enet(void) +{ + imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); +} + +#if (CONFIG_SYS_BOARD_VERSION == 2) +iomux_v3_cfg_t const ecspi4_pads[] = { + MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), + MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), +}; +#endif + +static iomux_v3_cfg_t const display_pads[] = { + MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL), + MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, + MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, + MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, + MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, + MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, + MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, + MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, + MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, + MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, + MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, + MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, + MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, + MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, + MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, + MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, + MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, + MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, + MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, + MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, + MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, + MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, + MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, + MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, + MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, + MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, + MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, + MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, +}; + +int board_spi_cs_gpio(unsigned int bus, unsigned int cs) +{ + if (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS) +#if (CONFIG_SYS_BOARD_VERSION == 2) + return IMX_GPIO_NR(5, 2); + + if (bus == 0 && cs == 0) + return IMX_GPIO_NR(4, 9); +#elif (CONFIG_SYS_BOARD_VERSION == 3) + return ECSPI1_CS0; + + if (bus == 0 && cs == 1) + return ECSPI1_CS1; +#endif + return -1; +} + +static void setup_spi(void) +{ + int i; + + imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); + +#if (CONFIG_SYS_BOARD_VERSION == 2) + imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads)); +#endif + + for (i = 0; i < 4; i++) + enable_spi_clk(true, i); + + gpio_direction_output(ECSPI1_CS0, 1); +#if (CONFIG_SYS_BOARD_VERSION == 2) + gpio_direction_output(ECSPI4_CS1, 0); + /* set cs0 to high (second device on spi bus #4) */ + gpio_direction_output(ECSPI4_CS0, 1); +#elif (CONFIG_SYS_BOARD_VERSION == 3) + gpio_direction_output(ECSPI1_CS1, 1); +#endif +} + +static void setup_iomux_uart(void) +{ + switch (CONFIG_MXC_UART_BASE) { + case UART1_BASE: + imx_iomux_v3_setup_multiple_pads(uart1_pads, + ARRAY_SIZE(uart1_pads)); + break; + case UART2_BASE: + imx_iomux_v3_setup_multiple_pads(uart2_pads, + ARRAY_SIZE(uart2_pads)); + break; + case UART3_BASE: + imx_iomux_v3_setup_multiple_pads(uart3_pads, + ARRAY_SIZE(uart3_pads)); + break; + case UART4_BASE: + imx_iomux_v3_setup_multiple_pads(uart4_pads, + ARRAY_SIZE(uart4_pads)); + break; + } +} + +int board_phy_config(struct phy_device *phydev) +{ + /* control data pad skew - devaddr = 0x02, register = 0x04 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CTRL_SIG_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* rx data pad skew - devaddr = 0x02, register = 0x05 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_RX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* tx data pad skew - devaddr = 0x02, register = 0x06 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_TX_DATA_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x0000); + /* gtx and rx clock pad skew - devaddr = 0x02, register = 0x08 */ + ksz9031_phy_extended_write(phydev, 0x02, + MII_KSZ9031_EXT_RGMII_CLOCK_SKEW, + MII_KSZ9031_MOD_DATA_NO_POST_INC, 0x03FF); + + if (phydev->drv->config) + phydev->drv->config(phydev); + + return 0; +} + +int board_eth_init(bd_t *bis) +{ + setup_iomux_enet(); + return cpu_eth_init(bis); +} + +static int rotate_logo_one(unsigned char *out, unsigned char *in) +{ + int i, j; + + for (i = 0; i < BMP_LOGO_WIDTH; i++) + for (j = 0; j < BMP_LOGO_HEIGHT; j++) + out[j * BMP_LOGO_WIDTH + BMP_LOGO_HEIGHT - 1 - i] = + in[i * BMP_LOGO_WIDTH + j]; + return 0; +} + +/* + * Rotate the BMP_LOGO (only) + * Will only work, if the logo is square, as + * BMP_LOGO_HEIGHT and BMP_LOGO_WIDTH are defines, not variables + */ +void rotate_logo(int rotations) +{ + unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT]; + unsigned char *in_logo; + int i, j; + + if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT) + return; + + in_logo = bmp_logo_bitmap; + + /* one 90 degree rotation */ + if (rotations == 1 || rotations == 2 || rotations == 3) + rotate_logo_one(out_logo, in_logo); + + /* second 90 degree rotation */ + if (rotations == 2 || rotations == 3) + rotate_logo_one(in_logo, out_logo); + + /* third 90 degree rotation */ + if (rotations == 3) + rotate_logo_one(out_logo, in_logo); + + /* copy result back to original array */ + if (rotations == 1 || rotations == 3) + for (i = 0; i < BMP_LOGO_WIDTH; i++) + for (j = 0; j < BMP_LOGO_HEIGHT; j++) + in_logo[i * BMP_LOGO_WIDTH + j] = + out_logo[i * BMP_LOGO_WIDTH + j]; +} + +static void enable_display_power(void) +{ + imx_iomux_v3_setup_multiple_pads(backlight_pads, + ARRAY_SIZE(backlight_pads)); + + /* backlight enable */ + gpio_direction_output(IMX_GPIO_NR(6, 31), 1); + /* LCD power enable */ + gpio_direction_output(IMX_GPIO_NR(6, 15), 1); + + /* enable backlight PWM 1 */ + if (pwm_init(0, 0, 0)) + goto error; + /* duty cycle 500ns, period: 3000ns */ + if (pwm_config(0, 50000, 300000)) + goto error; + if (pwm_enable(0)) + goto error; + return; + +error: + puts("error init pwm for backlight\n"); +} + +static void enable_lvds(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int reg; + s32 timeout = 100000; + + /* set PLL5 clock */ + reg = readl(&ccm->analog_pll_video); + reg |= BM_ANADIG_PLL_VIDEO_POWERDOWN; + writel(reg, &ccm->analog_pll_video); + + /* set PLL5 to 232720000Hz */ + reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; + reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x26); + reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; + reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0); + writel(reg, &ccm->analog_pll_video); + + writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xC0238), + &ccm->analog_pll_video_num); + writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xF4240), + &ccm->analog_pll_video_denom); + + reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; + writel(reg, &ccm->analog_pll_video); + + while (timeout--) + if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) + break; + if (timeout < 0) + printf("Warning: video pll lock timeout!\n"); + + reg = readl(&ccm->analog_pll_video); + reg |= BM_ANADIG_PLL_VIDEO_ENABLE; + reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; + writel(reg, &ccm->analog_pll_video); + + /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */ + reg = readl(&ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) + | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &ccm->cs2cdr); + + reg = readl(&ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &ccm->cscmr2); + + reg = readl(&ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + writel(reg, &ccm->chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH + | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH + | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT + | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED + | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); + writel(reg, &iomux->gpr[3]); +} + +static void enable_spi_display(struct display_info_t const *dev) +{ + struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; + struct mxc_ccm_reg *ccm = (struct mxc_ccm_reg *)CCM_BASE_ADDR; + int reg; + s32 timeout = 100000; + +#if defined(CONFIG_VIDEO_BMP_LOGO) + rotate_logo(3); /* portrait display in landscape mode */ +#endif + + /* + * set ldb clock to 28341000 Hz calculated through the formula: + * (XRES + LEFT_M + RIGHT_M + HSYNC_LEN) * + * (YRES + UPPER_M + LOWER_M + VSYNC_LEN) * REFRESH) + * see: + * https://community.freescale.com/thread/308170 + */ + ipu_set_ldb_clock(28341000); + + reg = readl(&ccm->cs2cdr); + + /* select pll 5 clock */ + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + writel(reg, &ccm->cs2cdr); + + /* set PLL5 to 197994996Hz */ + reg &= ~BM_ANADIG_PLL_VIDEO_DIV_SELECT; + reg |= BF_ANADIG_PLL_VIDEO_DIV_SELECT(0x21); + reg &= ~BM_ANADIG_PLL_VIDEO_POST_DIV_SELECT; + reg |= BF_ANADIG_PLL_VIDEO_POST_DIV_SELECT(0); + writel(reg, &ccm->analog_pll_video); + + writel(BF_ANADIG_PLL_VIDEO_NUM_A(0xfbf4), + &ccm->analog_pll_video_num); + writel(BF_ANADIG_PLL_VIDEO_DENOM_B(0xf4240), + &ccm->analog_pll_video_denom); + + reg &= ~BM_ANADIG_PLL_VIDEO_POWERDOWN; + writel(reg, &ccm->analog_pll_video); + + while (timeout--) + if (readl(&ccm->analog_pll_video) & BM_ANADIG_PLL_VIDEO_LOCK) + break; + if (timeout < 0) + printf("Warning: video pll lock timeout!\n"); + + reg = readl(&ccm->analog_pll_video); + reg |= BM_ANADIG_PLL_VIDEO_ENABLE; + reg &= ~BM_ANADIG_PLL_VIDEO_BYPASS; + writel(reg, &ccm->analog_pll_video); + + /* set LDB0, LDB1 clk select to 000/000 (PLL5 clock) */ + reg = readl(&ccm->cs2cdr); + reg &= ~(MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_MASK + | MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_MASK); + reg |= (0 << MXC_CCM_CS2CDR_LDB_DI0_CLK_SEL_OFFSET) + | (0 << MXC_CCM_CS2CDR_LDB_DI1_CLK_SEL_OFFSET); + writel(reg, &ccm->cs2cdr); + + reg = readl(&ccm->cscmr2); + reg |= MXC_CCM_CSCMR2_LDB_DI0_IPU_DIV; + writel(reg, &ccm->cscmr2); + + reg = readl(&ccm->chsccdr); + reg |= (CHSCCDR_CLK_SEL_LDB_DI0 + << MXC_CCM_CHSCCDR_IPU1_DI0_CLK_SEL_OFFSET); + reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PODF_MASK; + reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PODF_OFFSET); + reg &= ~MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_MASK; + reg |= (2 << MXC_CCM_CHSCCDR_IPU1_DI0_PRE_CLK_SEL_OFFSET); + writel(reg, &ccm->chsccdr); + + reg = IOMUXC_GPR2_BGREF_RRMODE_EXTERNAL_RES + | IOMUXC_GPR2_DI1_VS_POLARITY_ACTIVE_HIGH + | IOMUXC_GPR2_DI0_VS_POLARITY_ACTIVE_HIGH + | IOMUXC_GPR2_BIT_MAPPING_CH0_SPWG + | IOMUXC_GPR2_DATA_WIDTH_CH0_24BIT + | IOMUXC_GPR2_LVDS_CH1_MODE_DISABLED + | IOMUXC_GPR2_LVDS_CH0_MODE_ENABLED_DI0; + writel(reg, &iomux->gpr[2]); + + reg = readl(&iomux->gpr[3]); + reg = (reg & ~IOMUXC_GPR3_LVDS0_MUX_CTL_MASK) + | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 + << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); + writel(reg, &iomux->gpr[3]); + + imx_iomux_v3_setup_multiple_pads(display_pads, + ARRAY_SIZE(display_pads)); +} + +static void setup_display(void) +{ + enable_ipu_clock(); + enable_display_power(); +} + +static void setup_iomux_gpio(void) +{ + imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); +} + +static void set_gpr_register(void) +{ + struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; + + writel(IOMUXC_GPR1_APP_CLK_REQ_N | IOMUXC_GPR1_PCIE_RDY_L23 | + IOMUXC_GPR1_EXC_MON_SLVE | + (2 << IOMUXC_GPR1_ADDRS0_OFFSET) | + IOMUXC_GPR1_ACT_CS0, + &iomuxc_regs->gpr[1]); + writel(0x0, &iomuxc_regs->gpr[8]); + writel(IOMUXC_GPR12_ARMP_IPG_CLK_EN | IOMUXC_GPR12_ARMP_AHB_CLK_EN | + IOMUXC_GPR12_ARMP_ATB_CLK_EN | IOMUXC_GPR12_ARMP_APB_CLK_EN, + &iomuxc_regs->gpr[12]); +} + +int board_early_init_f(void) +{ + setup_iomux_uart(); + setup_iomux_gpio(); + + gpio_direction_output(SOFT_RESET_GPIO, 1); + gpio_direction_output(SD2_DRIVER_ENABLE, 1); + setup_display(); + set_gpr_register(); + return 0; +} + +static void setup_i2c4(void) +{ + setup_i2c(3, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, + &i2c_pad_info4); +} + +static void setup_board_gpio(void) +{ + /* enable all LEDs */ + gpio_request(IMX_GPIO_NR(2, 13), "LED ena"); /* 25 */ + gpio_direction_output(IMX_GPIO_NR(1, 25), 0); + + /* switch off Status LEDs */ +#if (CONFIG_SYS_BOARD_VERSION == 2) + gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */ + gpio_direction_output(IMX_GPIO_NR(6, 16), 1); + gpio_request(IMX_GPIO_NR(2, 28), "LED red"); /* 60 */ + gpio_direction_output(IMX_GPIO_NR(2, 28), 1); + gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */ + gpio_direction_output(IMX_GPIO_NR(5, 4), 1); + gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */ + gpio_direction_output(IMX_GPIO_NR(2, 29), 1); +#elif (CONFIG_SYS_BOARD_VERSION == 3) + gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */ + gpio_direction_output(IMX_GPIO_NR(6, 16), 0); + gpio_request(IMX_GPIO_NR(5, 0), "LED red"); /* 128 */ + gpio_direction_output(IMX_GPIO_NR(5, 0), 0); + gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */ + gpio_direction_output(IMX_GPIO_NR(5, 4), 0); + gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */ + gpio_direction_output(IMX_GPIO_NR(2, 29), 0); +#endif +} + +static void setup_board_spi(void) +{ + /* enable spi bus #2 SS drivers (and spi bus #4 SS1 for rev2b) */ + gpio_direction_output(IMX_GPIO_NR(6, 6), 1); +} + +int board_late_init(void) +{ + char *my_bootdelay; + char bootmode = 0; + char const *panel = env_get("panel"); + + /* + * Check the boot-source. If booting from NOR Flash, + * disable bootdelay + */ + gpio_request(IMX_GPIO_NR(7, 6), "bootsel0"); + gpio_direction_input(IMX_GPIO_NR(7, 6)); + gpio_request(IMX_GPIO_NR(7, 7), "bootsel1"); + gpio_direction_input(IMX_GPIO_NR(7, 7)); + gpio_request(IMX_GPIO_NR(7, 1), "bootsel2"); + gpio_direction_input(IMX_GPIO_NR(7, 1)); + bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 6)) ? 1 : 0) << 0; + bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 7)) ? 1 : 0) << 1; + bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 1)) ? 1 : 0) << 2; + + if (bootmode == 7) { + my_bootdelay = env_get("nor_bootdelay"); + if (my_bootdelay != NULL) + env_set("bootdelay", my_bootdelay); + else + env_set("bootdelay", "-2"); + } + + /* if we have the lg panel, we can initialze it now */ + if (panel) + if (!strcmp(panel, displays[1].mode.name)) + lg4573_spi_startup(CONFIG_LG4573_BUS, + CONFIG_LG4573_CS, + 10000000, SPI_MODE_0); + + return 0; +}
struct i2c_pads_info i2c_pad_info1 = { .scl = { diff --git a/include/configs/aristainetos-common.h b/include/configs/aristainetos-common.h deleted file mode 100644 index 9a6c205c72..0000000000 --- a/include/configs/aristainetos-common.h +++ /dev/null @@ -1,186 +0,0 @@ -/* SPDX-License-Identifier: GPL-2.0+ */ -/* - * (C) Copyright 2015 - * (C) Copyright 2014 - * Heiko Schocher, DENX Software Engineering, hs@denx.de. - * - * Based on: - * Copyright (C) 2012 Freescale Semiconductor, Inc. - * - * Configuration settings for the Freescale i.MX6Q SabreSD board. - */ -#ifndef __ARISTAINETOS_COMMON_CONFIG_H -#define __ARISTAINETOS_COMMON_CONFIG_H - -#include "mx6_common.h" - -#define CONFIG_MACH_TYPE 4501 -#define CONFIG_MMCROOT "/dev/mmcblk0p1" - -/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 - -#define IMX_FEC_BASE ENET_BASE_ADDR -#define CONFIG_ETHPRIME "FEC" -#define CONFIG_FEC_MXC_PHYADDR 0 - -#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN - -#define CONFIG_EXTRA_ENV_SETTINGS \ - "disable_giga=yes\0" \ - "script=u-boot.scr\0" \ - "fit_file=/boot/system.itb\0" \ - "loadaddr=0x12000000\0" \ - "fit_addr_r=0x14000000\0" \ - "uboot=/boot/u-boot.imx\0" \ - "uboot_sz=d0000\0" \ - "rescue_sys_addr=f0000\0" \ - "rescue_sys_length=f10000\0" \ - "panel=lb07wv8\0" \ - "splashpos=m,m\0" \ - "console=" CONSOLE_DEV "\0" \ - "fdt_high=0xffffffff\0" \ - "initrd_high=0xffffffff\0" \ - "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "set_fit_default=fdt addr ${fit_addr_r};fdt set /configurations " \ - "default ${board_type}\0" \ - "get_env=mw ${loadaddr} 0 0x20000;" \ - "mmc rescan;" \ - "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \ - "env import -t ${loadaddr}\0" \ - "default_env=mw ${loadaddr} 0 0x20000;" \ - "env export -t ${loadaddr} serial# ethaddr eth1addr " \ - "board_type panel;" \ - "env default -a;" \ - "env import -t ${loadaddr}\0" \ - "loadbootscript=" \ - "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ - "bootscript=echo Running bootscript from mmc ...; " \ - "source\0" \ - "mmcpart=1\0" \ - "mmcdev=0\0" \ - "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ - "mmcargs=setenv bootargs console=${console},${baudrate} " \ - "root=${mmcroot}\0" \ - "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs addmtd addmisc set_fit_default;" \ - "bootm ${fit_addr_r}\0" \ - "mmc_load_fit=ext2load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ - "${fit_file}\0" \ - "mmc_load_uboot=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ - "${uboot}\0" \ - "mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \ - "setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \ - "setexpr uboot_maxsize ${uboot_sz} - 400;" \ - "mw.b ${cmp_buf} 0x00 ${uboot_sz};" \ - "run mmc_load_uboot;sf probe;sf erase 0 ${uboot_sz};" \ - "sf write ${loadaddr} 400 ${filesize};" \ - "sf read ${cmp_buf} 400 ${uboot_sz};" \ - "cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \ - "ubiboot=echo Booting from ubi ...; " \ - "run ubiargs addmtd addmisc set_fit_default;" \ - "bootm ${fit_addr_r}\0" \ - "rescueargs=setenv bootargs console=${console},${baudrate} " \ - "root=/dev/ram rw\0 " \ - "rescueboot=echo Booting rescue system from NOR ...; " \ - "run rescueargs addmtd addmisc set_fit_default;" \ - "bootm ${fit_addr_r}\0" \ - "rescue_load_fit=sf probe;sf read ${fit_addr_r} ${rescue_sys_addr} " \ - "${rescue_sys_length}; imi ${fit_addr_r}\0" \ - CONFIG_EXTRA_ENV_BOARD_SETTINGS - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ - "else " \ - "if run mmc_load_fit; then " \ - "run mmcboot; " \ - "else " \ - "if run ubifs_load_fit; then " \ - "run ubiboot; " \ - "else " \ - "if run rescue_load_fit; then " \ - "run rescueboot; " \ - "else " \ - "echo RESCUE SYSTEM BOOT " \ - "FAILURE;" \ - "fi; " \ - "fi; " \ - "fi; " \ - "fi; " \ - "else " \ - "if run ubifs_load_fit; then " \ - "run ubiboot; " \ - "else " \ - "if run rescue_load_fit; then " \ - "run rescueboot; " \ - "else " \ - "echo RESCUE SYSTEM BOOT FAILURE;" \ - "fi; " \ - "fi; " \ - "fi" - -#define CONFIG_ARP_TIMEOUT 200UL - -#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM -#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) -#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 - -/* Physical Memory Map */ -#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR - -#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM -#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR -#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE - -#define CONFIG_SYS_INIT_SP_OFFSET \ - (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) -#define CONFIG_SYS_INIT_SP_ADDR \ - (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) - -/* Environment organization */ - -#define CONFIG_SYS_FSL_USDHC_NUM 2 - -/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0x7f -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} } - -/* NAND stuff */ -#define CONFIG_SYS_MAX_NAND_DEVICE 1 -#define CONFIG_SYS_NAND_BASE 0x40000000 -#define CONFIG_SYS_NAND_5_ADDR_CYCLE -#define CONFIG_SYS_NAND_ONFI_DETECTION - -/* DMA stuff, needed for GPMI/MXS NAND support */ - -/* RTC */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_RTC_BUS_NUM 2 -#define CONFIG_RTC_M41T11 - -/* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 -#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ -#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) -#define CONFIG_MXC_USB_FLAGS 0 - -/* UBI support */ - -/* Framebuffer */ -/* check this console not needed, after test remove it */ -#define CONFIG_VIDEO_BMP_RLE8 -#define CONFIG_SPLASH_SCREEN -#define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP -#define CONFIG_VIDEO_LOGO -#define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_IMX_VIDEO_SKIP - -#define CONFIG_IMX6_PWM_PER_CLK 66000000 - -#endif /* __ARISTAINETOS_COMMON_CONFIG_H */ diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 01998f0295..9291cfdffd 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -39,6 +39,174 @@ #define CONFIG_SYS_LDB_CLOCK 33246000 #define CONFIG_LG4573
-#include "aristainetos-common.h" +#include "mx6_common.h" + +#define CONFIG_MACH_TYPE 4501 +#define CONFIG_MMCROOT "/dev/mmcblk0p1" + +/* MMC Configs */ +#define CONFIG_SYS_FSL_ESDHC_ADDR 0 + +#define IMX_FEC_BASE ENET_BASE_ADDR +#define CONFIG_ETHPRIME "FEC" +#define CONFIG_FEC_MXC_PHYADDR 0 + +#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "disable_giga=yes\0" \ + "script=u-boot.scr\0" \ + "fit_file=/boot/system.itb\0" \ + "loadaddr=0x12000000\0" \ + "fit_addr_r=0x14000000\0" \ + "uboot=/boot/u-boot.imx\0" \ + "uboot_sz=d0000\0" \ + "rescue_sys_addr=f0000\0" \ + "rescue_sys_length=f10000\0" \ + "panel=lb07wv8\0" \ + "splashpos=m,m\0" \ + "console=" CONSOLE_DEV "\0" \ + "fdt_high=0xffffffff\0" \ + "initrd_high=0xffffffff\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "set_fit_default=fdt addr ${fit_addr_r};fdt set /configurations " \ + "default ${board_type}\0" \ + "get_env=mw ${loadaddr} 0 0x20000;" \ + "mmc rescan;" \ + "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \ + "env import -t ${loadaddr}\0" \ + "default_env=mw ${loadaddr} 0 0x20000;" \ + "env export -t ${loadaddr} serial# ethaddr eth1addr " \ + "board_type panel;" \ + "env default -a;" \ + "env import -t ${loadaddr}\0" \ + "loadbootscript=" \ + "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "bootscript=echo Running bootscript from mmc ...; " \ + "source\0" \ + "mmcpart=1\0" \ + "mmcdev=0\0" \ + "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ + "mmcargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "mmcboot=echo Booting from mmc ...; " \ + "run mmcargs addmtd addmisc set_fit_default;" \ + "bootm ${fit_addr_r}\0" \ + "mmc_load_fit=ext2load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ + "${fit_file}\0" \ + "mmc_load_uboot=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${uboot}\0" \ + "mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \ + "setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \ + "setexpr uboot_maxsize ${uboot_sz} - 400;" \ + "mw.b ${cmp_buf} 0x00 ${uboot_sz};" \ + "run mmc_load_uboot;sf probe;sf erase 0 ${uboot_sz};" \ + "sf write ${loadaddr} 400 ${filesize};" \ + "sf read ${cmp_buf} 400 ${uboot_sz};" \ + "cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \ + "ubiboot=echo Booting from ubi ...; " \ + "run ubiargs addmtd addmisc set_fit_default;" \ + "bootm ${fit_addr_r}\0" \ + "rescueargs=setenv bootargs console=${console},${baudrate} " \ + "root=/dev/ram rw\0 " \ + "rescueboot=echo Booting rescue system from NOR ...; " \ + "run rescueargs addmtd addmisc set_fit_default;" \ + "bootm ${fit_addr_r}\0" \ + "rescue_load_fit=sf probe;sf read ${fit_addr_r} ${rescue_sys_addr} " \ + "${rescue_sys_length}; imi ${fit_addr_r}\0" \ + CONFIG_EXTRA_ENV_BOARD_SETTINGS + +#define CONFIG_BOOTCOMMAND \ + "mmc dev ${mmcdev};" \ + "if mmc rescan; then " \ + "if run loadbootscript; then " \ + "run bootscript; " \ + "else " \ + "if run mmc_load_fit; then " \ + "run mmcboot; " \ + "else " \ + "if run ubifs_load_fit; then " \ + "run ubiboot; " \ + "else " \ + "if run rescue_load_fit; then " \ + "run rescueboot; " \ + "else " \ + "echo RESCUE SYSTEM BOOT " \ + "FAILURE;" \ + "fi; " \ + "fi; " \ + "fi; " \ + "fi; " \ + "else " \ + "if run ubifs_load_fit; then " \ + "run ubiboot; " \ + "else " \ + "if run rescue_load_fit; then " \ + "run rescueboot; " \ + "else " \ + "echo RESCUE SYSTEM BOOT FAILURE;" \ + "fi; " \ + "fi; " \ + "fi" + +#define CONFIG_ARP_TIMEOUT 200UL + +#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM +#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000) +#define CONFIG_SYS_MEMTEST_SCRATCH 0x10800000 + +/* Physical Memory Map */ +#define PHYS_SDRAM MMDC0_ARB_BASE_ADDR + +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM +#define CONFIG_SYS_INIT_RAM_ADDR IRAM_BASE_ADDR +#define CONFIG_SYS_INIT_RAM_SIZE IRAM_SIZE + +#define CONFIG_SYS_INIT_SP_OFFSET \ + (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) +#define CONFIG_SYS_INIT_SP_ADDR \ + (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) + +#define CONFIG_SYS_FSL_USDHC_NUM 2 + +/* I2C */ +#define CONFIG_SYS_I2C +#define CONFIG_SYS_I2C_SPEED 100000 +#define CONFIG_SYS_I2C_SLAVE 0x7f +#define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} } + +/* NAND stuff */ +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define CONFIG_SYS_NAND_BASE 0x40000000 +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_ONFI_DETECTION + +/* DMA stuff, needed for GPMI/MXS NAND support */ + +/* RTC */ +#define CONFIG_SYS_I2C_RTC_ADDR 0x68 +#define CONFIG_SYS_RTC_BUS_NUM 2 +#define CONFIG_RTC_M41T11 + +/* USB Configs */ +#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 +#define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ +#define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) +#define CONFIG_MXC_USB_FLAGS 0 + +/* UBI support */ + +/* Framebuffer */ +/* check this console not needed, after test remove it */ +#define CONFIG_VIDEO_BMP_RLE8 +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_LOGO +#define CONFIG_VIDEO_BMP_LOGO +#define CONFIG_IMX_VIDEO_SKIP + +#define CONFIG_IMX6_PWM_PER_CLK 66000000 +
#endif /* __ARISTAINETOS2_CONFIG_H */
remove aristainetos-v2.c file, as we now want to switch to DM/DTS support and have all board specific code in one file. Goal is to setup differences through DT. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
as we switch to support DM and DTS, rework the existing DTS trees. Change also Linux specific Device trees, goal is to push this changes to linux.
Collect U-Boot specific changes in separate "*u-boot*" dts files.
Signed-off-by: Heiko Schocher hs@denx.de ---
.../dts/imx6dl-aristainetos2_4-u-boot.dtsi | 13 + arch/arm/dts/imx6dl-aristainetos2_4.dts | 79 +-- arch/arm/dts/imx6dl-aristainetos2_4.dtsi | 84 +++ .../dts/imx6dl-aristainetos2_7-u-boot.dtsi | 19 + arch/arm/dts/imx6dl-aristainetos2_7.dts | 50 +- arch/arm/dts/imx6dl-aristainetos2_7.dtsi | 58 +++ .../arm/dts/imx6qdl-aristainetos2-common.dtsi | 492 ++++++++++++++++++ .../arm/dts/imx6qdl-aristainetos2-u-boot.dtsi | 101 ++++ arch/arm/dts/imx6qdl-aristainetos2.dtsi | 487 +++-------------- board/aristainetos/MAINTAINERS | 10 +- board/aristainetos/aristainetos.c | 68 +++ configs/aristainetos2_defconfig | 7 + 12 files changed, 914 insertions(+), 554 deletions(-) create mode 100644 arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2_4.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2_7.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2-common.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi
diff --git a/arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi new file mode 100644 index 0000000000..ac7052c7b7 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Heiko Schocher hs@denx.de + */ + +#include <imx6qdl-aristainetos2-u-boot.dtsi> + +&lcd_panel { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp>; + enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_4.dts b/arch/arm/dts/imx6dl-aristainetos2_4.dts index 0e28a70e78..0157e244ae 100644 --- a/arch/arm/dts/imx6dl-aristainetos2_4.dts +++ b/arch/arm/dts/imx6dl-aristainetos2_4.dts @@ -1,46 +1,21 @@ // SPDX-License-Identifier: (GPL-2.0) /* * support for the imx6 based aristainetos2 board + * parts for 4.3 inch LG display on spi1 port0 * * Copyright (C) 2019 Heiko Schocher hs@denx.de * Copyright (C) 2015 Heiko Schocher hs@denx.de * */ /dts-v1/; -#include "imx6dl.dtsi" + +#include "imx6dl-aristainetos2_4.dtsi" #include "imx6qdl-aristainetos2.dtsi"
/ { model = "aristainetos2 i.MX6 Dual Lite Board 4"; compatible = "fsl,imx6dl";
- memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - display0: disp0 { - #address-cells = <1>; - #size-cells = <0>; - compatible = "fsl,imx-parallel-display"; - interface-pix-fmt = "rgb24"; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ipu_disp>; - - port@0 { - reg = <0>; - display0_in: endpoint { - remote-endpoint = <&ipu1_di0_disp0>; - }; - }; - - port@1 { - reg = <1>; - display_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; };
&ecspi1 { @@ -74,51 +49,3 @@ }; }; }; - -&i2c3 { - touch: touch@4b { - compatible = "atmel,maxtouch"; - reg = <0x4b>; - interrupt-parent = <&gpio2>; - interrupts = <9 8>; - }; -}; - -&ipu1_di0_disp0 { - remote-endpoint = <&display0_in>; -}; - -&iomuxc { - pinctrl_ipu_disp: ipudisp1grp { - fsl,pins = < - MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x31 - MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xE1 - MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 - MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 - MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xE1 - MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xE1 - MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xE1 - MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xE1 - MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xE1 - MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xE1 - MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xE1 - MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xE1 - MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xE1 - MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xE1 - MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xE1 - MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xE1 - MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xE1 - MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xE1 - MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xe1 - MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xE1 - MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xE1 - MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xE1 - MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xE1 - MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xE1 - MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xE1 - MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xE1 - MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xE1 - MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xE1 - >; - }; -}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_4.dtsi b/arch/arm/dts/imx6dl-aristainetos2_4.dtsi new file mode 100644 index 0000000000..be4601b4b2 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2_4.dtsi @@ -0,0 +1,84 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2 board + * parts for 4.3 inch LG display on the parallel port and atmel maxtouch + * + * Copyright (C) 2019 Heiko Schocher hs@denx.de + * Copyright (C) 2015 Heiko Schocher hs@denx.de + * + */ +/dts-v1/; +#include "imx6dl.dtsi" + +/ { + display0: disp0 { + #address-cells = <1>; + #size-cells = <0>; + compatible = "fsl,imx-parallel-display"; + interface-pix-fmt = "rgb24"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp>; + + port@0 { + reg = <0>; + display0_in: endpoint { + remote-endpoint = <&ipu1_di0_disp0>; + }; + }; + + port@1 { + reg = <1>; + display_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; + +&i2c3 { + touch: touch@4b { + compatible = "atmel,maxtouch"; + reg = <0x4b>; + interrupt-parent = <&gpio2>; + interrupts = <9 8>; + }; +}; + +&ipu1_di0_disp0 { + remote-endpoint = <&display0_in>; +}; + +&iomuxc { + pinctrl_ipu_disp: ipudisp1grp { + fsl,pins = < + MX6QDL_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK 0x31 + MX6QDL_PAD_DI0_PIN15__IPU1_DI0_PIN15 0xE1 + MX6QDL_PAD_DI0_PIN2__IPU1_DI0_PIN02 0x10 + MX6QDL_PAD_DI0_PIN3__IPU1_DI0_PIN03 0x10 + MX6QDL_PAD_DISP0_DAT0__IPU1_DISP0_DATA00 0xE1 + MX6QDL_PAD_DISP0_DAT1__IPU1_DISP0_DATA01 0xE1 + MX6QDL_PAD_DISP0_DAT2__IPU1_DISP0_DATA02 0xE1 + MX6QDL_PAD_DISP0_DAT3__IPU1_DISP0_DATA03 0xE1 + MX6QDL_PAD_DISP0_DAT4__IPU1_DISP0_DATA04 0xE1 + MX6QDL_PAD_DISP0_DAT5__IPU1_DISP0_DATA05 0xE1 + MX6QDL_PAD_DISP0_DAT6__IPU1_DISP0_DATA06 0xE1 + MX6QDL_PAD_DISP0_DAT7__IPU1_DISP0_DATA07 0xE1 + MX6QDL_PAD_DISP0_DAT8__IPU1_DISP0_DATA08 0xE1 + MX6QDL_PAD_DISP0_DAT9__IPU1_DISP0_DATA09 0xE1 + MX6QDL_PAD_DISP0_DAT10__IPU1_DISP0_DATA10 0xE1 + MX6QDL_PAD_DISP0_DAT11__IPU1_DISP0_DATA11 0xE1 + MX6QDL_PAD_DISP0_DAT12__IPU1_DISP0_DATA12 0xE1 + MX6QDL_PAD_DISP0_DAT13__IPU1_DISP0_DATA13 0xE1 + MX6QDL_PAD_DISP0_DAT14__IPU1_DISP0_DATA14 0xe1 + MX6QDL_PAD_DISP0_DAT15__IPU1_DISP0_DATA15 0xE1 + MX6QDL_PAD_DISP0_DAT16__IPU1_DISP0_DATA16 0xE1 + MX6QDL_PAD_DISP0_DAT17__IPU1_DISP0_DATA17 0xE1 + MX6QDL_PAD_DISP0_DAT18__IPU1_DISP0_DATA18 0xE1 + MX6QDL_PAD_DISP0_DAT19__IPU1_DISP0_DATA19 0xE1 + MX6QDL_PAD_DISP0_DAT20__IPU1_DISP0_DATA20 0xE1 + MX6QDL_PAD_DISP0_DAT21__IPU1_DISP0_DATA21 0xE1 + MX6QDL_PAD_DISP0_DAT22__IPU1_DISP0_DATA22 0xE1 + MX6QDL_PAD_DISP0_DAT23__IPU1_DISP0_DATA23 0xE1 + >; + }; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi new file mode 100644 index 0000000000..25bc562064 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Heiko Schocher hs@denx.de + */ + +#include <imx6qdl-aristainetos2-u-boot.dtsi> +/ { + vdd_panel_reg: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "panel_regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&panel0 { + power-supply = <&vdd_panel_reg>; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2_7.dts b/arch/arm/dts/imx6dl-aristainetos2_7.dts index 320dbcffaf..0d1e83cb68 100644 --- a/arch/arm/dts/imx6dl-aristainetos2_7.dts +++ b/arch/arm/dts/imx6dl-aristainetos2_7.dts @@ -7,58 +7,10 @@ * */ /dts-v1/; -#include "imx6dl.dtsi" +#include "imx6dl-aristainetos2_7.dtsi" #include "imx6qdl-aristainetos2.dtsi"
/ { model = "aristainetos2 i.MX6 Dual Lite Board 7"; compatible = "fsl,imx6dl"; - - memory@10000000 { - device_type = "memory"; - reg = <0x10000000 0x40000000>; - }; - - panel: panel { - compatible = "lg,lb070wv8"; - backlight = <&backlight>; - enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; - - port { - panel_in: endpoint { - remote-endpoint = <&lvds0_out>; - }; - }; - }; -}; - -&i2c3 { - touch: touch@4d { - compatible = "atmel,maxtouch"; - reg = <0x4d>; - interrupt-parent = <&gpio2>; - interrupts = <9 8>; - }; -}; - -&ldb { - status = "okay"; - - lvds-channel@0 { - status = "okay"; - - port@0 { - reg = <0>; - lvds0_in: endpoint { - remote-endpoint = <&ipu1_di0_lvds0>; - }; - }; - - port@4 { - reg = <4>; - lvds0_out: endpoint { - remote-endpoint = <&panel_in>; - }; - }; - }; }; diff --git a/arch/arm/dts/imx6dl-aristainetos2_7.dtsi b/arch/arm/dts/imx6dl-aristainetos2_7.dtsi new file mode 100644 index 0000000000..52d6a517a7 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2_7.dtsi @@ -0,0 +1,58 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2 board + * parts for 7 inch LG display connected to the LVDS port and atmel maxtouch + * + * Copyright (C) 2019 Heiko Schocher hs@denx.de + * Copyright (C) 2015 Heiko Schocher hs@denx.de + * + */ +/dts-v1/; +#include <dt-bindings/gpio/gpio.h> + +#include "imx6dl.dtsi" + +/ { + panel0: panel_lg { + compatible = "lg,lb070wv8"; + backlight = <&backlight>; + enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + + port { + panel_in: endpoint { + remote-endpoint = <&lvds0_out>; + }; + }; + }; +}; + +&i2c3 { + touch: touch@4d { + compatible = "atmel,maxtouch"; + reg = <0x4d>; + interrupt-parent = <&gpio2>; + interrupts = <9 8>; + }; +}; + +&ldb { + status = "okay"; + + lvds-channel@0 { + status = "okay"; + + port@0 { + reg = <0>; + lvds0_in: endpoint { + remote-endpoint = <&ipu1_di0_lvds0>; + }; + }; + + port@4 { + reg = <4>; + lvds0_out: endpoint { + remote-endpoint = <&panel_in>; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi b/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi new file mode 100644 index 0000000000..2aa531b1ab --- /dev/null +++ b/arch/arm/dts/imx6qdl-aristainetos2-common.dtsi @@ -0,0 +1,492 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2 board + * parts common to all versions + * + * Copyright (C) 2019 Heiko Schocher hs@denx.de + * Copyright (C) 2015 Heiko Schocher hs@denx.de + * + */ +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/imx6qdl-clock.h> + +/ { + aliases { + eeprom0 = &i2c_eeprom0; + pmic0 = &i2c_pmic0; + }; + + memory@10000000 { + device_type = "memory"; + reg = <0x10000000 0x40000000>; + }; + + backlight: backlight { + compatible = "pwm-backlight"; + pwms = <&pwm1 0 5000000>; + brightness-levels = <0 4 8 16 32 64 128 255>; + default-brightness-level = <7>; + enable-gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; + }; + + reg_2p5v: regulator-2p5v { + compatible = "regulator-fixed"; + regulator-name = "2P5V"; + regulator-min-microvolt = <2500000>; + regulator-max-microvolt = <2500000>; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "3P3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; + + reg_usbh1_vbus: regulator-usbh1-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_aristainetos2_usbh1_vbus>; + regulator-name = "usb_h1_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; + + reg_usbotg_vbus: regulator-usbotg-vbus { + compatible = "regulator-fixed"; + enable-active-high; + gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_aristainetos2_usbotg_vbus>; + regulator-name = "usb_otg_vbus"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + }; +}; + +&audmux { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_audmux>; + status = "okay"; +}; + +&ecspi2 { + cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH &gpio2 27 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi2>; + status = "okay"; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c1>; + status = "okay"; + + i2c_pmic0: pmic@58 { + compatible = "dlg,da9063"; + /* the pmic uses addr 0x58 and 0x59 */ + reg = <0x58>; + interrupt-parent = <&gpio1>; + interrupts = <04 0x8>; + + regulators { + bcore1 { + regulator-name = "bcore1"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + bcore2 { + regulator-name = "bcore2"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + bpro { + regulator-name = "bpro"; + regulator-always-on = <1>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + bprob { + regulator-name = "bprob"; + regulator-always-on = <1>; + regulator-min-microvolt = <1200000>; + regulator-max-microvolt = <1200000>; + }; + + bperi { + regulator-name = "bperi"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + bmem { + regulator-name = "bmem"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo2 { + regulator-name = "ldo2"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <1800000>; + }; + + ldo3 { + regulator-name = "ldo3"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo4 { + regulator-name = "ldo4"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo5 { + regulator-name = "ldo5"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo6 { + regulator-name = "ldo6"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo7 { + regulator-name = "ldo7"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo8 { + regulator-name = "ldo8"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo9 { + regulator-name = "ldo9"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo10 { + regulator-name = "ldo10"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + ldo11 { + regulator-name = "ldo11"; + regulator-always-on = <1>; + regulator-min-microvolt = <300000>; + regulator-max-microvolt = <3300000>; + }; + + bio { + regulator-name = "bio"; + regulator-always-on = <1>; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + }; + }; + }; + + tmp103: tmp103@71 { + compatible = "ti,tmp103"; + reg = <0x71>; + }; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c2>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c3>; + status = "okay"; + + expander: tca6416@20 { + compatible = "ti,tca6416"; + reg = <0x20>; + #gpio-cells = <2>; + gpio-controller; + + env_reset { + gpio-hog; + input; + gpios = <6 GPIO_ACTIVE_LOW>; + }; + boot_rescue { + gpio-hog; + input; + gpios = <7 GPIO_ACTIVE_LOW>; + }; + }; + + rtc@68 { + compatible = "st,m41t11"; + reg = <0x68>; + }; +}; + +&i2c4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_i2c4>; + status = "okay"; + + i2c_eeprom0: eeprom@50{ + compatible = "atmel,24c64"; + reg = <0x50>; + pagesize = <32>; + }; + + i2c_eeprom1: eeprom@57{ + compatible = "atmel,24c64"; + reg = <0x57>; + pagesize = <32>; + }; +}; + +&gpio6 { + spi_bus_ena { + gpio-hog; + output-high; + gpios = <6 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio7 { + bootsel0 { + gpio-hog; + input; + gpios = <6 GPIO_ACTIVE_HIGH>; + }; + bootsel1 { + gpio-hog; + input; + gpios = <7 GPIO_ACTIVE_HIGH>; + }; + bootsel2 { + gpio-hog; + input; + gpios = <1 GPIO_ACTIVE_HIGH>; + }; + + soft_reset { + gpio-hog; + output-high; + gpios = <13 GPIO_ACTIVE_HIGH>; + }; +}; + +&fec { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_enet>; + phy-mode = "rgmii"; + txd0-skew-ps = <0>; + txd1-skew-ps = <0>; + txd2-skew-ps = <0>; + txd3-skew-ps = <0>; + status = "okay"; +}; + +&pcie { + reset-gpio = <&gpio2 16 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&pwm1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_pwm1>; + status = "okay"; +}; + +&uart1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart1>; + uart-has-rtscts; + status = "okay"; +}; + +&uart2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart2>; + status = "okay"; +}; + +&uart3 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart3>; + uart-has-rtscts; + status = "okay"; +}; + +&uart4 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_uart4>; + status = "okay"; +}; + +&usbh1 { + vbus-supply = <®_usbh1_vbus>; + dr_mode = "host"; + status = "okay"; +}; + +&usbotg { + vbus-supply = <®_usbotg_vbus>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usbotg>; + disable-over-current; + dr_mode = "host"; /* fixed configuration, ID pin not checked */ + status = "okay"; +}; + +&iomuxc { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio>; + + pinctrl_audmux: audmux { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 + MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 + MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 + >; + }; + + pinctrl_ecspi2: ecspi2grp { + fsl,pins = < + MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 + MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 + MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 + MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 /* SS0# */ + MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 /* SS1# */ + >; + }; + + pinctrl_enet: enetgrp { + fsl,pins = < + MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 + MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 + MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 + MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 + MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 + MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 + MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 + MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 + MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x400100b0 + MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 + MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 + MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 + MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 + MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 + MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 + /* make sure pin is GPIO and not ENET_REF_CLK */ + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x1a0b0 + >; + }; + + pinctrl_i2c1: i2c1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 + MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 + >; + }; + + pinctrl_i2c2: i2c2grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 + MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c3: i2c3grp { + fsl,pins = < + MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 + >; + }; + + pinctrl_i2c4: i2c4grp { + fsl,pins = < + MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 + MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 + >; + }; + + pinctrl_pwm1: pwm1grp { + fsl,pins = < + MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 + /* backlight enable */ + MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 + >; + }; + + pinctrl_uart1: uart1grp { + fsl,pins = < + MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 + MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart2: uart2grp { + fsl,pins = < + MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_uart3: uart3grp { + fsl,pins = < + MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 + MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 + MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + >; + }; + + pinctrl_uart4: uart4grp { + fsl,pins = < + MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 + MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + >; + }; + + pinctrl_aristainetos2_usbh1_vbus: aristainetos-usbh1-vbus { + fsl,pins = <MX6QDL_PAD_GPIO_0__GPIO1_IO00 0x400130b0>; + }; + + pinctrl_aristainetos2_usbotg_vbus: aristainetos-usbotg-vbus { + fsl,pins = <MX6QDL_PAD_KEY_ROW4__GPIO4_IO15 0x400130b0>; + }; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi new file mode 100644 index 0000000000..c713efd84c --- /dev/null +++ b/arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi @@ -0,0 +1,101 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2019 Heiko Schocher hs@denx.de + */ + +/ { + chosen { + u-boot,dm-pre-reloc; + stdout-path = &uart2; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + }; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_gpio { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart2 { + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-pre-reloc; +}; + +&backlight { + pwms = <&pwm1 0 300000>; + default-brightness-level = <2>; +}; + +/* + * allow switching write protect pin by gpio, + * because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot + */ +&gpio2 { + u-boot,dm-pre-reloc; + + wp_spi_nor { + gpio-hog; + output-high; + gpios = <15 GPIO_ACTIVE_HIGH>; + }; +}; + +&iomuxc { + pinctrl-0 = <&pinctrl_gpio &pinctrl_gpio_fix>; + u-boot,dm-pre-reloc; + + pinctrl_gpio_fix: gpiofixgrp { + /* + * usdhc2 has a levelshifter on the carrier board Rev. DV1, + * that will automatically detect the driving direction. + * During initialisation this isn't working correctly, + * which causes DAT3 to be driven low towards the SD-card. + * This causes a SD-card enetring the SPI-Mode + * and therefore getting inaccessible until next power cycle. + * As workaround we drive the DAT3 line as GPIO and set it high. + * This makes usdhc2 unusable in u-boot, but works for the + * initialisation in Linux + */ + fsl,pins = < + MX6QDL_PAD_SD2_DAT3__GPIO1_IO12 0x20000 + >; + }; +}; + +&gpio1 { + usdhc_fix { + gpio-hog; + output-high; + gpios = <12 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio3 { + u-boot,dm-pre-reloc; +}; + +&gpio5 { + u-boot,dm-pre-reloc; +}; + +&ecspi4 { + u-boot,dm-pre-reloc; +}; + +&flash { + u-boot,dm-pre-reloc; +}; + +&pinctrl_ecspi4 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2.dtsi b/arch/arm/dts/imx6qdl-aristainetos2.dtsi index da6ab63808..788e13edad 100644 --- a/arch/arm/dts/imx6qdl-aristainetos2.dtsi +++ b/arch/arm/dts/imx6qdl-aristainetos2.dtsi @@ -9,73 +9,43 @@ #include <dt-bindings/gpio/gpio.h> #include <dt-bindings/clock/imx6qdl-clock.h>
-/ { - backlight: backlight { - compatible = "pwm-backlight"; - pwms = <&pwm1 0 5000000>; - brightness-levels = <0 4 8 16 32 64 128 255>; - default-brightness-level = <7>; - enable-gpios = <&gpio6 31 GPIO_ACTIVE_HIGH>; - }; - - reg_2p5v: regulator-2p5v { - compatible = "regulator-fixed"; - regulator-name = "2P5V"; - regulator-min-microvolt = <2500000>; - regulator-max-microvolt = <2500000>; - regulator-always-on; - }; - - reg_3p3v: regulator-3p3v { - compatible = "regulator-fixed"; - regulator-name = "3P3V"; - regulator-min-microvolt = <3300000>; - regulator-max-microvolt = <3300000>; - regulator-always-on; - }; +#include "imx6qdl-aristainetos2-common.dtsi"
- reg_usbh1_vbus: regulator-usbh1-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio1 0 GPIO_ACTIVE_HIGH>; +/ { + leds { + compatible = "gpio-leds"; pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aristainetos2_usbh1_vbus>; - regulator-name = "usb_h1_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; + pinctrl-0 = <&pinctrl_gpio>;
- reg_usbotg_vbus: regulator-usbotg-vbus { - compatible = "regulator-fixed"; - enable-active-high; - gpio = <&gpio4 15 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_aristainetos2_usbotg_vbus>; - regulator-name = "usb_otg_vbus"; - regulator-min-microvolt = <5000000>; - regulator-max-microvolt = <5000000>; - }; -}; + LED_blue { + label = "led_blue"; + gpios = <&gpio2 29 GPIO_ACTIVE_LOW>; + };
-&audmux { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_audmux>; - status = "okay"; -}; + LED_green { + label = "led_green"; + gpios = <&gpio5 4 GPIO_ACTIVE_LOW>; + };
-&can1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan1>; - status = "okay"; -}; + LED_red { + label = "led_red"; + gpios = <&gpio2 28 GPIO_ACTIVE_LOW>; + };
-&can2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_flexcan2>; - status = "okay"; + LED_yellow { + label = "led_yellow"; + gpios = <&gpio6 16 GPIO_ACTIVE_LOW>; + }; + + LED_ena { + label = "led_ena"; + gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + }; + }; };
&ecspi1 { + fsl,spi-num-chipselects = <3>; cs-gpios = <&gpio4 9 GPIO_ACTIVE_HIGH &gpio4 10 GPIO_ACTIVE_HIGH &gpio4 11 GPIO_ACTIVE_HIGH>; @@ -84,18 +54,13 @@ status = "okay"; };
-&ecspi2 { - cs-gpios = <&gpio2 26 GPIO_ACTIVE_HIGH &gpio2 27 GPIO_ACTIVE_HIGH>; - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_ecspi2>; - status = "okay"; -}; - &ecspi4 { + fsl,spi-num-chipselects = <2>; cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; pinctrl-names = "default"; pinctrl-0 = <&pinctrl_ecspi4>; status = "okay"; + pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>;
flash: m25p80@1 { #address-cells = <1>; @@ -106,245 +71,29 @@ }; };
-&i2c1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c1>; - status = "okay"; - - pmic@58 { - compatible = "dlg,da9063"; - reg = <0x58>; - interrupt-parent = <&gpio1>; - interrupts = <04 0x8>; - - regulators { - bcore1 { - regulator-name = "bcore1"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bcore2 { - regulator-name = "bcore2"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bpro { - regulator-name = "bpro"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bperi { - regulator-name = "bperi"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bmem { - regulator-name = "bmem"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo2 { - regulator-name = "ldo2"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <1800000>; - }; - - ldo3 { - regulator-name = "ldo3"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo4 { - regulator-name = "ldo4"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo5 { - regulator-name = "ldo5"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo6 { - regulator-name = "ldo6"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo7 { - regulator-name = "ldo7"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo8 { - regulator-name = "ldo8"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo9 { - regulator-name = "ldo9"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo10 { - regulator-name = "ldo10"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - ldo11 { - regulator-name = "ldo11"; - regulator-always-on = <1>; - regulator-min-microvolt = <300000>; - regulator-max-microvolt = <3300000>; - }; - - bio { - regulator-name = "bio"; - regulator-always-on = <1>; - regulator-min-microvolt = <1800000>; - regulator-max-microvolt = <1800000>; - }; - }; - }; - - tmp103: tmp103@71 { - compatible = "ti,tmp103"; - reg = <0x71>; - }; -}; - -&i2c2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c2>; - status = "okay"; -}; - -&i2c3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c3>; - status = "okay"; - - expander: tca6416@20 { - compatible = "ti,tca6416"; - reg = <0x20>; - #gpio-cells = <2>; - gpio-controller; - }; - - rtc@68 { - compatible = "dallas,m41t00"; - reg = <0x68>; - }; -}; - -&i2c4 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_i2c4>; - status = "okay"; - - eeprom@50{ - compatible = "atmel,24c64"; - reg = <0x50>; - }; - - eeprom@57{ - compatible = "atmel,24c64"; - reg = <0x57>; +&gpio7 { + sd2_driver_ena { + gpio-hog; + output-high; + gpios = <8 GPIO_ACTIVE_HIGH>; }; };
-&fec { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_enet>; - phy-mode = "rgmii"; - phy-reset-gpios = <&gpio7 18 GPIO_ACTIVE_LOW>; - txd0-skew-ps = <0>; - txd1-skew-ps = <0>; - txd2-skew-ps = <0>; - txd3-skew-ps = <0>; - status = "okay"; -}; - &gpmi { pinctrl-names = "default"; pinctrl-0 = <&pinctrl_gpmi_nand>; status = "okay"; };
-&pcie { - reset-gpio = <&gpio2 16 GPIO_ACTIVE_LOW>; - status = "okay"; -}; - -&pwm1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_pwm1>; - status = "okay"; -}; - -&uart1 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart1>; - uart-has-rtscts; - status = "okay"; -}; - -&uart2 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart2>; - status = "okay"; -}; - -&uart3 { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart3>; - uart-has-rtscts; - status = "okay"; -}; - -&uart4 { +&can1 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_uart4>; - status = "okay"; -}; - -&usbh1 { - vbus-supply = <®_usbh1_vbus>; - dr_mode = "host"; + pinctrl-0 = <&pinctrl_flexcan1>; status = "okay"; };
-&usbotg { - vbus-supply = <®_usbotg_vbus>; +&can2 { pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_usbotg>; - disable-over-current; - dr_mode = "host"; + pinctrl-0 = <&pinctrl_flexcan2>; status = "okay"; };
@@ -366,18 +115,6 @@ };
&iomuxc { - pinctrl-names = "default"; - pinctrl-0 = <&pinctrl_gpio>; - - pinctrl_audmux: audmux { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT7__AUD3_RXD 0x1b0b0 - MX6QDL_PAD_CSI0_DAT4__AUD3_TXC 0x1b0b0 - MX6QDL_PAD_CSI0_DAT5__AUD3_TXD 0x1b0b0 - MX6QDL_PAD_CSI0_DAT6__AUD3_TXFS 0x1b0b0 - >; - }; - pinctrl_ecspi1: ecspi1grp { fsl,pins = < MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 @@ -389,16 +126,6 @@ >; };
- pinctrl_ecspi2: ecspi2grp { - fsl,pins = < - MX6QDL_PAD_EIM_OE__ECSPI2_MISO 0x100b1 - MX6QDL_PAD_EIM_CS0__ECSPI2_SCLK 0x100b1 - MX6QDL_PAD_EIM_CS1__ECSPI2_MOSI 0x100b1 - MX6QDL_PAD_EIM_RW__GPIO2_IO26 0x100b1 /* SS0# */ - MX6QDL_PAD_EIM_LBA__GPIO2_IO27 0x100b1 /* SS1# */ - >; - }; - pinctrl_ecspi4: ecspi4grp { fsl,pins = < MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 @@ -406,72 +133,40 @@ MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ - MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x1b0b0 /* WP pin */ - >; - }; - - pinctrl_enet: enetgrp { - fsl,pins = < - MX6QDL_PAD_ENET_MDIO__ENET_MDIO 0x1b0b0 - MX6QDL_PAD_ENET_MDC__ENET_MDC 0x1b0b0 - MX6QDL_PAD_RGMII_TXC__RGMII_TXC 0x1b0b0 - MX6QDL_PAD_RGMII_TD0__RGMII_TD0 0x1b0b0 - MX6QDL_PAD_RGMII_TD1__RGMII_TD1 0x1b0b0 - MX6QDL_PAD_RGMII_TD2__RGMII_TD2 0x1b0b0 - MX6QDL_PAD_RGMII_TD3__RGMII_TD3 0x1b0b0 - MX6QDL_PAD_RGMII_TX_CTL__RGMII_TX_CTL 0x1b0b0 - MX6QDL_PAD_ENET_REF_CLK__ENET_TX_CLK 0x1b0b0 - MX6QDL_PAD_RGMII_RXC__RGMII_RXC 0x1b0b0 - MX6QDL_PAD_RGMII_RD0__RGMII_RD0 0x1b0b0 - MX6QDL_PAD_RGMII_RD1__RGMII_RD1 0x1b0b0 - MX6QDL_PAD_RGMII_RD2__RGMII_RD2 0x1b0b0 - MX6QDL_PAD_RGMII_RD3__RGMII_RD3 0x1b0b0 - MX6QDL_PAD_RGMII_RX_CTL__RGMII_RX_CTL 0x1b0b0 - >; - }; - - pinctrl_flexcan1: flexcan1grp { - fsl,pins = < - MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 - MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 - >; - }; - - pinctrl_flexcan2: flexcan2grp { - fsl,pins = < - MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 - MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 /* WP pin */ >; };
pinctrl_gpio: gpiogrp { fsl,pins = < /* led enable */ - MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x1b0b0 + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 /* LCD power enable */ - MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x1b0b0 + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0 /* led yellow */ - MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x1b0b0 + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0 /* led red */ - MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x1b0b0 + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0 /* led green */ - MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x1b0b0 + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0 /* led blue */ - MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x1b0b0 + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0 /* Profibus IRQ */ MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 - /* FPGA IRQ */ + /* FPGA IRQ currently unused*/ MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 + /* Display reset because of clock failure */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 /* spi bus #2 SS driver enable */ - MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x1b0b0 + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 /* RST_LOC# PHY reset input (has pull-down!)*/ - MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x1b0b0 + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0 /* USB_OTG_ID = GPIO1_24*/ - MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x80000000 + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x4001b0b0 /* Touchscreen IRQ */ MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 /* PCIe reset */ - MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x1b0b0 + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 >; };
@@ -495,71 +190,17 @@ >; };
- pinctrl_i2c1: i2c1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT8__I2C1_SDA 0x4001b8b1 - MX6QDL_PAD_CSI0_DAT9__I2C1_SCL 0x4001b8b1 - >; - }; - - pinctrl_i2c2: i2c2grp { - fsl,pins = < - MX6QDL_PAD_KEY_COL3__I2C2_SCL 0x4001b8b1 - MX6QDL_PAD_KEY_ROW3__I2C2_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c3: i2c3grp { - fsl,pins = < - MX6QDL_PAD_GPIO_5__I2C3_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_6__I2C3_SDA 0x4001b8b1 - >; - }; - - pinctrl_i2c4: i2c4grp { - fsl,pins = < - MX6QDL_PAD_GPIO_7__I2C4_SCL 0x4001b8b1 - MX6QDL_PAD_GPIO_8__I2C4_SDA 0x4001b8b1 - >; - }; - - pinctrl_pwm1: pwm1grp { - fsl,pins = < - MX6QDL_PAD_GPIO_9__PWM1_OUT 0x1b0b0 - /* backlight enable */ - MX6QDL_PAD_EIM_BCLK__GPIO6_IO31 0x1b0b0 - >; - }; - - pinctrl_uart1: uart1grp { - fsl,pins = < - MX6QDL_PAD_CSI0_DAT10__UART1_TX_DATA 0x1b0b1 - MX6QDL_PAD_CSI0_DAT11__UART1_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D20__UART1_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D19__UART1_CTS_B 0x1b0b1 - >; - }; - - pinctrl_uart2: uart2grp { - fsl,pins = < - MX6QDL_PAD_EIM_D26__UART2_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D27__UART2_RX_DATA 0x1b0b1 - >; - }; - - pinctrl_uart3: uart3grp { + pinctrl_flexcan1: flexcan1grp { fsl,pins = < - MX6QDL_PAD_EIM_D24__UART3_TX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D25__UART3_RX_DATA 0x1b0b1 - MX6QDL_PAD_EIM_D31__UART3_RTS_B 0x1b0b1 - MX6QDL_PAD_EIM_D23__UART3_CTS_B 0x1b0b1 + MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 >; };
- pinctrl_uart4: uart4grp { + pinctrl_flexcan2: flexcan2grp { fsl,pins = < - MX6QDL_PAD_KEY_COL0__UART4_TX_DATA 0x1b0b1 - MX6QDL_PAD_KEY_ROW0__UART4_RX_DATA 0x1b0b1 + MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 >; };
@@ -569,14 +210,6 @@ >; };
- pinctrl_aristainetos2_usbh1_vbus: aristainetos-usbh1-vbus { - fsl,pins = <MX6QDL_PAD_GPIO_0__USB_H1_PWR 0x130b0>; - }; - - pinctrl_aristainetos2_usbotg_vbus: aristainetos-usbotg-vbus { - fsl,pins = <MX6QDL_PAD_KEY_ROW4__USB_OTG_PWR 0x130b0>; - }; - pinctrl_usdhc1: usdhc1grp { fsl,pins = < MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 @@ -601,7 +234,7 @@ MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 /* SD2 level shifter output enable */ - MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x1b0b0 + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 /* SD2 card detect input */ MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 /* SD2 write protect input */ diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS index 91c8ae0738..2495cd4a37 100644 --- a/board/aristainetos/MAINTAINERS +++ b/board/aristainetos/MAINTAINERS @@ -4,6 +4,12 @@ S: Maintained F: board/aristainetos/ F: include/configs/aristainetos2.h F: configs/aristainetos2_defconfig -F: arch/arm/dts/imx6dl-aristainetos2_4.dts -F: arch/arm/dts/imx6dl-aristainetos2_7.dts F: arch/arm/dts/imx6qdl-aristainetos2.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2-common.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi +F: arch/arm/dts/imx6dl-aristainetos2_7.dts +F: arch/arm/dts/imx6dl-aristainetos2_7.dtsi +F: arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi +F: arch/arm/dts/imx6dl-aristainetos2_4.dts +F: arch/arm/dts/imx6dl-aristainetos2_4.dtsi +F: arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 11b64d08be..b296ea2522 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -31,6 +31,7 @@ #include <asm/io.h> #include <asm/arch/sys_proto.h> #include <pwm.h> +#include <dm/root.h> #include <env.h> #include <micrel.h> #include <spi.h> @@ -82,6 +83,14 @@ DECLARE_GLOBAL_DATA_PTR; #define SOFT_RESET_GPIO IMX_GPIO_NR(7, 13) #define SD2_DRIVER_ENABLE IMX_GPIO_NR(7, 8)
+enum { + BOARD_TYPE_4 = 4, + BOARD_TYPE_7 = 7, +}; + +#define ARI_BT_4 "aristainetos2_4@2" +#define ARI_BT_7 "aristainetos2_7@1" + struct i2c_pads_info i2c_pad_info3 = { .scl = { .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, @@ -617,6 +626,7 @@ static void set_gpr_register(void) &iomuxc_regs->gpr[12]); }
+extern char __bss_start[], __bss_end[]; int board_early_init_f(void) { setup_iomux_uart(); @@ -626,6 +636,14 @@ int board_early_init_f(void) gpio_direction_output(SD2_DRIVER_ENABLE, 1); setup_display(); set_gpr_register(); + + /* + * clear bss here, so we can use spi driver + * before relocation and read Environment + * from spi flash. + */ + memset(__bss_start, 0x00, __bss_end - __bss_start); + return 0; }
@@ -704,6 +722,12 @@ int board_late_init(void) CONFIG_LG4573_CS, 10000000, SPI_MODE_0);
+ /* set board_type */ + if (gd->board_type == BOARD_TYPE_4) + env_set("board_type", ARI_BT_4); + else + env_set("board_type", ARI_BT_7); + return 0; }
@@ -962,6 +986,50 @@ int board_ehci_power(int port, int on) gpio_set_value(ARISTAINETOS_USB_OTG_PWR, on); else gpio_set_value(ARISTAINETOS_USB_H1_PWR, on); + + return 0; +} +#endif + +int board_fit_config_name_match(const char *name) +{ + if (gd->board_type == BOARD_TYPE_4 && + strchr(name, 0x34)) + return 0; + + if (gd->board_type == BOARD_TYPE_7 && + strchr(name, 0x37)) + return 0; + + return -1; +} + +static void do_board_detect(void) +{ + int ret; + char s[30]; + + /* default use board type 7 */ + gd->board_type = BOARD_TYPE_7; + if (env_init()) + return; + + ret = env_get_f("panel", s, sizeof(s)); + if (ret < 0) + return; + + if (!strncmp("lg4573", s, 6)) + gd->board_type = BOARD_TYPE_4; +} + +#ifdef CONFIG_DTB_RESELECT +int embedded_dtb_select(void) +{ + int rescan; + + do_board_detect(); + fdtdec_resetup(&rescan); + return 0; } #endif diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 4434d92e74..515f9a48a1 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -15,6 +15,7 @@ CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_TYPES=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y CONFIG_CMD_BOOTZ=y @@ -42,7 +43,13 @@ CONFIG_CMD_FAT=y CONFIG_CMD_FS_GENERIC=y CONFIG_CMD_MTDPARTS=y CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2_4" +CONFIG_OF_LIST="imx6dl-aristainetos2_4 imx6dl-aristainetos2_7" +CONFIG_DTB_RESELECT=y +CONFIG_MULTI_DTB_FIT=y CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SPI_EARLY=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_OFFSET_REDUND=0xE0000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y
as we switch to support DM and DTS, rework the existing DTS trees. Change also Linux specific Device trees, goal is to push this changes to linux. Collect U-Boot specific changes in separate "*u-boot*" dts files. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
add DM_SERIAL support for the aristainetos board, and remove not used code from board code.
remove CONSOLE_OVERWRITE_ROUTINE.
Signed-off-by: Heiko Schocher hs@denx.de ---
arch/arm/mach-imx/mx6/Kconfig | 2 ++ board/aristainetos/aristainetos.c | 60 ------------------------------- configs/aristainetos2_defconfig | 3 +- 3 files changed, 4 insertions(+), 61 deletions(-)
diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 3892d0a0e9..ede5989502 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -132,7 +132,9 @@ config TARGET_ARISTAINETOS2 select SYS_I2C_MXC select MXC_UART select FEC_MXC + select DM imply CMD_SATA + imply CMD_DM
config TARGET_CGTQMX6EVAL bool "cgtqmx6eval" diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index b296ea2522..00ffac8eb6 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -43,10 +43,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#define UART_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - #define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ PAD_CTL_SRE_FAST | PAD_CTL_HYS) @@ -117,30 +113,6 @@ struct i2c_pads_info i2c_pad_info4 = { } };
-iomux_v3_cfg_t const uart1_pads[] = { - MX6_PAD_CSI0_DAT10__UART1_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_CSI0_DAT11__UART1_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D19__UART1_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D20__UART1_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const uart2_pads[] = { - MX6_PAD_EIM_D26__UART2_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D27__UART2_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const uart3_pads[] = { - MX6_PAD_EIM_D24__UART3_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D25__UART3_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D31__UART3_RTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_EIM_D23__UART3_CTS_B | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - -iomux_v3_cfg_t const uart4_pads[] = { - MX6_PAD_KEY_COL0__UART4_TX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), - MX6_PAD_KEY_ROW0__UART4_RX_DATA | MUX_PAD_CTRL(UART_PAD_CTRL), -}; - iomux_v3_cfg_t const gpio_pads[] = { /* LED enable*/ MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -312,28 +284,6 @@ static void setup_spi(void) #endif }
-static void setup_iomux_uart(void) -{ - switch (CONFIG_MXC_UART_BASE) { - case UART1_BASE: - imx_iomux_v3_setup_multiple_pads(uart1_pads, - ARRAY_SIZE(uart1_pads)); - break; - case UART2_BASE: - imx_iomux_v3_setup_multiple_pads(uart2_pads, - ARRAY_SIZE(uart2_pads)); - break; - case UART3_BASE: - imx_iomux_v3_setup_multiple_pads(uart3_pads, - ARRAY_SIZE(uart3_pads)); - break; - case UART4_BASE: - imx_iomux_v3_setup_multiple_pads(uart4_pads, - ARRAY_SIZE(uart4_pads)); - break; - } -} - int board_phy_config(struct phy_device *phydev) { /* control data pad skew - devaddr = 0x02, register = 0x04 */ @@ -629,7 +579,6 @@ static void set_gpr_register(void) extern char __bss_start[], __bss_end[]; int board_early_init_f(void) { - setup_iomux_uart(); setup_iomux_gpio();
gpio_direction_output(SOFT_RESET_GPIO, 1); @@ -808,15 +757,6 @@ int board_mmc_init(bd_t *bis) } #endif
-/* - * Do not overwrite the console - * Use always serial for U-Boot console - */ -int overwrite_console(void) -{ - return 1; -} - struct display_info_t const displays[] = { { .bus = -1, diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 515f9a48a1..03be7f3f8f 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -2,6 +2,7 @@ CONFIG_ARM=y CONFIG_SYS_THUMB_BUILD=y CONFIG_ARCH_MX6=y CONFIG_SYS_TEXT_BASE=0x17800000 +CONFIG_SYS_MALLOC_F_LEN=0xe000 CONFIG_TARGET_ARISTAINETOS2=y CONFIG_ENV_SIZE=0x3000 CONFIG_ENV_OFFSET=0xD0000 @@ -12,7 +13,6 @@ CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y -CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE=y CONFIG_SUPPORT_RAW_INITRD=y CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_TYPES=y @@ -69,6 +69,7 @@ CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_MII=y CONFIG_PWM_IMX=y +CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y
add DM_SERIAL support for the aristainetos board, and remove not used code from board code. remove CONSOLE_OVERWRITE_ROUTINE. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
Enable DM_MMC support.
Signed-off-by: Heiko Schocher hs@denx.de ---
board/aristainetos/aristainetos.c | 53 ------------------------------- configs/aristainetos2_defconfig | 1 + include/configs/aristainetos2.h | 2 +- 3 files changed, 2 insertions(+), 54 deletions(-)
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 00ffac8eb6..6de71a46ed 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -19,8 +19,6 @@ #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/mxc_i2c.h> #include <asm/mach-imx/video.h> -#include <mmc.h> -#include <fsl_esdhc_imx.h> #include <miiphy.h> #include <netdev.h> #include <asm/arch/mxc_hdmi.h> @@ -43,10 +41,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#define USDHC_PAD_CTRL (PAD_CTL_PUS_47K_UP | \ - PAD_CTL_SPEED_LOW | PAD_CTL_DSE_80ohm | \ - PAD_CTL_SRE_FAST | PAD_CTL_HYS) - #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
@@ -63,9 +57,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define ECSPI4_CS1 IMX_GPIO_NR(5, 2)
-#define USDHC2_PAD_CTRL (PAD_CTL_SPEED_LOW | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - #if (CONFIG_SYS_BOARD_VERSION == 2) /* 4.3 display controller */ #define ECSPI1_CS0 IMX_GPIO_NR(4, 9) @@ -706,15 +697,6 @@ struct i2c_pads_info i2c_pad_info2 = { } };
-iomux_v3_cfg_t const usdhc1_pads[] = { - MX6_PAD_SD1_CLK__SD1_CLK | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_CMD__SD1_CMD | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT0__SD1_DATA0 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT1__SD1_DATA1 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT2__SD1_DATA2 | MUX_PAD_CTRL(USDHC_PAD_CTRL), - MX6_PAD_SD1_DAT3__SD1_DATA3 | MUX_PAD_CTRL(USDHC_PAD_CTRL), -}; - int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -722,41 +704,6 @@ int dram_init(void) return 0; }
-#ifdef CONFIG_FSL_ESDHC_IMX -struct fsl_esdhc_cfg usdhc_cfg[2] = { - {USDHC1_BASE_ADDR}, - {USDHC2_BASE_ADDR}, -}; - -int board_mmc_getcd(struct mmc *mmc) -{ - return 1; -} - -int board_mmc_init(bd_t *bis) -{ - usdhc_cfg[0].sdhc_clk = mxc_get_clock(MXC_ESDHC_CLK); - imx_iomux_v3_setup_multiple_pads(usdhc1_pads, ARRAY_SIZE(usdhc1_pads)); -#if (CONFIG_SYS_BOARD_VERSION == 2) - /* - * usdhc2 has a levelshifter on the carrier board Rev. DV1, - * that will automatically detect the driving direction. - * During initialisation this isn't working correctly, - * which causes DAT3 to be driven low towards the SD-card. - * This causes a SD-card enetring the SPI-Mode - * and therefore getting inaccessible until next power cycle. - * As workaround we drive the DAT3 line as GPIO and set it high. - * This makes usdhc2 unusable in u-boot, but works for the - * initialisation in Linux - */ - imx_iomux_v3_setup_pad(MX6_PAD_SD2_DAT3__GPIO1_IO12 | - MUX_PAD_CTRL(NO_PAD_CTRL)); - gpio_direction_output(IMX_GPIO_NR(1, 12) , 1); -#endif - return fsl_esdhc_initialize(bis, &usdhc_cfg[0]); -} -#endif - struct display_info_t const displays[] = { { .bus = -1, diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 03be7f3f8f..02c64a947c 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -53,6 +53,7 @@ CONFIG_ENV_SPI_EARLY=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_OFFSET_REDUND=0xE0000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y CONFIG_NAND=y CONFIG_NAND_MXS=y diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 9291cfdffd..b008928c06 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -45,7 +45,7 @@ #define CONFIG_MMCROOT "/dev/mmcblk0p1"
/* MMC Configs */ -#define CONFIG_SYS_FSL_ESDHC_ADDR 0 +#define CONFIG_SYS_FSL_ESDHC_ADDR USDHC1_BASE_ADDR
#define IMX_FEC_BASE ENET_BASE_ADDR #define CONFIG_ETHPRIME "FEC"
Enable DM_MMC support. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
Enable DM_GPIO, GPIO_HOG, LED and LED_GPIO as gpio and LEDs are now defined in DTS. Enable also here the pinctrl driver, so pinmux setup is also done.
Signed-off-by: Heiko Schocher hs@denx.de ---
board/aristainetos/aristainetos.c | 134 ++++++++++++------------------ configs/aristainetos2_defconfig | 8 ++ 2 files changed, 61 insertions(+), 81 deletions(-)
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 6de71a46ed..5639eefa15 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -38,6 +38,7 @@ #if defined(CONFIG_VIDEO_BMP_LOGO) #include <bmp_logo.h> #endif +#include <led.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -67,9 +68,6 @@ DECLARE_GLOBAL_DATA_PTR; #define ECSPI1_CS1 IMX_GPIO_NR(4, 10) #endif
-#define SOFT_RESET_GPIO IMX_GPIO_NR(7, 13) -#define SD2_DRIVER_ENABLE IMX_GPIO_NR(7, 8) - enum { BOARD_TYPE_4 = 4, BOARD_TYPE_7 = 7, @@ -104,43 +102,6 @@ struct i2c_pads_info i2c_pad_info4 = { } };
-iomux_v3_cfg_t const gpio_pads[] = { - /* LED enable*/ - MX6_PAD_ENET_CRS_DV__GPIO1_IO25 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* LED yellow */ - MX6_PAD_NANDF_CS3__GPIO6_IO16 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* LED red */ -#if (CONFIG_SYS_BOARD_VERSION == 2) - MX6_PAD_EIM_EB0__GPIO2_IO28 | MUX_PAD_CTRL(NO_PAD_CTRL), -#elif (CONFIG_SYS_BOARD_VERSION == 3) - MX6_PAD_EIM_WAIT__GPIO5_IO00 | MUX_PAD_CTRL(NO_PAD_CTRL), -#endif - /* LED green */ - MX6_PAD_EIM_A24__GPIO5_IO04 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* LED blue */ - MX6_PAD_EIM_EB1__GPIO2_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* spi flash WP protect */ - MX6_PAD_SD4_DAT7__GPIO2_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* spi CS 0 */ - MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* spi bus #2 SS driver enable */ - MX6_PAD_EIM_A23__GPIO6_IO06 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* RST_LOC# PHY reset input (has pull-down!)*/ - MX6_PAD_GPIO_18__GPIO7_IO13 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* SD 2 level shifter output enable */ - MX6_PAD_SD3_RST__GPIO7_IO08 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* SD1 card detect input */ - MX6_PAD_ENET_RXD0__GPIO1_IO27 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* SD1 write protect input */ - MX6_PAD_DI0_PIN4__GPIO4_IO20 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* SD2 card detect input */ - MX6_PAD_GPIO_19__GPIO4_IO05 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* SD2 write protect input */ - MX6_PAD_SD4_DAT2__GPIO2_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* Touchscreen IRQ */ - MX6_PAD_SD4_DAT1__GPIO2_IO09 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - static iomux_v3_cfg_t const misc_pads[] = { /* USB_OTG_ID = GPIO1_24*/ MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -265,12 +226,16 @@ static void setup_spi(void) for (i = 0; i < 4; i++) enable_spi_clk(true, i);
+ gpio_request(ECSPI1_CS0, "spi1_cs0"); gpio_direction_output(ECSPI1_CS0, 1); #if (CONFIG_SYS_BOARD_VERSION == 2) + gpio_request(ECSPI4_CS1, "spi4_cs1"); gpio_direction_output(ECSPI4_CS1, 0); /* set cs0 to high (second device on spi bus #4) */ + gpio_request(ECSPI4_CS0, "spi4_cs0"); gpio_direction_output(ECSPI4_CS0, 1); #elif (CONFIG_SYS_BOARD_VERSION == 3) + gpio_request(ECSPI1_CS1, "spi1_cs1"); gpio_direction_output(ECSPI1_CS1, 1); #endif } @@ -359,9 +324,13 @@ static void enable_display_power(void) ARRAY_SIZE(backlight_pads));
/* backlight enable */ + gpio_request(IMX_GPIO_NR(6, 31), "backlight"); gpio_direction_output(IMX_GPIO_NR(6, 31), 1); + gpio_free(IMX_GPIO_NR(6, 31)); /* LCD power enable */ + gpio_request(IMX_GPIO_NR(6, 15), "LCD_power_enable"); gpio_direction_output(IMX_GPIO_NR(6, 15), 1); + gpio_free(IMX_GPIO_NR(6, 15));
/* enable backlight PWM 1 */ if (pwm_init(0, 0, 0)) @@ -547,11 +516,6 @@ static void setup_display(void) enable_display_power(); }
-static void setup_iomux_gpio(void) -{ - imx_iomux_v3_setup_multiple_pads(gpio_pads, ARRAY_SIZE(gpio_pads)); -} - static void set_gpr_register(void) { struct iomuxc *iomuxc_regs = (struct iomuxc *)IOMUXC_BASE_ADDR; @@ -570,10 +534,6 @@ static void set_gpr_register(void) extern char __bss_start[], __bss_end[]; int board_early_init_f(void) { - setup_iomux_gpio(); - - gpio_direction_output(SOFT_RESET_GPIO, 1); - gpio_direction_output(SD2_DRIVER_ENABLE, 1); setup_display(); set_gpr_register();
@@ -593,37 +553,30 @@ static void setup_i2c4(void) &i2c_pad_info4); }
-static void setup_board_gpio(void) +static void setup_one_led(char *label, int state) { - /* enable all LEDs */ - gpio_request(IMX_GPIO_NR(2, 13), "LED ena"); /* 25 */ - gpio_direction_output(IMX_GPIO_NR(1, 25), 0); + struct udevice *dev; + int ret;
+ ret = led_get_by_label(label, &dev); + if (ret == 0) + led_set_state(dev, state); +} + +static void setup_board_gpio(void) +{ + setup_one_led("led_ena", LEDST_ON); /* switch off Status LEDs */ -#if (CONFIG_SYS_BOARD_VERSION == 2) - gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */ - gpio_direction_output(IMX_GPIO_NR(6, 16), 1); - gpio_request(IMX_GPIO_NR(2, 28), "LED red"); /* 60 */ - gpio_direction_output(IMX_GPIO_NR(2, 28), 1); - gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */ - gpio_direction_output(IMX_GPIO_NR(5, 4), 1); - gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */ - gpio_direction_output(IMX_GPIO_NR(2, 29), 1); -#elif (CONFIG_SYS_BOARD_VERSION == 3) - gpio_request(IMX_GPIO_NR(6, 16), "LED yellow"); /* 176 */ - gpio_direction_output(IMX_GPIO_NR(6, 16), 0); - gpio_request(IMX_GPIO_NR(5, 0), "LED red"); /* 128 */ - gpio_direction_output(IMX_GPIO_NR(5, 0), 0); - gpio_request(IMX_GPIO_NR(5, 4), "LED green"); /* 132 */ - gpio_direction_output(IMX_GPIO_NR(5, 4), 0); - gpio_request(IMX_GPIO_NR(2, 29), "LED blue"); /* 61 */ - gpio_direction_output(IMX_GPIO_NR(2, 29), 0); -#endif + setup_one_led("led_yellow", LEDST_OFF); + setup_one_led("led_red", LEDST_OFF); + setup_one_led("led_green", LEDST_OFF); + setup_one_led("led_blue", LEDST_OFF); }
static void setup_board_spi(void) { /* enable spi bus #2 SS drivers (and spi bus #4 SS1 for rev2b) */ + gpio_request(IMX_GPIO_NR(6, 6), "spi_ena"); gpio_direction_output(IMX_GPIO_NR(6, 6), 1); }
@@ -632,20 +585,23 @@ int board_late_init(void) char *my_bootdelay; char bootmode = 0; char const *panel = env_get("panel"); + struct gpio_desc *desc; + int ret;
+ led_default_state(); /* * Check the boot-source. If booting from NOR Flash, * disable bootdelay */ - gpio_request(IMX_GPIO_NR(7, 6), "bootsel0"); - gpio_direction_input(IMX_GPIO_NR(7, 6)); - gpio_request(IMX_GPIO_NR(7, 7), "bootsel1"); - gpio_direction_input(IMX_GPIO_NR(7, 7)); - gpio_request(IMX_GPIO_NR(7, 1), "bootsel2"); - gpio_direction_input(IMX_GPIO_NR(7, 1)); - bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 6)) ? 1 : 0) << 0; - bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 7)) ? 1 : 0) << 1; - bootmode |= (gpio_get_value(IMX_GPIO_NR(7, 1)) ? 1 : 0) << 2; + desc = gpio_hog_lookup_name("bootsel0"); + if (desc) + bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0; + desc = gpio_hog_lookup_name("bootsel1"); + if (desc) + bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1; + desc = gpio_hog_lookup_name("bootsel2"); + if (desc) + bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2;
if (bootmode == 7) { my_bootdelay = env_get("nor_bootdelay"); @@ -655,6 +611,22 @@ int board_late_init(void) env_set("bootdelay", "-2"); }
+ /* read out some jumper values*/ + ret = gpio_hog_lookup_name("env_reset", &desc); + if (!ret) { + if (dm_gpio_get_value(desc)) { + printf("\nClear env (set back to defaults)\n"); + run_command("run default_env; saveenv; saveenv", 0); + } + } + ret = gpio_hog_lookup_name("boot_rescue", &desc); + if (!ret) { + if (dm_gpio_get_value(desc)) { + aristainetos_run_rescue_command(16); + run_command("run rescue_xload_boot", 0); + } + } + /* if we have the lg panel, we can initialze it now */ if (panel) if (!strcmp(panel, displays[1].mode.name)) diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 02c64a947c..4253e4b562 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -28,6 +28,7 @@ CONFIG_CMD_GPIO=y CONFIG_CMD_I2C=y CONFIG_CMD_MMC=y CONFIG_CMD_NAND_TRIMFFS=y +# CONFIG_CMD_PINMUX is not set # CONFIG_CMD_SATA is not set CONFIG_CMD_USB=y CONFIG_CMD_DHCP=y @@ -53,6 +54,11 @@ CONFIG_ENV_SPI_EARLY=y CONFIG_SYS_REDUNDAND_ENVIRONMENT=y CONFIG_ENV_OFFSET_REDUND=0xE0000 CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_GPIO=y +CONFIG_GPIO_HOG=y +CONFIG_DM_PCA953X=y +CONFIG_LED=y +CONFIG_LED_GPIO=y CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y CONFIG_NAND=y @@ -69,6 +75,8 @@ CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_MII=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y CONFIG_PWM_IMX=y CONFIG_DM_SERIAL=y CONFIG_SPI=y
Enable DM_GPIO, GPIO_HOG, LED and LED_GPIO as gpio and LEDs are now defined in DTS. Enable also here the pinctrl driver, so pinmux setup is also done. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
Drop CONFIG_USB_MAX_CONTROLLER_COUNT and enable DM_USB in defconfig.
Signed-off-by: Heiko Schocher hs@denx.de ---
board/aristainetos/aristainetos.c | 35 ------------------------------- configs/aristainetos2_defconfig | 4 ++++ include/configs/aristainetos2.h | 3 --- 3 files changed, 4 insertions(+), 38 deletions(-)
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 5639eefa15..c2218cb5c2 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -102,15 +102,6 @@ struct i2c_pads_info i2c_pad_info4 = { } };
-static iomux_v3_cfg_t const misc_pads[] = { - /* USB_OTG_ID = GPIO1_24*/ - MX6_PAD_ENET_RX_ER__USB_OTG_ID | MUX_PAD_CTRL(NO_PAD_CTRL), - /* H1 Power enable = GPIO1_0*/ - MX6_PAD_GPIO_0__USB_H1_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), - /* OTG Power enable = GPIO4_15*/ - MX6_PAD_KEY_ROW4__USB_OTG_PWR | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - iomux_v3_cfg_t const enet_pads[] = { MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), @@ -815,7 +806,6 @@ int board_init(void)
/* GPIO_1 for USB_OTG_ID */ clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0); - imx_iomux_v3_setup_multiple_pads(misc_pads, ARRAY_SIZE(misc_pads)); return 0; }
@@ -825,31 +815,6 @@ int checkboard(void) return 0; }
-#ifdef CONFIG_USB_EHCI_MX6 -int board_ehci_hcd_init(int port) -{ - int ret; - - ret = gpio_request(ARISTAINETOS_USB_H1_PWR, "usb-h1-pwr"); - if (!ret) - gpio_direction_output(ARISTAINETOS_USB_H1_PWR, 1); - ret = gpio_request(ARISTAINETOS_USB_OTG_PWR, "usb-OTG-pwr"); - if (!ret) - gpio_direction_output(ARISTAINETOS_USB_OTG_PWR, 1); - return 0; -} - -int board_ehci_power(int port, int on) -{ - if (port) - gpio_set_value(ARISTAINETOS_USB_OTG_PWR, on); - else - gpio_set_value(ARISTAINETOS_USB_H1_PWR, on); - - return 0; -} -#endif - int board_fit_config_name_match(const char *name) { if (gd->board_type == BOARD_TYPE_4 && diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 4253e4b562..05af602dc8 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -77,11 +77,15 @@ CONFIG_PHY_MICREL_KSZ90X1=y CONFIG_MII=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_IMX=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y +CONFIG_DM_USB=y CONFIG_USB_STORAGE=y CONFIG_VIDEO_IPUV3=y CONFIG_VIDEO=y diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index b008928c06..269162eabf 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -31,8 +31,6 @@ "ubifsload ${fit_addr_r} /boot/system.itb; " \ "imi ${fit_addr_r}\0 "
-#define ARISTAINETOS_USB_OTG_PWR IMX_GPIO_NR(4, 15) -#define ARISTAINETOS_USB_H1_PWR IMX_GPIO_NR(1, 0) #define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15)
/* Framebuffer */ @@ -189,7 +187,6 @@ #define CONFIG_RTC_M41T11
/* USB Configs */ -#define CONFIG_USB_MAX_CONTROLLER_COUNT 2 #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW) #define CONFIG_MXC_USB_FLAGS 0
Drop CONFIG_USB_MAX_CONTROLLER_COUNT and enable DM_USB in defconfig. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
enable CONFIG_DM_SPI and CONFIG_DM_SPI_FLASH and get rid of build removal warnings.
define CONFIG_GPIO_ENABLE_SPI_FLASH is not longer needed, so remove it from config_whitelist.txt
Signed-off-by: Heiko Schocher hs@denx.de ---
board/aristainetos/aristainetos.c | 97 ------------------------------- configs/aristainetos2_defconfig | 3 + include/configs/aristainetos2.h | 2 - scripts/config_whitelist.txt | 1 - 4 files changed, 3 insertions(+), 100 deletions(-)
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index c2218cb5c2..5bb238b073 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -32,7 +32,6 @@ #include <dm/root.h> #include <env.h> #include <micrel.h> -#include <spi.h> #include <video.h> #include <../drivers/video/imx/ipu.h> #if defined(CONFIG_VIDEO_BMP_LOGO) @@ -45,9 +44,6 @@ DECLARE_GLOBAL_DATA_PTR; #define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS)
-#define SPI_PAD_CTRL (PAD_CTL_HYS | PAD_CTL_SPEED_MED | \ - PAD_CTL_DSE_40ohm | PAD_CTL_SRE_FAST) - #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) @@ -56,18 +52,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define DISP_PAD_CTRL (0x10)
-#define ECSPI4_CS1 IMX_GPIO_NR(5, 2) - -#if (CONFIG_SYS_BOARD_VERSION == 2) - /* 4.3 display controller */ - #define ECSPI1_CS0 IMX_GPIO_NR(4, 9) - #define ECSPI4_CS0 IMX_GPIO_NR(3, 29) -#elif (CONFIG_SYS_BOARD_VERSION == 3) - #define ECSPI1_CS0 IMX_GPIO_NR(2, 30) /* NOR flash */ - /* 4.3 display controller */ - #define ECSPI1_CS1 IMX_GPIO_NR(4, 10) -#endif - enum { BOARD_TYPE_4 = 4, BOARD_TYPE_7 = 7, @@ -129,33 +113,11 @@ static iomux_v3_cfg_t const backlight_pads[] = { MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), };
-static iomux_v3_cfg_t const ecspi1_pads[] = { - MX6_PAD_EIM_D16__ECSPI1_SCLK | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D17__ECSPI1_MISO | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_EIM_D18__ECSPI1_MOSI | MUX_PAD_CTRL(SPI_PAD_CTRL), -#if (CONFIG_SYS_BOARD_VERSION == 2) - MX6_PAD_KEY_ROW1__GPIO4_IO09 | MUX_PAD_CTRL(SPI_PAD_CTRL), -#elif (CONFIG_SYS_BOARD_VERSION == 3) - MX6_PAD_EIM_EB2__GPIO2_IO30 | MUX_PAD_CTRL(SPI_PAD_CTRL), - MX6_PAD_KEY_COL2__GPIO4_IO10 | MUX_PAD_CTRL(NO_PAD_CTRL), -#endif -}; - static void setup_iomux_enet(void) { imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); }
-#if (CONFIG_SYS_BOARD_VERSION == 2) -iomux_v3_cfg_t const ecspi4_pads[] = { - MX6_PAD_EIM_D21__ECSPI4_SCLK | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_EIM_D22__ECSPI4_MISO | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_EIM_D28__ECSPI4_MOSI | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_EIM_A25__GPIO5_IO02 | MUX_PAD_CTRL(NO_PAD_CTRL), - MX6_PAD_EIM_D29__GPIO3_IO29 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; -#endif - static iomux_v3_cfg_t const display_pads[] = { MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL), MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, @@ -187,50 +149,6 @@ static iomux_v3_cfg_t const display_pads[] = { MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, };
-int board_spi_cs_gpio(unsigned int bus, unsigned int cs) -{ - if (bus == CONFIG_SF_DEFAULT_BUS && cs == CONFIG_SF_DEFAULT_CS) -#if (CONFIG_SYS_BOARD_VERSION == 2) - return IMX_GPIO_NR(5, 2); - - if (bus == 0 && cs == 0) - return IMX_GPIO_NR(4, 9); -#elif (CONFIG_SYS_BOARD_VERSION == 3) - return ECSPI1_CS0; - - if (bus == 0 && cs == 1) - return ECSPI1_CS1; -#endif - return -1; -} - -static void setup_spi(void) -{ - int i; - - imx_iomux_v3_setup_multiple_pads(ecspi1_pads, ARRAY_SIZE(ecspi1_pads)); - -#if (CONFIG_SYS_BOARD_VERSION == 2) - imx_iomux_v3_setup_multiple_pads(ecspi4_pads, ARRAY_SIZE(ecspi4_pads)); -#endif - - for (i = 0; i < 4; i++) - enable_spi_clk(true, i); - - gpio_request(ECSPI1_CS0, "spi1_cs0"); - gpio_direction_output(ECSPI1_CS0, 1); -#if (CONFIG_SYS_BOARD_VERSION == 2) - gpio_request(ECSPI4_CS1, "spi4_cs1"); - gpio_direction_output(ECSPI4_CS1, 0); - /* set cs0 to high (second device on spi bus #4) */ - gpio_request(ECSPI4_CS0, "spi4_cs0"); - gpio_direction_output(ECSPI4_CS0, 1); -#elif (CONFIG_SYS_BOARD_VERSION == 3) - gpio_request(ECSPI1_CS1, "spi1_cs1"); - gpio_direction_output(ECSPI1_CS1, 1); -#endif -} - int board_phy_config(struct phy_device *phydev) { /* control data pad skew - devaddr = 0x02, register = 0x04 */ @@ -564,13 +482,6 @@ static void setup_board_gpio(void) setup_one_led("led_blue", LEDST_OFF); }
-static void setup_board_spi(void) -{ - /* enable spi bus #2 SS drivers (and spi bus #4 SS1 for rev2b) */ - gpio_request(IMX_GPIO_NR(6, 6), "spi_ena"); - gpio_direction_output(IMX_GPIO_NR(6, 6), 1); -} - int board_late_init(void) { char *my_bootdelay; @@ -785,8 +696,6 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
- setup_spi(); - setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, &i2c_pad_info1); setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, @@ -795,14 +704,8 @@ int board_init(void) &i2c_pad_info3); setup_i2c4();
- /* SPI NOR Flash read only */ - gpio_request(CONFIG_GPIO_ENABLE_SPI_FLASH, "ena_spi_nor"); - gpio_direction_output(CONFIG_GPIO_ENABLE_SPI_FLASH, 0); - gpio_free(CONFIG_GPIO_ENABLE_SPI_FLASH); - setup_board_gpio(); setup_gpmi_nand(); - setup_board_spi();
/* GPIO_1 for USB_OTG_ID */ clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0); diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 05af602dc8..d89b99b53d 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -61,8 +61,10 @@ CONFIG_LED=y CONFIG_LED_GPIO=y CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y +CONFIG_MTD=y CONFIG_NAND=y CONFIG_NAND_MXS=y +CONFIG_DM_SPI_FLASH=y CONFIG_SF_DEFAULT_BUS=3 CONFIG_SF_DEFAULT_CS=1 CONFIG_SF_DEFAULT_MODE=0 @@ -83,6 +85,7 @@ CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_IMX=y CONFIG_DM_SERIAL=y CONFIG_SPI=y +CONFIG_DM_SPI=y CONFIG_MXC_SPI=y CONFIG_USB=y CONFIG_DM_USB=y diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 269162eabf..ced2bab2b5 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -31,8 +31,6 @@ "ubifsload ${fit_addr_r} /boot/system.itb; " \ "imi ${fit_addr_r}\0 "
-#define CONFIG_GPIO_ENABLE_SPI_FLASH IMX_GPIO_NR(2, 15) - /* Framebuffer */ #define CONFIG_SYS_LDB_CLOCK 33246000 #define CONFIG_LG4573 diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt index c8e5eebe00..7a925187fe 100644 --- a/scripts/config_whitelist.txt +++ b/scripts/config_whitelist.txt @@ -653,7 +653,6 @@ CONFIG_GLOBAL_DATA_NOT_REG10 CONFIG_GLOBAL_TIMER CONFIG_GMII CONFIG_GPCNTRL -CONFIG_GPIO_ENABLE_SPI_FLASH CONFIG_GPIO_LED_INVERTED_TABLE CONFIG_GPIO_LED_STUBS CONFIG_GREEN_LED
enable CONFIG_DM_SPI and CONFIG_DM_SPI_FLASH and get rid of build removal warnings. define CONFIG_GPIO_ENABLE_SPI_FLASH is not longer needed, so remove it from config_whitelist.txt Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
enable DM_ETH and remove unneeded board code.
Signed-off-by: Heiko Schocher hs@denx.de ---
board/aristainetos/aristainetos.c | 35 +------------------------------ configs/aristainetos2_defconfig | 2 ++ 2 files changed, 3 insertions(+), 34 deletions(-)
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 5bb238b073..f08f09e17f 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -19,8 +19,6 @@ #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/mxc_i2c.h> #include <asm/mach-imx/video.h> -#include <miiphy.h> -#include <netdev.h> #include <asm/arch/mxc_hdmi.h> #include <asm/arch/crm_regs.h> #include <linux/fb.h> @@ -32,6 +30,7 @@ #include <dm/root.h> #include <env.h> #include <micrel.h> +#include <miiphy.h> #include <video.h> #include <../drivers/video/imx/ipu.h> #if defined(CONFIG_VIDEO_BMP_LOGO) @@ -41,9 +40,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#define ENET_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS) - #define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ PAD_CTL_ODE | PAD_CTL_SRE_FAST) @@ -86,24 +82,6 @@ struct i2c_pads_info i2c_pad_info4 = { } };
-iomux_v3_cfg_t const enet_pads[] = { - MX6_PAD_ENET_MDIO__ENET_MDIO | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_MDC__ENET_MDC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TXC__RGMII_TXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD0__RGMII_TD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD1__RGMII_TD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD2__RGMII_TD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TD3__RGMII_TD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_TX_CTL__RGMII_TX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_ENET_REF_CLK__ENET_TX_CLK | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RXC__RGMII_RXC | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD0__RGMII_RD0 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD1__RGMII_RD1 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD2__RGMII_RD2 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RD3__RGMII_RD3 | MUX_PAD_CTRL(ENET_PAD_CTRL), - MX6_PAD_RGMII_RX_CTL__RGMII_RX_CTL | MUX_PAD_CTRL(ENET_PAD_CTRL), -}; - static iomux_v3_cfg_t const backlight_pads[] = { /* backlight PWM brightness control */ MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -113,11 +91,6 @@ static iomux_v3_cfg_t const backlight_pads[] = { MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), };
-static void setup_iomux_enet(void) -{ - imx_iomux_v3_setup_multiple_pads(enet_pads, ARRAY_SIZE(enet_pads)); -} - static iomux_v3_cfg_t const display_pads[] = { MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL), MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, @@ -174,12 +147,6 @@ int board_phy_config(struct phy_device *phydev) return 0; }
-int board_eth_init(bd_t *bis) -{ - setup_iomux_enet(); - return cpu_eth_init(bis); -} - static int rotate_logo_one(unsigned char *out, unsigned char *in) { int i, j; diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index d89b99b53d..47d1efca56 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -76,7 +76,9 @@ CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 CONFIG_PHYLIB=y CONFIG_PHY_MICREL=y CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y CONFIG_MII=y +CONFIG_PHY=y CONFIG_PINCTRL=y CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y
enable DM_ETH and remove unneeded board code. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
add DM_VIDEO support and remove now unneeded board code. As we show a bmp logo on boot, call now bmp_display() from board code and do not use cfb_console anymore.
Signed-off-by: Heiko Schocher hs@denx.de ---
board/aristainetos/aristainetos.c | 111 ++++-------------------------- configs/aristainetos2_defconfig | 5 +- include/configs/aristainetos2.h | 9 ++- 3 files changed, 19 insertions(+), 106 deletions(-)
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index f08f09e17f..8d07edd3e0 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -19,24 +19,19 @@ #include <asm/mach-imx/boot_mode.h> #include <asm/mach-imx/mxc_i2c.h> #include <asm/mach-imx/video.h> -#include <asm/arch/mxc_hdmi.h> #include <asm/arch/crm_regs.h> -#include <linux/fb.h> -#include <ipu_pixfmt.h> -#include <input.h> #include <asm/io.h> #include <asm/arch/sys_proto.h> +#include <bmp_logo.h> #include <pwm.h> #include <dm/root.h> #include <env.h> #include <micrel.h> #include <miiphy.h> -#include <video.h> -#include <../drivers/video/imx/ipu.h> -#if defined(CONFIG_VIDEO_BMP_LOGO) - #include <bmp_logo.h> -#endif +#include <lcd.h> #include <led.h> +#include <splash.h> +#include <video_fb.h>
DECLARE_GLOBAL_DATA_PTR;
@@ -46,8 +41,6 @@ DECLARE_GLOBAL_DATA_PTR;
#define PC MUX_PAD_CTRL(I2C_PAD_CTRL)
-#define DISP_PAD_CTRL (0x10) - enum { BOARD_TYPE_4 = 4, BOARD_TYPE_7 = 7, @@ -91,37 +84,6 @@ static iomux_v3_cfg_t const backlight_pads[] = { MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), };
-static iomux_v3_cfg_t const display_pads[] = { - MX6_PAD_DI0_DISP_CLK__IPU1_DI0_DISP_CLK | MUX_PAD_CTRL(DISP_PAD_CTRL), - MX6_PAD_DI0_PIN15__IPU1_DI0_PIN15, - MX6_PAD_DI0_PIN2__IPU1_DI0_PIN02, - MX6_PAD_DI0_PIN3__IPU1_DI0_PIN03, - MX6_PAD_DISP0_DAT0__IPU1_DISP0_DATA00, - MX6_PAD_DISP0_DAT1__IPU1_DISP0_DATA01, - MX6_PAD_DISP0_DAT2__IPU1_DISP0_DATA02, - MX6_PAD_DISP0_DAT3__IPU1_DISP0_DATA03, - MX6_PAD_DISP0_DAT4__IPU1_DISP0_DATA04, - MX6_PAD_DISP0_DAT5__IPU1_DISP0_DATA05, - MX6_PAD_DISP0_DAT6__IPU1_DISP0_DATA06, - MX6_PAD_DISP0_DAT7__IPU1_DISP0_DATA07, - MX6_PAD_DISP0_DAT8__IPU1_DISP0_DATA08, - MX6_PAD_DISP0_DAT9__IPU1_DISP0_DATA09, - MX6_PAD_DISP0_DAT10__IPU1_DISP0_DATA10, - MX6_PAD_DISP0_DAT11__IPU1_DISP0_DATA11, - MX6_PAD_DISP0_DAT12__IPU1_DISP0_DATA12, - MX6_PAD_DISP0_DAT13__IPU1_DISP0_DATA13, - MX6_PAD_DISP0_DAT14__IPU1_DISP0_DATA14, - MX6_PAD_DISP0_DAT15__IPU1_DISP0_DATA15, - MX6_PAD_DISP0_DAT16__IPU1_DISP0_DATA16, - MX6_PAD_DISP0_DAT17__IPU1_DISP0_DATA17, - MX6_PAD_DISP0_DAT18__IPU1_DISP0_DATA18, - MX6_PAD_DISP0_DAT19__IPU1_DISP0_DATA19, - MX6_PAD_DISP0_DAT20__IPU1_DISP0_DATA20, - MX6_PAD_DISP0_DAT21__IPU1_DISP0_DATA21, - MX6_PAD_DISP0_DAT22__IPU1_DISP0_DATA22, - MX6_PAD_DISP0_DAT23__IPU1_DISP0_DATA23, -}; - int board_phy_config(struct phy_device *phydev) { /* control data pad skew - devaddr = 0x02, register = 0x04 */ @@ -166,13 +128,15 @@ static int rotate_logo_one(unsigned char *out, unsigned char *in) void rotate_logo(int rotations) { unsigned char out_logo[BMP_LOGO_WIDTH * BMP_LOGO_HEIGHT]; + struct bmp_header *header; unsigned char *in_logo; int i, j;
if (BMP_LOGO_WIDTH != BMP_LOGO_HEIGHT) return;
- in_logo = bmp_logo_bitmap; + header = (struct bmp_header *)bmp_logo_bitmap; + in_logo = bmp_logo_bitmap + header->data_offset;
/* one 90 degree rotation */ if (rotations == 1 || rotations == 2 || rotations == 3) @@ -194,34 +158,6 @@ void rotate_logo(int rotations) out_logo[i * BMP_LOGO_WIDTH + j]; }
-static void enable_display_power(void) -{ - imx_iomux_v3_setup_multiple_pads(backlight_pads, - ARRAY_SIZE(backlight_pads)); - - /* backlight enable */ - gpio_request(IMX_GPIO_NR(6, 31), "backlight"); - gpio_direction_output(IMX_GPIO_NR(6, 31), 1); - gpio_free(IMX_GPIO_NR(6, 31)); - /* LCD power enable */ - gpio_request(IMX_GPIO_NR(6, 15), "LCD_power_enable"); - gpio_direction_output(IMX_GPIO_NR(6, 15), 1); - gpio_free(IMX_GPIO_NR(6, 15)); - - /* enable backlight PWM 1 */ - if (pwm_init(0, 0, 0)) - goto error; - /* duty cycle 500ns, period: 3000ns */ - if (pwm_config(0, 50000, 300000)) - goto error; - if (pwm_enable(0)) - goto error; - return; - -error: - puts("error init pwm for backlight\n"); -} - static void enable_lvds(struct display_info_t const *dev) { struct iomuxc *iomux = (struct iomuxc *)IOMUXC_BASE_ADDR; @@ -304,15 +240,6 @@ static void enable_spi_display(struct display_info_t const *dev) rotate_logo(3); /* portrait display in landscape mode */ #endif
- /* - * set ldb clock to 28341000 Hz calculated through the formula: - * (XRES + LEFT_M + RIGHT_M + HSYNC_LEN) * - * (YRES + UPPER_M + LOWER_M + VSYNC_LEN) * REFRESH) - * see: - * https://community.freescale.com/thread/308170 - */ - ipu_set_ldb_clock(28341000); - reg = readl(&ccm->cs2cdr);
/* select pll 5 clock */ @@ -381,15 +308,11 @@ static void enable_spi_display(struct display_info_t const *dev) | (IOMUXC_GPR3_MUX_SRC_IPU1_DI0 << IOMUXC_GPR3_LVDS0_MUX_CTL_OFFSET); writel(reg, &iomux->gpr[3]); - - imx_iomux_v3_setup_multiple_pads(display_pads, - ARRAY_SIZE(display_pads)); }
static void setup_display(void) { enable_ipu_clock(); - enable_display_power(); }
static void set_gpr_register(void) @@ -410,7 +333,7 @@ static void set_gpr_register(void) extern char __bss_start[], __bss_end[]; int board_early_init_f(void) { - setup_display(); + select_ldb_di_clock_source(MXC_PLL5_CLK); set_gpr_register();
/* @@ -453,11 +376,13 @@ int board_late_init(void) { char *my_bootdelay; char bootmode = 0; - char const *panel = env_get("panel"); struct gpio_desc *desc; + int x, y; int ret;
led_default_state(); + splash_get_pos(&x, &y); + bmp_display((ulong)&bmp_logo_bitmap[0], x, y); /* * Check the boot-source. If booting from NOR Flash, * disable bootdelay @@ -496,13 +421,6 @@ int board_late_init(void) } }
- /* if we have the lg panel, we can initialze it now */ - if (panel) - if (!strcmp(panel, displays[1].mode.name)) - lg4573_spi_startup(CONFIG_LG4573_BUS, - CONFIG_LG4573_CS, - 10000000, SPI_MODE_0); - /* set board_type */ if (gd->board_type == BOARD_TYPE_4) env_set("board_type", ARI_BT_4); @@ -596,12 +514,6 @@ struct display_info_t const displays[] = { }; size_t display_count = ARRAY_SIZE(displays);
-/* no console on this board */ -int board_cfb_skip(void) -{ - return 1; -} - iomux_v3_cfg_t nfc_pads[] = { MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -673,6 +585,7 @@ int board_init(void)
setup_board_gpio(); setup_gpmi_nand(); + setup_display();
/* GPIO_1 for USB_OTG_ID */ clrsetbits_le32(&iomux->gpr[1], IOMUXC_GPR1_USB_OTG_ID_SEL_MASK, 0); diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 47d1efca56..d33eba7b8f 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -92,8 +92,9 @@ CONFIG_MXC_SPI=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_DISPLAY=y CONFIG_VIDEO_IPUV3=y -CONFIG_VIDEO=y -# CONFIG_VIDEO_SW_CURSOR is not set CONFIG_IMX_WATCHDOG=y # CONFIG_EFI_LOADER is not set diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index ced2bab2b5..45699dc614 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -32,7 +32,7 @@ "imi ${fit_addr_r}\0 "
/* Framebuffer */ -#define CONFIG_SYS_LDB_CLOCK 33246000 +#define CONFIG_SYS_LDB_CLOCK 28341000 #define CONFIG_LG4573
#include "mx6_common.h" @@ -193,15 +193,14 @@
/* Framebuffer */ /* check this console not needed, after test remove it */ -#define CONFIG_VIDEO_BMP_RLE8 #define CONFIG_SPLASH_SCREEN #define CONFIG_SPLASH_SCREEN_ALIGN -#define CONFIG_BMP_16BPP +#define CONFIG_IMX_VIDEO_SKIP #define CONFIG_VIDEO_LOGO #define CONFIG_VIDEO_BMP_LOGO -#define CONFIG_IMX_VIDEO_SKIP +#define CONFIG_BMP_16BPP +#define CONFIG_VIDEO_BMP_RLE8
#define CONFIG_IMX6_PWM_PER_CLK 66000000
- #endif /* __ARISTAINETOS2_CONFIG_H */
add DM_VIDEO support and remove now unneeded board code. As we show a bmp logo on boot, call now bmp_display() from board code and do not use cfb_console anymore. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
enable DM_I2C in defconfig and remove i2c specific board code.
Signed-off-by: Heiko Schocher hs@denx.de ---
board/aristainetos/aristainetos.c | 73 ------------------------------- configs/aristainetos2_defconfig | 6 ++- include/configs/aristainetos2.h | 11 ----- 3 files changed, 5 insertions(+), 85 deletions(-)
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 8d07edd3e0..0d1c06da5d 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -17,7 +17,6 @@ #include <asm/gpio.h> #include <asm/mach-imx/iomux-v3.h> #include <asm/mach-imx/boot_mode.h> -#include <asm/mach-imx/mxc_i2c.h> #include <asm/mach-imx/video.h> #include <asm/arch/crm_regs.h> #include <asm/io.h> @@ -35,12 +34,6 @@
DECLARE_GLOBAL_DATA_PTR;
-#define I2C_PAD_CTRL (PAD_CTL_PUS_100K_UP | \ - PAD_CTL_SPEED_MED | PAD_CTL_DSE_40ohm | PAD_CTL_HYS | \ - PAD_CTL_ODE | PAD_CTL_SRE_FAST) - -#define PC MUX_PAD_CTRL(I2C_PAD_CTRL) - enum { BOARD_TYPE_4 = 4, BOARD_TYPE_7 = 7, @@ -49,32 +42,6 @@ enum { #define ARI_BT_4 "aristainetos2_4@2" #define ARI_BT_7 "aristainetos2_7@1"
-struct i2c_pads_info i2c_pad_info3 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_5__I2C3_SCL | PC, - .gpio_mode = MX6_PAD_GPIO_5__GPIO1_IO05 | PC, - .gp = IMX_GPIO_NR(1, 5) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_6__I2C3_SDA | PC, - .gpio_mode = MX6_PAD_GPIO_6__GPIO1_IO06 | PC, - .gp = IMX_GPIO_NR(1, 6) - } -}; - -struct i2c_pads_info i2c_pad_info4 = { - .scl = { - .i2c_mode = MX6_PAD_GPIO_7__I2C4_SCL | PC, - .gpio_mode = MX6_PAD_GPIO_7__GPIO1_IO07 | PC, - .gp = IMX_GPIO_NR(1, 7) - }, - .sda = { - .i2c_mode = MX6_PAD_GPIO_8__I2C4_SDA | PC, - .gpio_mode = MX6_PAD_GPIO_8__GPIO1_IO08 | PC, - .gp = IMX_GPIO_NR(1, 8) - } -}; - static iomux_v3_cfg_t const backlight_pads[] = { /* backlight PWM brightness control */ MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -346,12 +313,6 @@ int board_early_init_f(void) return 0; }
-static void setup_i2c4(void) -{ - setup_i2c(3, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, - &i2c_pad_info4); -} - static void setup_one_led(char *label, int state) { struct udevice *dev; @@ -430,32 +391,6 @@ int board_late_init(void) return 0; }
-struct i2c_pads_info i2c_pad_info1 = { - .scl = { - .i2c_mode = MX6_PAD_CSI0_DAT9__I2C1_SCL | PC, - .gpio_mode = MX6_PAD_CSI0_DAT9__GPIO5_IO27 | PC, - .gp = IMX_GPIO_NR(5, 27) - }, - .sda = { - .i2c_mode = MX6_PAD_CSI0_DAT8__I2C1_SDA | PC, - .gpio_mode = MX6_PAD_CSI0_DAT8__GPIO5_IO26 | PC, - .gp = IMX_GPIO_NR(5, 26) - } -}; - -struct i2c_pads_info i2c_pad_info2 = { - .scl = { - .i2c_mode = MX6_PAD_KEY_COL3__I2C2_SCL | PC, - .gpio_mode = MX6_PAD_KEY_COL3__GPIO4_IO12 | PC, - .gp = IMX_GPIO_NR(4, 12) - }, - .sda = { - .i2c_mode = MX6_PAD_KEY_ROW3__I2C2_SDA | PC, - .gpio_mode = MX6_PAD_KEY_ROW3__GPIO4_IO13 | PC, - .gp = IMX_GPIO_NR(4, 13) - } -}; - int dram_init(void) { gd->ram_size = imx_ddr_size(); @@ -575,14 +510,6 @@ int board_init(void) /* address of boot parameters */ gd->bd->bi_boot_params = PHYS_SDRAM + 0x100;
- setup_i2c(0, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, - &i2c_pad_info1); - setup_i2c(1, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, - &i2c_pad_info2); - setup_i2c(2, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE, - &i2c_pad_info3); - setup_i2c4(); - setup_board_gpio(); setup_gpmi_nand(); setup_display(); diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index d33eba7b8f..07bdc006df 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -36,7 +36,6 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y -CONFIG_CMD_DATE=y CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y @@ -57,8 +56,11 @@ CONFIG_SYS_RELOC_GD_ENV_ADDR=y CONFIG_DM_GPIO=y CONFIG_GPIO_HOG=y CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y CONFIG_LED=y CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y CONFIG_DM_MMC=y CONFIG_FSL_USDHC=y CONFIG_MTD=y @@ -85,6 +87,8 @@ CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y CONFIG_PWM_IMX=y +CONFIG_DM_RTC=y +CONFIG_RTC_DS1307=y CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 45699dc614..1999c5c616 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -165,12 +165,6 @@
#define CONFIG_SYS_FSL_USDHC_NUM 2
-/* I2C */ -#define CONFIG_SYS_I2C -#define CONFIG_SYS_I2C_SPEED 100000 -#define CONFIG_SYS_I2C_SLAVE 0x7f -#define CONFIG_SYS_I2C_NOPROBES { {0, 0x00} } - /* NAND stuff */ #define CONFIG_SYS_MAX_NAND_DEVICE 1 #define CONFIG_SYS_NAND_BASE 0x40000000 @@ -179,11 +173,6 @@
/* DMA stuff, needed for GPMI/MXS NAND support */
-/* RTC */ -#define CONFIG_SYS_I2C_RTC_ADDR 0x68 -#define CONFIG_SYS_RTC_BUS_NUM 2 -#define CONFIG_RTC_M41T11 - /* USB Configs */ #define CONFIG_EHCI_HCD_INIT_AFTER_RESET /* For OTG port */ #define CONFIG_MXC_USB_PORTSC (PORT_PTS_UTMI | PORT_PTS_PTW)
enable DM_I2C in defconfig and remove i2c specific board code. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
use DM_PWM and DM_BLACKLIGHT support and remove board code.
Signed-off-by: Heiko Schocher hs@denx.de ---
board/aristainetos/aristainetos.c | 10 ---------- configs/aristainetos2_defconfig | 1 + 2 files changed, 1 insertion(+), 10 deletions(-)
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 0d1c06da5d..edaec5ee87 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -22,7 +22,6 @@ #include <asm/io.h> #include <asm/arch/sys_proto.h> #include <bmp_logo.h> -#include <pwm.h> #include <dm/root.h> #include <env.h> #include <micrel.h> @@ -42,15 +41,6 @@ enum { #define ARI_BT_4 "aristainetos2_4@2" #define ARI_BT_7 "aristainetos2_7@1"
-static iomux_v3_cfg_t const backlight_pads[] = { - /* backlight PWM brightness control */ - MX6_PAD_GPIO_9__PWM1_OUT | MUX_PAD_CTRL(NO_PAD_CTRL), - /* backlight enable */ - MX6_PAD_EIM_BCLK__GPIO6_IO31 | MUX_PAD_CTRL(NO_PAD_CTRL), - /* LCD power enable */ - MX6_PAD_NANDF_CS2__GPIO6_IO15 | MUX_PAD_CTRL(NO_PAD_CTRL), -}; - int board_phy_config(struct phy_device *phydev) { /* control data pad skew - devaddr = 0x02, register = 0x04 */ diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 07bdc006df..c7416a936a 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -86,6 +86,7 @@ CONFIG_PINCTRL_IMX6=y CONFIG_DM_PMIC=y CONFIG_DM_REGULATOR=y CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_PWM=y CONFIG_PWM_IMX=y CONFIG_DM_RTC=y CONFIG_RTC_DS1307=y
use DM_PWM and DM_BLACKLIGHT support and remove board code. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
CONFIG_BOARDNAME is not longer needed, as we use the model information from DTS.
Signed-off-by: Heiko Schocher hs@denx.de ---
board/aristainetos/Kconfig | 3 --- board/aristainetos/aristainetos.c | 6 ------ board/aristainetos/common/Kconfig | 5 ----- 3 files changed, 14 deletions(-)
diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig index 2bb12fce75..6700f517f1 100644 --- a/board/aristainetos/Kconfig +++ b/board/aristainetos/Kconfig @@ -8,7 +8,4 @@ config SYS_BOARD config SYS_BOARD_VERSION default 2
-config BOARDNAME - default "aristainetos2" - endif diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index edaec5ee87..846a99804a 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -509,12 +509,6 @@ int board_init(void) return 0; }
-int checkboard(void) -{ - printf("Board: %s\n", CONFIG_BOARDNAME); - return 0; -} - int board_fit_config_name_match(const char *name) { if (gd->board_type == BOARD_TYPE_4 && diff --git a/board/aristainetos/common/Kconfig b/board/aristainetos/common/Kconfig index 16c1325889..8f2561415b 100644 --- a/board/aristainetos/common/Kconfig +++ b/board/aristainetos/common/Kconfig @@ -1,8 +1,3 @@ -config BOARDNAME - string "name of the board" - help - set the name of the board. - config SYS_BOARD_VERSION int "select version of aristainetos board" help
CONFIG_BOARDNAME is not longer needed, as we use the model information from DTS. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
add support for i2c eeprom and add parsing "Rescue" or "DefEnv" at offset 0x1ff0.
Signed-off-by: Heiko Schocher hs@denx.de ---
board/aristainetos/aristainetos.c | 64 ++++++++++++++++++++++++++++++- 1 file changed, 63 insertions(+), 1 deletion(-)
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 846a99804a..55d3ab6f44 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -24,6 +24,8 @@ #include <bmp_logo.h> #include <dm/root.h> #include <env.h> +#include <i2c_eeprom.h> +#include <i2c.h> #include <micrel.h> #include <miiphy.h> #include <lcd.h> @@ -323,6 +325,64 @@ static void setup_board_gpio(void) setup_one_led("led_blue", LEDST_OFF); }
+#define ARI_RESC_FMT "setenv rescue_reason setenv bootargs \${bootargs}" \ + " rescueReason=%d " + +static void aristainetos_run_rescue_command(int reason) +{ + char rescue_reason_command[80]; + + sprintf(rescue_reason_command, ARI_RESC_FMT, reason); + run_command(rescue_reason_command, 0); +} + +static int aristainetos_eeprom(void) +{ + struct udevice *dev; + int off; + int ret; + u8 data[0x10]; + u8 rescue_reason; + + off = fdt_path_offset(gd->fdt_blob, "eeprom0"); + if (off < 0) { + printf("%s: No eeprom0 path offset\n", __func__); + return off; + } + + ret = uclass_get_device_by_of_offset(UCLASS_I2C_EEPROM, off, &dev); + if (ret) { + printf("%s: Could not find EEPROM\n", __func__); + return ret; + } + + ret = i2c_set_chip_offset_len(dev, 2); + if (ret) + return ret; + + ret = i2c_eeprom_read(dev, 0x1ff0, (uint8_t *)data, 6); + if (ret) { + printf("%s: Could not read EEPROM\n", __func__); + return ret; + } + + if (strncmp((char *)&data[3], "ReScUe", 6) == 0) { + rescue_reason = *(uint8_t *)&data[9]; + memset(&data[3], 0xff, 7); + i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)&data[3], 7); + printf("\nBooting into Rescue System (EEPROM)\n"); + aristainetos_run_rescue_command(rescue_reason); + run_command("run rescue_load_fit rescueboot", 0); + } else if (strncmp((char *)data, "DeF", 3) == 0) { + memset(data, 0xff, 3); + i2c_eeprom_write(dev, 0x1ff0, (uint8_t *)data, 3); + printf("\nClear u-boot environment (set back to defaults)\n"); + run_command("run default_env; saveenv; saveenv", 0); + } + + return 0; +}; + int board_late_init(void) { char *my_bootdelay; @@ -372,12 +432,14 @@ int board_late_init(void) } }
+ /* eeprom work */ + aristainetos_eeprom(); + /* set board_type */ if (gd->board_type == BOARD_TYPE_4) env_set("board_type", ARI_BT_4); else env_set("board_type", ARI_BT_7); - return 0; }
add support for i2c eeprom and add parsing "Rescue" or "DefEnv" at offset 0x1ff0. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
add stop autobooting via SHA256 encrypted password.
Signed-off-by: Heiko Schocher hs@denx.de ---
configs/aristainetos2_defconfig | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index c7416a936a..11b9f2ab1d 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -18,6 +18,9 @@ CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_TYPES=y CONFIG_BOARD_EARLY_INIT_F=y CONFIG_HUSH_PARSER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_ENCRYPTION=y +CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" CONFIG_CMD_BOOTZ=y # CONFIG_BOOTM_NETBSD is not set # CONFIG_BOOTM_PLAN9 is not set
add stop autobooting via SHA256 encrypted password. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
add VERSION_VARIABLE
Signed-off-by: Heiko Schocher hs@denx.de ---
configs/aristainetos2_defconfig | 1 + 1 file changed, 1 insertion(+)
diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 11b9f2ab1d..82fe512098 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -14,6 +14,7 @@ CONFIG_BOOTDELAY=3 # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_VERSION_VARIABLE=y CONFIG_BOUNCE_BUFFER=y CONFIG_BOARD_TYPES=y CONFIG_BOARD_EARLY_INIT_F=y
add VERSION_VARIABLE Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
on the aristainetos there are some jumpers for changing behaviour setting up Environment. Clean this up.
Signed-off-by: Heiko Schocher hs@denx.de ---
board/aristainetos/aristainetos.c | 43 +++++++++++++++++++++---------- 1 file changed, 30 insertions(+), 13 deletions(-)
diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 55d3ab6f44..ca6155947b 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -383,39 +383,44 @@ static int aristainetos_eeprom(void) return 0; };
-int board_late_init(void) +static void aristainetos_bootmode_settings(void) { + struct gpio_desc *desc; + struct src *psrc = (struct src *)SRC_BASE_ADDR; + unsigned int sbmr1 = readl(&psrc->sbmr1); char *my_bootdelay; char bootmode = 0; - struct gpio_desc *desc; - int x, y; int ret;
- led_default_state(); - splash_get_pos(&x, &y); - bmp_display((ulong)&bmp_logo_bitmap[0], x, y); /* * Check the boot-source. If booting from NOR Flash, * disable bootdelay */ - desc = gpio_hog_lookup_name("bootsel0"); - if (desc) + ret = gpio_hog_lookup_name("bootsel0", &desc); + if (!ret) bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 0; - desc = gpio_hog_lookup_name("bootsel1"); - if (desc) + ret = gpio_hog_lookup_name("bootsel1", &desc); + if (!ret) bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 1; - desc = gpio_hog_lookup_name("bootsel2"); - if (desc) + ret = gpio_hog_lookup_name("bootsel2", &desc); + if (!ret) bootmode |= (dm_gpio_get_value(desc) ? 1 : 0) << 2;
if (bootmode == 7) { my_bootdelay = env_get("nor_bootdelay"); - if (my_bootdelay != NULL) + if (my_bootdelay) env_set("bootdelay", my_bootdelay); else env_set("bootdelay", "-2"); }
+ if (sbmr1 & 0x40) { + env_set("bootmode", "1"); + printf("SD bootmode jumper set!\n"); + } else { + env_set("bootmode", "0"); + } + /* read out some jumper values*/ ret = gpio_hog_lookup_name("env_reset", &desc); if (!ret) { @@ -431,6 +436,17 @@ int board_late_init(void) run_command("run rescue_xload_boot", 0); } } +} + +int board_late_init(void) +{ + int x, y; + + led_default_state(); + splash_get_pos(&x, &y); + bmp_display((ulong)&bmp_logo_bitmap[0], x, y); + + aristainetos_bootmode_settings();
/* eeprom work */ aristainetos_eeprom(); @@ -440,6 +456,7 @@ int board_late_init(void) env_set("board_type", ARI_BT_4); else env_set("board_type", ARI_BT_7); + return 0; }
on the aristainetos there are some jumpers for changing behaviour setting up Environment. Clean this up. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
enable config symbols: CONFIG_SYSRESET CONFIG_SYSRESET_WATCHDOG
Signed-off-by: Heiko Schocher hs@denx.de ---
configs/aristainetos2_defconfig | 2 ++ 1 file changed, 2 insertions(+)
diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 82fe512098..be5cec96fa 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -98,6 +98,8 @@ CONFIG_DM_SERIAL=y CONFIG_SPI=y CONFIG_DM_SPI=y CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y CONFIG_USB=y CONFIG_DM_USB=y CONFIG_USB_STORAGE=y
enable config symbols: CONFIG_SYSRESET CONFIG_SYSRESET_WATCHDOG Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
sync defaut Envoronment with customer changes. Unfortunately they are not changeable, as already board is in production mode.
Get rid of the big bootcommand and set bootcommand through Kconfig option.
Signed-off-by: Heiko Schocher hs@denx.de ---
configs/aristainetos2_defconfig | 2 + include/configs/aristainetos2.h | 248 +++++++++++++++++++++++++------- 2 files changed, 195 insertions(+), 55 deletions(-)
diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index be5cec96fa..7278ec9d13 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -11,6 +11,8 @@ CONFIG_ENV_SECT_SIZE=0x10000 CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run ari_boot" # CONFIG_CONSOLE_MUX is not set CONFIG_SYS_CONSOLE_IS_IN_ENV=y CONFIG_SUPPORT_RAW_INITRD=y diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 1999c5c616..fba26d0151 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -18,19 +18,6 @@
#define CONFIG_FEC_XCV_TYPE RGMII
-#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ - "board_type=aristainetos2_7@1\0" \ - "nor_bootdelay=-2\0" \ - "mtdids=nand0=gpmi-nand,nor0=spi3.1\0" \ - "mtdparts=mtdparts=spi3.1:832k(u-boot),64k(env),64k(env-red)," \ - "-(rescue-system);gpmi-nand:-(ubi)\0" \ - "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0\0" \ - "ubiargs=setenv bootargs console=${console},${baudrate} " \ - "ubi.mtd=0,4096 root=ubi0:rootfs rootfstype=ubifs\0 " \ - "ubifs_load_fit=sf probe;ubi part ubi 4096;ubifsmount ubi:rootfs;" \ - "ubifsload ${fit_addr_r} /boot/system.itb; " \ - "imi ${fit_addr_r}\0 " - /* Framebuffer */ #define CONFIG_SYS_LDB_CLOCK 28341000 #define CONFIG_LG4573 @@ -49,49 +36,87 @@
#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
+#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ + "dead=led led_red on\0" \ + "mtdids=nand0=gpmi-nand,nor0=spi3.1\0" \ + "mtdparts=mtdparts=spi3.1:832k(u-boot),64k(env),64k(env-red)," \ + "-(ubi-nor);gpmi-nand:-(ubi)\0" \ + "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ + "bootmode=${bootmode} mmcpart=${mmcpart}\0" \ + "mainboot=echo Booting from SD-card ...; " \ + "run mainargs addmtd addmisc;" \ + "if test -n ${addmiscM}; then run addmiscM;fi;" \ + "if test -n ${addmiscC}; then run addmiscC;fi;" \ + "if test -n ${addmiscD}; then run addmiscD;fi;" \ + "run boot_board_type;" \ + "bootm ${fit_addr_r}\0" \ + "mainargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "main_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ + "${fit_file}\0" \ + "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ + "${fit_addr_r} ${rescue_fit_file}\0" + #define CONFIG_EXTRA_ENV_SETTINGS \ "disable_giga=yes\0" \ + "usb_pgood_delay=2000\0" \ + "nor_bootdelay=-2\0" \ "script=u-boot.scr\0" \ "fit_file=/boot/system.itb\0" \ + "rescue_fit_file=/boot/rescue.itb\0" \ "loadaddr=0x12000000\0" \ "fit_addr_r=0x14000000\0" \ "uboot=/boot/u-boot.imx\0" \ "uboot_sz=d0000\0" \ - "rescue_sys_addr=f0000\0" \ - "rescue_sys_length=f10000\0" \ "panel=lb07wv8\0" \ "splashpos=m,m\0" \ "console=" CONSOLE_DEV "\0" \ "fdt_high=0xffffffff\0" \ "initrd_high=0xffffffff\0" \ "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ - "set_fit_default=fdt addr ${fit_addr_r};fdt set /configurations " \ - "default ${board_type}\0" \ + "boot_board_type=bootm ${fit_addr_r}#${board_type}\0" \ "get_env=mw ${loadaddr} 0 0x20000;" \ "mmc rescan;" \ - "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \ + "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} env.txt;" \ "env import -t ${loadaddr}\0" \ - "default_env=mw ${loadaddr} 0 0x20000;" \ - "env export -t ${loadaddr} serial# ethaddr eth1addr " \ - "board_type panel;" \ + "default_env=gpio set wp_spi_nor.gpio-hog;" \ + "sf probe;" \ + "sf protect unlock 0 0x1000000;" \ + "mw ${loadaddr} 0 0x20000;" \ + "env export -t ${loadaddr} serial# ethaddr " \ + "board_type panel addmisc addmiscM addmiscC addmiscD;" \ "env default -a;" \ "env import -t ${loadaddr}\0" \ "loadbootscript=" \ - "ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} ${script};\0" \ + "ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "${script};\0" \ + "loadbootscriptUSB=" \ + "ext4load usb 0 ${loadaddr} ${script};\0" \ + "loadbootscriptUSBf=" \ + "fatload usb 0 ${loadaddr} ${script};\0" \ + "bootscriptUSB=echo Running bootscript from usb-stick ...; " \ + "source\0" \ "bootscript=echo Running bootscript from mmc ...; " \ "source\0" \ "mmcpart=1\0" \ + "mmcrescuepart=3\0" \ "mmcdev=0\0" \ "mmcroot=" CONFIG_MMCROOT " rootwait rw\0" \ "mmcargs=setenv bootargs console=${console},${baudrate} " \ "root=${mmcroot}\0" \ "mmcboot=echo Booting from mmc ...; " \ - "run mmcargs addmtd addmisc set_fit_default;" \ + "run mmcargs addmtd addmisc;" \ + "if test -n ${addmiscM}; then run addmiscM;fi;" \ + "if test -n ${addmiscC}; then run addmiscC;fi;" \ + "if test -n ${addmiscD}; then run addmiscD;fi;" \ + "run boot_board_type;" \ "bootm ${fit_addr_r}\0" \ - "mmc_load_fit=ext2load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ + "mmc_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ "${fit_file}\0" \ - "mmc_load_uboot=ext2load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ + "mmc_load_uboot=ext4load mmc ${mmcdev}:${mmcpart} ${loadaddr} " \ "${uboot}\0" \ + "mmc_rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ + "${fit_addr_r} ${rescue_fit_file}\0" \ "mmc_upd_uboot=mw.b ${loadaddr} 0xff ${uboot_sz};" \ "setexpr cmp_buf ${loadaddr} + ${uboot_sz};" \ "setexpr uboot_maxsize ${uboot_sz} - 400;" \ @@ -100,50 +125,163 @@ "sf write ${loadaddr} 400 ${filesize};" \ "sf read ${cmp_buf} 400 ${uboot_sz};" \ "cmp.b ${loadaddr} ${cmp_buf} ${uboot_maxsize}\0" \ - "ubiboot=echo Booting from ubi ...; " \ - "run ubiargs addmtd addmisc set_fit_default;" \ - "bootm ${fit_addr_r}\0" \ "rescueargs=setenv bootargs console=${console},${baudrate} " \ "root=/dev/ram rw\0 " \ - "rescueboot=echo Booting rescue system from NOR ...; " \ - "run rescueargs addmtd addmisc set_fit_default;" \ + "rescueboot=echo Booting rescue system ...; " \ + "run rescueargs addmtd addmisc;" \ + "if test -n ${rescue_reason}; then run rescue_reason;fi;" \ + "if test -n ${addmiscM}; then run addmiscM;fi;" \ + "if test -n ${addmiscC}; then run addmiscC;fi;" \ + "if test -n ${addmiscD}; then run addmiscD;fi;" \ + "run boot_board_type;" \ + "if bootm ${fit_addr_r}; then ; " \ + "else " \ + "run dead; " \ + "fi; \0" \ + "r_reason_syserr=setenv rescue_reason setenv bootargs " \ + "\\${bootargs} " \ + "rescueReason=18\0 " \ + "usb_load_fit=ext4load usb 0 ${fit_addr_r} ${fit_file}\0" \ + "usb_load_fitf=fatload usb 0 ${fit_addr_r} ${fit_file}\0" \ + "usb_load_rescuefit=ext4load usb 0 ${fit_addr_r} " \ + "${rescue_fit_file}\0" \ + "usb_load_rescuefitf=fatload usb 0 ${fit_addr_r} " \ + "${rescue_fit_file}\0" \ + "usbroot=/dev/sda1 rootwait rw\0" \ + "usbboot=echo Booting from usb-stick ...; " \ + "run usbargs addmtd addmisc;" \ + "if test -n ${addmiscM}; then run addmiscM;fi;" \ + "if test -n ${addmiscC}; then run addmiscC;fi;" \ + "if test -n ${addmiscD}; then run addmiscD;fi;" \ + "run boot_board_type;" \ "bootm ${fit_addr_r}\0" \ - "rescue_load_fit=sf probe;sf read ${fit_addr_r} ${rescue_sys_addr} " \ - "${rescue_sys_length}; imi ${fit_addr_r}\0" \ - CONFIG_EXTRA_ENV_BOARD_SETTINGS - -#define CONFIG_BOOTCOMMAND \ - "mmc dev ${mmcdev};" \ - "if mmc rescan; then " \ - "if run loadbootscript; then " \ - "run bootscript; " \ + "usbargs=setenv bootargs console=${console},${baudrate} " \ + "root=${usbroot}\0" \ + "mmc_rescue_boot=" \ + "run r_reason_syserr;" \ + "if run mmc_rescue_load_fit hab_check_file_fit; then " \ + "run rescueboot; " \ "else " \ - "if run mmc_load_fit; then " \ - "run mmcboot; " \ + "run dead; " \ + "echo RESCUE SYSTEM FROM SD-CARD BOOT FAILURE;" \ + "fi;\0" \ + "main_rescue_boot=" \ + "if run main_load_fit hab_check_flash_fit; then " \ + "if run mainboot; then ; " \ "else " \ - "if run ubifs_load_fit; then " \ - "run ubiboot; " \ + "run r_reason_syserr;" \ + "if run rescue_load_fit hab_check_file_fit;" \ + "then run rescueboot; " \ "else " \ - "if run rescue_load_fit; then " \ - "run rescueboot; " \ - "else " \ - "echo RESCUE SYSTEM BOOT " \ - "FAILURE;" \ - "fi; " \ + "run dead; " \ + "echo RESCUE SYSTEM BOOT FAILURE;" \ "fi; " \ "fi; " \ - "fi; " \ - "else " \ - "if run ubifs_load_fit; then " \ - "run ubiboot; " \ "else " \ - "if run rescue_load_fit; then " \ + "run r_reason_syserr;" \ + "if run rescue_load_fit hab_check_file_fit; then " \ "run rescueboot; " \ "else " \ + "run dead; " \ "echo RESCUE SYSTEM BOOT FAILURE;" \ "fi; " \ + "fi;\0" \ + "usb_mmc_rescue_boot=" \ + "usb start;" \ + "if usb storage; then " \ + "if run loadbootscriptUSB " \ + "hab_check_file_bootscript;" \ + "then run bootscriptUSB; " \ + "fi; " \ + "if run loadbootscriptUSBf " \ + "hab_check_file_bootscript;" \ + "then run bootscriptUSB; " \ + "fi; " \ + "if run usb_load_fit hab_check_file_fit; then " \ + "run usbboot; " \ + "fi; " \ + "if run usb_load_fitf hab_check_file_fit; then " \ + "run usbboot; " \ + "fi; "\ + "if run usb_load_rescuefit hab_check_file_fit;" \ + "then run r_reason_syserr rescueboot;" \ + "fi; " \ + "if run usb_load_rescuefitf hab_check_file_fit;" \ + "then run r_reason_syserr rescueboot;" \ + "fi; " \ + "run mmc_rescue_boot;" \ + "fi; "\ + "run mmc_rescue_boot;\0" \ + "rescue_xload_boot=" \ + "run r_reason_syserr;" \ + "if test ${bootmode} -ne 0 ; then " \ + "mmc dev ${mmcdev};" \ + "if mmc rescan; then " \ + "if run mmc_rescue_load_fit " \ + "hab_check_file_fit; then " \ + "run rescueboot; " \ + "else " \ + "usb start;" \ + "if usb storage; then " \ + "if run usb_load_rescuefit " \ + "hab_check_file_fit;"\ + "then " \ + "run rescueboot;" \ + "fi; " \ + "if run usb_load_rescuefitf "\ + "hab_check_file_fit;"\ + "then " \ + "run rescueboot;" \ + "fi; " \ + "fi;" \ + "fi;" \ + "run dead; " \ + "echo RESCUE SYSTEM ON SD OR " \ + "USB BOOT FAILURE;" \ + "else " \ + "usb start;" \ + "if usb storage; then " \ + "if run usb_load_rescuefit " \ + "hab_check_file_fit; then " \ + "run rescueboot;" \ + "fi; " \ + "if run usb_load_rescuefitf " \ + "hab_check_file_fit; then " \ + "run rescueboot;" \ + "fi; " \ + "fi;" \ + "run dead; " \ + "echo RESCUE SYSTEM ON USB BOOT FAILURE;" \ + "fi; " \ + "else "\ + "if run rescue_load_fit hab_check_file_fit; then " \ + "run rescueboot; " \ + "else " \ + "run dead; " \ + "echo RESCUE SYSTEM ON BOARD BOOT FAILURE;" \ + "fi; " \ + "fi;\0" \ + "ari_boot=if test ${bootmode} -ne 0 ; then " \ + "mmc dev ${mmcdev};" \ + "if mmc rescan; then " \ + "if run loadbootscript hab_check_file_bootscript;" \ + "then run bootscript; " \ + "fi; " \ + "if run mmc_load_fit hab_check_file_fit; then " \ + "if run mmcboot; then ; " \ + "else " \ + "run mmc_rescue_boot;" \ + "fi; " \ + "else " \ + "run usb_mmc_rescue_boot;" \ + "fi; " \ + "else " \ + "run usb_mmc_rescue_boot;" \ "fi; " \ - "fi" + "else "\ + "run main_rescue_boot;" \ + "fi; \0"\ + CONFIG_EXTRA_ENV_BOARD_SETTINGS
#define CONFIG_ARP_TIMEOUT 200UL
sync defaut Envoronment with customer changes. Unfortunately they are not changeable, as already board is in production mode. Get rid of the big bootcommand and set bootcommand through Kconfig option. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
enable IMX_HAB on aristianetos board
Signed-off-by: Heiko Schocher hs@denx.de ---
board/aristainetos/aristainetos2.cfg | 3 ++ configs/aristainetos2_defconfig | 4 +++ include/configs/aristainetos2.h | 51 ++++++++++++++++++++++++++++ 3 files changed, 58 insertions(+)
diff --git a/board/aristainetos/aristainetos2.cfg b/board/aristainetos/aristainetos2.cfg index fbbc2e5e6d..965ad64b49 100644 --- a/board/aristainetos/aristainetos2.cfg +++ b/board/aristainetos/aristainetos2.cfg @@ -23,6 +23,9 @@ BOOT_FROM spi
#define __ASSEMBLY__ #include <config.h> +#ifdef CONFIG_IMX_HAB +CSF CONFIG_CSF_SIZE +#endif #include "asm/arch/mx6-ddr.h" #include "asm/arch/iomux.h" #include "asm/arch/crm_regs.h" diff --git a/configs/aristainetos2_defconfig b/configs/aristainetos2_defconfig index 7278ec9d13..6c01eb6fff 100644 --- a/configs/aristainetos2_defconfig +++ b/configs/aristainetos2_defconfig @@ -8,6 +8,9 @@ CONFIG_ENV_SIZE=0x3000 CONFIG_ENV_OFFSET=0xD0000 CONFIG_NR_DRAM_BANKS=1 CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_IMX_HAB=y +# CONFIG_CMD_DEKBLOB is not set +# CONFIG_CMD_NANDBCB is not set CONFIG_FIT=y CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" CONFIG_BOOTDELAY=3 @@ -42,6 +45,7 @@ CONFIG_CMD_MII=y CONFIG_CMD_PING=y CONFIG_CMD_BMP=y CONFIG_CMD_CACHE=y +# CONFIG_CMD_HASH is not set CONFIG_CMD_EXT2=y CONFIG_CMD_EXT4=y CONFIG_CMD_EXT4_WRITE=y diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index fba26d0151..48cea2b4d0 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -36,6 +36,56 @@
#define CONFIG_SYS_SPI_ST_ENABLE_WP_PIN
+#ifdef CONFIG_IMX_HAB +#define HAB_EXTRA_SETTINGS \ + "hab_check_addr=" \ + "if hab_auth_img ${check_addr} ${filesize} ; then " \ + "true;" \ + "else " \ + "echo "HAB checks ${hab_check_filetype} " \ + "failed!"; " \ + "false; " \ + "fi;\0" \ + "hab_check_file_fit=" \ + "if env exists enable_hab_check && test " \ + "${enable_hab_check} -eq 1 ; then " \ + "setenv hab_check_filetype "FIT file on SD card " \ + "or eMMC";" \ + "env set check_addr ${fit_addr_r};" \ + "run hab_check_addr;" \ + "else " \ + "true; "\ + "fi;\0" \ + "hab_check_file_bootscript=" \ + "if env exists enable_hab_check && test " \ + "${enable_hab_check} -eq 1 ; then " \ + "setenv hab_check_filetype "Bootscript file";" \ + "env set check_addr ${loadaddr};" \ + "run hab_check_addr;" \ + "else " \ + "true; "\ + "fi;\0" \ + "hab_check_flash_fit=" \ + "if env exists enable_hab_check && test " \ + "${enable_hab_check} -eq 1 ; then " \ + "setenv hab_check_filetype "FIT files on flash";" \ + "env set check_addr ${fit_addr_r};" \ + "run hab_check_addr;" \ + "else " \ + "true; "\ + "fi;\0" \ + "enable_hab_check=1\0" +#else +#define HAB_EXTRA_SETTINGS \ + "hab_check_file_fit=echo HAB check FIT file always returns " \ + "true;true\0" \ + "hab_check_flash_fit=echo HAB check flash FIT always returns " \ + "true;true\0" \ + "hab_check_file_bootscript=echo HAB check bootscript always " \ + "returns true;true\0" \ + "enable_hab_check=0\0" +#endif + #define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ "dead=led led_red on\0" \ "mtdids=nand0=gpmi-nand,nor0=spi3.1\0" \ @@ -281,6 +331,7 @@ "else "\ "run main_rescue_boot;" \ "fi; \0"\ + HAB_EXTRA_SETTINGS \ CONFIG_EXTRA_ENV_BOARD_SETTINGS
#define CONFIG_ARP_TIMEOUT 200UL
enable IMX_HAB on aristianetos board Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
readd aristainetos 2b board.
Signed-off-by: Heiko Schocher hs@denx.de ---
arch/arm/dts/Makefile | 2 + .../dts/imx6dl-aristainetos2b_4-u-boot.dtsi | 13 + arch/arm/dts/imx6dl-aristainetos2b_4.dts | 50 ++++ .../dts/imx6dl-aristainetos2b_7-u-boot.dtsi | 19 ++ arch/arm/dts/imx6dl-aristainetos2b_7.dts | 16 ++ .../dts/imx6qdl-aristainetos2b-u-boot.dtsi | 77 +++++ arch/arm/dts/imx6qdl-aristainetos2b.dtsi | 266 ++++++++++++++++++ arch/arm/mach-imx/mx6/Kconfig | 11 + board/aristainetos/Kconfig | 12 + board/aristainetos/MAINTAINERS | 7 + board/aristainetos/common/Kconfig | 1 + configs/aristainetos2b_defconfig | 115 ++++++++ include/configs/aristainetos2.h | 23 ++ 13 files changed, 612 insertions(+) create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_4.dts create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_7.dts create mode 100644 arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2b.dtsi create mode 100644 configs/aristainetos2b_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index a2d673af4f..1cd120a98e 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -576,6 +576,8 @@ ifneq ($(CONFIG_MX6DL)$(CONFIG_MX6QDL)$(CONFIG_MX6S),) dtb-y += \ imx6dl-aristainetos2_4.dtb \ imx6dl-aristainetos2_7.dtb \ + imx6dl-aristainetos2b_4.dtb \ + imx6dl-aristainetos2b_7.dtb \ imx6dl-brppt2.dtb \ imx6dl-dhcom-pdk2.dtb \ imx6dl-icore.dtb \ diff --git a/arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi new file mode 100644 index 0000000000..ee02df39c1 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher hs@denx.de + */ + +#include <imx6qdl-aristainetos2b-u-boot.dtsi> + +&lcd_panel { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp>; + enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_4.dts b/arch/arm/dts/imx6dl-aristainetos2b_4.dts new file mode 100644 index 0000000000..a48a25c119 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2b_4.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2b board + * parts for 4.3 inch LG display on spi1 port1 + * + * Copyright (C) 2019 Heiko Schocher hs@denx.de + * + */ +/dts-v1/; + +#include "imx6dl-aristainetos2_4.dtsi" +#include "imx6qdl-aristainetos2b.dtsi" + +/ { + model = "aristainetos2b i.MX6 Dual Lite Board 4"; + compatible = "fsl,imx6dl"; + +}; + +&ecspi1 { + lcd_panel: display@0 { + compatible = "lg,lg4573"; + spi-max-frequency = <10000000>; + reg = <1>; + power-on-delay = <10>; + + display-timings { + 480x800p57 { + native-mode; + clock-frequency = <27000027>; + hactive = <480>; + vactive = <800>; + hfront-porch = <10>; + hback-porch = <59>; + hsync-len = <10>; + vback-porch = <15>; + vfront-porch = <15>; + vsync-len = <15>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi new file mode 100644 index 0000000000..0cb4f1974b --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher hs@denx.de + */ + +#include <imx6qdl-aristainetos2b-u-boot.dtsi> +/ { + vdd_panel_reg: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "panel_regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&panel0 { + power-supply = <&vdd_panel_reg>; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_7.dts b/arch/arm/dts/imx6dl-aristainetos2b_7.dts new file mode 100644 index 0000000000..f1496cbfdd --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2b_7.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2 board + * + * Copyright (C) 2019 Heiko Schocher hs@denx.de + * Copyright (C) 2015 Heiko Schocher hs@denx.de + * + */ +/dts-v1/; +#include "imx6dl-aristainetos2_7.dtsi" +#include "imx6qdl-aristainetos2b.dtsi" + +/ { + model = "aristainetos2b i.MX6 Dual Lite Board 7"; + compatible = "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi new file mode 100644 index 0000000000..88826a2634 --- /dev/null +++ b/arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher hs@denx.de + */ + +/ { + chosen { + u-boot,dm-pre-reloc; + stdout-path = &uart2; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + }; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_gpio { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart2 { + u-boot,dm-pre-reloc; +}; + +&iomuxc { + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-pre-reloc; +}; + +&backlight { + pwms = <&pwm1 0 300000>; + default-brightness-level = <2>; +}; + +/* + * allow switching write protect / reset pin by gpio, + * because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot + */ +&gpio2 { + u-boot,dm-pre-reloc; + + wp_spi_nor { + gpio-hog; + output-high; + gpios = <15 GPIO_ACTIVE_HIGH>; + }; + + reset_spi_nor { + gpio-hog; + output-high; + gpios = <28 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio4 { + u-boot,dm-pre-reloc; +}; + +&ecspi1 { + u-boot,dm-pre-reloc; +}; + +&flash { + u-boot,dm-pre-reloc; +}; + +&pinctrl_ecspi1 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2b.dtsi b/arch/arm/dts/imx6qdl-aristainetos2b.dtsi new file mode 100644 index 0000000000..7d92ea2af7 --- /dev/null +++ b/arch/arm/dts/imx6qdl-aristainetos2b.dtsi @@ -0,0 +1,266 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2b board + * + * Copyright (C) 2019 Heiko Schocher hs@denx.de + * Copyright (C) 2015 Heiko Schocher hs@denx.de + * + */ +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/imx6qdl-clock.h> + +#include "imx6qdl-aristainetos2-common.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio>; + + LED_blue { + label = "led_blue"; + gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; + }; + + LED_green { + label = "led_green"; + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + }; + + LED_red { + label = "led_red"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + }; + + LED_yellow { + label = "led_yellow"; + gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + }; + + LED_ena { + label = "led_ena"; + gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <3>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH + &gpio4 10 GPIO_ACTIVE_HIGH + &gpio4 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + status = "okay"; +}; + +&i2c1 { + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; +}; + +&gpio7 { + sd2_driver_ena { + gpio-hog; + output-high; + gpios = <8 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; + no-1-8-v; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + /* + * comment out this line to make the WiFi Eval-Module work in + * SD-Slot2, and add line: + * broken-cd; + * causes 6% CPU load if no WiFi module installed (polling) + */ + cd-gpios = <&gpio4 5 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio2 10 GPIO_ACTIVE_HIGH>; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* SS0# */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1 + /* SS1# */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 + /* SS2# */ + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 + /* WP pin NOR Flash */ + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 + /* Flash nReset */ + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0 + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + /* led enable */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 + /* LCD power enable */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0 + /* led yellow */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0 + /* led red */ + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0 + /* led green */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0 + /* led blue */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0 + /* Profibus IRQ */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + /* FPGA IRQ currently unused*/ + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 + /* Display reset because of clock failure */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 + /* spi bus #2 SS driver enable */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 + /* RST_LOC# PHY reset input (has pull-down!)*/ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0 + /* Touchscreen IRQ */ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 + /* PCIe reset */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 + /* make sure pin is GPIO and not ENET_REF_CLK */ + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0 + /* SD2 level shifter output enable / SD2 Reset# */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 + >; + }; + + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + /* SD1 card detect input */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 + /* SD1 write protect input */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 + /* SD2 card detect input */ + MX6QDL_PAD_GPIO_19__GPIO4_IO05 0x1b0b0 + /* SD2 write protect input */ + MX6QDL_PAD_SD4_DAT2__GPIO2_IO10 0x1b0b0 + >; + }; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index ede5989502..b3819d816d 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -136,6 +136,17 @@ config TARGET_ARISTAINETOS2 imply CMD_SATA imply CMD_DM
+config TARGET_ARISTAINETOS2B + bool "Support aristainetos2-revB" + select BOARD_LATE_INIT + select MX6DL + select SYS_I2C_MXC + select MXC_UART + select FEC_MXC + select DM + imply CMD_SATA + imply CMD_DM + config TARGET_CGTQMX6EVAL bool "cgtqmx6eval" select BOARD_LATE_INIT diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig index 6700f517f1..2e1d84d412 100644 --- a/board/aristainetos/Kconfig +++ b/board/aristainetos/Kconfig @@ -9,3 +9,15 @@ config SYS_BOARD_VERSION default 2
endif + +if TARGET_ARISTAINETOS2B + +source "board/aristainetos/common/Kconfig" + +config SYS_BOARD + default "aristainetos" + +config SYS_BOARD_VERSION + default 3 + +endif diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS index 2495cd4a37..4fa0ad2e98 100644 --- a/board/aristainetos/MAINTAINERS +++ b/board/aristainetos/MAINTAINERS @@ -4,6 +4,7 @@ S: Maintained F: board/aristainetos/ F: include/configs/aristainetos2.h F: configs/aristainetos2_defconfig +F: configs/aristainetos2b_defconfig F: arch/arm/dts/imx6qdl-aristainetos2.dtsi F: arch/arm/dts/imx6qdl-aristainetos2-common.dtsi F: arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi @@ -13,3 +14,9 @@ F: arch/arm/dts/imx6dl-aristainetos2_7-u-boot.dtsi F: arch/arm/dts/imx6dl-aristainetos2_4.dts F: arch/arm/dts/imx6dl-aristainetos2_4.dtsi F: arch/arm/dts/imx6dl-aristainetos2_4-u-boot.dtsi +F: arch/arm/dts/imx6dl-aristainetos2b_4.dts +F: arch/arm/dts/imx6dl-aristainetos2b_4-u-boot.dtsi +F: arch/arm/dts/imx6dl-aristainetos2b_7.dts +F: arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2b.dtsi diff --git a/board/aristainetos/common/Kconfig b/board/aristainetos/common/Kconfig index 8f2561415b..a15993e2de 100644 --- a/board/aristainetos/common/Kconfig +++ b/board/aristainetos/common/Kconfig @@ -3,6 +3,7 @@ config SYS_BOARD_VERSION help version of aristainetos board version 2 version 2 + 3 version 2b
config SYS_I2C_MXC_I2C1 default y diff --git a/configs/aristainetos2b_defconfig b/configs/aristainetos2b_defconfig new file mode 100644 index 0000000000..adfed9a3dc --- /dev/null +++ b/configs/aristainetos2b_defconfig @@ -0,0 +1,115 @@ +CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x17800000 +CONFIG_SYS_MALLOC_F_LEN=0xe000 +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xD0000 +CONFIG_TARGET_ARISTAINETOS2B=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_IMX_HAB=y +# CONFIG_CMD_DEKBLOB is not set +# CONFIG_CMD_NANDBCB is not set +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run ari_boot" +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_VERSION_VARIABLE=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_TYPES=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_ENCRYPTION=y +CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND_TRIMFFS=y +# CONFIG_CMD_PINMUX is not set +# CONFIG_CMD_SATA is not set +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +# CONFIG_CMD_HASH is not set +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2b_4" +CONFIG_OF_LIST="imx6dl-aristainetos2b_4 imx6dl-aristainetos2b_7" +CONFIG_DTB_RESELECT=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SPI_EARLY=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_OFFSET_REDUND=0xE0000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_GPIO=y +CONFIG_GPIO_HOG=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_PWM=y +CONFIG_PWM_IMX=y +CONFIG_DM_RTC=y +CONFIG_RTC_DS1307=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_WATCHDOG=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 48cea2b4d0..d2646d26da 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -86,6 +86,28 @@ "enable_hab_check=0\0" #endif
+#if (CONFIG_SYS_BOARD_VERSION == 3) +#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ + "dead=led led_red on\0" \ + "mtdids=nand0=gpmi-nand,nor0=spi0.0\0" \ + "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ + "-(ubi-nor);gpmi-nand:-(ubi)\0" \ + "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ + "bootmode=${bootmode} mmcpart=${mmcpart}\0" \ + "mainboot=echo Booting from SD-card ...; " \ + "run mainargs addmtd addmisc;" \ + "if test -n ${addmiscM}; then run addmiscM;fi;" \ + "if test -n ${addmiscC}; then run addmiscC;fi;" \ + "if test -n ${addmiscD}; then run addmiscD;fi;" \ + "run boot_board_type;" \ + "bootm ${fit_addr_r}\0" \ + "mainargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "main_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ + "${fit_file}\0" \ + "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ + "${fit_addr_r} ${rescue_fit_file}\0" +#else #define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ "dead=led led_red on\0" \ "mtdids=nand0=gpmi-nand,nor0=spi3.1\0" \ @@ -106,6 +128,7 @@ "${fit_file}\0" \ "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ "${fit_addr_r} ${rescue_fit_file}\0" +#endif
#define CONFIG_EXTRA_ENV_SETTINGS \ "disable_giga=yes\0" \
readd aristainetos 2b board. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
add aristainetso board version CSL.
Signed-off-by: Heiko Schocher hs@denx.de ---
arch/arm/dts/Makefile | 2 + .../imx6dl-aristainetos2b_csl_4-u-boot.dtsi | 13 + arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts | 50 ++++ .../imx6dl-aristainetos2b_csl_7-u-boot.dtsi | 19 ++ arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts | 16 ++ .../imx6qdl-aristainetos2b_csl-u-boot.dtsi | 77 ++++++ arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi | 248 ++++++++++++++++++ arch/arm/mach-imx/mx6/Kconfig | 11 + board/aristainetos/Kconfig | 12 + board/aristainetos/MAINTAINERS | 7 + board/aristainetos/aristainetos.c | 4 +- board/aristainetos/common/Kconfig | 1 + configs/aristainetos2bcsl_defconfig | 115 ++++++++ include/configs/aristainetos2.h | 21 ++ 14 files changed, 595 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts create mode 100644 arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi create mode 100644 configs/aristainetos2bcsl_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index 1cd120a98e..e7ae3e40f9 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -578,6 +578,8 @@ dtb-y += \ imx6dl-aristainetos2_7.dtb \ imx6dl-aristainetos2b_4.dtb \ imx6dl-aristainetos2b_7.dtb \ + imx6dl-aristainetos2b_csl_4.dtb \ + imx6dl-aristainetos2b_csl_7.dtb \ imx6dl-brppt2.dtb \ imx6dl-dhcom-pdk2.dtb \ imx6dl-icore.dtb \ diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi new file mode 100644 index 0000000000..654ac122a1 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher hs@denx.de + */ + +#include <imx6qdl-aristainetos2b_csl-u-boot.dtsi> + +&lcd_panel { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp>; + enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts b/arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts new file mode 100644 index 0000000000..bfbb799f20 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2b csl board + * parts for 4.3 inch LG display on spi1 port1 + * + * Copyright (C) 2019 Heiko Schocher hs@denx.de + * + */ +/dts-v1/; + +#include "imx6dl-aristainetos2_4.dtsi" +#include "imx6qdl-aristainetos2b_csl.dtsi" + +/ { + model = "aristainetos2b csl i.MX6 Dual Lite Board 4"; + compatible = "fsl,imx6dl"; + +}; + +&ecspi1 { + lcd_panel: display@0 { + compatible = "lg,lg4573"; + spi-max-frequency = <10000000>; + reg = <1>; + power-on-delay = <10>; + + display-timings { + 480x800p57 { + native-mode; + clock-frequency = <27000027>; + hactive = <480>; + vactive = <800>; + hfront-porch = <10>; + hback-porch = <59>; + hsync-len = <10>; + vback-porch = <15>; + vfront-porch = <15>; + vsync-len = <15>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi new file mode 100644 index 0000000000..70d195ecbf --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher hs@denx.de + */ + +#include <imx6qdl-aristainetos2b_csl-u-boot.dtsi> +/ { + vdd_panel_reg: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "panel_regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&panel0 { + power-supply = <&vdd_panel_reg>; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts b/arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts new file mode 100644 index 0000000000..ecf767da6c --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2 board + * + * Copyright (C) 2019 Heiko Schocher hs@denx.de + * Copyright (C) 2015 Heiko Schocher hs@denx.de + * + */ +/dts-v1/; +#include "imx6dl-aristainetos2_7.dtsi" +#include "imx6qdl-aristainetos2b_csl.dtsi" + +/ { + model = "aristainetos2b csl i.MX6 Dual Lite Board 7"; + compatible = "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi new file mode 100644 index 0000000000..8c2ed70075 --- /dev/null +++ b/arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher hs@denx.de + */ + +/ { + chosen { + u-boot,dm-pre-reloc; + stdout-path = &uart1; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + }; +}; + +&uart1 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_gpio { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart1 { + u-boot,dm-pre-reloc; +}; + +&iomuxc { + u-boot,dm-pre-reloc; +}; + +&aips1 { + u-boot,dm-pre-reloc; +}; + +&backlight { + pwms = <&pwm1 0 300000>; + default-brightness-level = <2>; +}; + +/* + * allow switching write protect / reset pin by gpio, + * because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot + */ +&gpio2 { + u-boot,dm-pre-reloc; + + wp_spi_nor { + gpio-hog; + output-high; + gpios = <15 GPIO_ACTIVE_HIGH>; + }; + + reset_spi_nor { + gpio-hog; + output-high; + gpios = <28 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio4 { + u-boot,dm-pre-reloc; +}; + +&ecspi1 { + u-boot,dm-pre-reloc; +}; + +&flash { + u-boot,dm-pre-reloc; +}; + +&pinctrl_ecspi1 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi b/arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi new file mode 100644 index 0000000000..fa4dadefb6 --- /dev/null +++ b/arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi @@ -0,0 +1,248 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2b-csl board + * + * Copyright (C) 2019 Heiko Schocher hs@denx.de + * Copyright (C) 2015 Heiko Schocher hs@denx.de + * + */ +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/imx6qdl-clock.h> + +#include "imx6qdl-aristainetos2-common.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio>; + + LED_blue { + label = "led_blue"; + gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; + }; + + LED_green { + label = "led_green"; + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + }; + + LED_red { + label = "led_red"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + }; + + LED_yellow { + label = "led_yellow"; + gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + }; + + LED_blue_2 { + label = "led_blue2"; + gpios = <&expander 15 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + LED_green_2 { + label = "led_green2"; + gpios = <&expander 14 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + LED_red_2 { + label = "led_red2"; + gpios = <&expander 12 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + LED_yellow_2 { + label = "led_yellow2"; + gpios = <&expander 13 GPIO_ACTIVE_LOW>; + default-state = "off"; + }; + + LED_ena { + label = "led_ena"; + gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <3>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH + &gpio4 10 GPIO_ACTIVE_HIGH + &gpio4 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + status = "okay"; +}; + +&i2c1 { + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; +}; + +&gpio7 { + wlan_reset { + gpio-hog; + output-high; + gpios = <8 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpmi { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpmi_nand>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + no-1-8-v; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* SS0# */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1 + /* SS1# */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 + /* SS2# */ + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 + /* WP pin NOR Flash */ + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 + /* Flash nReset */ + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0 + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + /* led enable */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 + /* LCD power enable */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0 + /* led yellow */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0 + /* led red */ + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0 + /* led green */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0 + /* led blue */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0 + /* Profibus IRQ */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + /* FPGA IRQ currently unused*/ + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 + /* Display reset because of clock failure */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 + /* spi bus #2 SS driver enable */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 + /* RST_LOC# PHY reset input (has pull-down!)*/ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0 + /* Touchscreen IRQ */ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 + /* PCIe reset */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 + /* make sure pin is GPIO and not ENET_REF_CLK */ + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0 + /* WLAN Module Reset# */ + MX6QDL_PAD_SD3_RST__GPIO7_IO08 0x4001b0b0 + >; + }; + + pinctrl_gpmi_nand: gpmi-nand { + fsl,pins = < + MX6QDL_PAD_NANDF_CLE__NAND_CLE 0xb0b1 + MX6QDL_PAD_NANDF_ALE__NAND_ALE 0xb0b1 + MX6QDL_PAD_NANDF_WP_B__NAND_WP_B 0xb0b1 + MX6QDL_PAD_NANDF_RB0__NAND_READY_B 0xb000 + MX6QDL_PAD_NANDF_CS0__NAND_CE0_B 0xb0b1 + MX6QDL_PAD_SD4_CMD__NAND_RE_B 0xb0b1 + MX6QDL_PAD_SD4_CLK__NAND_WE_B 0xb0b1 + MX6QDL_PAD_NANDF_D0__NAND_DATA00 0xb0b1 + MX6QDL_PAD_NANDF_D1__NAND_DATA01 0xb0b1 + MX6QDL_PAD_NANDF_D2__NAND_DATA02 0xb0b1 + MX6QDL_PAD_NANDF_D3__NAND_DATA03 0xb0b1 + MX6QDL_PAD_NANDF_D4__NAND_DATA04 0xb0b1 + MX6QDL_PAD_NANDF_D5__NAND_DATA05 0xb0b1 + MX6QDL_PAD_NANDF_D6__NAND_DATA06 0xb0b1 + MX6QDL_PAD_NANDF_D7__NAND_DATA07 0xb0b1 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + /* SD1 card detect input */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x71 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x71 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x71 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x71 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x71 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x71 + >; + }; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index b3819d816d..7787dbaf6d 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -147,6 +147,17 @@ config TARGET_ARISTAINETOS2B imply CMD_SATA imply CMD_DM
+config TARGET_ARISTAINETOS2BCSL + bool "Support aristainetos2-revB CSL" + select BOARD_LATE_INIT + select MX6DL + select SYS_I2C_MXC + select MXC_UART + select FEC_MXC + select DM + imply CMD_SATA + imply CMD_DM + config TARGET_CGTQMX6EVAL bool "cgtqmx6eval" select BOARD_LATE_INIT diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig index 2e1d84d412..9eb3c3b9d8 100644 --- a/board/aristainetos/Kconfig +++ b/board/aristainetos/Kconfig @@ -21,3 +21,15 @@ config SYS_BOARD_VERSION default 3
endif + +if TARGET_ARISTAINETOS2BCSL + +source "board/aristainetos/common/Kconfig" + +config SYS_BOARD + default "aristainetos" + +config SYS_BOARD_VERSION + default 4 + +endif diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS index 4fa0ad2e98..9685c032ab 100644 --- a/board/aristainetos/MAINTAINERS +++ b/board/aristainetos/MAINTAINERS @@ -5,6 +5,7 @@ F: board/aristainetos/ F: include/configs/aristainetos2.h F: configs/aristainetos2_defconfig F: configs/aristainetos2b_defconfig +F: configs/aristainetos2bcsl_defconfig F: arch/arm/dts/imx6qdl-aristainetos2.dtsi F: arch/arm/dts/imx6qdl-aristainetos2-common.dtsi F: arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi @@ -20,3 +21,9 @@ F: arch/arm/dts/imx6dl-aristainetos2b_7.dts F: arch/arm/dts/imx6dl-aristainetos2b_7-u-boot.dtsi F: arch/arm/dts/imx6qdl-aristainetos2b-u-boot.dtsi F: arch/arm/dts/imx6qdl-aristainetos2b.dtsi +F: arch/arm/dts/imx6dl-aristainetos2b_csl_4.dts +F: arch/arm/dts/imx6dl-aristainetos2b_csl_4-u-boot.dtsi +F: arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts +F: arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index ca6155947b..88090799a6 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -490,7 +490,9 @@ struct display_info_t const displays[] = { .vmode = FB_VMODE_NONINTERLACED } } -#if ((CONFIG_SYS_BOARD_VERSION == 2) || (CONFIG_SYS_BOARD_VERSION == 3)) +#if ((CONFIG_SYS_BOARD_VERSION == 2) || \ + (CONFIG_SYS_BOARD_VERSION == 3) || \ + (CONFIG_SYS_BOARD_VERSION == 4)) , { .bus = -1, .addr = 0, diff --git a/board/aristainetos/common/Kconfig b/board/aristainetos/common/Kconfig index a15993e2de..6f1c825d80 100644 --- a/board/aristainetos/common/Kconfig +++ b/board/aristainetos/common/Kconfig @@ -4,6 +4,7 @@ config SYS_BOARD_VERSION version of aristainetos board version 2 version 2 3 version 2b + 4 version 2bcsl
config SYS_I2C_MXC_I2C1 default y diff --git a/configs/aristainetos2bcsl_defconfig b/configs/aristainetos2bcsl_defconfig new file mode 100644 index 0000000000..d83d52fbc6 --- /dev/null +++ b/configs/aristainetos2bcsl_defconfig @@ -0,0 +1,115 @@ +CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x17800000 +CONFIG_SYS_MALLOC_F_LEN=0xe000 +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xD0000 +CONFIG_TARGET_ARISTAINETOS2BCSL=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_IMX_HAB=y +# CONFIG_CMD_DEKBLOB is not set +# CONFIG_CMD_NANDBCB is not set +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run ari_boot" +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_VERSION_VARIABLE=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_TYPES=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_ENCRYPTION=y +CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +CONFIG_CMD_NAND_TRIMFFS=y +# CONFIG_CMD_PINMUX is not set +# CONFIG_CMD_SATA is not set +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +# CONFIG_CMD_HASH is not set +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2b_csl_4" +CONFIG_OF_LIST="imx6dl-aristainetos2b_csl_4 imx6dl-aristainetos2b_csl_7" +CONFIG_DTB_RESELECT=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SPI_EARLY=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_OFFSET_REDUND=0xE0000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_DM_GPIO=y +CONFIG_GPIO_HOG=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_NAND=y +CONFIG_NAND_MXS=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_PWM=y +CONFIG_PWM_IMX=y +CONFIG_DM_RTC=y +CONFIG_RTC_DS1307=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_WATCHDOG=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index d2646d26da..64a819df13 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -107,6 +107,27 @@ "${fit_file}\0" \ "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ "${fit_addr_r} ${rescue_fit_file}\0" +#elif (CONFIG_SYS_BOARD_VERSION == 4) +#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ + "dead=led led_red on;led led_red2 on;\0" \ + "mtdids=nand0=gpmi-nand,nor0=spi0.0\0" \ + "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ + "-(ubi-nor);gpmi-nand:-(ubi)\0" \ + "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ + "bootmode=${bootmode} mmcpart=${mmcpart}\0" \ + "mainboot=echo Booting from SD-card ...; " \ + "run mainargs addmtd addmisc;" \ + "if test -n ${addmiscM}; then run addmiscM;fi;" \ + "if test -n ${addmiscC}; then run addmiscC;fi;" \ + "if test -n ${addmiscD}; then run addmiscD;fi;" \ + "run boot_board_type;" \ + "bootm ${fit_addr_r}\0" \ + "mainargs=setenv bootargs console=${console},${baudrate} " \ + "root=${mmcroot}\0" \ + "main_load_fit=ext4load mmc ${mmcdev}:${mmcpart} ${fit_addr_r} " \ + "${fit_file}\0" \ + "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ + "${fit_addr_r} ${rescue_fit_file}\0" #else #define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ "dead=led led_red on\0" \
add aristainetso board version CSL. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
add support for revision C boards. This board has no longer a NAND.
Signed-off-by: Heiko Schocher hs@denx.de ---
arch/arm/dts/Makefile | 2 + .../dts/imx6dl-aristainetos2c_4-u-boot.dtsi | 13 + arch/arm/dts/imx6dl-aristainetos2c_4.dts | 50 ++++ .../dts/imx6dl-aristainetos2c_7-u-boot.dtsi | 19 ++ arch/arm/dts/imx6dl-aristainetos2c_7.dts | 16 ++ .../dts/imx6qdl-aristainetos2c-u-boot.dtsi | 77 ++++++ arch/arm/dts/imx6qdl-aristainetos2c.dtsi | 228 ++++++++++++++++++ arch/arm/mach-imx/mx6/Kconfig | 11 + board/aristainetos/Kconfig | 12 + board/aristainetos/MAINTAINERS | 7 + board/aristainetos/aristainetos.c | 9 +- board/aristainetos/common/Kconfig | 1 + configs/aristainetos2c_defconfig | 115 +++++++++ include/configs/aristainetos2.h | 27 +++ 14 files changed, 586 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2c_4.dts create mode 100644 arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi create mode 100644 arch/arm/dts/imx6dl-aristainetos2c_7.dts create mode 100644 arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi create mode 100644 arch/arm/dts/imx6qdl-aristainetos2c.dtsi create mode 100644 configs/aristainetos2c_defconfig
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e7ae3e40f9..31579f0ba7 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -580,6 +580,8 @@ dtb-y += \ imx6dl-aristainetos2b_7.dtb \ imx6dl-aristainetos2b_csl_4.dtb \ imx6dl-aristainetos2b_csl_7.dtb \ + imx6dl-aristainetos2c_4.dtb \ + imx6dl-aristainetos2c_7.dtb \ imx6dl-brppt2.dtb \ imx6dl-dhcom-pdk2.dtb \ imx6dl-icore.dtb \ diff --git a/arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi new file mode 100644 index 0000000000..052d51852b --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi @@ -0,0 +1,13 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher hs@denx.de + */ + +#include <imx6qdl-aristainetos2c-u-boot.dtsi> + +&lcd_panel { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ipu_disp>; + enable-gpios = <&gpio6 15 GPIO_ACTIVE_HIGH>; + backlight = <&backlight>; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2c_4.dts b/arch/arm/dts/imx6dl-aristainetos2c_4.dts new file mode 100644 index 0000000000..142b108ace --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2c_4.dts @@ -0,0 +1,50 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2c board + * parts for 4.3 inch LG display on spi1 port1 + * + * Copyright (C) 2019 Heiko Schocher hs@denx.de + * + */ +/dts-v1/; + +#include "imx6dl-aristainetos2_4.dtsi" +#include "imx6qdl-aristainetos2c.dtsi" + +/ { + model = "aristainetos2c i.MX6 Dual Lite Board 4"; + compatible = "fsl,imx6dl"; + +}; + +&ecspi1 { + lcd_panel: display@0 { + compatible = "lg,lg4573"; + spi-max-frequency = <10000000>; + reg = <1>; + power-on-delay = <10>; + + display-timings { + 480x800p57 { + native-mode; + clock-frequency = <27000027>; + hactive = <480>; + vactive = <800>; + hfront-porch = <10>; + hback-porch = <59>; + hsync-len = <10>; + vback-porch = <15>; + vfront-porch = <15>; + vsync-len = <15>; + hsync-active = <1>; + vsync-active = <1>; + }; + }; + + port { + panel_in: endpoint { + remote-endpoint = <&display_out>; + }; + }; + }; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi b/arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi new file mode 100644 index 0000000000..cb2181d9e2 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher hs@denx.de + */ + +#include <imx6qdl-aristainetos2c-u-boot.dtsi> +/ { + vdd_panel_reg: regulator-panel { + compatible = "regulator-fixed"; + regulator-name = "panel_regulator"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-always-on; + }; +}; + +&panel0 { + power-supply = <&vdd_panel_reg>; +}; diff --git a/arch/arm/dts/imx6dl-aristainetos2c_7.dts b/arch/arm/dts/imx6dl-aristainetos2c_7.dts new file mode 100644 index 0000000000..35435e1c10 --- /dev/null +++ b/arch/arm/dts/imx6dl-aristainetos2c_7.dts @@ -0,0 +1,16 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2c board + * + * Copyright (C) 2019 Heiko Schocher hs@denx.de + * Copyright (C) 2015 Heiko Schocher hs@denx.de + * + */ +/dts-v1/; +#include "imx6dl-aristainetos2_7.dtsi" +#include "imx6qdl-aristainetos2c.dtsi" + +/ { + model = "aristainetos2c i.MX6 Dual Lite Board 7"; + compatible = "fsl,imx6dl"; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi b/arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi new file mode 100644 index 0000000000..88826a2634 --- /dev/null +++ b/arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi @@ -0,0 +1,77 @@ +// SPDX-License-Identifier: GPL-2.0+ or X11 +/* + * Copyright (C) 2019 Heiko Schocher hs@denx.de + */ + +/ { + chosen { + u-boot,dm-pre-reloc; + stdout-path = &uart2; + }; + + wdt-reboot { + compatible = "wdt-reboot"; + wdt = <&wdog1>; + }; +}; + +&uart2 { + u-boot,dm-pre-reloc; +}; + +&pinctrl_gpio { + u-boot,dm-pre-reloc; +}; + +&pinctrl_uart2 { + u-boot,dm-pre-reloc; +}; + +&iomuxc { + u-boot,dm-pre-reloc; +}; + +&aips2 { + u-boot,dm-pre-reloc; +}; + +&backlight { + pwms = <&pwm1 0 300000>; + default-brightness-level = <2>; +}; + +/* + * allow switching write protect / reset pin by gpio, + * because "pinctrl-assert-gpios" from &ecspi1 isn't handled by u-boot + */ +&gpio2 { + u-boot,dm-pre-reloc; + + wp_spi_nor { + gpio-hog; + output-high; + gpios = <15 GPIO_ACTIVE_HIGH>; + }; + + reset_spi_nor { + gpio-hog; + output-high; + gpios = <28 GPIO_ACTIVE_HIGH>; + }; +}; + +&gpio4 { + u-boot,dm-pre-reloc; +}; + +&ecspi1 { + u-boot,dm-pre-reloc; +}; + +&flash { + u-boot,dm-pre-reloc; +}; + +&pinctrl_ecspi1 { + u-boot,dm-pre-reloc; +}; diff --git a/arch/arm/dts/imx6qdl-aristainetos2c.dtsi b/arch/arm/dts/imx6qdl-aristainetos2c.dtsi new file mode 100644 index 0000000000..ba13d55f41 --- /dev/null +++ b/arch/arm/dts/imx6qdl-aristainetos2c.dtsi @@ -0,0 +1,228 @@ +// SPDX-License-Identifier: (GPL-2.0) +/* + * support for the imx6 based aristainetos2c board + * + * Copyright (C) 2019 Heiko Schocher hs@denx.de + * Copyright (C) 2015 Heiko Schocher hs@denx.de + * + */ +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/clock/imx6qdl-clock.h> + +#include "imx6qdl-aristainetos2-common.dtsi" + +/ { + leds { + compatible = "gpio-leds"; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_gpio>; + + LED_blue { + label = "led_blue"; + gpios = <&gpio2 29 GPIO_ACTIVE_HIGH>; + }; + + LED_green { + label = "led_green"; + gpios = <&gpio5 4 GPIO_ACTIVE_HIGH>; + }; + + LED_red { + label = "led_red"; + gpios = <&gpio5 0 GPIO_ACTIVE_HIGH>; + }; + + LED_yellow { + label = "led_yellow"; + gpios = <&gpio6 16 GPIO_ACTIVE_HIGH>; + }; + + LED_ena { + label = "led_ena"; + gpios = <&gpio1 25 GPIO_ACTIVE_LOW>; + }; + }; +}; + +&ecspi1 { + fsl,spi-num-chipselects = <3>; + cs-gpios = <&gpio2 30 GPIO_ACTIVE_HIGH + &gpio4 10 GPIO_ACTIVE_HIGH + &gpio4 11 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi1>; + status = "okay"; + pinctrl-assert-gpios = <&gpio2 28 GPIO_ACTIVE_HIGH>; + pinctrl-assert-gpios = <&gpio2 15 GPIO_ACTIVE_HIGH>; + + flash: m25p80@0 { + #address-cells = <1>; + #size-cells = <1>; + compatible = "micron,n25q128a11", "jedec,spi-nor"; + spi-max-frequency = <20000000>; + reg = <0>; + }; +}; + +&ecspi4 { + fsl,spi-num-chipselects = <2>; + cs-gpios = <&gpio3 29 GPIO_ACTIVE_HIGH &gpio5 2 GPIO_ACTIVE_HIGH>; + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_ecspi4>; + status = "okay"; +}; + +&i2c1 { + tpm@20 { + compatible = "infineon,slb9645tt"; + reg = <0x20>; + }; +}; + +&can1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan1>; + status = "okay"; +}; + +&can2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_flexcan2>; + status = "okay"; +}; + +&usdhc1 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc1>; + cd-gpios = <&gpio1 27 GPIO_ACTIVE_LOW>; + wp-gpios = <&gpio4 20 GPIO_ACTIVE_HIGH>; + no-1-8-v; + status = "okay"; +}; + +&usdhc2 { + pinctrl-names = "default"; + pinctrl-0 = <&pinctrl_usdhc2>; + bus-width = <8>; + no-1-8-v; + non-removable; + status = "okay"; +}; + +&iomuxc { + pinctrl_ecspi1: ecspi1grp { + fsl,pins = < + MX6QDL_PAD_EIM_D17__ECSPI1_MISO 0x100b1 + MX6QDL_PAD_EIM_D18__ECSPI1_MOSI 0x100b1 + MX6QDL_PAD_EIM_D16__ECSPI1_SCLK 0x100b1 + /* SS0# */ + MX6QDL_PAD_EIM_EB2__GPIO2_IO30 0x100b1 + /* SS1# */ + MX6QDL_PAD_KEY_COL2__GPIO4_IO10 0x100b1 + /* SS2# */ + MX6QDL_PAD_KEY_ROW2__GPIO4_IO11 0x100b1 + /* WP pin NOR Flash */ + MX6QDL_PAD_SD4_DAT7__GPIO2_IO15 0x4001b0b0 + /* Flash nReset */ + MX6QDL_PAD_EIM_EB0__GPIO2_IO28 0x4001b0b0 + >; + }; + + pinctrl_ecspi4: ecspi4grp { + fsl,pins = < + MX6QDL_PAD_EIM_D21__ECSPI4_SCLK 0x100b1 + MX6QDL_PAD_EIM_D22__ECSPI4_MISO 0x100b1 + MX6QDL_PAD_EIM_D28__ECSPI4_MOSI 0x100b1 + MX6QDL_PAD_EIM_D29__GPIO3_IO29 0x100b1 /* SS0# */ + MX6QDL_PAD_EIM_A25__GPIO5_IO02 0x100b1 /* SS1# */ + >; + }; + + pinctrl_gpio: gpiogrp { + fsl,pins = < + /* led enable */ + MX6QDL_PAD_ENET_CRS_DV__GPIO1_IO25 0x4001b0b0 + /* LCD power enable */ + MX6QDL_PAD_NANDF_CS2__GPIO6_IO15 0x4001b0b0 + /* led yellow */ + MX6QDL_PAD_NANDF_CS3__GPIO6_IO16 0x4001b0b0 + /* led red */ + MX6QDL_PAD_EIM_WAIT__GPIO5_IO00 0x4001b0b0 + /* led green */ + MX6QDL_PAD_EIM_A24__GPIO5_IO04 0x4001b0b0 + /* led blue */ + MX6QDL_PAD_EIM_EB1__GPIO2_IO29 0x4001b0b0 + /* Profibus IRQ */ + MX6QDL_PAD_SD3_DAT5__GPIO7_IO00 0x1b0b0 + /* FPGA IRQ currently unused*/ + MX6QDL_PAD_SD3_DAT6__GPIO6_IO18 0x1b0b0 + /* Display reset because of clock failure */ + MX6QDL_PAD_SD4_DAT3__GPIO2_IO11 0x4001b0b0 + /* spi bus #2 SS driver enable */ + MX6QDL_PAD_EIM_A23__GPIO6_IO06 0x4001b0b0 + /* RST_LOC# PHY reset input (has pull-down!)*/ + MX6QDL_PAD_GPIO_18__GPIO7_IO13 0x4001b0b0 + /* Touchscreen IRQ */ + MX6QDL_PAD_SD4_DAT1__GPIO2_IO09 0x1b0b0 + /* PCIe reset */ + MX6QDL_PAD_EIM_A22__GPIO2_IO16 0x4001b0b0 + /* make sure pin is GPIO and not ENET_REF_CLK */ + MX6QDL_PAD_GPIO_16__GPIO7_IO11 0x4001a0b0 + /* TPM PP */ + MX6QDL_PAD_EIM_A21__GPIO2_IO17 0x4001b0b0 + /* TPM Reset */ + MX6QDL_PAD_EIM_A20__GPIO2_IO18 0x4001b0b0 + >; + }; + + pinctrl_flexcan1: flexcan1grp { + fsl,pins = < + MX6QDL_PAD_SD3_CLK__FLEXCAN1_RX 0x1b0b0 + MX6QDL_PAD_SD3_CMD__FLEXCAN1_TX 0x1b0b0 + >; + }; + + pinctrl_flexcan2: flexcan2grp { + fsl,pins = < + MX6QDL_PAD_SD3_DAT0__FLEXCAN2_TX 0x1b0b0 + MX6QDL_PAD_SD3_DAT1__FLEXCAN2_RX 0x1b0b0 + >; + }; + + pinctrl_usbotg: usbotggrp { + fsl,pins = < + MX6QDL_PAD_ENET_RX_ER__USB_OTG_ID 0x17059 + MX6QDL_PAD_KEY_COL4__USB_OTG_OC 0x1b0b0 + >; + }; + + pinctrl_usdhc1: usdhc1grp { + fsl,pins = < + MX6QDL_PAD_SD1_CMD__SD1_CMD 0x17059 + MX6QDL_PAD_SD1_CLK__SD1_CLK 0x10059 + MX6QDL_PAD_SD1_DAT0__SD1_DATA0 0x17059 + MX6QDL_PAD_SD1_DAT1__SD1_DATA1 0x17059 + MX6QDL_PAD_SD1_DAT2__SD1_DATA2 0x17059 + MX6QDL_PAD_SD1_DAT3__SD1_DATA3 0x17059 + /* SD1 card detect input */ + MX6QDL_PAD_ENET_RXD0__GPIO1_IO27 0x1b0b0 + /* SD1 write protect input */ + MX6QDL_PAD_DI0_PIN4__GPIO4_IO20 0x1b0b0 + >; + }; + + pinctrl_usdhc2: usdhc2grp { + fsl,pins = < + MX6QDL_PAD_SD2_CMD__SD2_CMD 0x17059 + MX6QDL_PAD_SD2_CLK__SD2_CLK 0x10059 + MX6QDL_PAD_SD2_DAT0__SD2_DATA0 0x17059 + MX6QDL_PAD_SD2_DAT1__SD2_DATA1 0x17059 + MX6QDL_PAD_SD2_DAT2__SD2_DATA2 0x17059 + MX6QDL_PAD_SD2_DAT3__SD2_DATA3 0x17059 + MX6QDL_PAD_NANDF_D4__SD2_DATA4 0x17059 + MX6QDL_PAD_NANDF_D5__SD2_DATA5 0x17059 + MX6QDL_PAD_NANDF_D6__SD2_DATA6 0x17059 + MX6QDL_PAD_NANDF_D7__SD2_DATA7 0x17059 + >; + }; +}; diff --git a/arch/arm/mach-imx/mx6/Kconfig b/arch/arm/mach-imx/mx6/Kconfig index 7787dbaf6d..e3beb818ce 100644 --- a/arch/arm/mach-imx/mx6/Kconfig +++ b/arch/arm/mach-imx/mx6/Kconfig @@ -158,6 +158,17 @@ config TARGET_ARISTAINETOS2BCSL imply CMD_SATA imply CMD_DM
+config TARGET_ARISTAINETOS2C + bool "Support aristainetos2-revC" + select BOARD_LATE_INIT + select MX6DL + select SYS_I2C_MXC + select MXC_UART + select FEC_MXC + select DM + imply CMD_SATA + imply CMD_DM + config TARGET_CGTQMX6EVAL bool "cgtqmx6eval" select BOARD_LATE_INIT diff --git a/board/aristainetos/Kconfig b/board/aristainetos/Kconfig index 9eb3c3b9d8..2ad3dbd56c 100644 --- a/board/aristainetos/Kconfig +++ b/board/aristainetos/Kconfig @@ -33,3 +33,15 @@ config SYS_BOARD_VERSION default 4
endif + +if TARGET_ARISTAINETOS2C + +source "board/aristainetos/common/Kconfig" + +config SYS_BOARD + default "aristainetos" + +config SYS_BOARD_VERSION + default 5 + +endif diff --git a/board/aristainetos/MAINTAINERS b/board/aristainetos/MAINTAINERS index 9685c032ab..b4ca7abb9c 100644 --- a/board/aristainetos/MAINTAINERS +++ b/board/aristainetos/MAINTAINERS @@ -6,6 +6,7 @@ F: include/configs/aristainetos2.h F: configs/aristainetos2_defconfig F: configs/aristainetos2b_defconfig F: configs/aristainetos2bcsl_defconfig +F: configs/aristainetos2c_defconfig F: arch/arm/dts/imx6qdl-aristainetos2.dtsi F: arch/arm/dts/imx6qdl-aristainetos2-common.dtsi F: arch/arm/dts/imx6qdl-aristainetos2-u-boot.dtsi @@ -27,3 +28,9 @@ F: arch/arm/dts/imx6dl-aristainetos2b_csl_7.dts F: arch/arm/dts/imx6dl-aristainetos2b_csl_7-u-boot.dtsi F: arch/arm/dts/imx6qdl-aristainetos2b_csl.dtsi F: arch/arm/dts/imx6qdl-aristainetos2b_csl-u-boot.dtsi +F: arch/arm/dts/imx6dl-aristainetos2c_4.dts +F: arch/arm/dts/imx6dl-aristainetos2c_4-u-boot.dtsi +F: arch/arm/dts/imx6dl-aristainetos2c_7.dts +F: arch/arm/dts/imx6dl-aristainetos2c_7-u-boot.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2c.dtsi +F: arch/arm/dts/imx6qdl-aristainetos2c-u-boot.dtsi diff --git a/board/aristainetos/aristainetos.c b/board/aristainetos/aristainetos.c index 88090799a6..c79ac1d339 100644 --- a/board/aristainetos/aristainetos.c +++ b/board/aristainetos/aristainetos.c @@ -492,7 +492,8 @@ struct display_info_t const displays[] = { } #if ((CONFIG_SYS_BOARD_VERSION == 2) || \ (CONFIG_SYS_BOARD_VERSION == 3) || \ - (CONFIG_SYS_BOARD_VERSION == 4)) + (CONFIG_SYS_BOARD_VERSION == 4) || \ + (CONFIG_SYS_BOARD_VERSION == 5)) , { .bus = -1, .addr = 0, @@ -520,6 +521,7 @@ struct display_info_t const displays[] = { }; size_t display_count = ARRAY_SIZE(displays);
+#if defined(CONFIG_NAND) iomux_v3_cfg_t nfc_pads[] = { MX6_PAD_NANDF_CLE__NAND_CLE | MUX_PAD_CTRL(NO_PAD_CTRL), MX6_PAD_NANDF_ALE__NAND_ALE | MUX_PAD_CTRL(NO_PAD_CTRL), @@ -573,6 +575,11 @@ static void setup_gpmi_nand(void) /* enable apbh clock gating */ setbits_le32(&mxc_ccm->CCGR0, MXC_CCM_CCGR0_APBHDMA_MASK); } +#else +static void setup_gpmi_nand(void) +{ +} +#endif
int board_init(void) { diff --git a/board/aristainetos/common/Kconfig b/board/aristainetos/common/Kconfig index 6f1c825d80..e26de5144d 100644 --- a/board/aristainetos/common/Kconfig +++ b/board/aristainetos/common/Kconfig @@ -5,6 +5,7 @@ config SYS_BOARD_VERSION 2 version 2 3 version 2b 4 version 2bcsl + 5 version 2c
config SYS_I2C_MXC_I2C1 default y diff --git a/configs/aristainetos2c_defconfig b/configs/aristainetos2c_defconfig new file mode 100644 index 0000000000..46a3cf7298 --- /dev/null +++ b/configs/aristainetos2c_defconfig @@ -0,0 +1,115 @@ +CONFIG_ARM=y +CONFIG_SYS_THUMB_BUILD=y +CONFIG_ARCH_MX6=y +CONFIG_SYS_TEXT_BASE=0x17800000 +CONFIG_SYS_MALLOC_F_LEN=0xe000 +CONFIG_ENV_SIZE=0x3000 +CONFIG_ENV_OFFSET=0xD0000 +CONFIG_TARGET_ARISTAINETOS2C=y +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SECT_SIZE=0x10000 +CONFIG_IMX_HAB=y +# CONFIG_CMD_DEKBLOB is not set +CONFIG_FIT=y +CONFIG_SYS_EXTRA_OPTIONS="IMX_CONFIG=board/aristainetos/aristainetos2.cfg" +CONFIG_BOOTDELAY=3 +CONFIG_USE_BOOTCOMMAND=y +CONFIG_BOOTCOMMAND="run ari_boot" +# CONFIG_CONSOLE_MUX is not set +CONFIG_SYS_CONSOLE_IS_IN_ENV=y +CONFIG_SUPPORT_RAW_INITRD=y +CONFIG_VERSION_VARIABLE=y +CONFIG_BOUNCE_BUFFER=y +CONFIG_BOARD_TYPES=y +CONFIG_BOARD_EARLY_INIT_F=y +CONFIG_HUSH_PARSER=y +CONFIG_AUTOBOOT_KEYED=y +CONFIG_AUTOBOOT_ENCRYPTION=y +CONFIG_AUTOBOOT_STOP_STR_SHA256="30bb0bce5f77da71a6e8e436fe40af54bc823db9501ae170f77e9992499d88fb" +CONFIG_CMD_BOOTZ=y +# CONFIG_BOOTM_NETBSD is not set +# CONFIG_BOOTM_PLAN9 is not set +# CONFIG_BOOTM_RTEMS is not set +# CONFIG_BOOTM_VXWORKS is not set +# CONFIG_CMD_FLASH is not set +CONFIG_CMD_GPIO=y +CONFIG_CMD_I2C=y +CONFIG_CMD_MMC=y +# CONFIG_CMD_PINMUX is not set +# CONFIG_CMD_SATA is not set +CONFIG_CMD_USB=y +CONFIG_CMD_DHCP=y +CONFIG_CMD_MII=y +CONFIG_CMD_PING=y +CONFIG_CMD_BMP=y +CONFIG_CMD_CACHE=y +# CONFIG_CMD_HASH is not set +CONFIG_CMD_EXT2=y +CONFIG_CMD_EXT4=y +CONFIG_CMD_EXT4_WRITE=y +CONFIG_CMD_FAT=y +CONFIG_CMD_FS_GENERIC=y +CONFIG_CMD_MTDPARTS=y +CONFIG_CMD_UBI=y +CONFIG_OF_CONTROL=y +CONFIG_DEFAULT_DEVICE_TREE="imx6dl-aristainetos2c_4" +CONFIG_OF_LIST="imx6dl-aristainetos2c_4 imx6dl-aristainetos2c_7" +CONFIG_DTB_RESELECT=y +CONFIG_MULTI_DTB_FIT=y +CONFIG_ENV_IS_IN_SPI_FLASH=y +CONFIG_ENV_SPI_EARLY=y +CONFIG_SYS_REDUNDAND_ENVIRONMENT=y +CONFIG_ENV_OFFSET_REDUND=0xE0000 +CONFIG_SYS_RELOC_GD_ENV_ADDR=y +CONFIG_APBH_DMA=y +CONFIG_APBH_DMA_BURST=y +CONFIG_APBH_DMA_BURST8=y +CONFIG_DM_GPIO=y +CONFIG_GPIO_HOG=y +CONFIG_DM_PCA953X=y +CONFIG_DM_I2C=y +CONFIG_LED=y +CONFIG_LED_GPIO=y +CONFIG_MISC=y +CONFIG_I2C_EEPROM=y +CONFIG_DM_MMC=y +CONFIG_FSL_USDHC=y +CONFIG_MTD=y +CONFIG_MTD_DEVICE=y +CONFIG_DM_SPI_FLASH=y +CONFIG_SF_DEFAULT_MODE=0 +CONFIG_SF_DEFAULT_SPEED=20000000 +CONFIG_SPI_FLASH_STMICRO=y +CONFIG_SPI_FLASH_MTD=y +CONFIG_MTD_UBI_FASTMAP=y +CONFIG_MTD_UBI_FASTMAP_AUTOCONVERT=1 +CONFIG_PHYLIB=y +CONFIG_PHY_MICREL=y +CONFIG_PHY_MICREL_KSZ90X1=y +CONFIG_DM_ETH=y +CONFIG_MII=y +CONFIG_PHY=y +CONFIG_PINCTRL=y +CONFIG_PINCTRL_IMX6=y +CONFIG_DM_PMIC=y +CONFIG_DM_REGULATOR=y +CONFIG_DM_REGULATOR_FIXED=y +CONFIG_DM_PWM=y +CONFIG_PWM_IMX=y +CONFIG_DM_RTC=y +CONFIG_RTC_DS1307=y +CONFIG_DM_SERIAL=y +CONFIG_SPI=y +CONFIG_DM_SPI=y +CONFIG_MXC_SPI=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_WATCHDOG=y +CONFIG_USB=y +CONFIG_DM_USB=y +CONFIG_USB_STORAGE=y +CONFIG_DM_VIDEO=y +CONFIG_SYS_WHITE_ON_BLACK=y +CONFIG_DISPLAY=y +CONFIG_VIDEO_IPUV3=y +CONFIG_IMX_WATCHDOG=y +# CONFIG_EFI_LOADER is not set diff --git a/include/configs/aristainetos2.h b/include/configs/aristainetos2.h index 64a819df13..5f4a4f854f 100644 --- a/include/configs/aristainetos2.h +++ b/include/configs/aristainetos2.h @@ -128,6 +128,33 @@ "${fit_file}\0" \ "rescue_load_fit=ext4load mmc ${mmcdev}:${mmcrescuepart} " \ "${fit_addr_r} ${rescue_fit_file}\0" +#elif (CONFIG_SYS_BOARD_VERSION == 5) +#define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ + "emmcpart=1\0" \ + "emmc_rescue_part=3\0" \ + "emmcdev=1\0" \ + "emmcroot=/dev/mmcblk1p1 rootwait rw\0" \ + "dead=led led_red on\0" \ + "mtdids=nor0=spi0.0\0" \ + "mtdparts=mtdparts=spi0.0:832k(u-boot),64k(env),64k(env-red)," \ + "-(ubi-nor)\0" \ + "addmisc=setenv bootargs ${bootargs} net.ifnames=0 consoleblank=0 " \ + "bootmode=${bootmode} mmcpart=${mmcpart} " \ + "emmcpart=${emmcpart}\0" \ + "mainboot=echo Booting from eMMC ...; " \ + "run mainargs addmtd addmisc;" \ + "if test -n ${addmiscM}; then run addmiscM;fi;" \ + "if test -n ${addmiscC}; then run addmiscC;fi;" \ + "if test -n ${addmiscD}; then run addmiscD;fi;" \ + "run boot_board_type;" \ + "bootm ${fit_addr_r}\0" \ + "mainargs=setenv bootargs console=${console},${baudrate} " \ + "root=${emmcroot} rootfstype=ext4\0 " \ + "main_load_fit=ext4load mmc ${emmcdev}:${emmcpart} ${fit_addr_r} " \ + "${fit_file}; " \ + "imi ${fit_addr_r}\0 " \ + "rescue_load_fit=ext4load mmc ${emmcdev}:${emmc_rescue_part} " \ + "${fit_addr_r} ${rescue_fit_file};imi ${fit_addr_r}\0" #else #define CONFIG_EXTRA_ENV_BOARD_SETTINGS \ "dead=led led_red on\0" \
add support for revision C boards. This board has no longer a NAND. Signed-off-by: Heiko Schocher hs@denx.de
Applied to u-boot-imx, -next, thanks !
Best regards, Stefano Babic
participants (2)
-
Heiko Schocher -
sbabic＠denx.de