[U-Boot] [PATCH] crypto/fsl: fix BLOB encapsulation and decapsulation

The blob_encap and blob_decap functions were not flushing the dcache before passing data to CAAM/DMA and not invalidating the dcache when getting data back. Therefore, blob encapsulation and decapsulation failed with errors like the following due to data cache incoherency: "40000006: DECO: desc idx 0: Invalid KEY command"
To ensure coherency, we allocate aligned memory to store the data passed to/from CAAM and flush/invalidate the memory regions. Blobs can now be encapsulated and decapsulated with the blob cmd as well as from board code by calling blob_encap and blob_decap directly.
Tested on an i.MX6Q board.
Signed-off-by: Clemens Gruber clemens.gruber@pqgruber.com --- drivers/crypto/fsl/fsl_blob.c | 99 ++++++++++++++++++++++++++++++++++++------- 1 file changed, 83 insertions(+), 16 deletions(-)
diff --git a/drivers/crypto/fsl/fsl_blob.c b/drivers/crypto/fsl/fsl_blob.c index 38c6f9486b..65ce21f4af 100644 --- a/drivers/crypto/fsl/fsl_blob.c +++ b/drivers/crypto/fsl/fsl_blob.c @@ -7,6 +7,7 @@
#include <common.h> #include <malloc.h> +#include <memalign.h> #include <fsl_sec.h> #include <linux/errno.h> #include "jobdesc.h" @@ -15,56 +16,122 @@
int blob_decap(u8 *key_mod, u8 *src, u8 *dst, u32 len) { - int ret, i = 0; + ALLOC_CACHE_ALIGN_BUFFER(u8, aligned_key_mod, 16); + u8 *aligned_src, *aligned_dst; + int ret, size, i = 0; u32 *desc;
printf("\nDecapsulating blob to get data\n"); - desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE); + desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE); if (!desc) { debug("Not enough memory for descriptor allocation\n"); - return -1; + return -ENOMEM; }
- inline_cnstr_jobdesc_blob_decap(desc, key_mod, src, dst, len); + aligned_src = malloc_cache_aligned(BLOB_SIZE(len)); + aligned_dst = malloc_cache_aligned(len); + if (!aligned_src || !aligned_dst) { + debug("Not enough memory for blob allocations\n"); + return -ENOMEM; + } + + memcpy(aligned_key_mod, key_mod, 16); + size = ALIGN(16, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)aligned_key_mod, + (unsigned long)aligned_key_mod + size); + + memcpy(aligned_src, src, BLOB_SIZE(len)); + size = ALIGN(BLOB_SIZE(len), ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)aligned_src, + (unsigned long)aligned_src + size); + + inline_cnstr_jobdesc_blob_decap(desc, aligned_key_mod, aligned_src, + aligned_dst, len);
debug("Descriptor dump:\n"); for (i = 0; i < 14; i++) debug("Word[%d]: %08x\n", i, *(desc + i)); + + size = ALIGN(sizeof(int) * MAX_CAAM_DESCSIZE, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)desc, + (unsigned long)desc + size); + ret = run_descriptor_jr(desc);
- if (ret) - printf("Error in Decapsulation %d\n", ret); - else - printf("Decapsulation Success\n"); + if (ret) { + printf("Error in blob decapsulation: %d\n", ret); + } else { + size = ALIGN(len, ARCH_DMA_MINALIGN); + invalidate_dcache_range((unsigned long)aligned_dst, + (unsigned long)aligned_dst + size); + memcpy(dst, aligned_dst, len); + + puts("Blob decapsulation successful.\n"); + }
+ free(aligned_dst); + free(aligned_src); free(desc); return ret; }
int blob_encap(u8 *key_mod, u8 *src, u8 *dst, u32 len) { - int ret, i = 0; + ALLOC_CACHE_ALIGN_BUFFER(u8, aligned_key_mod, 16); + u8 *aligned_src, *aligned_dst; + int ret, size, i = 0; u32 *desc;
printf("\nEncapsulating data to form blob\n"); - desc = malloc(sizeof(int) * MAX_CAAM_DESCSIZE); + desc = malloc_cache_aligned(sizeof(int) * MAX_CAAM_DESCSIZE); if (!desc) { debug("Not enough memory for descriptor allocation\n"); - return -1; + return -ENOMEM; }
- inline_cnstr_jobdesc_blob_encap(desc, key_mod, src, dst, len); + aligned_src = malloc_cache_aligned(len); + aligned_dst = malloc_cache_aligned(BLOB_SIZE(len)); + if (!aligned_src || !aligned_dst) { + debug("Not enough memory for blob allocations\n"); + return -ENOMEM; + } + + memcpy(aligned_key_mod, key_mod, 16); + size = ALIGN(16, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)aligned_key_mod, + (unsigned long)aligned_key_mod + size); + + memcpy(aligned_src, src, len); + size = ALIGN(len, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)aligned_src, + (unsigned long)aligned_src + size); + + inline_cnstr_jobdesc_blob_encap(desc, aligned_key_mod, aligned_src, + aligned_dst, len);
debug("Descriptor dump:\n"); for (i = 0; i < 14; i++) debug("Word[%d]: %08x\n", i, *(desc + i)); + + size = ALIGN(sizeof(int) * MAX_CAAM_DESCSIZE, ARCH_DMA_MINALIGN); + flush_dcache_range((unsigned long)desc, + (unsigned long)desc + size); + ret = run_descriptor_jr(desc);
- if (ret) - printf("Error in Encapsulation %d\n", ret); - else - printf("Encapsulation Success\n"); + if (ret) { + printf("Error in blob encapsulation: %d\n", ret); + } else { + size = ALIGN(BLOB_SIZE(len), ARCH_DMA_MINALIGN); + invalidate_dcache_range((unsigned long)aligned_dst, + (unsigned long)aligned_dst + size); + memcpy(dst, aligned_dst, BLOB_SIZE(len)); + + puts("Blob encapsulation successful.\n"); + }
+ free(aligned_dst); + free(aligned_src); free(desc); return ret; }

Hi Clemens,
2017-12-20 20:08 GMT-02:00 Clemens Gruber clemens.gruber@pqgruber.com:
The blob_encap and blob_decap functions were not flushing the dcache before passing data to CAAM/DMA and not invalidating the dcache when getting data back. Therefore, blob encapsulation and decapsulation failed with errors like the following due to data cache incoherency: "40000006: DECO: desc idx 0: Invalid KEY command"
To ensure coherency, we allocate aligned memory to store the data passed to/from CAAM and flush/invalidate the memory regions. Blobs can now be encapsulated and decapsulated with the blob cmd as well as from board code by calling blob_encap and blob_decap directly.
Tested on an i.MX6Q board.
I tested your patch on a closed i.MX6QSabreAuto and the functions blob_encap() and blob_decap() are working fine. In my environment I had to add a small modification in function do_blob() in cmd/blob.c file to get the cmd blob working:
+ hab_caam_clock_enable(1); + sec_init();
I will investigate this and provide a fix.
Signed-off-by: Clemens Gruber clemens.gruber@pqgruber.com
Tested-by: Breno Lima breno.lima@nxp.com
Thanks

Hi Breno,
On Thu, Dec 21, 2017 at 07:18:44PM -0200, Breno Matheus Lima wrote:
Hi Clemens,
2017-12-20 20:08 GMT-02:00 Clemens Gruber clemens.gruber@pqgruber.com:
The blob_encap and blob_decap functions were not flushing the dcache before passing data to CAAM/DMA and not invalidating the dcache when getting data back. Therefore, blob encapsulation and decapsulation failed with errors like the following due to data cache incoherency: "40000006: DECO: desc idx 0: Invalid KEY command"
To ensure coherency, we allocate aligned memory to store the data passed to/from CAAM and flush/invalidate the memory regions. Blobs can now be encapsulated and decapsulated with the blob cmd as well as from board code by calling blob_encap and blob_decap directly.
Tested on an i.MX6Q board.
I tested your patch on a closed i.MX6QSabreAuto and the functions blob_encap() and blob_decap() are working fine.
Thanks for testing!
In my environment I had to add a small modification in function do_blob() in cmd/blob.c file to get the cmd blob working:
hab_caam_clock_enable(1);
sec_init();
I will investigate this and provide a fix.
Yes, I did need these two too and put them in my board code. But it's probably better to do this in do_blob, otherwise the command won't work as is for most boards and changing all of them is probably not an option. Thank you for looking into it.
Cheers, Clemens
Signed-off-by: Clemens Gruber clemens.gruber@pqgruber.com
Tested-by: Breno Lima breno.lima@nxp.com
Thanks

Hi Tom,
On Wed, Dec 20, 2017 at 8:08 PM, Clemens Gruber clemens.gruber@pqgruber.com wrote:
The blob_encap and blob_decap functions were not flushing the dcache before passing data to CAAM/DMA and not invalidating the dcache when getting data back. Therefore, blob encapsulation and decapsulation failed with errors like the following due to data cache incoherency: "40000006: DECO: desc idx 0: Invalid KEY command"
To ensure coherency, we allocate aligned memory to store the data passed to/from CAAM and flush/invalidate the memory regions. Blobs can now be encapsulated and decapsulated with the blob cmd as well as from board code by calling blob_encap and blob_decap directly.
Tested on an i.MX6Q board.
Signed-off-by: Clemens Gruber clemens.gruber@pqgruber.com
This bug fix patch seems like a good candidate for 2018.01.
Not sure who can pick it and apply it.
Tom, York? What do you guys think?
Thanks

On Wed, Jan 03, 2018 at 02:32:44PM -0200, Fabio Estevam wrote:
Hi Tom,
On Wed, Dec 20, 2017 at 8:08 PM, Clemens Gruber clemens.gruber@pqgruber.com wrote:
The blob_encap and blob_decap functions were not flushing the dcache before passing data to CAAM/DMA and not invalidating the dcache when getting data back. Therefore, blob encapsulation and decapsulation failed with errors like the following due to data cache incoherency: "40000006: DECO: desc idx 0: Invalid KEY command"
To ensure coherency, we allocate aligned memory to store the data passed to/from CAAM and flush/invalidate the memory regions. Blobs can now be encapsulated and decapsulated with the blob cmd as well as from board code by calling blob_encap and blob_decap directly.
Tested on an i.MX6Q board.
Signed-off-by: Clemens Gruber clemens.gruber@pqgruber.com
This bug fix patch seems like a good candidate for 2018.01.
Not sure who can pick it and apply it.
Tom, York? What do you guys think?
I'm fine with it coming in directly or via a PR.

Hi York,
On Wed, Jan 3, 2018 at 3:26 PM, Tom Rini trini@konsulko.com wrote:
On Wed, Jan 03, 2018 at 02:32:44PM -0200, Fabio Estevam wrote:
Hi Tom,
On Wed, Dec 20, 2017 at 8:08 PM, Clemens Gruber clemens.gruber@pqgruber.com wrote:
The blob_encap and blob_decap functions were not flushing the dcache before passing data to CAAM/DMA and not invalidating the dcache when getting data back. Therefore, blob encapsulation and decapsulation failed with errors like the following due to data cache incoherency: "40000006: DECO: desc idx 0: Invalid KEY command"
To ensure coherency, we allocate aligned memory to store the data passed to/from CAAM and flush/invalidate the memory regions. Blobs can now be encapsulated and decapsulated with the blob cmd as well as from board code by calling blob_encap and blob_decap directly.
Tested on an i.MX6Q board.
Signed-off-by: Clemens Gruber clemens.gruber@pqgruber.com
This bug fix patch seems like a good candidate for 2018.01.
Not sure who can pick it and apply it.
Tom, York? What do you guys think?
I'm fine with it coming in directly or via a PR.
Could you please help applying this one?
Thanks

On 01/04/2018 01:39 AM, Fabio Estevam wrote:
Hi York,
On Wed, Jan 3, 2018 at 3:26 PM, Tom Rini trini@konsulko.com wrote:
On Wed, Jan 03, 2018 at 02:32:44PM -0200, Fabio Estevam wrote:
Hi Tom,
On Wed, Dec 20, 2017 at 8:08 PM, Clemens Gruber clemens.gruber@pqgruber.com wrote:
The blob_encap and blob_decap functions were not flushing the dcache before passing data to CAAM/DMA and not invalidating the dcache when getting data back. Therefore, blob encapsulation and decapsulation failed with errors like the following due to data cache incoherency: "40000006: DECO: desc idx 0: Invalid KEY command"
To ensure coherency, we allocate aligned memory to store the data passed to/from CAAM and flush/invalidate the memory regions. Blobs can now be encapsulated and decapsulated with the blob cmd as well as from board code by calling blob_encap and blob_decap directly.
Tested on an i.MX6Q board.
Signed-off-by: Clemens Gruber clemens.gruber@pqgruber.com
This bug fix patch seems like a good candidate for 2018.01.
Not sure who can pick it and apply it.
Tom, York? What do you guys think?
I'm fine with it coming in directly or via a PR.
Could you please help applying this one?
Sorry for late reply. Trying to catch up after my vacation. I have kicked off compiling tests. Will send a PR if everything is fine.
York

On 01/04/2018 09:15 AM, York Sun wrote:
On 01/04/2018 01:39 AM, Fabio Estevam wrote:
Hi York,
On Wed, Jan 3, 2018 at 3:26 PM, Tom Rini trini@konsulko.com wrote:
On Wed, Jan 03, 2018 at 02:32:44PM -0200, Fabio Estevam wrote:
Hi Tom,
On Wed, Dec 20, 2017 at 8:08 PM, Clemens Gruber clemens.gruber@pqgruber.com wrote:
The blob_encap and blob_decap functions were not flushing the dcache before passing data to CAAM/DMA and not invalidating the dcache when getting data back. Therefore, blob encapsulation and decapsulation failed with errors like the following due to data cache incoherency: "40000006: DECO: desc idx 0: Invalid KEY command"
To ensure coherency, we allocate aligned memory to store the data passed to/from CAAM and flush/invalidate the memory regions. Blobs can now be encapsulated and decapsulated with the blob cmd as well as from board code by calling blob_encap and blob_decap directly.
Tested on an i.MX6Q board.
Signed-off-by: Clemens Gruber clemens.gruber@pqgruber.com
This bug fix patch seems like a good candidate for 2018.01.
Not sure who can pick it and apply it.
Tom, York? What do you guys think?
I'm fine with it coming in directly or via a PR.
Could you please help applying this one?
Sorry for late reply. Trying to catch up after my vacation. I have kicked off compiling tests. Will send a PR if everything is fine.
This patch causes errors in almost all Freescale secure boot targets, including ls2080aqds_SECURE_BOOT ls1088ardb_qspi_SECURE_BOOT ls2080ardb_SECURE_BOOT ls1043ardb_sdcard_SECURE_BOOT ls1043ardb_SECURE_BOOT ls1088aqds_qspi_SECURE_BOOT ls1012ardb_qspi_SECURE_BOOT ls1046aqds_SECURE_BOOT ls1043ardb_nand_SECURE_BOOT ls1046ardb_sdcard_SECURE_BOOT ls1046ardb_qspi_SECURE_BOOT ls2088ardb_qspi_SECURE_BOOT BSC9132QDS_NAND_DDRCLK133_SECURE P5040DS_NAND_SECURE_BOOT P1010RDB-PA_36BIT_SPIFLASH_SECBOOT T1040QDS_SECURE_BOOT P1010RDB-PA_36BIT_NOR_SECBOOT P2041RDB_SECURE_BOOT P1010RDB-PB_NOR_SECBOOT B4860QDS_SECURE_BOOT P5020DS_NAND_SECURE_BOOT T2080RDB_SECURE_BOOT P4080DS_SECURE_BOOT T2080QDS_SECURE_BOOT BSC9132QDS_NOR_DDRCLK100_SECURE P5020DS_SECURE_BOOT P5040DS_SECURE_BOOT P3041DS_SECURE_BOOT C29XPCIE_NOR_SECBOOT BSC9132QDS_NAND_DDRCLK100_SECURE C29XPCIE_SPIFLASH_SECBOOT T1024RDB_SECURE_BOOT P1010RDB-PB_36BIT_NAND_SECBOOT T1042D4RDB_SECURE_BOOT P1010RDB-PA_NAND_SECBOOT P1010RDB-PB_SPIFLASH_SECBOOT T1024QDS_DDR4_SECURE_BOOT T1042RDB_SECURE_BOOT T4240QDS_SECURE_BOOT P1010RDB-PA_36BIT_NAND_SECBOOT T1042RDB_PI_NAND_SECURE_BOOT T1040RDB_SECURE_BOOT P1010RDB-PB_36BIT_SPIFLASH_SECBOOT P1010RDB-PB_36BIT_NOR_SECBOOT BSC9132QDS_SDCARD_DDRCLK133_SECURE BSC9132QDS_SPIFLASH_DDRCLK100_SECURE BSC9132QDS_SDCARD_DDRCLK100_SECURE P3041DS_NAND_SECURE_BOOT BSC9132QDS_SPIFLASH_DDRCLK133_SECURE P1010RDB-PA_NOR_SECBOOT T1024QDS_SECURE_BOOT T1040D4RDB_SECURE_BOOT P1010RDB-PB_NAND_SECBOOT T4160QDS_SECURE_BOOT P1010RDB-PA_SPIFLASH_SECBOOT BSC9132QDS_NOR_DDRCLK133_SECURE T1023RDB_SECURE_BOOT
The error is undefined reference to `BLOB_SIZE'. Please fix.
York

Hi York,
On Thu, Jan 4, 2018 at 7:12 PM, York Sun york.sun@nxp.com wrote:
This patch causes errors in almost all Freescale secure boot targets,
...
The error is undefined reference to `BLOB_SIZE'. Please fix.
You are right. The BLOB_SIZE() macro is currently only defined for imx.
Clemens,
Please include the change below within your patch:
--- a/include/fsl_sec.h +++ b/include/fsl_sec.h @@ -215,6 +215,8 @@ struct sg_entry { #define SG_ENTRY_OFFSET_SHIFT 0 };
+#define BLOB_SIZE(x) (x + 32 + 16) /* Blob buffer size */ + #if defined(CONFIG_MX6) || defined(CONFIG_MX7) /* Job Ring Base Address */ #define JR_BASE_ADDR(x) (CONFIG_SYS_FSL_SEC_ADDR + 0x1000 * (x + 1)) @@ -274,8 +276,6 @@ struct sg_entry { #define PERM 0x0000B008 /* Clear on release, lock SMAP * lock SMAG group 1 Blob */
-#define BLOB_SIZE(x) (x + 32 + 16) /* Blob buffer size */ - /* HAB WRAPPED KEY header */ #define WRP_HDR_SIZE 0x08 #define HDR_TAG 0x81
Thanks

Hi Clemens,
On Thu, Jan 4, 2018 at 7:31 PM, Fabio Estevam festevam@gmail.com wrote:
Hi York,
On Thu, Jan 4, 2018 at 7:12 PM, York Sun york.sun@nxp.com wrote:
This patch causes errors in almost all Freescale secure boot targets,
...
The error is undefined reference to `BLOB_SIZE'. Please fix.
You are right. The BLOB_SIZE() macro is currently only defined for imx.
Clemens,
Please include the change below within your patch:
Nevermind. I did a v2 with this change integrated and now it can build ls2080ardb_SECURE_BOOT_defconfig.

Hi Fabio, Hi York,
On Thu, Jan 04, 2018 at 07:59:13PM -0200, Fabio Estevam wrote:
Hi Clemens,
On Thu, Jan 4, 2018 at 7:31 PM, Fabio Estevam festevam@gmail.com wrote:
Hi York,
On Thu, Jan 4, 2018 at 7:12 PM, York Sun york.sun@nxp.com wrote:
This patch causes errors in almost all Freescale secure boot targets,
...
The error is undefined reference to `BLOB_SIZE'. Please fix.
You are right. The BLOB_SIZE() macro is currently only defined for imx.
Clemens,
Please include the change below within your patch:
Nevermind. I did a v2 with this change integrated and now it can build ls2080ardb_SECURE_BOOT_defconfig.
Thanks for fixing up my patch and sorry for not noticing the breakage of other configs. Will use buildman the next time I send a patch!
Cheers, Clemens
participants (5)
-
Breno Matheus Lima
-
Clemens Gruber
-
Fabio Estevam
-
Tom Rini
-
York Sun