[PATCH v5 1/2] arm: mediatek: add mt8195 SOC support
From: Fabien Parent fparent@baylibre.com
The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts, SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options.
Signed-off-by: Fabien Parent fparent@baylibre.com Signed-off-by: Macpaul Lin macpaul.lin@mediatek.com --- MAINTAINERS | 2 + arch/arm/dts/mt8195.dtsi | 370 +++++++++++++++++++++++++ arch/arm/mach-mediatek/Kconfig | 13 +- arch/arm/mach-mediatek/Makefile | 1 + arch/arm/mach-mediatek/mt8195/Kconfig | 13 + arch/arm/mach-mediatek/mt8195/Makefile | 3 + arch/arm/mach-mediatek/mt8195/init.c | 97 +++++++ 7 files changed, 498 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/mt8195.dtsi create mode 100644 arch/arm/mach-mediatek/mt8195/Kconfig create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
Changes for v2: - Correct node name to t-phy for u3phy0. - Add platform compatible string "mediatek,mt8195-tphy" to all usb phy nodes. - remove clock nodes that software cannot controlled in phy nodes. - Test and add back "mac" for HOST only xhci nodes.
Changes for v3: - Revise device node name from "xhciX: xhciX@" to "xhciX: xhci@".
Changes for v4: - No change.
Changes for v5: - Fix Copyright year to 2023. - Fix memory map in dram_init() to support 8GB onboard memory. - Add '#if !IS_ENABLED(CONFIG_SYSRESET)' with reset_cpu(). - Correct reset_cpu() function prototype. - rebase patchset to v2023-10.rc1 - Add missing arch/arm/mach-mediatek/mt8195/Kconfig.
diff --git a/MAINTAINERS b/MAINTAINERS index 47581cf6fb..4d0f017e7e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -369,8 +369,10 @@ ARM MEDIATEK M: Ryder Lee ryder.lee@mediatek.com M: Weijie Gao weijie.gao@mediatek.com M: Chunfeng Yun chunfeng.yun@mediatek.com +M: Macpaul Lin macpaul.lin@mediatek.com R: GSS_MTK_Uboot_upstream GSS_MTK_Uboot_upstream@mediatek.com S: Maintained +F: arch/arm/dts/mt8195.dtsi F: arch/arm/mach-mediatek/ F: arch/arm/include/asm/arch-mediatek/ F: board/mediatek/ diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi new file mode 100644 index 0000000000..14cb28d008 --- /dev/null +++ b/arch/arm/dts/mt8195.dtsi @@ -0,0 +1,370 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2023 MediaTek Inc. + * Copyright (C) 2023 BayLibre, SAS + * Author: Ben Ho ben.ho@mediatek.com + * Erin Lo erin.lo@mediatek.com + * Fabien Parent fparent@baylibre.com + * Macpaul Lin macpaul.lin@mediatek.com + */ + +#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/phy/phy.h> + +/ { + compatible = "mediatek,mt8195"; + interrupt-parent = <&sysirq>; + #address-cells = <2>; + #size-cells = <2>; + + cpus { + #address-cells = <1>; + #size-cells = <0>; + + cpu-map { + cluster0 { + core0 { + cpu = <&cpu0>; + }; + core1 { + cpu = <&cpu1>; + }; + core2 { + cpu = <&cpu2>; + }; + core3 { + cpu = <&cpu3>; + }; + }; + + cluster1 { + core0 { + cpu = <&cpu4>; + }; + core1 { + cpu = <&cpu5>; + }; + core2 { + cpu = <&cpu6>; + }; + core3 { + cpu = <&cpu7>; + }; + }; + }; + + cpu0: cpu@0 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x000>; + enable-method = "psci"; + capacity-dmips-mhz = <741>; + }; + + cpu1: cpu@1 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x001>; + enable-method = "psci"; + capacity-dmips-mhz = <741>; + }; + + cpu2: cpu@2 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x002>; + enable-method = "psci"; + capacity-dmips-mhz = <741>; + }; + + cpu3: cpu@3 { + device_type = "cpu"; + compatible = "arm,cortex-a53"; + reg = <0x003>; + enable-method = "psci"; + capacity-dmips-mhz = <741>; + }; + + cpu4: cpu@100 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x100>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + }; + + cpu5: cpu@101 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x101>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + }; + + cpu6: cpu@102 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x102>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + }; + + cpu7: cpu@103 { + device_type = "cpu"; + compatible = "arm,cortex-a73"; + reg = <0x103>; + enable-method = "psci"; + capacity-dmips-mhz = <1024>; + }; + }; + + clk26m: oscillator { + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <26000000>; + clock-output-names = "clk26m"; + }; + + mmc_source_clk: mmc-source-clk{ + compatible = "fixed-clock"; + #clock-cells = <0>; + clock-frequency = <400000000>; + clock-output-names = "mmc_source_clk"; + }; + + soc { + #address-cells = <2>; + #size-cells = <2>; + compatible = "simple-bus"; + ranges; + + watchdog: watchdog@10007000 { + compatible = "mediatek,mt8195-wdt", + "mediatek,wdt"; + reg = <0 0x10007000 0 0x100>; + status = "disabled"; + }; + + gic: interrupt-controller@c000000 { + compatible = "arm,gic-v3"; + #interrupt-cells = <4>; + interrupt-parent = <&gic>; + interrupt-controller; + reg = <0 0x0c000000 0 0x40000>, /* GICD */ + <0 0x0c100000 0 0x200000>, /* GICR */ + <0 0x0c400000 0 0x2000>, /* GICC */ + <0 0x0c410000 0 0x1000>, /* GICH */ + <0 0x0c420000 0 0x2000>; /* GICV */ + + interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>; + ppi-partitions { + ppi_cluster0: interrupt-partition-0 { + affinity = <&cpu0 &cpu1 &cpu2 &cpu3>; + }; + ppi_cluster1: interrupt-partition-1 { + affinity = <&cpu4 &cpu5 &cpu6 &cpu7>; + }; + }; + }; + + sysirq: interrupt-controller@c530a80 { + compatible = "mediatek,mt8195-sysirq", + "mediatek,mt6577-sysirq"; + interrupt-controller; + #interrupt-cells = <3>; + interrupt-parent = <&gic>; + reg = <0 0x0c530a80 0 0x50>; + }; + + topckgen: syscon@10000000 { + compatible = "mediatek,mt8195-topckgen", "syscon"; + reg = <0 0x10000000 0 0x1000>; + #clock-cells = <1>; + }; + + infracfg: syscon@10001000 { + compatible = "mediatek,mt8195-infracfg", "syscon"; + reg = <0 0x10001000 0 0x1000>; + #clock-cells = <1>; + }; + + apmixedsys: syscon@1000c000 { + compatible = "mediatek,mt8195-apmixedsys", "syscon"; + reg = <0 0x1000c000 0 0x1000>; + #clock-cells = <1>; + }; + + uart0: serial@11001100 { + compatible = "mediatek,mt8195-uart", + "mediatek,hsuart"; + reg = <0 0x11001100 0 0x1000>; + interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>; + clock-frequency = <26000000>; + clocks = <&clk26m>, <&clk26m>; + clock-names = "baud", "bus"; + status = "disabled"; + }; + + mmc0: mmc@11230000 { + compatible = "mediatek,mt8195-mmc", + "mediatek,mt8183-mmc"; + reg = <0 0x11230000 0 0x1000>, + <0 0x11f50000 0 0x1000>; + interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>; + clocks = <&mmc_source_clk>, + <&clk26m>, + <&clk26m>; + clock-names = "source", "hclk", "source_cg"; + status = "disabled"; + }; + + u3phy0: t-phy@11f40000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e40000 0xe00>; + status = "okay"; + + u2port0: usb-phy@0 { + reg = <0 0x700>; + #phy-cells = <1>; + status = "okay"; + }; + + u3port0: usb-phy@700 { + reg = <0x700 0x700>; + #phy-cells = <1>; + status = "okay"; + }; + }; + + usb: usb@11200000 { + compatible ="mediatek,mt8195-mtu3", "mediatek,mtu3"; + reg = <0 0x11203e00 0 0x0100>; + reg-names = "ippc"; + phys = <&u2port0 PHY_TYPE_USB2>; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "sys_ck", "ref_ck", "mcu_ck"; + #address-cells = <2>; + #size-cells = <2>; + ranges; + status = "disabled"; + + ssusb: ssusb@11200000 { + compatible = "mediatek,ssusb"; + reg = <0 0x11200000 0 0x3e00>; + reg-names = "mac"; + interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>; + status = "disabled"; + }; + + xhci0: xhci@11200000 { + compatible = "mediatek,mtk-xhci"; + reg = <0 0x11200000 0 0x1000>; + reg-names = "mac"; + interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck"; + status = "disabled"; + }; + }; + + u3phy1: t-phy@11e30000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11e30000 0xe00>; + status = "disabled"; + + u2port1: usb-phy@0 { + reg = <0x0 0x700>; + #phy-cells = <1>; + }; + + u3port1: usb-phy@700 { + reg = <0x700 0x700>; + #phy-cells = <1>; + }; + }; + + xhci1: xhci@11290000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x11290000 0 0x1000>, + <0 0x11293e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>; + phys = <&u2port1 PHY_TYPE_USB2>; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck"; + status = "disabled"; + }; + + u3phy2: t-phy@11c40000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11c40000 0x700>; + status = "disabled"; + + u2port2: usb-phy@0 { + reg = <0x0 0x700>; + #phy-cells = <1>; + }; + }; + + xhci2: xhci@112a0000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x112a0000 0 0x1000>, + <0 0x112a3e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>; + phys = <&u2port2 PHY_TYPE_USB2>; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + status = "disabled"; + }; + + u3phy3: t-phy@11c50000 { + compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2"; + #address-cells = <1>; + #size-cells = <1>; + ranges = <0 0 0x11c50000 0x700>; + status = "okay"; + + u2port3: usb-phy@0 { + reg = <0x0 0x700>; + #phy-cells = <1>; + }; + }; + + xhci3: xhci@112b0000 { + compatible = "mediatek,mt8195-xhci", + "mediatek,mtk-xhci"; + reg = <0 0x112b0000 0 0x1000>, + <0 0x112b3e00 0 0x0100>; + reg-names = "mac", "ippc"; + interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>; + phys = <&u2port3 PHY_TYPE_USB2>; + clocks = <&clk26m>, + <&clk26m>, + <&clk26m>; + clock-names = "sys_ck", "xhci_ck", "ref_ck"; + usb2-lpm-disable; + status = "disabled"; + }; + }; +}; diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 04aa2fd97f..3a2af1cdee 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -67,6 +67,15 @@ config TARGET_MT8183 SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options.
+config TARGET_MT8195 + bool "MediaTek MT8195 SoC" + select ARM64 + help + The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and + a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts, + SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3 + and LPDDR4 options. + config TARGET_MT8512 bool "MediaTek MT8512 M1 Board" select ARM64 @@ -105,6 +114,7 @@ config SYS_BOARD default "mt7981" if TARGET_MT7981 default "mt7986" if TARGET_MT7986 default "mt8183" if TARGET_MT8183 + default "mt8195" if TARGET_MT8195 default "mt8512" if TARGET_MT8512 default "mt8516" if TARGET_MT8516 default "mt8518" if TARGET_MT8518 @@ -122,6 +132,7 @@ config SYS_CONFIG_NAME default "mt7981" if TARGET_MT7981 default "mt7986" if TARGET_MT7986 default "mt8183" if TARGET_MT8183 + default "mt8195" if TARGET_MT8195 default "mt8512" if TARGET_MT8512 default "mt8516" if TARGET_MT8516 default "mt8518" if TARGET_MT8518 @@ -134,7 +145,7 @@ config SYS_CONFIG_NAME config MTK_BROM_HEADER_INFO string default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622 - default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 + default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 || TARGET_MT8195 default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 default "lk=1" if TARGET_MT7623
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index fc85293f71..fbbb5431d1 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -10,5 +10,6 @@ obj-$(CONFIG_TARGET_MT7629) += mt7629/ obj-$(CONFIG_TARGET_MT7981) += mt7981/ obj-$(CONFIG_TARGET_MT7986) += mt7986/ obj-$(CONFIG_TARGET_MT8183) += mt8183/ +obj-$(CONFIG_TARGET_MT8195) += mt8195/ obj-$(CONFIG_TARGET_MT8516) += mt8516/ obj-$(CONFIG_TARGET_MT8518) += mt8518/ diff --git a/arch/arm/mach-mediatek/mt8195/Kconfig b/arch/arm/mach-mediatek/mt8195/Kconfig new file mode 100644 index 0000000000..a34fa2cf2e --- /dev/null +++ b/arch/arm/mach-mediatek/mt8195/Kconfig @@ -0,0 +1,13 @@ +if TARGET_MT8195 + +config SYS_BOARD + default "mt8195" + +config SYS_CONFIG_NAME + default "mt8195" + +config MTK_BROM_HEADER_INFO + string + default "media=emmc" + +endif diff --git a/arch/arm/mach-mediatek/mt8195/Makefile b/arch/arm/mach-mediatek/mt8195/Makefile new file mode 100644 index 0000000000..886ab7e4eb --- /dev/null +++ b/arch/arm/mach-mediatek/mt8195/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += init.o diff --git a/arch/arm/mach-mediatek/mt8195/init.c b/arch/arm/mach-mediatek/mt8195/init.c new file mode 100644 index 0000000000..8d6b700e7e --- /dev/null +++ b/arch/arm/mach-mediatek/mt8195/init.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 MediaTek Inc. + * Copyright (C) 2023 BayLibre, SAS + * Author: Macpaul Lin macpaul.lin@mediatek.com + * Author: Fabien Parent fparent@baylibre.com + */ + +#include <clk.h> +#include <common.h> +#include <cpu_func.h> +#include <dm.h> +#include <fdtdec.h> +#include <ram.h> +#include <asm/arch/misc.h> +#include <asm/armv8/mmu.h> +#include <asm/sections.h> +#include <asm/system.h> +#include <dm/uclass.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init(void) +{ + int ret; + + ret = fdtdec_setup_memory_banksize(); + if (ret) + return ret; + + fdtdec_setup_mem_size_base(); + + /* + * Limit gd->ram_top not exceeding SZ_4G. + * Because some periphals like mmc requires DMA buffer + * allocaed below SZ_4G. + * + * Note: SZ_2M is for adjusting gd->relocaddr, + * the reserved memory for u-boot itself. + */ + if (gd->ram_base + gd->ram_size >= SZ_4G) + gd->mon_len = SZ_4G + gd->ram_base + SZ_2M; + + return 0; +} + +int dram_init_banksize(void) +{ + gd->bd->bi_dram[0].start = gd->ram_base; + gd->bd->bi_dram[0].size = gd->ram_size; + + return 0; +} + +int mtk_pll_early_init(void) +{ + return 0; +} + +int mtk_soc_early_init(void) +{ + return 0; +} + +#if !IS_ENABLED(CONFIG_SYSRESET) +void reset_cpu(void) +{ + psci_system_reset(); +} +#endif + +int print_cpuinfo(void) +{ + printf("CPU: MediaTek MT8195\n"); + return 0; +} + +static struct mm_region mt8195_mem_map[] = { + { + /* DDR */ + .virt = 0x40000000UL, + .phys = 0x40000000UL, + .size = 0x200000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE, + }, { + .virt = 0x00000000UL, + .phys = 0x00000000UL, + .size = 0x20000000UL, + .attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) | + PTE_BLOCK_NON_SHARE | + PTE_BLOCK_PXN | PTE_BLOCK_UXN + }, { + 0, + } +}; + +struct mm_region *mem_map = mt8195_mem_map;
From: Fabien Parent fparent@baylibre.com
Add mt8195-demo board support. This demo purpose board uses MediaTek's MT8195 SoC.
Signed-off-by: Fabien Parent fparent@baylibre.com Signed-off-by: Amjad Ouled-Ameur aouledameur@baylibre.com Signed-off-by: Macpaul Lin macpaul.lin@mediatek.com --- MAINTAINERS | 1 + arch/arm/dts/Makefile | 1 + arch/arm/dts/mt8195-demo.dts | 122 ++++++++++++++++++++++++++++ board/mediatek/mt8195/MAINTAINERS | 6 ++ board/mediatek/mt8195/Makefile | 3 + board/mediatek/mt8195/README | 65 +++++++++++++++ board/mediatek/mt8195/mt8195_demo.c | 38 +++++++++ configs/mt8195_demo_defconfig | 99 ++++++++++++++++++++++ include/configs/mt8195.h | 46 +++++++++++ 9 files changed, 381 insertions(+) create mode 100644 arch/arm/dts/mt8195-demo.dts create mode 100644 board/mediatek/mt8195/MAINTAINERS create mode 100644 board/mediatek/mt8195/Makefile create mode 100644 board/mediatek/mt8195/README create mode 100644 board/mediatek/mt8195/mt8195_demo.c create mode 100644 configs/mt8195_demo_defconfig create mode 100644 include/configs/mt8195.h
Changes for v2 and v3: - no change.
Changes for v4: - Remove CONFIG_SYS_NS16550 related settings in mt8195.h.
Changes for v5: - Fix Copyright year to 2023. - Fix build error by adding 'CONFIG_TEXT_BASE' in defconfig. - Add README for mt8195-demo board includes toolchain setting 'CROSS_COMPILE=aarch64-linux-gnu-' - Fix 'CONFIG_EXTRA_ENV_SETTINGS' with 'CFG_EXTRA_ENV_SETTINGS' according to checkpatch error. - Update dram to 8GB size. - dts - Add optee and pcsi support in firmware section. - mt8195_demo_defconfig - enable I2C, DFU, GPT, MBR support - enable some USB ethernet adaptors - rebase patchset to v2023-10.rc1
diff --git a/MAINTAINERS b/MAINTAINERS index 4d0f017e7e..454d3615f4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -396,6 +396,7 @@ F: drivers/watchdog/mtk_wdt.c F: drivers/net/mtk_eth.c F: drivers/net/mtk_eth.h F: drivers/reset/reset-mediatek.c +F: include/configs/mt8195.h F: tools/mtk_image.c F: tools/mtk_image.h F: tools/mtk_nand_headers.c diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e66c32e268..d7104b77bf 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1342,6 +1342,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7986a-emmc-rfb.dtb \ mt7986b-emmc-rfb.dtb \ mt8183-pumpkin.dtb \ + mt8195-demo.dtb \ mt8512-bm1-emmc.dtb \ mt8516-pumpkin.dtb \ mt8518-ap1-emmc.dtb diff --git a/arch/arm/dts/mt8195-demo.dts b/arch/arm/dts/mt8195-demo.dts new file mode 100644 index 0000000000..e4063cd143 --- /dev/null +++ b/arch/arm/dts/mt8195-demo.dts @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/* + * Copyright (C) 2023 MediaTek Inc. + * Copyright (C) 2023 BayLibre SAS. + * Author: Macpaul Lin macpaul.lin@mediatek.com + * Author: Fabien Parent fparent@baylibre.com + */ + +/dts-v1/; + +#include <config.h> +#include "mt8195.dtsi" + +/ { + model = "MediaTek MT8195 demo board"; + compatible = "mediatek,mt8195-demo", "mediatek,mt8195"; + + memory@40000000 { + /* 8GB */ + device_type = "memory"; + reg = <0 0x40000000 2 0x00000000>; + }; + + firmware: firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + + psci: psci { + compatible = "arm,psci-1.0"; + method = "smc"; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: secmon@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x200000>; + }; + + /* 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + }; + + chosen { + stdout-path = &uart0; + }; + + reg_1p8v: regulator-1p8v { + compatible = "regulator-fixed"; + regulator-name = "fixed-1.8V"; + regulator-min-microvolt = <1800000>; + regulator-max-microvolt = <1800000>; + regulator-boot-on; + regulator-always-on; + }; + + reg_3p3v: regulator-3p3v { + compatible = "regulator-fixed"; + regulator-name = "fixed-3.3V"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + regulator-boot-on; + regulator-always-on; + }; +}; + +&watchdog { + status = "okay"; +}; + +&uart0 { + status = "okay"; +}; + +&mmc0 { + bus-width = <4>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + cap-mmc-hw-reset; + vmmc-supply = <®_3p3v>; + vqmmc-supply = <®_1p8v>; + non-removable; + status = "okay"; +}; + +&usb { + status = "okay"; +}; + +&ssusb { + mediatek,force-vbus; + maximum-speed = "high-speed"; + dr_mode = "peripheral"; + status = "okay"; +}; + +&xhci0 { + status = "okay"; +}; + +&xhci3 { + status = "okay"; +}; diff --git a/board/mediatek/mt8195/MAINTAINERS b/board/mediatek/mt8195/MAINTAINERS new file mode 100644 index 0000000000..01fa25115d --- /dev/null +++ b/board/mediatek/mt8195/MAINTAINERS @@ -0,0 +1,6 @@ +MT8195 Demo +M: Macpaul Lin macpaul.lin@mediatek.com +S: Maintained +F: board/mediatek/mt8195 +F: include/configs/mt8195.h +F: configs/mt8195_demo_defconfig diff --git a/board/mediatek/mt8195/Makefile b/board/mediatek/mt8195/Makefile new file mode 100644 index 0000000000..7e94a87aea --- /dev/null +++ b/board/mediatek/mt8195/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0 + +obj-y += mt8195_demo.o diff --git a/board/mediatek/mt8195/README b/board/mediatek/mt8195/README new file mode 100644 index 0000000000..27ac56e077 --- /dev/null +++ b/board/mediatek/mt8195/README @@ -0,0 +1,65 @@ +Introduction +============ + +The Genio 1200-Demo (mt8195-demo) board is featuring the MediaTek +MT8195/MT8395 Family SoC. + +Genio 1200-Demo board features: + * CPU: ARMv8 64bit Big-Little architecture, + * Big: quad-core Cortex-A73 + * Little: quad-core Cortex-A53 + * DRAM: 2x 4GB dual-channel + * eMMC: onboard eMMC + * SD/MMC + * GbE (onboard RTL8211F) Gigabit ethernet PHY + * PCIE: 2-lane M.2 E-Key + * USB: + * USB3.0 dual role port + * 1x USB3.0 host, 2x USB2.0 host + * Display: HDMI/eDP/MIPI + * Camera: 3x 4-lane CSI + * APU + +Here is the step-by-step to boot to U-Boot on Genio 1200-Demo (mt8195-demo) +board. + +Get the Source from Genio IOT Yocto +=================================== + +To download the Genio IOT Yocto source code, please follow the instructions +in [1]. With the full source code, developers can easily build the boot chain, +which includes components such as TF-A, u-boot, kernel, and the complete +Genio IOT Yocto image. + +Compile the U-Boot +================== + +Linux native build with latest U-Boot. + + > cd u-boot + > make CROSS_COMPILE=aarch64-linux-gnu- mt8195_demo_defconfig all + +Genio IOT Yocto build with latest U-boot or Genio IOT Yocto's U-boot. + + > DISTRO=rity-demo MACHINE=i1200-demo bitbake u-boot + +Genio IOT Yocto build TF-A and package U-boot into bl31 together. + + > DISTRO=rity-demo MACHINE=i1200-demo bitbake trusted-firmware-a + +Flash the image +=============== + +MediaTek currently support the use of the Genio IOT Yocto toolset with the +'genio-flash' USB download tool for flashing images. To install 'genio-flash', +use Python's 'pip' package manager. Then, follow the instructions provided +in [2] to flash u-boot with the IOT Yocto image. + + > pip install genio-flash + +cd into the folder contains Genio IOT Yocto image, then run 'genio-flash'. + + > genio-flash + +[1] https://mediatek.gitlab.io/aiot/doc/aiot-dev-guide/release/v22.2/sw/yocto/ge... +[2] https://mediatek.gitlab.io/aiot/doc/aiot-dev-guide/master/sw/yocto/get-start... diff --git a/board/mediatek/mt8195/mt8195_demo.c b/board/mediatek/mt8195/mt8195_demo.c new file mode 100644 index 0000000000..27e16ad2fe --- /dev/null +++ b/board/mediatek/mt8195/mt8195_demo.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/* + * Copyright (C) 2023 BayLibre SAS + * Author: Fabien Parent fparent@baylibre.com + */ + +#include <common.h> +#include <dm.h> +#include <net.h> +#include <asm/io.h> + +int board_init(void) +{ + struct udevice *dev; + int ret; + + if (CONFIG_IS_ENABLED(USB_GADGET)) { + ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev); + if (ret) { + pr_err("%s: Cannot find USB device\n", __func__); + return ret; + } + } + + if (CONFIG_IS_ENABLED(USB_ETHER)) + usb_ether_init(); + + printf("Disabling WDT\n"); + writel(0, 0x10007000); + + printf("Enabling SCP SRAM\n"); + for (unsigned int val = 0xFFFFFFFF; val != 0U;) { + val = val >> 1; + writel(val, 0x1072102C); + } + + return 0; +} diff --git a/configs/mt8195_demo_defconfig b/configs/mt8195_demo_defconfig new file mode 100644 index 0000000000..7e6c02a742 --- /dev/null +++ b/configs/mt8195_demo_defconfig @@ -0,0 +1,99 @@ +CONFIG_ARM=y +CONFIG_COUNTER_FREQUENCY=13000000 +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TEXT_BASE=0x4c000000 +CONFIG_SYS_MALLOC_LEN=0x500000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x0 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="mt8195-demo" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_TARGET_MT8195=y +CONFIG_DEBUG_UART_BASE=0x11001100 +CONFIG_DEBUG_UART_CLOCK=26000000 +CONFIG_ARMV8_CRYPTO=y +CONFIG_SYS_LOAD_ADDR=0x4c000000 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_DISTRO_DEFAULTS=y +CONFIG_DEFAULT_FDT_FILE="mt8195-demo" +# CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTEFI_SELFTEST=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_NVEDIT_INFO=y +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MBR=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_BLOCK_CACHE is not set +CONFIG_CMD_EFIDEBUG=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_ENV_IMPORT_FDT=y +CONFIG_DEVRES=y +CONFIG_CLK=y +CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x200000 +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x4d000000 +CONFIG_FASTBOOT_BUF_SIZE=0x8000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MTK=y +# CONFIG_INPUT is not set +# CONFIG_MMC_QUIRKS is not set +CONFIG_MMC_MTK=y +CONFIG_PHY=y +CONFIG_PHY_MTK_TPHY=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_BAUDRATE=921600 +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_MTK_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_MTU3=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x0e8d +CONFIG_USB_GADGET_PRODUCT_NUM=0x201c +CONFIG_USB_ETHER=y +CONFIG_WDT=y +CONFIG_EFI_SET_TIME=y diff --git a/include/configs/mt8195.h b/include/configs/mt8195.h new file mode 100644 index 0000000000..7af06da6ea --- /dev/null +++ b/include/configs/mt8195.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/* + * Configuration for MT8195 based boards + * + * Copyright (C) 2023 MediaTek Inc. + * Copyright (C) 2023 BayLibre, SAS + * Author: Macpaul Lin macpaul.lin@mediatek.com + * Author: Fabien Parent fparent@baylibre.com + */ + +#ifndef __MT8195_H +#define __MT8195_H + +#include <linux/sizes.h> + +/* Environment settings */ +#include <config_distro_bootcmd.h> + +#if IS_ENABLED(CONFIG_CMD_MMC) +#define BOOT_TARGET_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_MMC(func) +#endif + +#if IS_ENABLED(CONFIG_CMD_USB) +#define BOOT_TARGET_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_USB(func) +#endif + +#define BOOT_TARGET_DEVICES(func) \ + BOOT_TARGET_MMC(func) \ + BOOT_TARGET_USB(func) + +#if !defined(CFG_EXTRA_ENV_SETTINGS) +#define CFG_EXTRA_ENV_SETTINGS \ + "scriptaddr=0x40000000\0" \ + "fdt_addr_r=0x44000000\0" \ + "fdtoverlay_addr_r=0x44c00000\0" \ + "kernel_addr_r=0x45000000\0" \ + "ramdisk_addr_r=0x46000000\0" \ + "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \ + BOOTENV +#endif + +#endif
On Fri, Aug 04, 2023 at 07:04:48PM +0800, Macpaul Lin wrote:
From: Fabien Parent fparent@baylibre.com
Add mt8195-demo board support. This demo purpose board uses MediaTek's MT8195 SoC.
Signed-off-by: Fabien Parent fparent@baylibre.com Signed-off-by: Amjad Ouled-Ameur aouledameur@baylibre.com Signed-off-by: Macpaul Lin macpaul.lin@mediatek.com
[snip]
diff --git a/board/mediatek/mt8195/MAINTAINERS b/board/mediatek/mt8195/MAINTAINERS new file mode 100644 index 0000000000..01fa25115d --- /dev/null +++ b/board/mediatek/mt8195/MAINTAINERS @@ -0,0 +1,6 @@ +MT8195 Demo +M: Macpaul Lin macpaul.lin@mediatek.com +S: Maintained +F: board/mediatek/mt8195 +F: include/configs/mt8195.h +F: configs/mt8195_demo_defconfig
Please list the dts files here too, and these are being synced with Linux, yes?
[snip]
diff --git a/include/configs/mt8195.h b/include/configs/mt8195.h new file mode 100644 index 0000000000..7af06da6ea --- /dev/null +++ b/include/configs/mt8195.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Configuration for MT8195 based boards
- Copyright (C) 2023 MediaTek Inc.
- Copyright (C) 2023 BayLibre, SAS
- Author: Macpaul Lin macpaul.lin@mediatek.com
- Author: Fabien Parent fparent@baylibre.com
- */
+#ifndef __MT8195_H +#define __MT8195_H
+#include <linux/sizes.h>
Drop this, especially as there was just some time spent fixing "need <linux/size.h> in a generic header" mediatek code.
+/* Environment settings */ +#include <config_distro_bootcmd.h>
+#if IS_ENABLED(CONFIG_CMD_MMC) +#define BOOT_TARGET_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_MMC(func) +#endif
+#if IS_ENABLED(CONFIG_CMD_USB) +#define BOOT_TARGET_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_USB(func) +#endif
+#define BOOT_TARGET_DEVICES(func) \
- BOOT_TARGET_MMC(func) \
- BOOT_TARGET_USB(func)
+#if !defined(CFG_EXTRA_ENV_SETTINGS) +#define CFG_EXTRA_ENV_SETTINGS \
- "scriptaddr=0x40000000\0" \
- "fdt_addr_r=0x44000000\0" \
- "fdtoverlay_addr_r=0x44c00000\0" \
- "kernel_addr_r=0x45000000\0" \
- "ramdisk_addr_r=0x46000000\0" \
- "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
- BOOTENV
+#endif
Please look at moving to plain text environment, thanks.
Hi,
- printf("Disabling WDT\n");
- writel(0, 0x10007000);
Please don't use magic numbers. Also, I guess this should be a real watchdog driver and u-boot will take care of disabling it if the user wants to.
- printf("Enabling SCP SRAM\n");
- for (unsigned int val = 0xFFFFFFFF; val != 0U;) {
val = val >> 1;writel(val, 0x1072102C);
Even more magic numbers.
- }
Thanks, -michael
Hi Fabien and Macpaul
Thanks for your patch set.
On Fri, 2023-08-04 at 19:04 +0800, Macpaul Lin wrote:
From: Fabien Parent fparent@baylibre.com
Add mt8195-demo board support. This demo purpose board uses MediaTek's MT8195 SoC.
Signed-off-by: Fabien Parent fparent@baylibre.com Signed-off-by: Amjad Ouled-Ameur aouledameur@baylibre.com Signed-off-by: Macpaul Lin macpaul.lin@mediatek.com
MAINTAINERS | 1 + arch/arm/dts/Makefile | 1 + arch/arm/dts/mt8195-demo.dts | 122 ++++++++++++++++++++++++++++ board/mediatek/mt8195/MAINTAINERS | 6 ++ board/mediatek/mt8195/Makefile | 3 + board/mediatek/mt8195/README | 65 +++++++++++++++
Rather than such scattered README files nowadays it is preferred adding such documentation at doc/board/mediatek.
board/mediatek/mt8195/mt8195_demo.c | 38 +++++++++ configs/mt8195_demo_defconfig | 99 ++++++++++++++++++++++ include/configs/mt8195.h | 46 +++++++++++ 9 files changed, 381 insertions(+) create mode 100644 arch/arm/dts/mt8195-demo.dts create mode 100644 board/mediatek/mt8195/MAINTAINERS create mode 100644 board/mediatek/mt8195/Makefile create mode 100644 board/mediatek/mt8195/README create mode 100644 board/mediatek/mt8195/mt8195_demo.c create mode 100644 configs/mt8195_demo_defconfig create mode 100644 include/configs/mt8195.h
Changes for v2 and v3: - no change.
Changes for v4: - Remove CONFIG_SYS_NS16550 related settings in mt8195.h.
Changes for v5: - Fix Copyright year to 2023. - Fix build error by adding 'CONFIG_TEXT_BASE' in defconfig. - Add README for mt8195-demo board includes toolchain setting 'CROSS_COMPILE=aarch64-linux-gnu-' - Fix 'CONFIG_EXTRA_ENV_SETTINGS' with 'CFG_EXTRA_ENV_SETTINGS' according to checkpatch error. - Update dram to 8GB size. - dts - Add optee and pcsi support in firmware section. - mt8195_demo_defconfig - enable I2C, DFU, GPT, MBR support - enable some USB ethernet adaptors - rebase patchset to v2023-10.rc1
diff --git a/MAINTAINERS b/MAINTAINERS index 4d0f017e7e..454d3615f4 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -396,6 +396,7 @@ F: drivers/watchdog/mtk_wdt.c F: drivers/net/mtk_eth.c F: drivers/net/mtk_eth.h F: drivers/reset/reset-mediatek.c +F: include/configs/mt8195.h F: tools/mtk_image.c F: tools/mtk_image.h F: tools/mtk_nand_headers.c diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile index e66c32e268..d7104b77bf 100644 --- a/arch/arm/dts/Makefile +++ b/arch/arm/dts/Makefile @@ -1342,6 +1342,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += \ mt7986a-emmc-rfb.dtb \ mt7986b-emmc-rfb.dtb \ mt8183-pumpkin.dtb \
- mt8195-demo.dtb \
mt8512-bm1-emmc.dtb \ mt8516-pumpkin.dtb \ mt8518-ap1-emmc.dtb diff --git a/arch/arm/dts/mt8195-demo.dts b/arch/arm/dts/mt8195-demo.dts new file mode 100644 index 0000000000..e4063cd143 --- /dev/null +++ b/arch/arm/dts/mt8195-demo.dts @@ -0,0 +1,122 @@ +// SPDX-License-Identifier: GPL-2.0 OR MIT +/*
- Copyright (C) 2023 MediaTek Inc.
- Copyright (C) 2023 BayLibre SAS.
- Author: Macpaul Lin macpaul.lin@mediatek.com
- Author: Fabien Parent fparent@baylibre.com
- */
+/dts-v1/;
+#include <config.h> +#include "mt8195.dtsi"
+/ {
- model = "MediaTek MT8195 demo board";
- compatible = "mediatek,mt8195-demo", "mediatek,mt8195";
- memory@40000000 {
/* 8GB */device_type = "memory";reg = <0 0x40000000 2 0x00000000>;- };
- firmware: firmware {
optee {compatible = "linaro,optee-tz";method = "smc";};psci: psci {compatible = "arm,psci-1.0";method = "smc";};- };
- reserved-memory {
#address-cells = <2>;#size-cells = <2>;ranges;/* 2 MiB reserved for ARM Trusted Firmware (BL31) */bl31_secmon_reserved: secmon@54600000 {no-map;reg = <0 0x54600000 0x0 0x200000>;};/* 12 MiB reserved for OP-TEE (BL32)* +-----------------------+ 0x43e0_0000* | SHMEM 2MiB |* +-----------------------+ 0x43c0_0000* | | TA_RAM 8MiB |* + TZDRAM +--------------+ 0x4340_0000* | | TEE_RAM 2MiB |* +-----------------------+ 0x4320_0000*/optee_reserved: optee@43200000 {no-map;reg = <0 0x43200000 0 0x00c00000>;};- };
- chosen {
stdout-path = &uart0;- };
- reg_1p8v: regulator-1p8v {
compatible = "regulator-fixed";regulator-name = "fixed-1.8V";regulator-min-microvolt = <1800000>;regulator-max-microvolt = <1800000>;regulator-boot-on;regulator-always-on;- };
- reg_3p3v: regulator-3p3v {
compatible = "regulator-fixed";regulator-name = "fixed-3.3V";regulator-min-microvolt = <3300000>;regulator-max-microvolt = <3300000>;regulator-boot-on;regulator-always-on;- };
+};
+&watchdog {
- status = "okay";
+};
+&uart0 {
- status = "okay";
+};
+&mmc0 {
- bus-width = <4>;
- max-frequency = <200000000>;
- cap-mmc-highspeed;
- mmc-hs200-1_8v;
- cap-mmc-hw-reset;
- vmmc-supply = <®_3p3v>;
- vqmmc-supply = <®_1p8v>;
- non-removable;
- status = "okay";
+};
+&usb {
- status = "okay";
+};
+&ssusb {
- mediatek,force-vbus;
- maximum-speed = "high-speed";
- dr_mode = "peripheral";
- status = "okay";
+};
+&xhci0 {
- status = "okay";
+};
+&xhci3 {
- status = "okay";
+}; diff --git a/board/mediatek/mt8195/MAINTAINERS b/board/mediatek/mt8195/MAINTAINERS new file mode 100644 index 0000000000..01fa25115d --- /dev/null +++ b/board/mediatek/mt8195/MAINTAINERS @@ -0,0 +1,6 @@ +MT8195 Demo +M: Macpaul Lin macpaul.lin@mediatek.com +S: Maintained +F: board/mediatek/mt8195 +F: include/configs/mt8195.h +F: configs/mt8195_demo_defconfig diff --git a/board/mediatek/mt8195/Makefile b/board/mediatek/mt8195/Makefile new file mode 100644 index 0000000000..7e94a87aea --- /dev/null +++ b/board/mediatek/mt8195/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0
+obj-y += mt8195_demo.o diff --git a/board/mediatek/mt8195/README b/board/mediatek/mt8195/README new file mode 100644 index 0000000000..27ac56e077 --- /dev/null +++ b/board/mediatek/mt8195/README @@ -0,0 +1,65 @@ +Introduction +============
+The Genio 1200-Demo (mt8195-demo) board is featuring the MediaTek +MT8195/MT8395 Family SoC.
+Genio 1200-Demo board features:
- CPU: ARMv8 64bit Big-Little architecture,
* Big: quad-core Cortex-A73* Little: quad-core Cortex-A53
- DRAM: 2x 4GB dual-channel
- eMMC: onboard eMMC
- SD/MMC
- GbE (onboard RTL8211F) Gigabit ethernet PHY
- PCIE: 2-lane M.2 E-Key
- USB:
* USB3.0 dual role port* 1x USB3.0 host, 2x USB2.0 host
- Display: HDMI/eDP/MIPI
- Camera: 3x 4-lane CSI
- APU
+Here is the step-by-step to boot to U-Boot on Genio 1200-Demo (mt8195-demo) +board.
+Get the Source from Genio IOT Yocto +===================================
+To download the Genio IOT Yocto source code, please follow the instructions +in [1]. With the full source code, developers can easily build the boot chain, +which includes components such as TF-A, u-boot, kernel, and the complete +Genio IOT Yocto image.
+Compile the U-Boot +==================
+Linux native build with latest U-Boot.
+ > cd u-boot + > make CROSS_COMPILE=aarch64-linux-gnu- mt8195_demo_defconfig all
+Genio IOT Yocto build with latest U-boot or Genio IOT Yocto's U-boot.
+ > DISTRO=rity-demo MACHINE=i1200-demo bitbake u-boot
+Genio IOT Yocto build TF-A and package U-boot into bl31 together.
+ > DISTRO=rity-demo MACHINE=i1200-demo bitbake trusted-firmware-a
+Flash the image +===============
+MediaTek currently support the use of the Genio IOT Yocto toolset with the +'genio-flash' USB download tool for flashing images. To install 'genio-flash', +use Python's 'pip' package manager. Then, follow the instructions provided +in [2] to flash u-boot with the IOT Yocto image.
+ > pip install genio-flash
+cd into the folder contains Genio IOT Yocto image, then run 'genio-flash'.
+ > genio-flash
+[1] https://mediatek.gitlab.io/aiot/doc/aiot-dev-guide/release/v22.2/sw/yocto/ge... +[2] https://mediatek.gitlab.io/aiot/doc/aiot-dev-guide/master/sw/yocto/get-start... diff --git a/board/mediatek/mt8195/mt8195_demo.c b/board/mediatek/mt8195/mt8195_demo.c new file mode 100644 index 0000000000..27e16ad2fe --- /dev/null +++ b/board/mediatek/mt8195/mt8195_demo.c @@ -0,0 +1,38 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2023 BayLibre SAS
- Author: Fabien Parent fparent@baylibre.com
- */
+#include <common.h> +#include <dm.h> +#include <net.h> +#include <asm/io.h>
+int board_init(void) +{
- struct udevice *dev;
- int ret;
- if (CONFIG_IS_ENABLED(USB_GADGET)) {
ret = uclass_get_device(UCLASS_USB_GADGET_GENERIC, 0, &dev);if (ret) {pr_err("%s: Cannot find USB device\n", __func__);return ret;}- }
- if (CONFIG_IS_ENABLED(USB_ETHER))
usb_ether_init();- printf("Disabling WDT\n");
- writel(0, 0x10007000);
- printf("Enabling SCP SRAM\n");
- for (unsigned int val = 0xFFFFFFFF; val != 0U;) {
val = val >> 1;writel(val, 0x1072102C);- }
- return 0;
+} diff --git a/configs/mt8195_demo_defconfig b/configs/mt8195_demo_defconfig new file mode 100644 index 0000000000..7e6c02a742 --- /dev/null +++ b/configs/mt8195_demo_defconfig @@ -0,0 +1,99 @@ +CONFIG_ARM=y +CONFIG_COUNTER_FREQUENCY=13000000 +CONFIG_POSITION_INDEPENDENT=y +CONFIG_ARCH_MEDIATEK=y +CONFIG_TEXT_BASE=0x4c000000 +CONFIG_SYS_MALLOC_LEN=0x500000 +CONFIG_SYS_MALLOC_F_LEN=0x4000 +CONFIG_NR_DRAM_BANKS=1 +CONFIG_ENV_SIZE=0x1000 +CONFIG_ENV_OFFSET=0x0 +CONFIG_DM_GPIO=y +CONFIG_DEFAULT_DEVICE_TREE="mt8195-demo" +CONFIG_OF_LIBFDT_OVERLAY=y +CONFIG_TARGET_MT8195=y +CONFIG_DEBUG_UART_BASE=0x11001100 +CONFIG_DEBUG_UART_CLOCK=26000000 +CONFIG_ARMV8_CRYPTO=y +CONFIG_SYS_LOAD_ADDR=0x4c000000 +CONFIG_DEBUG_UART=y +CONFIG_FIT=y +CONFIG_FIT_SIGNATURE=y +# CONFIG_ARCH_FIXUP_FDT_MEMORY is not set +CONFIG_DISTRO_DEFAULTS=y +CONFIG_DEFAULT_FDT_FILE="mt8195-demo" +# CONFIG_DISPLAY_BOARDINFO is not set +# CONFIG_CMD_CONSOLE is not set +# CONFIG_CMD_BOOTD is not set +CONFIG_CMD_BOOTEFI_SELFTEST=y +# CONFIG_CMD_ELF is not set +# CONFIG_CMD_GO is not set +# CONFIG_CMD_IMI is not set +# CONFIG_CMD_XIMG is not set +CONFIG_CMD_NVEDIT_EFI=y +CONFIG_CMD_NVEDIT_INFO=y +# CONFIG_CMD_CRC32 is not set +CONFIG_CMD_CLK=y +CONFIG_CMD_DFU=y +CONFIG_CMD_DM=y +CONFIG_CMD_GPT=y +CONFIG_CMD_GPT_RENAME=y +CONFIG_CMD_I2C=y +# CONFIG_CMD_LOADB is not set +# CONFIG_CMD_LOADS is not set +CONFIG_CMD_MBR=y +CONFIG_CMD_MMC=y +CONFIG_CMD_USB=y +CONFIG_CMD_USB_MASS_STORAGE=y +# CONFIG_CMD_ITEST is not set +# CONFIG_CMD_BLOCK_CACHE is not set +CONFIG_CMD_EFIDEBUG=y +CONFIG_PARTITION_TYPE_GUID=y +CONFIG_ENV_IS_IN_MMC=y +CONFIG_SYS_MMC_ENV_PART=2 +CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG=y +CONFIG_ENV_IMPORT_FDT=y +CONFIG_DEVRES=y +CONFIG_CLK=y +CONFIG_DFU_MMC=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x100000 +CONFIG_SYS_DFU_MAX_FILE_SIZE=0x200000 +CONFIG_USB_FUNCTION_FASTBOOT=y +CONFIG_FASTBOOT_BUF_ADDR=0x4d000000 +CONFIG_FASTBOOT_BUF_SIZE=0x8000000 +CONFIG_FASTBOOT_FLASH=y +CONFIG_FASTBOOT_FLASH_MMC_DEV=0 +CONFIG_FASTBOOT_MMC_BOOT_SUPPORT=y +CONFIG_DM_I2C=y +CONFIG_SYS_I2C_MTK=y +# CONFIG_INPUT is not set +# CONFIG_MMC_QUIRKS is not set +CONFIG_MMC_MTK=y +CONFIG_PHY=y +CONFIG_PHY_MTK_TPHY=y +CONFIG_DM_RTC=y +CONFIG_RTC_EMULATION=y +CONFIG_BAUDRATE=921600 +CONFIG_DM_SERIAL=y +CONFIG_DEBUG_UART_ANNOUNCE=y +CONFIG_MTK_SERIAL=y +CONFIG_SYSRESET=y +CONFIG_SYSRESET_PSCI=y +CONFIG_USB=y +CONFIG_DM_USB_GADGET=y +CONFIG_USB_XHCI_HCD=y +CONFIG_USB_XHCI_MTK=y +CONFIG_USB_MTU3=y +CONFIG_USB_KEYBOARD=y +CONFIG_USB_HOST_ETHER=y +CONFIG_USB_ETHER_ASIX=y +CONFIG_USB_ETHER_ASIX88179=y +CONFIG_USB_ETHER_MCS7830=y +CONFIG_USB_ETHER_RTL8152=y +CONFIG_USB_ETHER_SMSC95XX=y +CONFIG_USB_GADGET=y +CONFIG_USB_GADGET_VENDOR_NUM=0x0e8d +CONFIG_USB_GADGET_PRODUCT_NUM=0x201c +CONFIG_USB_ETHER=y +CONFIG_WDT=y +CONFIG_EFI_SET_TIME=y diff --git a/include/configs/mt8195.h b/include/configs/mt8195.h new file mode 100644 index 0000000000..7af06da6ea --- /dev/null +++ b/include/configs/mt8195.h @@ -0,0 +1,46 @@ +/* SPDX-License-Identifier: GPL-2.0+ */ +/*
- Configuration for MT8195 based boards
- Copyright (C) 2023 MediaTek Inc.
- Copyright (C) 2023 BayLibre, SAS
- Author: Macpaul Lin macpaul.lin@mediatek.com
- Author: Fabien Parent fparent@baylibre.com
- */
+#ifndef __MT8195_H +#define __MT8195_H
+#include <linux/sizes.h>
+/* Environment settings */ +#include <config_distro_bootcmd.h>
+#if IS_ENABLED(CONFIG_CMD_MMC) +#define BOOT_TARGET_MMC(func) func(MMC, mmc, 0) +#else +#define BOOT_TARGET_MMC(func) +#endif
+#if IS_ENABLED(CONFIG_CMD_USB) +#define BOOT_TARGET_USB(func) func(USB, usb, 0) +#else +#define BOOT_TARGET_USB(func) +#endif
+#define BOOT_TARGET_DEVICES(func) \
- BOOT_TARGET_MMC(func) \
- BOOT_TARGET_USB(func)
+#if !defined(CFG_EXTRA_ENV_SETTINGS) +#define CFG_EXTRA_ENV_SETTINGS \
- "scriptaddr=0x40000000\0" \
- "fdt_addr_r=0x44000000\0" \
- "fdtoverlay_addr_r=0x44c00000\0" \
- "kernel_addr_r=0x45000000\0" \
- "ramdisk_addr_r=0x46000000\0" \
- "fdtfile=" CONFIG_DEFAULT_DEVICE_TREE ".dtb\0" \
- BOOTENV
+#endif
+#endif
Cheers
Marcel
Hi guys
On Fri, 2023-08-04 at 19:04 +0800, Macpaul Lin wrote:
From: Fabien Parent fparent@baylibre.com
The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts, SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options.
Signed-off-by: Fabien Parent fparent@baylibre.com Signed-off-by: Macpaul Lin macpaul.lin@mediatek.com
MAINTAINERS | 2 + arch/arm/dts/mt8195.dtsi | 370 +++++++++++++++++++++++++ arch/arm/mach-mediatek/Kconfig | 13 +- arch/arm/mach-mediatek/Makefile | 1 + arch/arm/mach-mediatek/mt8195/Kconfig | 13 + arch/arm/mach-mediatek/mt8195/Makefile | 3 + arch/arm/mach-mediatek/mt8195/init.c | 97 +++++++ 7 files changed, 498 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/mt8195.dtsi create mode 100644 arch/arm/mach-mediatek/mt8195/Kconfig create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
Changes for v2: - Correct node name to t-phy for u3phy0. - Add platform compatible string "mediatek,mt8195-tphy" to all usb phy nodes. - remove clock nodes that software cannot controlled in phy nodes. - Test and add back "mac" for HOST only xhci nodes.
Changes for v3: - Revise device node name from "xhciX: xhciX@" to "xhciX: xhci@".
Changes for v4: - No change.
Changes for v5: - Fix Copyright year to 2023. - Fix memory map in dram_init() to support 8GB onboard memory. - Add '#if !IS_ENABLED(CONFIG_SYSRESET)' with reset_cpu(). - Correct reset_cpu() function prototype. - rebase patchset to v2023-10.rc1 - Add missing arch/arm/mach-mediatek/mt8195/Kconfig.
[snip]
I finally got my hands on an EVK and gave this a try. However, I did not get that far. This is with latest downstream TF-A as I still struggle with upstream there as well. Any ideas?
U-Boot 2024.01-rc1-00056-g5237f2b48bb (Nov 10 2023 - 15:33:34 +0100)
CPU: MediaTek MT8195 DRAM: 8 GiB mtu3 usb@11200000: clks of sts1 are not stable! mtu3-peripheral ssusb@11200000: device enable failed -110 mtu3-peripheral ssusb@11200000: mtu3 hw init failed:-110 board_init: Cannot find USB device initcall failed at call 00000000ffe46a50 (err=-110) ### ERROR ### Please RESET the board ###
Cheers
Marcel
Marcel Ziswiler marcel.ziswiler@toradex.com 於 2023年11月11日 週六 上午4:24寫道：
[snip]
Changes for v5:
- Fix Copyright year to 2023.
- Fix memory map in dram_init() to support 8GB onboard memory.
- Add '#if !IS_ENABLED(CONFIG_SYSRESET)' with reset_cpu().
- Correct reset_cpu() function prototype.
- rebase patchset to v2023-10.rc1
- Add missing arch/arm/mach-mediatek/mt8195/Kconfig.
[snip]
I finally got my hands on an EVK and gave this a try. However, I did not get that far. This is with latest downstream TF-A as I still struggle with upstream there as well. Any ideas?
U-Boot 2024.01-rc1-00056-g5237f2b48bb (Nov 10 2023 - 15:33:34 +0100)
CPU: MediaTek MT8195 DRAM: 8 GiB mtu3 usb@11200000: clks of sts1 are not stable! mtu3-peripheral ssusb@11200000: device enable failed -110 mtu3-peripheral ssusb@11200000: mtu3 hw init failed:-110 board_init: Cannot find USB device initcall failed at call 00000000ffe46a50 (err=-110) ### ERROR ### Please RESET the board ###
Cheers
Marcel
I'm glad you've get a board and tested our patches. Currently we're busy on other tasks so the improvement to the patch v5 has been postponed. :~(
These error is because the power supplement settings are in the later patches. Hence the clock might not stable for the cold boot up. You can just press the key on the board and warm reset it, the clock issue should be disappear.
mtu3-peripheral ssusb@11200000: device enable failed -110 mtu3-peripheral ssusb@11200000: mtu3 hw init failed:-110
You can refer to the user guide and public domain code. https://mediatek.gitlab.io/aiot/doc/aiot-dev-guide/master/sw/yocto/get-start... https://mediatek.gitlab.io/aiot/doc/aiot-dev-guide/master/sw/yocto/get-start...
The latest u-boot code is here. https://gitlab.com/mediatek/aiot/bsp/u-boot/-/tree/mtk-v2022.10?ref_type=hea...
Hi,
On Fri, 4 Aug 2023 at 05:05, Macpaul Lin macpaul.lin@mediatek.com wrote:
From: Fabien Parent fparent@baylibre.com
The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts, SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options.
Signed-off-by: Fabien Parent fparent@baylibre.com Signed-off-by: Macpaul Lin macpaul.lin@mediatek.com
MAINTAINERS | 2 + arch/arm/dts/mt8195.dtsi | 370 +++++++++++++++++++++++++ arch/arm/mach-mediatek/Kconfig | 13 +- arch/arm/mach-mediatek/Makefile | 1 + arch/arm/mach-mediatek/mt8195/Kconfig | 13 + arch/arm/mach-mediatek/mt8195/Makefile | 3 + arch/arm/mach-mediatek/mt8195/init.c | 97 +++++++ 7 files changed, 498 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/mt8195.dtsi create mode 100644 arch/arm/mach-mediatek/mt8195/Kconfig create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
Reviewed-by: Simon Glass sjg@chromium.org
nits below
Changes for v2:
- Correct node name to t-phy for u3phy0.
- Add platform compatible string "mediatek,mt8195-tphy" to all usb phy nodes.
- remove clock nodes that software cannot controlled in phy nodes.
- Test and add back "mac" for HOST only xhci nodes.
Changes for v3:
- Revise device node name from "xhciX: xhciX@" to "xhciX: xhci@".
Changes for v4:
- No change.
Changes for v5:
- Fix Copyright year to 2023.
- Fix memory map in dram_init() to support 8GB onboard memory.
- Add '#if !IS_ENABLED(CONFIG_SYSRESET)' with reset_cpu().
- Correct reset_cpu() function prototype.
- rebase patchset to v2023-10.rc1
- Add missing arch/arm/mach-mediatek/mt8195/Kconfig.
diff --git a/MAINTAINERS b/MAINTAINERS index 47581cf6fb..4d0f017e7e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -369,8 +369,10 @@ ARM MEDIATEK M: Ryder Lee ryder.lee@mediatek.com M: Weijie Gao weijie.gao@mediatek.com M: Chunfeng Yun chunfeng.yun@mediatek.com +M: Macpaul Lin macpaul.lin@mediatek.com R: GSS_MTK_Uboot_upstream GSS_MTK_Uboot_upstream@mediatek.com S: Maintained +F: arch/arm/dts/mt8195.dtsi F: arch/arm/mach-mediatek/ F: arch/arm/include/asm/arch-mediatek/ F: board/mediatek/
diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 04aa2fd97f..3a2af1cdee 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -67,6 +67,15 @@ config TARGET_MT8183 SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options.
+config TARGET_MT8195
bool "MediaTek MT8195 SoC"select ARM64helpThe MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 anda quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts,SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3and LPDDR4 options.config TARGET_MT8512 bool "MediaTek MT8512 M1 Board" select ARM64 @@ -105,6 +114,7 @@ config SYS_BOARD default "mt7981" if TARGET_MT7981 default "mt7986" if TARGET_MT7986 default "mt8183" if TARGET_MT8183
default "mt8195" if TARGET_MT8195 default "mt8512" if TARGET_MT8512 default "mt8516" if TARGET_MT8516 default "mt8518" if TARGET_MT8518@@ -122,6 +132,7 @@ config SYS_CONFIG_NAME default "mt7981" if TARGET_MT7981 default "mt7986" if TARGET_MT7986 default "mt8183" if TARGET_MT8183
default "mt8195" if TARGET_MT8195 default "mt8512" if TARGET_MT8512 default "mt8516" if TARGET_MT8516 default "mt8518" if TARGET_MT8518@@ -134,7 +145,7 @@ config SYS_CONFIG_NAME config MTK_BROM_HEADER_INFO string default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 || TARGET_MT8195 default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 default "lk=1" if TARGET_MT7623diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index fc85293f71..fbbb5431d1 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -10,5 +10,6 @@ obj-$(CONFIG_TARGET_MT7629) += mt7629/ obj-$(CONFIG_TARGET_MT7981) += mt7981/ obj-$(CONFIG_TARGET_MT7986) += mt7986/ obj-$(CONFIG_TARGET_MT8183) += mt8183/ +obj-$(CONFIG_TARGET_MT8195) += mt8195/ obj-$(CONFIG_TARGET_MT8516) += mt8516/ obj-$(CONFIG_TARGET_MT8518) += mt8518/ diff --git a/arch/arm/mach-mediatek/mt8195/Kconfig b/arch/arm/mach-mediatek/mt8195/Kconfig new file mode 100644 index 0000000000..a34fa2cf2e --- /dev/null +++ b/arch/arm/mach-mediatek/mt8195/Kconfig @@ -0,0 +1,13 @@ +if TARGET_MT8195
+config SYS_BOARD
default "mt8195"+config SYS_CONFIG_NAME
default "mt8195"+config MTK_BROM_HEADER_INFO
stringdefault "media=emmc"+endif diff --git a/arch/arm/mach-mediatek/mt8195/Makefile b/arch/arm/mach-mediatek/mt8195/Makefile new file mode 100644 index 0000000000..886ab7e4eb --- /dev/null +++ b/arch/arm/mach-mediatek/mt8195/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0
+obj-y += init.o diff --git a/arch/arm/mach-mediatek/mt8195/init.c b/arch/arm/mach-mediatek/mt8195/init.c new file mode 100644 index 0000000000..8d6b700e7e --- /dev/null +++ b/arch/arm/mach-mediatek/mt8195/init.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2023 MediaTek Inc.
- Copyright (C) 2023 BayLibre, SAS
- Author: Macpaul Lin macpaul.lin@mediatek.com
- Author: Fabien Parent fparent@baylibre.com
- */
+#include <clk.h> +#include <common.h> +#include <cpu_func.h> +#include <dm.h> +#include <fdtdec.h> +#include <ram.h> +#include <asm/arch/misc.h> +#include <asm/armv8/mmu.h> +#include <asm/sections.h> +#include <asm/system.h> +#include <dm/uclass.h>
+DECLARE_GLOBAL_DATA_PTR;
+int dram_init(void) +{
int ret;ret = fdtdec_setup_memory_banksize();if (ret)return ret;fdtdec_setup_mem_size_base();/** Limit gd->ram_top not exceeding SZ_4G.* Because some periphals like mmc requires DMA buffer
spelling
* allocaed below SZ_4G.
spelling
Also please don't put punctuation after SZ_4G as it makes it harder for people to select it and search
** Note: SZ_2M is for adjusting gd->relocaddr,* the reserved memory for u-boot itself.*/if (gd->ram_base + gd->ram_size >= SZ_4G)gd->mon_len = SZ_4G + gd->ram_base + SZ_2M;return 0;+}
+int dram_init_banksize(void) +{
gd->bd->bi_dram[0].start = gd->ram_base;gd->bd->bi_dram[0].size = gd->ram_size;return 0;+}
+int mtk_pll_early_init(void) +{
return 0;+}
+int mtk_soc_early_init(void) +{
return 0;+}
+#if !IS_ENABLED(CONFIG_SYSRESET) +void reset_cpu(void) +{
psci_system_reset();+} +#endif
+int print_cpuinfo(void) +{
printf("CPU: MediaTek MT8195\n");return 0;
You should use a sysinfo driver to provide this information
+}
+static struct mm_region mt8195_mem_map[] = {
{/* DDR */.virt = 0x40000000UL,.phys = 0x40000000UL,.size = 0x200000000UL,.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,}, {.virt = 0x00000000UL,.phys = 0x00000000UL,.size = 0x20000000UL,.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |PTE_BLOCK_NON_SHARE |PTE_BLOCK_PXN | PTE_BLOCK_UXN}, {0,}+};
+struct mm_region *mem_map = mt8195_mem_map;
2.18.0
Regards, Simon
Hello,
What happened to this series? Has it been abandoned? Also, is it possible to get memory size installed to the board dynamically?
Best regards, Shengyu
在 2023/8/4 19:04, Macpaul Lin 写道:
From: Fabien Parent fparent@baylibre.com
The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 and a quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts, SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options.
Signed-off-by: Fabien Parent fparent@baylibre.com Signed-off-by: Macpaul Lin macpaul.lin@mediatek.com Reviewed-by: Simon Glass sjg@chromium.org
MAINTAINERS | 2 + arch/arm/dts/mt8195.dtsi | 370 +++++++++++++++++++++++++ arch/arm/mach-mediatek/Kconfig | 13 +- arch/arm/mach-mediatek/Makefile | 1 + arch/arm/mach-mediatek/mt8195/Kconfig | 13 + arch/arm/mach-mediatek/mt8195/Makefile | 3 + arch/arm/mach-mediatek/mt8195/init.c | 97 +++++++ 7 files changed, 498 insertions(+), 1 deletion(-) create mode 100644 arch/arm/dts/mt8195.dtsi create mode 100644 arch/arm/mach-mediatek/mt8195/Kconfig create mode 100644 arch/arm/mach-mediatek/mt8195/Makefile create mode 100644 arch/arm/mach-mediatek/mt8195/init.c
Changes for v2:
- Correct node name to t-phy for u3phy0.
- Add platform compatible string "mediatek,mt8195-tphy" to all usb phy nodes.
- remove clock nodes that software cannot controlled in phy nodes.
- Test and add back "mac" for HOST only xhci nodes.
Changes for v3:
- Revise device node name from "xhciX: xhciX@" to "xhciX: xhci@".
Changes for v4:
- No change.
Changes for v5:
- Fix Copyright year to 2023.
- Fix memory map in dram_init() to support 8GB onboard memory.
- Add '#if !IS_ENABLED(CONFIG_SYSRESET)' with reset_cpu().
- Correct reset_cpu() function prototype.
- rebase patchset to v2023-10.rc1
- Add missing arch/arm/mach-mediatek/mt8195/Kconfig.
diff --git a/MAINTAINERS b/MAINTAINERS index 47581cf6fb..4d0f017e7e 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -369,8 +369,10 @@ ARM MEDIATEK M: Ryder Lee ryder.lee@mediatek.com M: Weijie Gao weijie.gao@mediatek.com M: Chunfeng Yun chunfeng.yun@mediatek.com +M: Macpaul Lin macpaul.lin@mediatek.com R: GSS_MTK_Uboot_upstream GSS_MTK_Uboot_upstream@mediatek.com S: Maintained +F: arch/arm/dts/mt8195.dtsi F: arch/arm/mach-mediatek/ F: arch/arm/include/asm/arch-mediatek/ F: board/mediatek/ diff --git a/arch/arm/dts/mt8195.dtsi b/arch/arm/dts/mt8195.dtsi new file mode 100644 index 0000000000..14cb28d008 --- /dev/null +++ b/arch/arm/dts/mt8195.dtsi @@ -0,0 +1,370 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/*
- Copyright (C) 2023 MediaTek Inc.
- Copyright (C) 2023 BayLibre, SAS
- Author: Ben Ho ben.ho@mediatek.com
Erin Lo <erin.lo@mediatek.com>
Fabien Parent <fparent@baylibre.com>
Macpaul Lin <macpaul.lin@mediatek.com>- */
+#include <dt-bindings/gpio/gpio.h> +#include <dt-bindings/interrupt-controller/irq.h> +#include <dt-bindings/interrupt-controller/arm-gic.h> +#include <dt-bindings/phy/phy.h>
+/ {
- compatible = "mediatek,mt8195";
- interrupt-parent = <&sysirq>;
- #address-cells = <2>;
- #size-cells = <2>;
- cpus {
#address-cells = <1>;#size-cells = <0>;cpu-map {cluster0 {core0 {cpu = <&cpu0>;};core1 {cpu = <&cpu1>;};core2 {cpu = <&cpu2>;};core3 {cpu = <&cpu3>;};};cluster1 {core0 {cpu = <&cpu4>;};core1 {cpu = <&cpu5>;};core2 {cpu = <&cpu6>;};core3 {cpu = <&cpu7>;};};};cpu0: cpu@0 {device_type = "cpu";compatible = "arm,cortex-a53";reg = <0x000>;enable-method = "psci";capacity-dmips-mhz = <741>;};cpu1: cpu@1 {device_type = "cpu";compatible = "arm,cortex-a53";reg = <0x001>;enable-method = "psci";capacity-dmips-mhz = <741>;};cpu2: cpu@2 {device_type = "cpu";compatible = "arm,cortex-a53";reg = <0x002>;enable-method = "psci";capacity-dmips-mhz = <741>;};cpu3: cpu@3 {device_type = "cpu";compatible = "arm,cortex-a53";reg = <0x003>;enable-method = "psci";capacity-dmips-mhz = <741>;};cpu4: cpu@100 {device_type = "cpu";compatible = "arm,cortex-a73";reg = <0x100>;enable-method = "psci";capacity-dmips-mhz = <1024>;};cpu5: cpu@101 {device_type = "cpu";compatible = "arm,cortex-a73";reg = <0x101>;enable-method = "psci";capacity-dmips-mhz = <1024>;};cpu6: cpu@102 {device_type = "cpu";compatible = "arm,cortex-a73";reg = <0x102>;enable-method = "psci";capacity-dmips-mhz = <1024>;};cpu7: cpu@103 {device_type = "cpu";compatible = "arm,cortex-a73";reg = <0x103>;enable-method = "psci";capacity-dmips-mhz = <1024>;};- };
- clk26m: oscillator {
compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <26000000>;clock-output-names = "clk26m";- };
- mmc_source_clk: mmc-source-clk{
compatible = "fixed-clock";#clock-cells = <0>;clock-frequency = <400000000>;clock-output-names = "mmc_source_clk";- };
- soc {
#address-cells = <2>;#size-cells = <2>;compatible = "simple-bus";ranges;watchdog: watchdog@10007000 {compatible = "mediatek,mt8195-wdt","mediatek,wdt";reg = <0 0x10007000 0 0x100>;status = "disabled";};gic: interrupt-controller@c000000 {compatible = "arm,gic-v3";#interrupt-cells = <4>;interrupt-parent = <&gic>;interrupt-controller;reg = <0 0x0c000000 0 0x40000>, /* GICD */<0 0x0c100000 0 0x200000>, /* GICR */<0 0x0c400000 0 0x2000>, /* GICC */<0 0x0c410000 0 0x1000>, /* GICH */<0 0x0c420000 0 0x2000>; /* GICV */interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;ppi-partitions {ppi_cluster0: interrupt-partition-0 {affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;};ppi_cluster1: interrupt-partition-1 {affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;};};};sysirq: interrupt-controller@c530a80 {compatible = "mediatek,mt8195-sysirq","mediatek,mt6577-sysirq";interrupt-controller;#interrupt-cells = <3>;interrupt-parent = <&gic>;reg = <0 0x0c530a80 0 0x50>;};topckgen: syscon@10000000 {compatible = "mediatek,mt8195-topckgen", "syscon";reg = <0 0x10000000 0 0x1000>;#clock-cells = <1>;};infracfg: syscon@10001000 {compatible = "mediatek,mt8195-infracfg", "syscon";reg = <0 0x10001000 0 0x1000>;#clock-cells = <1>;};apmixedsys: syscon@1000c000 {compatible = "mediatek,mt8195-apmixedsys", "syscon";reg = <0 0x1000c000 0 0x1000>;#clock-cells = <1>;};uart0: serial@11001100 {compatible = "mediatek,mt8195-uart","mediatek,hsuart";reg = <0 0x11001100 0 0x1000>;interrupts = <GIC_SPI 91 IRQ_TYPE_LEVEL_LOW>;clock-frequency = <26000000>;clocks = <&clk26m>, <&clk26m>;clock-names = "baud", "bus";status = "disabled";};mmc0: mmc@11230000 {compatible = "mediatek,mt8195-mmc","mediatek,mt8183-mmc";reg = <0 0x11230000 0 0x1000>,<0 0x11f50000 0 0x1000>;interrupts = <GIC_SPI 77 IRQ_TYPE_LEVEL_LOW>;clocks = <&mmc_source_clk>,<&clk26m>,<&clk26m>;clock-names = "source", "hclk", "source_cg";status = "disabled";};u3phy0: t-phy@11f40000 {compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";#address-cells = <1>;#size-cells = <1>;ranges = <0 0 0x11e40000 0xe00>;status = "okay";u2port0: usb-phy@0 {reg = <0 0x700>;#phy-cells = <1>;status = "okay";};u3port0: usb-phy@700 {reg = <0x700 0x700>;#phy-cells = <1>;status = "okay";};};usb: usb@11200000 {compatible ="mediatek,mt8195-mtu3", "mediatek,mtu3";reg = <0 0x11203e00 0 0x0100>;reg-names = "ippc";phys = <&u2port0 PHY_TYPE_USB2>;clocks = <&clk26m>,<&clk26m>,<&clk26m>;clock-names = "sys_ck", "ref_ck", "mcu_ck";#address-cells = <2>;#size-cells = <2>;ranges;status = "disabled";ssusb: ssusb@11200000 {compatible = "mediatek,ssusb";reg = <0 0x11200000 0 0x3e00>;reg-names = "mac";interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_LOW>;status = "disabled";};xhci0: xhci@11200000 {compatible = "mediatek,mtk-xhci";reg = <0 0x11200000 0 0x1000>;reg-names = "mac";interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_LOW>;clocks = <&clk26m>,<&clk26m>,<&clk26m>,<&clk26m>;clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck";status = "disabled";};};u3phy1: t-phy@11e30000 {compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";#address-cells = <1>;#size-cells = <1>;ranges = <0 0 0x11e30000 0xe00>;status = "disabled";u2port1: usb-phy@0 {reg = <0x0 0x700>;#phy-cells = <1>;};u3port1: usb-phy@700 {reg = <0x700 0x700>;#phy-cells = <1>;};};xhci1: xhci@11290000 {compatible = "mediatek,mt8195-xhci","mediatek,mtk-xhci";reg = <0 0x11290000 0 0x1000>,<0 0x11293e00 0 0x0100>;reg-names = "mac", "ippc";interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH>;phys = <&u2port1 PHY_TYPE_USB2>;clocks = <&clk26m>,<&clk26m>,<&clk26m>,<&clk26m>;clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck";status = "disabled";};u3phy2: t-phy@11c40000 {compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";#address-cells = <1>;#size-cells = <1>;ranges = <0 0 0x11c40000 0x700>;status = "disabled";u2port2: usb-phy@0 {reg = <0x0 0x700>;#phy-cells = <1>;};};xhci2: xhci@112a0000 {compatible = "mediatek,mt8195-xhci","mediatek,mtk-xhci";reg = <0 0x112a0000 0 0x1000>,<0 0x112a3e00 0 0x0100>;reg-names = "mac", "ippc";interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH>;phys = <&u2port2 PHY_TYPE_USB2>;clocks = <&clk26m>,<&clk26m>,<&clk26m>;clock-names = "sys_ck", "xhci_ck", "ref_ck";status = "disabled";};u3phy3: t-phy@11c50000 {compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v2";#address-cells = <1>;#size-cells = <1>;ranges = <0 0 0x11c50000 0x700>;status = "okay";u2port3: usb-phy@0 {reg = <0x0 0x700>;#phy-cells = <1>;};};xhci3: xhci@112b0000 {compatible = "mediatek,mt8195-xhci","mediatek,mtk-xhci";reg = <0 0x112b0000 0 0x1000>,<0 0x112b3e00 0 0x0100>;reg-names = "mac", "ippc";interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH>;phys = <&u2port3 PHY_TYPE_USB2>;clocks = <&clk26m>,<&clk26m>,<&clk26m>;clock-names = "sys_ck", "xhci_ck", "ref_ck";usb2-lpm-disable;status = "disabled";};- };
+}; diff --git a/arch/arm/mach-mediatek/Kconfig b/arch/arm/mach-mediatek/Kconfig index 04aa2fd97f..3a2af1cdee 100644 --- a/arch/arm/mach-mediatek/Kconfig +++ b/arch/arm/mach-mediatek/Kconfig @@ -67,6 +67,15 @@ config TARGET_MT8183 SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3 and LPDDR4 options.
+config TARGET_MT8195
- bool "MediaTek MT8195 SoC"
- select ARM64
- help
The MediaTek MT8195 is a ARM64-based SoC with a quad-core Cortex-A73 anda quad-core Cortex-A53. It is including UART, SPI, USB3.0 device and hosts,SD and MMC cards, UFS, PWM, I2C, I2S, S/PDIF, and several LPDDR3and LPDDR4 options.- config TARGET_MT8512 bool "MediaTek MT8512 M1 Board" select ARM64
@@ -105,6 +114,7 @@ config SYS_BOARD default "mt7981" if TARGET_MT7981 default "mt7986" if TARGET_MT7986 default "mt8183" if TARGET_MT8183
- default "mt8195" if TARGET_MT8195 default "mt8512" if TARGET_MT8512 default "mt8516" if TARGET_MT8516 default "mt8518" if TARGET_MT8518
@@ -122,6 +132,7 @@ config SYS_CONFIG_NAME default "mt7981" if TARGET_MT7981 default "mt7986" if TARGET_MT7986 default "mt8183" if TARGET_MT8183
- default "mt8195" if TARGET_MT8195 default "mt8512" if TARGET_MT8512 default "mt8516" if TARGET_MT8516 default "mt8518" if TARGET_MT8518
@@ -134,7 +145,7 @@ config SYS_CONFIG_NAME config MTK_BROM_HEADER_INFO string default "media=nor" if TARGET_MT8518 || TARGET_MT8512 || TARGET_MT7629 || TARGET_MT7622
- default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183
- default "media=emmc" if TARGET_MT8516 || TARGET_MT8365 || TARGET_MT8183 || TARGET_MT8195 default "media=snand;nandinfo=2k+64" if TARGET_MT7981 || TARGET_MT7986 default "lk=1" if TARGET_MT7623
diff --git a/arch/arm/mach-mediatek/Makefile b/arch/arm/mach-mediatek/Makefile index fc85293f71..fbbb5431d1 100644 --- a/arch/arm/mach-mediatek/Makefile +++ b/arch/arm/mach-mediatek/Makefile @@ -10,5 +10,6 @@ obj-$(CONFIG_TARGET_MT7629) += mt7629/ obj-$(CONFIG_TARGET_MT7981) += mt7981/ obj-$(CONFIG_TARGET_MT7986) += mt7986/ obj-$(CONFIG_TARGET_MT8183) += mt8183/ +obj-$(CONFIG_TARGET_MT8195) += mt8195/ obj-$(CONFIG_TARGET_MT8516) += mt8516/ obj-$(CONFIG_TARGET_MT8518) += mt8518/ diff --git a/arch/arm/mach-mediatek/mt8195/Kconfig b/arch/arm/mach-mediatek/mt8195/Kconfig new file mode 100644 index 0000000000..a34fa2cf2e --- /dev/null +++ b/arch/arm/mach-mediatek/mt8195/Kconfig @@ -0,0 +1,13 @@ +if TARGET_MT8195
+config SYS_BOARD
- default "mt8195"
+config SYS_CONFIG_NAME
- default "mt8195"
+config MTK_BROM_HEADER_INFO
- string
- default "media=emmc"
+endif diff --git a/arch/arm/mach-mediatek/mt8195/Makefile b/arch/arm/mach-mediatek/mt8195/Makefile new file mode 100644 index 0000000000..886ab7e4eb --- /dev/null +++ b/arch/arm/mach-mediatek/mt8195/Makefile @@ -0,0 +1,3 @@ +# SPDX-License-Identifier: GPL-2.0
+obj-y += init.o diff --git a/arch/arm/mach-mediatek/mt8195/init.c b/arch/arm/mach-mediatek/mt8195/init.c new file mode 100644 index 0000000000..8d6b700e7e --- /dev/null +++ b/arch/arm/mach-mediatek/mt8195/init.c @@ -0,0 +1,97 @@ +// SPDX-License-Identifier: GPL-2.0 +/*
- Copyright (C) 2023 MediaTek Inc.
- Copyright (C) 2023 BayLibre, SAS
- Author: Macpaul Lin macpaul.lin@mediatek.com
- Author: Fabien Parent fparent@baylibre.com
- */
+#include <clk.h> +#include <common.h> +#include <cpu_func.h> +#include <dm.h> +#include <fdtdec.h> +#include <ram.h> +#include <asm/arch/misc.h> +#include <asm/armv8/mmu.h> +#include <asm/sections.h> +#include <asm/system.h> +#include <dm/uclass.h>
+DECLARE_GLOBAL_DATA_PTR;
+int dram_init(void) +{
- int ret;
- ret = fdtdec_setup_memory_banksize();
- if (ret)
return ret;- fdtdec_setup_mem_size_base();
- /*
* Limit gd->ram_top not exceeding SZ_4G.* Because some periphals like mmc requires DMA buffer* allocaed below SZ_4G.** Note: SZ_2M is for adjusting gd->relocaddr,* the reserved memory for u-boot itself.*/- if (gd->ram_base + gd->ram_size >= SZ_4G)
gd->mon_len = SZ_4G + gd->ram_base + SZ_2M;- return 0;
+}
+int dram_init_banksize(void) +{
- gd->bd->bi_dram[0].start = gd->ram_base;
- gd->bd->bi_dram[0].size = gd->ram_size;
- return 0;
+}
+int mtk_pll_early_init(void) +{
- return 0;
+}
+int mtk_soc_early_init(void) +{
- return 0;
+}
+#if !IS_ENABLED(CONFIG_SYSRESET) +void reset_cpu(void) +{
- psci_system_reset();
+} +#endif
+int print_cpuinfo(void) +{
- printf("CPU: MediaTek MT8195\n");
- return 0;
+}
+static struct mm_region mt8195_mem_map[] = {
- {
/* DDR */.virt = 0x40000000UL,.phys = 0x40000000UL,.size = 0x200000000UL,.attrs = PTE_BLOCK_MEMTYPE(MT_NORMAL) | PTE_BLOCK_OUTER_SHARE,- }, {
.virt = 0x00000000UL,.phys = 0x00000000UL,.size = 0x20000000UL,.attrs = PTE_BLOCK_MEMTYPE(MT_DEVICE_NGNRNE) |PTE_BLOCK_NON_SHARE |PTE_BLOCK_PXN | PTE_BLOCK_UXN- }, {
0,- }
+};
+struct mm_region *mem_map = mt8195_mem_map;
participants (7)
-
Macpaul Lin -
Macpaul Lin -
Marcel Ziswiler -
Michael Walle -
Shengyu Qu -
Simon Glass -
Tom Rini