[U-Boot] [PATCH v3 0/3] spi-nor: spi-nor-ids: Fix 4 Byte addressing for n25q*
n25q variants do not support stateless 4 byte addressing opcodes by default, therefore first patch disables this flag for those parts. Second patch adds entries for mt25q variants which are similar to n25q but supports stateless 4 byte opcodes. Third patch adds USE_FSR flag for mt25q* and n25q* variants where missing
Changes since v2: Add USE_FSR flags to all flash variants where missing Collect T-bys and R-bys Reword commit msgs as necessary
Changes since v1: Rename newer variants as mt25* Add a patch to enable flag register parsing for mt25qu512a
Vignesh Raghavendra (3): spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256* spi-nor: spi-nor-ids: Add entries for mt25q variants spi-nor: spi-nor-ids: Add USE_FSR flag for mt25q* and n25q* entry
drivers/mtd/spi/spi-nor-ids.c | 14 +++++++++----- 1 file changed, 9 insertions(+), 5 deletions(-)
Per datasheets of n25q256* and n25q512* not all variants of n25q256* and n25q512* support 4 Byte stateless addressing opcodes. Therefore drop SPI_NOR_4B_OPCODES flag from these entries
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com Reviewed-by: Tudor Ambarus tudor.ambarus@microchip.com Reviewed-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com Tested-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com Tested-by: Eugeniy Paltsev Eugeniy.Paltsev@synopsys.com --- drivers/mtd/spi/spi-nor-ids.c | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index cdb620205866..28a47b2f4428 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -161,12 +161,12 @@ const struct flash_info spi_nor_ids[] = { { INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, - { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, - { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, - { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, - { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, + { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("mt25qu02g", 0x20bb22, 0, 64 * 1024, 4096, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
mt25q* flashes support stateless 4 byte addressing opcodes. Add entries for the same. These flashes have bit 6 set in 5th byte of READ ID response when compared to n25q* variants.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com Reviewed-by: Tudor Ambarus tudor.ambarus@microchip.com Tested-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com --- drivers/mtd/spi/spi-nor-ids.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 28a47b2f4428..28ffe9de0d72 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -161,11 +161,14 @@ const struct flash_info spi_nor_ids[] = { { INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, + { INFO6("mt25ql256a", 0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, + { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024, SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, + { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { INFO("n25q00", 0x20ba21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) }, { INFO("n25q00a", 0x20bb21, 0, 64 * 1024, 2048, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | NO_CHIP_ERASE) },
n25q* and mt25q* (both 256Mb and 512Mb) flashes support Flag status register that indicates various errors that may be encountered during erase/write operations. Therefore add USE_FSR flag wherever missing.
Signed-off-by: Vignesh Raghavendra vigneshr@ti.com Reviewed-by: Tudor Ambarus tudor.ambarus@microchip.com Reviewed-by: Simon Goldschmidt simon.k.r.goldschmidt@gmail.com --- drivers/mtd/spi/spi-nor-ids.c | 11 ++++++----- 1 file changed, 6 insertions(+), 5 deletions(-)
diff --git a/drivers/mtd/spi/spi-nor-ids.c b/drivers/mtd/spi/spi-nor-ids.c index 28ffe9de0d72..370739670cd4 100644 --- a/drivers/mtd/spi/spi-nor-ids.c +++ b/drivers/mtd/spi/spi-nor-ids.c @@ -161,12 +161,13 @@ const struct flash_info spi_nor_ids[] = { { INFO("n25q064a", 0x20bb17, 0, 64 * 1024, 128, SECT_4K | SPI_NOR_QUAD_READ) }, { INFO("n25q128a11", 0x20bb18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, { INFO("n25q128a13", 0x20ba18, 0, 64 * 1024, 256, SECT_4K | SPI_NOR_QUAD_READ) }, - { INFO6("mt25ql256a", 0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, - { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ) }, - { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, - { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ) }, + { INFO6("mt25ql256a", 0x20ba19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, + { INFO("n25q256a", 0x20ba19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | USE_FSR) }, + { INFO6("mt25qu256a", 0x20bb19, 0x104400, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | USE_FSR) }, + { INFO("n25q256ax1", 0x20bb19, 0, 64 * 1024, 512, SECT_4K | SPI_NOR_QUAD_READ | USE_FSR) }, { INFO6("mt25qu512a", 0x20bb20, 0x104400, 64 * 1024, 1024, - SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + SPI_NOR_DUAL_READ | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES | + USE_FSR) }, { INFO("n25q512a", 0x20bb20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) }, { INFO6("mt25ql512a", 0x20ba20, 0x104400, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, { INFO("n25q512ax3", 0x20ba20, 0, 64 * 1024, 1024, SECT_4K | USE_FSR | SPI_NOR_QUAD_READ) },
Hi Vignesh,
On Fri, Oct 11, 2019 at 1:28 PM Vignesh Raghavendra vigneshr@ti.com wrote:
n25q* and mt25q* (both 256Mb and 512Mb) flashes support Flag status register that indicates various errors that may be encountered during erase/write operations. Therefore add USE_FSR flag wherever missing.
Does 256Mb require FSR? I remember Micron die is created after 512Mb where it creates die between two 256Mb on 512Mb flash. Indeed die switching would require FSR.
Hi Jagan,
On 23/10/19 12:00 AM, Jagan Teki wrote:
Hi Vignesh,
On Fri, Oct 11, 2019 at 1:28 PM Vignesh Raghavendra vigneshr@ti.com wrote:
n25q* and mt25q* (both 256Mb and 512Mb) flashes support Flag status register that indicates various errors that may be encountered during erase/write operations. Therefore add USE_FSR flag wherever missing.
Does 256Mb require FSR? I remember Micron die is created after 512Mb where it creates die between two 256Mb on 512Mb flash. Indeed die switching would require FSR.
Flag Status Register(FSR) is not for switching die but for looking up and printing out reason for write/erase failure. And yes 256Mb part does support FSR. See datasheet at: https://www.micron.com/-/media/client/global/documents/products/data-sheet/n... Table 17: Flag Status Register Bit Definition
https://www.mouser.com/datasheet/2/671/MT25Q_QLJS_U_256_ABA_0-1387271.pdf Table 5: Flag Status Register
On Wed, Oct 23, 2019 at 10:49 AM Vignesh Raghavendra vigneshr@ti.com wrote:
Hi Jagan,
On 23/10/19 12:00 AM, Jagan Teki wrote:
Hi Vignesh,
On Fri, Oct 11, 2019 at 1:28 PM Vignesh Raghavendra vigneshr@ti.com wrote:
n25q* and mt25q* (both 256Mb and 512Mb) flashes support Flag status register that indicates various errors that may be encountered during erase/write operations. Therefore add USE_FSR flag wherever missing.
Does 256Mb require FSR? I remember Micron die is created after 512Mb where it creates die between two 256Mb on 512Mb flash. Indeed die switching would require FSR.
Flag Status Register(FSR) is not for switching die but for looking up and printing out reason for write/erase failure. And yes 256Mb part does support FSR. See datasheet at: https://www.micron.com/-/media/client/global/documents/products/data-sheet/n... Table 17: Flag Status Register Bit Definition
https://www.mouser.com/datasheet/2/671/MT25Q_QLJS_U_256_ABA_0-1387271.pdf Table 5: Flag Status Register
Yes, I have seen these. I remember it wasn't require FSR when I did a test on zynq qspi last time. may be it can't consistent between all IP's
On Fri, Oct 11, 2019 at 1:28 PM Vignesh Raghavendra vigneshr@ti.com wrote:
n25q variants do not support stateless 4 byte addressing opcodes by default, therefore first patch disables this flag for those parts. Second patch adds entries for mt25q variants which are similar to n25q but supports stateless 4 byte opcodes. Third patch adds USE_FSR flag for mt25q* and n25q* variants where missing
Changes since v2: Add USE_FSR flags to all flash variants where missing Collect T-bys and R-bys Reword commit msgs as necessary
Changes since v1: Rename newer variants as mt25* Add a patch to enable flag register parsing for mt25qu512a
Vignesh Raghavendra (3): spi-nor: spi-nor-ids: Disable SPI_NOR_4B_OPCODES for n25q512* and n25q256* spi-nor: spi-nor-ids: Add entries for mt25q variants spi-nor: spi-nor-ids: Add USE_FSR flag for mt25q* and n25q* entry
Applied to u-boot-spi/master
participants (2)
-
Jagan Teki -
Vignesh Raghavendra